VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 31807

Last change on this file since 31807 was 31807, checked in by vboxsync, 14 years ago

FT: disable large page usage
Removed debug code
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 173.5 KB
Line 
1/* $Id: PGMInternal.h 31807 2010-08-20 09:15:56Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm.h>
28#include <VBox/mm.h>
29#include <VBox/pdmcritsect.h>
30#include <VBox/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/gmm.h>
35#include <VBox/hwaccm.h>
36#include <VBox/hwacc_vmx.h>
37#include <include/internal/pgm.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 0 /* ! remember to disable before committing ! XXX TODO */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark Use with care as we don't have so much dynamic mapping space in
237 * ring-0 on 32-bit darwin and in RC.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243#else
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_GCPHYS_2_PTR_V2
249 * Maps a GC physical page address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM handle.
253 * @param pVCpu The current CPU.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark Use with care as we don't have so much dynamic mapping space in
258 * ring-0 on 32-bit darwin and in RC.
259 * @remark There is no need to assert on the result.
260 */
261#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
262# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264#else
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM handle.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark Use with care as we don't have so much dynamic mapping space in
278 * ring-0 on 32-bit darwin and in RC.
279 * @remark There is no need to assert on the result.
280 */
281#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVCpu The current CPU.
288 * @param GCPhys The GC physical address to map to a virtual one.
289 * @param ppv Where to store the virtual address. No need to cast this.
290 *
291 * @remark Use with care as we don't have so much dynamic mapping space in
292 * ring-0 on 32-bit darwin and in RC.
293 * @remark There is no need to assert on the result.
294 */
295#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_DYNMAP_UNUSED_HINT
318 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319 * is no longer used.
320 *
321 * For best effect only apply this to the page that was mapped most recently.
322 *
323 * @param pVCpu The current CPU.
324 * @param pPage The pool page.
325 */
326#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327# ifdef LOG_ENABLED
328# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329# else
330# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331# endif
332#else
333# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334#endif
335
336/** @def PGM_DYNMAP_UNUSED_HINT_VM
337 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338 * is no longer used.
339 *
340 * For best effect only apply this to the page that was mapped most recently.
341 *
342 * @param pVM The VM handle.
343 * @param pPage The pool page.
344 */
345#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348/** @def PGM_INVL_PG
349 * Invalidates a page.
350 *
351 * @param pVCpu The VMCPU handle.
352 * @param GCVirt The virtual address of the page to invalidate.
353 */
354#ifdef IN_RC
355# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356#elif defined(IN_RING0)
357# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_PG_ALL_VCPU
363 * Invalidates a page on all VCPUs
364 *
365 * @param pVM The VM handle.
366 * @param GCVirt The virtual address of the page to invalidate.
367 */
368#ifdef IN_RC
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370#elif defined(IN_RING0)
371# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372#else
373# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374#endif
375
376/** @def PGM_INVL_BIG_PG
377 * Invalidates a 4MB page directory entry.
378 *
379 * @param pVCpu The VMCPU handle.
380 * @param GCVirt The virtual address within the page directory to invalidate.
381 */
382#ifdef IN_RC
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384#elif defined(IN_RING0)
385# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386#else
387# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388#endif
389
390/** @def PGM_INVL_VCPU_TLBS()
391 * Invalidates the TLBs of the specified VCPU
392 *
393 * @param pVCpu The VMCPU handle.
394 */
395#ifdef IN_RC
396# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397#elif defined(IN_RING0)
398# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399#else
400# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401#endif
402
403/** @def PGM_INVL_ALL_VCPU_TLBS()
404 * Invalidates the TLBs of all VCPUs
405 *
406 * @param pVM The VM handle.
407 */
408#ifdef IN_RC
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410#elif defined(IN_RING0)
411# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412#else
413# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414#endif
415
416
417/** @name Safer Shadow PAE PT/PTE
418 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419 * present.
420 *
421 * @{
422 */
423#if 1
424/**
425 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
426 * invalid entries for present.
427 * @sa X86PTEPAE.
428 */
429typedef union PGMSHWPTEPAE
430{
431 /** Unsigned integer view */
432 X86PGPAEUINT uCareful;
433 /* Not other views. */
434} PGMSHWPTEPAE;
435
436# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
443# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
446# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
452
453/**
454 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
455 * invalid entries for present.
456 * @sa X86PTPAE.
457 */
458typedef struct PGMSHWPTPAE
459{
460 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461} PGMSHWPTPAE;
462
463#else
464typedef X86PTEPAE PGMSHWPTEPAE;
465typedef X86PTPAE PGMSHWPTPAE;
466# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
473# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
476# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
482
483#endif
484
485/** Pointer to a shadow PAE PTE. */
486typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487/** Pointer to a const shadow PAE PTE. */
488typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490/** Pointer to a shadow PAE page table. */
491typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492/** Pointer to a const shadow PAE page table. */
493typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494/** @} */
495
496
497/** Size of the GCPtrConflict array in PGMMAPPING.
498 * @remarks Must be a power of two. */
499#define PGMMAPPING_CONFLICT_MAX 8
500
501/**
502 * Structure for tracking GC Mappings.
503 *
504 * This structure is used by linked list in both GC and HC.
505 */
506typedef struct PGMMAPPING
507{
508 /** Pointer to next entry. */
509 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510 /** Pointer to next entry. */
511 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512 /** Pointer to next entry. */
513 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514 /** Indicate whether this entry is finalized. */
515 bool fFinalized;
516 /** Start Virtual address. */
517 RTGCPTR GCPtr;
518 /** Last Virtual address (inclusive). */
519 RTGCPTR GCPtrLast;
520 /** Range size (bytes). */
521 RTGCPTR cb;
522 /** Pointer to relocation callback function. */
523 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524 /** User argument to the callback. */
525 R3PTRTYPE(void *) pvUser;
526 /** Mapping description / name. For easing debugging. */
527 R3PTRTYPE(const char *) pszDesc;
528 /** Last 8 addresses that caused conflicts. */
529 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530 /** Number of conflicts for this hypervisor mapping. */
531 uint32_t cConflicts;
532 /** Number of page tables. */
533 uint32_t cPTs;
534
535 /** Array of page table mapping data. Each entry
536 * describes one page table. The array can be longer
537 * than the declared length.
538 */
539 struct
540 {
541 /** The HC physical address of the page table. */
542 RTHCPHYS HCPhysPT;
543 /** The HC physical address of the first PAE page table. */
544 RTHCPHYS HCPhysPaePT0;
545 /** The HC physical address of the second PAE page table. */
546 RTHCPHYS HCPhysPaePT1;
547 /** The HC virtual address of the 32-bit page table. */
548 R3PTRTYPE(PX86PT) pPTR3;
549 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551 /** The RC virtual address of the 32-bit page table. */
552 RCPTRTYPE(PX86PT) pPTRC;
553 /** The RC virtual address of the two PAE page table. */
554 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555 /** The R0 virtual address of the 32-bit page table. */
556 R0PTRTYPE(PX86PT) pPTR0;
557 /** The R0 virtual address of the two PAE page table. */
558 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559 } aPTs[1];
560} PGMMAPPING;
561/** Pointer to structure for tracking GC Mappings. */
562typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565/**
566 * Physical page access handler structure.
567 *
568 * This is used to keep track of physical address ranges
569 * which are being monitored in some kind of way.
570 */
571typedef struct PGMPHYSHANDLER
572{
573 AVLROGCPHYSNODECORE Core;
574 /** Access type. */
575 PGMPHYSHANDLERTYPE enmType;
576 /** Number of pages to update. */
577 uint32_t cPages;
578 /** Pointer to R3 callback function. */
579 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
580 /** User argument for R3 handlers. */
581 R3PTRTYPE(void *) pvUserR3;
582 /** Pointer to R0 callback function. */
583 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
584 /** User argument for R0 handlers. */
585 R0PTRTYPE(void *) pvUserR0;
586 /** Pointer to RC callback function. */
587 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
588 /** User argument for RC handlers. */
589 RCPTRTYPE(void *) pvUserRC;
590 /** Description / Name. For easing debugging. */
591 R3PTRTYPE(const char *) pszDesc;
592#ifdef VBOX_WITH_STATISTICS
593 /** Profiling of this handler. */
594 STAMPROFILE Stat;
595#endif
596} PGMPHYSHANDLER;
597/** Pointer to a physical page access handler structure. */
598typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
599
600
601/**
602 * Cache node for the physical addresses covered by a virtual handler.
603 */
604typedef struct PGMPHYS2VIRTHANDLER
605{
606 /** Core node for the tree based on physical ranges. */
607 AVLROGCPHYSNODECORE Core;
608 /** Offset from this struct to the PGMVIRTHANDLER structure. */
609 int32_t offVirtHandler;
610 /** Offset of the next alias relative to this one.
611 * Bit 0 is used for indicating whether we're in the tree.
612 * Bit 1 is used for indicating that we're the head node.
613 */
614 int32_t offNextAlias;
615} PGMPHYS2VIRTHANDLER;
616/** Pointer to a phys to virtual handler structure. */
617typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
618
619/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
620 * node is in the tree. */
621#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
622/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
623 * node is in the head of an alias chain.
624 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
625#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
626/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
627#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
628
629
630/**
631 * Virtual page access handler structure.
632 *
633 * This is used to keep track of virtual address ranges
634 * which are being monitored in some kind of way.
635 */
636typedef struct PGMVIRTHANDLER
637{
638 /** Core node for the tree based on virtual ranges. */
639 AVLROGCPTRNODECORE Core;
640 /** Size of the range (in bytes). */
641 RTGCPTR cb;
642 /** Number of cache pages. */
643 uint32_t cPages;
644 /** Access type. */
645 PGMVIRTHANDLERTYPE enmType;
646 /** Pointer to the RC callback function. */
647 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
648#if HC_ARCH_BITS == 64
649 RTRCPTR padding;
650#endif
651 /** Pointer to the R3 callback function for invalidation. */
652 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
653 /** Pointer to the R3 callback function. */
654 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
655 /** Description / Name. For easing debugging. */
656 R3PTRTYPE(const char *) pszDesc;
657#ifdef VBOX_WITH_STATISTICS
658 /** Profiling of this handler. */
659 STAMPROFILE Stat;
660#endif
661 /** Array of cached physical addresses for the monitored ranged. */
662 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
663} PGMVIRTHANDLER;
664/** Pointer to a virtual page access handler structure. */
665typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
666
667
668/**
669 * Page type.
670 *
671 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
672 * @remarks This is used in the saved state, so changes to it requires bumping
673 * the saved state version.
674 * @todo So, convert to \#defines!
675 */
676typedef enum PGMPAGETYPE
677{
678 /** The usual invalid zero entry. */
679 PGMPAGETYPE_INVALID = 0,
680 /** RAM page. (RWX) */
681 PGMPAGETYPE_RAM,
682 /** MMIO2 page. (RWX) */
683 PGMPAGETYPE_MMIO2,
684 /** MMIO2 page aliased over an MMIO page. (RWX)
685 * See PGMHandlerPhysicalPageAlias(). */
686 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
687 /** Shadowed ROM. (RWX) */
688 PGMPAGETYPE_ROM_SHADOW,
689 /** ROM page. (R-X) */
690 PGMPAGETYPE_ROM,
691 /** MMIO page. (---) */
692 PGMPAGETYPE_MMIO,
693 /** End of valid entries. */
694 PGMPAGETYPE_END
695} PGMPAGETYPE;
696AssertCompile(PGMPAGETYPE_END <= 7);
697
698/** @name Page type predicates.
699 * @{ */
700#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
701#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
702#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
703#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
704#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
705/** @} */
706
707
708/**
709 * A Physical Guest Page tracking structure.
710 *
711 * The format of this structure is complicated because we have to fit a lot
712 * of information into as few bits as possible. The format is also subject
713 * to change (there is one comming up soon). Which means that for we'll be
714 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
715 * accesses to the structure.
716 */
717typedef struct PGMPAGE
718{
719 /** The physical address and the Page ID. */
720 RTHCPHYS HCPhysAndPageID;
721 /** Combination of:
722 * - [0-7]: u2HandlerPhysStateY - the physical handler state
723 * (PGM_PAGE_HNDL_PHYS_STATE_*).
724 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
725 * (PGM_PAGE_HNDL_VIRT_STATE_*).
726 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
727 * - [15]: fWrittenToY - flag indicating that a write monitored page was
728 * written to when set.
729 * - [10-13]: 4 unused bits.
730 * @remarks Warning! All accesses to the bits are hardcoded.
731 *
732 * @todo Change this to a union with both bitfields, u8 and u accessors.
733 * That'll help deal with some of the hardcoded accesses.
734 *
735 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
736 * will make it possible to turn some of the 16-bit accesses into
737 * 32-bit ones, which may be efficient (stalls).
738 */
739 RTUINT16U u16MiscY;
740 /** The page state.
741 * Only 3 bits are really needed for this. */
742 uint16_t uStateY : 3;
743 /** The page type (PGMPAGETYPE).
744 * Only 3 bits are really needed for this. */
745 uint16_t uTypeY : 3;
746 /** PTE index for usage tracking (page pool). */
747 uint16_t uPteIdx : 10;
748 /** Usage tracking (page pool). */
749 uint16_t u16TrackingY;
750 /** The number of read locks on this page. */
751 uint8_t cReadLocksY;
752 /** The number of write locks on this page. */
753 uint8_t cWriteLocksY;
754} PGMPAGE;
755AssertCompileSize(PGMPAGE, 16);
756/** Pointer to a physical guest page. */
757typedef PGMPAGE *PPGMPAGE;
758/** Pointer to a const physical guest page. */
759typedef const PGMPAGE *PCPGMPAGE;
760/** Pointer to a physical guest page pointer. */
761typedef PPGMPAGE *PPPGMPAGE;
762
763
764/**
765 * Clears the page structure.
766 * @param pPage Pointer to the physical guest page tracking structure.
767 */
768#define PGM_PAGE_CLEAR(pPage) \
769 do { \
770 (pPage)->HCPhysAndPageID = 0; \
771 (pPage)->uStateY = 0; \
772 (pPage)->uTypeY = 0; \
773 (pPage)->uPteIdx = 0; \
774 (pPage)->u16MiscY.u = 0; \
775 (pPage)->u16TrackingY = 0; \
776 (pPage)->cReadLocksY = 0; \
777 (pPage)->cWriteLocksY = 0; \
778 } while (0)
779
780/**
781 * Initializes the page structure.
782 * @param pPage Pointer to the physical guest page tracking structure.
783 */
784#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
785 do { \
786 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
787 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
788 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
789 (pPage)->uStateY = (_uState); \
790 (pPage)->uTypeY = (_uType); \
791 (pPage)->uPteIdx = 0; \
792 (pPage)->u16MiscY.u = 0; \
793 (pPage)->u16TrackingY = 0; \
794 (pPage)->cReadLocksY = 0; \
795 (pPage)->cWriteLocksY = 0; \
796 } while (0)
797
798/**
799 * Initializes the page structure of a ZERO page.
800 * @param pPage Pointer to the physical guest page tracking structure.
801 * @param pVM The VM handle (for getting the zero page address).
802 * @param uType The page type (PGMPAGETYPE).
803 */
804#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
805 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
806
807
808/** @name The Page state, PGMPAGE::uStateY.
809 * @{ */
810/** The zero page.
811 * This is a per-VM page that's never ever mapped writable. */
812#define PGM_PAGE_STATE_ZERO 0
813/** A allocated page.
814 * This is a per-VM page allocated from the page pool (or wherever
815 * we get MMIO2 pages from if the type is MMIO2).
816 */
817#define PGM_PAGE_STATE_ALLOCATED 1
818/** A allocated page that's being monitored for writes.
819 * The shadow page table mappings are read-only. When a write occurs, the
820 * fWrittenTo member is set, the page remapped as read-write and the state
821 * moved back to allocated. */
822#define PGM_PAGE_STATE_WRITE_MONITORED 2
823/** The page is shared, aka. copy-on-write.
824 * This is a page that's shared with other VMs. */
825#define PGM_PAGE_STATE_SHARED 3
826/** The page is ballooned, so no longer available for this VM. */
827#define PGM_PAGE_STATE_BALLOONED 4
828/** @} */
829
830
831/**
832 * Gets the page state.
833 * @returns page state (PGM_PAGE_STATE_*).
834 * @param pPage Pointer to the physical guest page tracking structure.
835 */
836#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
837
838/**
839 * Sets the page state.
840 * @param pPage Pointer to the physical guest page tracking structure.
841 * @param _uState The new page state.
842 */
843#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
844
845
846/**
847 * Gets the host physical address of the guest page.
848 * @returns host physical address (RTHCPHYS).
849 * @param pPage Pointer to the physical guest page tracking structure.
850 */
851#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
852
853/**
854 * Sets the host physical address of the guest page.
855 * @param pPage Pointer to the physical guest page tracking structure.
856 * @param _HCPhys The new host physical address.
857 */
858#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
859 do { \
860 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
861 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
862 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
863 | (SetHCPhysTmp << (28-12)); \
864 } while (0)
865
866/**
867 * Get the Page ID.
868 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
869 * @param pPage Pointer to the physical guest page tracking structure.
870 */
871#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
872
873/**
874 * Sets the Page ID.
875 * @param pPage Pointer to the physical guest page tracking structure.
876 */
877#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
878 do { \
879 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
880 | ((_idPage) & UINT32_C(0x0fffffff)); \
881 } while (0)
882
883/**
884 * Get the Chunk ID.
885 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
886 * @param pPage Pointer to the physical guest page tracking structure.
887 */
888#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
889
890/**
891 * Get the index of the page within the allocation chunk.
892 * @returns The page index.
893 * @param pPage Pointer to the physical guest page tracking structure.
894 */
895#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
896
897/**
898 * Gets the page type.
899 * @returns The page type.
900 * @param pPage Pointer to the physical guest page tracking structure.
901 */
902#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
903
904/**
905 * Sets the page type.
906 * @param pPage Pointer to the physical guest page tracking structure.
907 * @param _enmType The new page type (PGMPAGETYPE).
908 */
909#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
910
911/**
912 * Gets the page table index
913 * @returns The page table index.
914 * @param pPage Pointer to the physical guest page tracking structure.
915 */
916#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
917
918/**
919 * Sets the page table index
920 * @param pPage Pointer to the physical guest page tracking structure.
921 * @param iPte New page table index.
922 */
923#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
924
925/**
926 * Checks if the page is marked for MMIO.
927 * @returns true/false.
928 * @param pPage Pointer to the physical guest page tracking structure.
929 */
930#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
931
932/**
933 * Checks if the page is backed by the ZERO page.
934 * @returns true/false.
935 * @param pPage Pointer to the physical guest page tracking structure.
936 */
937#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
938
939/**
940 * Checks if the page is backed by a SHARED page.
941 * @returns true/false.
942 * @param pPage Pointer to the physical guest page tracking structure.
943 */
944#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
945
946/**
947 * Checks if the page is ballooned.
948 * @returns true/false.
949 * @param pPage Pointer to the physical guest page tracking structure.
950 */
951#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
952
953/**
954 * Marks the page as written to (for GMM change monitoring).
955 * @param pPage Pointer to the physical guest page tracking structure.
956 */
957#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
958
959/**
960 * Clears the written-to indicator.
961 * @param pPage Pointer to the physical guest page tracking structure.
962 */
963#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
964
965/**
966 * Checks if the page was marked as written-to.
967 * @returns true/false.
968 * @param pPage Pointer to the physical guest page tracking structure.
969 */
970#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
971
972/** @name PT usage values (PGMPAGE::u2PDEType).
973 *
974 * @{ */
975/** Either as a PT or PDE. */
976#define PGM_PAGE_PDE_TYPE_DONTCARE 0
977/** Must use a page table to map the range. */
978#define PGM_PAGE_PDE_TYPE_PT 1
979/** Can use a page directory entry to map the continous range. */
980#define PGM_PAGE_PDE_TYPE_PDE 2
981/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
982#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
983/** @} */
984
985/**
986 * Set the PDE type of the page
987 * @param pPage Pointer to the physical guest page tracking structure.
988 * @param uType PGM_PAGE_PDE_TYPE_*
989 */
990#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
991 do { \
992 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
993 | (((uType) & UINT8_C(0x03)) << 5); \
994 } while (0)
995
996/**
997 * Checks if the page was marked being part of a large page
998 * @returns true/false.
999 * @param pPage Pointer to the physical guest page tracking structure.
1000 */
1001#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
1002
1003/** Enabled optimized access handler tests.
1004 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
1005 * layout. When enabled, the compiler should normally generate more compact
1006 * code.
1007 */
1008#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1009
1010/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1011 *
1012 * @remarks The values are assigned in order of priority, so we can calculate
1013 * the correct state for a page with different handlers installed.
1014 * @{ */
1015/** No handler installed. */
1016#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1017/** Monitoring is temporarily disabled. */
1018#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1019/** Write access is monitored. */
1020#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1021/** All access is monitored. */
1022#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1023/** @} */
1024
1025/**
1026 * Gets the physical access handler state of a page.
1027 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1028 * @param pPage Pointer to the physical guest page tracking structure.
1029 */
1030#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
1031 ( (pPage)->u16MiscY.au8[0] )
1032
1033/**
1034 * Sets the physical access handler state of a page.
1035 * @param pPage Pointer to the physical guest page tracking structure.
1036 * @param _uState The new state value.
1037 */
1038#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
1039 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
1040
1041/**
1042 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
1043 * @returns true/false
1044 * @param pPage Pointer to the physical guest page tracking structure.
1045 */
1046#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
1047 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1048
1049/**
1050 * Checks if the page has any active physical access handlers.
1051 * @returns true/false
1052 * @param pPage Pointer to the physical guest page tracking structure.
1053 */
1054#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
1055 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1056
1057
1058/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1059 *
1060 * @remarks The values are assigned in order of priority, so we can calculate
1061 * the correct state for a page with different handlers installed.
1062 * @{ */
1063/** No handler installed. */
1064#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1065/* 1 is reserved so the lineup is identical with the physical ones. */
1066/** Write access is monitored. */
1067#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1068/** All access is monitored. */
1069#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1070/** @} */
1071
1072/**
1073 * Gets the virtual access handler state of a page.
1074 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1075 * @param pPage Pointer to the physical guest page tracking structure.
1076 */
1077#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
1078
1079/**
1080 * Sets the virtual access handler state of a page.
1081 * @param pPage Pointer to the physical guest page tracking structure.
1082 * @param _uState The new state value.
1083 */
1084#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1085 do { \
1086 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1087 | ((_uState) & UINT8_C(0x03)); \
1088 } while (0)
1089
1090/**
1091 * Checks if the page has any virtual access handlers.
1092 * @returns true/false
1093 * @param pPage Pointer to the physical guest page tracking structure.
1094 */
1095#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1096 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1097
1098/**
1099 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1100 * virtual handlers.
1101 * @returns true/false
1102 * @param pPage Pointer to the physical guest page tracking structure.
1103 */
1104#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1105 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1106
1107
1108/**
1109 * Checks if the page has any access handlers, including temporarily disabled ones.
1110 * @returns true/false
1111 * @param pPage Pointer to the physical guest page tracking structure.
1112 */
1113#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1114# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1115 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1116#else
1117# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1118 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1119 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1120#endif
1121
1122/**
1123 * Checks if the page has any active access handlers.
1124 * @returns true/false
1125 * @param pPage Pointer to the physical guest page tracking structure.
1126 */
1127#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1128# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1129 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1130#else
1131# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1132 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1133 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1134#endif
1135
1136/**
1137 * Checks if the page has any active access handlers catching all accesses.
1138 * @returns true/false
1139 * @param pPage Pointer to the physical guest page tracking structure.
1140 */
1141#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1142# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1143 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1144 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1145#else
1146# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1147 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1148 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1149#endif
1150
1151
1152/** @def PGM_PAGE_GET_TRACKING
1153 * Gets the packed shadow page pool tracking data associated with a guest page.
1154 * @returns uint16_t containing the data.
1155 * @param pPage Pointer to the physical guest page tracking structure.
1156 */
1157#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1158
1159/** @def PGM_PAGE_SET_TRACKING
1160 * Sets the packed shadow page pool tracking data associated with a guest page.
1161 * @param pPage Pointer to the physical guest page tracking structure.
1162 * @param u16TrackingData The tracking data to store.
1163 */
1164#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1165 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1166
1167/** @def PGM_PAGE_GET_TD_CREFS
1168 * Gets the @a cRefs tracking data member.
1169 * @returns cRefs.
1170 * @param pPage Pointer to the physical guest page tracking structure.
1171 */
1172#define PGM_PAGE_GET_TD_CREFS(pPage) \
1173 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1174
1175/** @def PGM_PAGE_GET_TD_IDX
1176 * Gets the @a idx tracking data member.
1177 * @returns idx.
1178 * @param pPage Pointer to the physical guest page tracking structure.
1179 */
1180#define PGM_PAGE_GET_TD_IDX(pPage) \
1181 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1182
1183
1184/** Max number of locks on a page. */
1185#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1186
1187/** Get the read lock count.
1188 * @returns count.
1189 * @param pPage Pointer to the physical guest page tracking structure.
1190 */
1191#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1192
1193/** Get the write lock count.
1194 * @returns count.
1195 * @param pPage Pointer to the physical guest page tracking structure.
1196 */
1197#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1198
1199/** Decrement the read lock counter.
1200 * @param pPage Pointer to the physical guest page tracking structure.
1201 */
1202#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1203
1204/** Decrement the write lock counter.
1205 * @param pPage Pointer to the physical guest page tracking structure.
1206 */
1207#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1208
1209/** Increment the read lock counter.
1210 * @param pPage Pointer to the physical guest page tracking structure.
1211 */
1212#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1213
1214/** Increment the write lock counter.
1215 * @param pPage Pointer to the physical guest page tracking structure.
1216 */
1217#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1218
1219
1220#if 0
1221/** Enables sanity checking of write monitoring using CRC-32. */
1222# define PGMLIVESAVERAMPAGE_WITH_CRC32
1223#endif
1224
1225/**
1226 * Per page live save tracking data.
1227 */
1228typedef struct PGMLIVESAVERAMPAGE
1229{
1230 /** Number of times it has been dirtied. */
1231 uint32_t cDirtied : 24;
1232 /** Whether it is currently dirty. */
1233 uint32_t fDirty : 1;
1234 /** Ignore the page.
1235 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1236 * deal with these after pausing the VM and DevPCI have said it bit about
1237 * remappings. */
1238 uint32_t fIgnore : 1;
1239 /** Was a ZERO page last time around. */
1240 uint32_t fZero : 1;
1241 /** Was a SHARED page last time around. */
1242 uint32_t fShared : 1;
1243 /** Whether the page is/was write monitored in a previous pass. */
1244 uint32_t fWriteMonitored : 1;
1245 /** Whether the page is/was write monitored earlier in this pass. */
1246 uint32_t fWriteMonitoredJustNow : 1;
1247 /** Bits reserved for future use. */
1248 uint32_t u2Reserved : 2;
1249#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1250 /** CRC-32 for the page. This is for internal consistency checks. */
1251 uint32_t u32Crc;
1252#endif
1253} PGMLIVESAVERAMPAGE;
1254#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1255AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1256#else
1257AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1258#endif
1259/** Pointer to the per page live save tracking data. */
1260typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1261
1262/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1263#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1264
1265
1266/**
1267 * Ram range for GC Phys to HC Phys conversion.
1268 *
1269 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1270 * conversions too, but we'll let MM handle that for now.
1271 *
1272 * This structure is used by linked lists in both GC and HC.
1273 */
1274typedef struct PGMRAMRANGE
1275{
1276 /** Start of the range. Page aligned. */
1277 RTGCPHYS GCPhys;
1278 /** Size of the range. (Page aligned of course). */
1279 RTGCPHYS cb;
1280 /** Pointer to the next RAM range - for R3. */
1281 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1282 /** Pointer to the next RAM range - for R0. */
1283 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1284 /** Pointer to the next RAM range - for RC. */
1285 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1286 /** PGM_RAM_RANGE_FLAGS_* flags. */
1287 uint32_t fFlags;
1288 /** Last address in the range (inclusive). Page aligned (-1). */
1289 RTGCPHYS GCPhysLast;
1290 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1291 R3PTRTYPE(void *) pvR3;
1292 /** Live save per page tracking data. */
1293 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1294 /** The range description. */
1295 R3PTRTYPE(const char *) pszDesc;
1296 /** Pointer to self - R0 pointer. */
1297 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1298 /** Pointer to self - RC pointer. */
1299 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1300 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1301 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1302 /** Array of physical guest page tracking structures. */
1303 PGMPAGE aPages[1];
1304} PGMRAMRANGE;
1305/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1306typedef PGMRAMRANGE *PPGMRAMRANGE;
1307
1308/** @name PGMRAMRANGE::fFlags
1309 * @{ */
1310/** The RAM range is floating around as an independent guest mapping. */
1311#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1312/** Ad hoc RAM range for an ROM mapping. */
1313#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1314/** Ad hoc RAM range for an MMIO mapping. */
1315#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1316/** Ad hoc RAM range for an MMIO2 mapping. */
1317#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1318/** @} */
1319
1320/** Tests if a RAM range is an ad hoc one or not.
1321 * @returns true/false.
1322 * @param pRam The RAM range.
1323 */
1324#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1325 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1326
1327
1328/**
1329 * Per page tracking structure for ROM image.
1330 *
1331 * A ROM image may have a shadow page, in which case we may have two pages
1332 * backing it. This structure contains the PGMPAGE for both while
1333 * PGMRAMRANGE have a copy of the active one. It is important that these
1334 * aren't out of sync in any regard other than page pool tracking data.
1335 */
1336typedef struct PGMROMPAGE
1337{
1338 /** The page structure for the virgin ROM page. */
1339 PGMPAGE Virgin;
1340 /** The page structure for the shadow RAM page. */
1341 PGMPAGE Shadow;
1342 /** The current protection setting. */
1343 PGMROMPROT enmProt;
1344 /** Live save status information. Makes use of unused alignment space. */
1345 struct
1346 {
1347 /** The previous protection value. */
1348 uint8_t u8Prot;
1349 /** Written to flag set by the handler. */
1350 bool fWrittenTo;
1351 /** Whether the shadow page is dirty or not. */
1352 bool fDirty;
1353 /** Whether it was dirtied in the recently. */
1354 bool fDirtiedRecently;
1355 } LiveSave;
1356} PGMROMPAGE;
1357AssertCompileSizeAlignment(PGMROMPAGE, 8);
1358/** Pointer to a ROM page tracking structure. */
1359typedef PGMROMPAGE *PPGMROMPAGE;
1360
1361
1362/**
1363 * A registered ROM image.
1364 *
1365 * This is needed to keep track of ROM image since they generally intrude
1366 * into a PGMRAMRANGE. It also keeps track of additional info like the
1367 * two page sets (read-only virgin and read-write shadow), the current
1368 * state of each page.
1369 *
1370 * Because access handlers cannot easily be executed in a different
1371 * context, the ROM ranges needs to be accessible and in all contexts.
1372 */
1373typedef struct PGMROMRANGE
1374{
1375 /** Pointer to the next range - R3. */
1376 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1377 /** Pointer to the next range - R0. */
1378 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1379 /** Pointer to the next range - RC. */
1380 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1381 /** Pointer alignment */
1382 RTRCPTR RCPtrAlignment;
1383 /** Address of the range. */
1384 RTGCPHYS GCPhys;
1385 /** Address of the last byte in the range. */
1386 RTGCPHYS GCPhysLast;
1387 /** Size of the range. */
1388 RTGCPHYS cb;
1389 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1390 uint32_t fFlags;
1391 /** The saved state range ID. */
1392 uint8_t idSavedState;
1393 /** Alignment padding. */
1394 uint8_t au8Alignment[3];
1395 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1396 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1397 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1398 * This is used for strictness checks. */
1399 R3PTRTYPE(const void *) pvOriginal;
1400 /** The ROM description. */
1401 R3PTRTYPE(const char *) pszDesc;
1402 /** The per page tracking structures. */
1403 PGMROMPAGE aPages[1];
1404} PGMROMRANGE;
1405/** Pointer to a ROM range. */
1406typedef PGMROMRANGE *PPGMROMRANGE;
1407
1408
1409/**
1410 * Live save per page data for an MMIO2 page.
1411 *
1412 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1413 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1414 * CRC-32 for detecting changes as well as special handling of zero pages. This
1415 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1416 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1417 * because of speed (2.5x and 6x slower).)
1418 *
1419 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1420 * save but normally is disabled. Since we can write monitore guest
1421 * accesses on our own, we only need this for host accesses. Shouldn't be
1422 * too difficult for DevVGA, VMMDev might be doable, the planned
1423 * networking fun will be fun since it involves ring-0.
1424 */
1425typedef struct PGMLIVESAVEMMIO2PAGE
1426{
1427 /** Set if the page is considered dirty. */
1428 bool fDirty;
1429 /** The number of scans this page has remained unchanged for.
1430 * Only updated for dirty pages. */
1431 uint8_t cUnchangedScans;
1432 /** Whether this page was zero at the last scan. */
1433 bool fZero;
1434 /** Alignment padding. */
1435 bool fReserved;
1436 /** CRC-32 for the first half of the page.
1437 * This is used together with u32CrcH2 to quickly detect changes in the page
1438 * during the non-final passes. */
1439 uint32_t u32CrcH1;
1440 /** CRC-32 for the second half of the page. */
1441 uint32_t u32CrcH2;
1442 /** SHA-1 for the saved page.
1443 * This is used in the final pass to skip pages without changes. */
1444 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1445} PGMLIVESAVEMMIO2PAGE;
1446/** Pointer to a live save status data for an MMIO2 page. */
1447typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1448
1449/**
1450 * A registered MMIO2 (= Device RAM) range.
1451 *
1452 * There are a few reason why we need to keep track of these
1453 * registrations. One of them is the deregistration & cleanup stuff,
1454 * while another is that the PGMRAMRANGE associated with such a region may
1455 * have to be removed from the ram range list.
1456 *
1457 * Overlapping with a RAM range has to be 100% or none at all. The pages
1458 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1459 * will be raised if a partial overlap or an overlap of ROM pages is
1460 * encountered. On an overlap we will free all the existing RAM pages and
1461 * put in the ram range pages instead.
1462 */
1463typedef struct PGMMMIO2RANGE
1464{
1465 /** The owner of the range. (a device) */
1466 PPDMDEVINSR3 pDevInsR3;
1467 /** Pointer to the ring-3 mapping of the allocation. */
1468 RTR3PTR pvR3;
1469 /** Pointer to the next range - R3. */
1470 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1471 /** Whether it's mapped or not. */
1472 bool fMapped;
1473 /** Whether it's overlapping or not. */
1474 bool fOverlapping;
1475 /** The PCI region number.
1476 * @remarks This ASSUMES that nobody will ever really need to have multiple
1477 * PCI devices with matching MMIO region numbers on a single device. */
1478 uint8_t iRegion;
1479 /** The saved state range ID. */
1480 uint8_t idSavedState;
1481 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1482 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1483 /** Live save per page tracking data. */
1484 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1485 /** The associated RAM range. */
1486 PGMRAMRANGE RamRange;
1487} PGMMMIO2RANGE;
1488/** Pointer to a MMIO2 range. */
1489typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1490
1491
1492
1493
1494/**
1495 * PGMPhysRead/Write cache entry
1496 */
1497typedef struct PGMPHYSCACHEENTRY
1498{
1499 /** R3 pointer to physical page. */
1500 R3PTRTYPE(uint8_t *) pbR3;
1501 /** GC Physical address for cache entry */
1502 RTGCPHYS GCPhys;
1503#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1504 RTGCPHYS u32Padding0; /**< alignment padding. */
1505#endif
1506} PGMPHYSCACHEENTRY;
1507
1508/**
1509 * PGMPhysRead/Write cache to reduce REM memory access overhead
1510 */
1511typedef struct PGMPHYSCACHE
1512{
1513 /** Bitmap of valid cache entries */
1514 uint64_t aEntries;
1515 /** Cache entries */
1516 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1517} PGMPHYSCACHE;
1518
1519
1520/** Pointer to an allocation chunk ring-3 mapping. */
1521typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1522/** Pointer to an allocation chunk ring-3 mapping pointer. */
1523typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1524
1525/**
1526 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1527 *
1528 * The primary tree (Core) uses the chunk id as key.
1529 */
1530typedef struct PGMCHUNKR3MAP
1531{
1532 /** The key is the chunk id. */
1533 AVLU32NODECORE Core;
1534 /** The current age thingy. */
1535 uint32_t iAge;
1536 /** The current reference count. */
1537 uint32_t volatile cRefs;
1538 /** The current permanent reference count. */
1539 uint32_t volatile cPermRefs;
1540 /** The mapping address. */
1541 void *pv;
1542} PGMCHUNKR3MAP;
1543
1544/**
1545 * Allocation chunk ring-3 mapping TLB entry.
1546 */
1547typedef struct PGMCHUNKR3MAPTLBE
1548{
1549 /** The chunk id. */
1550 uint32_t volatile idChunk;
1551#if HC_ARCH_BITS == 64
1552 uint32_t u32Padding; /**< alignment padding. */
1553#endif
1554 /** The chunk map. */
1555#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1556 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1557#else
1558 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1559#endif
1560} PGMCHUNKR3MAPTLBE;
1561/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1562typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1563
1564/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1565 * @remark Must be a power of two value. */
1566#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1567
1568/**
1569 * Allocation chunk ring-3 mapping TLB.
1570 *
1571 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1572 * At first glance this might look kinda odd since AVL trees are
1573 * supposed to give the most optimial lookup times of all trees
1574 * due to their balancing. However, take a tree with 1023 nodes
1575 * in it, that's 10 levels, meaning that most searches has to go
1576 * down 9 levels before they find what they want. This isn't fast
1577 * compared to a TLB hit. There is the factor of cache misses,
1578 * and of course the problem with trees and branch prediction.
1579 * This is why we use TLBs in front of most of the trees.
1580 *
1581 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1582 * difficult when we switch to the new inlined AVL trees (from kStuff).
1583 */
1584typedef struct PGMCHUNKR3MAPTLB
1585{
1586 /** The TLB entries. */
1587 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1588} PGMCHUNKR3MAPTLB;
1589
1590/**
1591 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1592 * @returns Chunk TLB index.
1593 * @param idChunk The Chunk ID.
1594 */
1595#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1596
1597
1598/**
1599 * Ring-3 guest page mapping TLB entry.
1600 * @remarks used in ring-0 as well at the moment.
1601 */
1602typedef struct PGMPAGER3MAPTLBE
1603{
1604 /** Address of the page. */
1605 RTGCPHYS volatile GCPhys;
1606 /** The guest page. */
1607#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1608 R3PTRTYPE(PPGMPAGE) volatile pPage;
1609#else
1610 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1611#endif
1612 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1613#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1614 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1615#else
1616 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1617#endif
1618 /** The address */
1619#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1620 R3PTRTYPE(void *) volatile pv;
1621#else
1622 R3R0PTRTYPE(void *) volatile pv;
1623#endif
1624#if HC_ARCH_BITS == 32
1625 uint32_t u32Padding; /**< alignment padding. */
1626#endif
1627} PGMPAGER3MAPTLBE;
1628/** Pointer to an entry in the HC physical TLB. */
1629typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1630
1631
1632/** The number of entries in the ring-3 guest page mapping TLB.
1633 * @remarks The value must be a power of two. */
1634#define PGM_PAGER3MAPTLB_ENTRIES 256
1635
1636/**
1637 * Ring-3 guest page mapping TLB.
1638 * @remarks used in ring-0 as well at the moment.
1639 */
1640typedef struct PGMPAGER3MAPTLB
1641{
1642 /** The TLB entries. */
1643 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1644} PGMPAGER3MAPTLB;
1645/** Pointer to the ring-3 guest page mapping TLB. */
1646typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1647
1648/**
1649 * Calculates the index of the TLB entry for the specified guest page.
1650 * @returns Physical TLB index.
1651 * @param GCPhys The guest physical address.
1652 */
1653#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1654
1655
1656/**
1657 * Raw-mode context dynamic mapping cache entry.
1658 *
1659 * Because of raw-mode context being reloctable and all relocations are applied
1660 * in ring-3, this has to be defined here and be RC specfic.
1661 *
1662 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1663 */
1664typedef struct PGMRCDYNMAPENTRY
1665{
1666 /** The physical address of the currently mapped page.
1667 * This is duplicate for three reasons: cache locality, cache policy of the PT
1668 * mappings and sanity checks. */
1669 RTHCPHYS HCPhys;
1670 /** Pointer to the page. */
1671 RTRCPTR pvPage;
1672 /** The number of references. */
1673 int32_t volatile cRefs;
1674 /** PTE pointer union. */
1675 union PGMRCDYNMAPENTRY_PPTE
1676 {
1677 /** PTE pointer, 32-bit legacy version. */
1678 RCPTRTYPE(PX86PTE) pLegacy;
1679 /** PTE pointer, PAE version. */
1680 RCPTRTYPE(PX86PTEPAE) pPae;
1681 /** PTE pointer, the void version. */
1682 RTRCPTR pv;
1683 } uPte;
1684 /** Alignment padding. */
1685 RTRCPTR RCPtrAlignment;
1686} PGMRCDYNMAPENTRY;
1687/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1688typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1689
1690
1691/**
1692 * Dynamic mapping cache for the raw-mode context.
1693 *
1694 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1695 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1696 * so that we can perform relocations from PGMR3Relocate. This has the
1697 * consequence that we must have separate ring-0 and raw-mode context versions
1698 * of this struct even if they share the basic elements.
1699 *
1700 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1701 */
1702typedef struct PGMRCDYNMAP
1703{
1704 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1705 uint32_t u32Magic;
1706 /** Array for tracking and managing the pages. */
1707 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1708 /** The cache size given as a number of pages. */
1709 uint32_t cPages;
1710 /** Whether it's 32-bit legacy or PAE/AMD64 paging mode. */
1711 bool fLegacyMode;
1712 /** The current load.
1713 * This does not include guard pages. */
1714 uint32_t cLoad;
1715 /** The max load ever.
1716 * This is maintained to get trigger adding of more mapping space. */
1717 uint32_t cMaxLoad;
1718 /** The number of guard pages. */
1719 uint32_t cGuardPages;
1720 /** The number of users (protected by hInitLock). */
1721 uint32_t cUsers;
1722} PGMRCDYNMAP;
1723/** Pointer to the dynamic cache for the raw-mode context. */
1724typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1725
1726
1727/**
1728 * Mapping cache usage set entry.
1729 *
1730 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1731 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1732 * cache. If it's extended to include ring-3, well, then something
1733 * will have be changed here...
1734 */
1735typedef struct PGMMAPSETENTRY
1736{
1737 /** Pointer to the page. */
1738#ifndef IN_RC
1739 RTR0PTR pvPage;
1740#else
1741 RTRCPTR pvPage;
1742# if HC_ARCH_BITS == 64
1743 uint32_t u32Alignment2;
1744# endif
1745#endif
1746 /** The mapping cache index. */
1747 uint16_t iPage;
1748 /** The number of references.
1749 * The max is UINT16_MAX - 1. */
1750 uint16_t cRefs;
1751 /** The number inlined references.
1752 * The max is UINT16_MAX - 1. */
1753 uint16_t cInlinedRefs;
1754 /** Unreferences. */
1755 uint16_t cUnrefs;
1756
1757#if HC_ARCH_BITS == 32
1758 uint32_t u32Alignment1;
1759#endif
1760 /** The physical address for this entry. */
1761 RTHCPHYS HCPhys;
1762} PGMMAPSETENTRY;
1763AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1764AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1765/** Pointer to a mapping cache usage set entry. */
1766typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1767
1768/**
1769 * Mapping cache usage set.
1770 *
1771 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1772 * done during exits / traps. The set is
1773 */
1774typedef struct PGMMAPSET
1775{
1776 /** The number of occupied entries.
1777 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1778 * dynamic mappings. */
1779 uint32_t cEntries;
1780 /** The start of the current subset.
1781 * This is UINT32_MAX if no subset is currently open. */
1782 uint32_t iSubset;
1783 /** The index of the current CPU, only valid if the set is open. */
1784 int32_t iCpu;
1785 uint32_t alignment;
1786 /** The entries. */
1787 PGMMAPSETENTRY aEntries[64];
1788 /** HCPhys -> iEntry fast lookup table.
1789 * Use PGMMAPSET_HASH for hashing.
1790 * The entries may or may not be valid, check against cEntries. */
1791 uint8_t aiHashTable[128];
1792} PGMMAPSET;
1793AssertCompileSizeAlignment(PGMMAPSET, 8);
1794/** Pointer to the mapping cache set. */
1795typedef PGMMAPSET *PPGMMAPSET;
1796
1797/** PGMMAPSET::cEntries value for a closed set. */
1798#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1799
1800/** Hash function for aiHashTable. */
1801#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1802
1803/** The max fill size (strict builds). */
1804#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1805
1806
1807/** @name Context neutrual page mapper TLB.
1808 *
1809 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1810 * code is writting in a kind of context neutrual way. Time will show whether
1811 * this actually makes sense or not...
1812 *
1813 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1814 * context ends up using a global mapping cache on some platforms
1815 * (darwin).
1816 *
1817 * @{ */
1818/** @typedef PPGMPAGEMAPTLB
1819 * The page mapper TLB pointer type for the current context. */
1820/** @typedef PPGMPAGEMAPTLB
1821 * The page mapper TLB entry pointer type for the current context. */
1822/** @typedef PPGMPAGEMAPTLB
1823 * The page mapper TLB entry pointer pointer type for the current context. */
1824/** @def PGM_PAGEMAPTLB_ENTRIES
1825 * The number of TLB entries in the page mapper TLB for the current context. */
1826/** @def PGM_PAGEMAPTLB_IDX
1827 * Calculate the TLB index for a guest physical address.
1828 * @returns The TLB index.
1829 * @param GCPhys The guest physical address. */
1830/** @typedef PPGMPAGEMAP
1831 * Pointer to a page mapper unit for current context. */
1832/** @typedef PPPGMPAGEMAP
1833 * Pointer to a page mapper unit pointer for current context. */
1834#ifdef IN_RC
1835// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1836// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1837// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1838# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1839# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1840 typedef void * PPGMPAGEMAP;
1841 typedef void ** PPPGMPAGEMAP;
1842//#elif IN_RING0
1843// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1844// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1845// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1846//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1847//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1848// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1849// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1850#else
1851 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1852 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1853 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1854# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1855# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1856 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1857 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1858#endif
1859/** @} */
1860
1861
1862/** @name PGM Pool Indexes.
1863 * Aka. the unique shadow page identifier.
1864 * @{ */
1865/** NIL page pool IDX. */
1866#define NIL_PGMPOOL_IDX 0
1867/** The first normal index. */
1868#define PGMPOOL_IDX_FIRST_SPECIAL 1
1869/** Page directory (32-bit root). */
1870#define PGMPOOL_IDX_PD 1
1871/** Page Directory Pointer Table (PAE root). */
1872#define PGMPOOL_IDX_PDPT 2
1873/** AMD64 CR3 level index.*/
1874#define PGMPOOL_IDX_AMD64_CR3 3
1875/** Nested paging root.*/
1876#define PGMPOOL_IDX_NESTED_ROOT 4
1877/** The first normal index. */
1878#define PGMPOOL_IDX_FIRST 5
1879/** The last valid index. (inclusive, 14 bits) */
1880#define PGMPOOL_IDX_LAST 0x3fff
1881/** @} */
1882
1883/** The NIL index for the parent chain. */
1884#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1885#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1886
1887/**
1888 * Node in the chain linking a shadowed page to it's parent (user).
1889 */
1890#pragma pack(1)
1891typedef struct PGMPOOLUSER
1892{
1893 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1894 uint16_t iNext;
1895 /** The user page index. */
1896 uint16_t iUser;
1897 /** Index into the user table. */
1898 uint32_t iUserTable;
1899} PGMPOOLUSER, *PPGMPOOLUSER;
1900typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1901#pragma pack()
1902
1903
1904/** The NIL index for the phys ext chain. */
1905#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1906/** The NIL pte index for a phys ext chain slot. */
1907#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1908
1909/**
1910 * Node in the chain of physical cross reference extents.
1911 * @todo Calling this an 'extent' is not quite right, find a better name.
1912 * @todo find out the optimal size of the aidx array
1913 */
1914#pragma pack(1)
1915typedef struct PGMPOOLPHYSEXT
1916{
1917 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1918 uint16_t iNext;
1919 /** Alignment. */
1920 uint16_t u16Align;
1921 /** The user page index. */
1922 uint16_t aidx[3];
1923 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1924 uint16_t apte[3];
1925} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1926typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1927#pragma pack()
1928
1929
1930/**
1931 * The kind of page that's being shadowed.
1932 */
1933typedef enum PGMPOOLKIND
1934{
1935 /** The virtual invalid 0 entry. */
1936 PGMPOOLKIND_INVALID = 0,
1937 /** The entry is free (=unused). */
1938 PGMPOOLKIND_FREE,
1939
1940 /** Shw: 32-bit page table; Gst: no paging */
1941 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1942 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1943 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1944 /** Shw: 32-bit page table; Gst: 4MB page. */
1945 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1946 /** Shw: PAE page table; Gst: no paging */
1947 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1948 /** Shw: PAE page table; Gst: 32-bit page table. */
1949 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1950 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1951 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1952 /** Shw: PAE page table; Gst: PAE page table. */
1953 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1954 /** Shw: PAE page table; Gst: 2MB page. */
1955 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1956
1957 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1958 PGMPOOLKIND_32BIT_PD,
1959 /** Shw: 32-bit page directory. Gst: no paging. */
1960 PGMPOOLKIND_32BIT_PD_PHYS,
1961 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1962 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1963 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1964 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1965 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1966 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1967 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1968 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1969 /** Shw: PAE page directory; Gst: PAE page directory. */
1970 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1971 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1972 PGMPOOLKIND_PAE_PD_PHYS,
1973
1974 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1975 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1976 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1977 PGMPOOLKIND_PAE_PDPT,
1978 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1979 PGMPOOLKIND_PAE_PDPT_PHYS,
1980
1981 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1982 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1983 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1984 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1985 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1986 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1987 /** Shw: 64-bit page directory table; Gst: no paging */
1988 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1989
1990 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1991 PGMPOOLKIND_64BIT_PML4,
1992
1993 /** Shw: EPT page directory pointer table; Gst: no paging */
1994 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1995 /** Shw: EPT page directory table; Gst: no paging */
1996 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1997 /** Shw: EPT page table; Gst: no paging */
1998 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1999
2000 /** Shw: Root Nested paging table. */
2001 PGMPOOLKIND_ROOT_NESTED,
2002
2003 /** The last valid entry. */
2004 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2005} PGMPOOLKIND;
2006
2007/**
2008 * The access attributes of the page; only applies to big pages.
2009 */
2010typedef enum
2011{
2012 PGMPOOLACCESS_DONTCARE = 0,
2013 PGMPOOLACCESS_USER_RW,
2014 PGMPOOLACCESS_USER_R,
2015 PGMPOOLACCESS_USER_RW_NX,
2016 PGMPOOLACCESS_USER_R_NX,
2017 PGMPOOLACCESS_SUPERVISOR_RW,
2018 PGMPOOLACCESS_SUPERVISOR_R,
2019 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2020 PGMPOOLACCESS_SUPERVISOR_R_NX
2021} PGMPOOLACCESS;
2022
2023/**
2024 * The tracking data for a page in the pool.
2025 */
2026typedef struct PGMPOOLPAGE
2027{
2028 /** AVL node code with the (R3) physical address of this page. */
2029 AVLOHCPHYSNODECORE Core;
2030 /** Pointer to the R3 mapping of the page. */
2031#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2032 R3PTRTYPE(void *) pvPageR3;
2033#else
2034 R3R0PTRTYPE(void *) pvPageR3;
2035#endif
2036 /** The guest physical address. */
2037#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2038 uint32_t Alignment0;
2039#endif
2040 RTGCPHYS GCPhys;
2041
2042 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2043 RTGCPTR pvLastAccessHandlerRip;
2044 RTGCPTR pvLastAccessHandlerFault;
2045 uint64_t cLastAccessHandlerCount;
2046
2047 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2048 uint8_t enmKind;
2049 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2050 uint8_t enmAccess;
2051 /** The index of this page. */
2052 uint16_t idx;
2053 /** The next entry in the list this page currently resides in.
2054 * It's either in the free list or in the GCPhys hash. */
2055 uint16_t iNext;
2056 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2057 uint16_t iUserHead;
2058 /** The number of present entries. */
2059 uint16_t cPresent;
2060 /** The first entry in the table which is present. */
2061 uint16_t iFirstPresent;
2062 /** The number of modifications to the monitored page. */
2063 uint16_t cModifications;
2064 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2065 uint16_t iModifiedNext;
2066 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2067 uint16_t iModifiedPrev;
2068 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2069 uint16_t iMonitoredNext;
2070 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2071 uint16_t iMonitoredPrev;
2072 /** The next page in the age list. */
2073 uint16_t iAgeNext;
2074 /** The previous page in the age list. */
2075 uint16_t iAgePrev;
2076 /** Used to indicate that the page is zeroed. */
2077 bool fZeroed;
2078 /** Used to indicate that a PT has non-global entries. */
2079 bool fSeenNonGlobal;
2080 /** Used to indicate that we're monitoring writes to the guest page. */
2081 bool fMonitored;
2082 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2083 * (All pages are in the age list.) */
2084 bool fCached;
2085 /** This is used by the R3 access handlers when invoked by an async thread.
2086 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2087 bool volatile fReusedFlushPending;
2088 /** Used to mark the page as dirty (write monitoring is temporarily
2089 * off). */
2090 bool fDirty;
2091
2092 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2093 uint32_t cLocked;
2094 uint32_t idxDirty;
2095 RTGCPTR pvDirtyFault;
2096} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
2097/** Pointer to a const pool page. */
2098typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2099
2100
2101/** The hash table size. */
2102# define PGMPOOL_HASH_SIZE 0x40
2103/** The hash function. */
2104# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2105
2106
2107/**
2108 * The shadow page pool instance data.
2109 *
2110 * It's all one big allocation made at init time, except for the
2111 * pages that is. The user nodes follows immediatly after the
2112 * page structures.
2113 */
2114typedef struct PGMPOOL
2115{
2116 /** The VM handle - R3 Ptr. */
2117 PVMR3 pVMR3;
2118 /** The VM handle - R0 Ptr. */
2119 PVMR0 pVMR0;
2120 /** The VM handle - RC Ptr. */
2121 PVMRC pVMRC;
2122 /** The max pool size. This includes the special IDs. */
2123 uint16_t cMaxPages;
2124 /** The current pool size. */
2125 uint16_t cCurPages;
2126 /** The head of the free page list. */
2127 uint16_t iFreeHead;
2128 /* Padding. */
2129 uint16_t u16Padding;
2130 /** Head of the chain of free user nodes. */
2131 uint16_t iUserFreeHead;
2132 /** The number of user nodes we've allocated. */
2133 uint16_t cMaxUsers;
2134 /** The number of present page table entries in the entire pool. */
2135 uint32_t cPresent;
2136 /** Pointer to the array of user nodes - RC pointer. */
2137 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2138 /** Pointer to the array of user nodes - R3 pointer. */
2139 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2140 /** Pointer to the array of user nodes - R0 pointer. */
2141 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2142 /** Head of the chain of free phys ext nodes. */
2143 uint16_t iPhysExtFreeHead;
2144 /** The number of user nodes we've allocated. */
2145 uint16_t cMaxPhysExts;
2146 /** Pointer to the array of physical xref extent - RC pointer. */
2147 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2148 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2149 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2150 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2151 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2152 /** Hash table for GCPhys addresses. */
2153 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2154 /** The head of the age list. */
2155 uint16_t iAgeHead;
2156 /** The tail of the age list. */
2157 uint16_t iAgeTail;
2158 /** Set if the cache is enabled. */
2159 bool fCacheEnabled;
2160 /** Alignment padding. */
2161 bool afPadding1[3];
2162 /** Head of the list of modified pages. */
2163 uint16_t iModifiedHead;
2164 /** The current number of modified pages. */
2165 uint16_t cModifiedPages;
2166 /** Access handler, RC. */
2167 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2168 /** Access handler, R0. */
2169 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2170 /** Access handler, R3. */
2171 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2172 /** The access handler description (R3 ptr). */
2173 R3PTRTYPE(const char *) pszAccessHandler;
2174# if HC_ARCH_BITS == 32
2175 /** Alignment padding. */
2176 uint32_t u32Padding2;
2177# endif
2178 /* Next available slot. */
2179 uint32_t idxFreeDirtyPage;
2180 /* Number of active dirty pages. */
2181 uint32_t cDirtyPages;
2182 /* Array of current dirty pgm pool page indices. */
2183 uint16_t aIdxDirtyPages[16];
2184 uint64_t aDirtyPages[16][512];
2185 /** The number of pages currently in use. */
2186 uint16_t cUsedPages;
2187#ifdef VBOX_WITH_STATISTICS
2188 /** The high water mark for cUsedPages. */
2189 uint16_t cUsedPagesHigh;
2190 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
2191 /** Profiling pgmPoolAlloc(). */
2192 STAMPROFILEADV StatAlloc;
2193 /** Profiling pgmR3PoolClearDoIt(). */
2194 STAMPROFILE StatClearAll;
2195 /** Profiling pgmR3PoolReset(). */
2196 STAMPROFILE StatR3Reset;
2197 /** Profiling pgmPoolFlushPage(). */
2198 STAMPROFILE StatFlushPage;
2199 /** Profiling pgmPoolFree(). */
2200 STAMPROFILE StatFree;
2201 /** Counting explicit flushes by PGMPoolFlushPage(). */
2202 STAMCOUNTER StatForceFlushPage;
2203 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2204 STAMCOUNTER StatForceFlushDirtyPage;
2205 /** Counting flushes for reused pages. */
2206 STAMCOUNTER StatForceFlushReused;
2207 /** Profiling time spent zeroing pages. */
2208 STAMPROFILE StatZeroPage;
2209 /** Profiling of pgmPoolTrackDeref. */
2210 STAMPROFILE StatTrackDeref;
2211 /** Profiling pgmTrackFlushGCPhysPT. */
2212 STAMPROFILE StatTrackFlushGCPhysPT;
2213 /** Profiling pgmTrackFlushGCPhysPTs. */
2214 STAMPROFILE StatTrackFlushGCPhysPTs;
2215 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2216 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2217 /** Number of times we've been out of user records. */
2218 STAMCOUNTER StatTrackFreeUpOneUser;
2219 /** Nr of flushed entries. */
2220 STAMCOUNTER StatTrackFlushEntry;
2221 /** Nr of updated entries. */
2222 STAMCOUNTER StatTrackFlushEntryKeep;
2223 /** Profiling deref activity related tracking GC physical pages. */
2224 STAMPROFILE StatTrackDerefGCPhys;
2225 /** Number of linear searches for a HCPhys in the ram ranges. */
2226 STAMCOUNTER StatTrackLinearRamSearches;
2227 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2228 STAMCOUNTER StamTrackPhysExtAllocFailures;
2229 /** Profiling the RC/R0 access handler. */
2230 STAMPROFILE StatMonitorRZ;
2231 /** Times we've failed interpreting the instruction. */
2232 STAMCOUNTER StatMonitorRZEmulateInstr;
2233 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2234 STAMPROFILE StatMonitorRZFlushPage;
2235 /* Times we've detected a page table reinit. */
2236 STAMCOUNTER StatMonitorRZFlushReinit;
2237 /** Counting flushes for pages that are modified too often. */
2238 STAMCOUNTER StatMonitorRZFlushModOverflow;
2239 /** Times we've detected fork(). */
2240 STAMCOUNTER StatMonitorRZFork;
2241 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2242 STAMPROFILE StatMonitorRZHandled;
2243 /** Times we've failed interpreting a patch code instruction. */
2244 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2245 /** Times we've failed interpreting a patch code instruction during flushing. */
2246 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2247 /** The number of times we've seen rep prefixes we can't handle. */
2248 STAMCOUNTER StatMonitorRZRepPrefix;
2249 /** Profiling the REP STOSD cases we've handled. */
2250 STAMPROFILE StatMonitorRZRepStosd;
2251 /** Nr of handled PT faults. */
2252 STAMCOUNTER StatMonitorRZFaultPT;
2253 /** Nr of handled PD faults. */
2254 STAMCOUNTER StatMonitorRZFaultPD;
2255 /** Nr of handled PDPT faults. */
2256 STAMCOUNTER StatMonitorRZFaultPDPT;
2257 /** Nr of handled PML4 faults. */
2258 STAMCOUNTER StatMonitorRZFaultPML4;
2259
2260 /** Profiling the R3 access handler. */
2261 STAMPROFILE StatMonitorR3;
2262 /** Times we've failed interpreting the instruction. */
2263 STAMCOUNTER StatMonitorR3EmulateInstr;
2264 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2265 STAMPROFILE StatMonitorR3FlushPage;
2266 /* Times we've detected a page table reinit. */
2267 STAMCOUNTER StatMonitorR3FlushReinit;
2268 /** Counting flushes for pages that are modified too often. */
2269 STAMCOUNTER StatMonitorR3FlushModOverflow;
2270 /** Times we've detected fork(). */
2271 STAMCOUNTER StatMonitorR3Fork;
2272 /** Profiling the R3 access we've handled (except REP STOSD). */
2273 STAMPROFILE StatMonitorR3Handled;
2274 /** The number of times we've seen rep prefixes we can't handle. */
2275 STAMCOUNTER StatMonitorR3RepPrefix;
2276 /** Profiling the REP STOSD cases we've handled. */
2277 STAMPROFILE StatMonitorR3RepStosd;
2278 /** Nr of handled PT faults. */
2279 STAMCOUNTER StatMonitorR3FaultPT;
2280 /** Nr of handled PD faults. */
2281 STAMCOUNTER StatMonitorR3FaultPD;
2282 /** Nr of handled PDPT faults. */
2283 STAMCOUNTER StatMonitorR3FaultPDPT;
2284 /** Nr of handled PML4 faults. */
2285 STAMCOUNTER StatMonitorR3FaultPML4;
2286 /** The number of times we're called in an async thread an need to flush. */
2287 STAMCOUNTER StatMonitorR3Async;
2288 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2289 STAMCOUNTER StatResetDirtyPages;
2290 /** Times we've called pgmPoolAddDirtyPage. */
2291 STAMCOUNTER StatDirtyPage;
2292 /** Times we've had to flush duplicates for dirty page management. */
2293 STAMCOUNTER StatDirtyPageDupFlush;
2294 /** Times we've had to flush because of overflow. */
2295 STAMCOUNTER StatDirtyPageOverFlowFlush;
2296
2297 /** The high wather mark for cModifiedPages. */
2298 uint16_t cModifiedPagesHigh;
2299 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2300
2301 /** The number of cache hits. */
2302 STAMCOUNTER StatCacheHits;
2303 /** The number of cache misses. */
2304 STAMCOUNTER StatCacheMisses;
2305 /** The number of times we've got a conflict of 'kind' in the cache. */
2306 STAMCOUNTER StatCacheKindMismatches;
2307 /** Number of times we've been out of pages. */
2308 STAMCOUNTER StatCacheFreeUpOne;
2309 /** The number of cacheable allocations. */
2310 STAMCOUNTER StatCacheCacheable;
2311 /** The number of uncacheable allocations. */
2312 STAMCOUNTER StatCacheUncacheable;
2313#else
2314 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2315#endif
2316 /** The AVL tree for looking up a page by its HC physical address. */
2317 AVLOHCPHYSTREE HCPhysTree;
2318 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2319 /** Array of pages. (cMaxPages in length)
2320 * The Id is the index into thist array.
2321 */
2322 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2323} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2324AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2325AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2326AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2327#ifdef VBOX_WITH_STATISTICS
2328AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2329#endif
2330AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2331
2332
2333/** @def PGMPOOL_PAGE_2_PTR
2334 * Maps a pool page pool into the current context.
2335 *
2336 * @returns VBox status code.
2337 * @param pVM The VM handle.
2338 * @param pPage The pool page.
2339 *
2340 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2341 * small page window employeed by that function. Be careful.
2342 * @remark There is no need to assert on the result.
2343 */
2344#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2345# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage) RTLOG_COMMA_SRC_POS)
2346#elif defined(VBOX_STRICT)
2347# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2348DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2349{
2350 Assert(pPage && pPage->pvPageR3);
2351 return pPage->pvPageR3;
2352}
2353#else
2354# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2355#endif
2356
2357
2358/** @def PGMPOOL_PAGE_2_PTR_V2
2359 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2360 *
2361 * @returns VBox status code.
2362 * @param pVM The VM handle.
2363 * @param pVCpu The current CPU.
2364 * @param pPage The pool page.
2365 *
2366 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2367 * small page window employeed by that function. Be careful.
2368 * @remark There is no need to assert on the result.
2369 */
2370#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2371# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage) RTLOG_COMMA_SRC_POS)
2372#else
2373# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2374#endif
2375
2376
2377/** @name Per guest page tracking data.
2378 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2379 * is to use more bits for it and split it up later on. But for now we'll play
2380 * safe and change as little as possible.
2381 *
2382 * The 16-bit word has two parts:
2383 *
2384 * The first 14-bit forms the @a idx field. It is either the index of a page in
2385 * the shadow page pool, or and index into the extent list.
2386 *
2387 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2388 * shadow page pool references to the page. If cRefs equals
2389 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2390 * (misnomer) table and not the shadow page pool.
2391 *
2392 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2393 * the 16-bit word.
2394 *
2395 * @{ */
2396/** The shift count for getting to the cRefs part. */
2397#define PGMPOOL_TD_CREFS_SHIFT 14
2398/** The mask applied after shifting the tracking data down by
2399 * PGMPOOL_TD_CREFS_SHIFT. */
2400#define PGMPOOL_TD_CREFS_MASK 0x3
2401/** The cRefs value used to indiciate that the idx is the head of a
2402 * physical cross reference list. */
2403#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2404/** The shift used to get idx. */
2405#define PGMPOOL_TD_IDX_SHIFT 0
2406/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2407#define PGMPOOL_TD_IDX_MASK 0x3fff
2408/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2409 * simply too many mappings of this page. */
2410#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2411
2412/** @def PGMPOOL_TD_MAKE
2413 * Makes a 16-bit tracking data word.
2414 *
2415 * @returns tracking data.
2416 * @param cRefs The @a cRefs field. Must be within bounds!
2417 * @param idx The @a idx field. Must also be within bounds! */
2418#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2419
2420/** @def PGMPOOL_TD_GET_CREFS
2421 * Get the @a cRefs field from a tracking data word.
2422 *
2423 * @returns The @a cRefs field
2424 * @param u16 The tracking data word.
2425 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2426 * non-zero @a u16. */
2427#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2428
2429/** @def PGMPOOL_TD_GET_IDX
2430 * Get the @a idx field from a tracking data word.
2431 *
2432 * @returns The @a idx field
2433 * @param u16 The tracking data word. */
2434#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2435/** @} */
2436
2437
2438/**
2439 * Trees are using self relative offsets as pointers.
2440 * So, all its data, including the root pointer, must be in the heap for HC and GC
2441 * to have the same layout.
2442 */
2443typedef struct PGMTREES
2444{
2445 /** Physical access handlers (AVL range+offsetptr tree). */
2446 AVLROGCPHYSTREE PhysHandlers;
2447 /** Virtual access handlers (AVL range + GC ptr tree). */
2448 AVLROGCPTRTREE VirtHandlers;
2449 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2450 AVLROGCPHYSTREE PhysToVirtHandlers;
2451 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2452 AVLROGCPTRTREE HyperVirtHandlers;
2453} PGMTREES;
2454/** Pointer to PGM trees. */
2455typedef PGMTREES *PPGMTREES;
2456
2457
2458/**
2459 * Page fault guest state for the AMD64 paging mode.
2460 */
2461typedef struct PGMPTWALKCORE
2462{
2463 /** The guest virtual address that is being resolved by the walk
2464 * (input). */
2465 RTGCPTR GCPtr;
2466
2467 /** The guest physcial address that is the result of the walk.
2468 * @remarks only valid if fSucceeded is set. */
2469 RTGCPHYS GCPhys;
2470
2471 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2472 bool fSucceeded;
2473 /** The level problem arrised at.
2474 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2475 * level 8. This is 0 on success. */
2476 uint8_t uLevel;
2477 /** Set if the page isn't present. */
2478 bool fNotPresent;
2479 /** Encountered a bad physical address. */
2480 bool fBadPhysAddr;
2481 /** Set if there was reserved bit violations. */
2482 bool fRsvdError;
2483 /** Set if it involves a big page (2/4 MB). */
2484 bool fBigPage;
2485 /** Set if it involves a gigantic page (1 GB). */
2486 bool fGigantPage;
2487 /** The effect X86_PTE_US flag for the address. */
2488 bool fEffectiveUS;
2489 /** The effect X86_PTE_RW flag for the address. */
2490 bool fEffectiveRW;
2491 /** The effect X86_PTE_NX flag for the address. */
2492 bool fEffectiveNX;
2493} PGMPTWALKCORE;
2494
2495
2496/**
2497 * Guest page table walk for the AMD64 mode.
2498 */
2499typedef struct PGMPTWALKGSTAMD64
2500{
2501 /** The common core. */
2502 PGMPTWALKCORE Core;
2503
2504 PX86PML4 pPml4;
2505 PX86PML4E pPml4e;
2506 X86PML4E Pml4e;
2507
2508 PX86PDPT pPdpt;
2509 PX86PDPE pPdpe;
2510 X86PDPE Pdpe;
2511
2512 PX86PDPAE pPd;
2513 PX86PDEPAE pPde;
2514 X86PDEPAE Pde;
2515
2516 PX86PTPAE pPt;
2517 PX86PTEPAE pPte;
2518 X86PTEPAE Pte;
2519} PGMPTWALKGSTAMD64;
2520/** Pointer to a AMD64 guest page table walk. */
2521typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2522/** Pointer to a const AMD64 guest page table walk. */
2523typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2524
2525/**
2526 * Guest page table walk for the PAE mode.
2527 */
2528typedef struct PGMPTWALKGSTPAE
2529{
2530 /** The common core. */
2531 PGMPTWALKCORE Core;
2532
2533 PX86PDPT pPdpt;
2534 PX86PDPE pPdpe;
2535 X86PDPE Pdpe;
2536
2537 PX86PDPAE pPd;
2538 PX86PDEPAE pPde;
2539 X86PDEPAE Pde;
2540
2541 PX86PTPAE pPt;
2542 PX86PTEPAE pPte;
2543 X86PTEPAE Pte;
2544} PGMPTWALKGSTPAE;
2545/** Pointer to a PAE guest page table walk. */
2546typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2547/** Pointer to a const AMD64 guest page table walk. */
2548typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2549
2550/**
2551 * Guest page table walk for the 32-bit mode.
2552 */
2553typedef struct PGMPTWALKGST32BIT
2554{
2555 /** The common core. */
2556 PGMPTWALKCORE Core;
2557
2558 PX86PD pPd;
2559 PX86PDE pPde;
2560 X86PDE Pde;
2561
2562 PX86PT pPt;
2563 PX86PTE pPte;
2564 X86PTE Pte;
2565} PGMPTWALKGST32BIT;
2566/** Pointer to a 32-bit guest page table walk. */
2567typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2568/** Pointer to a const 32-bit guest page table walk. */
2569typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2570
2571
2572/** @name Paging mode macros
2573 * @{
2574 */
2575#ifdef IN_RC
2576# define PGM_CTX(a,b) a##RC##b
2577# define PGM_CTX_STR(a,b) a "GC" b
2578# define PGM_CTX_DECL(type) VMMRCDECL(type)
2579#else
2580# ifdef IN_RING3
2581# define PGM_CTX(a,b) a##R3##b
2582# define PGM_CTX_STR(a,b) a "R3" b
2583# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2584# else
2585# define PGM_CTX(a,b) a##R0##b
2586# define PGM_CTX_STR(a,b) a "R0" b
2587# define PGM_CTX_DECL(type) VMMDECL(type)
2588# endif
2589#endif
2590
2591#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2592#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2593#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2594#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2595#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2596#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2597#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2598#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2599#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2600#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2601#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2602#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2603#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2604#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2605#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2606#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2607#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2608
2609#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2610#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2611#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2612#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2613#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2614#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2615#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2616#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2617#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2618#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2619#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2620#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2621#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2622#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2623#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2624#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2625#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2626
2627/* Shw_Gst */
2628#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2629#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2630#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2631#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2632#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2633#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2634#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2635#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2636#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2637#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2638#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2639#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2640#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2641#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2642#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2643#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2644#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2645#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2646#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2647
2648#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2649#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2650#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2651#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2652#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2653#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2654#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2655#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2656#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2657#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2658#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2659#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2660#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2661#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2662#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2663#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2664#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2665#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2666#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2667#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2668#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2669#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2670#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2671#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2672#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2673#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2674#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2675#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2676#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2677#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2678#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2679#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2680#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2681#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2682#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2683#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2684#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2685
2686#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2687#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2688/** @} */
2689
2690/**
2691 * Data for each paging mode.
2692 */
2693typedef struct PGMMODEDATA
2694{
2695 /** The guest mode type. */
2696 uint32_t uGstType;
2697 /** The shadow mode type. */
2698 uint32_t uShwType;
2699
2700 /** @name Function pointers for Shadow paging.
2701 * @{
2702 */
2703 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2704 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2705 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2706 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2707
2708 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2709 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2710
2711 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2712 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2713 /** @} */
2714
2715 /** @name Function pointers for Guest paging.
2716 * @{
2717 */
2718 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2719 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2720 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2721 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2722 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2723 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2724 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2725 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2726 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2727 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2728 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2729 /** @} */
2730
2731 /** @name Function pointers for Both Shadow and Guest paging.
2732 * @{
2733 */
2734 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2735 /* no pfnR3BthTrap0eHandler */
2736 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2737 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2738 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2739 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2740#ifdef VBOX_STRICT
2741 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2742#endif
2743 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2744 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2745
2746 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2747 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2748 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2749 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2750 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2751#ifdef VBOX_STRICT
2752 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2753#endif
2754 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2755 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2756
2757 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2758 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2759 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2760 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2761 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2762#ifdef VBOX_STRICT
2763 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2764#endif
2765 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2766 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2767 /** @} */
2768} PGMMODEDATA, *PPGMMODEDATA;
2769
2770
2771#ifdef VBOX_WITH_STATISTICS
2772/**
2773 * PGM statistics.
2774 *
2775 * These lives on the heap when compiled in as they would otherwise waste
2776 * unecessary space in release builds.
2777 */
2778typedef struct PGMSTATS
2779{
2780 /* R3 only: */
2781 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2782 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2783
2784 /* R3+RZ */
2785 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2786 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2787 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2788 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2789 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2790 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2791 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2792 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2793 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2794 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2795 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2796 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2797 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2798 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2799 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2800 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2801 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2802 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2803 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2804 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2805 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2806 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2807 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2808 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2809/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2810 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2811 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2812/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2813
2814 /* RC only: */
2815 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2816 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2817
2818 STAMCOUNTER StatRZPhysRead;
2819 STAMCOUNTER StatRZPhysReadBytes;
2820 STAMCOUNTER StatRZPhysWrite;
2821 STAMCOUNTER StatRZPhysWriteBytes;
2822 STAMCOUNTER StatR3PhysRead;
2823 STAMCOUNTER StatR3PhysReadBytes;
2824 STAMCOUNTER StatR3PhysWrite;
2825 STAMCOUNTER StatR3PhysWriteBytes;
2826 STAMCOUNTER StatRCPhysRead;
2827 STAMCOUNTER StatRCPhysReadBytes;
2828 STAMCOUNTER StatRCPhysWrite;
2829 STAMCOUNTER StatRCPhysWriteBytes;
2830
2831 STAMCOUNTER StatRZPhysSimpleRead;
2832 STAMCOUNTER StatRZPhysSimpleReadBytes;
2833 STAMCOUNTER StatRZPhysSimpleWrite;
2834 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2835 STAMCOUNTER StatR3PhysSimpleRead;
2836 STAMCOUNTER StatR3PhysSimpleReadBytes;
2837 STAMCOUNTER StatR3PhysSimpleWrite;
2838 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2839 STAMCOUNTER StatRCPhysSimpleRead;
2840 STAMCOUNTER StatRCPhysSimpleReadBytes;
2841 STAMCOUNTER StatRCPhysSimpleWrite;
2842 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2843
2844 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2845 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2846 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2847 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2848 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2849 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2850 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2851
2852 /** Time spent by the host OS for large page allocation. */
2853 STAMPROFILE StatAllocLargePage;
2854 /** Time spent clearing the newly allocated large pages. */
2855 STAMPROFILE StatClearLargePage;
2856 /** pgmPhysIsValidLargePage profiling - R3 */
2857 STAMPROFILE StatR3IsValidLargePage;
2858 /** pgmPhysIsValidLargePage profiling - RZ*/
2859 STAMPROFILE StatRZIsValidLargePage;
2860
2861 STAMPROFILE StatChunkAging;
2862 STAMPROFILE StatChunkFindCandidate;
2863 STAMPROFILE StatChunkUnmap;
2864 STAMPROFILE StatChunkMap;
2865} PGMSTATS;
2866#endif /* VBOX_WITH_STATISTICS */
2867
2868
2869/**
2870 * Converts a PGM pointer into a VM pointer.
2871 * @returns Pointer to the VM structure the PGM is part of.
2872 * @param pPGM Pointer to PGM instance data.
2873 */
2874#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2875
2876/**
2877 * PGM Data (part of VM)
2878 */
2879typedef struct PGM
2880{
2881 /** Offset to the VM structure. */
2882 int32_t offVM;
2883 /** Offset of the PGMCPU structure relative to VMCPU. */
2884 int32_t offVCpuPGM;
2885
2886 /** @cfgm{RamPreAlloc, boolean, false}
2887 * Indicates whether the base RAM should all be allocated before starting
2888 * the VM (default), or if it should be allocated when first written to.
2889 */
2890 bool fRamPreAlloc;
2891 /** Indicates whether write monitoring is currently in use.
2892 * This is used to prevent conflicts between live saving and page sharing
2893 * detection. */
2894 bool fPhysWriteMonitoringEngaged;
2895 /** Set if the CPU has less than 52-bit physical address width.
2896 * This is used */
2897 bool fLessThan52PhysicalAddressBits;
2898 /** Set when nested paging is active.
2899 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2900 * compilers optimize the code better. Whether we use nested paging or
2901 * not is something we find out during VMM initialization and we won't
2902 * change this later on. */
2903 bool fNestedPaging;
2904 /** The host paging mode. (This is what SUPLib reports.) */
2905 SUPPAGINGMODE enmHostMode;
2906 /** We're not in a state which permits writes to guest memory.
2907 * (Only used in strict builds.) */
2908 bool fNoMorePhysWrites;
2909 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2910 bool afAlignment1[3];
2911
2912 /** Indicates that PGMR3FinalizeMappings has been called and that further
2913 * PGMR3MapIntermediate calls will be rejected. */
2914 bool fFinalizedMappings;
2915 /** If set no conflict checks are required. */
2916 bool fMappingsFixed;
2917 /** If set if restored as fixed but we were unable to re-fixate at the old
2918 * location because of room or address incompatibilities. */
2919 bool fMappingsFixedRestored;
2920 /** If set, then no mappings are put into the shadow page table.
2921 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2922 bool fMappingsDisabled;
2923 /** Size of fixed mapping.
2924 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2925 uint32_t cbMappingFixed;
2926 /** Generation ID for the RAM ranges. This member is incremented everytime
2927 * a RAM range is linked or unlinked. */
2928 uint32_t volatile idRamRangesGen;
2929
2930 /** Base address (GC) of fixed mapping.
2931 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2932 RTGCPTR GCPtrMappingFixed;
2933 /** The address of the previous RAM range mapping. */
2934 RTGCPTR GCPtrPrevRamRangeMapping;
2935
2936 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2937 RTGCPHYS GCPhys4MBPSEMask;
2938 /** Mask containing the invalid bits of a guest physical address.
2939 * @remarks this does not stop at bit 52. */
2940 RTGCPHYS GCPhysInvAddrMask;
2941
2942
2943 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2944 * This is sorted by physical address and contains no overlapping ranges. */
2945 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2946 /** PGM offset based trees - R3 Ptr. */
2947 R3PTRTYPE(PPGMTREES) pTreesR3;
2948 /** Caching the last physical handler we looked up in R3. */
2949 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2950 /** Shadow Page Pool - R3 Ptr. */
2951 R3PTRTYPE(PPGMPOOL) pPoolR3;
2952 /** Linked list of GC mappings - for HC.
2953 * The list is sorted ascending on address. */
2954 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2955 /** Pointer to the list of ROM ranges - for R3.
2956 * This is sorted by physical address and contains no overlapping ranges. */
2957 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2958 /** Pointer to the list of MMIO2 ranges - for R3.
2959 * Registration order. */
2960 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2961 /** Pointer to SHW+GST mode data (function pointers).
2962 * The index into this table is made up from */
2963 R3PTRTYPE(PPGMMODEDATA) paModeData;
2964 /*RTR3PTR R3PtrAlignment0;*/
2965
2966
2967 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2968 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2969 /** PGM offset based trees - R0 Ptr. */
2970 R0PTRTYPE(PPGMTREES) pTreesR0;
2971 /** Caching the last physical handler we looked up in R0. */
2972 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2973 /** Shadow Page Pool - R0 Ptr. */
2974 R0PTRTYPE(PPGMPOOL) pPoolR0;
2975 /** Linked list of GC mappings - for R0.
2976 * The list is sorted ascending on address. */
2977 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2978 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2979 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2980 /*RTR0PTR R0PtrAlignment0;*/
2981
2982
2983 /** RC pointer corresponding to PGM::pRamRangesR3. */
2984 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2985 /** PGM offset based trees - RC Ptr. */
2986 RCPTRTYPE(PPGMTREES) pTreesRC;
2987 /** Caching the last physical handler we looked up in RC. */
2988 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
2989 /** Shadow Page Pool - RC Ptr. */
2990 RCPTRTYPE(PPGMPOOL) pPoolRC;
2991 /** Linked list of GC mappings - for RC.
2992 * The list is sorted ascending on address. */
2993 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2994 /** RC pointer corresponding to PGM::pRomRangesR3. */
2995 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2996 /*RTRCPTR RCPtrAlignment0;*/
2997 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2998 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2999 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3000 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3001
3002
3003 /** Pointer to the 5 page CR3 content mapping.
3004 * The first page is always the CR3 (in some form) while the 4 other pages
3005 * are used of the PDs in PAE mode. */
3006 RTGCPTR GCPtrCR3Mapping;
3007
3008 /** @name Intermediate Context
3009 * @{ */
3010 /** Pointer to the intermediate page directory - Normal. */
3011 R3PTRTYPE(PX86PD) pInterPD;
3012 /** Pointer to the intermedate page tables - Normal.
3013 * There are two page tables, one for the identity mapping and one for
3014 * the host context mapping (of the core code). */
3015 R3PTRTYPE(PX86PT) apInterPTs[2];
3016 /** Pointer to the intermedate page tables - PAE. */
3017 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3018 /** Pointer to the intermedate page directory - PAE. */
3019 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3020 /** Pointer to the intermedate page directory - PAE. */
3021 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3022 /** Pointer to the intermedate page-map level 4 - AMD64. */
3023 R3PTRTYPE(PX86PML4) pInterPaePML4;
3024 /** Pointer to the intermedate page directory - AMD64. */
3025 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3026 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3027 RTHCPHYS HCPhysInterPD;
3028 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3029 RTHCPHYS HCPhysInterPaePDPT;
3030 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3031 RTHCPHYS HCPhysInterPaePML4;
3032 /** @} */
3033
3034 /** Base address of the dynamic page mapping area.
3035 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3036 *
3037 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3038 * work out. Some cleaning up of the initialization that would
3039 * remove this memory is yet to be done...
3040 */
3041 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3042 /** The address of the raw-mode context mapping cache. */
3043 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3044 /** The address of the ring-0 mapping cache if we're making use of it. */
3045 RTR0PTR pvR0DynMapUsed;
3046#if HC_ARCH_BITS == 32
3047 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
3048 uint32_t u32Alignment2;
3049#endif
3050
3051 /** PGM critical section.
3052 * This protects the physical & virtual access handlers, ram ranges,
3053 * and the page flag updating (some of it anyway).
3054 */
3055 PDMCRITSECT CritSect;
3056
3057 /**
3058 * Data associated with managing the ring-3 mappings of the allocation chunks.
3059 */
3060 struct
3061 {
3062 /** The chunk tree, ordered by chunk id. */
3063#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3064 R3PTRTYPE(PAVLU32NODECORE) pTree;
3065#else
3066 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3067#endif
3068#if HC_ARCH_BITS == 32
3069 uint32_t u32Alignment;
3070#endif
3071 /** The chunk mapping TLB. */
3072 PGMCHUNKR3MAPTLB Tlb;
3073 /** The number of mapped chunks. */
3074 uint32_t c;
3075 /** The maximum number of mapped chunks.
3076 * @cfgm PGM/MaxRing3Chunks */
3077 uint32_t cMax;
3078 /** The current time. */
3079 uint32_t iNow;
3080 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3081 uint32_t AgeingCountdown;
3082 } ChunkR3Map;
3083
3084 /**
3085 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3086 */
3087 PGMPAGER3MAPTLB PhysTlbHC;
3088
3089 /** @name The zero page.
3090 * @{ */
3091 /** The host physical address of the zero page. */
3092 RTHCPHYS HCPhysZeroPg;
3093 /** The ring-3 mapping of the zero page. */
3094 RTR3PTR pvZeroPgR3;
3095 /** The ring-0 mapping of the zero page. */
3096 RTR0PTR pvZeroPgR0;
3097 /** The GC mapping of the zero page. */
3098 RTRCPTR pvZeroPgRC;
3099 RTRCPTR RCPtrAlignment3;
3100 /** @}*/
3101
3102 /** @name The Invalid MMIO page.
3103 * This page is filled with 0xfeedface.
3104 * @{ */
3105 /** The host physical address of the invalid MMIO page. */
3106 RTHCPHYS HCPhysMmioPg;
3107 /** The host pysical address of the invalid MMIO page pluss all invalid
3108 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3109 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3110 RTHCPHYS HCPhysInvMmioPg;
3111 /** The ring-3 mapping of the invalid MMIO page. */
3112 RTR3PTR pvMmioPgR3;
3113#if HC_ARCH_BITS == 32
3114 RTR3PTR R3PtrAlignment4;
3115#endif
3116 /** @} */
3117
3118
3119 /** The number of handy pages. */
3120 uint32_t cHandyPages;
3121
3122 /** The number of large handy pages. */
3123 uint32_t cLargeHandyPages;
3124
3125 /**
3126 * Array of handy pages.
3127 *
3128 * This array is used in a two way communication between pgmPhysAllocPage
3129 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3130 * an intermediary.
3131 *
3132 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3133 * (The current size of 32 pages, means 128 KB of handy memory.)
3134 */
3135 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3136
3137 /**
3138 * Array of large handy pages. (currently size 1)
3139 *
3140 * This array is used in a two way communication between pgmPhysAllocLargePage
3141 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3142 * an intermediary.
3143 */
3144 GMMPAGEDESC aLargeHandyPage[1];
3145
3146 /**
3147 * Live save data.
3148 */
3149 struct
3150 {
3151 /** Per type statistics. */
3152 struct
3153 {
3154 /** The number of ready pages. */
3155 uint32_t cReadyPages;
3156 /** The number of dirty pages. */
3157 uint32_t cDirtyPages;
3158 /** The number of ready zero pages. */
3159 uint32_t cZeroPages;
3160 /** The number of write monitored pages. */
3161 uint32_t cMonitoredPages;
3162 } Rom,
3163 Mmio2,
3164 Ram;
3165 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3166 uint32_t cIgnoredPages;
3167 /** Indicates that a live save operation is active. */
3168 bool fActive;
3169 /** Padding. */
3170 bool afReserved[2];
3171 /** The next history index. */
3172 uint8_t iDirtyPagesHistory;
3173 /** History of the total amount of dirty pages. */
3174 uint32_t acDirtyPagesHistory[64];
3175 /** Short term dirty page average. */
3176 uint32_t cDirtyPagesShort;
3177 /** Long term dirty page average. */
3178 uint32_t cDirtyPagesLong;
3179 /** The number of saved pages. This is used to get some kind of estimate of the
3180 * link speed so we can decide when we're done. It is reset after the first
3181 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3182 * zero pages. */
3183 uint64_t cSavedPages;
3184 /** The nanosecond timestamp when cSavedPages was 0. */
3185 uint64_t uSaveStartNS;
3186 /** Pages per second (for statistics). */
3187 uint32_t cPagesPerSecond;
3188 uint32_t cAlignment;
3189 } LiveSave;
3190
3191 /** @name Error injection.
3192 * @{ */
3193 /** Inject handy page allocation errors pretending we're completely out of
3194 * memory. */
3195 bool volatile fErrInjHandyPages;
3196 /** Padding. */
3197 bool afReserved[3];
3198 /** @} */
3199
3200 /** @name Release Statistics
3201 * @{ */
3202 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3203 uint32_t cPrivatePages; /**< The number of private pages. */
3204 uint32_t cSharedPages; /**< The number of shared pages. */
3205 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3206 uint32_t cZeroPages; /**< The number of zero backed pages. */
3207 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3208 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3209 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3210 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3211 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3212 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3213 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3214 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3215/* uint32_t aAlignment4[1]; */
3216
3217 /** The number of times we were forced to change the hypervisor region location. */
3218 STAMCOUNTER cRelocations;
3219
3220 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
3221 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3222 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3223 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3224 /** @} */
3225
3226#ifdef VBOX_WITH_STATISTICS
3227 /** @name Statistics on the heap.
3228 * @{ */
3229 R3PTRTYPE(PGMSTATS *) pStatsR3;
3230 R0PTRTYPE(PGMSTATS *) pStatsR0;
3231 RCPTRTYPE(PGMSTATS *) pStatsRC;
3232 RTRCPTR RCPtrAlignment;
3233 /** @} */
3234#endif
3235} PGM;
3236#ifndef IN_TSTVMSTRUCTGC /* HACK */
3237AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3238AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3239AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3240AssertCompileMemberAlignment(PGM, CritSect, 8);
3241AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3242AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3243AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3244AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3245AssertCompileMemberAlignment(PGM, cRelocations, 8);
3246#endif /* !IN_TSTVMSTRUCTGC */
3247/** Pointer to the PGM instance data. */
3248typedef PGM *PPGM;
3249
3250
3251
3252typedef struct PGMCPUSTATS
3253{
3254 /* Common */
3255 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3256 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3257
3258 /* R0 only: */
3259 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3260 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3261
3262 /* RZ only: */
3263 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3264 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3265 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3266 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3267 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3268 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3269 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3270 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3271 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3272 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3273 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3274 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3275 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3276 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3277 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3278 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3279 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3280 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3281 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3282 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3283 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3284 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3285 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3286 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3287 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3288 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3289 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3290 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3291 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3292 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3293 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3294 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3295 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3296 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3297 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3298 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3299 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3300 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3301 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3302 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3303 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3304 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3305 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3306 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3307 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3308 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3309 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3310 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3311 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3312 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3313 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3314 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3315 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3316 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3317 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3318 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3319 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3320 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3321 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3322 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3323 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3324 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restorting to subset flushes. */
3325 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3326 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3327 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3328 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3329 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3330 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3331 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3332 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3333 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3334 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3335 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3336 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3337 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3338 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3339
3340 /* HC - R3 and (maybe) R0: */
3341
3342 /* RZ & R3: */
3343 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3344 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3345 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3346 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3347 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3348 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3349 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3350 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3351 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3352 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3353 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3354 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3355 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3356 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3357 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3358 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3359 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3360 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3361 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3362 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3363 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3364 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3365 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3366 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3367 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3368 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3369 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3370 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3371 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3372 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3373 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3374 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3375 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3376 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3377 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3378 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3379 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3380 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3381 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3382 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3383 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3384 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3385 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3386 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3387 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3388 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3389 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3390
3391 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3392 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3393 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3394 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3395 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3396 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3397 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3398 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3399 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3400 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3401 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3402 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3403 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3404 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3405 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3406 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3407 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3408 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3409 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3410 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3411 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3412 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3413 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3414 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3415 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3416 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3417 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3418 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3419 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3420 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3421 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3422 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3423 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3424 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3425 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3426 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3427 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3428 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3429 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3430 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3431 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3432 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3433 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3434 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3435 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3436 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3437 /** @} */
3438} PGMCPUSTATS;
3439
3440
3441/**
3442 * Converts a PGMCPU pointer into a VM pointer.
3443 * @returns Pointer to the VM structure the PGM is part of.
3444 * @param pPGM Pointer to PGMCPU instance data.
3445 */
3446#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3447
3448/**
3449 * Converts a PGMCPU pointer into a PGM pointer.
3450 * @returns Pointer to the VM structure the PGM is part of.
3451 * @param pPGM Pointer to PGMCPU instance data.
3452 */
3453#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3454
3455/**
3456 * PGMCPU Data (part of VMCPU).
3457 */
3458typedef struct PGMCPU
3459{
3460 /** Offset to the VM structure. */
3461 int32_t offVM;
3462 /** Offset to the VMCPU structure. */
3463 int32_t offVCpu;
3464 /** Offset of the PGM structure relative to VMCPU. */
3465 int32_t offPGM;
3466 uint32_t uPadding0; /**< structure size alignment. */
3467
3468#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3469 /** Automatically tracked physical memory mapping set.
3470 * Ring-0 and strict raw-mode builds. */
3471 PGMMAPSET AutoSet;
3472#endif
3473
3474 /** A20 gate mask.
3475 * Our current approach to A20 emulation is to let REM do it and don't bother
3476 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3477 * But whould need arrise, we'll subject physical addresses to this mask. */
3478 RTGCPHYS GCPhysA20Mask;
3479 /** A20 gate state - boolean! */
3480 bool fA20Enabled;
3481 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3482 bool fNoExecuteEnabled;
3483 /** Unused bits. */
3484 bool afUnused[2];
3485
3486 /** What needs syncing (PGM_SYNC_*).
3487 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3488 * PGMFlushTLB, and PGMR3Load. */
3489 RTUINT fSyncFlags;
3490
3491 /** The shadow paging mode. */
3492 PGMMODE enmShadowMode;
3493 /** The guest paging mode. */
3494 PGMMODE enmGuestMode;
3495
3496 /** The current physical address representing in the guest CR3 register. */
3497 RTGCPHYS GCPhysCR3;
3498
3499 /** @name 32-bit Guest Paging.
3500 * @{ */
3501 /** The guest's page directory, R3 pointer. */
3502 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3503#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3504 /** The guest's page directory, R0 pointer. */
3505 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3506#endif
3507 /** The guest's page directory, static RC mapping. */
3508 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3509 /** Mask containing the MBZ bits of a big page PDE. */
3510 uint32_t fGst32BitMbzBigPdeMask;
3511 /** Set if the page size extension (PSE) is enabled. */
3512 bool fGst32BitPageSizeExtension;
3513 /** Alignment padding. */
3514 bool afAlignment2[3];
3515 /** @} */
3516
3517 /** @name PAE Guest Paging.
3518 * @{ */
3519 /** The guest's page directory pointer table, static RC mapping. */
3520 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3521 /** The guest's page directory pointer table, R3 pointer. */
3522 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3523#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3524 /** The guest's page directory pointer table, R0 pointer. */
3525 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3526#endif
3527
3528 /** The guest's page directories, R3 pointers.
3529 * These are individual pointers and don't have to be adjecent.
3530 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3531 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3532 /** The guest's page directories, R0 pointers.
3533 * Same restrictions as apGstPaePDsR3. */
3534#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3535 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3536#endif
3537 /** The guest's page directories, static GC mapping.
3538 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3539 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3540 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3541 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3542 RTGCPHYS aGCPhysGstPaePDs[4];
3543 /** The physical addresses of the monitored guest page directories (PAE). */
3544 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3545 /** Mask containing the MBZ PTE bits. */
3546 uint64_t fGstPaeMbzPteMask;
3547 /** Mask containing the MBZ PDE bits. */
3548 uint64_t fGstPaeMbzPdeMask;
3549 /** Mask containing the MBZ big page PDE bits. */
3550 uint64_t fGstPaeMbzBigPdeMask;
3551 /** Mask containing the MBZ PDPE bits. */
3552 uint64_t fGstPaeMbzPdpeMask;
3553 /** @} */
3554
3555 /** @name AMD64 Guest Paging.
3556 * @{ */
3557 /** The guest's page directory pointer table, R3 pointer. */
3558 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3559#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3560 /** The guest's page directory pointer table, R0 pointer. */
3561 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3562#else
3563 RTR0PTR alignment6b; /**< alignment equalizer. */
3564#endif
3565 /** Mask containing the MBZ PTE bits. */
3566 uint64_t fGstAmd64MbzPteMask;
3567 /** Mask containing the MBZ PDE bits. */
3568 uint64_t fGstAmd64MbzPdeMask;
3569 /** Mask containing the MBZ big page PDE bits. */
3570 uint64_t fGstAmd64MbzBigPdeMask;
3571 /** Mask containing the MBZ PDPE bits. */
3572 uint64_t fGstAmd64MbzPdpeMask;
3573 /** Mask containing the MBZ big page PDPE bits. */
3574 uint64_t fGstAmd64MbzBigPdpeMask;
3575 /** Mask containing the MBZ PML4E bits. */
3576 uint64_t fGstAmd64MbzPml4eMask;
3577 /** @} */
3578
3579 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3580 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3581 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3582 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3583 /** Pointer to the page of the current active CR3 - RC Ptr. */
3584 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3585 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3586 uint32_t iShwUser;
3587 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3588 uint32_t iShwUserTable;
3589# if HC_ARCH_BITS == 64
3590 RTRCPTR alignment6; /**< structure size alignment. */
3591# endif
3592 /** @} */
3593
3594 /** @name Function pointers for Shadow paging.
3595 * @{
3596 */
3597 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3598 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3599 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3600 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3601
3602 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3603 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3604
3605 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3606 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3607
3608 /** @} */
3609
3610 /** @name Function pointers for Guest paging.
3611 * @{
3612 */
3613 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3614 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3615 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3616 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3617 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3618 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3619 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3620 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3621#if HC_ARCH_BITS == 64
3622 RTRCPTR alignment3; /**< structure size alignment. */
3623#endif
3624
3625 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3626 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3627 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3628 /** @} */
3629
3630 /** @name Function pointers for Both Shadow and Guest paging.
3631 * @{
3632 */
3633 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3634 /* no pfnR3BthTrap0eHandler */
3635 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3636 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3637 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3638 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3639 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3640 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3641 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3642
3643 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3644 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3645 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3646 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3647 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3648 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3649 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3650 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3651
3652 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3653 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3654 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3655 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3656 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3657 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3658 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3659 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3660#if 0
3661 RTRCPTR alignment2; /**< structure size alignment. */
3662#endif
3663 /** @} */
3664
3665 /** For saving stack space, the disassembler state is allocated here instead of
3666 * on the stack.
3667 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3668 union
3669 {
3670 /** The disassembler scratch space. */
3671 DISCPUSTATE DisState;
3672 /** Padding. */
3673 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3674 };
3675
3676 /** Count the number of pgm pool access handler calls. */
3677 uint64_t cPoolAccessHandler;
3678
3679 /** @name Release Statistics
3680 * @{ */
3681 /** The number of times the guest has switched mode since last reset or statistics reset. */
3682 STAMCOUNTER cGuestModeChanges;
3683 /** @} */
3684
3685#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3686 /** @name Statistics
3687 * @{ */
3688 /** RC: Pointer to the statistics. */
3689 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3690 /** RC: Which statistic this \#PF should be attributed to. */
3691 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3692 /** R0: Pointer to the statistics. */
3693 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3694 /** R0: Which statistic this \#PF should be attributed to. */
3695 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3696 /** R3: Pointer to the statistics. */
3697 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3698 /** Alignment padding. */
3699 RTR3PTR pPaddingR3;
3700 /** @} */
3701#endif /* VBOX_WITH_STATISTICS */
3702} PGMCPU;
3703/** Pointer to the per-cpu PGM data. */
3704typedef PGMCPU *PPGMCPU;
3705
3706
3707/** @name PGM::fSyncFlags Flags
3708 * @{
3709 */
3710/** Updates the virtual access handler state bit in PGMPAGE. */
3711#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3712/** Always sync CR3. */
3713#define PGM_SYNC_ALWAYS RT_BIT(1)
3714/** Check monitoring on next CR3 (re)load and invalidate page.
3715 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3716#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3717/** Check guest mapping in SyncCR3. */
3718#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3719/** Clear the page pool (a light weight flush). */
3720#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3721#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3722/** @} */
3723
3724
3725RT_C_DECLS_BEGIN
3726
3727int pgmLock(PVM pVM);
3728void pgmUnlock(PVM pVM);
3729
3730int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3731int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3732int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3733PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3734int pgmMapResolveConflicts(PVM pVM);
3735DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3736
3737void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3738bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3739void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3740int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3741DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3742#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3743void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3744#else
3745# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3746#endif
3747DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3748int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3749
3750int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3751int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3752int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3753int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3754int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3755void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3756int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3757int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3758int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3759int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3760int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3761int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3762int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3763VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3764VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3765int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3766
3767#ifdef IN_RING3
3768void pgmR3PhysRelinkRamRanges(PVM pVM);
3769int pgmR3PhysRamPreAllocate(PVM pVM);
3770int pgmR3PhysRamReset(PVM pVM);
3771int pgmR3PhysRomReset(PVM pVM);
3772int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3773int pgmR3PhysRamTerm(PVM pVM);
3774void pgmR3PhysRomTerm(PVM pVM);
3775
3776int pgmR3PoolInit(PVM pVM);
3777void pgmR3PoolRelocate(PVM pVM);
3778void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3779void pgmR3PoolReset(PVM pVM);
3780void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3781DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3782
3783#endif /* IN_RING3 */
3784#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || IN_RC
3785int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3786int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3787# ifdef LOG_ENABLED
3788void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3789# else
3790void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3791# endif
3792#endif
3793int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3794
3795DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3796{
3797 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3798}
3799
3800void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3801void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3802int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3803void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3804PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3805int pgmPoolSyncCR3(PVMCPU pVCpu);
3806bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3807int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3808void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3809void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3810DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3811{
3812 return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3813}
3814
3815uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3816void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3817void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3818int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3819void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3820
3821void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3822void pgmPoolResetDirtyPages(PVM pVM);
3823
3824int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3825int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3826
3827void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3828void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3829int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3830int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3831
3832int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3833int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3834
3835int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3836int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3837int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3838int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3839
3840# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3841DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3842DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3843# endif
3844
3845RT_C_DECLS_END
3846
3847/** @} */
3848
3849#endif
3850
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