PGMInternal.h@ 31834

Last change on this file since 31834 was 31834, checked in by vboxsync, 14 years ago
PGMRZDynMap.cpp: Dropped the PGMMAPSET_MAX_FILL checks and instead make sure we can optimize the better.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 173.5 KB

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1	/* $Id: PGMInternal.h 31834 2010-08-21 00:52:39Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/dbg.h>
25	#include <VBox/stam.h>
26	#include <VBox/param.h>
27	#include <VBox/vmm.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdmcritsect.h>
30	#include <VBox/pdmapi.h>
31	#include <VBox/dis.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/log.h>
34	#include <VBox/gmm.h>
35	#include <VBox/hwaccm.h>
36	#include <VBox/hwacc_vmx.h>
37	#include <include/internal/pgm.h>
38	#include <iprt/asm.h>
39	#include <iprt/assert.h>
40	#include <iprt/avl.h>
41	#include <iprt/critsect.h>
42	#include <iprt/sha.h>
43
44
45
46	/** @defgroup grp_pgm_int Internals
47	* @ingroup grp_pgm
48	* @internal
49	* @{
50	*/
51
52
53	/** @name PGM Compile Time Config
54	* @{
55	*/
56
57	/**
58	* Indicates that there are no guest mappings to care about.
59	* Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60	*/
61	#if defined(IN_RING0) \|\| !defined(VBOX_WITH_RAW_MODE)
62	# define PGM_WITHOUT_MAPPINGS
63	#endif
64
65	/**
66	* Check and skip global PDEs for non-global flushes
67	*/
68	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70	/**
71	* Optimization for PAE page tables that are modified often
72	*/
73	//#if 0 /* disabled again while debugging */
74	#ifndef IN_RC
75	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76	#endif
77	//#endif
78
79	/**
80	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
81	*/
82	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83	# define PGM_WITH_LARGE_PAGES
84	#endif
85
86	/**
87	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88	* VMX_EXIT_EPT_MISCONFIG.
89	*/
90	#if 0 /* ! remember to disable before committing ! XXX TODO */
91	# define PGM_WITH_MMIO_OPTIMIZATIONS
92	#endif
93
94	/**
95	* Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96	*/
97	#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98	# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99	#endif
100
101	/**
102	* Sync N pages instead of a whole page table
103	*/
104	#define PGM_SYNC_N_PAGES
105
106	/**
107	* Number of pages to sync during a page fault
108	*
109	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111	*
112	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113	* world switch overhead, so let's sync more.
114	*/
115	# ifdef IN_RING0
116	/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118	* but ~5% fewer faults.
119	*/
120	# define PGM_SYNC_NR_PAGES 32
121	#else
122	# define PGM_SYNC_NR_PAGES 8
123	#endif
124
125	/**
126	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127	*/
128	#define PGM_MAX_PHYSCACHE_ENTRIES 64
129	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132	/** @def PGMPOOL_CFG_MAX_GROW
133	* The maximum number of pages to add to the pool in one go.
134	*/
135	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
139	*/
140	#ifdef VBOX_STRICT
141	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142	#endif
143
144	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145	* Enables the experimental lazy page allocation code. */
146	/#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
147
148	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149	* Enables real write monitoring of pages, i.e. mapping them read-only and
150	* only making them writable when getting a write access #PF. */
151	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153	/** @} */
154
155
156	/** @name PDPT and PML4 flags.
157	* These are placed in the three bits available for system programs in
158	* the PDPT and PML4 entries.
159	* @{ */
160	/** The entry is a permanent one and it's must always be present.
161	* Never free such an entry. */
162	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163	/** Mapping (hypervisor allocated pagetable). */
164	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165	/** @} */
166
167	/** @name Page directory flags.
168	* These are placed in the three bits available for system programs in
169	* the page directory entries.
170	* @{ */
171	/** Mapping (hypervisor allocated pagetable). */
172	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173	/** Made read-only to facilitate dirty bit tracking. */
174	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175	/** @} */
176
177	/** @name Page flags.
178	* These are placed in the three bits available for system programs in
179	* the page entries.
180	* @{ */
181	/** Made read-only to facilitate dirty bit tracking. */
182	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185	/** Scanned and approved by CSAM (tm).
186	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
187	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
188	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189	#endif
190
191	/** @} */
192
193	/** @name Defines used to indicate the shadow and guest paging in the templates.
194	* @{ */
195	#define PGM_TYPE_REAL 1
196	#define PGM_TYPE_PROT 2
197	#define PGM_TYPE_32BIT 3
198	#define PGM_TYPE_PAE 4
199	#define PGM_TYPE_AMD64 5
200	#define PGM_TYPE_NESTED 6
201	#define PGM_TYPE_EPT 7
202	#define PGM_TYPE_MAX PGM_TYPE_EPT
203	/** @} */
204
205	/** Macro for checking if the guest is using paging.
206	* @param uGstType PGM_TYPE_*
207	* @param uShwType PGM_TYPE_*
208	* @remark ASSUMES certain order of the PGM_TYPE_* values.
209	*/
210	#define PGM_WITH_PAGING(uGstType, uShwType) \
211	( (uGstType) >= PGM_TYPE_32BIT \
212	&& (uShwType) != PGM_TYPE_NESTED \
213	&& (uShwType) != PGM_TYPE_EPT)
214
215	/** Macro for checking if the guest supports the NX bit.
216	* @param uGstType PGM_TYPE_*
217	* @param uShwType PGM_TYPE_*
218	* @remark ASSUMES certain order of the PGM_TYPE_* values.
219	*/
220	#define PGM_WITH_NX(uGstType, uShwType) \
221	( (uGstType) >= PGM_TYPE_PAE \
222	&& (uShwType) != PGM_TYPE_NESTED \
223	&& (uShwType) != PGM_TYPE_EPT)
224
225
226	/** @def PGM_HCPHYS_2_PTR
227	* Maps a HC physical page pool address to a virtual address.
228	*
229	* @returns VBox status code.
230	* @param pVM The VM handle.
231	* @param pVCpu The current CPU.
232	* @param HCPhys The HC physical address to map to a virtual one.
233	* @param ppv Where to store the virtual address. No need to cast
234	* this.
235	*
236	* @remark Use with care as we don't have so much dynamic mapping space in
237	* ring-0 on 32-bit darwin and in RC.
238	* @remark There is no need to assert on the result.
239	*/
240	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
241	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242	pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243	#else
244	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246	#endif
247
248	/** @def PGM_GCPHYS_2_PTR_V2
249	* Maps a GC physical page address to a virtual address.
250	*
251	* @returns VBox status code.
252	* @param pVM The VM handle.
253	* @param pVCpu The current CPU.
254	* @param GCPhys The GC physical address to map to a virtual one.
255	* @param ppv Where to store the virtual address. No need to cast this.
256	*
257	* @remark Use with care as we don't have so much dynamic mapping space in
258	* ring-0 on 32-bit darwin and in RC.
259	* @remark There is no need to assert on the result.
260	*/
261	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
262	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264	#else
265	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267	#endif
268
269	/** @def PGM_GCPHYS_2_PTR
270	* Maps a GC physical page address to a virtual address.
271	*
272	* @returns VBox status code.
273	* @param pVM The VM handle.
274	* @param GCPhys The GC physical address to map to a virtual one.
275	* @param ppv Where to store the virtual address. No need to cast this.
276	*
277	* @remark Use with care as we don't have so much dynamic mapping space in
278	* ring-0 on 32-bit darwin and in RC.
279	* @remark There is no need to assert on the result.
280	*/
281	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284	* Maps a GC physical page address to a virtual address.
285	*
286	* @returns VBox status code.
287	* @param pVCpu The current CPU.
288	* @param GCPhys The GC physical address to map to a virtual one.
289	* @param ppv Where to store the virtual address. No need to cast this.
290	*
291	* @remark Use with care as we don't have so much dynamic mapping space in
292	* ring-0 on 32-bit darwin and in RC.
293	* @remark There is no need to assert on the result.
294	*/
295	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297	/** @def PGM_GCPHYS_2_PTR_EX
298	* Maps a unaligned GC physical page address to a virtual address.
299	*
300	* @returns VBox status code.
301	* @param pVM The VM handle.
302	* @param GCPhys The GC physical address to map to a virtual one.
303	* @param ppv Where to store the virtual address. No need to cast this.
304	*
305	* @remark Use with care as we don't have so much dynamic mapping space in
306	* ring-0 on 32-bit darwin and in RC.
307	* @remark There is no need to assert on the result.
308	*/
309	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312	#else
313	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315	#endif
316
317	/** @def PGM_DYNMAP_UNUSED_HINT
318	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319	* is no longer used.
320	*
321	* For best effect only apply this to the page that was mapped most recently.
322	*
323	* @param pVCpu The current CPU.
324	* @param pPage The pool page.
325	*/
326	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327	# ifdef LOG_ENABLED
328	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329	# else
330	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331	# endif
332	#else
333	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334	#endif
335
336	/** @def PGM_DYNMAP_UNUSED_HINT_VM
337	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338	* is no longer used.
339	*
340	* For best effect only apply this to the page that was mapped most recently.
341	*
342	* @param pVM The VM handle.
343	* @param pPage The pool page.
344	*/
345	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348	/** @def PGM_INVL_PG
349	* Invalidates a page.
350	*
351	* @param pVCpu The VMCPU handle.
352	* @param GCVirt The virtual address of the page to invalidate.
353	*/
354	#ifdef IN_RC
355	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356	#elif defined(IN_RING0)
357	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358	#else
359	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360	#endif
361
362	/** @def PGM_INVL_PG_ALL_VCPU
363	* Invalidates a page on all VCPUs
364	*
365	* @param pVM The VM handle.
366	* @param GCVirt The virtual address of the page to invalidate.
367	*/
368	#ifdef IN_RC
369	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370	#elif defined(IN_RING0)
371	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372	#else
373	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374	#endif
375
376	/** @def PGM_INVL_BIG_PG
377	* Invalidates a 4MB page directory entry.
378	*
379	* @param pVCpu The VMCPU handle.
380	* @param GCVirt The virtual address within the page directory to invalidate.
381	*/
382	#ifdef IN_RC
383	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384	#elif defined(IN_RING0)
385	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386	#else
387	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388	#endif
389
390	/** @def PGM_INVL_VCPU_TLBS()
391	* Invalidates the TLBs of the specified VCPU
392	*
393	* @param pVCpu The VMCPU handle.
394	*/
395	#ifdef IN_RC
396	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397	#elif defined(IN_RING0)
398	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399	#else
400	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401	#endif
402
403	/** @def PGM_INVL_ALL_VCPU_TLBS()
404	* Invalidates the TLBs of all VCPUs
405	*
406	* @param pVM The VM handle.
407	*/
408	#ifdef IN_RC
409	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410	#elif defined(IN_RING0)
411	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412	#else
413	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414	#endif
415
416
417	/** @name Safer Shadow PAE PT/PTE
418	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419	* present.
420	*
421	* @{
422	*/
423	#if 0
424	/**
425	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
426	* invalid entries for present.
427	* @sa X86PTEPAE.
428	*/
429	typedef union PGMSHWPTEPAE
430	{
431	/** Unsigned integer view */
432	X86PGPAEUINT uCareful;
433	/* Not other views. */
434	} PGMSHWPTEPAE;
435
436	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
443	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
446	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
452
453	/**
454	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
455	* invalid entries for present.
456	* @sa X86PTPAE.
457	*/
458	typedef struct PGMSHWPTPAE
459	{
460	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461	} PGMSHWPTPAE;
462
463	#else
464	typedef X86PTEPAE PGMSHWPTEPAE;
465	typedef X86PTPAE PGMSHWPTPAE;
466	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
473	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
476	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
482
483	#endif
484
485	/** Pointer to a shadow PAE PTE. */
486	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487	/** Pointer to a const shadow PAE PTE. */
488	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490	/** Pointer to a shadow PAE page table. */
491	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492	/** Pointer to a const shadow PAE page table. */
493	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494	/** @} */
495
496
497	/** Size of the GCPtrConflict array in PGMMAPPING.
498	* @remarks Must be a power of two. */
499	#define PGMMAPPING_CONFLICT_MAX 8
500
501	/**
502	* Structure for tracking GC Mappings.
503	*
504	* This structure is used by linked list in both GC and HC.
505	*/
506	typedef struct PGMMAPPING
507	{
508	/** Pointer to next entry. */
509	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510	/** Pointer to next entry. */
511	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512	/** Pointer to next entry. */
513	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514	/** Indicate whether this entry is finalized. */
515	bool fFinalized;
516	/** Start Virtual address. */
517	RTGCPTR GCPtr;
518	/** Last Virtual address (inclusive). */
519	RTGCPTR GCPtrLast;
520	/** Range size (bytes). */
521	RTGCPTR cb;
522	/** Pointer to relocation callback function. */
523	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524	/** User argument to the callback. */
525	R3PTRTYPE(void *) pvUser;
526	/** Mapping description / name. For easing debugging. */
527	R3PTRTYPE(const char *) pszDesc;
528	/** Last 8 addresses that caused conflicts. */
529	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530	/** Number of conflicts for this hypervisor mapping. */
531	uint32_t cConflicts;
532	/** Number of page tables. */
533	uint32_t cPTs;
534
535	/** Array of page table mapping data. Each entry
536	* describes one page table. The array can be longer
537	* than the declared length.
538	*/
539	struct
540	{
541	/** The HC physical address of the page table. */
542	RTHCPHYS HCPhysPT;
543	/** The HC physical address of the first PAE page table. */
544	RTHCPHYS HCPhysPaePT0;
545	/** The HC physical address of the second PAE page table. */
546	RTHCPHYS HCPhysPaePT1;
547	/** The HC virtual address of the 32-bit page table. */
548	R3PTRTYPE(PX86PT) pPTR3;
549	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551	/** The RC virtual address of the 32-bit page table. */
552	RCPTRTYPE(PX86PT) pPTRC;
553	/** The RC virtual address of the two PAE page table. */
554	RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555	/** The R0 virtual address of the 32-bit page table. */
556	R0PTRTYPE(PX86PT) pPTR0;
557	/** The R0 virtual address of the two PAE page table. */
558	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559	} aPTs[1];
560	} PGMMAPPING;
561	/** Pointer to structure for tracking GC Mappings. */
562	typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565	/**
566	* Physical page access handler structure.
567	*
568	* This is used to keep track of physical address ranges
569	* which are being monitored in some kind of way.
570	*/
571	typedef struct PGMPHYSHANDLER
572	{
573	AVLROGCPHYSNODECORE Core;
574	/** Access type. */
575	PGMPHYSHANDLERTYPE enmType;
576	/** Number of pages to update. */
577	uint32_t cPages;
578	/** Pointer to R3 callback function. */
579	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
580	/** User argument for R3 handlers. */
581	R3PTRTYPE(void *) pvUserR3;
582	/** Pointer to R0 callback function. */
583	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
584	/** User argument for R0 handlers. */
585	R0PTRTYPE(void *) pvUserR0;
586	/** Pointer to RC callback function. */
587	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
588	/** User argument for RC handlers. */
589	RCPTRTYPE(void *) pvUserRC;
590	/** Description / Name. For easing debugging. */
591	R3PTRTYPE(const char *) pszDesc;
592	#ifdef VBOX_WITH_STATISTICS
593	/** Profiling of this handler. */
594	STAMPROFILE Stat;
595	#endif
596	} PGMPHYSHANDLER;
597	/** Pointer to a physical page access handler structure. */
598	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
599
600
601	/**
602	* Cache node for the physical addresses covered by a virtual handler.
603	*/
604	typedef struct PGMPHYS2VIRTHANDLER
605	{
606	/** Core node for the tree based on physical ranges. */
607	AVLROGCPHYSNODECORE Core;
608	/** Offset from this struct to the PGMVIRTHANDLER structure. */
609	int32_t offVirtHandler;
610	/** Offset of the next alias relative to this one.
611	* Bit 0 is used for indicating whether we're in the tree.
612	* Bit 1 is used for indicating that we're the head node.
613	*/
614	int32_t offNextAlias;
615	} PGMPHYS2VIRTHANDLER;
616	/** Pointer to a phys to virtual handler structure. */
617	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
618
619	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
620	* node is in the tree. */
621	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
622	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
623	* node is in the head of an alias chain.
624	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
625	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
626	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
627	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
628
629
630	/**
631	* Virtual page access handler structure.
632	*
633	* This is used to keep track of virtual address ranges
634	* which are being monitored in some kind of way.
635	*/
636	typedef struct PGMVIRTHANDLER
637	{
638	/** Core node for the tree based on virtual ranges. */
639	AVLROGCPTRNODECORE Core;
640	/** Size of the range (in bytes). */
641	RTGCPTR cb;
642	/** Number of cache pages. */
643	uint32_t cPages;
644	/** Access type. */
645	PGMVIRTHANDLERTYPE enmType;
646	/** Pointer to the RC callback function. */
647	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
648	#if HC_ARCH_BITS == 64
649	RTRCPTR padding;
650	#endif
651	/** Pointer to the R3 callback function for invalidation. */
652	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
653	/** Pointer to the R3 callback function. */
654	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
655	/** Description / Name. For easing debugging. */
656	R3PTRTYPE(const char *) pszDesc;
657	#ifdef VBOX_WITH_STATISTICS
658	/** Profiling of this handler. */
659	STAMPROFILE Stat;
660	#endif
661	/** Array of cached physical addresses for the monitored ranged. */
662	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
663	} PGMVIRTHANDLER;
664	/** Pointer to a virtual page access handler structure. */
665	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
666
667
668	/**
669	* Page type.
670	*
671	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
672	* @remarks This is used in the saved state, so changes to it requires bumping
673	* the saved state version.
674	* @todo So, convert to \#defines!
675	*/
676	typedef enum PGMPAGETYPE
677	{
678	/** The usual invalid zero entry. */
679	PGMPAGETYPE_INVALID = 0,
680	/** RAM page. (RWX) */
681	PGMPAGETYPE_RAM,
682	/** MMIO2 page. (RWX) */
683	PGMPAGETYPE_MMIO2,
684	/** MMIO2 page aliased over an MMIO page. (RWX)
685	* See PGMHandlerPhysicalPageAlias(). */
686	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
687	/** Shadowed ROM. (RWX) */
688	PGMPAGETYPE_ROM_SHADOW,
689	/** ROM page. (R-X) */
690	PGMPAGETYPE_ROM,
691	/** MMIO page. (---) */
692	PGMPAGETYPE_MMIO,
693	/** End of valid entries. */
694	PGMPAGETYPE_END
695	} PGMPAGETYPE;
696	AssertCompile(PGMPAGETYPE_END <= 7);
697
698	/** @name Page type predicates.
699	* @{ */
700	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
701	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
702	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
703	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
704	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
705	/** @} */
706
707
708	/**
709	* A Physical Guest Page tracking structure.
710	*
711	* The format of this structure is complicated because we have to fit a lot
712	* of information into as few bits as possible. The format is also subject
713	* to change (there is one comming up soon). Which means that for we'll be
714	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
715	* accesses to the structure.
716	*/
717	typedef struct PGMPAGE
718	{
719	/** The physical address and the Page ID. */
720	RTHCPHYS HCPhysAndPageID;
721	/** Combination of:
722	* - [0-7]: u2HandlerPhysStateY - the physical handler state
723	* (PGM_PAGE_HNDL_PHYS_STATE_*).
724	* - [8-9]: u2HandlerVirtStateY - the virtual handler state
725	* (PGM_PAGE_HNDL_VIRT_STATE_*).
726	* - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
727	* - [15]: fWrittenToY - flag indicating that a write monitored page was
728	* written to when set.
729	* - [10-13]: 4 unused bits.
730	* @remarks Warning! All accesses to the bits are hardcoded.
731	*
732	* @todo Change this to a union with both bitfields, u8 and u accessors.
733	* That'll help deal with some of the hardcoded accesses.
734	*
735	* @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
736	* will make it possible to turn some of the 16-bit accesses into
737	* 32-bit ones, which may be efficient (stalls).
738	*/
739	RTUINT16U u16MiscY;
740	/** The page state.
741	* Only 3 bits are really needed for this. */
742	uint16_t uStateY : 3;
743	/** The page type (PGMPAGETYPE).
744	* Only 3 bits are really needed for this. */
745	uint16_t uTypeY : 3;
746	/** PTE index for usage tracking (page pool). */
747	uint16_t uPteIdx : 10;
748	/** Usage tracking (page pool). */
749	uint16_t u16TrackingY;
750	/** The number of read locks on this page. */
751	uint8_t cReadLocksY;
752	/** The number of write locks on this page. */
753	uint8_t cWriteLocksY;
754	} PGMPAGE;
755	AssertCompileSize(PGMPAGE, 16);
756	/** Pointer to a physical guest page. */
757	typedef PGMPAGE *PPGMPAGE;
758	/** Pointer to a const physical guest page. */
759	typedef const PGMPAGE *PCPGMPAGE;
760	/** Pointer to a physical guest page pointer. */
761	typedef PPGMPAGE *PPPGMPAGE;
762
763
764	/**
765	* Clears the page structure.
766	* @param pPage Pointer to the physical guest page tracking structure.
767	*/
768	#define PGM_PAGE_CLEAR(pPage) \
769	do { \
770	(pPage)->HCPhysAndPageID = 0; \
771	(pPage)->uStateY = 0; \
772	(pPage)->uTypeY = 0; \
773	(pPage)->uPteIdx = 0; \
774	(pPage)->u16MiscY.u = 0; \
775	(pPage)->u16TrackingY = 0; \
776	(pPage)->cReadLocksY = 0; \
777	(pPage)->cWriteLocksY = 0; \
778	} while (0)
779
780	/**
781	* Initializes the page structure.
782	* @param pPage Pointer to the physical guest page tracking structure.
783	*/
784	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
785	do { \
786	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
787	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
788	(pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) \| ((_idPage) & UINT32_C(0x0fffffff)); \
789	(pPage)->uStateY = (_uState); \
790	(pPage)->uTypeY = (_uType); \
791	(pPage)->uPteIdx = 0; \
792	(pPage)->u16MiscY.u = 0; \
793	(pPage)->u16TrackingY = 0; \
794	(pPage)->cReadLocksY = 0; \
795	(pPage)->cWriteLocksY = 0; \
796	} while (0)
797
798	/**
799	* Initializes the page structure of a ZERO page.
800	* @param pPage Pointer to the physical guest page tracking structure.
801	* @param pVM The VM handle (for getting the zero page address).
802	* @param uType The page type (PGMPAGETYPE).
803	*/
804	#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
805	PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
806
807
808	/** @name The Page state, PGMPAGE::uStateY.
809	* @{ */
810	/** The zero page.
811	* This is a per-VM page that's never ever mapped writable. */
812	#define PGM_PAGE_STATE_ZERO 0
813	/** A allocated page.
814	* This is a per-VM page allocated from the page pool (or wherever
815	* we get MMIO2 pages from if the type is MMIO2).
816	*/
817	#define PGM_PAGE_STATE_ALLOCATED 1
818	/** A allocated page that's being monitored for writes.
819	* The shadow page table mappings are read-only. When a write occurs, the
820	* fWrittenTo member is set, the page remapped as read-write and the state
821	* moved back to allocated. */
822	#define PGM_PAGE_STATE_WRITE_MONITORED 2
823	/** The page is shared, aka. copy-on-write.
824	* This is a page that's shared with other VMs. */
825	#define PGM_PAGE_STATE_SHARED 3
826	/** The page is ballooned, so no longer available for this VM. */
827	#define PGM_PAGE_STATE_BALLOONED 4
828	/** @} */
829
830
831	/**
832	* Gets the page state.
833	* @returns page state (PGM_PAGE_STATE_*).
834	* @param pPage Pointer to the physical guest page tracking structure.
835	*/
836	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
837
838	/**
839	* Sets the page state.
840	* @param pPage Pointer to the physical guest page tracking structure.
841	* @param _uState The new page state.
842	*/
843	#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
844
845
846	/**
847	* Gets the host physical address of the guest page.
848	* @returns host physical address (RTHCPHYS).
849	* @param pPage Pointer to the physical guest page tracking structure.
850	*/
851	#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
852
853	/**
854	* Sets the host physical address of the guest page.
855	* @param pPage Pointer to the physical guest page tracking structure.
856	* @param _HCPhys The new host physical address.
857	*/
858	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
859	do { \
860	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
861	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
862	(pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
863	\| (SetHCPhysTmp << (28-12)); \
864	} while (0)
865
866	/**
867	* Get the Page ID.
868	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
869	* @param pPage Pointer to the physical guest page tracking structure.
870	*/
871	#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
872
873	/**
874	* Sets the Page ID.
875	* @param pPage Pointer to the physical guest page tracking structure.
876	*/
877	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
878	do { \
879	(pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
880	\| ((_idPage) & UINT32_C(0x0fffffff)); \
881	} while (0)
882
883	/**
884	* Get the Chunk ID.
885	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
886	* @param pPage Pointer to the physical guest page tracking structure.
887	*/
888	#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
889
890	/**
891	* Get the index of the page within the allocation chunk.
892	* @returns The page index.
893	* @param pPage Pointer to the physical guest page tracking structure.
894	*/
895	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
896
897	/**
898	* Gets the page type.
899	* @returns The page type.
900	* @param pPage Pointer to the physical guest page tracking structure.
901	*/
902	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
903
904	/**
905	* Sets the page type.
906	* @param pPage Pointer to the physical guest page tracking structure.
907	* @param _enmType The new page type (PGMPAGETYPE).
908	*/
909	#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
910
911	/**
912	* Gets the page table index
913	* @returns The page table index.
914	* @param pPage Pointer to the physical guest page tracking structure.
915	*/
916	#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
917
918	/**
919	* Sets the page table index
920	* @param pPage Pointer to the physical guest page tracking structure.
921	* @param iPte New page table index.
922	*/
923	#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
924
925	/**
926	* Checks if the page is marked for MMIO.
927	* @returns true/false.
928	* @param pPage Pointer to the physical guest page tracking structure.
929	*/
930	#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
931
932	/**
933	* Checks if the page is backed by the ZERO page.
934	* @returns true/false.
935	* @param pPage Pointer to the physical guest page tracking structure.
936	*/
937	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
938
939	/**
940	* Checks if the page is backed by a SHARED page.
941	* @returns true/false.
942	* @param pPage Pointer to the physical guest page tracking structure.
943	*/
944	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
945
946	/**
947	* Checks if the page is ballooned.
948	* @returns true/false.
949	* @param pPage Pointer to the physical guest page tracking structure.
950	*/
951	#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
952
953	/**
954	* Marks the page as written to (for GMM change monitoring).
955	* @param pPage Pointer to the physical guest page tracking structure.
956	*/
957	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] \|= UINT8_C(0x80); } while (0)
958
959	/**
960	* Clears the written-to indicator.
961	* @param pPage Pointer to the physical guest page tracking structure.
962	*/
963	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
964
965	/**
966	* Checks if the page was marked as written-to.
967	* @returns true/false.
968	* @param pPage Pointer to the physical guest page tracking structure.
969	*/
970	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
971
972	/** @name PT usage values (PGMPAGE::u2PDEType).
973	*
974	* @{ */
975	/** Either as a PT or PDE. */
976	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
977	/** Must use a page table to map the range. */
978	#define PGM_PAGE_PDE_TYPE_PT 1
979	/** Can use a page directory entry to map the continous range. */
980	#define PGM_PAGE_PDE_TYPE_PDE 2
981	/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
982	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
983	/** @} */
984
985	/**
986	* Set the PDE type of the page
987	* @param pPage Pointer to the physical guest page tracking structure.
988	* @param uType PGM_PAGE_PDE_TYPE_*
989	*/
990	#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
991	do { \
992	(pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
993	\| (((uType) & UINT8_C(0x03)) << 5); \
994	} while (0)
995
996	/**
997	* Checks if the page was marked being part of a large page
998	* @returns true/false.
999	* @param pPage Pointer to the physical guest page tracking structure.
1000	*/
1001	#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
1002
1003	/** Enabled optimized access handler tests.
1004	* These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
1005	* layout. When enabled, the compiler should normally generate more compact
1006	* code.
1007	*/
1008	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1009
1010	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1011	*
1012	* @remarks The values are assigned in order of priority, so we can calculate
1013	* the correct state for a page with different handlers installed.
1014	* @{ */
1015	/** No handler installed. */
1016	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1017	/** Monitoring is temporarily disabled. */
1018	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1019	/** Write access is monitored. */
1020	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1021	/** All access is monitored. */
1022	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1023	/** @} */
1024
1025	/**
1026	* Gets the physical access handler state of a page.
1027	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1028	* @param pPage Pointer to the physical guest page tracking structure.
1029	*/
1030	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
1031	( (pPage)->u16MiscY.au8[0] )
1032
1033	/**
1034	* Sets the physical access handler state of a page.
1035	* @param pPage Pointer to the physical guest page tracking structure.
1036	* @param _uState The new state value.
1037	*/
1038	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
1039	do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
1040
1041	/**
1042	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
1043	* @returns true/false
1044	* @param pPage Pointer to the physical guest page tracking structure.
1045	*/
1046	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
1047	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1048
1049	/**
1050	* Checks if the page has any active physical access handlers.
1051	* @returns true/false
1052	* @param pPage Pointer to the physical guest page tracking structure.
1053	*/
1054	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
1055	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1056
1057
1058	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1059	*
1060	* @remarks The values are assigned in order of priority, so we can calculate
1061	* the correct state for a page with different handlers installed.
1062	* @{ */
1063	/** No handler installed. */
1064	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1065	/* 1 is reserved so the lineup is identical with the physical ones. */
1066	/** Write access is monitored. */
1067	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1068	/** All access is monitored. */
1069	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1070	/** @} */
1071
1072	/**
1073	* Gets the virtual access handler state of a page.
1074	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1075	* @param pPage Pointer to the physical guest page tracking structure.
1076	*/
1077	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
1078
1079	/**
1080	* Sets the virtual access handler state of a page.
1081	* @param pPage Pointer to the physical guest page tracking structure.
1082	* @param _uState The new state value.
1083	*/
1084	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1085	do { \
1086	(pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1087	\| ((_uState) & UINT8_C(0x03)); \
1088	} while (0)
1089
1090	/**
1091	* Checks if the page has any virtual access handlers.
1092	* @returns true/false
1093	* @param pPage Pointer to the physical guest page tracking structure.
1094	*/
1095	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1096	( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1097
1098	/**
1099	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1100	* virtual handlers.
1101	* @returns true/false
1102	* @param pPage Pointer to the physical guest page tracking structure.
1103	*/
1104	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1105	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1106
1107
1108	/**
1109	* Checks if the page has any access handlers, including temporarily disabled ones.
1110	* @returns true/false
1111	* @param pPage Pointer to the physical guest page tracking structure.
1112	*/
1113	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1114	# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1115	( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1116	#else
1117	# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1118	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1119	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1120	#endif
1121
1122	/**
1123	* Checks if the page has any active access handlers.
1124	* @returns true/false
1125	* @param pPage Pointer to the physical guest page tracking structure.
1126	*/
1127	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1128	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1129	( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1130	#else
1131	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1132	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1133	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1134	#endif
1135
1136	/**
1137	* Checks if the page has any active access handlers catching all accesses.
1138	* @returns true/false
1139	* @param pPage Pointer to the physical guest page tracking structure.
1140	*/
1141	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1142	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1143	( ( ((pPage)->u16MiscY.au8[0] \| (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1144	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
1145	#else
1146	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1147	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1148	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1149	#endif
1150
1151
1152	/** @def PGM_PAGE_GET_TRACKING
1153	* Gets the packed shadow page pool tracking data associated with a guest page.
1154	* @returns uint16_t containing the data.
1155	* @param pPage Pointer to the physical guest page tracking structure.
1156	*/
1157	#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1158
1159	/** @def PGM_PAGE_SET_TRACKING
1160	* Sets the packed shadow page pool tracking data associated with a guest page.
1161	* @param pPage Pointer to the physical guest page tracking structure.
1162	* @param u16TrackingData The tracking data to store.
1163	*/
1164	#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1165	do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1166
1167	/** @def PGM_PAGE_GET_TD_CREFS
1168	* Gets the @a cRefs tracking data member.
1169	* @returns cRefs.
1170	* @param pPage Pointer to the physical guest page tracking structure.
1171	*/
1172	#define PGM_PAGE_GET_TD_CREFS(pPage) \
1173	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1174
1175	/** @def PGM_PAGE_GET_TD_IDX
1176	* Gets the @a idx tracking data member.
1177	* @returns idx.
1178	* @param pPage Pointer to the physical guest page tracking structure.
1179	*/
1180	#define PGM_PAGE_GET_TD_IDX(pPage) \
1181	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1182
1183
1184	/** Max number of locks on a page. */
1185	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1186
1187	/** Get the read lock count.
1188	* @returns count.
1189	* @param pPage Pointer to the physical guest page tracking structure.
1190	*/
1191	#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1192
1193	/** Get the write lock count.
1194	* @returns count.
1195	* @param pPage Pointer to the physical guest page tracking structure.
1196	*/
1197	#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1198
1199	/** Decrement the read lock counter.
1200	* @param pPage Pointer to the physical guest page tracking structure.
1201	*/
1202	#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1203
1204	/** Decrement the write lock counter.
1205	* @param pPage Pointer to the physical guest page tracking structure.
1206	*/
1207	#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1208
1209	/** Increment the read lock counter.
1210	* @param pPage Pointer to the physical guest page tracking structure.
1211	*/
1212	#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1213
1214	/** Increment the write lock counter.
1215	* @param pPage Pointer to the physical guest page tracking structure.
1216	*/
1217	#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1218
1219
1220	#if 0
1221	/** Enables sanity checking of write monitoring using CRC-32. */
1222	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1223	#endif
1224
1225	/**
1226	* Per page live save tracking data.
1227	*/
1228	typedef struct PGMLIVESAVERAMPAGE
1229	{
1230	/** Number of times it has been dirtied. */
1231	uint32_t cDirtied : 24;
1232	/** Whether it is currently dirty. */
1233	uint32_t fDirty : 1;
1234	/** Ignore the page.
1235	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1236	* deal with these after pausing the VM and DevPCI have said it bit about
1237	* remappings. */
1238	uint32_t fIgnore : 1;
1239	/** Was a ZERO page last time around. */
1240	uint32_t fZero : 1;
1241	/** Was a SHARED page last time around. */
1242	uint32_t fShared : 1;
1243	/** Whether the page is/was write monitored in a previous pass. */
1244	uint32_t fWriteMonitored : 1;
1245	/** Whether the page is/was write monitored earlier in this pass. */
1246	uint32_t fWriteMonitoredJustNow : 1;
1247	/** Bits reserved for future use. */
1248	uint32_t u2Reserved : 2;
1249	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1250	/** CRC-32 for the page. This is for internal consistency checks. */
1251	uint32_t u32Crc;
1252	#endif
1253	} PGMLIVESAVERAMPAGE;
1254	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1255	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1256	#else
1257	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1258	#endif
1259	/** Pointer to the per page live save tracking data. */
1260	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1261
1262	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1263	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1264
1265
1266	/**
1267	* Ram range for GC Phys to HC Phys conversion.
1268	*
1269	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1270	* conversions too, but we'll let MM handle that for now.
1271	*
1272	* This structure is used by linked lists in both GC and HC.
1273	*/
1274	typedef struct PGMRAMRANGE
1275	{
1276	/** Start of the range. Page aligned. */
1277	RTGCPHYS GCPhys;
1278	/** Size of the range. (Page aligned of course). */
1279	RTGCPHYS cb;
1280	/** Pointer to the next RAM range - for R3. */
1281	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1282	/** Pointer to the next RAM range - for R0. */
1283	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1284	/** Pointer to the next RAM range - for RC. */
1285	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1286	/** PGM_RAM_RANGE_FLAGS_* flags. */
1287	uint32_t fFlags;
1288	/** Last address in the range (inclusive). Page aligned (-1). */
1289	RTGCPHYS GCPhysLast;
1290	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1291	R3PTRTYPE(void *) pvR3;
1292	/** Live save per page tracking data. */
1293	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1294	/** The range description. */
1295	R3PTRTYPE(const char *) pszDesc;
1296	/** Pointer to self - R0 pointer. */
1297	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1298	/** Pointer to self - RC pointer. */
1299	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1300	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1301	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1302	/** Array of physical guest page tracking structures. */
1303	PGMPAGE aPages[1];
1304	} PGMRAMRANGE;
1305	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1306	typedef PGMRAMRANGE *PPGMRAMRANGE;
1307
1308	/** @name PGMRAMRANGE::fFlags
1309	* @{ */
1310	/** The RAM range is floating around as an independent guest mapping. */
1311	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1312	/** Ad hoc RAM range for an ROM mapping. */
1313	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1314	/** Ad hoc RAM range for an MMIO mapping. */
1315	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1316	/** Ad hoc RAM range for an MMIO2 mapping. */
1317	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1318	/** @} */
1319
1320	/** Tests if a RAM range is an ad hoc one or not.
1321	* @returns true/false.
1322	* @param pRam The RAM range.
1323	*/
1324	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1325	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1326
1327
1328	/**
1329	* Per page tracking structure for ROM image.
1330	*
1331	* A ROM image may have a shadow page, in which case we may have two pages
1332	* backing it. This structure contains the PGMPAGE for both while
1333	* PGMRAMRANGE have a copy of the active one. It is important that these
1334	* aren't out of sync in any regard other than page pool tracking data.
1335	*/
1336	typedef struct PGMROMPAGE
1337	{
1338	/** The page structure for the virgin ROM page. */
1339	PGMPAGE Virgin;
1340	/** The page structure for the shadow RAM page. */
1341	PGMPAGE Shadow;
1342	/** The current protection setting. */
1343	PGMROMPROT enmProt;
1344	/** Live save status information. Makes use of unused alignment space. */
1345	struct
1346	{
1347	/** The previous protection value. */
1348	uint8_t u8Prot;
1349	/** Written to flag set by the handler. */
1350	bool fWrittenTo;
1351	/** Whether the shadow page is dirty or not. */
1352	bool fDirty;
1353	/** Whether it was dirtied in the recently. */
1354	bool fDirtiedRecently;
1355	} LiveSave;
1356	} PGMROMPAGE;
1357	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1358	/** Pointer to a ROM page tracking structure. */
1359	typedef PGMROMPAGE *PPGMROMPAGE;
1360
1361
1362	/**
1363	* A registered ROM image.
1364	*
1365	* This is needed to keep track of ROM image since they generally intrude
1366	* into a PGMRAMRANGE. It also keeps track of additional info like the
1367	* two page sets (read-only virgin and read-write shadow), the current
1368	* state of each page.
1369	*
1370	* Because access handlers cannot easily be executed in a different
1371	* context, the ROM ranges needs to be accessible and in all contexts.
1372	*/
1373	typedef struct PGMROMRANGE
1374	{
1375	/** Pointer to the next range - R3. */
1376	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1377	/** Pointer to the next range - R0. */
1378	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1379	/** Pointer to the next range - RC. */
1380	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1381	/** Pointer alignment */
1382	RTRCPTR RCPtrAlignment;
1383	/** Address of the range. */
1384	RTGCPHYS GCPhys;
1385	/** Address of the last byte in the range. */
1386	RTGCPHYS GCPhysLast;
1387	/** Size of the range. */
1388	RTGCPHYS cb;
1389	/** The flags (PGMPHYS_ROM_FLAGS_). /
1390	uint32_t fFlags;
1391	/** The saved state range ID. */
1392	uint8_t idSavedState;
1393	/** Alignment padding. */
1394	uint8_t au8Alignment[3];
1395	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1396	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1397	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1398	* This is used for strictness checks. */
1399	R3PTRTYPE(const void *) pvOriginal;
1400	/** The ROM description. */
1401	R3PTRTYPE(const char *) pszDesc;
1402	/** The per page tracking structures. */
1403	PGMROMPAGE aPages[1];
1404	} PGMROMRANGE;
1405	/** Pointer to a ROM range. */
1406	typedef PGMROMRANGE *PPGMROMRANGE;
1407
1408
1409	/**
1410	* Live save per page data for an MMIO2 page.
1411	*
1412	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1413	* of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1414	* CRC-32 for detecting changes as well as special handling of zero pages. This
1415	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1416	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1417	* because of speed (2.5x and 6x slower).)
1418	*
1419	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1420	* save but normally is disabled. Since we can write monitore guest
1421	* accesses on our own, we only need this for host accesses. Shouldn't be
1422	* too difficult for DevVGA, VMMDev might be doable, the planned
1423	* networking fun will be fun since it involves ring-0.
1424	*/
1425	typedef struct PGMLIVESAVEMMIO2PAGE
1426	{
1427	/** Set if the page is considered dirty. */
1428	bool fDirty;
1429	/** The number of scans this page has remained unchanged for.
1430	* Only updated for dirty pages. */
1431	uint8_t cUnchangedScans;
1432	/** Whether this page was zero at the last scan. */
1433	bool fZero;
1434	/** Alignment padding. */
1435	bool fReserved;
1436	/** CRC-32 for the first half of the page.
1437	* This is used together with u32CrcH2 to quickly detect changes in the page
1438	* during the non-final passes. */
1439	uint32_t u32CrcH1;
1440	/** CRC-32 for the second half of the page. */
1441	uint32_t u32CrcH2;
1442	/** SHA-1 for the saved page.
1443	* This is used in the final pass to skip pages without changes. */
1444	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1445	} PGMLIVESAVEMMIO2PAGE;
1446	/** Pointer to a live save status data for an MMIO2 page. */
1447	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1448
1449	/**
1450	* A registered MMIO2 (= Device RAM) range.
1451	*
1452	* There are a few reason why we need to keep track of these
1453	* registrations. One of them is the deregistration & cleanup stuff,
1454	* while another is that the PGMRAMRANGE associated with such a region may
1455	* have to be removed from the ram range list.
1456	*
1457	* Overlapping with a RAM range has to be 100% or none at all. The pages
1458	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1459	* will be raised if a partial overlap or an overlap of ROM pages is
1460	* encountered. On an overlap we will free all the existing RAM pages and
1461	* put in the ram range pages instead.
1462	*/
1463	typedef struct PGMMMIO2RANGE
1464	{
1465	/** The owner of the range. (a device) */
1466	PPDMDEVINSR3 pDevInsR3;
1467	/** Pointer to the ring-3 mapping of the allocation. */
1468	RTR3PTR pvR3;
1469	/** Pointer to the next range - R3. */
1470	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1471	/** Whether it's mapped or not. */
1472	bool fMapped;
1473	/** Whether it's overlapping or not. */
1474	bool fOverlapping;
1475	/** The PCI region number.
1476	* @remarks This ASSUMES that nobody will ever really need to have multiple
1477	* PCI devices with matching MMIO region numbers on a single device. */
1478	uint8_t iRegion;
1479	/** The saved state range ID. */
1480	uint8_t idSavedState;
1481	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1482	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1483	/** Live save per page tracking data. */
1484	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1485	/** The associated RAM range. */
1486	PGMRAMRANGE RamRange;
1487	} PGMMMIO2RANGE;
1488	/** Pointer to a MMIO2 range. */
1489	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1490
1491
1492
1493
1494	/**
1495	* PGMPhysRead/Write cache entry
1496	*/
1497	typedef struct PGMPHYSCACHEENTRY
1498	{
1499	/** R3 pointer to physical page. */
1500	R3PTRTYPE(uint8_t *) pbR3;
1501	/** GC Physical address for cache entry */
1502	RTGCPHYS GCPhys;
1503	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1504	RTGCPHYS u32Padding0; /*< alignment padding. /
1505	#endif
1506	} PGMPHYSCACHEENTRY;
1507
1508	/**
1509	* PGMPhysRead/Write cache to reduce REM memory access overhead
1510	*/
1511	typedef struct PGMPHYSCACHE
1512	{
1513	/** Bitmap of valid cache entries */
1514	uint64_t aEntries;
1515	/** Cache entries */
1516	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1517	} PGMPHYSCACHE;
1518
1519
1520	/** Pointer to an allocation chunk ring-3 mapping. */
1521	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1522	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1523	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1524
1525	/**
1526	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1527	*
1528	* The primary tree (Core) uses the chunk id as key.
1529	*/
1530	typedef struct PGMCHUNKR3MAP
1531	{
1532	/** The key is the chunk id. */
1533	AVLU32NODECORE Core;
1534	/** The current age thingy. */
1535	uint32_t iAge;
1536	/** The current reference count. */
1537	uint32_t volatile cRefs;
1538	/** The current permanent reference count. */
1539	uint32_t volatile cPermRefs;
1540	/** The mapping address. */
1541	void *pv;
1542	} PGMCHUNKR3MAP;
1543
1544	/**
1545	* Allocation chunk ring-3 mapping TLB entry.
1546	*/
1547	typedef struct PGMCHUNKR3MAPTLBE
1548	{
1549	/** The chunk id. */
1550	uint32_t volatile idChunk;
1551	#if HC_ARCH_BITS == 64
1552	uint32_t u32Padding; /*< alignment padding. /
1553	#endif
1554	/** The chunk map. */
1555	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1556	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1557	#else
1558	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1559	#endif
1560	} PGMCHUNKR3MAPTLBE;
1561	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1562	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1563
1564	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1565	* @remark Must be a power of two value. */
1566	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1567
1568	/**
1569	* Allocation chunk ring-3 mapping TLB.
1570	*
1571	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1572	* At first glance this might look kinda odd since AVL trees are
1573	* supposed to give the most optimial lookup times of all trees
1574	* due to their balancing. However, take a tree with 1023 nodes
1575	* in it, that's 10 levels, meaning that most searches has to go
1576	* down 9 levels before they find what they want. This isn't fast
1577	* compared to a TLB hit. There is the factor of cache misses,
1578	* and of course the problem with trees and branch prediction.
1579	* This is why we use TLBs in front of most of the trees.
1580	*
1581	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1582	* difficult when we switch to the new inlined AVL trees (from kStuff).
1583	*/
1584	typedef struct PGMCHUNKR3MAPTLB
1585	{
1586	/** The TLB entries. */
1587	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1588	} PGMCHUNKR3MAPTLB;
1589
1590	/**
1591	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1592	* @returns Chunk TLB index.
1593	* @param idChunk The Chunk ID.
1594	*/
1595	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1596
1597
1598	/**
1599	* Ring-3 guest page mapping TLB entry.
1600	* @remarks used in ring-0 as well at the moment.
1601	*/
1602	typedef struct PGMPAGER3MAPTLBE
1603	{
1604	/** Address of the page. */
1605	RTGCPHYS volatile GCPhys;
1606	/** The guest page. */
1607	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1608	R3PTRTYPE(PPGMPAGE) volatile pPage;
1609	#else
1610	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1611	#endif
1612	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1613	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1614	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1615	#else
1616	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1617	#endif
1618	/** The address */
1619	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1620	R3PTRTYPE(void *) volatile pv;
1621	#else
1622	R3R0PTRTYPE(void *) volatile pv;
1623	#endif
1624	#if HC_ARCH_BITS == 32
1625	uint32_t u32Padding; /*< alignment padding. /
1626	#endif
1627	} PGMPAGER3MAPTLBE;
1628	/** Pointer to an entry in the HC physical TLB. */
1629	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1630
1631
1632	/** The number of entries in the ring-3 guest page mapping TLB.
1633	* @remarks The value must be a power of two. */
1634	#define PGM_PAGER3MAPTLB_ENTRIES 256
1635
1636	/**
1637	* Ring-3 guest page mapping TLB.
1638	* @remarks used in ring-0 as well at the moment.
1639	*/
1640	typedef struct PGMPAGER3MAPTLB
1641	{
1642	/** The TLB entries. */
1643	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1644	} PGMPAGER3MAPTLB;
1645	/** Pointer to the ring-3 guest page mapping TLB. */
1646	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1647
1648	/**
1649	* Calculates the index of the TLB entry for the specified guest page.
1650	* @returns Physical TLB index.
1651	* @param GCPhys The guest physical address.
1652	*/
1653	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1654
1655
1656	/**
1657	* Raw-mode context dynamic mapping cache entry.
1658	*
1659	* Because of raw-mode context being reloctable and all relocations are applied
1660	* in ring-3, this has to be defined here and be RC specfic.
1661	*
1662	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1663	*/
1664	typedef struct PGMRCDYNMAPENTRY
1665	{
1666	/** The physical address of the currently mapped page.
1667	* This is duplicate for three reasons: cache locality, cache policy of the PT
1668	* mappings and sanity checks. */
1669	RTHCPHYS HCPhys;
1670	/** Pointer to the page. */
1671	RTRCPTR pvPage;
1672	/** The number of references. */
1673	int32_t volatile cRefs;
1674	/** PTE pointer union. */
1675	union PGMRCDYNMAPENTRY_PPTE
1676	{
1677	/** PTE pointer, 32-bit legacy version. */
1678	RCPTRTYPE(PX86PTE) pLegacy;
1679	/** PTE pointer, PAE version. */
1680	RCPTRTYPE(PX86PTEPAE) pPae;
1681	/** PTE pointer, the void version. */
1682	RTRCPTR pv;
1683	} uPte;
1684	/** Alignment padding. */
1685	RTRCPTR RCPtrAlignment;
1686	} PGMRCDYNMAPENTRY;
1687	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1688	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1689
1690
1691	/**
1692	* Dynamic mapping cache for the raw-mode context.
1693	*
1694	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1695	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1696	* so that we can perform relocations from PGMR3Relocate. This has the
1697	* consequence that we must have separate ring-0 and raw-mode context versions
1698	* of this struct even if they share the basic elements.
1699	*
1700	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1701	*/
1702	typedef struct PGMRCDYNMAP
1703	{
1704	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1705	uint32_t u32Magic;
1706	/** Array for tracking and managing the pages. */
1707	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1708	/** The cache size given as a number of pages. */
1709	uint32_t cPages;
1710	/** Whether it's 32-bit legacy or PAE/AMD64 paging mode. */
1711	bool fLegacyMode;
1712	/** The current load.
1713	* This does not include guard pages. */
1714	uint32_t cLoad;
1715	/** The max load ever.
1716	* This is maintained to get trigger adding of more mapping space. */
1717	uint32_t cMaxLoad;
1718	/** The number of guard pages. */
1719	uint32_t cGuardPages;
1720	/** The number of users (protected by hInitLock). */
1721	uint32_t cUsers;
1722	} PGMRCDYNMAP;
1723	/** Pointer to the dynamic cache for the raw-mode context. */
1724	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1725
1726
1727	/**
1728	* Mapping cache usage set entry.
1729	*
1730	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1731	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1732	* cache. If it's extended to include ring-3, well, then something
1733	* will have be changed here...
1734	*/
1735	typedef struct PGMMAPSETENTRY
1736	{
1737	/** Pointer to the page. */
1738	#ifndef IN_RC
1739	RTR0PTR pvPage;
1740	#else
1741	RTRCPTR pvPage;
1742	# if HC_ARCH_BITS == 64
1743	uint32_t u32Alignment2;
1744	# endif
1745	#endif
1746	/** The mapping cache index. */
1747	uint16_t iPage;
1748	/** The number of references.
1749	* The max is UINT16_MAX - 1. */
1750	uint16_t cRefs;
1751	/** The number inlined references.
1752	* The max is UINT16_MAX - 1. */
1753	uint16_t cInlinedRefs;
1754	/** Unreferences. */
1755	uint16_t cUnrefs;
1756
1757	#if HC_ARCH_BITS == 32
1758	uint32_t u32Alignment1;
1759	#endif
1760	/** The physical address for this entry. */
1761	RTHCPHYS HCPhys;
1762	} PGMMAPSETENTRY;
1763	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1764	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1765	/** Pointer to a mapping cache usage set entry. */
1766	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1767
1768	/**
1769	* Mapping cache usage set.
1770	*
1771	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1772	* done during exits / traps. The set is
1773	*/
1774	typedef struct PGMMAPSET
1775	{
1776	/** The number of occupied entries.
1777	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1778	* dynamic mappings. */
1779	uint32_t cEntries;
1780	/** The start of the current subset.
1781	* This is UINT32_MAX if no subset is currently open. */
1782	uint32_t iSubset;
1783	/** The index of the current CPU, only valid if the set is open. */
1784	int32_t iCpu;
1785	uint32_t alignment;
1786	/** The entries. */
1787	PGMMAPSETENTRY aEntries[64];
1788	/** HCPhys -> iEntry fast lookup table.
1789	* Use PGMMAPSET_HASH for hashing.
1790	* The entries may or may not be valid, check against cEntries. */
1791	uint8_t aiHashTable[128];
1792	} PGMMAPSET;
1793	AssertCompileSizeAlignment(PGMMAPSET, 8);
1794	/** Pointer to the mapping cache set. */
1795	typedef PGMMAPSET *PPGMMAPSET;
1796
1797	/** PGMMAPSET::cEntries value for a closed set. */
1798	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1799
1800	/** Hash function for aiHashTable. */
1801	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1802
1803
1804	/** @name Context neutrual page mapper TLB.
1805	*
1806	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1807	* code is writting in a kind of context neutrual way. Time will show whether
1808	* this actually makes sense or not...
1809	*
1810	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1811	* context ends up using a global mapping cache on some platforms
1812	* (darwin).
1813	*
1814	* @{ */
1815	/** @typedef PPGMPAGEMAPTLB
1816	* The page mapper TLB pointer type for the current context. */
1817	/** @typedef PPGMPAGEMAPTLB
1818	* The page mapper TLB entry pointer type for the current context. */
1819	/** @typedef PPGMPAGEMAPTLB
1820	* The page mapper TLB entry pointer pointer type for the current context. */
1821	/** @def PGM_PAGEMAPTLB_ENTRIES
1822	* The number of TLB entries in the page mapper TLB for the current context. */
1823	/** @def PGM_PAGEMAPTLB_IDX
1824	* Calculate the TLB index for a guest physical address.
1825	* @returns The TLB index.
1826	* @param GCPhys The guest physical address. */
1827	/** @typedef PPGMPAGEMAP
1828	* Pointer to a page mapper unit for current context. */
1829	/** @typedef PPPGMPAGEMAP
1830	* Pointer to a page mapper unit pointer for current context. */
1831	#ifdef IN_RC
1832	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1833	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1834	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1835	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1836	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1837	typedef void * PPGMPAGEMAP;
1838	typedef void ** PPPGMPAGEMAP;
1839	//#elif IN_RING0
1840	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1841	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1842	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1843	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1844	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1845	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1846	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1847	#else
1848	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1849	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1850	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1851	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1852	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1853	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1854	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1855	#endif
1856	/** @} */
1857
1858
1859	/** @name PGM Pool Indexes.
1860	* Aka. the unique shadow page identifier.
1861	* @{ */
1862	/** NIL page pool IDX. */
1863	#define NIL_PGMPOOL_IDX 0
1864	/** The first normal index. */
1865	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1866	/** Page directory (32-bit root). */
1867	#define PGMPOOL_IDX_PD 1
1868	/** Page Directory Pointer Table (PAE root). */
1869	#define PGMPOOL_IDX_PDPT 2
1870	/** AMD64 CR3 level index.*/
1871	#define PGMPOOL_IDX_AMD64_CR3 3
1872	/** Nested paging root.*/
1873	#define PGMPOOL_IDX_NESTED_ROOT 4
1874	/** The first normal index. */
1875	#define PGMPOOL_IDX_FIRST 5
1876	/** The last valid index. (inclusive, 14 bits) */
1877	#define PGMPOOL_IDX_LAST 0x3fff
1878	/** @} */
1879
1880	/** The NIL index for the parent chain. */
1881	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1882	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1883
1884	/**
1885	* Node in the chain linking a shadowed page to it's parent (user).
1886	*/
1887	#pragma pack(1)
1888	typedef struct PGMPOOLUSER
1889	{
1890	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1891	uint16_t iNext;
1892	/** The user page index. */
1893	uint16_t iUser;
1894	/** Index into the user table. */
1895	uint32_t iUserTable;
1896	} PGMPOOLUSER, *PPGMPOOLUSER;
1897	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1898	#pragma pack()
1899
1900
1901	/** The NIL index for the phys ext chain. */
1902	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1903	/** The NIL pte index for a phys ext chain slot. */
1904	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1905
1906	/**
1907	* Node in the chain of physical cross reference extents.
1908	* @todo Calling this an 'extent' is not quite right, find a better name.
1909	* @todo find out the optimal size of the aidx array
1910	*/
1911	#pragma pack(1)
1912	typedef struct PGMPOOLPHYSEXT
1913	{
1914	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1915	uint16_t iNext;
1916	/** Alignment. */
1917	uint16_t u16Align;
1918	/** The user page index. */
1919	uint16_t aidx[3];
1920	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1921	uint16_t apte[3];
1922	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1923	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1924	#pragma pack()
1925
1926
1927	/**
1928	* The kind of page that's being shadowed.
1929	*/
1930	typedef enum PGMPOOLKIND
1931	{
1932	/** The virtual invalid 0 entry. */
1933	PGMPOOLKIND_INVALID = 0,
1934	/** The entry is free (=unused). */
1935	PGMPOOLKIND_FREE,
1936
1937	/** Shw: 32-bit page table; Gst: no paging */
1938	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1939	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1940	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1941	/** Shw: 32-bit page table; Gst: 4MB page. */
1942	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1943	/** Shw: PAE page table; Gst: no paging */
1944	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1945	/** Shw: PAE page table; Gst: 32-bit page table. */
1946	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1947	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1948	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1949	/** Shw: PAE page table; Gst: PAE page table. */
1950	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1951	/** Shw: PAE page table; Gst: 2MB page. */
1952	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1953
1954	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1955	PGMPOOLKIND_32BIT_PD,
1956	/** Shw: 32-bit page directory. Gst: no paging. */
1957	PGMPOOLKIND_32BIT_PD_PHYS,
1958	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1959	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1960	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1961	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1962	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1963	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1964	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1965	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1966	/** Shw: PAE page directory; Gst: PAE page directory. */
1967	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1968	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1969	PGMPOOLKIND_PAE_PD_PHYS,
1970
1971	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1972	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1973	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1974	PGMPOOLKIND_PAE_PDPT,
1975	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1976	PGMPOOLKIND_PAE_PDPT_PHYS,
1977
1978	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1979	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1980	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1981	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1982	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1983	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1984	/** Shw: 64-bit page directory table; Gst: no paging */
1985	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1986
1987	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1988	PGMPOOLKIND_64BIT_PML4,
1989
1990	/** Shw: EPT page directory pointer table; Gst: no paging */
1991	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1992	/** Shw: EPT page directory table; Gst: no paging */
1993	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1994	/** Shw: EPT page table; Gst: no paging */
1995	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1996
1997	/** Shw: Root Nested paging table. */
1998	PGMPOOLKIND_ROOT_NESTED,
1999
2000	/** The last valid entry. */
2001	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2002	} PGMPOOLKIND;
2003
2004	/**
2005	* The access attributes of the page; only applies to big pages.
2006	*/
2007	typedef enum
2008	{
2009	PGMPOOLACCESS_DONTCARE = 0,
2010	PGMPOOLACCESS_USER_RW,
2011	PGMPOOLACCESS_USER_R,
2012	PGMPOOLACCESS_USER_RW_NX,
2013	PGMPOOLACCESS_USER_R_NX,
2014	PGMPOOLACCESS_SUPERVISOR_RW,
2015	PGMPOOLACCESS_SUPERVISOR_R,
2016	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2017	PGMPOOLACCESS_SUPERVISOR_R_NX
2018	} PGMPOOLACCESS;
2019
2020	/**
2021	* The tracking data for a page in the pool.
2022	*/
2023	typedef struct PGMPOOLPAGE
2024	{
2025	/** AVL node code with the (R3) physical address of this page. */
2026	AVLOHCPHYSNODECORE Core;
2027	/** Pointer to the R3 mapping of the page. */
2028	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2029	R3PTRTYPE(void *) pvPageR3;
2030	#else
2031	R3R0PTRTYPE(void *) pvPageR3;
2032	#endif
2033	/** The guest physical address. */
2034	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2035	uint32_t Alignment0;
2036	#endif
2037	RTGCPHYS GCPhys;
2038
2039	/** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2040	RTGCPTR pvLastAccessHandlerRip;
2041	RTGCPTR pvLastAccessHandlerFault;
2042	uint64_t cLastAccessHandlerCount;
2043
2044	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2045	uint8_t enmKind;
2046	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2047	uint8_t enmAccess;
2048	/** The index of this page. */
2049	uint16_t idx;
2050	/** The next entry in the list this page currently resides in.
2051	* It's either in the free list or in the GCPhys hash. */
2052	uint16_t iNext;
2053	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2054	uint16_t iUserHead;
2055	/** The number of present entries. */
2056	uint16_t cPresent;
2057	/** The first entry in the table which is present. */
2058	uint16_t iFirstPresent;
2059	/** The number of modifications to the monitored page. */
2060	uint16_t cModifications;
2061	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2062	uint16_t iModifiedNext;
2063	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2064	uint16_t iModifiedPrev;
2065	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2066	uint16_t iMonitoredNext;
2067	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2068	uint16_t iMonitoredPrev;
2069	/** The next page in the age list. */
2070	uint16_t iAgeNext;
2071	/** The previous page in the age list. */
2072	uint16_t iAgePrev;
2073	/** Used to indicate that the page is zeroed. */
2074	bool fZeroed;
2075	/** Used to indicate that a PT has non-global entries. */
2076	bool fSeenNonGlobal;
2077	/** Used to indicate that we're monitoring writes to the guest page. */
2078	bool fMonitored;
2079	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2080	* (All pages are in the age list.) */
2081	bool fCached;
2082	/** This is used by the R3 access handlers when invoked by an async thread.
2083	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2084	bool volatile fReusedFlushPending;
2085	/** Used to mark the page as dirty (write monitoring is temporarily
2086	* off). */
2087	bool fDirty;
2088
2089	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2090	uint32_t cLocked;
2091	uint32_t idxDirty;
2092	RTGCPTR pvDirtyFault;
2093	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
2094	/** Pointer to a const pool page. */
2095	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2096
2097
2098	/** The hash table size. */
2099	# define PGMPOOL_HASH_SIZE 0x40
2100	/** The hash function. */
2101	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2102
2103
2104	/**
2105	* The shadow page pool instance data.
2106	*
2107	* It's all one big allocation made at init time, except for the
2108	* pages that is. The user nodes follows immediatly after the
2109	* page structures.
2110	*/
2111	typedef struct PGMPOOL
2112	{
2113	/** The VM handle - R3 Ptr. */
2114	PVMR3 pVMR3;
2115	/** The VM handle - R0 Ptr. */
2116	PVMR0 pVMR0;
2117	/** The VM handle - RC Ptr. */
2118	PVMRC pVMRC;
2119	/** The max pool size. This includes the special IDs. */
2120	uint16_t cMaxPages;
2121	/** The current pool size. */
2122	uint16_t cCurPages;
2123	/** The head of the free page list. */
2124	uint16_t iFreeHead;
2125	/* Padding. */
2126	uint16_t u16Padding;
2127	/** Head of the chain of free user nodes. */
2128	uint16_t iUserFreeHead;
2129	/** The number of user nodes we've allocated. */
2130	uint16_t cMaxUsers;
2131	/** The number of present page table entries in the entire pool. */
2132	uint32_t cPresent;
2133	/** Pointer to the array of user nodes - RC pointer. */
2134	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2135	/** Pointer to the array of user nodes - R3 pointer. */
2136	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2137	/** Pointer to the array of user nodes - R0 pointer. */
2138	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2139	/** Head of the chain of free phys ext nodes. */
2140	uint16_t iPhysExtFreeHead;
2141	/** The number of user nodes we've allocated. */
2142	uint16_t cMaxPhysExts;
2143	/** Pointer to the array of physical xref extent - RC pointer. */
2144	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2145	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2146	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2147	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2148	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2149	/** Hash table for GCPhys addresses. */
2150	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2151	/** The head of the age list. */
2152	uint16_t iAgeHead;
2153	/** The tail of the age list. */
2154	uint16_t iAgeTail;
2155	/** Set if the cache is enabled. */
2156	bool fCacheEnabled;
2157	/** Alignment padding. */
2158	bool afPadding1[3];
2159	/** Head of the list of modified pages. */
2160	uint16_t iModifiedHead;
2161	/** The current number of modified pages. */
2162	uint16_t cModifiedPages;
2163	/** Access handler, RC. */
2164	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2165	/** Access handler, R0. */
2166	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2167	/** Access handler, R3. */
2168	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2169	/** The access handler description (R3 ptr). */
2170	R3PTRTYPE(const char *) pszAccessHandler;
2171	# if HC_ARCH_BITS == 32
2172	/** Alignment padding. */
2173	uint32_t u32Padding2;
2174	# endif
2175	/* Next available slot. */
2176	uint32_t idxFreeDirtyPage;
2177	/* Number of active dirty pages. */
2178	uint32_t cDirtyPages;
2179	/* Array of current dirty pgm pool page indices. */
2180	uint16_t aIdxDirtyPages[16];
2181	uint64_t aDirtyPages[16][512];
2182	/** The number of pages currently in use. */
2183	uint16_t cUsedPages;
2184	#ifdef VBOX_WITH_STATISTICS
2185	/** The high water mark for cUsedPages. */
2186	uint16_t cUsedPagesHigh;
2187	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
2188	/** Profiling pgmPoolAlloc(). */
2189	STAMPROFILEADV StatAlloc;
2190	/** Profiling pgmR3PoolClearDoIt(). */
2191	STAMPROFILE StatClearAll;
2192	/** Profiling pgmR3PoolReset(). */
2193	STAMPROFILE StatR3Reset;
2194	/** Profiling pgmPoolFlushPage(). */
2195	STAMPROFILE StatFlushPage;
2196	/** Profiling pgmPoolFree(). */
2197	STAMPROFILE StatFree;
2198	/** Counting explicit flushes by PGMPoolFlushPage(). */
2199	STAMCOUNTER StatForceFlushPage;
2200	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2201	STAMCOUNTER StatForceFlushDirtyPage;
2202	/** Counting flushes for reused pages. */
2203	STAMCOUNTER StatForceFlushReused;
2204	/** Profiling time spent zeroing pages. */
2205	STAMPROFILE StatZeroPage;
2206	/** Profiling of pgmPoolTrackDeref. */
2207	STAMPROFILE StatTrackDeref;
2208	/** Profiling pgmTrackFlushGCPhysPT. */
2209	STAMPROFILE StatTrackFlushGCPhysPT;
2210	/** Profiling pgmTrackFlushGCPhysPTs. */
2211	STAMPROFILE StatTrackFlushGCPhysPTs;
2212	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2213	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2214	/** Number of times we've been out of user records. */
2215	STAMCOUNTER StatTrackFreeUpOneUser;
2216	/** Nr of flushed entries. */
2217	STAMCOUNTER StatTrackFlushEntry;
2218	/** Nr of updated entries. */
2219	STAMCOUNTER StatTrackFlushEntryKeep;
2220	/** Profiling deref activity related tracking GC physical pages. */
2221	STAMPROFILE StatTrackDerefGCPhys;
2222	/** Number of linear searches for a HCPhys in the ram ranges. */
2223	STAMCOUNTER StatTrackLinearRamSearches;
2224	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2225	STAMCOUNTER StamTrackPhysExtAllocFailures;
2226	/** Profiling the RC/R0 access handler. */
2227	STAMPROFILE StatMonitorRZ;
2228	/** Times we've failed interpreting the instruction. */
2229	STAMCOUNTER StatMonitorRZEmulateInstr;
2230	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2231	STAMPROFILE StatMonitorRZFlushPage;
2232	/* Times we've detected a page table reinit. */
2233	STAMCOUNTER StatMonitorRZFlushReinit;
2234	/** Counting flushes for pages that are modified too often. */
2235	STAMCOUNTER StatMonitorRZFlushModOverflow;
2236	/** Times we've detected fork(). */
2237	STAMCOUNTER StatMonitorRZFork;
2238	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2239	STAMPROFILE StatMonitorRZHandled;
2240	/** Times we've failed interpreting a patch code instruction. */
2241	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2242	/** Times we've failed interpreting a patch code instruction during flushing. */
2243	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2244	/** The number of times we've seen rep prefixes we can't handle. */
2245	STAMCOUNTER StatMonitorRZRepPrefix;
2246	/** Profiling the REP STOSD cases we've handled. */
2247	STAMPROFILE StatMonitorRZRepStosd;
2248	/** Nr of handled PT faults. */
2249	STAMCOUNTER StatMonitorRZFaultPT;
2250	/** Nr of handled PD faults. */
2251	STAMCOUNTER StatMonitorRZFaultPD;
2252	/** Nr of handled PDPT faults. */
2253	STAMCOUNTER StatMonitorRZFaultPDPT;
2254	/** Nr of handled PML4 faults. */
2255	STAMCOUNTER StatMonitorRZFaultPML4;
2256
2257	/** Profiling the R3 access handler. */
2258	STAMPROFILE StatMonitorR3;
2259	/** Times we've failed interpreting the instruction. */
2260	STAMCOUNTER StatMonitorR3EmulateInstr;
2261	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2262	STAMPROFILE StatMonitorR3FlushPage;
2263	/* Times we've detected a page table reinit. */
2264	STAMCOUNTER StatMonitorR3FlushReinit;
2265	/** Counting flushes for pages that are modified too often. */
2266	STAMCOUNTER StatMonitorR3FlushModOverflow;
2267	/** Times we've detected fork(). */
2268	STAMCOUNTER StatMonitorR3Fork;
2269	/** Profiling the R3 access we've handled (except REP STOSD). */
2270	STAMPROFILE StatMonitorR3Handled;
2271	/** The number of times we've seen rep prefixes we can't handle. */
2272	STAMCOUNTER StatMonitorR3RepPrefix;
2273	/** Profiling the REP STOSD cases we've handled. */
2274	STAMPROFILE StatMonitorR3RepStosd;
2275	/** Nr of handled PT faults. */
2276	STAMCOUNTER StatMonitorR3FaultPT;
2277	/** Nr of handled PD faults. */
2278	STAMCOUNTER StatMonitorR3FaultPD;
2279	/** Nr of handled PDPT faults. */
2280	STAMCOUNTER StatMonitorR3FaultPDPT;
2281	/** Nr of handled PML4 faults. */
2282	STAMCOUNTER StatMonitorR3FaultPML4;
2283	/** The number of times we're called in an async thread an need to flush. */
2284	STAMCOUNTER StatMonitorR3Async;
2285	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2286	STAMCOUNTER StatResetDirtyPages;
2287	/** Times we've called pgmPoolAddDirtyPage. */
2288	STAMCOUNTER StatDirtyPage;
2289	/** Times we've had to flush duplicates for dirty page management. */
2290	STAMCOUNTER StatDirtyPageDupFlush;
2291	/** Times we've had to flush because of overflow. */
2292	STAMCOUNTER StatDirtyPageOverFlowFlush;
2293
2294	/** The high wather mark for cModifiedPages. */
2295	uint16_t cModifiedPagesHigh;
2296	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
2297
2298	/** The number of cache hits. */
2299	STAMCOUNTER StatCacheHits;
2300	/** The number of cache misses. */
2301	STAMCOUNTER StatCacheMisses;
2302	/** The number of times we've got a conflict of 'kind' in the cache. */
2303	STAMCOUNTER StatCacheKindMismatches;
2304	/** Number of times we've been out of pages. */
2305	STAMCOUNTER StatCacheFreeUpOne;
2306	/** The number of cacheable allocations. */
2307	STAMCOUNTER StatCacheCacheable;
2308	/** The number of uncacheable allocations. */
2309	STAMCOUNTER StatCacheUncacheable;
2310	#else
2311	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
2312	#endif
2313	/** The AVL tree for looking up a page by its HC physical address. */
2314	AVLOHCPHYSTREE HCPhysTree;
2315	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
2316	/** Array of pages. (cMaxPages in length)
2317	* The Id is the index into thist array.
2318	*/
2319	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2320	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2321	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2322	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2323	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2324	#ifdef VBOX_WITH_STATISTICS
2325	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2326	#endif
2327	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2328
2329
2330	/** @def PGMPOOL_PAGE_2_PTR
2331	* Maps a pool page pool into the current context.
2332	*
2333	* @returns VBox status code.
2334	* @param pVM The VM handle.
2335	* @param pPage The pool page.
2336	*
2337	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2338	* small page window employeed by that function. Be careful.
2339	* @remark There is no need to assert on the result.
2340	*/
2341	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2342	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage) RTLOG_COMMA_SRC_POS)
2343	#elif defined(VBOX_STRICT)
2344	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2345	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2346	{
2347	Assert(pPage && pPage->pvPageR3);
2348	return pPage->pvPageR3;
2349	}
2350	#else
2351	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2352	#endif
2353
2354
2355	/** @def PGMPOOL_PAGE_2_PTR_V2
2356	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2357	*
2358	* @returns VBox status code.
2359	* @param pVM The VM handle.
2360	* @param pVCpu The current CPU.
2361	* @param pPage The pool page.
2362	*
2363	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2364	* small page window employeed by that function. Be careful.
2365	* @remark There is no need to assert on the result.
2366	*/
2367	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2368	# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage) RTLOG_COMMA_SRC_POS)
2369	#else
2370	# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2371	#endif
2372
2373
2374	/** @name Per guest page tracking data.
2375	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2376	* is to use more bits for it and split it up later on. But for now we'll play
2377	* safe and change as little as possible.
2378	*
2379	* The 16-bit word has two parts:
2380	*
2381	* The first 14-bit forms the @a idx field. It is either the index of a page in
2382	* the shadow page pool, or and index into the extent list.
2383	*
2384	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2385	* shadow page pool references to the page. If cRefs equals
2386	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2387	* (misnomer) table and not the shadow page pool.
2388	*
2389	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2390	* the 16-bit word.
2391	*
2392	* @{ */
2393	/** The shift count for getting to the cRefs part. */
2394	#define PGMPOOL_TD_CREFS_SHIFT 14
2395	/** The mask applied after shifting the tracking data down by
2396	* PGMPOOL_TD_CREFS_SHIFT. */
2397	#define PGMPOOL_TD_CREFS_MASK 0x3
2398	/** The cRefs value used to indiciate that the idx is the head of a
2399	* physical cross reference list. */
2400	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2401	/** The shift used to get idx. */
2402	#define PGMPOOL_TD_IDX_SHIFT 0
2403	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2404	#define PGMPOOL_TD_IDX_MASK 0x3fff
2405	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2406	* simply too many mappings of this page. */
2407	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2408
2409	/** @def PGMPOOL_TD_MAKE
2410	* Makes a 16-bit tracking data word.
2411	*
2412	* @returns tracking data.
2413	* @param cRefs The @a cRefs field. Must be within bounds!
2414	* @param idx The @a idx field. Must also be within bounds! */
2415	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2416
2417	/** @def PGMPOOL_TD_GET_CREFS
2418	* Get the @a cRefs field from a tracking data word.
2419	*
2420	* @returns The @a cRefs field
2421	* @param u16 The tracking data word.
2422	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2423	* non-zero @a u16. */
2424	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2425
2426	/** @def PGMPOOL_TD_GET_IDX
2427	* Get the @a idx field from a tracking data word.
2428	*
2429	* @returns The @a idx field
2430	* @param u16 The tracking data word. */
2431	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2432	/** @} */
2433
2434
2435	/**
2436	* Trees are using self relative offsets as pointers.
2437	* So, all its data, including the root pointer, must be in the heap for HC and GC
2438	* to have the same layout.
2439	*/
2440	typedef struct PGMTREES
2441	{
2442	/** Physical access handlers (AVL range+offsetptr tree). */
2443	AVLROGCPHYSTREE PhysHandlers;
2444	/** Virtual access handlers (AVL range + GC ptr tree). */
2445	AVLROGCPTRTREE VirtHandlers;
2446	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2447	AVLROGCPHYSTREE PhysToVirtHandlers;
2448	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2449	AVLROGCPTRTREE HyperVirtHandlers;
2450	} PGMTREES;
2451	/** Pointer to PGM trees. */
2452	typedef PGMTREES *PPGMTREES;
2453
2454
2455	/**
2456	* Page fault guest state for the AMD64 paging mode.
2457	*/
2458	typedef struct PGMPTWALKCORE
2459	{
2460	/** The guest virtual address that is being resolved by the walk
2461	* (input). */
2462	RTGCPTR GCPtr;
2463
2464	/** The guest physcial address that is the result of the walk.
2465	* @remarks only valid if fSucceeded is set. */
2466	RTGCPHYS GCPhys;
2467
2468	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2469	bool fSucceeded;
2470	/** The level problem arrised at.
2471	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2472	* level 8. This is 0 on success. */
2473	uint8_t uLevel;
2474	/** Set if the page isn't present. */
2475	bool fNotPresent;
2476	/** Encountered a bad physical address. */
2477	bool fBadPhysAddr;
2478	/** Set if there was reserved bit violations. */
2479	bool fRsvdError;
2480	/** Set if it involves a big page (2/4 MB). */
2481	bool fBigPage;
2482	/** Set if it involves a gigantic page (1 GB). */
2483	bool fGigantPage;
2484	/** The effect X86_PTE_US flag for the address. */
2485	bool fEffectiveUS;
2486	/** The effect X86_PTE_RW flag for the address. */
2487	bool fEffectiveRW;
2488	/** The effect X86_PTE_NX flag for the address. */
2489	bool fEffectiveNX;
2490	} PGMPTWALKCORE;
2491
2492
2493	/**
2494	* Guest page table walk for the AMD64 mode.
2495	*/
2496	typedef struct PGMPTWALKGSTAMD64
2497	{
2498	/** The common core. */
2499	PGMPTWALKCORE Core;
2500
2501	PX86PML4 pPml4;
2502	PX86PML4E pPml4e;
2503	X86PML4E Pml4e;
2504
2505	PX86PDPT pPdpt;
2506	PX86PDPE pPdpe;
2507	X86PDPE Pdpe;
2508
2509	PX86PDPAE pPd;
2510	PX86PDEPAE pPde;
2511	X86PDEPAE Pde;
2512
2513	PX86PTPAE pPt;
2514	PX86PTEPAE pPte;
2515	X86PTEPAE Pte;
2516	} PGMPTWALKGSTAMD64;
2517	/** Pointer to a AMD64 guest page table walk. */
2518	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2519	/** Pointer to a const AMD64 guest page table walk. */
2520	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2521
2522	/**
2523	* Guest page table walk for the PAE mode.
2524	*/
2525	typedef struct PGMPTWALKGSTPAE
2526	{
2527	/** The common core. */
2528	PGMPTWALKCORE Core;
2529
2530	PX86PDPT pPdpt;
2531	PX86PDPE pPdpe;
2532	X86PDPE Pdpe;
2533
2534	PX86PDPAE pPd;
2535	PX86PDEPAE pPde;
2536	X86PDEPAE Pde;
2537
2538	PX86PTPAE pPt;
2539	PX86PTEPAE pPte;
2540	X86PTEPAE Pte;
2541	} PGMPTWALKGSTPAE;
2542	/** Pointer to a PAE guest page table walk. */
2543	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2544	/** Pointer to a const AMD64 guest page table walk. */
2545	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2546
2547	/**
2548	* Guest page table walk for the 32-bit mode.
2549	*/
2550	typedef struct PGMPTWALKGST32BIT
2551	{
2552	/** The common core. */
2553	PGMPTWALKCORE Core;
2554
2555	PX86PD pPd;
2556	PX86PDE pPde;
2557	X86PDE Pde;
2558
2559	PX86PT pPt;
2560	PX86PTE pPte;
2561	X86PTE Pte;
2562	} PGMPTWALKGST32BIT;
2563	/** Pointer to a 32-bit guest page table walk. */
2564	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2565	/** Pointer to a const 32-bit guest page table walk. */
2566	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2567
2568
2569	/** @name Paging mode macros
2570	* @{
2571	*/
2572	#ifdef IN_RC
2573	# define PGM_CTX(a,b) a##RC##b
2574	# define PGM_CTX_STR(a,b) a "GC" b
2575	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2576	#else
2577	# ifdef IN_RING3
2578	# define PGM_CTX(a,b) a##R3##b
2579	# define PGM_CTX_STR(a,b) a "R3" b
2580	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2581	# else
2582	# define PGM_CTX(a,b) a##R0##b
2583	# define PGM_CTX_STR(a,b) a "R0" b
2584	# define PGM_CTX_DECL(type) VMMDECL(type)
2585	# endif
2586	#endif
2587
2588	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2589	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2590	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2591	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2592	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2593	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2594	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2595	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2596	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2597	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2598	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2599	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2600	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2601	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2602	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2603	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2604	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2605
2606	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2607	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2608	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2609	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2610	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2611	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2612	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2613	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2614	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2615	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2616	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2617	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2618	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2619	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2620	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2621	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2622	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2623
2624	/* Shw_Gst */
2625	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2626	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2627	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2628	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2629	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2630	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2631	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2632	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2633	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2634	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2635	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2636	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2637	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2638	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2639	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2640	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2641	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2642	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2643	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2644
2645	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2646	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2647	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2648	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2649	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2650	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2651	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2652	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2653	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2654	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2655	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2656	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2657	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2658	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2659	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2660	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2661	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2662	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2663	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2664	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2665	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2666	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2667	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2668	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2669	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2670	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2671	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2672	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2673	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2674	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2675	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2676	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2677	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2678	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2679	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2680	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2681	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2682
2683	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2684	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2685	/** @} */
2686
2687	/**
2688	* Data for each paging mode.
2689	*/
2690	typedef struct PGMMODEDATA
2691	{
2692	/** The guest mode type. */
2693	uint32_t uGstType;
2694	/** The shadow mode type. */
2695	uint32_t uShwType;
2696
2697	/** @name Function pointers for Shadow paging.
2698	* @{
2699	*/
2700	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2701	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2702	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2703	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2704
2705	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2706	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2707
2708	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2709	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2710	/** @} */
2711
2712	/** @name Function pointers for Guest paging.
2713	* @{
2714	*/
2715	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2716	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2717	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2718	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2719	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2720	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2721	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2722	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2723	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2724	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2725	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2726	/** @} */
2727
2728	/** @name Function pointers for Both Shadow and Guest paging.
2729	* @{
2730	*/
2731	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2732	/* no pfnR3BthTrap0eHandler */
2733	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2734	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2735	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2736	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2737	#ifdef VBOX_STRICT
2738	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2739	#endif
2740	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2741	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2742
2743	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2744	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2745	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2746	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2747	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2748	#ifdef VBOX_STRICT
2749	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2750	#endif
2751	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2752	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2753
2754	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2755	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2756	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2757	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2758	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2759	#ifdef VBOX_STRICT
2760	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2761	#endif
2762	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2763	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2764	/** @} */
2765	} PGMMODEDATA, *PPGMMODEDATA;
2766
2767
2768	#ifdef VBOX_WITH_STATISTICS
2769	/**
2770	* PGM statistics.
2771	*
2772	* These lives on the heap when compiled in as they would otherwise waste
2773	* unecessary space in release builds.
2774	*/
2775	typedef struct PGMSTATS
2776	{
2777	/* R3 only: */
2778	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2779	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2780
2781	/* R3+RZ */
2782	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2783	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2784	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2785	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2786	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2787	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2788	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2789	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2790	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2791	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2792	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2793	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2794	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2795	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2796	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2797	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2798	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2799	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2800	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2801	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2802	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2803	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2804	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2805	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2806	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2807	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2808	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2809	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2810
2811	/* RC only: */
2812	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2813	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2814
2815	STAMCOUNTER StatRZPhysRead;
2816	STAMCOUNTER StatRZPhysReadBytes;
2817	STAMCOUNTER StatRZPhysWrite;
2818	STAMCOUNTER StatRZPhysWriteBytes;
2819	STAMCOUNTER StatR3PhysRead;
2820	STAMCOUNTER StatR3PhysReadBytes;
2821	STAMCOUNTER StatR3PhysWrite;
2822	STAMCOUNTER StatR3PhysWriteBytes;
2823	STAMCOUNTER StatRCPhysRead;
2824	STAMCOUNTER StatRCPhysReadBytes;
2825	STAMCOUNTER StatRCPhysWrite;
2826	STAMCOUNTER StatRCPhysWriteBytes;
2827
2828	STAMCOUNTER StatRZPhysSimpleRead;
2829	STAMCOUNTER StatRZPhysSimpleReadBytes;
2830	STAMCOUNTER StatRZPhysSimpleWrite;
2831	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2832	STAMCOUNTER StatR3PhysSimpleRead;
2833	STAMCOUNTER StatR3PhysSimpleReadBytes;
2834	STAMCOUNTER StatR3PhysSimpleWrite;
2835	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2836	STAMCOUNTER StatRCPhysSimpleRead;
2837	STAMCOUNTER StatRCPhysSimpleReadBytes;
2838	STAMCOUNTER StatRCPhysSimpleWrite;
2839	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2840
2841	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2842	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2843	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2844	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2845	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2846	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2847	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2848
2849	/** Time spent by the host OS for large page allocation. */
2850	STAMPROFILE StatAllocLargePage;
2851	/** Time spent clearing the newly allocated large pages. */
2852	STAMPROFILE StatClearLargePage;
2853	/** pgmPhysIsValidLargePage profiling - R3 */
2854	STAMPROFILE StatR3IsValidLargePage;
2855	/** pgmPhysIsValidLargePage profiling - RZ*/
2856	STAMPROFILE StatRZIsValidLargePage;
2857
2858	STAMPROFILE StatChunkAging;
2859	STAMPROFILE StatChunkFindCandidate;
2860	STAMPROFILE StatChunkUnmap;
2861	STAMPROFILE StatChunkMap;
2862	} PGMSTATS;
2863	#endif /* VBOX_WITH_STATISTICS */
2864
2865
2866	/**
2867	* Converts a PGM pointer into a VM pointer.
2868	* @returns Pointer to the VM structure the PGM is part of.
2869	* @param pPGM Pointer to PGM instance data.
2870	*/
2871	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2872
2873	/**
2874	* PGM Data (part of VM)
2875	*/
2876	typedef struct PGM
2877	{
2878	/** Offset to the VM structure. */
2879	int32_t offVM;
2880	/** Offset of the PGMCPU structure relative to VMCPU. */
2881	int32_t offVCpuPGM;
2882
2883	/** @cfgm{RamPreAlloc, boolean, false}
2884	* Indicates whether the base RAM should all be allocated before starting
2885	* the VM (default), or if it should be allocated when first written to.
2886	*/
2887	bool fRamPreAlloc;
2888	/** Indicates whether write monitoring is currently in use.
2889	* This is used to prevent conflicts between live saving and page sharing
2890	* detection. */
2891	bool fPhysWriteMonitoringEngaged;
2892	/** Set if the CPU has less than 52-bit physical address width.
2893	* This is used */
2894	bool fLessThan52PhysicalAddressBits;
2895	/** Set when nested paging is active.
2896	* This is meant to save calls to HWACCMIsNestedPagingActive and let the
2897	* compilers optimize the code better. Whether we use nested paging or
2898	* not is something we find out during VMM initialization and we won't
2899	* change this later on. */
2900	bool fNestedPaging;
2901	/** The host paging mode. (This is what SUPLib reports.) */
2902	SUPPAGINGMODE enmHostMode;
2903	/** We're not in a state which permits writes to guest memory.
2904	* (Only used in strict builds.) */
2905	bool fNoMorePhysWrites;
2906	/** Alignment padding that makes the next member start on a 8 byte boundrary. */
2907	bool afAlignment1[3];
2908
2909	/** Indicates that PGMR3FinalizeMappings has been called and that further
2910	* PGMR3MapIntermediate calls will be rejected. */
2911	bool fFinalizedMappings;
2912	/** If set no conflict checks are required. */
2913	bool fMappingsFixed;
2914	/** If set if restored as fixed but we were unable to re-fixate at the old
2915	* location because of room or address incompatibilities. */
2916	bool fMappingsFixedRestored;
2917	/** If set, then no mappings are put into the shadow page table.
2918	* Use pgmMapAreMappingsEnabled() instead of direct access. */
2919	bool fMappingsDisabled;
2920	/** Size of fixed mapping.
2921	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2922	uint32_t cbMappingFixed;
2923	/** Generation ID for the RAM ranges. This member is incremented everytime
2924	* a RAM range is linked or unlinked. */
2925	uint32_t volatile idRamRangesGen;
2926
2927	/** Base address (GC) of fixed mapping.
2928	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2929	RTGCPTR GCPtrMappingFixed;
2930	/** The address of the previous RAM range mapping. */
2931	RTGCPTR GCPtrPrevRamRangeMapping;
2932
2933	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2934	RTGCPHYS GCPhys4MBPSEMask;
2935	/** Mask containing the invalid bits of a guest physical address.
2936	* @remarks this does not stop at bit 52. */
2937	RTGCPHYS GCPhysInvAddrMask;
2938
2939
2940	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2941	* This is sorted by physical address and contains no overlapping ranges. */
2942	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2943	/** PGM offset based trees - R3 Ptr. */
2944	R3PTRTYPE(PPGMTREES) pTreesR3;
2945	/** Caching the last physical handler we looked up in R3. */
2946	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2947	/** Shadow Page Pool - R3 Ptr. */
2948	R3PTRTYPE(PPGMPOOL) pPoolR3;
2949	/** Linked list of GC mappings - for HC.
2950	* The list is sorted ascending on address. */
2951	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2952	/** Pointer to the list of ROM ranges - for R3.
2953	* This is sorted by physical address and contains no overlapping ranges. */
2954	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2955	/** Pointer to the list of MMIO2 ranges - for R3.
2956	* Registration order. */
2957	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2958	/** Pointer to SHW+GST mode data (function pointers).
2959	* The index into this table is made up from */
2960	R3PTRTYPE(PPGMMODEDATA) paModeData;
2961	/RTR3PTR R3PtrAlignment0;/
2962
2963
2964	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2965	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2966	/** PGM offset based trees - R0 Ptr. */
2967	R0PTRTYPE(PPGMTREES) pTreesR0;
2968	/** Caching the last physical handler we looked up in R0. */
2969	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2970	/** Shadow Page Pool - R0 Ptr. */
2971	R0PTRTYPE(PPGMPOOL) pPoolR0;
2972	/** Linked list of GC mappings - for R0.
2973	* The list is sorted ascending on address. */
2974	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2975	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2976	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2977	/RTR0PTR R0PtrAlignment0;/
2978
2979
2980	/** RC pointer corresponding to PGM::pRamRangesR3. */
2981	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2982	/** PGM offset based trees - RC Ptr. */
2983	RCPTRTYPE(PPGMTREES) pTreesRC;
2984	/** Caching the last physical handler we looked up in RC. */
2985	RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
2986	/** Shadow Page Pool - RC Ptr. */
2987	RCPTRTYPE(PPGMPOOL) pPoolRC;
2988	/** Linked list of GC mappings - for RC.
2989	* The list is sorted ascending on address. */
2990	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2991	/** RC pointer corresponding to PGM::pRomRangesR3. */
2992	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2993	/RTRCPTR RCPtrAlignment0;/
2994	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2995	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2996	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2997	RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
2998
2999
3000	/** Pointer to the 5 page CR3 content mapping.
3001	* The first page is always the CR3 (in some form) while the 4 other pages
3002	* are used of the PDs in PAE mode. */
3003	RTGCPTR GCPtrCR3Mapping;
3004
3005	/** @name Intermediate Context
3006	* @{ */
3007	/** Pointer to the intermediate page directory - Normal. */
3008	R3PTRTYPE(PX86PD) pInterPD;
3009	/** Pointer to the intermedate page tables - Normal.
3010	* There are two page tables, one for the identity mapping and one for
3011	* the host context mapping (of the core code). */
3012	R3PTRTYPE(PX86PT) apInterPTs[2];
3013	/** Pointer to the intermedate page tables - PAE. */
3014	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3015	/** Pointer to the intermedate page directory - PAE. */
3016	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3017	/** Pointer to the intermedate page directory - PAE. */
3018	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3019	/** Pointer to the intermedate page-map level 4 - AMD64. */
3020	R3PTRTYPE(PX86PML4) pInterPaePML4;
3021	/** Pointer to the intermedate page directory - AMD64. */
3022	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3023	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3024	RTHCPHYS HCPhysInterPD;
3025	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3026	RTHCPHYS HCPhysInterPaePDPT;
3027	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3028	RTHCPHYS HCPhysInterPaePML4;
3029	/** @} */
3030
3031	/** Base address of the dynamic page mapping area.
3032	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3033	*
3034	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3035	* work out. Some cleaning up of the initialization that would
3036	* remove this memory is yet to be done...
3037	*/
3038	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3039	/** The address of the raw-mode context mapping cache. */
3040	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3041	/** The address of the ring-0 mapping cache if we're making use of it. */
3042	RTR0PTR pvR0DynMapUsed;
3043	#if HC_ARCH_BITS == 32
3044	/** Alignment padding that makes the next member start on a 8 byte boundrary. */
3045	uint32_t u32Alignment2;
3046	#endif
3047
3048	/** PGM critical section.
3049	* This protects the physical & virtual access handlers, ram ranges,
3050	* and the page flag updating (some of it anyway).
3051	*/
3052	PDMCRITSECT CritSect;
3053
3054	/**
3055	* Data associated with managing the ring-3 mappings of the allocation chunks.
3056	*/
3057	struct
3058	{
3059	/** The chunk tree, ordered by chunk id. */
3060	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3061	R3PTRTYPE(PAVLU32NODECORE) pTree;
3062	#else
3063	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3064	#endif
3065	#if HC_ARCH_BITS == 32
3066	uint32_t u32Alignment;
3067	#endif
3068	/** The chunk mapping TLB. */
3069	PGMCHUNKR3MAPTLB Tlb;
3070	/** The number of mapped chunks. */
3071	uint32_t c;
3072	/** The maximum number of mapped chunks.
3073	* @cfgm PGM/MaxRing3Chunks */
3074	uint32_t cMax;
3075	/** The current time. */
3076	uint32_t iNow;
3077	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3078	uint32_t AgeingCountdown;
3079	} ChunkR3Map;
3080
3081	/**
3082	* The page mapping TLB for ring-3 and (for the time being) ring-0.
3083	*/
3084	PGMPAGER3MAPTLB PhysTlbHC;
3085
3086	/** @name The zero page.
3087	* @{ */
3088	/** The host physical address of the zero page. */
3089	RTHCPHYS HCPhysZeroPg;
3090	/** The ring-3 mapping of the zero page. */
3091	RTR3PTR pvZeroPgR3;
3092	/** The ring-0 mapping of the zero page. */
3093	RTR0PTR pvZeroPgR0;
3094	/** The GC mapping of the zero page. */
3095	RTRCPTR pvZeroPgRC;
3096	RTRCPTR RCPtrAlignment3;
3097	/** @}*/
3098
3099	/** @name The Invalid MMIO page.
3100	* This page is filled with 0xfeedface.
3101	* @{ */
3102	/** The host physical address of the invalid MMIO page. */
3103	RTHCPHYS HCPhysMmioPg;
3104	/** The host pysical address of the invalid MMIO page pluss all invalid
3105	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3106	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3107	RTHCPHYS HCPhysInvMmioPg;
3108	/** The ring-3 mapping of the invalid MMIO page. */
3109	RTR3PTR pvMmioPgR3;
3110	#if HC_ARCH_BITS == 32
3111	RTR3PTR R3PtrAlignment4;
3112	#endif
3113	/** @} */
3114
3115
3116	/** The number of handy pages. */
3117	uint32_t cHandyPages;
3118
3119	/** The number of large handy pages. */
3120	uint32_t cLargeHandyPages;
3121
3122	/**
3123	* Array of handy pages.
3124	*
3125	* This array is used in a two way communication between pgmPhysAllocPage
3126	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3127	* an intermediary.
3128	*
3129	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3130	* (The current size of 32 pages, means 128 KB of handy memory.)
3131	*/
3132	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3133
3134	/**
3135	* Array of large handy pages. (currently size 1)
3136	*
3137	* This array is used in a two way communication between pgmPhysAllocLargePage
3138	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3139	* an intermediary.
3140	*/
3141	GMMPAGEDESC aLargeHandyPage[1];
3142
3143	/**
3144	* Live save data.
3145	*/
3146	struct
3147	{
3148	/** Per type statistics. */
3149	struct
3150	{
3151	/** The number of ready pages. */
3152	uint32_t cReadyPages;
3153	/** The number of dirty pages. */
3154	uint32_t cDirtyPages;
3155	/** The number of ready zero pages. */
3156	uint32_t cZeroPages;
3157	/** The number of write monitored pages. */
3158	uint32_t cMonitoredPages;
3159	} Rom,
3160	Mmio2,
3161	Ram;
3162	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3163	uint32_t cIgnoredPages;
3164	/** Indicates that a live save operation is active. */
3165	bool fActive;
3166	/** Padding. */
3167	bool afReserved[2];
3168	/** The next history index. */
3169	uint8_t iDirtyPagesHistory;
3170	/** History of the total amount of dirty pages. */
3171	uint32_t acDirtyPagesHistory[64];
3172	/** Short term dirty page average. */
3173	uint32_t cDirtyPagesShort;
3174	/** Long term dirty page average. */
3175	uint32_t cDirtyPagesLong;
3176	/** The number of saved pages. This is used to get some kind of estimate of the
3177	* link speed so we can decide when we're done. It is reset after the first
3178	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3179	* zero pages. */
3180	uint64_t cSavedPages;
3181	/** The nanosecond timestamp when cSavedPages was 0. */
3182	uint64_t uSaveStartNS;
3183	/** Pages per second (for statistics). */
3184	uint32_t cPagesPerSecond;
3185	uint32_t cAlignment;
3186	} LiveSave;
3187
3188	/** @name Error injection.
3189	* @{ */
3190	/** Inject handy page allocation errors pretending we're completely out of
3191	* memory. */
3192	bool volatile fErrInjHandyPages;
3193	/** Padding. */
3194	bool afReserved[3];
3195	/** @} */
3196
3197	/** @name Release Statistics
3198	* @{ */
3199	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3200	uint32_t cPrivatePages; /*< The number of private pages. /
3201	uint32_t cSharedPages; /*< The number of shared pages. /
3202	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3203	uint32_t cZeroPages; /*< The number of zero backed pages. /
3204	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3205	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3206	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3207	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3208	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3209	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3210	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3211	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3212	/* uint32_t aAlignment4[1]; */
3213
3214	/** The number of times we were forced to change the hypervisor region location. */
3215	STAMCOUNTER cRelocations;
3216
3217	STAMCOUNTER StatLargePageAlloc; /*< The number of large pages we've allocated./
3218	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3219	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3220	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3221	/** @} */
3222
3223	#ifdef VBOX_WITH_STATISTICS
3224	/** @name Statistics on the heap.
3225	* @{ */
3226	R3PTRTYPE(PGMSTATS *) pStatsR3;
3227	R0PTRTYPE(PGMSTATS *) pStatsR0;
3228	RCPTRTYPE(PGMSTATS *) pStatsRC;
3229	RTRCPTR RCPtrAlignment;
3230	/** @} */
3231	#endif
3232	} PGM;
3233	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3234	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3235	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3236	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3237	AssertCompileMemberAlignment(PGM, CritSect, 8);
3238	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3239	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3240	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3241	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3242	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3243	#endif /* !IN_TSTVMSTRUCTGC */
3244	/** Pointer to the PGM instance data. */
3245	typedef PGM *PPGM;
3246
3247
3248
3249	typedef struct PGMCPUSTATS
3250	{
3251	/* Common */
3252	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3253	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3254
3255	/* R0 only: */
3256	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3257	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3258
3259	/* RZ only: */
3260	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3261	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3262	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3263	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3264	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3265	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3266	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3267	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3268	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3269	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3270	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3271	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3272	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3273	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3274	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3275	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3276	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3277	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3278	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3279	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3280	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3281	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3282	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3283	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3284	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3285	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3286	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3287	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3288	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3289	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3290	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3291	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3292	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3293	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3294	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3295	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3296	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3297	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3298	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3299	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3300	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3301	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3302	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3303	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3304	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3305	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3306	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3307	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3308	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3309	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3310	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3311	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3312	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3313	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3314	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3315	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3316	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3317	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3318	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3319	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3320	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3321	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restorting to subset flushes. /
3322	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3323	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3324	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3325	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3326	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3327	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3328	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3329	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3330	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3331	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3332	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3333	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3334	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3335	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3336
3337	/* HC - R3 and (maybe) R0: */
3338
3339	/* RZ & R3: */
3340	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3341	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3342	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3343	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3344	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3345	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3346	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3347	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3348	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3349	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3350	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3351	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3352	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3353	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3354	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3355	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3356	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3357	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3358	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3359	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3360	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3361	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3362	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3363	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3364	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3365	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3366	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3367	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3368	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3369	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3370	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3371	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3372	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3373	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3374	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3375	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3376	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3377	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3378	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3379	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3380	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3381	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3382	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3383	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3384	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3385	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3386	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3387
3388	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3389	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3390	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3391	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3392	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3393	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3394	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3395	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3396	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3397	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3398	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3399	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3400	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3401	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3402	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3403	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3404	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3405	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3406	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3407	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3408	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3409	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3410	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3411	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3412	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3413	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3414	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3415	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3416	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3417	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3418	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3419	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3420	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3421	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3422	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3423	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3424	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3425	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3426	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3427	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3428	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3429	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3430	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3431	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3432	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3433	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3434	/** @} */
3435	} PGMCPUSTATS;
3436
3437
3438	/**
3439	* Converts a PGMCPU pointer into a VM pointer.
3440	* @returns Pointer to the VM structure the PGM is part of.
3441	* @param pPGM Pointer to PGMCPU instance data.
3442	*/
3443	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3444
3445	/**
3446	* Converts a PGMCPU pointer into a PGM pointer.
3447	* @returns Pointer to the VM structure the PGM is part of.
3448	* @param pPGM Pointer to PGMCPU instance data.
3449	*/
3450	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3451
3452	/**
3453	* PGMCPU Data (part of VMCPU).
3454	*/
3455	typedef struct PGMCPU
3456	{
3457	/** Offset to the VM structure. */
3458	int32_t offVM;
3459	/** Offset to the VMCPU structure. */
3460	int32_t offVCpu;
3461	/** Offset of the PGM structure relative to VMCPU. */
3462	int32_t offPGM;
3463	uint32_t uPadding0; /*< structure size alignment. /
3464
3465	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAW_MODE)
3466	/** Automatically tracked physical memory mapping set.
3467	* Ring-0 and strict raw-mode builds. */
3468	PGMMAPSET AutoSet;
3469	#endif
3470
3471	/** A20 gate mask.
3472	* Our current approach to A20 emulation is to let REM do it and don't bother
3473	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3474	* But whould need arrise, we'll subject physical addresses to this mask. */
3475	RTGCPHYS GCPhysA20Mask;
3476	/** A20 gate state - boolean! */
3477	bool fA20Enabled;
3478	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3479	bool fNoExecuteEnabled;
3480	/** Unused bits. */
3481	bool afUnused[2];
3482
3483	/** What needs syncing (PGM_SYNC_*).
3484	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3485	* PGMFlushTLB, and PGMR3Load. */
3486	RTUINT fSyncFlags;
3487
3488	/** The shadow paging mode. */
3489	PGMMODE enmShadowMode;
3490	/** The guest paging mode. */
3491	PGMMODE enmGuestMode;
3492
3493	/** The current physical address representing in the guest CR3 register. */
3494	RTGCPHYS GCPhysCR3;
3495
3496	/** @name 32-bit Guest Paging.
3497	* @{ */
3498	/** The guest's page directory, R3 pointer. */
3499	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3500	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3501	/** The guest's page directory, R0 pointer. */
3502	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3503	#endif
3504	/** The guest's page directory, static RC mapping. */
3505	RCPTRTYPE(PX86PD) pGst32BitPdRC;
3506	/** Mask containing the MBZ bits of a big page PDE. */
3507	uint32_t fGst32BitMbzBigPdeMask;
3508	/** Set if the page size extension (PSE) is enabled. */
3509	bool fGst32BitPageSizeExtension;
3510	/** Alignment padding. */
3511	bool afAlignment2[3];
3512	/** @} */
3513
3514	/** @name PAE Guest Paging.
3515	* @{ */
3516	/** The guest's page directory pointer table, static RC mapping. */
3517	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3518	/** The guest's page directory pointer table, R3 pointer. */
3519	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3520	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3521	/** The guest's page directory pointer table, R0 pointer. */
3522	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3523	#endif
3524
3525	/** The guest's page directories, R3 pointers.
3526	* These are individual pointers and don't have to be adjecent.
3527	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3528	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3529	/** The guest's page directories, R0 pointers.
3530	* Same restrictions as apGstPaePDsR3. */
3531	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3532	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3533	#endif
3534	/** The guest's page directories, static GC mapping.
3535	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3536	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3537	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3538	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3539	RTGCPHYS aGCPhysGstPaePDs[4];
3540	/** The physical addresses of the monitored guest page directories (PAE). */
3541	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3542	/** Mask containing the MBZ PTE bits. */
3543	uint64_t fGstPaeMbzPteMask;
3544	/** Mask containing the MBZ PDE bits. */
3545	uint64_t fGstPaeMbzPdeMask;
3546	/** Mask containing the MBZ big page PDE bits. */
3547	uint64_t fGstPaeMbzBigPdeMask;
3548	/** Mask containing the MBZ PDPE bits. */
3549	uint64_t fGstPaeMbzPdpeMask;
3550	/** @} */
3551
3552	/** @name AMD64 Guest Paging.
3553	* @{ */
3554	/** The guest's page directory pointer table, R3 pointer. */
3555	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3556	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3557	/** The guest's page directory pointer table, R0 pointer. */
3558	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3559	#else
3560	RTR0PTR alignment6b; /*< alignment equalizer. /
3561	#endif
3562	/** Mask containing the MBZ PTE bits. */
3563	uint64_t fGstAmd64MbzPteMask;
3564	/** Mask containing the MBZ PDE bits. */
3565	uint64_t fGstAmd64MbzPdeMask;
3566	/** Mask containing the MBZ big page PDE bits. */
3567	uint64_t fGstAmd64MbzBigPdeMask;
3568	/** Mask containing the MBZ PDPE bits. */
3569	uint64_t fGstAmd64MbzPdpeMask;
3570	/** Mask containing the MBZ big page PDPE bits. */
3571	uint64_t fGstAmd64MbzBigPdpeMask;
3572	/** Mask containing the MBZ PML4E bits. */
3573	uint64_t fGstAmd64MbzPml4eMask;
3574	/** @} */
3575
3576	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3577	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3578	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3579	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3580	/** Pointer to the page of the current active CR3 - RC Ptr. */
3581	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3582	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3583	uint32_t iShwUser;
3584	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3585	uint32_t iShwUserTable;
3586	# if HC_ARCH_BITS == 64
3587	RTRCPTR alignment6; /*< structure size alignment. /
3588	# endif
3589	/** @} */
3590
3591	/** @name Function pointers for Shadow paging.
3592	* @{
3593	*/
3594	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3595	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3596	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3597	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3598
3599	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3600	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3601
3602	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3603	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3604
3605	/** @} */
3606
3607	/** @name Function pointers for Guest paging.
3608	* @{
3609	*/
3610	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3611	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3612	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3613	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3614	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3615	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3616	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3617	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3618	#if HC_ARCH_BITS == 64
3619	RTRCPTR alignment3; /*< structure size alignment. /
3620	#endif
3621
3622	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3623	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3624	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3625	/** @} */
3626
3627	/** @name Function pointers for Both Shadow and Guest paging.
3628	* @{
3629	*/
3630	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3631	/* no pfnR3BthTrap0eHandler */
3632	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3633	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3634	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3635	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3636	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3637	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3638	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3639
3640	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3641	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3642	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3643	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3644	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3645	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3646	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3647	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3648
3649	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3650	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3651	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3652	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3653	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3654	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3655	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3656	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3657	#if 0
3658	RTRCPTR alignment2; /*< structure size alignment. /
3659	#endif
3660	/** @} */
3661
3662	/** For saving stack space, the disassembler state is allocated here instead of
3663	* on the stack.
3664	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3665	union
3666	{
3667	/** The disassembler scratch space. */
3668	DISCPUSTATE DisState;
3669	/** Padding. */
3670	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3671	};
3672
3673	/** Count the number of pgm pool access handler calls. */
3674	uint64_t cPoolAccessHandler;
3675
3676	/** @name Release Statistics
3677	* @{ */
3678	/** The number of times the guest has switched mode since last reset or statistics reset. */
3679	STAMCOUNTER cGuestModeChanges;
3680	/** @} */
3681
3682	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3683	/** @name Statistics
3684	* @{ */
3685	/** RC: Pointer to the statistics. */
3686	RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3687	/** RC: Which statistic this \#PF should be attributed to. */
3688	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3689	/** R0: Pointer to the statistics. */
3690	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3691	/** R0: Which statistic this \#PF should be attributed to. */
3692	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3693	/** R3: Pointer to the statistics. */
3694	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3695	/** Alignment padding. */
3696	RTR3PTR pPaddingR3;
3697	/** @} */
3698	#endif /* VBOX_WITH_STATISTICS */
3699	} PGMCPU;
3700	/** Pointer to the per-cpu PGM data. */
3701	typedef PGMCPU *PPGMCPU;
3702
3703
3704	/** @name PGM::fSyncFlags Flags
3705	* @{
3706	*/
3707	/** Updates the virtual access handler state bit in PGMPAGE. */
3708	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3709	/** Always sync CR3. */
3710	#define PGM_SYNC_ALWAYS RT_BIT(1)
3711	/** Check monitoring on next CR3 (re)load and invalidate page.
3712	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3713	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3714	/** Check guest mapping in SyncCR3. */
3715	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3716	/** Clear the page pool (a light weight flush). */
3717	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3718	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3719	/** @} */
3720
3721
3722	RT_C_DECLS_BEGIN
3723
3724	int pgmLock(PVM pVM);
3725	void pgmUnlock(PVM pVM);
3726
3727	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3728	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3729	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3730	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3731	int pgmMapResolveConflicts(PVM pVM);
3732	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3733
3734	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3735	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3736	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3737	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
3738	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3739	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
3740	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3741	#else
3742	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3743	#endif
3744	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3745	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3746
3747	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3748	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3749	int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3750	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3751	int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3752	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3753	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3754	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3755	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3756	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3757	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3758	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3759	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3760	VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3761	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3762	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3763
3764	#ifdef IN_RING3
3765	void pgmR3PhysRelinkRamRanges(PVM pVM);
3766	int pgmR3PhysRamPreAllocate(PVM pVM);
3767	int pgmR3PhysRamReset(PVM pVM);
3768	int pgmR3PhysRomReset(PVM pVM);
3769	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3770	int pgmR3PhysRamTerm(PVM pVM);
3771	void pgmR3PhysRomTerm(PVM pVM);
3772
3773	int pgmR3PoolInit(PVM pVM);
3774	void pgmR3PoolRelocate(PVM pVM);
3775	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3776	void pgmR3PoolReset(PVM pVM);
3777	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3778	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3779
3780	#endif /* IN_RING3 */
3781	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| IN_RC
3782	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3783	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3784	# ifdef LOG_ENABLED
3785	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3786	# else
3787	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3788	# endif
3789	#endif
3790	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3791
3792	DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3793	{
3794	return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3795	}
3796
3797	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3798	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3799	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3800	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3801	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3802	int pgmPoolSyncCR3(PVMCPU pVCpu);
3803	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3804	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3805	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3806	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3807	DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3808	{
3809	return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3810	}
3811
3812	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3813	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3814	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3815	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3816	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3817
3818	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3819	void pgmPoolResetDirtyPages(PVM pVM);
3820
3821	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3822	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3823
3824	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3825	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3826	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3827	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3828
3829	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3830	int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3831
3832	int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3833	int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3834	int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3835	int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3836
3837	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3838	DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3839	DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3840	# endif
3841
3842	RT_C_DECLS_END
3843
3844	/** @} */
3845
3846	#endif
3847

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 31834

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