VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 32043

Last change on this file since 32043 was 32043, checked in by vboxsync, 14 years ago

PGM: Re-enabled the code that previously cause w7-64 regressions. (We no longer sync any unncessary bits.)
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1/* $Id: PGMInternal.h 32043 2010-08-27 11:47:17Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm.h>
28#include <VBox/mm.h>
29#include <VBox/pdmcritsect.h>
30#include <VBox/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/gmm.h>
35#include <VBox/hwaccm.h>
36#include <VBox/hwacc_vmx.h>
37#include <include/internal/pgm.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 0 /* ! remember to disable before committing ! XXX TODO */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark Use with care as we don't have so much dynamic mapping space in
237 * ring-0 on 32-bit darwin and in RC.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243#else
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_GCPHYS_2_PTR_V2
249 * Maps a GC physical page address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM handle.
253 * @param pVCpu The current CPU.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark Use with care as we don't have so much dynamic mapping space in
258 * ring-0 on 32-bit darwin and in RC.
259 * @remark There is no need to assert on the result.
260 */
261#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
262# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264#else
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM handle.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark Use with care as we don't have so much dynamic mapping space in
278 * ring-0 on 32-bit darwin and in RC.
279 * @remark There is no need to assert on the result.
280 */
281#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVCpu The current CPU.
288 * @param GCPhys The GC physical address to map to a virtual one.
289 * @param ppv Where to store the virtual address. No need to cast this.
290 *
291 * @remark Use with care as we don't have so much dynamic mapping space in
292 * ring-0 on 32-bit darwin and in RC.
293 * @remark There is no need to assert on the result.
294 */
295#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_DYNMAP_UNUSED_HINT
318 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319 * is no longer used.
320 *
321 * For best effect only apply this to the page that was mapped most recently.
322 *
323 * @param pVCpu The current CPU.
324 * @param pPage The pool page.
325 */
326#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327# ifdef LOG_ENABLED
328# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329# else
330# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331# endif
332#else
333# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334#endif
335
336/** @def PGM_DYNMAP_UNUSED_HINT_VM
337 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338 * is no longer used.
339 *
340 * For best effect only apply this to the page that was mapped most recently.
341 *
342 * @param pVM The VM handle.
343 * @param pPage The pool page.
344 */
345#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348/** @def PGM_INVL_PG
349 * Invalidates a page.
350 *
351 * @param pVCpu The VMCPU handle.
352 * @param GCVirt The virtual address of the page to invalidate.
353 */
354#ifdef IN_RC
355# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356#elif defined(IN_RING0)
357# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_PG_ALL_VCPU
363 * Invalidates a page on all VCPUs
364 *
365 * @param pVM The VM handle.
366 * @param GCVirt The virtual address of the page to invalidate.
367 */
368#ifdef IN_RC
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370#elif defined(IN_RING0)
371# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372#else
373# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374#endif
375
376/** @def PGM_INVL_BIG_PG
377 * Invalidates a 4MB page directory entry.
378 *
379 * @param pVCpu The VMCPU handle.
380 * @param GCVirt The virtual address within the page directory to invalidate.
381 */
382#ifdef IN_RC
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384#elif defined(IN_RING0)
385# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386#else
387# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388#endif
389
390/** @def PGM_INVL_VCPU_TLBS()
391 * Invalidates the TLBs of the specified VCPU
392 *
393 * @param pVCpu The VMCPU handle.
394 */
395#ifdef IN_RC
396# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397#elif defined(IN_RING0)
398# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399#else
400# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401#endif
402
403/** @def PGM_INVL_ALL_VCPU_TLBS()
404 * Invalidates the TLBs of all VCPUs
405 *
406 * @param pVM The VM handle.
407 */
408#ifdef IN_RC
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410#elif defined(IN_RING0)
411# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412#else
413# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414#endif
415
416
417/** @name Safer Shadow PAE PT/PTE
418 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419 * present.
420 *
421 * @{
422 */
423#if 1
424/**
425 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
426 * invalid entries for present.
427 * @sa X86PTEPAE.
428 */
429typedef union PGMSHWPTEPAE
430{
431 /** Unsigned integer view */
432 X86PGPAEUINT uCareful;
433 /* Not other views. */
434} PGMSHWPTEPAE;
435
436# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
443# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
446# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
452
453/**
454 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
455 * invalid entries for present.
456 * @sa X86PTPAE.
457 */
458typedef struct PGMSHWPTPAE
459{
460 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461} PGMSHWPTPAE;
462
463#else
464typedef X86PTEPAE PGMSHWPTEPAE;
465typedef X86PTPAE PGMSHWPTPAE;
466# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
473# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
476# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
482
483#endif
484
485/** Pointer to a shadow PAE PTE. */
486typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487/** Pointer to a const shadow PAE PTE. */
488typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490/** Pointer to a shadow PAE page table. */
491typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492/** Pointer to a const shadow PAE page table. */
493typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494/** @} */
495
496
497/** Size of the GCPtrConflict array in PGMMAPPING.
498 * @remarks Must be a power of two. */
499#define PGMMAPPING_CONFLICT_MAX 8
500
501/**
502 * Structure for tracking GC Mappings.
503 *
504 * This structure is used by linked list in both GC and HC.
505 */
506typedef struct PGMMAPPING
507{
508 /** Pointer to next entry. */
509 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510 /** Pointer to next entry. */
511 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512 /** Pointer to next entry. */
513 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514 /** Indicate whether this entry is finalized. */
515 bool fFinalized;
516 /** Start Virtual address. */
517 RTGCPTR GCPtr;
518 /** Last Virtual address (inclusive). */
519 RTGCPTR GCPtrLast;
520 /** Range size (bytes). */
521 RTGCPTR cb;
522 /** Pointer to relocation callback function. */
523 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524 /** User argument to the callback. */
525 R3PTRTYPE(void *) pvUser;
526 /** Mapping description / name. For easing debugging. */
527 R3PTRTYPE(const char *) pszDesc;
528 /** Last 8 addresses that caused conflicts. */
529 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530 /** Number of conflicts for this hypervisor mapping. */
531 uint32_t cConflicts;
532 /** Number of page tables. */
533 uint32_t cPTs;
534
535 /** Array of page table mapping data. Each entry
536 * describes one page table. The array can be longer
537 * than the declared length.
538 */
539 struct
540 {
541 /** The HC physical address of the page table. */
542 RTHCPHYS HCPhysPT;
543 /** The HC physical address of the first PAE page table. */
544 RTHCPHYS HCPhysPaePT0;
545 /** The HC physical address of the second PAE page table. */
546 RTHCPHYS HCPhysPaePT1;
547 /** The HC virtual address of the 32-bit page table. */
548 R3PTRTYPE(PX86PT) pPTR3;
549 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551 /** The RC virtual address of the 32-bit page table. */
552 RCPTRTYPE(PX86PT) pPTRC;
553 /** The RC virtual address of the two PAE page table. */
554 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555 /** The R0 virtual address of the 32-bit page table. */
556 R0PTRTYPE(PX86PT) pPTR0;
557 /** The R0 virtual address of the two PAE page table. */
558 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559 } aPTs[1];
560} PGMMAPPING;
561/** Pointer to structure for tracking GC Mappings. */
562typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565/**
566 * Physical page access handler structure.
567 *
568 * This is used to keep track of physical address ranges
569 * which are being monitored in some kind of way.
570 */
571typedef struct PGMPHYSHANDLER
572{
573 AVLROGCPHYSNODECORE Core;
574 /** Access type. */
575 PGMPHYSHANDLERTYPE enmType;
576 /** Number of pages to update. */
577 uint32_t cPages;
578 /** Pointer to R3 callback function. */
579 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
580 /** User argument for R3 handlers. */
581 R3PTRTYPE(void *) pvUserR3;
582 /** Pointer to R0 callback function. */
583 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
584 /** User argument for R0 handlers. */
585 R0PTRTYPE(void *) pvUserR0;
586 /** Pointer to RC callback function. */
587 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
588 /** User argument for RC handlers. */
589 RCPTRTYPE(void *) pvUserRC;
590 /** Description / Name. For easing debugging. */
591 R3PTRTYPE(const char *) pszDesc;
592#ifdef VBOX_WITH_STATISTICS
593 /** Profiling of this handler. */
594 STAMPROFILE Stat;
595#endif
596} PGMPHYSHANDLER;
597/** Pointer to a physical page access handler structure. */
598typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
599
600
601/**
602 * Cache node for the physical addresses covered by a virtual handler.
603 */
604typedef struct PGMPHYS2VIRTHANDLER
605{
606 /** Core node for the tree based on physical ranges. */
607 AVLROGCPHYSNODECORE Core;
608 /** Offset from this struct to the PGMVIRTHANDLER structure. */
609 int32_t offVirtHandler;
610 /** Offset of the next alias relative to this one.
611 * Bit 0 is used for indicating whether we're in the tree.
612 * Bit 1 is used for indicating that we're the head node.
613 */
614 int32_t offNextAlias;
615} PGMPHYS2VIRTHANDLER;
616/** Pointer to a phys to virtual handler structure. */
617typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
618
619/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
620 * node is in the tree. */
621#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
622/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
623 * node is in the head of an alias chain.
624 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
625#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
626/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
627#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
628
629
630/**
631 * Virtual page access handler structure.
632 *
633 * This is used to keep track of virtual address ranges
634 * which are being monitored in some kind of way.
635 */
636typedef struct PGMVIRTHANDLER
637{
638 /** Core node for the tree based on virtual ranges. */
639 AVLROGCPTRNODECORE Core;
640 /** Size of the range (in bytes). */
641 RTGCPTR cb;
642 /** Number of cache pages. */
643 uint32_t cPages;
644 /** Access type. */
645 PGMVIRTHANDLERTYPE enmType;
646 /** Pointer to the RC callback function. */
647 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
648#if HC_ARCH_BITS == 64
649 RTRCPTR padding;
650#endif
651 /** Pointer to the R3 callback function for invalidation. */
652 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
653 /** Pointer to the R3 callback function. */
654 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
655 /** Description / Name. For easing debugging. */
656 R3PTRTYPE(const char *) pszDesc;
657#ifdef VBOX_WITH_STATISTICS
658 /** Profiling of this handler. */
659 STAMPROFILE Stat;
660#endif
661 /** Array of cached physical addresses for the monitored ranged. */
662 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
663} PGMVIRTHANDLER;
664/** Pointer to a virtual page access handler structure. */
665typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
666
667
668/**
669 * Page type.
670 *
671 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
672 * @remarks This is used in the saved state, so changes to it requires bumping
673 * the saved state version.
674 * @todo So, convert to \#defines!
675 */
676typedef enum PGMPAGETYPE
677{
678 /** The usual invalid zero entry. */
679 PGMPAGETYPE_INVALID = 0,
680 /** RAM page. (RWX) */
681 PGMPAGETYPE_RAM,
682 /** MMIO2 page. (RWX) */
683 PGMPAGETYPE_MMIO2,
684 /** MMIO2 page aliased over an MMIO page. (RWX)
685 * See PGMHandlerPhysicalPageAlias(). */
686 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
687 /** Shadowed ROM. (RWX) */
688 PGMPAGETYPE_ROM_SHADOW,
689 /** ROM page. (R-X) */
690 PGMPAGETYPE_ROM,
691 /** MMIO page. (---) */
692 PGMPAGETYPE_MMIO,
693 /** End of valid entries. */
694 PGMPAGETYPE_END
695} PGMPAGETYPE;
696AssertCompile(PGMPAGETYPE_END <= 7);
697
698/** @name Page type predicates.
699 * @{ */
700#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
701#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
702#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
703#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
704#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
705/** @} */
706
707
708/**
709 * A Physical Guest Page tracking structure.
710 *
711 * The format of this structure is complicated because we have to fit a lot
712 * of information into as few bits as possible. The format is also subject
713 * to change (there is one comming up soon). Which means that for we'll be
714 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
715 * accesses to the structure.
716 */
717typedef struct PGMPAGE
718{
719 /** The physical address and the Page ID. */
720 RTHCPHYS HCPhysAndPageID;
721 /** Combination of:
722 * - [0-7]: u2HandlerPhysStateY - the physical handler state
723 * (PGM_PAGE_HNDL_PHYS_STATE_*).
724 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
725 * (PGM_PAGE_HNDL_VIRT_STATE_*).
726 * - [10]: u1FTDirty - indicator of dirty page for fault tolerance tracking
727 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
728 * - [15]: fWrittenToY - flag indicating that a write monitored page was
729 * written to when set.
730 * - [11-13]: 3 unused bits.
731 * @remarks Warning! All accesses to the bits are hardcoded.
732 *
733 * @todo Change this to a union with both bitfields, u8 and u accessors.
734 * That'll help deal with some of the hardcoded accesses.
735 *
736 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
737 * will make it possible to turn some of the 16-bit accesses into
738 * 32-bit ones, which may be efficient (stalls).
739 */
740 RTUINT16U u16MiscY;
741 /** The page state.
742 * Only 3 bits are really needed for this. */
743 uint16_t uStateY : 3;
744 /** The page type (PGMPAGETYPE).
745 * Only 3 bits are really needed for this. */
746 uint16_t uTypeY : 3;
747 /** PTE index for usage tracking (page pool). */
748 uint16_t uPteIdx : 10;
749 /** Usage tracking (page pool). */
750 uint16_t u16TrackingY;
751 /** The number of read locks on this page. */
752 uint8_t cReadLocksY;
753 /** The number of write locks on this page. */
754 uint8_t cWriteLocksY;
755} PGMPAGE;
756AssertCompileSize(PGMPAGE, 16);
757/** Pointer to a physical guest page. */
758typedef PGMPAGE *PPGMPAGE;
759/** Pointer to a const physical guest page. */
760typedef const PGMPAGE *PCPGMPAGE;
761/** Pointer to a physical guest page pointer. */
762typedef PPGMPAGE *PPPGMPAGE;
763
764
765/**
766 * Clears the page structure.
767 * @param pPage Pointer to the physical guest page tracking structure.
768 */
769#define PGM_PAGE_CLEAR(pPage) \
770 do { \
771 (pPage)->HCPhysAndPageID = 0; \
772 (pPage)->uStateY = 0; \
773 (pPage)->uTypeY = 0; \
774 (pPage)->uPteIdx = 0; \
775 (pPage)->u16MiscY.u = 0; \
776 (pPage)->u16TrackingY = 0; \
777 (pPage)->cReadLocksY = 0; \
778 (pPage)->cWriteLocksY = 0; \
779 } while (0)
780
781/**
782 * Initializes the page structure.
783 * @param pPage Pointer to the physical guest page tracking structure.
784 */
785#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
786 do { \
787 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
788 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
789 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
790 (pPage)->uStateY = (_uState); \
791 (pPage)->uTypeY = (_uType); \
792 (pPage)->uPteIdx = 0; \
793 (pPage)->u16MiscY.u = 0; \
794 (pPage)->u16TrackingY = 0; \
795 (pPage)->cReadLocksY = 0; \
796 (pPage)->cWriteLocksY = 0; \
797 } while (0)
798
799/**
800 * Initializes the page structure of a ZERO page.
801 * @param pPage Pointer to the physical guest page tracking structure.
802 * @param pVM The VM handle (for getting the zero page address).
803 * @param uType The page type (PGMPAGETYPE).
804 */
805#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
806 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
807
808
809/** @name The Page state, PGMPAGE::uStateY.
810 * @{ */
811/** The zero page.
812 * This is a per-VM page that's never ever mapped writable. */
813#define PGM_PAGE_STATE_ZERO 0
814/** A allocated page.
815 * This is a per-VM page allocated from the page pool (or wherever
816 * we get MMIO2 pages from if the type is MMIO2).
817 */
818#define PGM_PAGE_STATE_ALLOCATED 1
819/** A allocated page that's being monitored for writes.
820 * The shadow page table mappings are read-only. When a write occurs, the
821 * fWrittenTo member is set, the page remapped as read-write and the state
822 * moved back to allocated. */
823#define PGM_PAGE_STATE_WRITE_MONITORED 2
824/** The page is shared, aka. copy-on-write.
825 * This is a page that's shared with other VMs. */
826#define PGM_PAGE_STATE_SHARED 3
827/** The page is ballooned, so no longer available for this VM. */
828#define PGM_PAGE_STATE_BALLOONED 4
829/** @} */
830
831
832/**
833 * Gets the page state.
834 * @returns page state (PGM_PAGE_STATE_*).
835 * @param pPage Pointer to the physical guest page tracking structure.
836 */
837#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
838
839/**
840 * Sets the page state.
841 * @param pPage Pointer to the physical guest page tracking structure.
842 * @param _uState The new page state.
843 */
844#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
845
846
847/**
848 * Gets the host physical address of the guest page.
849 * @returns host physical address (RTHCPHYS).
850 * @param pPage Pointer to the physical guest page tracking structure.
851 */
852#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
853
854/**
855 * Sets the host physical address of the guest page.
856 * @param pPage Pointer to the physical guest page tracking structure.
857 * @param _HCPhys The new host physical address.
858 */
859#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
860 do { \
861 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
862 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
863 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
864 | (SetHCPhysTmp << (28-12)); \
865 } while (0)
866
867/**
868 * Get the Page ID.
869 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
870 * @param pPage Pointer to the physical guest page tracking structure.
871 */
872#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
873
874/**
875 * Sets the Page ID.
876 * @param pPage Pointer to the physical guest page tracking structure.
877 */
878#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
879 do { \
880 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
881 | ((_idPage) & UINT32_C(0x0fffffff)); \
882 } while (0)
883
884/**
885 * Get the Chunk ID.
886 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
887 * @param pPage Pointer to the physical guest page tracking structure.
888 */
889#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
890
891/**
892 * Get the index of the page within the allocation chunk.
893 * @returns The page index.
894 * @param pPage Pointer to the physical guest page tracking structure.
895 */
896#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
897
898/**
899 * Gets the page type.
900 * @returns The page type.
901 * @param pPage Pointer to the physical guest page tracking structure.
902 */
903#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
904
905/**
906 * Sets the page type.
907 * @param pPage Pointer to the physical guest page tracking structure.
908 * @param _enmType The new page type (PGMPAGETYPE).
909 */
910#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
911
912/**
913 * Gets the page table index
914 * @returns The page table index.
915 * @param pPage Pointer to the physical guest page tracking structure.
916 */
917#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
918
919/**
920 * Sets the page table index
921 * @param pPage Pointer to the physical guest page tracking structure.
922 * @param iPte New page table index.
923 */
924#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
925
926/**
927 * Checks if the page is marked for MMIO.
928 * @returns true/false.
929 * @param pPage Pointer to the physical guest page tracking structure.
930 */
931#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
932
933/**
934 * Checks if the page is backed by the ZERO page.
935 * @returns true/false.
936 * @param pPage Pointer to the physical guest page tracking structure.
937 */
938#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
939
940/**
941 * Checks if the page is backed by a SHARED page.
942 * @returns true/false.
943 * @param pPage Pointer to the physical guest page tracking structure.
944 */
945#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
946
947/**
948 * Checks if the page is ballooned.
949 * @returns true/false.
950 * @param pPage Pointer to the physical guest page tracking structure.
951 */
952#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
953
954/**
955 * Marks the page as written to (for GMM change monitoring).
956 * @param pPage Pointer to the physical guest page tracking structure.
957 */
958#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
959
960/**
961 * Clears the written-to indicator.
962 * @param pPage Pointer to the physical guest page tracking structure.
963 */
964#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
965
966/**
967 * Checks if the page was marked as written-to.
968 * @returns true/false.
969 * @param pPage Pointer to the physical guest page tracking structure.
970 */
971#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
972
973/**
974 * Marks the page as dirty for FTM
975 * @param pPage Pointer to the physical guest page tracking structure.
976 */
977#define PGM_PAGE_SET_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x04); } while (0)
978
979/**
980 * Clears the FTM dirty indicator
981 * @param pPage Pointer to the physical guest page tracking structure.
982 */
983#define PGM_PAGE_CLEAR_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0xfb); } while (0)
984
985/**
986 * Checks if the page was marked as dirty for FTM
987 * @returns true/false.
988 * @param pPage Pointer to the physical guest page tracking structure.
989 */
990#define PGM_PAGE_IS_FT_DIRTY(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x04)) )
991
992
993/** @name PT usage values (PGMPAGE::u2PDEType).
994 *
995 * @{ */
996/** Either as a PT or PDE. */
997#define PGM_PAGE_PDE_TYPE_DONTCARE 0
998/** Must use a page table to map the range. */
999#define PGM_PAGE_PDE_TYPE_PT 1
1000/** Can use a page directory entry to map the continous range. */
1001#define PGM_PAGE_PDE_TYPE_PDE 2
1002/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
1003#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1004/** @} */
1005
1006/**
1007 * Set the PDE type of the page
1008 * @param pPage Pointer to the physical guest page tracking structure.
1009 * @param uType PGM_PAGE_PDE_TYPE_*
1010 */
1011#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
1012 do { \
1013 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
1014 | (((uType) & UINT8_C(0x03)) << 5); \
1015 } while (0)
1016
1017/**
1018 * Checks if the page was marked being part of a large page
1019 * @returns true/false.
1020 * @param pPage Pointer to the physical guest page tracking structure.
1021 */
1022#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
1023
1024/** Enabled optimized access handler tests.
1025 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
1026 * layout. When enabled, the compiler should normally generate more compact
1027 * code.
1028 */
1029#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1030
1031/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1032 *
1033 * @remarks The values are assigned in order of priority, so we can calculate
1034 * the correct state for a page with different handlers installed.
1035 * @{ */
1036/** No handler installed. */
1037#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1038/** Monitoring is temporarily disabled. */
1039#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1040/** Write access is monitored. */
1041#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1042/** All access is monitored. */
1043#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1044/** @} */
1045
1046/**
1047 * Gets the physical access handler state of a page.
1048 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1049 * @param pPage Pointer to the physical guest page tracking structure.
1050 */
1051#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
1052 ( (pPage)->u16MiscY.au8[0] )
1053
1054/**
1055 * Sets the physical access handler state of a page.
1056 * @param pPage Pointer to the physical guest page tracking structure.
1057 * @param _uState The new state value.
1058 */
1059#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
1060 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
1061
1062/**
1063 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
1064 * @returns true/false
1065 * @param pPage Pointer to the physical guest page tracking structure.
1066 */
1067#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
1068 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1069
1070/**
1071 * Checks if the page has any active physical access handlers.
1072 * @returns true/false
1073 * @param pPage Pointer to the physical guest page tracking structure.
1074 */
1075#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
1076 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1077
1078
1079/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1080 *
1081 * @remarks The values are assigned in order of priority, so we can calculate
1082 * the correct state for a page with different handlers installed.
1083 * @{ */
1084/** No handler installed. */
1085#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1086/* 1 is reserved so the lineup is identical with the physical ones. */
1087/** Write access is monitored. */
1088#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1089/** All access is monitored. */
1090#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1091/** @} */
1092
1093/**
1094 * Gets the virtual access handler state of a page.
1095 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1096 * @param pPage Pointer to the physical guest page tracking structure.
1097 */
1098#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
1099
1100/**
1101 * Sets the virtual access handler state of a page.
1102 * @param pPage Pointer to the physical guest page tracking structure.
1103 * @param _uState The new state value.
1104 */
1105#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1106 do { \
1107 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1108 | ((_uState) & UINT8_C(0x03)); \
1109 } while (0)
1110
1111/**
1112 * Checks if the page has any virtual access handlers.
1113 * @returns true/false
1114 * @param pPage Pointer to the physical guest page tracking structure.
1115 */
1116#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1117 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1118
1119/**
1120 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1121 * virtual handlers.
1122 * @returns true/false
1123 * @param pPage Pointer to the physical guest page tracking structure.
1124 */
1125#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1126 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1127
1128
1129/**
1130 * Checks if the page has any access handlers, including temporarily disabled ones.
1131 * @returns true/false
1132 * @param pPage Pointer to the physical guest page tracking structure.
1133 */
1134#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1135# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1136 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1137#else
1138# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1139 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1140 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1141#endif
1142
1143/**
1144 * Checks if the page has any active access handlers.
1145 * @returns true/false
1146 * @param pPage Pointer to the physical guest page tracking structure.
1147 */
1148#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1149# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1150 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1151#else
1152# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1153 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1154 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1155#endif
1156
1157/**
1158 * Checks if the page has any active access handlers catching all accesses.
1159 * @returns true/false
1160 * @param pPage Pointer to the physical guest page tracking structure.
1161 */
1162#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1163# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1164 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1165 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1166#else
1167# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1168 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1169 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1170#endif
1171
1172
1173/** @def PGM_PAGE_GET_TRACKING
1174 * Gets the packed shadow page pool tracking data associated with a guest page.
1175 * @returns uint16_t containing the data.
1176 * @param pPage Pointer to the physical guest page tracking structure.
1177 */
1178#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1179
1180/** @def PGM_PAGE_SET_TRACKING
1181 * Sets the packed shadow page pool tracking data associated with a guest page.
1182 * @param pPage Pointer to the physical guest page tracking structure.
1183 * @param u16TrackingData The tracking data to store.
1184 */
1185#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1186 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1187
1188/** @def PGM_PAGE_GET_TD_CREFS
1189 * Gets the @a cRefs tracking data member.
1190 * @returns cRefs.
1191 * @param pPage Pointer to the physical guest page tracking structure.
1192 */
1193#define PGM_PAGE_GET_TD_CREFS(pPage) \
1194 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1195
1196/** @def PGM_PAGE_GET_TD_IDX
1197 * Gets the @a idx tracking data member.
1198 * @returns idx.
1199 * @param pPage Pointer to the physical guest page tracking structure.
1200 */
1201#define PGM_PAGE_GET_TD_IDX(pPage) \
1202 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1203
1204
1205/** Max number of locks on a page. */
1206#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1207
1208/** Get the read lock count.
1209 * @returns count.
1210 * @param pPage Pointer to the physical guest page tracking structure.
1211 */
1212#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1213
1214/** Get the write lock count.
1215 * @returns count.
1216 * @param pPage Pointer to the physical guest page tracking structure.
1217 */
1218#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1219
1220/** Decrement the read lock counter.
1221 * @param pPage Pointer to the physical guest page tracking structure.
1222 */
1223#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1224
1225/** Decrement the write lock counter.
1226 * @param pPage Pointer to the physical guest page tracking structure.
1227 */
1228#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1229
1230/** Increment the read lock counter.
1231 * @param pPage Pointer to the physical guest page tracking structure.
1232 */
1233#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1234
1235/** Increment the write lock counter.
1236 * @param pPage Pointer to the physical guest page tracking structure.
1237 */
1238#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1239
1240
1241#if 0
1242/** Enables sanity checking of write monitoring using CRC-32. */
1243# define PGMLIVESAVERAMPAGE_WITH_CRC32
1244#endif
1245
1246/**
1247 * Per page live save tracking data.
1248 */
1249typedef struct PGMLIVESAVERAMPAGE
1250{
1251 /** Number of times it has been dirtied. */
1252 uint32_t cDirtied : 24;
1253 /** Whether it is currently dirty. */
1254 uint32_t fDirty : 1;
1255 /** Ignore the page.
1256 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1257 * deal with these after pausing the VM and DevPCI have said it bit about
1258 * remappings. */
1259 uint32_t fIgnore : 1;
1260 /** Was a ZERO page last time around. */
1261 uint32_t fZero : 1;
1262 /** Was a SHARED page last time around. */
1263 uint32_t fShared : 1;
1264 /** Whether the page is/was write monitored in a previous pass. */
1265 uint32_t fWriteMonitored : 1;
1266 /** Whether the page is/was write monitored earlier in this pass. */
1267 uint32_t fWriteMonitoredJustNow : 1;
1268 /** Bits reserved for future use. */
1269 uint32_t u2Reserved : 2;
1270#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1271 /** CRC-32 for the page. This is for internal consistency checks. */
1272 uint32_t u32Crc;
1273#endif
1274} PGMLIVESAVERAMPAGE;
1275#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1276AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1277#else
1278AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1279#endif
1280/** Pointer to the per page live save tracking data. */
1281typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1282
1283/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1284#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1285
1286
1287/**
1288 * Ram range for GC Phys to HC Phys conversion.
1289 *
1290 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1291 * conversions too, but we'll let MM handle that for now.
1292 *
1293 * This structure is used by linked lists in both GC and HC.
1294 */
1295typedef struct PGMRAMRANGE
1296{
1297 /** Start of the range. Page aligned. */
1298 RTGCPHYS GCPhys;
1299 /** Size of the range. (Page aligned of course). */
1300 RTGCPHYS cb;
1301 /** Pointer to the next RAM range - for R3. */
1302 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1303 /** Pointer to the next RAM range - for R0. */
1304 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1305 /** Pointer to the next RAM range - for RC. */
1306 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1307 /** PGM_RAM_RANGE_FLAGS_* flags. */
1308 uint32_t fFlags;
1309 /** Last address in the range (inclusive). Page aligned (-1). */
1310 RTGCPHYS GCPhysLast;
1311 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1312 R3PTRTYPE(void *) pvR3;
1313 /** Live save per page tracking data. */
1314 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1315 /** The range description. */
1316 R3PTRTYPE(const char *) pszDesc;
1317 /** Pointer to self - R0 pointer. */
1318 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1319 /** Pointer to self - RC pointer. */
1320 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1321 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1322 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1323 /** Array of physical guest page tracking structures. */
1324 PGMPAGE aPages[1];
1325} PGMRAMRANGE;
1326/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1327typedef PGMRAMRANGE *PPGMRAMRANGE;
1328
1329/** @name PGMRAMRANGE::fFlags
1330 * @{ */
1331/** The RAM range is floating around as an independent guest mapping. */
1332#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1333/** Ad hoc RAM range for an ROM mapping. */
1334#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1335/** Ad hoc RAM range for an MMIO mapping. */
1336#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1337/** Ad hoc RAM range for an MMIO2 mapping. */
1338#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1339/** @} */
1340
1341/** Tests if a RAM range is an ad hoc one or not.
1342 * @returns true/false.
1343 * @param pRam The RAM range.
1344 */
1345#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1346 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1347
1348
1349/**
1350 * Per page tracking structure for ROM image.
1351 *
1352 * A ROM image may have a shadow page, in which case we may have two pages
1353 * backing it. This structure contains the PGMPAGE for both while
1354 * PGMRAMRANGE have a copy of the active one. It is important that these
1355 * aren't out of sync in any regard other than page pool tracking data.
1356 */
1357typedef struct PGMROMPAGE
1358{
1359 /** The page structure for the virgin ROM page. */
1360 PGMPAGE Virgin;
1361 /** The page structure for the shadow RAM page. */
1362 PGMPAGE Shadow;
1363 /** The current protection setting. */
1364 PGMROMPROT enmProt;
1365 /** Live save status information. Makes use of unused alignment space. */
1366 struct
1367 {
1368 /** The previous protection value. */
1369 uint8_t u8Prot;
1370 /** Written to flag set by the handler. */
1371 bool fWrittenTo;
1372 /** Whether the shadow page is dirty or not. */
1373 bool fDirty;
1374 /** Whether it was dirtied in the recently. */
1375 bool fDirtiedRecently;
1376 } LiveSave;
1377} PGMROMPAGE;
1378AssertCompileSizeAlignment(PGMROMPAGE, 8);
1379/** Pointer to a ROM page tracking structure. */
1380typedef PGMROMPAGE *PPGMROMPAGE;
1381
1382
1383/**
1384 * A registered ROM image.
1385 *
1386 * This is needed to keep track of ROM image since they generally intrude
1387 * into a PGMRAMRANGE. It also keeps track of additional info like the
1388 * two page sets (read-only virgin and read-write shadow), the current
1389 * state of each page.
1390 *
1391 * Because access handlers cannot easily be executed in a different
1392 * context, the ROM ranges needs to be accessible and in all contexts.
1393 */
1394typedef struct PGMROMRANGE
1395{
1396 /** Pointer to the next range - R3. */
1397 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1398 /** Pointer to the next range - R0. */
1399 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1400 /** Pointer to the next range - RC. */
1401 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1402 /** Pointer alignment */
1403 RTRCPTR RCPtrAlignment;
1404 /** Address of the range. */
1405 RTGCPHYS GCPhys;
1406 /** Address of the last byte in the range. */
1407 RTGCPHYS GCPhysLast;
1408 /** Size of the range. */
1409 RTGCPHYS cb;
1410 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1411 uint32_t fFlags;
1412 /** The saved state range ID. */
1413 uint8_t idSavedState;
1414 /** Alignment padding. */
1415 uint8_t au8Alignment[3];
1416 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1417 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1418 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1419 * This is used for strictness checks. */
1420 R3PTRTYPE(const void *) pvOriginal;
1421 /** The ROM description. */
1422 R3PTRTYPE(const char *) pszDesc;
1423 /** The per page tracking structures. */
1424 PGMROMPAGE aPages[1];
1425} PGMROMRANGE;
1426/** Pointer to a ROM range. */
1427typedef PGMROMRANGE *PPGMROMRANGE;
1428
1429
1430/**
1431 * Live save per page data for an MMIO2 page.
1432 *
1433 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1434 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1435 * CRC-32 for detecting changes as well as special handling of zero pages. This
1436 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1437 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1438 * because of speed (2.5x and 6x slower).)
1439 *
1440 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1441 * save but normally is disabled. Since we can write monitore guest
1442 * accesses on our own, we only need this for host accesses. Shouldn't be
1443 * too difficult for DevVGA, VMMDev might be doable, the planned
1444 * networking fun will be fun since it involves ring-0.
1445 */
1446typedef struct PGMLIVESAVEMMIO2PAGE
1447{
1448 /** Set if the page is considered dirty. */
1449 bool fDirty;
1450 /** The number of scans this page has remained unchanged for.
1451 * Only updated for dirty pages. */
1452 uint8_t cUnchangedScans;
1453 /** Whether this page was zero at the last scan. */
1454 bool fZero;
1455 /** Alignment padding. */
1456 bool fReserved;
1457 /** CRC-32 for the first half of the page.
1458 * This is used together with u32CrcH2 to quickly detect changes in the page
1459 * during the non-final passes. */
1460 uint32_t u32CrcH1;
1461 /** CRC-32 for the second half of the page. */
1462 uint32_t u32CrcH2;
1463 /** SHA-1 for the saved page.
1464 * This is used in the final pass to skip pages without changes. */
1465 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1466} PGMLIVESAVEMMIO2PAGE;
1467/** Pointer to a live save status data for an MMIO2 page. */
1468typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1469
1470/**
1471 * A registered MMIO2 (= Device RAM) range.
1472 *
1473 * There are a few reason why we need to keep track of these
1474 * registrations. One of them is the deregistration & cleanup stuff,
1475 * while another is that the PGMRAMRANGE associated with such a region may
1476 * have to be removed from the ram range list.
1477 *
1478 * Overlapping with a RAM range has to be 100% or none at all. The pages
1479 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1480 * will be raised if a partial overlap or an overlap of ROM pages is
1481 * encountered. On an overlap we will free all the existing RAM pages and
1482 * put in the ram range pages instead.
1483 */
1484typedef struct PGMMMIO2RANGE
1485{
1486 /** The owner of the range. (a device) */
1487 PPDMDEVINSR3 pDevInsR3;
1488 /** Pointer to the ring-3 mapping of the allocation. */
1489 RTR3PTR pvR3;
1490 /** Pointer to the next range - R3. */
1491 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1492 /** Whether it's mapped or not. */
1493 bool fMapped;
1494 /** Whether it's overlapping or not. */
1495 bool fOverlapping;
1496 /** The PCI region number.
1497 * @remarks This ASSUMES that nobody will ever really need to have multiple
1498 * PCI devices with matching MMIO region numbers on a single device. */
1499 uint8_t iRegion;
1500 /** The saved state range ID. */
1501 uint8_t idSavedState;
1502 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1503 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1504 /** Live save per page tracking data. */
1505 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1506 /** The associated RAM range. */
1507 PGMRAMRANGE RamRange;
1508} PGMMMIO2RANGE;
1509/** Pointer to a MMIO2 range. */
1510typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1511
1512
1513
1514
1515/**
1516 * PGMPhysRead/Write cache entry
1517 */
1518typedef struct PGMPHYSCACHEENTRY
1519{
1520 /** R3 pointer to physical page. */
1521 R3PTRTYPE(uint8_t *) pbR3;
1522 /** GC Physical address for cache entry */
1523 RTGCPHYS GCPhys;
1524#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1525 RTGCPHYS u32Padding0; /**< alignment padding. */
1526#endif
1527} PGMPHYSCACHEENTRY;
1528
1529/**
1530 * PGMPhysRead/Write cache to reduce REM memory access overhead
1531 */
1532typedef struct PGMPHYSCACHE
1533{
1534 /** Bitmap of valid cache entries */
1535 uint64_t aEntries;
1536 /** Cache entries */
1537 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1538} PGMPHYSCACHE;
1539
1540
1541/** Pointer to an allocation chunk ring-3 mapping. */
1542typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1543/** Pointer to an allocation chunk ring-3 mapping pointer. */
1544typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1545
1546/**
1547 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1548 *
1549 * The primary tree (Core) uses the chunk id as key.
1550 */
1551typedef struct PGMCHUNKR3MAP
1552{
1553 /** The key is the chunk id. */
1554 AVLU32NODECORE Core;
1555 /** The current age thingy. */
1556 uint32_t iAge;
1557 /** The current reference count. */
1558 uint32_t volatile cRefs;
1559 /** The current permanent reference count. */
1560 uint32_t volatile cPermRefs;
1561 /** The mapping address. */
1562 void *pv;
1563} PGMCHUNKR3MAP;
1564
1565/**
1566 * Allocation chunk ring-3 mapping TLB entry.
1567 */
1568typedef struct PGMCHUNKR3MAPTLBE
1569{
1570 /** The chunk id. */
1571 uint32_t volatile idChunk;
1572#if HC_ARCH_BITS == 64
1573 uint32_t u32Padding; /**< alignment padding. */
1574#endif
1575 /** The chunk map. */
1576#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1577 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1578#else
1579 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1580#endif
1581} PGMCHUNKR3MAPTLBE;
1582/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1583typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1584
1585/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1586 * @remark Must be a power of two value. */
1587#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1588
1589/**
1590 * Allocation chunk ring-3 mapping TLB.
1591 *
1592 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1593 * At first glance this might look kinda odd since AVL trees are
1594 * supposed to give the most optimial lookup times of all trees
1595 * due to their balancing. However, take a tree with 1023 nodes
1596 * in it, that's 10 levels, meaning that most searches has to go
1597 * down 9 levels before they find what they want. This isn't fast
1598 * compared to a TLB hit. There is the factor of cache misses,
1599 * and of course the problem with trees and branch prediction.
1600 * This is why we use TLBs in front of most of the trees.
1601 *
1602 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1603 * difficult when we switch to the new inlined AVL trees (from kStuff).
1604 */
1605typedef struct PGMCHUNKR3MAPTLB
1606{
1607 /** The TLB entries. */
1608 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1609} PGMCHUNKR3MAPTLB;
1610
1611/**
1612 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1613 * @returns Chunk TLB index.
1614 * @param idChunk The Chunk ID.
1615 */
1616#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1617
1618
1619/**
1620 * Ring-3 guest page mapping TLB entry.
1621 * @remarks used in ring-0 as well at the moment.
1622 */
1623typedef struct PGMPAGER3MAPTLBE
1624{
1625 /** Address of the page. */
1626 RTGCPHYS volatile GCPhys;
1627 /** The guest page. */
1628#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1629 R3PTRTYPE(PPGMPAGE) volatile pPage;
1630#else
1631 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1632#endif
1633 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1634#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1635 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1636#else
1637 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1638#endif
1639 /** The address */
1640#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1641 R3PTRTYPE(void *) volatile pv;
1642#else
1643 R3R0PTRTYPE(void *) volatile pv;
1644#endif
1645#if HC_ARCH_BITS == 32
1646 uint32_t u32Padding; /**< alignment padding. */
1647#endif
1648} PGMPAGER3MAPTLBE;
1649/** Pointer to an entry in the HC physical TLB. */
1650typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1651
1652
1653/** The number of entries in the ring-3 guest page mapping TLB.
1654 * @remarks The value must be a power of two. */
1655#define PGM_PAGER3MAPTLB_ENTRIES 256
1656
1657/**
1658 * Ring-3 guest page mapping TLB.
1659 * @remarks used in ring-0 as well at the moment.
1660 */
1661typedef struct PGMPAGER3MAPTLB
1662{
1663 /** The TLB entries. */
1664 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1665} PGMPAGER3MAPTLB;
1666/** Pointer to the ring-3 guest page mapping TLB. */
1667typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1668
1669/**
1670 * Calculates the index of the TLB entry for the specified guest page.
1671 * @returns Physical TLB index.
1672 * @param GCPhys The guest physical address.
1673 */
1674#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1675
1676
1677/**
1678 * Raw-mode context dynamic mapping cache entry.
1679 *
1680 * Because of raw-mode context being reloctable and all relocations are applied
1681 * in ring-3, this has to be defined here and be RC specfic.
1682 *
1683 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1684 */
1685typedef struct PGMRCDYNMAPENTRY
1686{
1687 /** The physical address of the currently mapped page.
1688 * This is duplicate for three reasons: cache locality, cache policy of the PT
1689 * mappings and sanity checks. */
1690 RTHCPHYS HCPhys;
1691 /** Pointer to the page. */
1692 RTRCPTR pvPage;
1693 /** The number of references. */
1694 int32_t volatile cRefs;
1695 /** PTE pointer union. */
1696 union PGMRCDYNMAPENTRY_PPTE
1697 {
1698 /** PTE pointer, 32-bit legacy version. */
1699 RCPTRTYPE(PX86PTE) pLegacy;
1700 /** PTE pointer, PAE version. */
1701 RCPTRTYPE(PX86PTEPAE) pPae;
1702 /** PTE pointer, the void version. */
1703 RTRCPTR pv;
1704 } uPte;
1705 /** Alignment padding. */
1706 RTRCPTR RCPtrAlignment;
1707} PGMRCDYNMAPENTRY;
1708/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1709typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1710
1711
1712/**
1713 * Dynamic mapping cache for the raw-mode context.
1714 *
1715 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1716 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1717 * so that we can perform relocations from PGMR3Relocate. This has the
1718 * consequence that we must have separate ring-0 and raw-mode context versions
1719 * of this struct even if they share the basic elements.
1720 *
1721 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1722 */
1723typedef struct PGMRCDYNMAP
1724{
1725 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1726 uint32_t u32Magic;
1727 /** Array for tracking and managing the pages. */
1728 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1729 /** The cache size given as a number of pages. */
1730 uint32_t cPages;
1731 /** Whether it's 32-bit legacy or PAE/AMD64 paging mode. */
1732 bool fLegacyMode;
1733 /** The current load.
1734 * This does not include guard pages. */
1735 uint32_t cLoad;
1736 /** The max load ever.
1737 * This is maintained to get trigger adding of more mapping space. */
1738 uint32_t cMaxLoad;
1739 /** The number of guard pages. */
1740 uint32_t cGuardPages;
1741 /** The number of users (protected by hInitLock). */
1742 uint32_t cUsers;
1743} PGMRCDYNMAP;
1744/** Pointer to the dynamic cache for the raw-mode context. */
1745typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1746
1747
1748/**
1749 * Mapping cache usage set entry.
1750 *
1751 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1752 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1753 * cache. If it's extended to include ring-3, well, then something
1754 * will have be changed here...
1755 */
1756typedef struct PGMMAPSETENTRY
1757{
1758 /** Pointer to the page. */
1759#ifndef IN_RC
1760 RTR0PTR pvPage;
1761#else
1762 RTRCPTR pvPage;
1763# if HC_ARCH_BITS == 64
1764 uint32_t u32Alignment2;
1765# endif
1766#endif
1767 /** The mapping cache index. */
1768 uint16_t iPage;
1769 /** The number of references.
1770 * The max is UINT16_MAX - 1. */
1771 uint16_t cRefs;
1772 /** The number inlined references.
1773 * The max is UINT16_MAX - 1. */
1774 uint16_t cInlinedRefs;
1775 /** Unreferences. */
1776 uint16_t cUnrefs;
1777
1778#if HC_ARCH_BITS == 32
1779 uint32_t u32Alignment1;
1780#endif
1781 /** The physical address for this entry. */
1782 RTHCPHYS HCPhys;
1783} PGMMAPSETENTRY;
1784AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1785AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1786/** Pointer to a mapping cache usage set entry. */
1787typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1788
1789/**
1790 * Mapping cache usage set.
1791 *
1792 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1793 * done during exits / traps. The set is
1794 */
1795typedef struct PGMMAPSET
1796{
1797 /** The number of occupied entries.
1798 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1799 * dynamic mappings. */
1800 uint32_t cEntries;
1801 /** The start of the current subset.
1802 * This is UINT32_MAX if no subset is currently open. */
1803 uint32_t iSubset;
1804 /** The index of the current CPU, only valid if the set is open. */
1805 int32_t iCpu;
1806 uint32_t alignment;
1807 /** The entries. */
1808 PGMMAPSETENTRY aEntries[64];
1809 /** HCPhys -> iEntry fast lookup table.
1810 * Use PGMMAPSET_HASH for hashing.
1811 * The entries may or may not be valid, check against cEntries. */
1812 uint8_t aiHashTable[128];
1813} PGMMAPSET;
1814AssertCompileSizeAlignment(PGMMAPSET, 8);
1815/** Pointer to the mapping cache set. */
1816typedef PGMMAPSET *PPGMMAPSET;
1817
1818/** PGMMAPSET::cEntries value for a closed set. */
1819#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1820
1821/** Hash function for aiHashTable. */
1822#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1823
1824
1825/** @name Context neutrual page mapper TLB.
1826 *
1827 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1828 * code is writting in a kind of context neutrual way. Time will show whether
1829 * this actually makes sense or not...
1830 *
1831 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1832 * context ends up using a global mapping cache on some platforms
1833 * (darwin).
1834 *
1835 * @{ */
1836/** @typedef PPGMPAGEMAPTLB
1837 * The page mapper TLB pointer type for the current context. */
1838/** @typedef PPGMPAGEMAPTLB
1839 * The page mapper TLB entry pointer type for the current context. */
1840/** @typedef PPGMPAGEMAPTLB
1841 * The page mapper TLB entry pointer pointer type for the current context. */
1842/** @def PGM_PAGEMAPTLB_ENTRIES
1843 * The number of TLB entries in the page mapper TLB for the current context. */
1844/** @def PGM_PAGEMAPTLB_IDX
1845 * Calculate the TLB index for a guest physical address.
1846 * @returns The TLB index.
1847 * @param GCPhys The guest physical address. */
1848/** @typedef PPGMPAGEMAP
1849 * Pointer to a page mapper unit for current context. */
1850/** @typedef PPPGMPAGEMAP
1851 * Pointer to a page mapper unit pointer for current context. */
1852#ifdef IN_RC
1853// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1854// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1855// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1856# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1857# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1858 typedef void * PPGMPAGEMAP;
1859 typedef void ** PPPGMPAGEMAP;
1860//#elif IN_RING0
1861// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1862// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1863// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1864//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1865//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1866// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1867// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1868#else
1869 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1870 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1871 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1872# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1873# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1874 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1875 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1876#endif
1877/** @} */
1878
1879
1880/** @name PGM Pool Indexes.
1881 * Aka. the unique shadow page identifier.
1882 * @{ */
1883/** NIL page pool IDX. */
1884#define NIL_PGMPOOL_IDX 0
1885/** The first normal index. */
1886#define PGMPOOL_IDX_FIRST_SPECIAL 1
1887/** Page directory (32-bit root). */
1888#define PGMPOOL_IDX_PD 1
1889/** Page Directory Pointer Table (PAE root). */
1890#define PGMPOOL_IDX_PDPT 2
1891/** AMD64 CR3 level index.*/
1892#define PGMPOOL_IDX_AMD64_CR3 3
1893/** Nested paging root.*/
1894#define PGMPOOL_IDX_NESTED_ROOT 4
1895/** The first normal index. */
1896#define PGMPOOL_IDX_FIRST 5
1897/** The last valid index. (inclusive, 14 bits) */
1898#define PGMPOOL_IDX_LAST 0x3fff
1899/** @} */
1900
1901/** The NIL index for the parent chain. */
1902#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1903#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1904
1905/**
1906 * Node in the chain linking a shadowed page to it's parent (user).
1907 */
1908#pragma pack(1)
1909typedef struct PGMPOOLUSER
1910{
1911 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1912 uint16_t iNext;
1913 /** The user page index. */
1914 uint16_t iUser;
1915 /** Index into the user table. */
1916 uint32_t iUserTable;
1917} PGMPOOLUSER, *PPGMPOOLUSER;
1918typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1919#pragma pack()
1920
1921
1922/** The NIL index for the phys ext chain. */
1923#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1924/** The NIL pte index for a phys ext chain slot. */
1925#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1926
1927/**
1928 * Node in the chain of physical cross reference extents.
1929 * @todo Calling this an 'extent' is not quite right, find a better name.
1930 * @todo find out the optimal size of the aidx array
1931 */
1932#pragma pack(1)
1933typedef struct PGMPOOLPHYSEXT
1934{
1935 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1936 uint16_t iNext;
1937 /** Alignment. */
1938 uint16_t u16Align;
1939 /** The user page index. */
1940 uint16_t aidx[3];
1941 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1942 uint16_t apte[3];
1943} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1944typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1945#pragma pack()
1946
1947
1948/**
1949 * The kind of page that's being shadowed.
1950 */
1951typedef enum PGMPOOLKIND
1952{
1953 /** The virtual invalid 0 entry. */
1954 PGMPOOLKIND_INVALID = 0,
1955 /** The entry is free (=unused). */
1956 PGMPOOLKIND_FREE,
1957
1958 /** Shw: 32-bit page table; Gst: no paging */
1959 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1960 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1961 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1962 /** Shw: 32-bit page table; Gst: 4MB page. */
1963 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1964 /** Shw: PAE page table; Gst: no paging */
1965 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1966 /** Shw: PAE page table; Gst: 32-bit page table. */
1967 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1968 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1969 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1970 /** Shw: PAE page table; Gst: PAE page table. */
1971 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1972 /** Shw: PAE page table; Gst: 2MB page. */
1973 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1974
1975 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1976 PGMPOOLKIND_32BIT_PD,
1977 /** Shw: 32-bit page directory. Gst: no paging. */
1978 PGMPOOLKIND_32BIT_PD_PHYS,
1979 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1980 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1981 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1982 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1983 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1984 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1985 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1986 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1987 /** Shw: PAE page directory; Gst: PAE page directory. */
1988 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1989 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1990 PGMPOOLKIND_PAE_PD_PHYS,
1991
1992 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1993 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1994 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1995 PGMPOOLKIND_PAE_PDPT,
1996 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1997 PGMPOOLKIND_PAE_PDPT_PHYS,
1998
1999 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2000 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2001 /** Shw: 64-bit page directory pointer table; Gst: no paging */
2002 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2003 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2004 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2005 /** Shw: 64-bit page directory table; Gst: no paging */
2006 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
2007
2008 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2009 PGMPOOLKIND_64BIT_PML4,
2010
2011 /** Shw: EPT page directory pointer table; Gst: no paging */
2012 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2013 /** Shw: EPT page directory table; Gst: no paging */
2014 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2015 /** Shw: EPT page table; Gst: no paging */
2016 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2017
2018 /** Shw: Root Nested paging table. */
2019 PGMPOOLKIND_ROOT_NESTED,
2020
2021 /** The last valid entry. */
2022 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2023} PGMPOOLKIND;
2024
2025/**
2026 * The access attributes of the page; only applies to big pages.
2027 */
2028typedef enum
2029{
2030 PGMPOOLACCESS_DONTCARE = 0,
2031 PGMPOOLACCESS_USER_RW,
2032 PGMPOOLACCESS_USER_R,
2033 PGMPOOLACCESS_USER_RW_NX,
2034 PGMPOOLACCESS_USER_R_NX,
2035 PGMPOOLACCESS_SUPERVISOR_RW,
2036 PGMPOOLACCESS_SUPERVISOR_R,
2037 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2038 PGMPOOLACCESS_SUPERVISOR_R_NX
2039} PGMPOOLACCESS;
2040
2041/**
2042 * The tracking data for a page in the pool.
2043 */
2044typedef struct PGMPOOLPAGE
2045{
2046 /** AVL node code with the (R3) physical address of this page. */
2047 AVLOHCPHYSNODECORE Core;
2048 /** Pointer to the R3 mapping of the page. */
2049#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2050 R3PTRTYPE(void *) pvPageR3;
2051#else
2052 R3R0PTRTYPE(void *) pvPageR3;
2053#endif
2054 /** The guest physical address. */
2055#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2056 uint32_t Alignment0;
2057#endif
2058 RTGCPHYS GCPhys;
2059
2060 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2061 RTGCPTR pvLastAccessHandlerRip;
2062 RTGCPTR pvLastAccessHandlerFault;
2063 uint64_t cLastAccessHandlerCount;
2064
2065 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2066 uint8_t enmKind;
2067 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2068 uint8_t enmAccess;
2069 /** The index of this page. */
2070 uint16_t idx;
2071 /** The next entry in the list this page currently resides in.
2072 * It's either in the free list or in the GCPhys hash. */
2073 uint16_t iNext;
2074 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2075 uint16_t iUserHead;
2076 /** The number of present entries. */
2077 uint16_t cPresent;
2078 /** The first entry in the table which is present. */
2079 uint16_t iFirstPresent;
2080 /** The number of modifications to the monitored page. */
2081 uint16_t cModifications;
2082 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2083 uint16_t iModifiedNext;
2084 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2085 uint16_t iModifiedPrev;
2086 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2087 uint16_t iMonitoredNext;
2088 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2089 uint16_t iMonitoredPrev;
2090 /** The next page in the age list. */
2091 uint16_t iAgeNext;
2092 /** The previous page in the age list. */
2093 uint16_t iAgePrev;
2094 /** Used to indicate that the page is zeroed. */
2095 bool fZeroed;
2096 /** Used to indicate that a PT has non-global entries. */
2097 bool fSeenNonGlobal;
2098 /** Used to indicate that we're monitoring writes to the guest page. */
2099 bool fMonitored;
2100 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2101 * (All pages are in the age list.) */
2102 bool fCached;
2103 /** This is used by the R3 access handlers when invoked by an async thread.
2104 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2105 bool volatile fReusedFlushPending;
2106 /** Used to mark the page as dirty (write monitoring is temporarily
2107 * off). */
2108 bool fDirty;
2109
2110 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2111 uint32_t cLocked;
2112 uint32_t idxDirty;
2113 RTGCPTR pvDirtyFault;
2114} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
2115/** Pointer to a const pool page. */
2116typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2117
2118
2119/** The hash table size. */
2120# define PGMPOOL_HASH_SIZE 0x40
2121/** The hash function. */
2122# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2123
2124
2125/**
2126 * The shadow page pool instance data.
2127 *
2128 * It's all one big allocation made at init time, except for the
2129 * pages that is. The user nodes follows immediatly after the
2130 * page structures.
2131 */
2132typedef struct PGMPOOL
2133{
2134 /** The VM handle - R3 Ptr. */
2135 PVMR3 pVMR3;
2136 /** The VM handle - R0 Ptr. */
2137 PVMR0 pVMR0;
2138 /** The VM handle - RC Ptr. */
2139 PVMRC pVMRC;
2140 /** The max pool size. This includes the special IDs. */
2141 uint16_t cMaxPages;
2142 /** The current pool size. */
2143 uint16_t cCurPages;
2144 /** The head of the free page list. */
2145 uint16_t iFreeHead;
2146 /* Padding. */
2147 uint16_t u16Padding;
2148 /** Head of the chain of free user nodes. */
2149 uint16_t iUserFreeHead;
2150 /** The number of user nodes we've allocated. */
2151 uint16_t cMaxUsers;
2152 /** The number of present page table entries in the entire pool. */
2153 uint32_t cPresent;
2154 /** Pointer to the array of user nodes - RC pointer. */
2155 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2156 /** Pointer to the array of user nodes - R3 pointer. */
2157 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2158 /** Pointer to the array of user nodes - R0 pointer. */
2159 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2160 /** Head of the chain of free phys ext nodes. */
2161 uint16_t iPhysExtFreeHead;
2162 /** The number of user nodes we've allocated. */
2163 uint16_t cMaxPhysExts;
2164 /** Pointer to the array of physical xref extent - RC pointer. */
2165 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2166 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2167 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2168 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2169 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2170 /** Hash table for GCPhys addresses. */
2171 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2172 /** The head of the age list. */
2173 uint16_t iAgeHead;
2174 /** The tail of the age list. */
2175 uint16_t iAgeTail;
2176 /** Set if the cache is enabled. */
2177 bool fCacheEnabled;
2178 /** Alignment padding. */
2179 bool afPadding1[3];
2180 /** Head of the list of modified pages. */
2181 uint16_t iModifiedHead;
2182 /** The current number of modified pages. */
2183 uint16_t cModifiedPages;
2184 /** Access handler, RC. */
2185 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2186 /** Access handler, R0. */
2187 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2188 /** Access handler, R3. */
2189 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2190 /** The access handler description (R3 ptr). */
2191 R3PTRTYPE(const char *) pszAccessHandler;
2192# if HC_ARCH_BITS == 32
2193 /** Alignment padding. */
2194 uint32_t u32Padding2;
2195# endif
2196 /* Next available slot. */
2197 uint32_t idxFreeDirtyPage;
2198 /* Number of active dirty pages. */
2199 uint32_t cDirtyPages;
2200 /* Array of current dirty pgm pool page indices. */
2201 uint16_t aIdxDirtyPages[16];
2202 uint64_t aDirtyPages[16][512];
2203 /** The number of pages currently in use. */
2204 uint16_t cUsedPages;
2205#ifdef VBOX_WITH_STATISTICS
2206 /** The high water mark for cUsedPages. */
2207 uint16_t cUsedPagesHigh;
2208 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
2209 /** Profiling pgmPoolAlloc(). */
2210 STAMPROFILEADV StatAlloc;
2211 /** Profiling pgmR3PoolClearDoIt(). */
2212 STAMPROFILE StatClearAll;
2213 /** Profiling pgmR3PoolReset(). */
2214 STAMPROFILE StatR3Reset;
2215 /** Profiling pgmPoolFlushPage(). */
2216 STAMPROFILE StatFlushPage;
2217 /** Profiling pgmPoolFree(). */
2218 STAMPROFILE StatFree;
2219 /** Counting explicit flushes by PGMPoolFlushPage(). */
2220 STAMCOUNTER StatForceFlushPage;
2221 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2222 STAMCOUNTER StatForceFlushDirtyPage;
2223 /** Counting flushes for reused pages. */
2224 STAMCOUNTER StatForceFlushReused;
2225 /** Profiling time spent zeroing pages. */
2226 STAMPROFILE StatZeroPage;
2227 /** Profiling of pgmPoolTrackDeref. */
2228 STAMPROFILE StatTrackDeref;
2229 /** Profiling pgmTrackFlushGCPhysPT. */
2230 STAMPROFILE StatTrackFlushGCPhysPT;
2231 /** Profiling pgmTrackFlushGCPhysPTs. */
2232 STAMPROFILE StatTrackFlushGCPhysPTs;
2233 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2234 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2235 /** Number of times we've been out of user records. */
2236 STAMCOUNTER StatTrackFreeUpOneUser;
2237 /** Nr of flushed entries. */
2238 STAMCOUNTER StatTrackFlushEntry;
2239 /** Nr of updated entries. */
2240 STAMCOUNTER StatTrackFlushEntryKeep;
2241 /** Profiling deref activity related tracking GC physical pages. */
2242 STAMPROFILE StatTrackDerefGCPhys;
2243 /** Number of linear searches for a HCPhys in the ram ranges. */
2244 STAMCOUNTER StatTrackLinearRamSearches;
2245 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2246 STAMCOUNTER StamTrackPhysExtAllocFailures;
2247 /** Profiling the RC/R0 access handler. */
2248 STAMPROFILE StatMonitorRZ;
2249 /** Times we've failed interpreting the instruction. */
2250 STAMCOUNTER StatMonitorRZEmulateInstr;
2251 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2252 STAMPROFILE StatMonitorRZFlushPage;
2253 /* Times we've detected a page table reinit. */
2254 STAMCOUNTER StatMonitorRZFlushReinit;
2255 /** Counting flushes for pages that are modified too often. */
2256 STAMCOUNTER StatMonitorRZFlushModOverflow;
2257 /** Times we've detected fork(). */
2258 STAMCOUNTER StatMonitorRZFork;
2259 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2260 STAMPROFILE StatMonitorRZHandled;
2261 /** Times we've failed interpreting a patch code instruction. */
2262 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2263 /** Times we've failed interpreting a patch code instruction during flushing. */
2264 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2265 /** The number of times we've seen rep prefixes we can't handle. */
2266 STAMCOUNTER StatMonitorRZRepPrefix;
2267 /** Profiling the REP STOSD cases we've handled. */
2268 STAMPROFILE StatMonitorRZRepStosd;
2269 /** Nr of handled PT faults. */
2270 STAMCOUNTER StatMonitorRZFaultPT;
2271 /** Nr of handled PD faults. */
2272 STAMCOUNTER StatMonitorRZFaultPD;
2273 /** Nr of handled PDPT faults. */
2274 STAMCOUNTER StatMonitorRZFaultPDPT;
2275 /** Nr of handled PML4 faults. */
2276 STAMCOUNTER StatMonitorRZFaultPML4;
2277
2278 /** Profiling the R3 access handler. */
2279 STAMPROFILE StatMonitorR3;
2280 /** Times we've failed interpreting the instruction. */
2281 STAMCOUNTER StatMonitorR3EmulateInstr;
2282 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2283 STAMPROFILE StatMonitorR3FlushPage;
2284 /* Times we've detected a page table reinit. */
2285 STAMCOUNTER StatMonitorR3FlushReinit;
2286 /** Counting flushes for pages that are modified too often. */
2287 STAMCOUNTER StatMonitorR3FlushModOverflow;
2288 /** Times we've detected fork(). */
2289 STAMCOUNTER StatMonitorR3Fork;
2290 /** Profiling the R3 access we've handled (except REP STOSD). */
2291 STAMPROFILE StatMonitorR3Handled;
2292 /** The number of times we've seen rep prefixes we can't handle. */
2293 STAMCOUNTER StatMonitorR3RepPrefix;
2294 /** Profiling the REP STOSD cases we've handled. */
2295 STAMPROFILE StatMonitorR3RepStosd;
2296 /** Nr of handled PT faults. */
2297 STAMCOUNTER StatMonitorR3FaultPT;
2298 /** Nr of handled PD faults. */
2299 STAMCOUNTER StatMonitorR3FaultPD;
2300 /** Nr of handled PDPT faults. */
2301 STAMCOUNTER StatMonitorR3FaultPDPT;
2302 /** Nr of handled PML4 faults. */
2303 STAMCOUNTER StatMonitorR3FaultPML4;
2304 /** The number of times we're called in an async thread an need to flush. */
2305 STAMCOUNTER StatMonitorR3Async;
2306 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2307 STAMCOUNTER StatResetDirtyPages;
2308 /** Times we've called pgmPoolAddDirtyPage. */
2309 STAMCOUNTER StatDirtyPage;
2310 /** Times we've had to flush duplicates for dirty page management. */
2311 STAMCOUNTER StatDirtyPageDupFlush;
2312 /** Times we've had to flush because of overflow. */
2313 STAMCOUNTER StatDirtyPageOverFlowFlush;
2314
2315 /** The high wather mark for cModifiedPages. */
2316 uint16_t cModifiedPagesHigh;
2317 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2318
2319 /** The number of cache hits. */
2320 STAMCOUNTER StatCacheHits;
2321 /** The number of cache misses. */
2322 STAMCOUNTER StatCacheMisses;
2323 /** The number of times we've got a conflict of 'kind' in the cache. */
2324 STAMCOUNTER StatCacheKindMismatches;
2325 /** Number of times we've been out of pages. */
2326 STAMCOUNTER StatCacheFreeUpOne;
2327 /** The number of cacheable allocations. */
2328 STAMCOUNTER StatCacheCacheable;
2329 /** The number of uncacheable allocations. */
2330 STAMCOUNTER StatCacheUncacheable;
2331#else
2332 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2333#endif
2334 /** The AVL tree for looking up a page by its HC physical address. */
2335 AVLOHCPHYSTREE HCPhysTree;
2336 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2337 /** Array of pages. (cMaxPages in length)
2338 * The Id is the index into thist array.
2339 */
2340 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2341} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2342AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2343AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2344AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2345#ifdef VBOX_WITH_STATISTICS
2346AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2347#endif
2348AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2349
2350
2351/** @def PGMPOOL_PAGE_2_PTR
2352 * Maps a pool page pool into the current context.
2353 *
2354 * @returns VBox status code.
2355 * @param pVM The VM handle.
2356 * @param pPage The pool page.
2357 *
2358 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2359 * small page window employeed by that function. Be careful.
2360 * @remark There is no need to assert on the result.
2361 */
2362#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2363# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage) RTLOG_COMMA_SRC_POS)
2364#elif defined(VBOX_STRICT)
2365# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2366DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2367{
2368 Assert(pPage && pPage->pvPageR3);
2369 return pPage->pvPageR3;
2370}
2371#else
2372# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2373#endif
2374
2375
2376/** @def PGMPOOL_PAGE_2_PTR_V2
2377 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2378 *
2379 * @returns VBox status code.
2380 * @param pVM The VM handle.
2381 * @param pVCpu The current CPU.
2382 * @param pPage The pool page.
2383 *
2384 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2385 * small page window employeed by that function. Be careful.
2386 * @remark There is no need to assert on the result.
2387 */
2388#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2389# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage) RTLOG_COMMA_SRC_POS)
2390#else
2391# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2392#endif
2393
2394
2395/** @name Per guest page tracking data.
2396 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2397 * is to use more bits for it and split it up later on. But for now we'll play
2398 * safe and change as little as possible.
2399 *
2400 * The 16-bit word has two parts:
2401 *
2402 * The first 14-bit forms the @a idx field. It is either the index of a page in
2403 * the shadow page pool, or and index into the extent list.
2404 *
2405 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2406 * shadow page pool references to the page. If cRefs equals
2407 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2408 * (misnomer) table and not the shadow page pool.
2409 *
2410 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2411 * the 16-bit word.
2412 *
2413 * @{ */
2414/** The shift count for getting to the cRefs part. */
2415#define PGMPOOL_TD_CREFS_SHIFT 14
2416/** The mask applied after shifting the tracking data down by
2417 * PGMPOOL_TD_CREFS_SHIFT. */
2418#define PGMPOOL_TD_CREFS_MASK 0x3
2419/** The cRefs value used to indiciate that the idx is the head of a
2420 * physical cross reference list. */
2421#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2422/** The shift used to get idx. */
2423#define PGMPOOL_TD_IDX_SHIFT 0
2424/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2425#define PGMPOOL_TD_IDX_MASK 0x3fff
2426/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2427 * simply too many mappings of this page. */
2428#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2429
2430/** @def PGMPOOL_TD_MAKE
2431 * Makes a 16-bit tracking data word.
2432 *
2433 * @returns tracking data.
2434 * @param cRefs The @a cRefs field. Must be within bounds!
2435 * @param idx The @a idx field. Must also be within bounds! */
2436#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2437
2438/** @def PGMPOOL_TD_GET_CREFS
2439 * Get the @a cRefs field from a tracking data word.
2440 *
2441 * @returns The @a cRefs field
2442 * @param u16 The tracking data word.
2443 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2444 * non-zero @a u16. */
2445#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2446
2447/** @def PGMPOOL_TD_GET_IDX
2448 * Get the @a idx field from a tracking data word.
2449 *
2450 * @returns The @a idx field
2451 * @param u16 The tracking data word. */
2452#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2453/** @} */
2454
2455
2456/**
2457 * Trees are using self relative offsets as pointers.
2458 * So, all its data, including the root pointer, must be in the heap for HC and GC
2459 * to have the same layout.
2460 */
2461typedef struct PGMTREES
2462{
2463 /** Physical access handlers (AVL range+offsetptr tree). */
2464 AVLROGCPHYSTREE PhysHandlers;
2465 /** Virtual access handlers (AVL range + GC ptr tree). */
2466 AVLROGCPTRTREE VirtHandlers;
2467 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2468 AVLROGCPHYSTREE PhysToVirtHandlers;
2469 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2470 AVLROGCPTRTREE HyperVirtHandlers;
2471} PGMTREES;
2472/** Pointer to PGM trees. */
2473typedef PGMTREES *PPGMTREES;
2474
2475
2476/**
2477 * Page fault guest state for the AMD64 paging mode.
2478 */
2479typedef struct PGMPTWALKCORE
2480{
2481 /** The guest virtual address that is being resolved by the walk
2482 * (input). */
2483 RTGCPTR GCPtr;
2484
2485 /** The guest physcial address that is the result of the walk.
2486 * @remarks only valid if fSucceeded is set. */
2487 RTGCPHYS GCPhys;
2488
2489 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2490 bool fSucceeded;
2491 /** The level problem arrised at.
2492 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2493 * level 8. This is 0 on success. */
2494 uint8_t uLevel;
2495 /** Set if the page isn't present. */
2496 bool fNotPresent;
2497 /** Encountered a bad physical address. */
2498 bool fBadPhysAddr;
2499 /** Set if there was reserved bit violations. */
2500 bool fRsvdError;
2501 /** Set if it involves a big page (2/4 MB). */
2502 bool fBigPage;
2503 /** Set if it involves a gigantic page (1 GB). */
2504 bool fGigantPage;
2505 /** The effect X86_PTE_US flag for the address. */
2506 bool fEffectiveUS;
2507 /** The effect X86_PTE_RW flag for the address. */
2508 bool fEffectiveRW;
2509 /** The effect X86_PTE_NX flag for the address. */
2510 bool fEffectiveNX;
2511} PGMPTWALKCORE;
2512
2513
2514/**
2515 * Guest page table walk for the AMD64 mode.
2516 */
2517typedef struct PGMPTWALKGSTAMD64
2518{
2519 /** The common core. */
2520 PGMPTWALKCORE Core;
2521
2522 PX86PML4 pPml4;
2523 PX86PML4E pPml4e;
2524 X86PML4E Pml4e;
2525
2526 PX86PDPT pPdpt;
2527 PX86PDPE pPdpe;
2528 X86PDPE Pdpe;
2529
2530 PX86PDPAE pPd;
2531 PX86PDEPAE pPde;
2532 X86PDEPAE Pde;
2533
2534 PX86PTPAE pPt;
2535 PX86PTEPAE pPte;
2536 X86PTEPAE Pte;
2537} PGMPTWALKGSTAMD64;
2538/** Pointer to a AMD64 guest page table walk. */
2539typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2540/** Pointer to a const AMD64 guest page table walk. */
2541typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2542
2543/**
2544 * Guest page table walk for the PAE mode.
2545 */
2546typedef struct PGMPTWALKGSTPAE
2547{
2548 /** The common core. */
2549 PGMPTWALKCORE Core;
2550
2551 PX86PDPT pPdpt;
2552 PX86PDPE pPdpe;
2553 X86PDPE Pdpe;
2554
2555 PX86PDPAE pPd;
2556 PX86PDEPAE pPde;
2557 X86PDEPAE Pde;
2558
2559 PX86PTPAE pPt;
2560 PX86PTEPAE pPte;
2561 X86PTEPAE Pte;
2562} PGMPTWALKGSTPAE;
2563/** Pointer to a PAE guest page table walk. */
2564typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2565/** Pointer to a const AMD64 guest page table walk. */
2566typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2567
2568/**
2569 * Guest page table walk for the 32-bit mode.
2570 */
2571typedef struct PGMPTWALKGST32BIT
2572{
2573 /** The common core. */
2574 PGMPTWALKCORE Core;
2575
2576 PX86PD pPd;
2577 PX86PDE pPde;
2578 X86PDE Pde;
2579
2580 PX86PT pPt;
2581 PX86PTE pPte;
2582 X86PTE Pte;
2583} PGMPTWALKGST32BIT;
2584/** Pointer to a 32-bit guest page table walk. */
2585typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2586/** Pointer to a const 32-bit guest page table walk. */
2587typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2588
2589
2590/** @name Paging mode macros
2591 * @{
2592 */
2593#ifdef IN_RC
2594# define PGM_CTX(a,b) a##RC##b
2595# define PGM_CTX_STR(a,b) a "GC" b
2596# define PGM_CTX_DECL(type) VMMRCDECL(type)
2597#else
2598# ifdef IN_RING3
2599# define PGM_CTX(a,b) a##R3##b
2600# define PGM_CTX_STR(a,b) a "R3" b
2601# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2602# else
2603# define PGM_CTX(a,b) a##R0##b
2604# define PGM_CTX_STR(a,b) a "R0" b
2605# define PGM_CTX_DECL(type) VMMDECL(type)
2606# endif
2607#endif
2608
2609#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2610#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2611#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2612#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2613#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2614#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2615#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2616#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2617#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2618#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2619#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2620#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2621#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2622#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2623#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2624#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2625#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2626
2627#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2628#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2629#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2630#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2631#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2632#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2633#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2634#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2635#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2636#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2637#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2638#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2639#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2640#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2641#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2642#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2643#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2644
2645/* Shw_Gst */
2646#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2647#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2648#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2649#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2650#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2651#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2652#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2653#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2654#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2655#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2656#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2657#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2658#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2659#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2660#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2661#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2662#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2663#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2664#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2665
2666#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2667#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2668#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2669#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2670#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2671#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2672#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2673#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2674#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2675#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2676#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2677#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2678#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2679#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2680#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2681#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2682#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2683#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2684#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2685#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2686#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2687#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2688#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2689#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2690#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2691#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2692#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2693#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2694#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2695#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2696#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2697#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2698#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2699#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2700#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2701#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2702#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2703
2704#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2705#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2706/** @} */
2707
2708/**
2709 * Data for each paging mode.
2710 */
2711typedef struct PGMMODEDATA
2712{
2713 /** The guest mode type. */
2714 uint32_t uGstType;
2715 /** The shadow mode type. */
2716 uint32_t uShwType;
2717
2718 /** @name Function pointers for Shadow paging.
2719 * @{
2720 */
2721 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2722 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2723 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2724 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2725
2726 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2727 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2728
2729 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2730 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2731 /** @} */
2732
2733 /** @name Function pointers for Guest paging.
2734 * @{
2735 */
2736 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2737 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2738 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2739 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2740 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2741 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2742 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2743 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2744 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2745 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2746 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2747 /** @} */
2748
2749 /** @name Function pointers for Both Shadow and Guest paging.
2750 * @{
2751 */
2752 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2753 /* no pfnR3BthTrap0eHandler */
2754 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2755 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2756 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2757 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2758#ifdef VBOX_STRICT
2759 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2760#endif
2761 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2762 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2763
2764 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2765 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2766 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2767 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2768 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2769#ifdef VBOX_STRICT
2770 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2771#endif
2772 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2773 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2774
2775 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2776 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2777 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2778 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2779 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2780#ifdef VBOX_STRICT
2781 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2782#endif
2783 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2784 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2785 /** @} */
2786} PGMMODEDATA, *PPGMMODEDATA;
2787
2788
2789#ifdef VBOX_WITH_STATISTICS
2790/**
2791 * PGM statistics.
2792 *
2793 * These lives on the heap when compiled in as they would otherwise waste
2794 * unecessary space in release builds.
2795 */
2796typedef struct PGMSTATS
2797{
2798 /* R3 only: */
2799 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2800 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2801
2802 /* R3+RZ */
2803 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2804 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2805 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2806 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2807 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2808 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2809 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2810 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2811 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2812 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2813 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2814 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2815 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2816 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2817 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2818 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2819 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2820 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2821 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2822 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2823 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2824 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2825 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2826 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2827/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2828 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2829 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2830/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2831
2832 /* RC only: */
2833 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2834 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2835
2836 STAMCOUNTER StatRZPhysRead;
2837 STAMCOUNTER StatRZPhysReadBytes;
2838 STAMCOUNTER StatRZPhysWrite;
2839 STAMCOUNTER StatRZPhysWriteBytes;
2840 STAMCOUNTER StatR3PhysRead;
2841 STAMCOUNTER StatR3PhysReadBytes;
2842 STAMCOUNTER StatR3PhysWrite;
2843 STAMCOUNTER StatR3PhysWriteBytes;
2844 STAMCOUNTER StatRCPhysRead;
2845 STAMCOUNTER StatRCPhysReadBytes;
2846 STAMCOUNTER StatRCPhysWrite;
2847 STAMCOUNTER StatRCPhysWriteBytes;
2848
2849 STAMCOUNTER StatRZPhysSimpleRead;
2850 STAMCOUNTER StatRZPhysSimpleReadBytes;
2851 STAMCOUNTER StatRZPhysSimpleWrite;
2852 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2853 STAMCOUNTER StatR3PhysSimpleRead;
2854 STAMCOUNTER StatR3PhysSimpleReadBytes;
2855 STAMCOUNTER StatR3PhysSimpleWrite;
2856 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2857 STAMCOUNTER StatRCPhysSimpleRead;
2858 STAMCOUNTER StatRCPhysSimpleReadBytes;
2859 STAMCOUNTER StatRCPhysSimpleWrite;
2860 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2861
2862 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2863 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2864 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2865 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2866 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2867 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2868 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2869
2870 /** Time spent by the host OS for large page allocation. */
2871 STAMPROFILE StatAllocLargePage;
2872 /** Time spent clearing the newly allocated large pages. */
2873 STAMPROFILE StatClearLargePage;
2874 /** pgmPhysIsValidLargePage profiling - R3 */
2875 STAMPROFILE StatR3IsValidLargePage;
2876 /** pgmPhysIsValidLargePage profiling - RZ*/
2877 STAMPROFILE StatRZIsValidLargePage;
2878
2879 STAMPROFILE StatChunkAging;
2880 STAMPROFILE StatChunkFindCandidate;
2881 STAMPROFILE StatChunkUnmap;
2882 STAMPROFILE StatChunkMap;
2883} PGMSTATS;
2884#endif /* VBOX_WITH_STATISTICS */
2885
2886
2887/**
2888 * Converts a PGM pointer into a VM pointer.
2889 * @returns Pointer to the VM structure the PGM is part of.
2890 * @param pPGM Pointer to PGM instance data.
2891 */
2892#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2893
2894/**
2895 * PGM Data (part of VM)
2896 */
2897typedef struct PGM
2898{
2899 /** Offset to the VM structure. */
2900 int32_t offVM;
2901 /** Offset of the PGMCPU structure relative to VMCPU. */
2902 int32_t offVCpuPGM;
2903
2904 /** @cfgm{RamPreAlloc, boolean, false}
2905 * Indicates whether the base RAM should all be allocated before starting
2906 * the VM (default), or if it should be allocated when first written to.
2907 */
2908 bool fRamPreAlloc;
2909 /** Indicates whether write monitoring is currently in use.
2910 * This is used to prevent conflicts between live saving and page sharing
2911 * detection. */
2912 bool fPhysWriteMonitoringEngaged;
2913 /** Set if the CPU has less than 52-bit physical address width.
2914 * This is used */
2915 bool fLessThan52PhysicalAddressBits;
2916 /** Set when nested paging is active.
2917 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2918 * compilers optimize the code better. Whether we use nested paging or
2919 * not is something we find out during VMM initialization and we won't
2920 * change this later on. */
2921 bool fNestedPaging;
2922 /** The host paging mode. (This is what SUPLib reports.) */
2923 SUPPAGINGMODE enmHostMode;
2924 /** We're not in a state which permits writes to guest memory.
2925 * (Only used in strict builds.) */
2926 bool fNoMorePhysWrites;
2927 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2928 bool afAlignment1[3];
2929
2930 /** Indicates that PGMR3FinalizeMappings has been called and that further
2931 * PGMR3MapIntermediate calls will be rejected. */
2932 bool fFinalizedMappings;
2933 /** If set no conflict checks are required. */
2934 bool fMappingsFixed;
2935 /** If set if restored as fixed but we were unable to re-fixate at the old
2936 * location because of room or address incompatibilities. */
2937 bool fMappingsFixedRestored;
2938 /** If set, then no mappings are put into the shadow page table.
2939 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2940 bool fMappingsDisabled;
2941 /** Size of fixed mapping.
2942 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2943 uint32_t cbMappingFixed;
2944 /** Generation ID for the RAM ranges. This member is incremented everytime
2945 * a RAM range is linked or unlinked. */
2946 uint32_t volatile idRamRangesGen;
2947
2948 /** Base address (GC) of fixed mapping.
2949 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2950 RTGCPTR GCPtrMappingFixed;
2951 /** The address of the previous RAM range mapping. */
2952 RTGCPTR GCPtrPrevRamRangeMapping;
2953
2954 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2955 RTGCPHYS GCPhys4MBPSEMask;
2956 /** Mask containing the invalid bits of a guest physical address.
2957 * @remarks this does not stop at bit 52. */
2958 RTGCPHYS GCPhysInvAddrMask;
2959
2960
2961 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2962 * This is sorted by physical address and contains no overlapping ranges. */
2963 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2964 /** PGM offset based trees - R3 Ptr. */
2965 R3PTRTYPE(PPGMTREES) pTreesR3;
2966 /** Caching the last physical handler we looked up in R3. */
2967 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2968 /** Shadow Page Pool - R3 Ptr. */
2969 R3PTRTYPE(PPGMPOOL) pPoolR3;
2970 /** Linked list of GC mappings - for HC.
2971 * The list is sorted ascending on address. */
2972 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2973 /** Pointer to the list of ROM ranges - for R3.
2974 * This is sorted by physical address and contains no overlapping ranges. */
2975 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2976 /** Pointer to the list of MMIO2 ranges - for R3.
2977 * Registration order. */
2978 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2979 /** Pointer to SHW+GST mode data (function pointers).
2980 * The index into this table is made up from */
2981 R3PTRTYPE(PPGMMODEDATA) paModeData;
2982 /*RTR3PTR R3PtrAlignment0;*/
2983
2984
2985 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2986 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2987 /** PGM offset based trees - R0 Ptr. */
2988 R0PTRTYPE(PPGMTREES) pTreesR0;
2989 /** Caching the last physical handler we looked up in R0. */
2990 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2991 /** Shadow Page Pool - R0 Ptr. */
2992 R0PTRTYPE(PPGMPOOL) pPoolR0;
2993 /** Linked list of GC mappings - for R0.
2994 * The list is sorted ascending on address. */
2995 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2996 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2997 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2998 /*RTR0PTR R0PtrAlignment0;*/
2999
3000
3001 /** RC pointer corresponding to PGM::pRamRangesR3. */
3002 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
3003 /** PGM offset based trees - RC Ptr. */
3004 RCPTRTYPE(PPGMTREES) pTreesRC;
3005 /** Caching the last physical handler we looked up in RC. */
3006 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3007 /** Shadow Page Pool - RC Ptr. */
3008 RCPTRTYPE(PPGMPOOL) pPoolRC;
3009 /** Linked list of GC mappings - for RC.
3010 * The list is sorted ascending on address. */
3011 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3012 /** RC pointer corresponding to PGM::pRomRangesR3. */
3013 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3014 /*RTRCPTR RCPtrAlignment0;*/
3015 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3016 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3017 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3018 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3019
3020
3021 /** Pointer to the 5 page CR3 content mapping.
3022 * The first page is always the CR3 (in some form) while the 4 other pages
3023 * are used of the PDs in PAE mode. */
3024 RTGCPTR GCPtrCR3Mapping;
3025
3026 /** @name Intermediate Context
3027 * @{ */
3028 /** Pointer to the intermediate page directory - Normal. */
3029 R3PTRTYPE(PX86PD) pInterPD;
3030 /** Pointer to the intermedate page tables - Normal.
3031 * There are two page tables, one for the identity mapping and one for
3032 * the host context mapping (of the core code). */
3033 R3PTRTYPE(PX86PT) apInterPTs[2];
3034 /** Pointer to the intermedate page tables - PAE. */
3035 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3036 /** Pointer to the intermedate page directory - PAE. */
3037 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3038 /** Pointer to the intermedate page directory - PAE. */
3039 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3040 /** Pointer to the intermedate page-map level 4 - AMD64. */
3041 R3PTRTYPE(PX86PML4) pInterPaePML4;
3042 /** Pointer to the intermedate page directory - AMD64. */
3043 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3044 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3045 RTHCPHYS HCPhysInterPD;
3046 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3047 RTHCPHYS HCPhysInterPaePDPT;
3048 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3049 RTHCPHYS HCPhysInterPaePML4;
3050 /** @} */
3051
3052 /** Base address of the dynamic page mapping area.
3053 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3054 *
3055 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3056 * work out. Some cleaning up of the initialization that would
3057 * remove this memory is yet to be done...
3058 */
3059 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3060 /** The address of the raw-mode context mapping cache. */
3061 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3062 /** The address of the ring-0 mapping cache if we're making use of it. */
3063 RTR0PTR pvR0DynMapUsed;
3064#if HC_ARCH_BITS == 32
3065 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
3066 uint32_t u32Alignment2;
3067#endif
3068
3069 /** PGM critical section.
3070 * This protects the physical & virtual access handlers, ram ranges,
3071 * and the page flag updating (some of it anyway).
3072 */
3073 PDMCRITSECT CritSect;
3074
3075 /**
3076 * Data associated with managing the ring-3 mappings of the allocation chunks.
3077 */
3078 struct
3079 {
3080 /** The chunk tree, ordered by chunk id. */
3081#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3082 R3PTRTYPE(PAVLU32NODECORE) pTree;
3083#else
3084 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3085#endif
3086#if HC_ARCH_BITS == 32
3087 uint32_t u32Alignment;
3088#endif
3089 /** The chunk mapping TLB. */
3090 PGMCHUNKR3MAPTLB Tlb;
3091 /** The number of mapped chunks. */
3092 uint32_t c;
3093 /** The maximum number of mapped chunks.
3094 * @cfgm PGM/MaxRing3Chunks */
3095 uint32_t cMax;
3096 /** The current time. */
3097 uint32_t iNow;
3098 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3099 uint32_t AgeingCountdown;
3100 } ChunkR3Map;
3101
3102 /**
3103 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3104 */
3105 PGMPAGER3MAPTLB PhysTlbHC;
3106
3107 /** @name The zero page.
3108 * @{ */
3109 /** The host physical address of the zero page. */
3110 RTHCPHYS HCPhysZeroPg;
3111 /** The ring-3 mapping of the zero page. */
3112 RTR3PTR pvZeroPgR3;
3113 /** The ring-0 mapping of the zero page. */
3114 RTR0PTR pvZeroPgR0;
3115 /** The GC mapping of the zero page. */
3116 RTRCPTR pvZeroPgRC;
3117 RTRCPTR RCPtrAlignment3;
3118 /** @}*/
3119
3120 /** @name The Invalid MMIO page.
3121 * This page is filled with 0xfeedface.
3122 * @{ */
3123 /** The host physical address of the invalid MMIO page. */
3124 RTHCPHYS HCPhysMmioPg;
3125 /** The host pysical address of the invalid MMIO page pluss all invalid
3126 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3127 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3128 RTHCPHYS HCPhysInvMmioPg;
3129 /** The ring-3 mapping of the invalid MMIO page. */
3130 RTR3PTR pvMmioPgR3;
3131#if HC_ARCH_BITS == 32
3132 RTR3PTR R3PtrAlignment4;
3133#endif
3134 /** @} */
3135
3136
3137 /** The number of handy pages. */
3138 uint32_t cHandyPages;
3139
3140 /** The number of large handy pages. */
3141 uint32_t cLargeHandyPages;
3142
3143 /**
3144 * Array of handy pages.
3145 *
3146 * This array is used in a two way communication between pgmPhysAllocPage
3147 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3148 * an intermediary.
3149 *
3150 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3151 * (The current size of 32 pages, means 128 KB of handy memory.)
3152 */
3153 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3154
3155 /**
3156 * Array of large handy pages. (currently size 1)
3157 *
3158 * This array is used in a two way communication between pgmPhysAllocLargePage
3159 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3160 * an intermediary.
3161 */
3162 GMMPAGEDESC aLargeHandyPage[1];
3163
3164 /**
3165 * Live save data.
3166 */
3167 struct
3168 {
3169 /** Per type statistics. */
3170 struct
3171 {
3172 /** The number of ready pages. */
3173 uint32_t cReadyPages;
3174 /** The number of dirty pages. */
3175 uint32_t cDirtyPages;
3176 /** The number of ready zero pages. */
3177 uint32_t cZeroPages;
3178 /** The number of write monitored pages. */
3179 uint32_t cMonitoredPages;
3180 } Rom,
3181 Mmio2,
3182 Ram;
3183 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3184 uint32_t cIgnoredPages;
3185 /** Indicates that a live save operation is active. */
3186 bool fActive;
3187 /** Padding. */
3188 bool afReserved[2];
3189 /** The next history index. */
3190 uint8_t iDirtyPagesHistory;
3191 /** History of the total amount of dirty pages. */
3192 uint32_t acDirtyPagesHistory[64];
3193 /** Short term dirty page average. */
3194 uint32_t cDirtyPagesShort;
3195 /** Long term dirty page average. */
3196 uint32_t cDirtyPagesLong;
3197 /** The number of saved pages. This is used to get some kind of estimate of the
3198 * link speed so we can decide when we're done. It is reset after the first
3199 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3200 * zero pages. */
3201 uint64_t cSavedPages;
3202 /** The nanosecond timestamp when cSavedPages was 0. */
3203 uint64_t uSaveStartNS;
3204 /** Pages per second (for statistics). */
3205 uint32_t cPagesPerSecond;
3206 uint32_t cAlignment;
3207 } LiveSave;
3208
3209 /** @name Error injection.
3210 * @{ */
3211 /** Inject handy page allocation errors pretending we're completely out of
3212 * memory. */
3213 bool volatile fErrInjHandyPages;
3214 /** Padding. */
3215 bool afReserved[3];
3216 /** @} */
3217
3218 /** @name Release Statistics
3219 * @{ */
3220 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3221 uint32_t cPrivatePages; /**< The number of private pages. */
3222 uint32_t cSharedPages; /**< The number of shared pages. */
3223 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3224 uint32_t cZeroPages; /**< The number of zero backed pages. */
3225 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3226 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3227 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3228 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3229 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3230 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3231 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3232 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3233/* uint32_t aAlignment4[1]; */
3234
3235 /** The number of times we were forced to change the hypervisor region location. */
3236 STAMCOUNTER cRelocations;
3237
3238 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
3239 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3240 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3241 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3242 /** @} */
3243
3244#ifdef VBOX_WITH_STATISTICS
3245 /** @name Statistics on the heap.
3246 * @{ */
3247 R3PTRTYPE(PGMSTATS *) pStatsR3;
3248 R0PTRTYPE(PGMSTATS *) pStatsR0;
3249 RCPTRTYPE(PGMSTATS *) pStatsRC;
3250 RTRCPTR RCPtrAlignment;
3251 /** @} */
3252#endif
3253} PGM;
3254#ifndef IN_TSTVMSTRUCTGC /* HACK */
3255AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3256AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3257AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3258AssertCompileMemberAlignment(PGM, CritSect, 8);
3259AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3260AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3261AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3262AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3263AssertCompileMemberAlignment(PGM, cRelocations, 8);
3264#endif /* !IN_TSTVMSTRUCTGC */
3265/** Pointer to the PGM instance data. */
3266typedef PGM *PPGM;
3267
3268
3269
3270typedef struct PGMCPUSTATS
3271{
3272 /* Common */
3273 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3274 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3275
3276 /* R0 only: */
3277 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3278 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3279
3280 /* RZ only: */
3281 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3282 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3283 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3284 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3285 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3286 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3287 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3288 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3289 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3290 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3291 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3292 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3293 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3294 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3295 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3296 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3297 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3298 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3299 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3300 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3301 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3302 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3303 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3304 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3305 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3306 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3307 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3308 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3309 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3310 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3311 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3312 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3313 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3314 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3315 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3316 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3317 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3318 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3319 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3320 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3321 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3322 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3323 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3324 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3325 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3326 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3327 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3328 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3329 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3330 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3331 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3332 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3333 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3334 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3335 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3336 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3337 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3338 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3339 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3340 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3341 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3342 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restorting to subset flushes. */
3343 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3344 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3345 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3346 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3347 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3348 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3349 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3350 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3351 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3352 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3353 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3354 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3355 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3356 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3357
3358 /* HC - R3 and (maybe) R0: */
3359
3360 /* RZ & R3: */
3361 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3362 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3363 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3364 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3365 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3366 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3367 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3368 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3369 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3370 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3371 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3372 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3373 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3374 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3375 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3376 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3377 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3378 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3379 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3380 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3381 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3382 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3383 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3384 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3385 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3386 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3387 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3388 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3389 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3390 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3391 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3392 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3393 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3394 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3395 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3396 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3397 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3398 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3399 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3400 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3401 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3402 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3403 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3404 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3405 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3406 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3407 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3408
3409 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3410 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3411 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3412 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3413 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3414 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3415 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3416 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3417 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3418 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3419 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3420 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3421 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3422 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3423 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3424 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3425 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3426 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3427 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3428 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3429 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3430 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3431 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3432 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3433 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3434 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3435 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3436 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3437 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3438 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3439 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3440 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3441 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3442 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3443 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3444 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3445 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3446 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3447 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3448 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3449 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3450 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3451 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3452 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3453 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3454 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3455 /** @} */
3456} PGMCPUSTATS;
3457
3458
3459/**
3460 * Converts a PGMCPU pointer into a VM pointer.
3461 * @returns Pointer to the VM structure the PGM is part of.
3462 * @param pPGM Pointer to PGMCPU instance data.
3463 */
3464#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3465
3466/**
3467 * Converts a PGMCPU pointer into a PGM pointer.
3468 * @returns Pointer to the VM structure the PGM is part of.
3469 * @param pPGM Pointer to PGMCPU instance data.
3470 */
3471#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3472
3473/**
3474 * PGMCPU Data (part of VMCPU).
3475 */
3476typedef struct PGMCPU
3477{
3478 /** Offset to the VM structure. */
3479 int32_t offVM;
3480 /** Offset to the VMCPU structure. */
3481 int32_t offVCpu;
3482 /** Offset of the PGM structure relative to VMCPU. */
3483 int32_t offPGM;
3484 uint32_t uPadding0; /**< structure size alignment. */
3485
3486#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3487 /** Automatically tracked physical memory mapping set.
3488 * Ring-0 and strict raw-mode builds. */
3489 PGMMAPSET AutoSet;
3490#endif
3491
3492 /** A20 gate mask.
3493 * Our current approach to A20 emulation is to let REM do it and don't bother
3494 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3495 * But whould need arrise, we'll subject physical addresses to this mask. */
3496 RTGCPHYS GCPhysA20Mask;
3497 /** A20 gate state - boolean! */
3498 bool fA20Enabled;
3499 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3500 bool fNoExecuteEnabled;
3501 /** Unused bits. */
3502 bool afUnused[2];
3503
3504 /** What needs syncing (PGM_SYNC_*).
3505 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3506 * PGMFlushTLB, and PGMR3Load. */
3507 RTUINT fSyncFlags;
3508
3509 /** The shadow paging mode. */
3510 PGMMODE enmShadowMode;
3511 /** The guest paging mode. */
3512 PGMMODE enmGuestMode;
3513
3514 /** The current physical address representing in the guest CR3 register. */
3515 RTGCPHYS GCPhysCR3;
3516
3517 /** @name 32-bit Guest Paging.
3518 * @{ */
3519 /** The guest's page directory, R3 pointer. */
3520 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3521#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3522 /** The guest's page directory, R0 pointer. */
3523 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3524#endif
3525 /** The guest's page directory, static RC mapping. */
3526 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3527 /** Mask containing the MBZ bits of a big page PDE. */
3528 uint32_t fGst32BitMbzBigPdeMask;
3529 /** Set if the page size extension (PSE) is enabled. */
3530 bool fGst32BitPageSizeExtension;
3531 /** Alignment padding. */
3532 bool afAlignment2[3];
3533 /** @} */
3534
3535 /** @name PAE Guest Paging.
3536 * @{ */
3537 /** The guest's page directory pointer table, static RC mapping. */
3538 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3539 /** The guest's page directory pointer table, R3 pointer. */
3540 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3541#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3542 /** The guest's page directory pointer table, R0 pointer. */
3543 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3544#endif
3545
3546 /** The guest's page directories, R3 pointers.
3547 * These are individual pointers and don't have to be adjecent.
3548 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3549 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3550 /** The guest's page directories, R0 pointers.
3551 * Same restrictions as apGstPaePDsR3. */
3552#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3553 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3554#endif
3555 /** The guest's page directories, static GC mapping.
3556 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3557 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3558 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3559 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3560 RTGCPHYS aGCPhysGstPaePDs[4];
3561 /** The physical addresses of the monitored guest page directories (PAE). */
3562 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3563 /** Mask containing the MBZ PTE bits. */
3564 uint64_t fGstPaeMbzPteMask;
3565 /** Mask containing the MBZ PDE bits. */
3566 uint64_t fGstPaeMbzPdeMask;
3567 /** Mask containing the MBZ big page PDE bits. */
3568 uint64_t fGstPaeMbzBigPdeMask;
3569 /** Mask containing the MBZ PDPE bits. */
3570 uint64_t fGstPaeMbzPdpeMask;
3571 /** @} */
3572
3573 /** @name AMD64 Guest Paging.
3574 * @{ */
3575 /** The guest's page directory pointer table, R3 pointer. */
3576 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3577#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3578 /** The guest's page directory pointer table, R0 pointer. */
3579 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3580#else
3581 RTR0PTR alignment6b; /**< alignment equalizer. */
3582#endif
3583 /** Mask containing the MBZ PTE bits. */
3584 uint64_t fGstAmd64MbzPteMask;
3585 /** Mask containing the MBZ PDE bits. */
3586 uint64_t fGstAmd64MbzPdeMask;
3587 /** Mask containing the MBZ big page PDE bits. */
3588 uint64_t fGstAmd64MbzBigPdeMask;
3589 /** Mask containing the MBZ PDPE bits. */
3590 uint64_t fGstAmd64MbzPdpeMask;
3591 /** Mask containing the MBZ big page PDPE bits. */
3592 uint64_t fGstAmd64MbzBigPdpeMask;
3593 /** Mask containing the MBZ PML4E bits. */
3594 uint64_t fGstAmd64MbzPml4eMask;
3595 /** Mask containing the PDPE bits that we shadow. */
3596 uint64_t fGstAmd64ShadowedPdpeMask;
3597 /** Mask containing the PML4E bits that we shadow. */
3598 uint64_t fGstAmd64ShadowedPml4eMask;
3599 /** @} */
3600
3601 /** @name PAE and AMD64 Guest Paging.
3602 * @{ */
3603 /** Mask containing the PTE bits that we shadow. */
3604 uint64_t fGst64ShadowedPteMask;
3605 /** Mask containing the PDE bits that we shadow. */
3606 uint64_t fGst64ShadowedPdeMask;
3607 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3608 uint64_t fGst64ShadowedBigPdeMask;
3609 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3610 uint64_t fGst64ShadowedBigPde4PteMask;
3611 /** @} */
3612
3613 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3614 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3615 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3616 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3617 /** Pointer to the page of the current active CR3 - RC Ptr. */
3618 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3619 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3620 uint32_t iShwUser;
3621 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3622 uint32_t iShwUserTable;
3623# if HC_ARCH_BITS == 64
3624 RTRCPTR alignment6; /**< structure size alignment. */
3625# endif
3626 /** @} */
3627
3628 /** @name Function pointers for Shadow paging.
3629 * @{
3630 */
3631 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3632 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3633 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3634 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3635
3636 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3637 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3638
3639 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3640 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3641
3642 /** @} */
3643
3644 /** @name Function pointers for Guest paging.
3645 * @{
3646 */
3647 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3648 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3649 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3650 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3651 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3652 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3653 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3654 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3655#if HC_ARCH_BITS == 64
3656 RTRCPTR alignment3; /**< structure size alignment. */
3657#endif
3658
3659 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3660 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3661 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3662 /** @} */
3663
3664 /** @name Function pointers for Both Shadow and Guest paging.
3665 * @{
3666 */
3667 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3668 /* no pfnR3BthTrap0eHandler */
3669 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3670 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3671 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3672 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3673 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3674 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3675 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3676
3677 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3678 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3679 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3680 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3681 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3682 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3683 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3684 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3685
3686 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3687 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3688 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3689 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3690 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3691 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3692 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3693 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3694#if 0
3695 RTRCPTR alignment2; /**< structure size alignment. */
3696#endif
3697 /** @} */
3698
3699 /** For saving stack space, the disassembler state is allocated here instead of
3700 * on the stack.
3701 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3702 union
3703 {
3704 /** The disassembler scratch space. */
3705 DISCPUSTATE DisState;
3706 /** Padding. */
3707 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3708 };
3709
3710 /** Count the number of pgm pool access handler calls. */
3711 uint64_t cPoolAccessHandler;
3712
3713 /** @name Release Statistics
3714 * @{ */
3715 /** The number of times the guest has switched mode since last reset or statistics reset. */
3716 STAMCOUNTER cGuestModeChanges;
3717 /** @} */
3718
3719#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3720 /** @name Statistics
3721 * @{ */
3722 /** RC: Pointer to the statistics. */
3723 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3724 /** RC: Which statistic this \#PF should be attributed to. */
3725 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3726 /** R0: Pointer to the statistics. */
3727 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3728 /** R0: Which statistic this \#PF should be attributed to. */
3729 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3730 /** R3: Pointer to the statistics. */
3731 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3732 /** Alignment padding. */
3733 RTR3PTR pPaddingR3;
3734 /** @} */
3735#endif /* VBOX_WITH_STATISTICS */
3736} PGMCPU;
3737/** Pointer to the per-cpu PGM data. */
3738typedef PGMCPU *PPGMCPU;
3739
3740
3741/** @name PGM::fSyncFlags Flags
3742 * @{
3743 */
3744/** Updates the virtual access handler state bit in PGMPAGE. */
3745#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3746/** Always sync CR3. */
3747#define PGM_SYNC_ALWAYS RT_BIT(1)
3748/** Check monitoring on next CR3 (re)load and invalidate page.
3749 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3750#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3751/** Check guest mapping in SyncCR3. */
3752#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3753/** Clear the page pool (a light weight flush). */
3754#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3755#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3756/** @} */
3757
3758
3759RT_C_DECLS_BEGIN
3760
3761int pgmLock(PVM pVM);
3762void pgmUnlock(PVM pVM);
3763
3764int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3765int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3766int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3767PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3768int pgmMapResolveConflicts(PVM pVM);
3769DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3770
3771void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3772bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3773void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3774int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3775DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3776#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3777void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3778#else
3779# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3780#endif
3781DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3782int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3783
3784int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3785int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3786int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3787int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3788int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3789void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3790int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3791int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3792int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3793int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3794int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3795int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3796int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3797VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3798VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3799int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3800
3801#ifdef IN_RING3
3802void pgmR3PhysRelinkRamRanges(PVM pVM);
3803int pgmR3PhysRamPreAllocate(PVM pVM);
3804int pgmR3PhysRamReset(PVM pVM);
3805int pgmR3PhysRomReset(PVM pVM);
3806int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3807int pgmR3PhysRamTerm(PVM pVM);
3808void pgmR3PhysRomTerm(PVM pVM);
3809
3810int pgmR3PoolInit(PVM pVM);
3811void pgmR3PoolRelocate(PVM pVM);
3812void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3813void pgmR3PoolReset(PVM pVM);
3814void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3815DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3816void pgmR3PoolWriteProtectPages(PVM pVM);
3817
3818#endif /* IN_RING3 */
3819#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || IN_RC
3820int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3821int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3822# ifdef LOG_ENABLED
3823void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3824# else
3825void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3826# endif
3827#endif
3828int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
3829 uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3830
3831DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
3832 PPPGMPOOLPAGE ppPage)
3833{
3834 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
3835}
3836
3837void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3838void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3839int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3840void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3841PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3842PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3843int pgmPoolSyncCR3(PVMCPU pVCpu);
3844bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3845int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3846void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3847void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3848DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3849{
3850 return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3851}
3852
3853uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3854void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3855void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3856int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3857void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3858
3859void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3860void pgmPoolResetDirtyPages(PVM pVM);
3861
3862int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3863int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3864
3865void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3866void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3867int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3868int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3869
3870int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3871int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3872
3873int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3874int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3875int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3876int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3877
3878# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3879DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3880DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3881# endif
3882
3883RT_C_DECLS_END
3884
3885/** @} */
3886
3887#endif
3888
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