PGMInternal.h@ 32225

Last change on this file since 32225 was 32087, checked in by vboxsync, 15 years ago
PGM: Account for aliased and off pages in physical handlers so that PGMR0Trap0eHandlerNPMisconfig can avoid resolving the PGMPAGE when these features are not used.
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1	/* $Id: PGMInternal.h 32087 2010-08-30 12:23:05Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/dbg.h>
25	#include <VBox/stam.h>
26	#include <VBox/param.h>
27	#include <VBox/vmm.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdmcritsect.h>
30	#include <VBox/pdmapi.h>
31	#include <VBox/dis.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/log.h>
34	#include <VBox/gmm.h>
35	#include <VBox/hwaccm.h>
36	#include <VBox/hwacc_vmx.h>
37	#include <include/internal/pgm.h>
38	#include <iprt/asm.h>
39	#include <iprt/assert.h>
40	#include <iprt/avl.h>
41	#include <iprt/critsect.h>
42	#include <iprt/sha.h>
43
44
45
46	/** @defgroup grp_pgm_int Internals
47	* @ingroup grp_pgm
48	* @internal
49	* @{
50	*/
51
52
53	/** @name PGM Compile Time Config
54	* @{
55	*/
56
57	/**
58	* Indicates that there are no guest mappings to care about.
59	* Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60	*/
61	#if defined(IN_RING0) \|\| !defined(VBOX_WITH_RAW_MODE)
62	# define PGM_WITHOUT_MAPPINGS
63	#endif
64
65	/**
66	* Check and skip global PDEs for non-global flushes
67	*/
68	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70	/**
71	* Optimization for PAE page tables that are modified often
72	*/
73	//#if 0 /* disabled again while debugging */
74	#ifndef IN_RC
75	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76	#endif
77	//#endif
78
79	/**
80	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
81	*/
82	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83	# define PGM_WITH_LARGE_PAGES
84	#endif
85
86	/**
87	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88	* VMX_EXIT_EPT_MISCONFIG.
89	*/
90	#if 1 /* testing */
91	# define PGM_WITH_MMIO_OPTIMIZATIONS
92	#endif
93
94	/**
95	* Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96	*/
97	#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98	# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99	#endif
100
101	/**
102	* Sync N pages instead of a whole page table
103	*/
104	#define PGM_SYNC_N_PAGES
105
106	/**
107	* Number of pages to sync during a page fault
108	*
109	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111	*
112	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113	* world switch overhead, so let's sync more.
114	*/
115	# ifdef IN_RING0
116	/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118	* but ~5% fewer faults.
119	*/
120	# define PGM_SYNC_NR_PAGES 32
121	#else
122	# define PGM_SYNC_NR_PAGES 8
123	#endif
124
125	/**
126	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127	*/
128	#define PGM_MAX_PHYSCACHE_ENTRIES 64
129	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132	/** @def PGMPOOL_CFG_MAX_GROW
133	* The maximum number of pages to add to the pool in one go.
134	*/
135	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
139	*/
140	#ifdef VBOX_STRICT
141	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142	#endif
143
144	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145	* Enables the experimental lazy page allocation code. */
146	/#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
147
148	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149	* Enables real write monitoring of pages, i.e. mapping them read-only and
150	* only making them writable when getting a write access #PF. */
151	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153	/** @} */
154
155
156	/** @name PDPT and PML4 flags.
157	* These are placed in the three bits available for system programs in
158	* the PDPT and PML4 entries.
159	* @{ */
160	/** The entry is a permanent one and it's must always be present.
161	* Never free such an entry. */
162	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163	/** Mapping (hypervisor allocated pagetable). */
164	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165	/** @} */
166
167	/** @name Page directory flags.
168	* These are placed in the three bits available for system programs in
169	* the page directory entries.
170	* @{ */
171	/** Mapping (hypervisor allocated pagetable). */
172	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173	/** Made read-only to facilitate dirty bit tracking. */
174	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175	/** @} */
176
177	/** @name Page flags.
178	* These are placed in the three bits available for system programs in
179	* the page entries.
180	* @{ */
181	/** Made read-only to facilitate dirty bit tracking. */
182	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185	/** Scanned and approved by CSAM (tm).
186	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
187	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
188	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189	#endif
190
191	/** @} */
192
193	/** @name Defines used to indicate the shadow and guest paging in the templates.
194	* @{ */
195	#define PGM_TYPE_REAL 1
196	#define PGM_TYPE_PROT 2
197	#define PGM_TYPE_32BIT 3
198	#define PGM_TYPE_PAE 4
199	#define PGM_TYPE_AMD64 5
200	#define PGM_TYPE_NESTED 6
201	#define PGM_TYPE_EPT 7
202	#define PGM_TYPE_MAX PGM_TYPE_EPT
203	/** @} */
204
205	/** Macro for checking if the guest is using paging.
206	* @param uGstType PGM_TYPE_*
207	* @param uShwType PGM_TYPE_*
208	* @remark ASSUMES certain order of the PGM_TYPE_* values.
209	*/
210	#define PGM_WITH_PAGING(uGstType, uShwType) \
211	( (uGstType) >= PGM_TYPE_32BIT \
212	&& (uShwType) != PGM_TYPE_NESTED \
213	&& (uShwType) != PGM_TYPE_EPT)
214
215	/** Macro for checking if the guest supports the NX bit.
216	* @param uGstType PGM_TYPE_*
217	* @param uShwType PGM_TYPE_*
218	* @remark ASSUMES certain order of the PGM_TYPE_* values.
219	*/
220	#define PGM_WITH_NX(uGstType, uShwType) \
221	( (uGstType) >= PGM_TYPE_PAE \
222	&& (uShwType) != PGM_TYPE_NESTED \
223	&& (uShwType) != PGM_TYPE_EPT)
224
225
226	/** @def PGM_HCPHYS_2_PTR
227	* Maps a HC physical page pool address to a virtual address.
228	*
229	* @returns VBox status code.
230	* @param pVM The VM handle.
231	* @param pVCpu The current CPU.
232	* @param HCPhys The HC physical address to map to a virtual one.
233	* @param ppv Where to store the virtual address. No need to cast
234	* this.
235	*
236	* @remark Use with care as we don't have so much dynamic mapping space in
237	* ring-0 on 32-bit darwin and in RC.
238	* @remark There is no need to assert on the result.
239	*/
240	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
241	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242	pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243	#else
244	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246	#endif
247
248	/** @def PGM_GCPHYS_2_PTR_V2
249	* Maps a GC physical page address to a virtual address.
250	*
251	* @returns VBox status code.
252	* @param pVM The VM handle.
253	* @param pVCpu The current CPU.
254	* @param GCPhys The GC physical address to map to a virtual one.
255	* @param ppv Where to store the virtual address. No need to cast this.
256	*
257	* @remark Use with care as we don't have so much dynamic mapping space in
258	* ring-0 on 32-bit darwin and in RC.
259	* @remark There is no need to assert on the result.
260	*/
261	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
262	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264	#else
265	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267	#endif
268
269	/** @def PGM_GCPHYS_2_PTR
270	* Maps a GC physical page address to a virtual address.
271	*
272	* @returns VBox status code.
273	* @param pVM The VM handle.
274	* @param GCPhys The GC physical address to map to a virtual one.
275	* @param ppv Where to store the virtual address. No need to cast this.
276	*
277	* @remark Use with care as we don't have so much dynamic mapping space in
278	* ring-0 on 32-bit darwin and in RC.
279	* @remark There is no need to assert on the result.
280	*/
281	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284	* Maps a GC physical page address to a virtual address.
285	*
286	* @returns VBox status code.
287	* @param pVCpu The current CPU.
288	* @param GCPhys The GC physical address to map to a virtual one.
289	* @param ppv Where to store the virtual address. No need to cast this.
290	*
291	* @remark Use with care as we don't have so much dynamic mapping space in
292	* ring-0 on 32-bit darwin and in RC.
293	* @remark There is no need to assert on the result.
294	*/
295	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297	/** @def PGM_GCPHYS_2_PTR_EX
298	* Maps a unaligned GC physical page address to a virtual address.
299	*
300	* @returns VBox status code.
301	* @param pVM The VM handle.
302	* @param GCPhys The GC physical address to map to a virtual one.
303	* @param ppv Where to store the virtual address. No need to cast this.
304	*
305	* @remark Use with care as we don't have so much dynamic mapping space in
306	* ring-0 on 32-bit darwin and in RC.
307	* @remark There is no need to assert on the result.
308	*/
309	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312	#else
313	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315	#endif
316
317	/** @def PGM_DYNMAP_UNUSED_HINT
318	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319	* is no longer used.
320	*
321	* For best effect only apply this to the page that was mapped most recently.
322	*
323	* @param pVCpu The current CPU.
324	* @param pPage The pool page.
325	*/
326	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327	# ifdef LOG_ENABLED
328	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329	# else
330	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331	# endif
332	#else
333	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334	#endif
335
336	/** @def PGM_DYNMAP_UNUSED_HINT_VM
337	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338	* is no longer used.
339	*
340	* For best effect only apply this to the page that was mapped most recently.
341	*
342	* @param pVM The VM handle.
343	* @param pPage The pool page.
344	*/
345	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348	/** @def PGM_INVL_PG
349	* Invalidates a page.
350	*
351	* @param pVCpu The VMCPU handle.
352	* @param GCVirt The virtual address of the page to invalidate.
353	*/
354	#ifdef IN_RC
355	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356	#elif defined(IN_RING0)
357	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358	#else
359	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360	#endif
361
362	/** @def PGM_INVL_PG_ALL_VCPU
363	* Invalidates a page on all VCPUs
364	*
365	* @param pVM The VM handle.
366	* @param GCVirt The virtual address of the page to invalidate.
367	*/
368	#ifdef IN_RC
369	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370	#elif defined(IN_RING0)
371	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372	#else
373	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374	#endif
375
376	/** @def PGM_INVL_BIG_PG
377	* Invalidates a 4MB page directory entry.
378	*
379	* @param pVCpu The VMCPU handle.
380	* @param GCVirt The virtual address within the page directory to invalidate.
381	*/
382	#ifdef IN_RC
383	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384	#elif defined(IN_RING0)
385	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386	#else
387	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388	#endif
389
390	/** @def PGM_INVL_VCPU_TLBS()
391	* Invalidates the TLBs of the specified VCPU
392	*
393	* @param pVCpu The VMCPU handle.
394	*/
395	#ifdef IN_RC
396	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397	#elif defined(IN_RING0)
398	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399	#else
400	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401	#endif
402
403	/** @def PGM_INVL_ALL_VCPU_TLBS()
404	* Invalidates the TLBs of all VCPUs
405	*
406	* @param pVM The VM handle.
407	*/
408	#ifdef IN_RC
409	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410	#elif defined(IN_RING0)
411	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412	#else
413	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414	#endif
415
416
417	/** @name Safer Shadow PAE PT/PTE
418	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419	* present.
420	*
421	* @{
422	*/
423	#if 1
424	/**
425	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
426	* invalid entries for present.
427	* @sa X86PTEPAE.
428	*/
429	typedef union PGMSHWPTEPAE
430	{
431	/** Unsigned integer view */
432	X86PGPAEUINT uCareful;
433	/* Not other views. */
434	} PGMSHWPTEPAE;
435
436	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
443	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
446	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
452
453	/**
454	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
455	* invalid entries for present.
456	* @sa X86PTPAE.
457	*/
458	typedef struct PGMSHWPTPAE
459	{
460	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461	} PGMSHWPTPAE;
462
463	#else
464	typedef X86PTEPAE PGMSHWPTEPAE;
465	typedef X86PTPAE PGMSHWPTPAE;
466	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
473	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
476	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
482
483	#endif
484
485	/** Pointer to a shadow PAE PTE. */
486	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487	/** Pointer to a const shadow PAE PTE. */
488	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490	/** Pointer to a shadow PAE page table. */
491	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492	/** Pointer to a const shadow PAE page table. */
493	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494	/** @} */
495
496
497	/** Size of the GCPtrConflict array in PGMMAPPING.
498	* @remarks Must be a power of two. */
499	#define PGMMAPPING_CONFLICT_MAX 8
500
501	/**
502	* Structure for tracking GC Mappings.
503	*
504	* This structure is used by linked list in both GC and HC.
505	*/
506	typedef struct PGMMAPPING
507	{
508	/** Pointer to next entry. */
509	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510	/** Pointer to next entry. */
511	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512	/** Pointer to next entry. */
513	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514	/** Indicate whether this entry is finalized. */
515	bool fFinalized;
516	/** Start Virtual address. */
517	RTGCPTR GCPtr;
518	/** Last Virtual address (inclusive). */
519	RTGCPTR GCPtrLast;
520	/** Range size (bytes). */
521	RTGCPTR cb;
522	/** Pointer to relocation callback function. */
523	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524	/** User argument to the callback. */
525	R3PTRTYPE(void *) pvUser;
526	/** Mapping description / name. For easing debugging. */
527	R3PTRTYPE(const char *) pszDesc;
528	/** Last 8 addresses that caused conflicts. */
529	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530	/** Number of conflicts for this hypervisor mapping. */
531	uint32_t cConflicts;
532	/** Number of page tables. */
533	uint32_t cPTs;
534
535	/** Array of page table mapping data. Each entry
536	* describes one page table. The array can be longer
537	* than the declared length.
538	*/
539	struct
540	{
541	/** The HC physical address of the page table. */
542	RTHCPHYS HCPhysPT;
543	/** The HC physical address of the first PAE page table. */
544	RTHCPHYS HCPhysPaePT0;
545	/** The HC physical address of the second PAE page table. */
546	RTHCPHYS HCPhysPaePT1;
547	/** The HC virtual address of the 32-bit page table. */
548	R3PTRTYPE(PX86PT) pPTR3;
549	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551	/** The RC virtual address of the 32-bit page table. */
552	RCPTRTYPE(PX86PT) pPTRC;
553	/** The RC virtual address of the two PAE page table. */
554	RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555	/** The R0 virtual address of the 32-bit page table. */
556	R0PTRTYPE(PX86PT) pPTR0;
557	/** The R0 virtual address of the two PAE page table. */
558	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559	} aPTs[1];
560	} PGMMAPPING;
561	/** Pointer to structure for tracking GC Mappings. */
562	typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565	/**
566	* Physical page access handler structure.
567	*
568	* This is used to keep track of physical address ranges
569	* which are being monitored in some kind of way.
570	*/
571	typedef struct PGMPHYSHANDLER
572	{
573	AVLROGCPHYSNODECORE Core;
574	/** Access type. */
575	PGMPHYSHANDLERTYPE enmType;
576	/** Number of pages to update. */
577	uint32_t cPages;
578	/** Set if we have pages that have been aliased. */
579	uint32_t cAliasedPages;
580	/** Set if we have pages that have temporarily been disabled. */
581	uint32_t cTmpOffPages;
582	/** Pointer to R3 callback function. */
583	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
584	/** User argument for R3 handlers. */
585	R3PTRTYPE(void *) pvUserR3;
586	/** Pointer to R0 callback function. */
587	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
588	/** User argument for R0 handlers. */
589	R0PTRTYPE(void *) pvUserR0;
590	/** Pointer to RC callback function. */
591	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
592	/** User argument for RC handlers. */
593	RCPTRTYPE(void *) pvUserRC;
594	/** Description / Name. For easing debugging. */
595	R3PTRTYPE(const char *) pszDesc;
596	#ifdef VBOX_WITH_STATISTICS
597	/** Profiling of this handler. */
598	STAMPROFILE Stat;
599	#endif
600	} PGMPHYSHANDLER;
601	/** Pointer to a physical page access handler structure. */
602	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
603
604
605	/**
606	* Cache node for the physical addresses covered by a virtual handler.
607	*/
608	typedef struct PGMPHYS2VIRTHANDLER
609	{
610	/** Core node for the tree based on physical ranges. */
611	AVLROGCPHYSNODECORE Core;
612	/** Offset from this struct to the PGMVIRTHANDLER structure. */
613	int32_t offVirtHandler;
614	/** Offset of the next alias relative to this one.
615	* Bit 0 is used for indicating whether we're in the tree.
616	* Bit 1 is used for indicating that we're the head node.
617	*/
618	int32_t offNextAlias;
619	} PGMPHYS2VIRTHANDLER;
620	/** Pointer to a phys to virtual handler structure. */
621	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
622
623	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
624	* node is in the tree. */
625	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
626	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
627	* node is in the head of an alias chain.
628	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
629	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
630	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
631	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
632
633
634	/**
635	* Virtual page access handler structure.
636	*
637	* This is used to keep track of virtual address ranges
638	* which are being monitored in some kind of way.
639	*/
640	typedef struct PGMVIRTHANDLER
641	{
642	/** Core node for the tree based on virtual ranges. */
643	AVLROGCPTRNODECORE Core;
644	/** Size of the range (in bytes). */
645	RTGCPTR cb;
646	/** Number of cache pages. */
647	uint32_t cPages;
648	/** Access type. */
649	PGMVIRTHANDLERTYPE enmType;
650	/** Pointer to the RC callback function. */
651	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
652	#if HC_ARCH_BITS == 64
653	RTRCPTR padding;
654	#endif
655	/** Pointer to the R3 callback function for invalidation. */
656	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
657	/** Pointer to the R3 callback function. */
658	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
659	/** Description / Name. For easing debugging. */
660	R3PTRTYPE(const char *) pszDesc;
661	#ifdef VBOX_WITH_STATISTICS
662	/** Profiling of this handler. */
663	STAMPROFILE Stat;
664	#endif
665	/** Array of cached physical addresses for the monitored ranged. */
666	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
667	} PGMVIRTHANDLER;
668	/** Pointer to a virtual page access handler structure. */
669	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
670
671
672	/**
673	* Page type.
674	*
675	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
676	* @remarks This is used in the saved state, so changes to it requires bumping
677	* the saved state version.
678	* @todo So, convert to \#defines!
679	*/
680	typedef enum PGMPAGETYPE
681	{
682	/** The usual invalid zero entry. */
683	PGMPAGETYPE_INVALID = 0,
684	/** RAM page. (RWX) */
685	PGMPAGETYPE_RAM,
686	/** MMIO2 page. (RWX) */
687	PGMPAGETYPE_MMIO2,
688	/** MMIO2 page aliased over an MMIO page. (RWX)
689	* See PGMHandlerPhysicalPageAlias(). */
690	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
691	/** Shadowed ROM. (RWX) */
692	PGMPAGETYPE_ROM_SHADOW,
693	/** ROM page. (R-X) */
694	PGMPAGETYPE_ROM,
695	/** MMIO page. (---) */
696	PGMPAGETYPE_MMIO,
697	/** End of valid entries. */
698	PGMPAGETYPE_END
699	} PGMPAGETYPE;
700	AssertCompile(PGMPAGETYPE_END <= 7);
701
702	/** @name Page type predicates.
703	* @{ */
704	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
705	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
706	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
707	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
708	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
709	/** @} */
710
711
712	/**
713	* A Physical Guest Page tracking structure.
714	*
715	* The format of this structure is complicated because we have to fit a lot
716	* of information into as few bits as possible. The format is also subject
717	* to change (there is one comming up soon). Which means that for we'll be
718	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
719	* accesses to the structure.
720	*/
721	typedef struct PGMPAGE
722	{
723	/** The physical address and the Page ID. */
724	RTHCPHYS HCPhysAndPageID;
725	/** Combination of:
726	* - [0-7]: u2HandlerPhysStateY - the physical handler state
727	* (PGM_PAGE_HNDL_PHYS_STATE_*).
728	* - [8-9]: u2HandlerVirtStateY - the virtual handler state
729	* (PGM_PAGE_HNDL_VIRT_STATE_*).
730	* - [10]: u1FTDirty - indicator of dirty page for fault tolerance tracking
731	* - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
732	* - [15]: fWrittenToY - flag indicating that a write monitored page was
733	* written to when set.
734	* - [11-13]: 3 unused bits.
735	* @remarks Warning! All accesses to the bits are hardcoded.
736	*
737	* @todo Change this to a union with both bitfields, u8 and u accessors.
738	* That'll help deal with some of the hardcoded accesses.
739	*
740	* @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
741	* will make it possible to turn some of the 16-bit accesses into
742	* 32-bit ones, which may be efficient (stalls).
743	*/
744	RTUINT16U u16MiscY;
745	/** The page state.
746	* Only 3 bits are really needed for this. */
747	uint16_t uStateY : 3;
748	/** The page type (PGMPAGETYPE).
749	* Only 3 bits are really needed for this. */
750	uint16_t uTypeY : 3;
751	/** PTE index for usage tracking (page pool). */
752	uint16_t uPteIdx : 10;
753	/** Usage tracking (page pool). */
754	uint16_t u16TrackingY;
755	/** The number of read locks on this page. */
756	uint8_t cReadLocksY;
757	/** The number of write locks on this page. */
758	uint8_t cWriteLocksY;
759	} PGMPAGE;
760	AssertCompileSize(PGMPAGE, 16);
761	/** Pointer to a physical guest page. */
762	typedef PGMPAGE *PPGMPAGE;
763	/** Pointer to a const physical guest page. */
764	typedef const PGMPAGE *PCPGMPAGE;
765	/** Pointer to a physical guest page pointer. */
766	typedef PPGMPAGE *PPPGMPAGE;
767
768
769	/**
770	* Clears the page structure.
771	* @param pPage Pointer to the physical guest page tracking structure.
772	*/
773	#define PGM_PAGE_CLEAR(pPage) \
774	do { \
775	(pPage)->HCPhysAndPageID = 0; \
776	(pPage)->uStateY = 0; \
777	(pPage)->uTypeY = 0; \
778	(pPage)->uPteIdx = 0; \
779	(pPage)->u16MiscY.u = 0; \
780	(pPage)->u16TrackingY = 0; \
781	(pPage)->cReadLocksY = 0; \
782	(pPage)->cWriteLocksY = 0; \
783	} while (0)
784
785	/**
786	* Initializes the page structure.
787	* @param pPage Pointer to the physical guest page tracking structure.
788	*/
789	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
790	do { \
791	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
792	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
793	(pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) \| ((_idPage) & UINT32_C(0x0fffffff)); \
794	(pPage)->uStateY = (_uState); \
795	(pPage)->uTypeY = (_uType); \
796	(pPage)->uPteIdx = 0; \
797	(pPage)->u16MiscY.u = 0; \
798	(pPage)->u16TrackingY = 0; \
799	(pPage)->cReadLocksY = 0; \
800	(pPage)->cWriteLocksY = 0; \
801	} while (0)
802
803	/**
804	* Initializes the page structure of a ZERO page.
805	* @param pPage Pointer to the physical guest page tracking structure.
806	* @param pVM The VM handle (for getting the zero page address).
807	* @param uType The page type (PGMPAGETYPE).
808	*/
809	#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
810	PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
811
812
813	/** @name The Page state, PGMPAGE::uStateY.
814	* @{ */
815	/** The zero page.
816	* This is a per-VM page that's never ever mapped writable. */
817	#define PGM_PAGE_STATE_ZERO 0
818	/** A allocated page.
819	* This is a per-VM page allocated from the page pool (or wherever
820	* we get MMIO2 pages from if the type is MMIO2).
821	*/
822	#define PGM_PAGE_STATE_ALLOCATED 1
823	/** A allocated page that's being monitored for writes.
824	* The shadow page table mappings are read-only. When a write occurs, the
825	* fWrittenTo member is set, the page remapped as read-write and the state
826	* moved back to allocated. */
827	#define PGM_PAGE_STATE_WRITE_MONITORED 2
828	/** The page is shared, aka. copy-on-write.
829	* This is a page that's shared with other VMs. */
830	#define PGM_PAGE_STATE_SHARED 3
831	/** The page is ballooned, so no longer available for this VM. */
832	#define PGM_PAGE_STATE_BALLOONED 4
833	/** @} */
834
835
836	/**
837	* Gets the page state.
838	* @returns page state (PGM_PAGE_STATE_*).
839	* @param pPage Pointer to the physical guest page tracking structure.
840	*/
841	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
842
843	/**
844	* Sets the page state.
845	* @param pPage Pointer to the physical guest page tracking structure.
846	* @param _uState The new page state.
847	*/
848	#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
849
850
851	/**
852	* Gets the host physical address of the guest page.
853	* @returns host physical address (RTHCPHYS).
854	* @param pPage Pointer to the physical guest page tracking structure.
855	*/
856	#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
857
858	/**
859	* Sets the host physical address of the guest page.
860	* @param pPage Pointer to the physical guest page tracking structure.
861	* @param _HCPhys The new host physical address.
862	*/
863	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
864	do { \
865	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
866	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
867	(pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
868	\| (SetHCPhysTmp << (28-12)); \
869	} while (0)
870
871	/**
872	* Get the Page ID.
873	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
874	* @param pPage Pointer to the physical guest page tracking structure.
875	*/
876	#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
877
878	/**
879	* Sets the Page ID.
880	* @param pPage Pointer to the physical guest page tracking structure.
881	*/
882	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
883	do { \
884	(pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
885	\| ((_idPage) & UINT32_C(0x0fffffff)); \
886	} while (0)
887
888	/**
889	* Get the Chunk ID.
890	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
891	* @param pPage Pointer to the physical guest page tracking structure.
892	*/
893	#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
894
895	/**
896	* Get the index of the page within the allocation chunk.
897	* @returns The page index.
898	* @param pPage Pointer to the physical guest page tracking structure.
899	*/
900	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
901
902	/**
903	* Gets the page type.
904	* @returns The page type.
905	* @param pPage Pointer to the physical guest page tracking structure.
906	*/
907	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
908
909	/**
910	* Sets the page type.
911	* @param pPage Pointer to the physical guest page tracking structure.
912	* @param _enmType The new page type (PGMPAGETYPE).
913	*/
914	#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
915
916	/**
917	* Gets the page table index
918	* @returns The page table index.
919	* @param pPage Pointer to the physical guest page tracking structure.
920	*/
921	#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
922
923	/**
924	* Sets the page table index
925	* @param pPage Pointer to the physical guest page tracking structure.
926	* @param iPte New page table index.
927	*/
928	#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
929
930	/**
931	* Checks if the page is marked for MMIO.
932	* @returns true/false.
933	* @param pPage Pointer to the physical guest page tracking structure.
934	*/
935	#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
936
937	/**
938	* Checks if the page is backed by the ZERO page.
939	* @returns true/false.
940	* @param pPage Pointer to the physical guest page tracking structure.
941	*/
942	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
943
944	/**
945	* Checks if the page is backed by a SHARED page.
946	* @returns true/false.
947	* @param pPage Pointer to the physical guest page tracking structure.
948	*/
949	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
950
951	/**
952	* Checks if the page is ballooned.
953	* @returns true/false.
954	* @param pPage Pointer to the physical guest page tracking structure.
955	*/
956	#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
957
958	/**
959	* Marks the page as written to (for GMM change monitoring).
960	* @param pPage Pointer to the physical guest page tracking structure.
961	*/
962	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] \|= UINT8_C(0x80); } while (0)
963
964	/**
965	* Clears the written-to indicator.
966	* @param pPage Pointer to the physical guest page tracking structure.
967	*/
968	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
969
970	/**
971	* Checks if the page was marked as written-to.
972	* @returns true/false.
973	* @param pPage Pointer to the physical guest page tracking structure.
974	*/
975	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
976
977	/**
978	* Marks the page as dirty for FTM
979	* @param pPage Pointer to the physical guest page tracking structure.
980	*/
981	#define PGM_PAGE_SET_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] \|= UINT8_C(0x04); } while (0)
982
983	/**
984	* Clears the FTM dirty indicator
985	* @param pPage Pointer to the physical guest page tracking structure.
986	*/
987	#define PGM_PAGE_CLEAR_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0xfb); } while (0)
988
989	/**
990	* Checks if the page was marked as dirty for FTM
991	* @returns true/false.
992	* @param pPage Pointer to the physical guest page tracking structure.
993	*/
994	#define PGM_PAGE_IS_FT_DIRTY(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x04)) )
995
996
997	/** @name PT usage values (PGMPAGE::u2PDEType).
998	*
999	* @{ */
1000	/** Either as a PT or PDE. */
1001	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1002	/** Must use a page table to map the range. */
1003	#define PGM_PAGE_PDE_TYPE_PT 1
1004	/** Can use a page directory entry to map the continous range. */
1005	#define PGM_PAGE_PDE_TYPE_PDE 2
1006	/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
1007	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1008	/** @} */
1009
1010	/**
1011	* Set the PDE type of the page
1012	* @param pPage Pointer to the physical guest page tracking structure.
1013	* @param uType PGM_PAGE_PDE_TYPE_*
1014	*/
1015	#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
1016	do { \
1017	(pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
1018	\| (((uType) & UINT8_C(0x03)) << 5); \
1019	} while (0)
1020
1021	/**
1022	* Checks if the page was marked being part of a large page
1023	* @returns true/false.
1024	* @param pPage Pointer to the physical guest page tracking structure.
1025	*/
1026	#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
1027
1028	/** Enabled optimized access handler tests.
1029	* These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
1030	* layout. When enabled, the compiler should normally generate more compact
1031	* code.
1032	*/
1033	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1034
1035	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1036	*
1037	* @remarks The values are assigned in order of priority, so we can calculate
1038	* the correct state for a page with different handlers installed.
1039	* @{ */
1040	/** No handler installed. */
1041	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1042	/** Monitoring is temporarily disabled. */
1043	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1044	/** Write access is monitored. */
1045	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1046	/** All access is monitored. */
1047	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1048	/** @} */
1049
1050	/**
1051	* Gets the physical access handler state of a page.
1052	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1053	* @param pPage Pointer to the physical guest page tracking structure.
1054	*/
1055	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
1056	( (pPage)->u16MiscY.au8[0] )
1057
1058	/**
1059	* Sets the physical access handler state of a page.
1060	* @param pPage Pointer to the physical guest page tracking structure.
1061	* @param _uState The new state value.
1062	*/
1063	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
1064	do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
1065
1066	/**
1067	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
1068	* @returns true/false
1069	* @param pPage Pointer to the physical guest page tracking structure.
1070	*/
1071	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
1072	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1073
1074	/**
1075	* Checks if the page has any active physical access handlers.
1076	* @returns true/false
1077	* @param pPage Pointer to the physical guest page tracking structure.
1078	*/
1079	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
1080	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1081
1082
1083	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1084	*
1085	* @remarks The values are assigned in order of priority, so we can calculate
1086	* the correct state for a page with different handlers installed.
1087	* @{ */
1088	/** No handler installed. */
1089	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1090	/* 1 is reserved so the lineup is identical with the physical ones. */
1091	/** Write access is monitored. */
1092	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1093	/** All access is monitored. */
1094	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1095	/** @} */
1096
1097	/**
1098	* Gets the virtual access handler state of a page.
1099	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1100	* @param pPage Pointer to the physical guest page tracking structure.
1101	*/
1102	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
1103
1104	/**
1105	* Sets the virtual access handler state of a page.
1106	* @param pPage Pointer to the physical guest page tracking structure.
1107	* @param _uState The new state value.
1108	*/
1109	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1110	do { \
1111	(pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1112	\| ((_uState) & UINT8_C(0x03)); \
1113	} while (0)
1114
1115	/**
1116	* Checks if the page has any virtual access handlers.
1117	* @returns true/false
1118	* @param pPage Pointer to the physical guest page tracking structure.
1119	*/
1120	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1121	( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1122
1123	/**
1124	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1125	* virtual handlers.
1126	* @returns true/false
1127	* @param pPage Pointer to the physical guest page tracking structure.
1128	*/
1129	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1130	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1131
1132
1133	/**
1134	* Checks if the page has any access handlers, including temporarily disabled ones.
1135	* @returns true/false
1136	* @param pPage Pointer to the physical guest page tracking structure.
1137	*/
1138	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1139	# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1140	( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1141	#else
1142	# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1143	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1144	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1145	#endif
1146
1147	/**
1148	* Checks if the page has any active access handlers.
1149	* @returns true/false
1150	* @param pPage Pointer to the physical guest page tracking structure.
1151	*/
1152	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1153	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1154	( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1155	#else
1156	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1157	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1158	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1159	#endif
1160
1161	/**
1162	* Checks if the page has any active access handlers catching all accesses.
1163	* @returns true/false
1164	* @param pPage Pointer to the physical guest page tracking structure.
1165	*/
1166	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1167	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1168	( ( ((pPage)->u16MiscY.au8[0] \| (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1169	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
1170	#else
1171	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1172	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1173	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1174	#endif
1175
1176
1177	/** @def PGM_PAGE_GET_TRACKING
1178	* Gets the packed shadow page pool tracking data associated with a guest page.
1179	* @returns uint16_t containing the data.
1180	* @param pPage Pointer to the physical guest page tracking structure.
1181	*/
1182	#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1183
1184	/** @def PGM_PAGE_SET_TRACKING
1185	* Sets the packed shadow page pool tracking data associated with a guest page.
1186	* @param pPage Pointer to the physical guest page tracking structure.
1187	* @param u16TrackingData The tracking data to store.
1188	*/
1189	#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1190	do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1191
1192	/** @def PGM_PAGE_GET_TD_CREFS
1193	* Gets the @a cRefs tracking data member.
1194	* @returns cRefs.
1195	* @param pPage Pointer to the physical guest page tracking structure.
1196	*/
1197	#define PGM_PAGE_GET_TD_CREFS(pPage) \
1198	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1199
1200	/** @def PGM_PAGE_GET_TD_IDX
1201	* Gets the @a idx tracking data member.
1202	* @returns idx.
1203	* @param pPage Pointer to the physical guest page tracking structure.
1204	*/
1205	#define PGM_PAGE_GET_TD_IDX(pPage) \
1206	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1207
1208
1209	/** Max number of locks on a page. */
1210	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1211
1212	/** Get the read lock count.
1213	* @returns count.
1214	* @param pPage Pointer to the physical guest page tracking structure.
1215	*/
1216	#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1217
1218	/** Get the write lock count.
1219	* @returns count.
1220	* @param pPage Pointer to the physical guest page tracking structure.
1221	*/
1222	#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1223
1224	/** Decrement the read lock counter.
1225	* @param pPage Pointer to the physical guest page tracking structure.
1226	*/
1227	#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1228
1229	/** Decrement the write lock counter.
1230	* @param pPage Pointer to the physical guest page tracking structure.
1231	*/
1232	#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1233
1234	/** Increment the read lock counter.
1235	* @param pPage Pointer to the physical guest page tracking structure.
1236	*/
1237	#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1238
1239	/** Increment the write lock counter.
1240	* @param pPage Pointer to the physical guest page tracking structure.
1241	*/
1242	#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1243
1244
1245	#if 0
1246	/** Enables sanity checking of write monitoring using CRC-32. */
1247	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1248	#endif
1249
1250	/**
1251	* Per page live save tracking data.
1252	*/
1253	typedef struct PGMLIVESAVERAMPAGE
1254	{
1255	/** Number of times it has been dirtied. */
1256	uint32_t cDirtied : 24;
1257	/** Whether it is currently dirty. */
1258	uint32_t fDirty : 1;
1259	/** Ignore the page.
1260	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1261	* deal with these after pausing the VM and DevPCI have said it bit about
1262	* remappings. */
1263	uint32_t fIgnore : 1;
1264	/** Was a ZERO page last time around. */
1265	uint32_t fZero : 1;
1266	/** Was a SHARED page last time around. */
1267	uint32_t fShared : 1;
1268	/** Whether the page is/was write monitored in a previous pass. */
1269	uint32_t fWriteMonitored : 1;
1270	/** Whether the page is/was write monitored earlier in this pass. */
1271	uint32_t fWriteMonitoredJustNow : 1;
1272	/** Bits reserved for future use. */
1273	uint32_t u2Reserved : 2;
1274	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1275	/** CRC-32 for the page. This is for internal consistency checks. */
1276	uint32_t u32Crc;
1277	#endif
1278	} PGMLIVESAVERAMPAGE;
1279	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1280	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1281	#else
1282	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1283	#endif
1284	/** Pointer to the per page live save tracking data. */
1285	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1286
1287	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1288	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1289
1290
1291	/**
1292	* Ram range for GC Phys to HC Phys conversion.
1293	*
1294	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1295	* conversions too, but we'll let MM handle that for now.
1296	*
1297	* This structure is used by linked lists in both GC and HC.
1298	*/
1299	typedef struct PGMRAMRANGE
1300	{
1301	/** Start of the range. Page aligned. */
1302	RTGCPHYS GCPhys;
1303	/** Size of the range. (Page aligned of course). */
1304	RTGCPHYS cb;
1305	/** Pointer to the next RAM range - for R3. */
1306	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1307	/** Pointer to the next RAM range - for R0. */
1308	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1309	/** Pointer to the next RAM range - for RC. */
1310	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1311	/** PGM_RAM_RANGE_FLAGS_* flags. */
1312	uint32_t fFlags;
1313	/** Last address in the range (inclusive). Page aligned (-1). */
1314	RTGCPHYS GCPhysLast;
1315	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1316	R3PTRTYPE(void *) pvR3;
1317	/** Live save per page tracking data. */
1318	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1319	/** The range description. */
1320	R3PTRTYPE(const char *) pszDesc;
1321	/** Pointer to self - R0 pointer. */
1322	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1323	/** Pointer to self - RC pointer. */
1324	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1325	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1326	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1327	/** Array of physical guest page tracking structures. */
1328	PGMPAGE aPages[1];
1329	} PGMRAMRANGE;
1330	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1331	typedef PGMRAMRANGE *PPGMRAMRANGE;
1332
1333	/** @name PGMRAMRANGE::fFlags
1334	* @{ */
1335	/** The RAM range is floating around as an independent guest mapping. */
1336	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1337	/** Ad hoc RAM range for an ROM mapping. */
1338	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1339	/** Ad hoc RAM range for an MMIO mapping. */
1340	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1341	/** Ad hoc RAM range for an MMIO2 mapping. */
1342	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1343	/** @} */
1344
1345	/** Tests if a RAM range is an ad hoc one or not.
1346	* @returns true/false.
1347	* @param pRam The RAM range.
1348	*/
1349	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1350	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1351
1352
1353	/**
1354	* Per page tracking structure for ROM image.
1355	*
1356	* A ROM image may have a shadow page, in which case we may have two pages
1357	* backing it. This structure contains the PGMPAGE for both while
1358	* PGMRAMRANGE have a copy of the active one. It is important that these
1359	* aren't out of sync in any regard other than page pool tracking data.
1360	*/
1361	typedef struct PGMROMPAGE
1362	{
1363	/** The page structure for the virgin ROM page. */
1364	PGMPAGE Virgin;
1365	/** The page structure for the shadow RAM page. */
1366	PGMPAGE Shadow;
1367	/** The current protection setting. */
1368	PGMROMPROT enmProt;
1369	/** Live save status information. Makes use of unused alignment space. */
1370	struct
1371	{
1372	/** The previous protection value. */
1373	uint8_t u8Prot;
1374	/** Written to flag set by the handler. */
1375	bool fWrittenTo;
1376	/** Whether the shadow page is dirty or not. */
1377	bool fDirty;
1378	/** Whether it was dirtied in the recently. */
1379	bool fDirtiedRecently;
1380	} LiveSave;
1381	} PGMROMPAGE;
1382	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1383	/** Pointer to a ROM page tracking structure. */
1384	typedef PGMROMPAGE *PPGMROMPAGE;
1385
1386
1387	/**
1388	* A registered ROM image.
1389	*
1390	* This is needed to keep track of ROM image since they generally intrude
1391	* into a PGMRAMRANGE. It also keeps track of additional info like the
1392	* two page sets (read-only virgin and read-write shadow), the current
1393	* state of each page.
1394	*
1395	* Because access handlers cannot easily be executed in a different
1396	* context, the ROM ranges needs to be accessible and in all contexts.
1397	*/
1398	typedef struct PGMROMRANGE
1399	{
1400	/** Pointer to the next range - R3. */
1401	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1402	/** Pointer to the next range - R0. */
1403	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1404	/** Pointer to the next range - RC. */
1405	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1406	/** Pointer alignment */
1407	RTRCPTR RCPtrAlignment;
1408	/** Address of the range. */
1409	RTGCPHYS GCPhys;
1410	/** Address of the last byte in the range. */
1411	RTGCPHYS GCPhysLast;
1412	/** Size of the range. */
1413	RTGCPHYS cb;
1414	/** The flags (PGMPHYS_ROM_FLAGS_). /
1415	uint32_t fFlags;
1416	/** The saved state range ID. */
1417	uint8_t idSavedState;
1418	/** Alignment padding. */
1419	uint8_t au8Alignment[3];
1420	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1421	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1422	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1423	* This is used for strictness checks. */
1424	R3PTRTYPE(const void *) pvOriginal;
1425	/** The ROM description. */
1426	R3PTRTYPE(const char *) pszDesc;
1427	/** The per page tracking structures. */
1428	PGMROMPAGE aPages[1];
1429	} PGMROMRANGE;
1430	/** Pointer to a ROM range. */
1431	typedef PGMROMRANGE *PPGMROMRANGE;
1432
1433
1434	/**
1435	* Live save per page data for an MMIO2 page.
1436	*
1437	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1438	* of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1439	* CRC-32 for detecting changes as well as special handling of zero pages. This
1440	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1441	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1442	* because of speed (2.5x and 6x slower).)
1443	*
1444	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1445	* save but normally is disabled. Since we can write monitore guest
1446	* accesses on our own, we only need this for host accesses. Shouldn't be
1447	* too difficult for DevVGA, VMMDev might be doable, the planned
1448	* networking fun will be fun since it involves ring-0.
1449	*/
1450	typedef struct PGMLIVESAVEMMIO2PAGE
1451	{
1452	/** Set if the page is considered dirty. */
1453	bool fDirty;
1454	/** The number of scans this page has remained unchanged for.
1455	* Only updated for dirty pages. */
1456	uint8_t cUnchangedScans;
1457	/** Whether this page was zero at the last scan. */
1458	bool fZero;
1459	/** Alignment padding. */
1460	bool fReserved;
1461	/** CRC-32 for the first half of the page.
1462	* This is used together with u32CrcH2 to quickly detect changes in the page
1463	* during the non-final passes. */
1464	uint32_t u32CrcH1;
1465	/** CRC-32 for the second half of the page. */
1466	uint32_t u32CrcH2;
1467	/** SHA-1 for the saved page.
1468	* This is used in the final pass to skip pages without changes. */
1469	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1470	} PGMLIVESAVEMMIO2PAGE;
1471	/** Pointer to a live save status data for an MMIO2 page. */
1472	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1473
1474	/**
1475	* A registered MMIO2 (= Device RAM) range.
1476	*
1477	* There are a few reason why we need to keep track of these
1478	* registrations. One of them is the deregistration & cleanup stuff,
1479	* while another is that the PGMRAMRANGE associated with such a region may
1480	* have to be removed from the ram range list.
1481	*
1482	* Overlapping with a RAM range has to be 100% or none at all. The pages
1483	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1484	* will be raised if a partial overlap or an overlap of ROM pages is
1485	* encountered. On an overlap we will free all the existing RAM pages and
1486	* put in the ram range pages instead.
1487	*/
1488	typedef struct PGMMMIO2RANGE
1489	{
1490	/** The owner of the range. (a device) */
1491	PPDMDEVINSR3 pDevInsR3;
1492	/** Pointer to the ring-3 mapping of the allocation. */
1493	RTR3PTR pvR3;
1494	/** Pointer to the next range - R3. */
1495	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1496	/** Whether it's mapped or not. */
1497	bool fMapped;
1498	/** Whether it's overlapping or not. */
1499	bool fOverlapping;
1500	/** The PCI region number.
1501	* @remarks This ASSUMES that nobody will ever really need to have multiple
1502	* PCI devices with matching MMIO region numbers on a single device. */
1503	uint8_t iRegion;
1504	/** The saved state range ID. */
1505	uint8_t idSavedState;
1506	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1507	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1508	/** Live save per page tracking data. */
1509	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1510	/** The associated RAM range. */
1511	PGMRAMRANGE RamRange;
1512	} PGMMMIO2RANGE;
1513	/** Pointer to a MMIO2 range. */
1514	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1515
1516
1517
1518
1519	/**
1520	* PGMPhysRead/Write cache entry
1521	*/
1522	typedef struct PGMPHYSCACHEENTRY
1523	{
1524	/** R3 pointer to physical page. */
1525	R3PTRTYPE(uint8_t *) pbR3;
1526	/** GC Physical address for cache entry */
1527	RTGCPHYS GCPhys;
1528	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1529	RTGCPHYS u32Padding0; /*< alignment padding. /
1530	#endif
1531	} PGMPHYSCACHEENTRY;
1532
1533	/**
1534	* PGMPhysRead/Write cache to reduce REM memory access overhead
1535	*/
1536	typedef struct PGMPHYSCACHE
1537	{
1538	/** Bitmap of valid cache entries */
1539	uint64_t aEntries;
1540	/** Cache entries */
1541	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1542	} PGMPHYSCACHE;
1543
1544
1545	/** Pointer to an allocation chunk ring-3 mapping. */
1546	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1547	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1548	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1549
1550	/**
1551	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1552	*
1553	* The primary tree (Core) uses the chunk id as key.
1554	*/
1555	typedef struct PGMCHUNKR3MAP
1556	{
1557	/** The key is the chunk id. */
1558	AVLU32NODECORE Core;
1559	/** The current age thingy. */
1560	uint32_t iAge;
1561	/** The current reference count. */
1562	uint32_t volatile cRefs;
1563	/** The current permanent reference count. */
1564	uint32_t volatile cPermRefs;
1565	/** The mapping address. */
1566	void *pv;
1567	} PGMCHUNKR3MAP;
1568
1569	/**
1570	* Allocation chunk ring-3 mapping TLB entry.
1571	*/
1572	typedef struct PGMCHUNKR3MAPTLBE
1573	{
1574	/** The chunk id. */
1575	uint32_t volatile idChunk;
1576	#if HC_ARCH_BITS == 64
1577	uint32_t u32Padding; /*< alignment padding. /
1578	#endif
1579	/** The chunk map. */
1580	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1581	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1582	#else
1583	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1584	#endif
1585	} PGMCHUNKR3MAPTLBE;
1586	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1587	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1588
1589	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1590	* @remark Must be a power of two value. */
1591	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1592
1593	/**
1594	* Allocation chunk ring-3 mapping TLB.
1595	*
1596	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1597	* At first glance this might look kinda odd since AVL trees are
1598	* supposed to give the most optimial lookup times of all trees
1599	* due to their balancing. However, take a tree with 1023 nodes
1600	* in it, that's 10 levels, meaning that most searches has to go
1601	* down 9 levels before they find what they want. This isn't fast
1602	* compared to a TLB hit. There is the factor of cache misses,
1603	* and of course the problem with trees and branch prediction.
1604	* This is why we use TLBs in front of most of the trees.
1605	*
1606	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1607	* difficult when we switch to the new inlined AVL trees (from kStuff).
1608	*/
1609	typedef struct PGMCHUNKR3MAPTLB
1610	{
1611	/** The TLB entries. */
1612	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1613	} PGMCHUNKR3MAPTLB;
1614
1615	/**
1616	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1617	* @returns Chunk TLB index.
1618	* @param idChunk The Chunk ID.
1619	*/
1620	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1621
1622
1623	/**
1624	* Ring-3 guest page mapping TLB entry.
1625	* @remarks used in ring-0 as well at the moment.
1626	*/
1627	typedef struct PGMPAGER3MAPTLBE
1628	{
1629	/** Address of the page. */
1630	RTGCPHYS volatile GCPhys;
1631	/** The guest page. */
1632	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1633	R3PTRTYPE(PPGMPAGE) volatile pPage;
1634	#else
1635	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1636	#endif
1637	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1638	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1639	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1640	#else
1641	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1642	#endif
1643	/** The address */
1644	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1645	R3PTRTYPE(void *) volatile pv;
1646	#else
1647	R3R0PTRTYPE(void *) volatile pv;
1648	#endif
1649	#if HC_ARCH_BITS == 32
1650	uint32_t u32Padding; /*< alignment padding. /
1651	#endif
1652	} PGMPAGER3MAPTLBE;
1653	/** Pointer to an entry in the HC physical TLB. */
1654	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1655
1656
1657	/** The number of entries in the ring-3 guest page mapping TLB.
1658	* @remarks The value must be a power of two. */
1659	#define PGM_PAGER3MAPTLB_ENTRIES 256
1660
1661	/**
1662	* Ring-3 guest page mapping TLB.
1663	* @remarks used in ring-0 as well at the moment.
1664	*/
1665	typedef struct PGMPAGER3MAPTLB
1666	{
1667	/** The TLB entries. */
1668	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1669	} PGMPAGER3MAPTLB;
1670	/** Pointer to the ring-3 guest page mapping TLB. */
1671	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1672
1673	/**
1674	* Calculates the index of the TLB entry for the specified guest page.
1675	* @returns Physical TLB index.
1676	* @param GCPhys The guest physical address.
1677	*/
1678	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1679
1680
1681	/**
1682	* Raw-mode context dynamic mapping cache entry.
1683	*
1684	* Because of raw-mode context being reloctable and all relocations are applied
1685	* in ring-3, this has to be defined here and be RC specfic.
1686	*
1687	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1688	*/
1689	typedef struct PGMRCDYNMAPENTRY
1690	{
1691	/** The physical address of the currently mapped page.
1692	* This is duplicate for three reasons: cache locality, cache policy of the PT
1693	* mappings and sanity checks. */
1694	RTHCPHYS HCPhys;
1695	/** Pointer to the page. */
1696	RTRCPTR pvPage;
1697	/** The number of references. */
1698	int32_t volatile cRefs;
1699	/** PTE pointer union. */
1700	union PGMRCDYNMAPENTRY_PPTE
1701	{
1702	/** PTE pointer, 32-bit legacy version. */
1703	RCPTRTYPE(PX86PTE) pLegacy;
1704	/** PTE pointer, PAE version. */
1705	RCPTRTYPE(PX86PTEPAE) pPae;
1706	/** PTE pointer, the void version. */
1707	RTRCPTR pv;
1708	} uPte;
1709	/** Alignment padding. */
1710	RTRCPTR RCPtrAlignment;
1711	} PGMRCDYNMAPENTRY;
1712	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1713	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1714
1715
1716	/**
1717	* Dynamic mapping cache for the raw-mode context.
1718	*
1719	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1720	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1721	* so that we can perform relocations from PGMR3Relocate. This has the
1722	* consequence that we must have separate ring-0 and raw-mode context versions
1723	* of this struct even if they share the basic elements.
1724	*
1725	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1726	*/
1727	typedef struct PGMRCDYNMAP
1728	{
1729	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1730	uint32_t u32Magic;
1731	/** Array for tracking and managing the pages. */
1732	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1733	/** The cache size given as a number of pages. */
1734	uint32_t cPages;
1735	/** Whether it's 32-bit legacy or PAE/AMD64 paging mode. */
1736	bool fLegacyMode;
1737	/** The current load.
1738	* This does not include guard pages. */
1739	uint32_t cLoad;
1740	/** The max load ever.
1741	* This is maintained to get trigger adding of more mapping space. */
1742	uint32_t cMaxLoad;
1743	/** The number of guard pages. */
1744	uint32_t cGuardPages;
1745	/** The number of users (protected by hInitLock). */
1746	uint32_t cUsers;
1747	} PGMRCDYNMAP;
1748	/** Pointer to the dynamic cache for the raw-mode context. */
1749	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1750
1751
1752	/**
1753	* Mapping cache usage set entry.
1754	*
1755	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1756	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1757	* cache. If it's extended to include ring-3, well, then something
1758	* will have be changed here...
1759	*/
1760	typedef struct PGMMAPSETENTRY
1761	{
1762	/** Pointer to the page. */
1763	#ifndef IN_RC
1764	RTR0PTR pvPage;
1765	#else
1766	RTRCPTR pvPage;
1767	# if HC_ARCH_BITS == 64
1768	uint32_t u32Alignment2;
1769	# endif
1770	#endif
1771	/** The mapping cache index. */
1772	uint16_t iPage;
1773	/** The number of references.
1774	* The max is UINT16_MAX - 1. */
1775	uint16_t cRefs;
1776	/** The number inlined references.
1777	* The max is UINT16_MAX - 1. */
1778	uint16_t cInlinedRefs;
1779	/** Unreferences. */
1780	uint16_t cUnrefs;
1781
1782	#if HC_ARCH_BITS == 32
1783	uint32_t u32Alignment1;
1784	#endif
1785	/** The physical address for this entry. */
1786	RTHCPHYS HCPhys;
1787	} PGMMAPSETENTRY;
1788	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1789	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1790	/** Pointer to a mapping cache usage set entry. */
1791	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1792
1793	/**
1794	* Mapping cache usage set.
1795	*
1796	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1797	* done during exits / traps. The set is
1798	*/
1799	typedef struct PGMMAPSET
1800	{
1801	/** The number of occupied entries.
1802	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1803	* dynamic mappings. */
1804	uint32_t cEntries;
1805	/** The start of the current subset.
1806	* This is UINT32_MAX if no subset is currently open. */
1807	uint32_t iSubset;
1808	/** The index of the current CPU, only valid if the set is open. */
1809	int32_t iCpu;
1810	uint32_t alignment;
1811	/** The entries. */
1812	PGMMAPSETENTRY aEntries[64];
1813	/** HCPhys -> iEntry fast lookup table.
1814	* Use PGMMAPSET_HASH for hashing.
1815	* The entries may or may not be valid, check against cEntries. */
1816	uint8_t aiHashTable[128];
1817	} PGMMAPSET;
1818	AssertCompileSizeAlignment(PGMMAPSET, 8);
1819	/** Pointer to the mapping cache set. */
1820	typedef PGMMAPSET *PPGMMAPSET;
1821
1822	/** PGMMAPSET::cEntries value for a closed set. */
1823	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1824
1825	/** Hash function for aiHashTable. */
1826	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1827
1828
1829	/** @name Context neutrual page mapper TLB.
1830	*
1831	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1832	* code is writting in a kind of context neutrual way. Time will show whether
1833	* this actually makes sense or not...
1834	*
1835	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1836	* context ends up using a global mapping cache on some platforms
1837	* (darwin).
1838	*
1839	* @{ */
1840	/** @typedef PPGMPAGEMAPTLB
1841	* The page mapper TLB pointer type for the current context. */
1842	/** @typedef PPGMPAGEMAPTLB
1843	* The page mapper TLB entry pointer type for the current context. */
1844	/** @typedef PPGMPAGEMAPTLB
1845	* The page mapper TLB entry pointer pointer type for the current context. */
1846	/** @def PGM_PAGEMAPTLB_ENTRIES
1847	* The number of TLB entries in the page mapper TLB for the current context. */
1848	/** @def PGM_PAGEMAPTLB_IDX
1849	* Calculate the TLB index for a guest physical address.
1850	* @returns The TLB index.
1851	* @param GCPhys The guest physical address. */
1852	/** @typedef PPGMPAGEMAP
1853	* Pointer to a page mapper unit for current context. */
1854	/** @typedef PPPGMPAGEMAP
1855	* Pointer to a page mapper unit pointer for current context. */
1856	#ifdef IN_RC
1857	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1858	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1859	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1860	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1861	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1862	typedef void * PPGMPAGEMAP;
1863	typedef void ** PPPGMPAGEMAP;
1864	//#elif IN_RING0
1865	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1866	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1867	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1868	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1869	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1870	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1871	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1872	#else
1873	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1874	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1875	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1876	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1877	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1878	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1879	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1880	#endif
1881	/** @} */
1882
1883
1884	/** @name PGM Pool Indexes.
1885	* Aka. the unique shadow page identifier.
1886	* @{ */
1887	/** NIL page pool IDX. */
1888	#define NIL_PGMPOOL_IDX 0
1889	/** The first normal index. */
1890	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1891	/** Page directory (32-bit root). */
1892	#define PGMPOOL_IDX_PD 1
1893	/** Page Directory Pointer Table (PAE root). */
1894	#define PGMPOOL_IDX_PDPT 2
1895	/** AMD64 CR3 level index.*/
1896	#define PGMPOOL_IDX_AMD64_CR3 3
1897	/** Nested paging root.*/
1898	#define PGMPOOL_IDX_NESTED_ROOT 4
1899	/** The first normal index. */
1900	#define PGMPOOL_IDX_FIRST 5
1901	/** The last valid index. (inclusive, 14 bits) */
1902	#define PGMPOOL_IDX_LAST 0x3fff
1903	/** @} */
1904
1905	/** The NIL index for the parent chain. */
1906	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1907	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1908
1909	/**
1910	* Node in the chain linking a shadowed page to it's parent (user).
1911	*/
1912	#pragma pack(1)
1913	typedef struct PGMPOOLUSER
1914	{
1915	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1916	uint16_t iNext;
1917	/** The user page index. */
1918	uint16_t iUser;
1919	/** Index into the user table. */
1920	uint32_t iUserTable;
1921	} PGMPOOLUSER, *PPGMPOOLUSER;
1922	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1923	#pragma pack()
1924
1925
1926	/** The NIL index for the phys ext chain. */
1927	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1928	/** The NIL pte index for a phys ext chain slot. */
1929	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1930
1931	/**
1932	* Node in the chain of physical cross reference extents.
1933	* @todo Calling this an 'extent' is not quite right, find a better name.
1934	* @todo find out the optimal size of the aidx array
1935	*/
1936	#pragma pack(1)
1937	typedef struct PGMPOOLPHYSEXT
1938	{
1939	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1940	uint16_t iNext;
1941	/** Alignment. */
1942	uint16_t u16Align;
1943	/** The user page index. */
1944	uint16_t aidx[3];
1945	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1946	uint16_t apte[3];
1947	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1948	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1949	#pragma pack()
1950
1951
1952	/**
1953	* The kind of page that's being shadowed.
1954	*/
1955	typedef enum PGMPOOLKIND
1956	{
1957	/** The virtual invalid 0 entry. */
1958	PGMPOOLKIND_INVALID = 0,
1959	/** The entry is free (=unused). */
1960	PGMPOOLKIND_FREE,
1961
1962	/** Shw: 32-bit page table; Gst: no paging */
1963	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1964	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1965	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1966	/** Shw: 32-bit page table; Gst: 4MB page. */
1967	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1968	/** Shw: PAE page table; Gst: no paging */
1969	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1970	/** Shw: PAE page table; Gst: 32-bit page table. */
1971	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1972	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1973	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1974	/** Shw: PAE page table; Gst: PAE page table. */
1975	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1976	/** Shw: PAE page table; Gst: 2MB page. */
1977	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1978
1979	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1980	PGMPOOLKIND_32BIT_PD,
1981	/** Shw: 32-bit page directory. Gst: no paging. */
1982	PGMPOOLKIND_32BIT_PD_PHYS,
1983	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1984	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1985	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1986	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1987	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1988	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1989	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1990	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1991	/** Shw: PAE page directory; Gst: PAE page directory. */
1992	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1993	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1994	PGMPOOLKIND_PAE_PD_PHYS,
1995
1996	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1997	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1998	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1999	PGMPOOLKIND_PAE_PDPT,
2000	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2001	PGMPOOLKIND_PAE_PDPT_PHYS,
2002
2003	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2004	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2005	/** Shw: 64-bit page directory pointer table; Gst: no paging */
2006	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2007	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2008	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2009	/** Shw: 64-bit page directory table; Gst: no paging */
2010	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
2011
2012	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2013	PGMPOOLKIND_64BIT_PML4,
2014
2015	/** Shw: EPT page directory pointer table; Gst: no paging */
2016	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2017	/** Shw: EPT page directory table; Gst: no paging */
2018	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2019	/** Shw: EPT page table; Gst: no paging */
2020	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2021
2022	/** Shw: Root Nested paging table. */
2023	PGMPOOLKIND_ROOT_NESTED,
2024
2025	/** The last valid entry. */
2026	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2027	} PGMPOOLKIND;
2028
2029	/**
2030	* The access attributes of the page; only applies to big pages.
2031	*/
2032	typedef enum
2033	{
2034	PGMPOOLACCESS_DONTCARE = 0,
2035	PGMPOOLACCESS_USER_RW,
2036	PGMPOOLACCESS_USER_R,
2037	PGMPOOLACCESS_USER_RW_NX,
2038	PGMPOOLACCESS_USER_R_NX,
2039	PGMPOOLACCESS_SUPERVISOR_RW,
2040	PGMPOOLACCESS_SUPERVISOR_R,
2041	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2042	PGMPOOLACCESS_SUPERVISOR_R_NX
2043	} PGMPOOLACCESS;
2044
2045	/**
2046	* The tracking data for a page in the pool.
2047	*/
2048	typedef struct PGMPOOLPAGE
2049	{
2050	/** AVL node code with the (R3) physical address of this page. */
2051	AVLOHCPHYSNODECORE Core;
2052	/** Pointer to the R3 mapping of the page. */
2053	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2054	R3PTRTYPE(void *) pvPageR3;
2055	#else
2056	R3R0PTRTYPE(void *) pvPageR3;
2057	#endif
2058	/** The guest physical address. */
2059	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2060	uint32_t Alignment0;
2061	#endif
2062	RTGCPHYS GCPhys;
2063
2064	/** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2065	RTGCPTR pvLastAccessHandlerRip;
2066	RTGCPTR pvLastAccessHandlerFault;
2067	uint64_t cLastAccessHandlerCount;
2068
2069	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2070	uint8_t enmKind;
2071	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2072	uint8_t enmAccess;
2073	/** The index of this page. */
2074	uint16_t idx;
2075	/** The next entry in the list this page currently resides in.
2076	* It's either in the free list or in the GCPhys hash. */
2077	uint16_t iNext;
2078	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2079	uint16_t iUserHead;
2080	/** The number of present entries. */
2081	uint16_t cPresent;
2082	/** The first entry in the table which is present. */
2083	uint16_t iFirstPresent;
2084	/** The number of modifications to the monitored page. */
2085	uint16_t cModifications;
2086	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2087	uint16_t iModifiedNext;
2088	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2089	uint16_t iModifiedPrev;
2090	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2091	uint16_t iMonitoredNext;
2092	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2093	uint16_t iMonitoredPrev;
2094	/** The next page in the age list. */
2095	uint16_t iAgeNext;
2096	/** The previous page in the age list. */
2097	uint16_t iAgePrev;
2098	/** Used to indicate that the page is zeroed. */
2099	bool fZeroed;
2100	/** Used to indicate that a PT has non-global entries. */
2101	bool fSeenNonGlobal;
2102	/** Used to indicate that we're monitoring writes to the guest page. */
2103	bool fMonitored;
2104	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2105	* (All pages are in the age list.) */
2106	bool fCached;
2107	/** This is used by the R3 access handlers when invoked by an async thread.
2108	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2109	bool volatile fReusedFlushPending;
2110	/** Used to mark the page as dirty (write monitoring is temporarily
2111	* off). */
2112	bool fDirty;
2113
2114	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2115	uint32_t cLocked;
2116	uint32_t idxDirty;
2117	RTGCPTR pvDirtyFault;
2118	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
2119	/** Pointer to a const pool page. */
2120	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2121
2122
2123	/** The hash table size. */
2124	# define PGMPOOL_HASH_SIZE 0x40
2125	/** The hash function. */
2126	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2127
2128
2129	/**
2130	* The shadow page pool instance data.
2131	*
2132	* It's all one big allocation made at init time, except for the
2133	* pages that is. The user nodes follows immediatly after the
2134	* page structures.
2135	*/
2136	typedef struct PGMPOOL
2137	{
2138	/** The VM handle - R3 Ptr. */
2139	PVMR3 pVMR3;
2140	/** The VM handle - R0 Ptr. */
2141	PVMR0 pVMR0;
2142	/** The VM handle - RC Ptr. */
2143	PVMRC pVMRC;
2144	/** The max pool size. This includes the special IDs. */
2145	uint16_t cMaxPages;
2146	/** The current pool size. */
2147	uint16_t cCurPages;
2148	/** The head of the free page list. */
2149	uint16_t iFreeHead;
2150	/* Padding. */
2151	uint16_t u16Padding;
2152	/** Head of the chain of free user nodes. */
2153	uint16_t iUserFreeHead;
2154	/** The number of user nodes we've allocated. */
2155	uint16_t cMaxUsers;
2156	/** The number of present page table entries in the entire pool. */
2157	uint32_t cPresent;
2158	/** Pointer to the array of user nodes - RC pointer. */
2159	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2160	/** Pointer to the array of user nodes - R3 pointer. */
2161	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2162	/** Pointer to the array of user nodes - R0 pointer. */
2163	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2164	/** Head of the chain of free phys ext nodes. */
2165	uint16_t iPhysExtFreeHead;
2166	/** The number of user nodes we've allocated. */
2167	uint16_t cMaxPhysExts;
2168	/** Pointer to the array of physical xref extent - RC pointer. */
2169	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2170	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2171	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2172	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2173	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2174	/** Hash table for GCPhys addresses. */
2175	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2176	/** The head of the age list. */
2177	uint16_t iAgeHead;
2178	/** The tail of the age list. */
2179	uint16_t iAgeTail;
2180	/** Set if the cache is enabled. */
2181	bool fCacheEnabled;
2182	/** Alignment padding. */
2183	bool afPadding1[3];
2184	/** Head of the list of modified pages. */
2185	uint16_t iModifiedHead;
2186	/** The current number of modified pages. */
2187	uint16_t cModifiedPages;
2188	/** Access handler, RC. */
2189	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2190	/** Access handler, R0. */
2191	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2192	/** Access handler, R3. */
2193	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2194	/** The access handler description (R3 ptr). */
2195	R3PTRTYPE(const char *) pszAccessHandler;
2196	# if HC_ARCH_BITS == 32
2197	/** Alignment padding. */
2198	uint32_t u32Padding2;
2199	# endif
2200	/* Next available slot. */
2201	uint32_t idxFreeDirtyPage;
2202	/* Number of active dirty pages. */
2203	uint32_t cDirtyPages;
2204	/* Array of current dirty pgm pool page indices. */
2205	uint16_t aIdxDirtyPages[16];
2206	uint64_t aDirtyPages[16][512];
2207	/** The number of pages currently in use. */
2208	uint16_t cUsedPages;
2209	#ifdef VBOX_WITH_STATISTICS
2210	/** The high water mark for cUsedPages. */
2211	uint16_t cUsedPagesHigh;
2212	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
2213	/** Profiling pgmPoolAlloc(). */
2214	STAMPROFILEADV StatAlloc;
2215	/** Profiling pgmR3PoolClearDoIt(). */
2216	STAMPROFILE StatClearAll;
2217	/** Profiling pgmR3PoolReset(). */
2218	STAMPROFILE StatR3Reset;
2219	/** Profiling pgmPoolFlushPage(). */
2220	STAMPROFILE StatFlushPage;
2221	/** Profiling pgmPoolFree(). */
2222	STAMPROFILE StatFree;
2223	/** Counting explicit flushes by PGMPoolFlushPage(). */
2224	STAMCOUNTER StatForceFlushPage;
2225	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2226	STAMCOUNTER StatForceFlushDirtyPage;
2227	/** Counting flushes for reused pages. */
2228	STAMCOUNTER StatForceFlushReused;
2229	/** Profiling time spent zeroing pages. */
2230	STAMPROFILE StatZeroPage;
2231	/** Profiling of pgmPoolTrackDeref. */
2232	STAMPROFILE StatTrackDeref;
2233	/** Profiling pgmTrackFlushGCPhysPT. */
2234	STAMPROFILE StatTrackFlushGCPhysPT;
2235	/** Profiling pgmTrackFlushGCPhysPTs. */
2236	STAMPROFILE StatTrackFlushGCPhysPTs;
2237	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2238	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2239	/** Number of times we've been out of user records. */
2240	STAMCOUNTER StatTrackFreeUpOneUser;
2241	/** Nr of flushed entries. */
2242	STAMCOUNTER StatTrackFlushEntry;
2243	/** Nr of updated entries. */
2244	STAMCOUNTER StatTrackFlushEntryKeep;
2245	/** Profiling deref activity related tracking GC physical pages. */
2246	STAMPROFILE StatTrackDerefGCPhys;
2247	/** Number of linear searches for a HCPhys in the ram ranges. */
2248	STAMCOUNTER StatTrackLinearRamSearches;
2249	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2250	STAMCOUNTER StamTrackPhysExtAllocFailures;
2251	/** Profiling the RC/R0 access handler. */
2252	STAMPROFILE StatMonitorRZ;
2253	/** Times we've failed interpreting the instruction. */
2254	STAMCOUNTER StatMonitorRZEmulateInstr;
2255	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2256	STAMPROFILE StatMonitorRZFlushPage;
2257	/* Times we've detected a page table reinit. */
2258	STAMCOUNTER StatMonitorRZFlushReinit;
2259	/** Counting flushes for pages that are modified too often. */
2260	STAMCOUNTER StatMonitorRZFlushModOverflow;
2261	/** Times we've detected fork(). */
2262	STAMCOUNTER StatMonitorRZFork;
2263	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2264	STAMPROFILE StatMonitorRZHandled;
2265	/** Times we've failed interpreting a patch code instruction. */
2266	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2267	/** Times we've failed interpreting a patch code instruction during flushing. */
2268	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2269	/** The number of times we've seen rep prefixes we can't handle. */
2270	STAMCOUNTER StatMonitorRZRepPrefix;
2271	/** Profiling the REP STOSD cases we've handled. */
2272	STAMPROFILE StatMonitorRZRepStosd;
2273	/** Nr of handled PT faults. */
2274	STAMCOUNTER StatMonitorRZFaultPT;
2275	/** Nr of handled PD faults. */
2276	STAMCOUNTER StatMonitorRZFaultPD;
2277	/** Nr of handled PDPT faults. */
2278	STAMCOUNTER StatMonitorRZFaultPDPT;
2279	/** Nr of handled PML4 faults. */
2280	STAMCOUNTER StatMonitorRZFaultPML4;
2281
2282	/** Profiling the R3 access handler. */
2283	STAMPROFILE StatMonitorR3;
2284	/** Times we've failed interpreting the instruction. */
2285	STAMCOUNTER StatMonitorR3EmulateInstr;
2286	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2287	STAMPROFILE StatMonitorR3FlushPage;
2288	/* Times we've detected a page table reinit. */
2289	STAMCOUNTER StatMonitorR3FlushReinit;
2290	/** Counting flushes for pages that are modified too often. */
2291	STAMCOUNTER StatMonitorR3FlushModOverflow;
2292	/** Times we've detected fork(). */
2293	STAMCOUNTER StatMonitorR3Fork;
2294	/** Profiling the R3 access we've handled (except REP STOSD). */
2295	STAMPROFILE StatMonitorR3Handled;
2296	/** The number of times we've seen rep prefixes we can't handle. */
2297	STAMCOUNTER StatMonitorR3RepPrefix;
2298	/** Profiling the REP STOSD cases we've handled. */
2299	STAMPROFILE StatMonitorR3RepStosd;
2300	/** Nr of handled PT faults. */
2301	STAMCOUNTER StatMonitorR3FaultPT;
2302	/** Nr of handled PD faults. */
2303	STAMCOUNTER StatMonitorR3FaultPD;
2304	/** Nr of handled PDPT faults. */
2305	STAMCOUNTER StatMonitorR3FaultPDPT;
2306	/** Nr of handled PML4 faults. */
2307	STAMCOUNTER StatMonitorR3FaultPML4;
2308	/** The number of times we're called in an async thread an need to flush. */
2309	STAMCOUNTER StatMonitorR3Async;
2310	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2311	STAMCOUNTER StatResetDirtyPages;
2312	/** Times we've called pgmPoolAddDirtyPage. */
2313	STAMCOUNTER StatDirtyPage;
2314	/** Times we've had to flush duplicates for dirty page management. */
2315	STAMCOUNTER StatDirtyPageDupFlush;
2316	/** Times we've had to flush because of overflow. */
2317	STAMCOUNTER StatDirtyPageOverFlowFlush;
2318
2319	/** The high wather mark for cModifiedPages. */
2320	uint16_t cModifiedPagesHigh;
2321	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
2322
2323	/** The number of cache hits. */
2324	STAMCOUNTER StatCacheHits;
2325	/** The number of cache misses. */
2326	STAMCOUNTER StatCacheMisses;
2327	/** The number of times we've got a conflict of 'kind' in the cache. */
2328	STAMCOUNTER StatCacheKindMismatches;
2329	/** Number of times we've been out of pages. */
2330	STAMCOUNTER StatCacheFreeUpOne;
2331	/** The number of cacheable allocations. */
2332	STAMCOUNTER StatCacheCacheable;
2333	/** The number of uncacheable allocations. */
2334	STAMCOUNTER StatCacheUncacheable;
2335	#else
2336	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
2337	#endif
2338	/** The AVL tree for looking up a page by its HC physical address. */
2339	AVLOHCPHYSTREE HCPhysTree;
2340	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
2341	/** Array of pages. (cMaxPages in length)
2342	* The Id is the index into thist array.
2343	*/
2344	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2345	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2346	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2347	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2348	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2349	#ifdef VBOX_WITH_STATISTICS
2350	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2351	#endif
2352	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2353
2354
2355	/** @def PGMPOOL_PAGE_2_PTR
2356	* Maps a pool page pool into the current context.
2357	*
2358	* @returns VBox status code.
2359	* @param pVM The VM handle.
2360	* @param pPage The pool page.
2361	*
2362	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2363	* small page window employeed by that function. Be careful.
2364	* @remark There is no need to assert on the result.
2365	*/
2366	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2367	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage) RTLOG_COMMA_SRC_POS)
2368	#elif defined(VBOX_STRICT)
2369	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2370	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2371	{
2372	Assert(pPage && pPage->pvPageR3);
2373	return pPage->pvPageR3;
2374	}
2375	#else
2376	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2377	#endif
2378
2379
2380	/** @def PGMPOOL_PAGE_2_PTR_V2
2381	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2382	*
2383	* @returns VBox status code.
2384	* @param pVM The VM handle.
2385	* @param pVCpu The current CPU.
2386	* @param pPage The pool page.
2387	*
2388	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2389	* small page window employeed by that function. Be careful.
2390	* @remark There is no need to assert on the result.
2391	*/
2392	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2393	# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage) RTLOG_COMMA_SRC_POS)
2394	#else
2395	# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2396	#endif
2397
2398
2399	/** @name Per guest page tracking data.
2400	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2401	* is to use more bits for it and split it up later on. But for now we'll play
2402	* safe and change as little as possible.
2403	*
2404	* The 16-bit word has two parts:
2405	*
2406	* The first 14-bit forms the @a idx field. It is either the index of a page in
2407	* the shadow page pool, or and index into the extent list.
2408	*
2409	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2410	* shadow page pool references to the page. If cRefs equals
2411	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2412	* (misnomer) table and not the shadow page pool.
2413	*
2414	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2415	* the 16-bit word.
2416	*
2417	* @{ */
2418	/** The shift count for getting to the cRefs part. */
2419	#define PGMPOOL_TD_CREFS_SHIFT 14
2420	/** The mask applied after shifting the tracking data down by
2421	* PGMPOOL_TD_CREFS_SHIFT. */
2422	#define PGMPOOL_TD_CREFS_MASK 0x3
2423	/** The cRefs value used to indiciate that the idx is the head of a
2424	* physical cross reference list. */
2425	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2426	/** The shift used to get idx. */
2427	#define PGMPOOL_TD_IDX_SHIFT 0
2428	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2429	#define PGMPOOL_TD_IDX_MASK 0x3fff
2430	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2431	* simply too many mappings of this page. */
2432	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2433
2434	/** @def PGMPOOL_TD_MAKE
2435	* Makes a 16-bit tracking data word.
2436	*
2437	* @returns tracking data.
2438	* @param cRefs The @a cRefs field. Must be within bounds!
2439	* @param idx The @a idx field. Must also be within bounds! */
2440	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2441
2442	/** @def PGMPOOL_TD_GET_CREFS
2443	* Get the @a cRefs field from a tracking data word.
2444	*
2445	* @returns The @a cRefs field
2446	* @param u16 The tracking data word.
2447	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2448	* non-zero @a u16. */
2449	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2450
2451	/** @def PGMPOOL_TD_GET_IDX
2452	* Get the @a idx field from a tracking data word.
2453	*
2454	* @returns The @a idx field
2455	* @param u16 The tracking data word. */
2456	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2457	/** @} */
2458
2459
2460	/**
2461	* Trees are using self relative offsets as pointers.
2462	* So, all its data, including the root pointer, must be in the heap for HC and GC
2463	* to have the same layout.
2464	*/
2465	typedef struct PGMTREES
2466	{
2467	/** Physical access handlers (AVL range+offsetptr tree). */
2468	AVLROGCPHYSTREE PhysHandlers;
2469	/** Virtual access handlers (AVL range + GC ptr tree). */
2470	AVLROGCPTRTREE VirtHandlers;
2471	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2472	AVLROGCPHYSTREE PhysToVirtHandlers;
2473	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2474	AVLROGCPTRTREE HyperVirtHandlers;
2475	} PGMTREES;
2476	/** Pointer to PGM trees. */
2477	typedef PGMTREES *PPGMTREES;
2478
2479
2480	/**
2481	* Page fault guest state for the AMD64 paging mode.
2482	*/
2483	typedef struct PGMPTWALKCORE
2484	{
2485	/** The guest virtual address that is being resolved by the walk
2486	* (input). */
2487	RTGCPTR GCPtr;
2488
2489	/** The guest physcial address that is the result of the walk.
2490	* @remarks only valid if fSucceeded is set. */
2491	RTGCPHYS GCPhys;
2492
2493	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2494	bool fSucceeded;
2495	/** The level problem arrised at.
2496	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2497	* level 8. This is 0 on success. */
2498	uint8_t uLevel;
2499	/** Set if the page isn't present. */
2500	bool fNotPresent;
2501	/** Encountered a bad physical address. */
2502	bool fBadPhysAddr;
2503	/** Set if there was reserved bit violations. */
2504	bool fRsvdError;
2505	/** Set if it involves a big page (2/4 MB). */
2506	bool fBigPage;
2507	/** Set if it involves a gigantic page (1 GB). */
2508	bool fGigantPage;
2509	/** The effect X86_PTE_US flag for the address. */
2510	bool fEffectiveUS;
2511	/** The effect X86_PTE_RW flag for the address. */
2512	bool fEffectiveRW;
2513	/** The effect X86_PTE_NX flag for the address. */
2514	bool fEffectiveNX;
2515	} PGMPTWALKCORE;
2516
2517
2518	/**
2519	* Guest page table walk for the AMD64 mode.
2520	*/
2521	typedef struct PGMPTWALKGSTAMD64
2522	{
2523	/** The common core. */
2524	PGMPTWALKCORE Core;
2525
2526	PX86PML4 pPml4;
2527	PX86PML4E pPml4e;
2528	X86PML4E Pml4e;
2529
2530	PX86PDPT pPdpt;
2531	PX86PDPE pPdpe;
2532	X86PDPE Pdpe;
2533
2534	PX86PDPAE pPd;
2535	PX86PDEPAE pPde;
2536	X86PDEPAE Pde;
2537
2538	PX86PTPAE pPt;
2539	PX86PTEPAE pPte;
2540	X86PTEPAE Pte;
2541	} PGMPTWALKGSTAMD64;
2542	/** Pointer to a AMD64 guest page table walk. */
2543	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2544	/** Pointer to a const AMD64 guest page table walk. */
2545	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2546
2547	/**
2548	* Guest page table walk for the PAE mode.
2549	*/
2550	typedef struct PGMPTWALKGSTPAE
2551	{
2552	/** The common core. */
2553	PGMPTWALKCORE Core;
2554
2555	PX86PDPT pPdpt;
2556	PX86PDPE pPdpe;
2557	X86PDPE Pdpe;
2558
2559	PX86PDPAE pPd;
2560	PX86PDEPAE pPde;
2561	X86PDEPAE Pde;
2562
2563	PX86PTPAE pPt;
2564	PX86PTEPAE pPte;
2565	X86PTEPAE Pte;
2566	} PGMPTWALKGSTPAE;
2567	/** Pointer to a PAE guest page table walk. */
2568	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2569	/** Pointer to a const AMD64 guest page table walk. */
2570	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2571
2572	/**
2573	* Guest page table walk for the 32-bit mode.
2574	*/
2575	typedef struct PGMPTWALKGST32BIT
2576	{
2577	/** The common core. */
2578	PGMPTWALKCORE Core;
2579
2580	PX86PD pPd;
2581	PX86PDE pPde;
2582	X86PDE Pde;
2583
2584	PX86PT pPt;
2585	PX86PTE pPte;
2586	X86PTE Pte;
2587	} PGMPTWALKGST32BIT;
2588	/** Pointer to a 32-bit guest page table walk. */
2589	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2590	/** Pointer to a const 32-bit guest page table walk. */
2591	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2592
2593
2594	/** @name Paging mode macros
2595	* @{
2596	*/
2597	#ifdef IN_RC
2598	# define PGM_CTX(a,b) a##RC##b
2599	# define PGM_CTX_STR(a,b) a "GC" b
2600	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2601	#else
2602	# ifdef IN_RING3
2603	# define PGM_CTX(a,b) a##R3##b
2604	# define PGM_CTX_STR(a,b) a "R3" b
2605	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2606	# else
2607	# define PGM_CTX(a,b) a##R0##b
2608	# define PGM_CTX_STR(a,b) a "R0" b
2609	# define PGM_CTX_DECL(type) VMMDECL(type)
2610	# endif
2611	#endif
2612
2613	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2614	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2615	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2616	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2617	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2618	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2619	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2620	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2621	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2622	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2623	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2624	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2625	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2626	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2627	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2628	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2629	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2630
2631	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2632	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2633	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2634	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2635	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2636	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2637	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2638	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2639	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2640	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2641	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2642	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2643	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2644	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2645	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2646	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2647	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2648
2649	/* Shw_Gst */
2650	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2651	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2652	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2653	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2654	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2655	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2656	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2657	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2658	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2659	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2660	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2661	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2662	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2663	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2664	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2665	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2666	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2667	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2668	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2669
2670	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2671	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2672	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2673	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2674	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2675	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2676	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2677	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2678	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2679	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2680	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2681	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2682	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2683	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2684	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2685	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2686	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2687	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2688	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2689	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2690	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2691	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2692	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2693	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2694	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2695	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2696	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2697	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2698	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2699	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2700	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2701	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2702	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2703	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2704	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2705	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2706	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2707
2708	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2709	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2710	/** @} */
2711
2712	/**
2713	* Data for each paging mode.
2714	*/
2715	typedef struct PGMMODEDATA
2716	{
2717	/** The guest mode type. */
2718	uint32_t uGstType;
2719	/** The shadow mode type. */
2720	uint32_t uShwType;
2721
2722	/** @name Function pointers for Shadow paging.
2723	* @{
2724	*/
2725	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2726	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2727	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2728	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2729
2730	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2731	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2732
2733	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2734	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2735	/** @} */
2736
2737	/** @name Function pointers for Guest paging.
2738	* @{
2739	*/
2740	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2741	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2742	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2743	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2744	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2745	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2746	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2747	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2748	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2749	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2750	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2751	/** @} */
2752
2753	/** @name Function pointers for Both Shadow and Guest paging.
2754	* @{
2755	*/
2756	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2757	/* no pfnR3BthTrap0eHandler */
2758	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2759	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2760	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2761	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2762	#ifdef VBOX_STRICT
2763	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2764	#endif
2765	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2766	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2767
2768	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2769	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2770	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2771	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2772	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2773	#ifdef VBOX_STRICT
2774	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2775	#endif
2776	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2777	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2778
2779	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2780	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2781	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2782	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2783	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2784	#ifdef VBOX_STRICT
2785	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2786	#endif
2787	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2788	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2789	/** @} */
2790	} PGMMODEDATA, *PPGMMODEDATA;
2791
2792
2793	#ifdef VBOX_WITH_STATISTICS
2794	/**
2795	* PGM statistics.
2796	*
2797	* These lives on the heap when compiled in as they would otherwise waste
2798	* unecessary space in release builds.
2799	*/
2800	typedef struct PGMSTATS
2801	{
2802	/* R3 only: */
2803	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2804	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2805
2806	/* R3+RZ */
2807	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2808	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2809	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2810	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2811	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2812	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2813	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2814	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2815	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2816	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2817	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2818	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2819	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2820	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2821	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2822	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2823	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2824	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2825	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2826	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2827	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2828	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2829	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2830	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2831	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2832	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2833	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2834	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2835
2836	/* RC only: */
2837	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2838	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2839
2840	STAMCOUNTER StatRZPhysRead;
2841	STAMCOUNTER StatRZPhysReadBytes;
2842	STAMCOUNTER StatRZPhysWrite;
2843	STAMCOUNTER StatRZPhysWriteBytes;
2844	STAMCOUNTER StatR3PhysRead;
2845	STAMCOUNTER StatR3PhysReadBytes;
2846	STAMCOUNTER StatR3PhysWrite;
2847	STAMCOUNTER StatR3PhysWriteBytes;
2848	STAMCOUNTER StatRCPhysRead;
2849	STAMCOUNTER StatRCPhysReadBytes;
2850	STAMCOUNTER StatRCPhysWrite;
2851	STAMCOUNTER StatRCPhysWriteBytes;
2852
2853	STAMCOUNTER StatRZPhysSimpleRead;
2854	STAMCOUNTER StatRZPhysSimpleReadBytes;
2855	STAMCOUNTER StatRZPhysSimpleWrite;
2856	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2857	STAMCOUNTER StatR3PhysSimpleRead;
2858	STAMCOUNTER StatR3PhysSimpleReadBytes;
2859	STAMCOUNTER StatR3PhysSimpleWrite;
2860	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2861	STAMCOUNTER StatRCPhysSimpleRead;
2862	STAMCOUNTER StatRCPhysSimpleReadBytes;
2863	STAMCOUNTER StatRCPhysSimpleWrite;
2864	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2865
2866	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2867	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2868	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2869	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2870	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2871	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2872	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2873
2874	/** Time spent by the host OS for large page allocation. */
2875	STAMPROFILE StatAllocLargePage;
2876	/** Time spent clearing the newly allocated large pages. */
2877	STAMPROFILE StatClearLargePage;
2878	/** pgmPhysIsValidLargePage profiling - R3 */
2879	STAMPROFILE StatR3IsValidLargePage;
2880	/** pgmPhysIsValidLargePage profiling - RZ*/
2881	STAMPROFILE StatRZIsValidLargePage;
2882
2883	STAMPROFILE StatChunkAging;
2884	STAMPROFILE StatChunkFindCandidate;
2885	STAMPROFILE StatChunkUnmap;
2886	STAMPROFILE StatChunkMap;
2887	} PGMSTATS;
2888	#endif /* VBOX_WITH_STATISTICS */
2889
2890
2891	/**
2892	* Converts a PGM pointer into a VM pointer.
2893	* @returns Pointer to the VM structure the PGM is part of.
2894	* @param pPGM Pointer to PGM instance data.
2895	*/
2896	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2897
2898	/**
2899	* PGM Data (part of VM)
2900	*/
2901	typedef struct PGM
2902	{
2903	/** Offset to the VM structure. */
2904	int32_t offVM;
2905	/** Offset of the PGMCPU structure relative to VMCPU. */
2906	int32_t offVCpuPGM;
2907
2908	/** @cfgm{RamPreAlloc, boolean, false}
2909	* Indicates whether the base RAM should all be allocated before starting
2910	* the VM (default), or if it should be allocated when first written to.
2911	*/
2912	bool fRamPreAlloc;
2913	/** Indicates whether write monitoring is currently in use.
2914	* This is used to prevent conflicts between live saving and page sharing
2915	* detection. */
2916	bool fPhysWriteMonitoringEngaged;
2917	/** Set if the CPU has less than 52-bit physical address width.
2918	* This is used */
2919	bool fLessThan52PhysicalAddressBits;
2920	/** Set when nested paging is active.
2921	* This is meant to save calls to HWACCMIsNestedPagingActive and let the
2922	* compilers optimize the code better. Whether we use nested paging or
2923	* not is something we find out during VMM initialization and we won't
2924	* change this later on. */
2925	bool fNestedPaging;
2926	/** The host paging mode. (This is what SUPLib reports.) */
2927	SUPPAGINGMODE enmHostMode;
2928	/** We're not in a state which permits writes to guest memory.
2929	* (Only used in strict builds.) */
2930	bool fNoMorePhysWrites;
2931	/** Alignment padding that makes the next member start on a 8 byte boundrary. */
2932	bool afAlignment1[3];
2933
2934	/** Indicates that PGMR3FinalizeMappings has been called and that further
2935	* PGMR3MapIntermediate calls will be rejected. */
2936	bool fFinalizedMappings;
2937	/** If set no conflict checks are required. */
2938	bool fMappingsFixed;
2939	/** If set if restored as fixed but we were unable to re-fixate at the old
2940	* location because of room or address incompatibilities. */
2941	bool fMappingsFixedRestored;
2942	/** If set, then no mappings are put into the shadow page table.
2943	* Use pgmMapAreMappingsEnabled() instead of direct access. */
2944	bool fMappingsDisabled;
2945	/** Size of fixed mapping.
2946	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2947	uint32_t cbMappingFixed;
2948	/** Generation ID for the RAM ranges. This member is incremented everytime
2949	* a RAM range is linked or unlinked. */
2950	uint32_t volatile idRamRangesGen;
2951
2952	/** Base address (GC) of fixed mapping.
2953	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2954	RTGCPTR GCPtrMappingFixed;
2955	/** The address of the previous RAM range mapping. */
2956	RTGCPTR GCPtrPrevRamRangeMapping;
2957
2958	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2959	RTGCPHYS GCPhys4MBPSEMask;
2960	/** Mask containing the invalid bits of a guest physical address.
2961	* @remarks this does not stop at bit 52. */
2962	RTGCPHYS GCPhysInvAddrMask;
2963
2964
2965	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2966	* This is sorted by physical address and contains no overlapping ranges. */
2967	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2968	/** PGM offset based trees - R3 Ptr. */
2969	R3PTRTYPE(PPGMTREES) pTreesR3;
2970	/** Caching the last physical handler we looked up in R3. */
2971	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2972	/** Shadow Page Pool - R3 Ptr. */
2973	R3PTRTYPE(PPGMPOOL) pPoolR3;
2974	/** Linked list of GC mappings - for HC.
2975	* The list is sorted ascending on address. */
2976	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2977	/** Pointer to the list of ROM ranges - for R3.
2978	* This is sorted by physical address and contains no overlapping ranges. */
2979	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2980	/** Pointer to the list of MMIO2 ranges - for R3.
2981	* Registration order. */
2982	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2983	/** Pointer to SHW+GST mode data (function pointers).
2984	* The index into this table is made up from */
2985	R3PTRTYPE(PPGMMODEDATA) paModeData;
2986	/RTR3PTR R3PtrAlignment0;/
2987
2988
2989	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2990	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2991	/** PGM offset based trees - R0 Ptr. */
2992	R0PTRTYPE(PPGMTREES) pTreesR0;
2993	/** Caching the last physical handler we looked up in R0. */
2994	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2995	/** Shadow Page Pool - R0 Ptr. */
2996	R0PTRTYPE(PPGMPOOL) pPoolR0;
2997	/** Linked list of GC mappings - for R0.
2998	* The list is sorted ascending on address. */
2999	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3000	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3001	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3002	/RTR0PTR R0PtrAlignment0;/
3003
3004
3005	/** RC pointer corresponding to PGM::pRamRangesR3. */
3006	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
3007	/** PGM offset based trees - RC Ptr. */
3008	RCPTRTYPE(PPGMTREES) pTreesRC;
3009	/** Caching the last physical handler we looked up in RC. */
3010	RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3011	/** Shadow Page Pool - RC Ptr. */
3012	RCPTRTYPE(PPGMPOOL) pPoolRC;
3013	/** Linked list of GC mappings - for RC.
3014	* The list is sorted ascending on address. */
3015	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3016	/** RC pointer corresponding to PGM::pRomRangesR3. */
3017	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3018	/RTRCPTR RCPtrAlignment0;/
3019	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3020	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3021	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3022	RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3023
3024
3025	/** Pointer to the 5 page CR3 content mapping.
3026	* The first page is always the CR3 (in some form) while the 4 other pages
3027	* are used of the PDs in PAE mode. */
3028	RTGCPTR GCPtrCR3Mapping;
3029
3030	/** @name Intermediate Context
3031	* @{ */
3032	/** Pointer to the intermediate page directory - Normal. */
3033	R3PTRTYPE(PX86PD) pInterPD;
3034	/** Pointer to the intermedate page tables - Normal.
3035	* There are two page tables, one for the identity mapping and one for
3036	* the host context mapping (of the core code). */
3037	R3PTRTYPE(PX86PT) apInterPTs[2];
3038	/** Pointer to the intermedate page tables - PAE. */
3039	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3040	/** Pointer to the intermedate page directory - PAE. */
3041	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3042	/** Pointer to the intermedate page directory - PAE. */
3043	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3044	/** Pointer to the intermedate page-map level 4 - AMD64. */
3045	R3PTRTYPE(PX86PML4) pInterPaePML4;
3046	/** Pointer to the intermedate page directory - AMD64. */
3047	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3048	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3049	RTHCPHYS HCPhysInterPD;
3050	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3051	RTHCPHYS HCPhysInterPaePDPT;
3052	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3053	RTHCPHYS HCPhysInterPaePML4;
3054	/** @} */
3055
3056	/** Base address of the dynamic page mapping area.
3057	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3058	*
3059	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3060	* work out. Some cleaning up of the initialization that would
3061	* remove this memory is yet to be done...
3062	*/
3063	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3064	/** The address of the raw-mode context mapping cache. */
3065	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3066	/** The address of the ring-0 mapping cache if we're making use of it. */
3067	RTR0PTR pvR0DynMapUsed;
3068	#if HC_ARCH_BITS == 32
3069	/** Alignment padding that makes the next member start on a 8 byte boundrary. */
3070	uint32_t u32Alignment2;
3071	#endif
3072
3073	/** PGM critical section.
3074	* This protects the physical & virtual access handlers, ram ranges,
3075	* and the page flag updating (some of it anyway).
3076	*/
3077	PDMCRITSECT CritSect;
3078
3079	/**
3080	* Data associated with managing the ring-3 mappings of the allocation chunks.
3081	*/
3082	struct
3083	{
3084	/** The chunk tree, ordered by chunk id. */
3085	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3086	R3PTRTYPE(PAVLU32NODECORE) pTree;
3087	#else
3088	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3089	#endif
3090	#if HC_ARCH_BITS == 32
3091	uint32_t u32Alignment;
3092	#endif
3093	/** The chunk mapping TLB. */
3094	PGMCHUNKR3MAPTLB Tlb;
3095	/** The number of mapped chunks. */
3096	uint32_t c;
3097	/** The maximum number of mapped chunks.
3098	* @cfgm PGM/MaxRing3Chunks */
3099	uint32_t cMax;
3100	/** The current time. */
3101	uint32_t iNow;
3102	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3103	uint32_t AgeingCountdown;
3104	} ChunkR3Map;
3105
3106	/**
3107	* The page mapping TLB for ring-3 and (for the time being) ring-0.
3108	*/
3109	PGMPAGER3MAPTLB PhysTlbHC;
3110
3111	/** @name The zero page.
3112	* @{ */
3113	/** The host physical address of the zero page. */
3114	RTHCPHYS HCPhysZeroPg;
3115	/** The ring-3 mapping of the zero page. */
3116	RTR3PTR pvZeroPgR3;
3117	/** The ring-0 mapping of the zero page. */
3118	RTR0PTR pvZeroPgR0;
3119	/** The GC mapping of the zero page. */
3120	RTRCPTR pvZeroPgRC;
3121	RTRCPTR RCPtrAlignment3;
3122	/** @}*/
3123
3124	/** @name The Invalid MMIO page.
3125	* This page is filled with 0xfeedface.
3126	* @{ */
3127	/** The host physical address of the invalid MMIO page. */
3128	RTHCPHYS HCPhysMmioPg;
3129	/** The host pysical address of the invalid MMIO page pluss all invalid
3130	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3131	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3132	RTHCPHYS HCPhysInvMmioPg;
3133	/** The ring-3 mapping of the invalid MMIO page. */
3134	RTR3PTR pvMmioPgR3;
3135	#if HC_ARCH_BITS == 32
3136	RTR3PTR R3PtrAlignment4;
3137	#endif
3138	/** @} */
3139
3140
3141	/** The number of handy pages. */
3142	uint32_t cHandyPages;
3143
3144	/** The number of large handy pages. */
3145	uint32_t cLargeHandyPages;
3146
3147	/**
3148	* Array of handy pages.
3149	*
3150	* This array is used in a two way communication between pgmPhysAllocPage
3151	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3152	* an intermediary.
3153	*
3154	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3155	* (The current size of 32 pages, means 128 KB of handy memory.)
3156	*/
3157	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3158
3159	/**
3160	* Array of large handy pages. (currently size 1)
3161	*
3162	* This array is used in a two way communication between pgmPhysAllocLargePage
3163	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3164	* an intermediary.
3165	*/
3166	GMMPAGEDESC aLargeHandyPage[1];
3167
3168	/**
3169	* Live save data.
3170	*/
3171	struct
3172	{
3173	/** Per type statistics. */
3174	struct
3175	{
3176	/** The number of ready pages. */
3177	uint32_t cReadyPages;
3178	/** The number of dirty pages. */
3179	uint32_t cDirtyPages;
3180	/** The number of ready zero pages. */
3181	uint32_t cZeroPages;
3182	/** The number of write monitored pages. */
3183	uint32_t cMonitoredPages;
3184	} Rom,
3185	Mmio2,
3186	Ram;
3187	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3188	uint32_t cIgnoredPages;
3189	/** Indicates that a live save operation is active. */
3190	bool fActive;
3191	/** Padding. */
3192	bool afReserved[2];
3193	/** The next history index. */
3194	uint8_t iDirtyPagesHistory;
3195	/** History of the total amount of dirty pages. */
3196	uint32_t acDirtyPagesHistory[64];
3197	/** Short term dirty page average. */
3198	uint32_t cDirtyPagesShort;
3199	/** Long term dirty page average. */
3200	uint32_t cDirtyPagesLong;
3201	/** The number of saved pages. This is used to get some kind of estimate of the
3202	* link speed so we can decide when we're done. It is reset after the first
3203	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3204	* zero pages. */
3205	uint64_t cSavedPages;
3206	/** The nanosecond timestamp when cSavedPages was 0. */
3207	uint64_t uSaveStartNS;
3208	/** Pages per second (for statistics). */
3209	uint32_t cPagesPerSecond;
3210	uint32_t cAlignment;
3211	} LiveSave;
3212
3213	/** @name Error injection.
3214	* @{ */
3215	/** Inject handy page allocation errors pretending we're completely out of
3216	* memory. */
3217	bool volatile fErrInjHandyPages;
3218	/** Padding. */
3219	bool afReserved[3];
3220	/** @} */
3221
3222	/** @name Release Statistics
3223	* @{ */
3224	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3225	uint32_t cPrivatePages; /*< The number of private pages. /
3226	uint32_t cSharedPages; /*< The number of shared pages. /
3227	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3228	uint32_t cZeroPages; /*< The number of zero backed pages. /
3229	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3230	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3231	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3232	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3233	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3234	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3235	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3236	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3237	/* uint32_t aAlignment4[1]; */
3238
3239	/** The number of times we were forced to change the hypervisor region location. */
3240	STAMCOUNTER cRelocations;
3241
3242	STAMCOUNTER StatLargePageAlloc; /*< The number of large pages we've allocated./
3243	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3244	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3245	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3246	/** @} */
3247
3248	#ifdef VBOX_WITH_STATISTICS
3249	/** @name Statistics on the heap.
3250	* @{ */
3251	R3PTRTYPE(PGMSTATS *) pStatsR3;
3252	R0PTRTYPE(PGMSTATS *) pStatsR0;
3253	RCPTRTYPE(PGMSTATS *) pStatsRC;
3254	RTRCPTR RCPtrAlignment;
3255	/** @} */
3256	#endif
3257	} PGM;
3258	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3259	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3260	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3261	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3262	AssertCompileMemberAlignment(PGM, CritSect, 8);
3263	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3264	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3265	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3266	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3267	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3268	#endif /* !IN_TSTVMSTRUCTGC */
3269	/** Pointer to the PGM instance data. */
3270	typedef PGM *PPGM;
3271
3272
3273
3274	typedef struct PGMCPUSTATS
3275	{
3276	/* Common */
3277	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3278	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3279
3280	/* R0 only: */
3281	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3282	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3283
3284	/* RZ only: */
3285	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3286	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3287	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3288	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3289	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3290	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3291	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3292	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3293	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3294	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3295	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3296	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3297	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3298	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3299	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3300	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3301	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3302	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3303	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3304	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3305	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3306	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3307	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3308	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3309	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3310	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3311	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3312	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3313	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3314	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3315	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3316	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3317	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3318	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3319	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3320	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3321	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3322	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3323	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3324	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3325	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3326	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3327	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3328	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3329	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3330	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3331	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3332	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3333	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3334	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3335	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3336	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3337	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3338	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3339	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3340	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3341	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3342	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3343	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3344	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3345	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3346	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restorting to subset flushes. /
3347	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3348	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3349	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3350	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3351	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3352	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3353	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3354	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3355	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3356	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3357	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3358	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3359	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3360	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3361
3362	/* HC - R3 and (maybe) R0: */
3363
3364	/* RZ & R3: */
3365	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3366	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3367	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3368	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3369	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3370	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3371	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3372	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3373	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3374	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3375	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3376	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3377	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3378	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3379	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3380	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3381	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3382	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3383	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3384	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3385	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3386	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3387	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3388	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3389	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3390	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3391	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3392	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3393	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3394	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3395	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3396	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3397	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3398	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3399	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3400	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3401	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3402	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3403	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3404	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3405	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3406	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3407	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3408	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3409	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3410	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3411	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3412
3413	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3414	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3415	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3416	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3417	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3418	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3419	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3420	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3421	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3422	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3423	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3424	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3425	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3426	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3427	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3428	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3429	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3430	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3431	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3432	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3433	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3434	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3435	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3436	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3437	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3438	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3439	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3440	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3441	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3442	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3443	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3444	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3445	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3446	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3447	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3448	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3449	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3450	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3451	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3452	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3453	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3454	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3455	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3456	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3457	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3458	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3459	/** @} */
3460	} PGMCPUSTATS;
3461
3462
3463	/**
3464	* Converts a PGMCPU pointer into a VM pointer.
3465	* @returns Pointer to the VM structure the PGM is part of.
3466	* @param pPGM Pointer to PGMCPU instance data.
3467	*/
3468	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3469
3470	/**
3471	* Converts a PGMCPU pointer into a PGM pointer.
3472	* @returns Pointer to the VM structure the PGM is part of.
3473	* @param pPGM Pointer to PGMCPU instance data.
3474	*/
3475	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3476
3477	/**
3478	* PGMCPU Data (part of VMCPU).
3479	*/
3480	typedef struct PGMCPU
3481	{
3482	/** Offset to the VM structure. */
3483	int32_t offVM;
3484	/** Offset to the VMCPU structure. */
3485	int32_t offVCpu;
3486	/** Offset of the PGM structure relative to VMCPU. */
3487	int32_t offPGM;
3488	uint32_t uPadding0; /*< structure size alignment. /
3489
3490	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAW_MODE)
3491	/** Automatically tracked physical memory mapping set.
3492	* Ring-0 and strict raw-mode builds. */
3493	PGMMAPSET AutoSet;
3494	#endif
3495
3496	/** A20 gate mask.
3497	* Our current approach to A20 emulation is to let REM do it and don't bother
3498	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3499	* But whould need arrise, we'll subject physical addresses to this mask. */
3500	RTGCPHYS GCPhysA20Mask;
3501	/** A20 gate state - boolean! */
3502	bool fA20Enabled;
3503	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3504	bool fNoExecuteEnabled;
3505	/** Unused bits. */
3506	bool afUnused[2];
3507
3508	/** What needs syncing (PGM_SYNC_*).
3509	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3510	* PGMFlushTLB, and PGMR3Load. */
3511	RTUINT fSyncFlags;
3512
3513	/** The shadow paging mode. */
3514	PGMMODE enmShadowMode;
3515	/** The guest paging mode. */
3516	PGMMODE enmGuestMode;
3517
3518	/** The current physical address representing in the guest CR3 register. */
3519	RTGCPHYS GCPhysCR3;
3520
3521	/** @name 32-bit Guest Paging.
3522	* @{ */
3523	/** The guest's page directory, R3 pointer. */
3524	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3525	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3526	/** The guest's page directory, R0 pointer. */
3527	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3528	#endif
3529	/** The guest's page directory, static RC mapping. */
3530	RCPTRTYPE(PX86PD) pGst32BitPdRC;
3531	/** Mask containing the MBZ bits of a big page PDE. */
3532	uint32_t fGst32BitMbzBigPdeMask;
3533	/** Set if the page size extension (PSE) is enabled. */
3534	bool fGst32BitPageSizeExtension;
3535	/** Alignment padding. */
3536	bool afAlignment2[3];
3537	/** @} */
3538
3539	/** @name PAE Guest Paging.
3540	* @{ */
3541	/** The guest's page directory pointer table, static RC mapping. */
3542	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3543	/** The guest's page directory pointer table, R3 pointer. */
3544	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3545	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3546	/** The guest's page directory pointer table, R0 pointer. */
3547	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3548	#endif
3549
3550	/** The guest's page directories, R3 pointers.
3551	* These are individual pointers and don't have to be adjecent.
3552	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3553	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3554	/** The guest's page directories, R0 pointers.
3555	* Same restrictions as apGstPaePDsR3. */
3556	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3557	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3558	#endif
3559	/** The guest's page directories, static GC mapping.
3560	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3561	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3562	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3563	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3564	RTGCPHYS aGCPhysGstPaePDs[4];
3565	/** The physical addresses of the monitored guest page directories (PAE). */
3566	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3567	/** Mask containing the MBZ PTE bits. */
3568	uint64_t fGstPaeMbzPteMask;
3569	/** Mask containing the MBZ PDE bits. */
3570	uint64_t fGstPaeMbzPdeMask;
3571	/** Mask containing the MBZ big page PDE bits. */
3572	uint64_t fGstPaeMbzBigPdeMask;
3573	/** Mask containing the MBZ PDPE bits. */
3574	uint64_t fGstPaeMbzPdpeMask;
3575	/** @} */
3576
3577	/** @name AMD64 Guest Paging.
3578	* @{ */
3579	/** The guest's page directory pointer table, R3 pointer. */
3580	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3581	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3582	/** The guest's page directory pointer table, R0 pointer. */
3583	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3584	#else
3585	RTR0PTR alignment6b; /*< alignment equalizer. /
3586	#endif
3587	/** Mask containing the MBZ PTE bits. */
3588	uint64_t fGstAmd64MbzPteMask;
3589	/** Mask containing the MBZ PDE bits. */
3590	uint64_t fGstAmd64MbzPdeMask;
3591	/** Mask containing the MBZ big page PDE bits. */
3592	uint64_t fGstAmd64MbzBigPdeMask;
3593	/** Mask containing the MBZ PDPE bits. */
3594	uint64_t fGstAmd64MbzPdpeMask;
3595	/** Mask containing the MBZ big page PDPE bits. */
3596	uint64_t fGstAmd64MbzBigPdpeMask;
3597	/** Mask containing the MBZ PML4E bits. */
3598	uint64_t fGstAmd64MbzPml4eMask;
3599	/** Mask containing the PDPE bits that we shadow. */
3600	uint64_t fGstAmd64ShadowedPdpeMask;
3601	/** Mask containing the PML4E bits that we shadow. */
3602	uint64_t fGstAmd64ShadowedPml4eMask;
3603	/** @} */
3604
3605	/** @name PAE and AMD64 Guest Paging.
3606	* @{ */
3607	/** Mask containing the PTE bits that we shadow. */
3608	uint64_t fGst64ShadowedPteMask;
3609	/** Mask containing the PDE bits that we shadow. */
3610	uint64_t fGst64ShadowedPdeMask;
3611	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3612	uint64_t fGst64ShadowedBigPdeMask;
3613	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3614	uint64_t fGst64ShadowedBigPde4PteMask;
3615	/** @} */
3616
3617	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3618	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3619	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3620	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3621	/** Pointer to the page of the current active CR3 - RC Ptr. */
3622	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3623	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3624	uint32_t iShwUser;
3625	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3626	uint32_t iShwUserTable;
3627	# if HC_ARCH_BITS == 64
3628	RTRCPTR alignment6; /*< structure size alignment. /
3629	# endif
3630	/** @} */
3631
3632	/** @name Function pointers for Shadow paging.
3633	* @{
3634	*/
3635	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3636	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3637	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3638	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3639
3640	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3641	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3642
3643	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3644	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3645
3646	/** @} */
3647
3648	/** @name Function pointers for Guest paging.
3649	* @{
3650	*/
3651	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3652	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3653	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3654	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3655	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3656	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3657	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3658	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3659	#if HC_ARCH_BITS == 64
3660	RTRCPTR alignment3; /*< structure size alignment. /
3661	#endif
3662
3663	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3664	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3665	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3666	/** @} */
3667
3668	/** @name Function pointers for Both Shadow and Guest paging.
3669	* @{
3670	*/
3671	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3672	/* no pfnR3BthTrap0eHandler */
3673	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3674	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3675	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3676	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3677	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3678	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3679	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3680
3681	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3682	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3683	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3684	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3685	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3686	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3687	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3688	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3689
3690	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3691	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3692	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3693	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3694	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3695	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3696	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3697	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3698	#if 0
3699	RTRCPTR alignment2; /*< structure size alignment. /
3700	#endif
3701	/** @} */
3702
3703	/** For saving stack space, the disassembler state is allocated here instead of
3704	* on the stack.
3705	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3706	union
3707	{
3708	/** The disassembler scratch space. */
3709	DISCPUSTATE DisState;
3710	/** Padding. */
3711	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3712	};
3713
3714	/** Count the number of pgm pool access handler calls. */
3715	uint64_t cPoolAccessHandler;
3716
3717	/** @name Release Statistics
3718	* @{ */
3719	/** The number of times the guest has switched mode since last reset or statistics reset. */
3720	STAMCOUNTER cGuestModeChanges;
3721	/** @} */
3722
3723	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3724	/** @name Statistics
3725	* @{ */
3726	/** RC: Pointer to the statistics. */
3727	RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3728	/** RC: Which statistic this \#PF should be attributed to. */
3729	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3730	/** R0: Pointer to the statistics. */
3731	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3732	/** R0: Which statistic this \#PF should be attributed to. */
3733	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3734	/** R3: Pointer to the statistics. */
3735	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3736	/** Alignment padding. */
3737	RTR3PTR pPaddingR3;
3738	/** @} */
3739	#endif /* VBOX_WITH_STATISTICS */
3740	} PGMCPU;
3741	/** Pointer to the per-cpu PGM data. */
3742	typedef PGMCPU *PPGMCPU;
3743
3744
3745	/** @name PGM::fSyncFlags Flags
3746	* @{
3747	*/
3748	/** Updates the virtual access handler state bit in PGMPAGE. */
3749	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3750	/** Always sync CR3. */
3751	#define PGM_SYNC_ALWAYS RT_BIT(1)
3752	/** Check monitoring on next CR3 (re)load and invalidate page.
3753	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3754	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3755	/** Check guest mapping in SyncCR3. */
3756	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3757	/** Clear the page pool (a light weight flush). */
3758	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3759	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3760	/** @} */
3761
3762
3763	RT_C_DECLS_BEGIN
3764
3765	int pgmLock(PVM pVM);
3766	void pgmUnlock(PVM pVM);
3767
3768	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3769	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3770	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3771	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3772	int pgmMapResolveConflicts(PVM pVM);
3773	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3774
3775	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3776	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3777	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3778	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
3779	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3780	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
3781	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3782	#else
3783	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3784	#endif
3785	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3786	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3787
3788	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3789	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3790	int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3791	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3792	int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3793	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3794	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3795	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3796	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3797	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3798	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3799	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3800	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3801	VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3802	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3803	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3804
3805	#ifdef IN_RING3
3806	void pgmR3PhysRelinkRamRanges(PVM pVM);
3807	int pgmR3PhysRamPreAllocate(PVM pVM);
3808	int pgmR3PhysRamReset(PVM pVM);
3809	int pgmR3PhysRomReset(PVM pVM);
3810	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3811	int pgmR3PhysRamTerm(PVM pVM);
3812	void pgmR3PhysRomTerm(PVM pVM);
3813
3814	int pgmR3PoolInit(PVM pVM);
3815	void pgmR3PoolRelocate(PVM pVM);
3816	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3817	void pgmR3PoolReset(PVM pVM);
3818	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3819	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3820	void pgmR3PoolWriteProtectPages(PVM pVM);
3821
3822	#endif /* IN_RING3 */
3823	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| IN_RC
3824	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3825	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3826	# ifdef LOG_ENABLED
3827	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3828	# else
3829	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3830	# endif
3831	#endif
3832	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
3833	uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3834
3835	DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
3836	PPPGMPOOLPAGE ppPage)
3837	{
3838	return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
3839	}
3840
3841	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3842	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3843	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3844	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3845	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3846	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3847	int pgmPoolSyncCR3(PVMCPU pVCpu);
3848	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3849	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3850	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3851	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3852	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3853	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3854	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3855	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3856	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3857
3858	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3859	void pgmPoolResetDirtyPages(PVM pVM);
3860
3861	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3862	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3863
3864	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3865	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3866	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3867	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3868
3869	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3870	int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3871
3872	int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3873	int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3874	int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3875	int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3876
3877	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3878	DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3879	DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3880	# endif
3881
3882	RT_C_DECLS_END
3883
3884	/** @} */
3885
3886	#endif
3887

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 32225

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