VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 32302

Last change on this file since 32302 was 32302, checked in by vboxsync, 14 years ago

FTM statistics
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 174.3 KB
Line 
1/* $Id: PGMInternal.h 32302 2010-09-08 09:21:30Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm.h>
28#include <VBox/mm.h>
29#include <VBox/pdmcritsect.h>
30#include <VBox/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/gmm.h>
35#include <VBox/hwaccm.h>
36#include <VBox/hwacc_vmx.h>
37#include <include/internal/pgm.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 1 /* testing */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark Use with care as we don't have so much dynamic mapping space in
237 * ring-0 on 32-bit darwin and in RC.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243#else
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_GCPHYS_2_PTR_V2
249 * Maps a GC physical page address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM handle.
253 * @param pVCpu The current CPU.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark Use with care as we don't have so much dynamic mapping space in
258 * ring-0 on 32-bit darwin and in RC.
259 * @remark There is no need to assert on the result.
260 */
261#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
262# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264#else
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM handle.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark Use with care as we don't have so much dynamic mapping space in
278 * ring-0 on 32-bit darwin and in RC.
279 * @remark There is no need to assert on the result.
280 */
281#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVCpu The current CPU.
288 * @param GCPhys The GC physical address to map to a virtual one.
289 * @param ppv Where to store the virtual address. No need to cast this.
290 *
291 * @remark Use with care as we don't have so much dynamic mapping space in
292 * ring-0 on 32-bit darwin and in RC.
293 * @remark There is no need to assert on the result.
294 */
295#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_DYNMAP_UNUSED_HINT
318 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319 * is no longer used.
320 *
321 * For best effect only apply this to the page that was mapped most recently.
322 *
323 * @param pVCpu The current CPU.
324 * @param pPage The pool page.
325 */
326#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327# ifdef LOG_ENABLED
328# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329# else
330# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331# endif
332#else
333# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334#endif
335
336/** @def PGM_DYNMAP_UNUSED_HINT_VM
337 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338 * is no longer used.
339 *
340 * For best effect only apply this to the page that was mapped most recently.
341 *
342 * @param pVM The VM handle.
343 * @param pPage The pool page.
344 */
345#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348/** @def PGM_INVL_PG
349 * Invalidates a page.
350 *
351 * @param pVCpu The VMCPU handle.
352 * @param GCVirt The virtual address of the page to invalidate.
353 */
354#ifdef IN_RC
355# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356#elif defined(IN_RING0)
357# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_PG_ALL_VCPU
363 * Invalidates a page on all VCPUs
364 *
365 * @param pVM The VM handle.
366 * @param GCVirt The virtual address of the page to invalidate.
367 */
368#ifdef IN_RC
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370#elif defined(IN_RING0)
371# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372#else
373# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374#endif
375
376/** @def PGM_INVL_BIG_PG
377 * Invalidates a 4MB page directory entry.
378 *
379 * @param pVCpu The VMCPU handle.
380 * @param GCVirt The virtual address within the page directory to invalidate.
381 */
382#ifdef IN_RC
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384#elif defined(IN_RING0)
385# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386#else
387# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388#endif
389
390/** @def PGM_INVL_VCPU_TLBS()
391 * Invalidates the TLBs of the specified VCPU
392 *
393 * @param pVCpu The VMCPU handle.
394 */
395#ifdef IN_RC
396# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397#elif defined(IN_RING0)
398# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399#else
400# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401#endif
402
403/** @def PGM_INVL_ALL_VCPU_TLBS()
404 * Invalidates the TLBs of all VCPUs
405 *
406 * @param pVM The VM handle.
407 */
408#ifdef IN_RC
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410#elif defined(IN_RING0)
411# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412#else
413# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414#endif
415
416
417/** @name Safer Shadow PAE PT/PTE
418 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419 * present.
420 *
421 * @{
422 */
423#if 1
424/**
425 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
426 * invalid entries for present.
427 * @sa X86PTEPAE.
428 */
429typedef union PGMSHWPTEPAE
430{
431 /** Unsigned integer view */
432 X86PGPAEUINT uCareful;
433 /* Not other views. */
434} PGMSHWPTEPAE;
435
436# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
443# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
446# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
452
453/**
454 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
455 * invalid entries for present.
456 * @sa X86PTPAE.
457 */
458typedef struct PGMSHWPTPAE
459{
460 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461} PGMSHWPTPAE;
462
463#else
464typedef X86PTEPAE PGMSHWPTEPAE;
465typedef X86PTPAE PGMSHWPTPAE;
466# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
473# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
476# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
482
483#endif
484
485/** Pointer to a shadow PAE PTE. */
486typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487/** Pointer to a const shadow PAE PTE. */
488typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490/** Pointer to a shadow PAE page table. */
491typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492/** Pointer to a const shadow PAE page table. */
493typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494/** @} */
495
496
497/** Size of the GCPtrConflict array in PGMMAPPING.
498 * @remarks Must be a power of two. */
499#define PGMMAPPING_CONFLICT_MAX 8
500
501/**
502 * Structure for tracking GC Mappings.
503 *
504 * This structure is used by linked list in both GC and HC.
505 */
506typedef struct PGMMAPPING
507{
508 /** Pointer to next entry. */
509 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510 /** Pointer to next entry. */
511 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512 /** Pointer to next entry. */
513 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514 /** Indicate whether this entry is finalized. */
515 bool fFinalized;
516 /** Start Virtual address. */
517 RTGCPTR GCPtr;
518 /** Last Virtual address (inclusive). */
519 RTGCPTR GCPtrLast;
520 /** Range size (bytes). */
521 RTGCPTR cb;
522 /** Pointer to relocation callback function. */
523 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524 /** User argument to the callback. */
525 R3PTRTYPE(void *) pvUser;
526 /** Mapping description / name. For easing debugging. */
527 R3PTRTYPE(const char *) pszDesc;
528 /** Last 8 addresses that caused conflicts. */
529 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530 /** Number of conflicts for this hypervisor mapping. */
531 uint32_t cConflicts;
532 /** Number of page tables. */
533 uint32_t cPTs;
534
535 /** Array of page table mapping data. Each entry
536 * describes one page table. The array can be longer
537 * than the declared length.
538 */
539 struct
540 {
541 /** The HC physical address of the page table. */
542 RTHCPHYS HCPhysPT;
543 /** The HC physical address of the first PAE page table. */
544 RTHCPHYS HCPhysPaePT0;
545 /** The HC physical address of the second PAE page table. */
546 RTHCPHYS HCPhysPaePT1;
547 /** The HC virtual address of the 32-bit page table. */
548 R3PTRTYPE(PX86PT) pPTR3;
549 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551 /** The RC virtual address of the 32-bit page table. */
552 RCPTRTYPE(PX86PT) pPTRC;
553 /** The RC virtual address of the two PAE page table. */
554 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555 /** The R0 virtual address of the 32-bit page table. */
556 R0PTRTYPE(PX86PT) pPTR0;
557 /** The R0 virtual address of the two PAE page table. */
558 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559 } aPTs[1];
560} PGMMAPPING;
561/** Pointer to structure for tracking GC Mappings. */
562typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565/**
566 * Physical page access handler structure.
567 *
568 * This is used to keep track of physical address ranges
569 * which are being monitored in some kind of way.
570 */
571typedef struct PGMPHYSHANDLER
572{
573 AVLROGCPHYSNODECORE Core;
574 /** Access type. */
575 PGMPHYSHANDLERTYPE enmType;
576 /** Number of pages to update. */
577 uint32_t cPages;
578 /** Set if we have pages that have been aliased. */
579 uint32_t cAliasedPages;
580 /** Set if we have pages that have temporarily been disabled. */
581 uint32_t cTmpOffPages;
582 /** Pointer to R3 callback function. */
583 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
584 /** User argument for R3 handlers. */
585 R3PTRTYPE(void *) pvUserR3;
586 /** Pointer to R0 callback function. */
587 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
588 /** User argument for R0 handlers. */
589 R0PTRTYPE(void *) pvUserR0;
590 /** Pointer to RC callback function. */
591 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
592 /** User argument for RC handlers. */
593 RCPTRTYPE(void *) pvUserRC;
594 /** Description / Name. For easing debugging. */
595 R3PTRTYPE(const char *) pszDesc;
596#ifdef VBOX_WITH_STATISTICS
597 /** Profiling of this handler. */
598 STAMPROFILE Stat;
599#endif
600} PGMPHYSHANDLER;
601/** Pointer to a physical page access handler structure. */
602typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
603
604
605/**
606 * Cache node for the physical addresses covered by a virtual handler.
607 */
608typedef struct PGMPHYS2VIRTHANDLER
609{
610 /** Core node for the tree based on physical ranges. */
611 AVLROGCPHYSNODECORE Core;
612 /** Offset from this struct to the PGMVIRTHANDLER structure. */
613 int32_t offVirtHandler;
614 /** Offset of the next alias relative to this one.
615 * Bit 0 is used for indicating whether we're in the tree.
616 * Bit 1 is used for indicating that we're the head node.
617 */
618 int32_t offNextAlias;
619} PGMPHYS2VIRTHANDLER;
620/** Pointer to a phys to virtual handler structure. */
621typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
622
623/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
624 * node is in the tree. */
625#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
626/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
627 * node is in the head of an alias chain.
628 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
629#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
630/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
631#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
632
633
634/**
635 * Virtual page access handler structure.
636 *
637 * This is used to keep track of virtual address ranges
638 * which are being monitored in some kind of way.
639 */
640typedef struct PGMVIRTHANDLER
641{
642 /** Core node for the tree based on virtual ranges. */
643 AVLROGCPTRNODECORE Core;
644 /** Size of the range (in bytes). */
645 RTGCPTR cb;
646 /** Number of cache pages. */
647 uint32_t cPages;
648 /** Access type. */
649 PGMVIRTHANDLERTYPE enmType;
650 /** Pointer to the RC callback function. */
651 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
652#if HC_ARCH_BITS == 64
653 RTRCPTR padding;
654#endif
655 /** Pointer to the R3 callback function for invalidation. */
656 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
657 /** Pointer to the R3 callback function. */
658 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
659 /** Description / Name. For easing debugging. */
660 R3PTRTYPE(const char *) pszDesc;
661#ifdef VBOX_WITH_STATISTICS
662 /** Profiling of this handler. */
663 STAMPROFILE Stat;
664#endif
665 /** Array of cached physical addresses for the monitored ranged. */
666 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
667} PGMVIRTHANDLER;
668/** Pointer to a virtual page access handler structure. */
669typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
670
671
672/** @name Page type predicates.
673 * @{ */
674#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
675#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
676#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
677#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
678#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
679/** @} */
680
681
682/**
683 * A Physical Guest Page tracking structure.
684 *
685 * The format of this structure is complicated because we have to fit a lot
686 * of information into as few bits as possible. The format is also subject
687 * to change (there is one comming up soon). Which means that for we'll be
688 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
689 * accesses to the structure.
690 */
691typedef struct PGMPAGE
692{
693 /** The physical address and the Page ID. */
694 RTHCPHYS HCPhysAndPageID;
695 /** Combination of:
696 * - [0-7]: u2HandlerPhysStateY - the physical handler state
697 * (PGM_PAGE_HNDL_PHYS_STATE_*).
698 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
699 * (PGM_PAGE_HNDL_VIRT_STATE_*).
700 * - [10]: u1FTDirty - indicator of dirty page for fault tolerance tracking
701 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
702 * - [15]: fWrittenToY - flag indicating that a write monitored page was
703 * written to when set.
704 * - [11-13]: 3 unused bits.
705 * @remarks Warning! All accesses to the bits are hardcoded.
706 *
707 * @todo Change this to a union with both bitfields, u8 and u accessors.
708 * That'll help deal with some of the hardcoded accesses.
709 *
710 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
711 * will make it possible to turn some of the 16-bit accesses into
712 * 32-bit ones, which may be efficient (stalls).
713 */
714 RTUINT16U u16MiscY;
715 /** The page state.
716 * Only 3 bits are really needed for this. */
717 uint16_t uStateY : 3;
718 /** The page type (PGMPAGETYPE).
719 * Only 3 bits are really needed for this. */
720 uint16_t uTypeY : 3;
721 /** PTE index for usage tracking (page pool). */
722 uint16_t uPteIdx : 10;
723 /** Usage tracking (page pool). */
724 uint16_t u16TrackingY;
725 /** The number of read locks on this page. */
726 uint8_t cReadLocksY;
727 /** The number of write locks on this page. */
728 uint8_t cWriteLocksY;
729} PGMPAGE;
730AssertCompileSize(PGMPAGE, 16);
731/** Pointer to a physical guest page. */
732typedef PGMPAGE *PPGMPAGE;
733/** Pointer to a const physical guest page. */
734typedef const PGMPAGE *PCPGMPAGE;
735/** Pointer to a physical guest page pointer. */
736typedef PPGMPAGE *PPPGMPAGE;
737
738
739/**
740 * Clears the page structure.
741 * @param pPage Pointer to the physical guest page tracking structure.
742 */
743#define PGM_PAGE_CLEAR(pPage) \
744 do { \
745 (pPage)->HCPhysAndPageID = 0; \
746 (pPage)->uStateY = 0; \
747 (pPage)->uTypeY = 0; \
748 (pPage)->uPteIdx = 0; \
749 (pPage)->u16MiscY.u = 0; \
750 (pPage)->u16TrackingY = 0; \
751 (pPage)->cReadLocksY = 0; \
752 (pPage)->cWriteLocksY = 0; \
753 } while (0)
754
755/**
756 * Initializes the page structure.
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
760 do { \
761 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
762 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
763 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
764 (pPage)->uStateY = (_uState); \
765 (pPage)->uTypeY = (_uType); \
766 (pPage)->uPteIdx = 0; \
767 (pPage)->u16MiscY.u = 0; \
768 (pPage)->u16TrackingY = 0; \
769 (pPage)->cReadLocksY = 0; \
770 (pPage)->cWriteLocksY = 0; \
771 } while (0)
772
773/**
774 * Initializes the page structure of a ZERO page.
775 * @param pPage Pointer to the physical guest page tracking structure.
776 * @param pVM The VM handle (for getting the zero page address).
777 * @param uType The page type (PGMPAGETYPE).
778 */
779#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
780 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
781
782
783/** @name The Page state, PGMPAGE::uStateY.
784 * @{ */
785/** The zero page.
786 * This is a per-VM page that's never ever mapped writable. */
787#define PGM_PAGE_STATE_ZERO 0
788/** A allocated page.
789 * This is a per-VM page allocated from the page pool (or wherever
790 * we get MMIO2 pages from if the type is MMIO2).
791 */
792#define PGM_PAGE_STATE_ALLOCATED 1
793/** A allocated page that's being monitored for writes.
794 * The shadow page table mappings are read-only. When a write occurs, the
795 * fWrittenTo member is set, the page remapped as read-write and the state
796 * moved back to allocated. */
797#define PGM_PAGE_STATE_WRITE_MONITORED 2
798/** The page is shared, aka. copy-on-write.
799 * This is a page that's shared with other VMs. */
800#define PGM_PAGE_STATE_SHARED 3
801/** The page is ballooned, so no longer available for this VM. */
802#define PGM_PAGE_STATE_BALLOONED 4
803/** @} */
804
805
806/**
807 * Gets the page state.
808 * @returns page state (PGM_PAGE_STATE_*).
809 * @param pPage Pointer to the physical guest page tracking structure.
810 */
811#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
812
813/**
814 * Sets the page state.
815 * @param pPage Pointer to the physical guest page tracking structure.
816 * @param _uState The new page state.
817 */
818#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
819
820
821/**
822 * Gets the host physical address of the guest page.
823 * @returns host physical address (RTHCPHYS).
824 * @param pPage Pointer to the physical guest page tracking structure.
825 */
826#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
827
828/**
829 * Sets the host physical address of the guest page.
830 * @param pPage Pointer to the physical guest page tracking structure.
831 * @param _HCPhys The new host physical address.
832 */
833#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
834 do { \
835 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
836 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
837 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
838 | (SetHCPhysTmp << (28-12)); \
839 } while (0)
840
841/**
842 * Get the Page ID.
843 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
844 * @param pPage Pointer to the physical guest page tracking structure.
845 */
846#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
847
848/**
849 * Sets the Page ID.
850 * @param pPage Pointer to the physical guest page tracking structure.
851 */
852#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
853 do { \
854 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
855 | ((_idPage) & UINT32_C(0x0fffffff)); \
856 } while (0)
857
858/**
859 * Get the Chunk ID.
860 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
861 * @param pPage Pointer to the physical guest page tracking structure.
862 */
863#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
864
865/**
866 * Get the index of the page within the allocation chunk.
867 * @returns The page index.
868 * @param pPage Pointer to the physical guest page tracking structure.
869 */
870#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
871
872/**
873 * Gets the page type.
874 * @returns The page type.
875 * @param pPage Pointer to the physical guest page tracking structure.
876 */
877#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
878
879/**
880 * Sets the page type.
881 * @param pPage Pointer to the physical guest page tracking structure.
882 * @param _enmType The new page type (PGMPAGETYPE).
883 */
884#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
885
886/**
887 * Gets the page table index
888 * @returns The page table index.
889 * @param pPage Pointer to the physical guest page tracking structure.
890 */
891#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
892
893/**
894 * Sets the page table index
895 * @param pPage Pointer to the physical guest page tracking structure.
896 * @param iPte New page table index.
897 */
898#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
899
900/**
901 * Checks if the page is marked for MMIO.
902 * @returns true/false.
903 * @param pPage Pointer to the physical guest page tracking structure.
904 */
905#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
906
907/**
908 * Checks if the page is backed by the ZERO page.
909 * @returns true/false.
910 * @param pPage Pointer to the physical guest page tracking structure.
911 */
912#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
913
914/**
915 * Checks if the page is backed by a SHARED page.
916 * @returns true/false.
917 * @param pPage Pointer to the physical guest page tracking structure.
918 */
919#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
920
921/**
922 * Checks if the page is ballooned.
923 * @returns true/false.
924 * @param pPage Pointer to the physical guest page tracking structure.
925 */
926#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
927
928/**
929 * Marks the page as written to (for GMM change monitoring).
930 * @param pPage Pointer to the physical guest page tracking structure.
931 */
932#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
933
934/**
935 * Clears the written-to indicator.
936 * @param pPage Pointer to the physical guest page tracking structure.
937 */
938#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
939
940/**
941 * Checks if the page was marked as written-to.
942 * @returns true/false.
943 * @param pPage Pointer to the physical guest page tracking structure.
944 */
945#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
946
947/**
948 * Marks the page as dirty for FTM
949 * @param pPage Pointer to the physical guest page tracking structure.
950 */
951#define PGM_PAGE_SET_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x04); } while (0)
952
953/**
954 * Clears the FTM dirty indicator
955 * @param pPage Pointer to the physical guest page tracking structure.
956 */
957#define PGM_PAGE_CLEAR_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0xfb); } while (0)
958
959/**
960 * Checks if the page was marked as dirty for FTM
961 * @returns true/false.
962 * @param pPage Pointer to the physical guest page tracking structure.
963 */
964#define PGM_PAGE_IS_FT_DIRTY(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x04)) )
965
966
967/** @name PT usage values (PGMPAGE::u2PDEType).
968 *
969 * @{ */
970/** Either as a PT or PDE. */
971#define PGM_PAGE_PDE_TYPE_DONTCARE 0
972/** Must use a page table to map the range. */
973#define PGM_PAGE_PDE_TYPE_PT 1
974/** Can use a page directory entry to map the continous range. */
975#define PGM_PAGE_PDE_TYPE_PDE 2
976/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
977#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
978/** @} */
979
980/**
981 * Set the PDE type of the page
982 * @param pPage Pointer to the physical guest page tracking structure.
983 * @param uType PGM_PAGE_PDE_TYPE_*
984 */
985#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
986 do { \
987 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
988 | (((uType) & UINT8_C(0x03)) << 5); \
989 } while (0)
990
991/**
992 * Checks if the page was marked being part of a large page
993 * @returns true/false.
994 * @param pPage Pointer to the physical guest page tracking structure.
995 */
996#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
997
998/** Enabled optimized access handler tests.
999 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
1000 * layout. When enabled, the compiler should normally generate more compact
1001 * code.
1002 */
1003#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1004
1005/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1006 *
1007 * @remarks The values are assigned in order of priority, so we can calculate
1008 * the correct state for a page with different handlers installed.
1009 * @{ */
1010/** No handler installed. */
1011#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1012/** Monitoring is temporarily disabled. */
1013#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1014/** Write access is monitored. */
1015#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1016/** All access is monitored. */
1017#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1018/** @} */
1019
1020/**
1021 * Gets the physical access handler state of a page.
1022 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1023 * @param pPage Pointer to the physical guest page tracking structure.
1024 */
1025#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
1026 ( (pPage)->u16MiscY.au8[0] )
1027
1028/**
1029 * Sets the physical access handler state of a page.
1030 * @param pPage Pointer to the physical guest page tracking structure.
1031 * @param _uState The new state value.
1032 */
1033#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
1034 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
1035
1036/**
1037 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
1038 * @returns true/false
1039 * @param pPage Pointer to the physical guest page tracking structure.
1040 */
1041#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
1042 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1043
1044/**
1045 * Checks if the page has any active physical access handlers.
1046 * @returns true/false
1047 * @param pPage Pointer to the physical guest page tracking structure.
1048 */
1049#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
1050 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1051
1052
1053/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1054 *
1055 * @remarks The values are assigned in order of priority, so we can calculate
1056 * the correct state for a page with different handlers installed.
1057 * @{ */
1058/** No handler installed. */
1059#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1060/* 1 is reserved so the lineup is identical with the physical ones. */
1061/** Write access is monitored. */
1062#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1063/** All access is monitored. */
1064#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1065/** @} */
1066
1067/**
1068 * Gets the virtual access handler state of a page.
1069 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1070 * @param pPage Pointer to the physical guest page tracking structure.
1071 */
1072#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
1073
1074/**
1075 * Sets the virtual access handler state of a page.
1076 * @param pPage Pointer to the physical guest page tracking structure.
1077 * @param _uState The new state value.
1078 */
1079#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1080 do { \
1081 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1082 | ((_uState) & UINT8_C(0x03)); \
1083 } while (0)
1084
1085/**
1086 * Checks if the page has any virtual access handlers.
1087 * @returns true/false
1088 * @param pPage Pointer to the physical guest page tracking structure.
1089 */
1090#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1091 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1092
1093/**
1094 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1095 * virtual handlers.
1096 * @returns true/false
1097 * @param pPage Pointer to the physical guest page tracking structure.
1098 */
1099#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1100 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1101
1102
1103/**
1104 * Checks if the page has any access handlers, including temporarily disabled ones.
1105 * @returns true/false
1106 * @param pPage Pointer to the physical guest page tracking structure.
1107 */
1108#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1109# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1110 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1111#else
1112# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1113 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1114 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1115#endif
1116
1117/**
1118 * Checks if the page has any active access handlers.
1119 * @returns true/false
1120 * @param pPage Pointer to the physical guest page tracking structure.
1121 */
1122#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1123# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1124 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1125#else
1126# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1127 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1128 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1129#endif
1130
1131/**
1132 * Checks if the page has any active access handlers catching all accesses.
1133 * @returns true/false
1134 * @param pPage Pointer to the physical guest page tracking structure.
1135 */
1136#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1137# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1138 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1139 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1140#else
1141# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1142 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1143 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1144#endif
1145
1146
1147/** @def PGM_PAGE_GET_TRACKING
1148 * Gets the packed shadow page pool tracking data associated with a guest page.
1149 * @returns uint16_t containing the data.
1150 * @param pPage Pointer to the physical guest page tracking structure.
1151 */
1152#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1153
1154/** @def PGM_PAGE_SET_TRACKING
1155 * Sets the packed shadow page pool tracking data associated with a guest page.
1156 * @param pPage Pointer to the physical guest page tracking structure.
1157 * @param u16TrackingData The tracking data to store.
1158 */
1159#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1160 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1161
1162/** @def PGM_PAGE_GET_TD_CREFS
1163 * Gets the @a cRefs tracking data member.
1164 * @returns cRefs.
1165 * @param pPage Pointer to the physical guest page tracking structure.
1166 */
1167#define PGM_PAGE_GET_TD_CREFS(pPage) \
1168 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1169
1170/** @def PGM_PAGE_GET_TD_IDX
1171 * Gets the @a idx tracking data member.
1172 * @returns idx.
1173 * @param pPage Pointer to the physical guest page tracking structure.
1174 */
1175#define PGM_PAGE_GET_TD_IDX(pPage) \
1176 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1177
1178
1179/** Max number of locks on a page. */
1180#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1181
1182/** Get the read lock count.
1183 * @returns count.
1184 * @param pPage Pointer to the physical guest page tracking structure.
1185 */
1186#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1187
1188/** Get the write lock count.
1189 * @returns count.
1190 * @param pPage Pointer to the physical guest page tracking structure.
1191 */
1192#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1193
1194/** Decrement the read lock counter.
1195 * @param pPage Pointer to the physical guest page tracking structure.
1196 */
1197#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1198
1199/** Decrement the write lock counter.
1200 * @param pPage Pointer to the physical guest page tracking structure.
1201 */
1202#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1203
1204/** Increment the read lock counter.
1205 * @param pPage Pointer to the physical guest page tracking structure.
1206 */
1207#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1208
1209/** Increment the write lock counter.
1210 * @param pPage Pointer to the physical guest page tracking structure.
1211 */
1212#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1213
1214
1215#if 0
1216/** Enables sanity checking of write monitoring using CRC-32. */
1217# define PGMLIVESAVERAMPAGE_WITH_CRC32
1218#endif
1219
1220/**
1221 * Per page live save tracking data.
1222 */
1223typedef struct PGMLIVESAVERAMPAGE
1224{
1225 /** Number of times it has been dirtied. */
1226 uint32_t cDirtied : 24;
1227 /** Whether it is currently dirty. */
1228 uint32_t fDirty : 1;
1229 /** Ignore the page.
1230 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1231 * deal with these after pausing the VM and DevPCI have said it bit about
1232 * remappings. */
1233 uint32_t fIgnore : 1;
1234 /** Was a ZERO page last time around. */
1235 uint32_t fZero : 1;
1236 /** Was a SHARED page last time around. */
1237 uint32_t fShared : 1;
1238 /** Whether the page is/was write monitored in a previous pass. */
1239 uint32_t fWriteMonitored : 1;
1240 /** Whether the page is/was write monitored earlier in this pass. */
1241 uint32_t fWriteMonitoredJustNow : 1;
1242 /** Bits reserved for future use. */
1243 uint32_t u2Reserved : 2;
1244#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1245 /** CRC-32 for the page. This is for internal consistency checks. */
1246 uint32_t u32Crc;
1247#endif
1248} PGMLIVESAVERAMPAGE;
1249#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1250AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1251#else
1252AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1253#endif
1254/** Pointer to the per page live save tracking data. */
1255typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1256
1257/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1258#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1259
1260
1261/**
1262 * Ram range for GC Phys to HC Phys conversion.
1263 *
1264 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1265 * conversions too, but we'll let MM handle that for now.
1266 *
1267 * This structure is used by linked lists in both GC and HC.
1268 */
1269typedef struct PGMRAMRANGE
1270{
1271 /** Start of the range. Page aligned. */
1272 RTGCPHYS GCPhys;
1273 /** Size of the range. (Page aligned of course). */
1274 RTGCPHYS cb;
1275 /** Pointer to the next RAM range - for R3. */
1276 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1277 /** Pointer to the next RAM range - for R0. */
1278 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1279 /** Pointer to the next RAM range - for RC. */
1280 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1281 /** PGM_RAM_RANGE_FLAGS_* flags. */
1282 uint32_t fFlags;
1283 /** Last address in the range (inclusive). Page aligned (-1). */
1284 RTGCPHYS GCPhysLast;
1285 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1286 R3PTRTYPE(void *) pvR3;
1287 /** Live save per page tracking data. */
1288 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1289 /** The range description. */
1290 R3PTRTYPE(const char *) pszDesc;
1291 /** Pointer to self - R0 pointer. */
1292 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1293 /** Pointer to self - RC pointer. */
1294 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1295 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1296 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1297 /** Array of physical guest page tracking structures. */
1298 PGMPAGE aPages[1];
1299} PGMRAMRANGE;
1300/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1301typedef PGMRAMRANGE *PPGMRAMRANGE;
1302
1303/** @name PGMRAMRANGE::fFlags
1304 * @{ */
1305/** The RAM range is floating around as an independent guest mapping. */
1306#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1307/** Ad hoc RAM range for an ROM mapping. */
1308#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1309/** Ad hoc RAM range for an MMIO mapping. */
1310#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1311/** Ad hoc RAM range for an MMIO2 mapping. */
1312#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1313/** @} */
1314
1315/** Tests if a RAM range is an ad hoc one or not.
1316 * @returns true/false.
1317 * @param pRam The RAM range.
1318 */
1319#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1320 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1321
1322
1323/**
1324 * Per page tracking structure for ROM image.
1325 *
1326 * A ROM image may have a shadow page, in which case we may have two pages
1327 * backing it. This structure contains the PGMPAGE for both while
1328 * PGMRAMRANGE have a copy of the active one. It is important that these
1329 * aren't out of sync in any regard other than page pool tracking data.
1330 */
1331typedef struct PGMROMPAGE
1332{
1333 /** The page structure for the virgin ROM page. */
1334 PGMPAGE Virgin;
1335 /** The page structure for the shadow RAM page. */
1336 PGMPAGE Shadow;
1337 /** The current protection setting. */
1338 PGMROMPROT enmProt;
1339 /** Live save status information. Makes use of unused alignment space. */
1340 struct
1341 {
1342 /** The previous protection value. */
1343 uint8_t u8Prot;
1344 /** Written to flag set by the handler. */
1345 bool fWrittenTo;
1346 /** Whether the shadow page is dirty or not. */
1347 bool fDirty;
1348 /** Whether it was dirtied in the recently. */
1349 bool fDirtiedRecently;
1350 } LiveSave;
1351} PGMROMPAGE;
1352AssertCompileSizeAlignment(PGMROMPAGE, 8);
1353/** Pointer to a ROM page tracking structure. */
1354typedef PGMROMPAGE *PPGMROMPAGE;
1355
1356
1357/**
1358 * A registered ROM image.
1359 *
1360 * This is needed to keep track of ROM image since they generally intrude
1361 * into a PGMRAMRANGE. It also keeps track of additional info like the
1362 * two page sets (read-only virgin and read-write shadow), the current
1363 * state of each page.
1364 *
1365 * Because access handlers cannot easily be executed in a different
1366 * context, the ROM ranges needs to be accessible and in all contexts.
1367 */
1368typedef struct PGMROMRANGE
1369{
1370 /** Pointer to the next range - R3. */
1371 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1372 /** Pointer to the next range - R0. */
1373 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1374 /** Pointer to the next range - RC. */
1375 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1376 /** Pointer alignment */
1377 RTRCPTR RCPtrAlignment;
1378 /** Address of the range. */
1379 RTGCPHYS GCPhys;
1380 /** Address of the last byte in the range. */
1381 RTGCPHYS GCPhysLast;
1382 /** Size of the range. */
1383 RTGCPHYS cb;
1384 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1385 uint32_t fFlags;
1386 /** The saved state range ID. */
1387 uint8_t idSavedState;
1388 /** Alignment padding. */
1389 uint8_t au8Alignment[3];
1390 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1391 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1392 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1393 * This is used for strictness checks. */
1394 R3PTRTYPE(const void *) pvOriginal;
1395 /** The ROM description. */
1396 R3PTRTYPE(const char *) pszDesc;
1397 /** The per page tracking structures. */
1398 PGMROMPAGE aPages[1];
1399} PGMROMRANGE;
1400/** Pointer to a ROM range. */
1401typedef PGMROMRANGE *PPGMROMRANGE;
1402
1403
1404/**
1405 * Live save per page data for an MMIO2 page.
1406 *
1407 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1408 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1409 * CRC-32 for detecting changes as well as special handling of zero pages. This
1410 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1411 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1412 * because of speed (2.5x and 6x slower).)
1413 *
1414 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1415 * save but normally is disabled. Since we can write monitore guest
1416 * accesses on our own, we only need this for host accesses. Shouldn't be
1417 * too difficult for DevVGA, VMMDev might be doable, the planned
1418 * networking fun will be fun since it involves ring-0.
1419 */
1420typedef struct PGMLIVESAVEMMIO2PAGE
1421{
1422 /** Set if the page is considered dirty. */
1423 bool fDirty;
1424 /** The number of scans this page has remained unchanged for.
1425 * Only updated for dirty pages. */
1426 uint8_t cUnchangedScans;
1427 /** Whether this page was zero at the last scan. */
1428 bool fZero;
1429 /** Alignment padding. */
1430 bool fReserved;
1431 /** CRC-32 for the first half of the page.
1432 * This is used together with u32CrcH2 to quickly detect changes in the page
1433 * during the non-final passes. */
1434 uint32_t u32CrcH1;
1435 /** CRC-32 for the second half of the page. */
1436 uint32_t u32CrcH2;
1437 /** SHA-1 for the saved page.
1438 * This is used in the final pass to skip pages without changes. */
1439 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1440} PGMLIVESAVEMMIO2PAGE;
1441/** Pointer to a live save status data for an MMIO2 page. */
1442typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1443
1444/**
1445 * A registered MMIO2 (= Device RAM) range.
1446 *
1447 * There are a few reason why we need to keep track of these
1448 * registrations. One of them is the deregistration & cleanup stuff,
1449 * while another is that the PGMRAMRANGE associated with such a region may
1450 * have to be removed from the ram range list.
1451 *
1452 * Overlapping with a RAM range has to be 100% or none at all. The pages
1453 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1454 * will be raised if a partial overlap or an overlap of ROM pages is
1455 * encountered. On an overlap we will free all the existing RAM pages and
1456 * put in the ram range pages instead.
1457 */
1458typedef struct PGMMMIO2RANGE
1459{
1460 /** The owner of the range. (a device) */
1461 PPDMDEVINSR3 pDevInsR3;
1462 /** Pointer to the ring-3 mapping of the allocation. */
1463 RTR3PTR pvR3;
1464 /** Pointer to the next range - R3. */
1465 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1466 /** Whether it's mapped or not. */
1467 bool fMapped;
1468 /** Whether it's overlapping or not. */
1469 bool fOverlapping;
1470 /** The PCI region number.
1471 * @remarks This ASSUMES that nobody will ever really need to have multiple
1472 * PCI devices with matching MMIO region numbers on a single device. */
1473 uint8_t iRegion;
1474 /** The saved state range ID. */
1475 uint8_t idSavedState;
1476 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1477 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1478 /** Live save per page tracking data. */
1479 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1480 /** The associated RAM range. */
1481 PGMRAMRANGE RamRange;
1482} PGMMMIO2RANGE;
1483/** Pointer to a MMIO2 range. */
1484typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1485
1486
1487
1488
1489/**
1490 * PGMPhysRead/Write cache entry
1491 */
1492typedef struct PGMPHYSCACHEENTRY
1493{
1494 /** R3 pointer to physical page. */
1495 R3PTRTYPE(uint8_t *) pbR3;
1496 /** GC Physical address for cache entry */
1497 RTGCPHYS GCPhys;
1498#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1499 RTGCPHYS u32Padding0; /**< alignment padding. */
1500#endif
1501} PGMPHYSCACHEENTRY;
1502
1503/**
1504 * PGMPhysRead/Write cache to reduce REM memory access overhead
1505 */
1506typedef struct PGMPHYSCACHE
1507{
1508 /** Bitmap of valid cache entries */
1509 uint64_t aEntries;
1510 /** Cache entries */
1511 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1512} PGMPHYSCACHE;
1513
1514
1515/** Pointer to an allocation chunk ring-3 mapping. */
1516typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1517/** Pointer to an allocation chunk ring-3 mapping pointer. */
1518typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1519
1520/**
1521 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1522 *
1523 * The primary tree (Core) uses the chunk id as key.
1524 */
1525typedef struct PGMCHUNKR3MAP
1526{
1527 /** The key is the chunk id. */
1528 AVLU32NODECORE Core;
1529 /** The current age thingy. */
1530 uint32_t iAge;
1531 /** The current reference count. */
1532 uint32_t volatile cRefs;
1533 /** The current permanent reference count. */
1534 uint32_t volatile cPermRefs;
1535 /** The mapping address. */
1536 void *pv;
1537} PGMCHUNKR3MAP;
1538
1539/**
1540 * Allocation chunk ring-3 mapping TLB entry.
1541 */
1542typedef struct PGMCHUNKR3MAPTLBE
1543{
1544 /** The chunk id. */
1545 uint32_t volatile idChunk;
1546#if HC_ARCH_BITS == 64
1547 uint32_t u32Padding; /**< alignment padding. */
1548#endif
1549 /** The chunk map. */
1550#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1551 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1552#else
1553 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1554#endif
1555} PGMCHUNKR3MAPTLBE;
1556/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1557typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1558
1559/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1560 * @remark Must be a power of two value. */
1561#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1562
1563/**
1564 * Allocation chunk ring-3 mapping TLB.
1565 *
1566 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1567 * At first glance this might look kinda odd since AVL trees are
1568 * supposed to give the most optimial lookup times of all trees
1569 * due to their balancing. However, take a tree with 1023 nodes
1570 * in it, that's 10 levels, meaning that most searches has to go
1571 * down 9 levels before they find what they want. This isn't fast
1572 * compared to a TLB hit. There is the factor of cache misses,
1573 * and of course the problem with trees and branch prediction.
1574 * This is why we use TLBs in front of most of the trees.
1575 *
1576 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1577 * difficult when we switch to the new inlined AVL trees (from kStuff).
1578 */
1579typedef struct PGMCHUNKR3MAPTLB
1580{
1581 /** The TLB entries. */
1582 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1583} PGMCHUNKR3MAPTLB;
1584
1585/**
1586 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1587 * @returns Chunk TLB index.
1588 * @param idChunk The Chunk ID.
1589 */
1590#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1591
1592
1593/**
1594 * Ring-3 guest page mapping TLB entry.
1595 * @remarks used in ring-0 as well at the moment.
1596 */
1597typedef struct PGMPAGER3MAPTLBE
1598{
1599 /** Address of the page. */
1600 RTGCPHYS volatile GCPhys;
1601 /** The guest page. */
1602#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1603 R3PTRTYPE(PPGMPAGE) volatile pPage;
1604#else
1605 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1606#endif
1607 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1608#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1609 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1610#else
1611 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1612#endif
1613 /** The address */
1614#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1615 R3PTRTYPE(void *) volatile pv;
1616#else
1617 R3R0PTRTYPE(void *) volatile pv;
1618#endif
1619#if HC_ARCH_BITS == 32
1620 uint32_t u32Padding; /**< alignment padding. */
1621#endif
1622} PGMPAGER3MAPTLBE;
1623/** Pointer to an entry in the HC physical TLB. */
1624typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1625
1626
1627/** The number of entries in the ring-3 guest page mapping TLB.
1628 * @remarks The value must be a power of two. */
1629#define PGM_PAGER3MAPTLB_ENTRIES 256
1630
1631/**
1632 * Ring-3 guest page mapping TLB.
1633 * @remarks used in ring-0 as well at the moment.
1634 */
1635typedef struct PGMPAGER3MAPTLB
1636{
1637 /** The TLB entries. */
1638 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1639} PGMPAGER3MAPTLB;
1640/** Pointer to the ring-3 guest page mapping TLB. */
1641typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1642
1643/**
1644 * Calculates the index of the TLB entry for the specified guest page.
1645 * @returns Physical TLB index.
1646 * @param GCPhys The guest physical address.
1647 */
1648#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1649
1650
1651/**
1652 * Raw-mode context dynamic mapping cache entry.
1653 *
1654 * Because of raw-mode context being reloctable and all relocations are applied
1655 * in ring-3, this has to be defined here and be RC specfic.
1656 *
1657 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1658 */
1659typedef struct PGMRCDYNMAPENTRY
1660{
1661 /** The physical address of the currently mapped page.
1662 * This is duplicate for three reasons: cache locality, cache policy of the PT
1663 * mappings and sanity checks. */
1664 RTHCPHYS HCPhys;
1665 /** Pointer to the page. */
1666 RTRCPTR pvPage;
1667 /** The number of references. */
1668 int32_t volatile cRefs;
1669 /** PTE pointer union. */
1670 union PGMRCDYNMAPENTRY_PPTE
1671 {
1672 /** PTE pointer, 32-bit legacy version. */
1673 RCPTRTYPE(PX86PTE) pLegacy;
1674 /** PTE pointer, PAE version. */
1675 RCPTRTYPE(PX86PTEPAE) pPae;
1676 /** PTE pointer, the void version. */
1677 RTRCPTR pv;
1678 } uPte;
1679 /** Alignment padding. */
1680 RTRCPTR RCPtrAlignment;
1681} PGMRCDYNMAPENTRY;
1682/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1683typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1684
1685
1686/**
1687 * Dynamic mapping cache for the raw-mode context.
1688 *
1689 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1690 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1691 * so that we can perform relocations from PGMR3Relocate. This has the
1692 * consequence that we must have separate ring-0 and raw-mode context versions
1693 * of this struct even if they share the basic elements.
1694 *
1695 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1696 */
1697typedef struct PGMRCDYNMAP
1698{
1699 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1700 uint32_t u32Magic;
1701 /** Array for tracking and managing the pages. */
1702 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1703 /** The cache size given as a number of pages. */
1704 uint32_t cPages;
1705 /** Whether it's 32-bit legacy or PAE/AMD64 paging mode. */
1706 bool fLegacyMode;
1707 /** The current load.
1708 * This does not include guard pages. */
1709 uint32_t cLoad;
1710 /** The max load ever.
1711 * This is maintained to get trigger adding of more mapping space. */
1712 uint32_t cMaxLoad;
1713 /** The number of guard pages. */
1714 uint32_t cGuardPages;
1715 /** The number of users (protected by hInitLock). */
1716 uint32_t cUsers;
1717} PGMRCDYNMAP;
1718/** Pointer to the dynamic cache for the raw-mode context. */
1719typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1720
1721
1722/**
1723 * Mapping cache usage set entry.
1724 *
1725 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1726 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1727 * cache. If it's extended to include ring-3, well, then something
1728 * will have be changed here...
1729 */
1730typedef struct PGMMAPSETENTRY
1731{
1732 /** Pointer to the page. */
1733#ifndef IN_RC
1734 RTR0PTR pvPage;
1735#else
1736 RTRCPTR pvPage;
1737# if HC_ARCH_BITS == 64
1738 uint32_t u32Alignment2;
1739# endif
1740#endif
1741 /** The mapping cache index. */
1742 uint16_t iPage;
1743 /** The number of references.
1744 * The max is UINT16_MAX - 1. */
1745 uint16_t cRefs;
1746 /** The number inlined references.
1747 * The max is UINT16_MAX - 1. */
1748 uint16_t cInlinedRefs;
1749 /** Unreferences. */
1750 uint16_t cUnrefs;
1751
1752#if HC_ARCH_BITS == 32
1753 uint32_t u32Alignment1;
1754#endif
1755 /** The physical address for this entry. */
1756 RTHCPHYS HCPhys;
1757} PGMMAPSETENTRY;
1758AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1759AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1760/** Pointer to a mapping cache usage set entry. */
1761typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1762
1763/**
1764 * Mapping cache usage set.
1765 *
1766 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1767 * done during exits / traps. The set is
1768 */
1769typedef struct PGMMAPSET
1770{
1771 /** The number of occupied entries.
1772 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1773 * dynamic mappings. */
1774 uint32_t cEntries;
1775 /** The start of the current subset.
1776 * This is UINT32_MAX if no subset is currently open. */
1777 uint32_t iSubset;
1778 /** The index of the current CPU, only valid if the set is open. */
1779 int32_t iCpu;
1780 uint32_t alignment;
1781 /** The entries. */
1782 PGMMAPSETENTRY aEntries[64];
1783 /** HCPhys -> iEntry fast lookup table.
1784 * Use PGMMAPSET_HASH for hashing.
1785 * The entries may or may not be valid, check against cEntries. */
1786 uint8_t aiHashTable[128];
1787} PGMMAPSET;
1788AssertCompileSizeAlignment(PGMMAPSET, 8);
1789/** Pointer to the mapping cache set. */
1790typedef PGMMAPSET *PPGMMAPSET;
1791
1792/** PGMMAPSET::cEntries value for a closed set. */
1793#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1794
1795/** Hash function for aiHashTable. */
1796#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1797
1798
1799/** @name Context neutrual page mapper TLB.
1800 *
1801 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1802 * code is writting in a kind of context neutrual way. Time will show whether
1803 * this actually makes sense or not...
1804 *
1805 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1806 * context ends up using a global mapping cache on some platforms
1807 * (darwin).
1808 *
1809 * @{ */
1810/** @typedef PPGMPAGEMAPTLB
1811 * The page mapper TLB pointer type for the current context. */
1812/** @typedef PPGMPAGEMAPTLB
1813 * The page mapper TLB entry pointer type for the current context. */
1814/** @typedef PPGMPAGEMAPTLB
1815 * The page mapper TLB entry pointer pointer type for the current context. */
1816/** @def PGM_PAGEMAPTLB_ENTRIES
1817 * The number of TLB entries in the page mapper TLB for the current context. */
1818/** @def PGM_PAGEMAPTLB_IDX
1819 * Calculate the TLB index for a guest physical address.
1820 * @returns The TLB index.
1821 * @param GCPhys The guest physical address. */
1822/** @typedef PPGMPAGEMAP
1823 * Pointer to a page mapper unit for current context. */
1824/** @typedef PPPGMPAGEMAP
1825 * Pointer to a page mapper unit pointer for current context. */
1826#ifdef IN_RC
1827// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1828// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1829// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1830# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1831# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1832 typedef void * PPGMPAGEMAP;
1833 typedef void ** PPPGMPAGEMAP;
1834//#elif IN_RING0
1835// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1836// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1837// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1838//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1839//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1840// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1841// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1842#else
1843 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1844 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1845 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1846# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1847# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1848 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1849 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1850#endif
1851/** @} */
1852
1853
1854/** @name PGM Pool Indexes.
1855 * Aka. the unique shadow page identifier.
1856 * @{ */
1857/** NIL page pool IDX. */
1858#define NIL_PGMPOOL_IDX 0
1859/** The first normal index. */
1860#define PGMPOOL_IDX_FIRST_SPECIAL 1
1861/** Page directory (32-bit root). */
1862#define PGMPOOL_IDX_PD 1
1863/** Page Directory Pointer Table (PAE root). */
1864#define PGMPOOL_IDX_PDPT 2
1865/** AMD64 CR3 level index.*/
1866#define PGMPOOL_IDX_AMD64_CR3 3
1867/** Nested paging root.*/
1868#define PGMPOOL_IDX_NESTED_ROOT 4
1869/** The first normal index. */
1870#define PGMPOOL_IDX_FIRST 5
1871/** The last valid index. (inclusive, 14 bits) */
1872#define PGMPOOL_IDX_LAST 0x3fff
1873/** @} */
1874
1875/** The NIL index for the parent chain. */
1876#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1877#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1878
1879/**
1880 * Node in the chain linking a shadowed page to it's parent (user).
1881 */
1882#pragma pack(1)
1883typedef struct PGMPOOLUSER
1884{
1885 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1886 uint16_t iNext;
1887 /** The user page index. */
1888 uint16_t iUser;
1889 /** Index into the user table. */
1890 uint32_t iUserTable;
1891} PGMPOOLUSER, *PPGMPOOLUSER;
1892typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1893#pragma pack()
1894
1895
1896/** The NIL index for the phys ext chain. */
1897#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1898/** The NIL pte index for a phys ext chain slot. */
1899#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1900
1901/**
1902 * Node in the chain of physical cross reference extents.
1903 * @todo Calling this an 'extent' is not quite right, find a better name.
1904 * @todo find out the optimal size of the aidx array
1905 */
1906#pragma pack(1)
1907typedef struct PGMPOOLPHYSEXT
1908{
1909 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1910 uint16_t iNext;
1911 /** Alignment. */
1912 uint16_t u16Align;
1913 /** The user page index. */
1914 uint16_t aidx[3];
1915 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1916 uint16_t apte[3];
1917} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1918typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1919#pragma pack()
1920
1921
1922/**
1923 * The kind of page that's being shadowed.
1924 */
1925typedef enum PGMPOOLKIND
1926{
1927 /** The virtual invalid 0 entry. */
1928 PGMPOOLKIND_INVALID = 0,
1929 /** The entry is free (=unused). */
1930 PGMPOOLKIND_FREE,
1931
1932 /** Shw: 32-bit page table; Gst: no paging */
1933 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1934 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1935 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1936 /** Shw: 32-bit page table; Gst: 4MB page. */
1937 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1938 /** Shw: PAE page table; Gst: no paging */
1939 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1940 /** Shw: PAE page table; Gst: 32-bit page table. */
1941 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1942 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1943 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1944 /** Shw: PAE page table; Gst: PAE page table. */
1945 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1946 /** Shw: PAE page table; Gst: 2MB page. */
1947 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1948
1949 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1950 PGMPOOLKIND_32BIT_PD,
1951 /** Shw: 32-bit page directory. Gst: no paging. */
1952 PGMPOOLKIND_32BIT_PD_PHYS,
1953 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1954 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1955 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1956 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1957 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1958 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1959 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1960 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1961 /** Shw: PAE page directory; Gst: PAE page directory. */
1962 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1963 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1964 PGMPOOLKIND_PAE_PD_PHYS,
1965
1966 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1967 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1968 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1969 PGMPOOLKIND_PAE_PDPT,
1970 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1971 PGMPOOLKIND_PAE_PDPT_PHYS,
1972
1973 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1974 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1975 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1976 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1977 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1978 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1979 /** Shw: 64-bit page directory table; Gst: no paging */
1980 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1981
1982 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1983 PGMPOOLKIND_64BIT_PML4,
1984
1985 /** Shw: EPT page directory pointer table; Gst: no paging */
1986 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1987 /** Shw: EPT page directory table; Gst: no paging */
1988 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1989 /** Shw: EPT page table; Gst: no paging */
1990 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1991
1992 /** Shw: Root Nested paging table. */
1993 PGMPOOLKIND_ROOT_NESTED,
1994
1995 /** The last valid entry. */
1996 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1997} PGMPOOLKIND;
1998
1999/**
2000 * The access attributes of the page; only applies to big pages.
2001 */
2002typedef enum
2003{
2004 PGMPOOLACCESS_DONTCARE = 0,
2005 PGMPOOLACCESS_USER_RW,
2006 PGMPOOLACCESS_USER_R,
2007 PGMPOOLACCESS_USER_RW_NX,
2008 PGMPOOLACCESS_USER_R_NX,
2009 PGMPOOLACCESS_SUPERVISOR_RW,
2010 PGMPOOLACCESS_SUPERVISOR_R,
2011 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2012 PGMPOOLACCESS_SUPERVISOR_R_NX
2013} PGMPOOLACCESS;
2014
2015/**
2016 * The tracking data for a page in the pool.
2017 */
2018typedef struct PGMPOOLPAGE
2019{
2020 /** AVL node code with the (R3) physical address of this page. */
2021 AVLOHCPHYSNODECORE Core;
2022 /** Pointer to the R3 mapping of the page. */
2023#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2024 R3PTRTYPE(void *) pvPageR3;
2025#else
2026 R3R0PTRTYPE(void *) pvPageR3;
2027#endif
2028 /** The guest physical address. */
2029#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2030 uint32_t Alignment0;
2031#endif
2032 RTGCPHYS GCPhys;
2033
2034 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2035 RTGCPTR pvLastAccessHandlerRip;
2036 RTGCPTR pvLastAccessHandlerFault;
2037 uint64_t cLastAccessHandlerCount;
2038
2039 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2040 uint8_t enmKind;
2041 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2042 uint8_t enmAccess;
2043 /** The index of this page. */
2044 uint16_t idx;
2045 /** The next entry in the list this page currently resides in.
2046 * It's either in the free list or in the GCPhys hash. */
2047 uint16_t iNext;
2048 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2049 uint16_t iUserHead;
2050 /** The number of present entries. */
2051 uint16_t cPresent;
2052 /** The first entry in the table which is present. */
2053 uint16_t iFirstPresent;
2054 /** The number of modifications to the monitored page. */
2055 uint16_t cModifications;
2056 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2057 uint16_t iModifiedNext;
2058 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2059 uint16_t iModifiedPrev;
2060 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2061 uint16_t iMonitoredNext;
2062 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2063 uint16_t iMonitoredPrev;
2064 /** The next page in the age list. */
2065 uint16_t iAgeNext;
2066 /** The previous page in the age list. */
2067 uint16_t iAgePrev;
2068 /** Used to indicate that the page is zeroed. */
2069 bool fZeroed;
2070 /** Used to indicate that a PT has non-global entries. */
2071 bool fSeenNonGlobal;
2072 /** Used to indicate that we're monitoring writes to the guest page. */
2073 bool fMonitored;
2074 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2075 * (All pages are in the age list.) */
2076 bool fCached;
2077 /** This is used by the R3 access handlers when invoked by an async thread.
2078 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2079 bool volatile fReusedFlushPending;
2080 /** Used to mark the page as dirty (write monitoring is temporarily
2081 * off). */
2082 bool fDirty;
2083
2084 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2085 uint32_t cLocked;
2086 uint32_t idxDirty;
2087 RTGCPTR pvDirtyFault;
2088} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
2089/** Pointer to a const pool page. */
2090typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2091
2092
2093/** The hash table size. */
2094# define PGMPOOL_HASH_SIZE 0x40
2095/** The hash function. */
2096# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2097
2098
2099/**
2100 * The shadow page pool instance data.
2101 *
2102 * It's all one big allocation made at init time, except for the
2103 * pages that is. The user nodes follows immediatly after the
2104 * page structures.
2105 */
2106typedef struct PGMPOOL
2107{
2108 /** The VM handle - R3 Ptr. */
2109 PVMR3 pVMR3;
2110 /** The VM handle - R0 Ptr. */
2111 PVMR0 pVMR0;
2112 /** The VM handle - RC Ptr. */
2113 PVMRC pVMRC;
2114 /** The max pool size. This includes the special IDs. */
2115 uint16_t cMaxPages;
2116 /** The current pool size. */
2117 uint16_t cCurPages;
2118 /** The head of the free page list. */
2119 uint16_t iFreeHead;
2120 /* Padding. */
2121 uint16_t u16Padding;
2122 /** Head of the chain of free user nodes. */
2123 uint16_t iUserFreeHead;
2124 /** The number of user nodes we've allocated. */
2125 uint16_t cMaxUsers;
2126 /** The number of present page table entries in the entire pool. */
2127 uint32_t cPresent;
2128 /** Pointer to the array of user nodes - RC pointer. */
2129 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2130 /** Pointer to the array of user nodes - R3 pointer. */
2131 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2132 /** Pointer to the array of user nodes - R0 pointer. */
2133 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2134 /** Head of the chain of free phys ext nodes. */
2135 uint16_t iPhysExtFreeHead;
2136 /** The number of user nodes we've allocated. */
2137 uint16_t cMaxPhysExts;
2138 /** Pointer to the array of physical xref extent - RC pointer. */
2139 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2140 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2141 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2142 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2143 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2144 /** Hash table for GCPhys addresses. */
2145 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2146 /** The head of the age list. */
2147 uint16_t iAgeHead;
2148 /** The tail of the age list. */
2149 uint16_t iAgeTail;
2150 /** Set if the cache is enabled. */
2151 bool fCacheEnabled;
2152 /** Alignment padding. */
2153 bool afPadding1[3];
2154 /** Head of the list of modified pages. */
2155 uint16_t iModifiedHead;
2156 /** The current number of modified pages. */
2157 uint16_t cModifiedPages;
2158 /** Access handler, RC. */
2159 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2160 /** Access handler, R0. */
2161 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2162 /** Access handler, R3. */
2163 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2164 /** The access handler description (R3 ptr). */
2165 R3PTRTYPE(const char *) pszAccessHandler;
2166# if HC_ARCH_BITS == 32
2167 /** Alignment padding. */
2168 uint32_t u32Padding2;
2169# endif
2170 /* Next available slot. */
2171 uint32_t idxFreeDirtyPage;
2172 /* Number of active dirty pages. */
2173 uint32_t cDirtyPages;
2174 /* Array of current dirty pgm pool page indices. */
2175 uint16_t aIdxDirtyPages[16];
2176 uint64_t aDirtyPages[16][512];
2177 /** The number of pages currently in use. */
2178 uint16_t cUsedPages;
2179#ifdef VBOX_WITH_STATISTICS
2180 /** The high water mark for cUsedPages. */
2181 uint16_t cUsedPagesHigh;
2182 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
2183 /** Profiling pgmPoolAlloc(). */
2184 STAMPROFILEADV StatAlloc;
2185 /** Profiling pgmR3PoolClearDoIt(). */
2186 STAMPROFILE StatClearAll;
2187 /** Profiling pgmR3PoolReset(). */
2188 STAMPROFILE StatR3Reset;
2189 /** Profiling pgmPoolFlushPage(). */
2190 STAMPROFILE StatFlushPage;
2191 /** Profiling pgmPoolFree(). */
2192 STAMPROFILE StatFree;
2193 /** Counting explicit flushes by PGMPoolFlushPage(). */
2194 STAMCOUNTER StatForceFlushPage;
2195 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2196 STAMCOUNTER StatForceFlushDirtyPage;
2197 /** Counting flushes for reused pages. */
2198 STAMCOUNTER StatForceFlushReused;
2199 /** Profiling time spent zeroing pages. */
2200 STAMPROFILE StatZeroPage;
2201 /** Profiling of pgmPoolTrackDeref. */
2202 STAMPROFILE StatTrackDeref;
2203 /** Profiling pgmTrackFlushGCPhysPT. */
2204 STAMPROFILE StatTrackFlushGCPhysPT;
2205 /** Profiling pgmTrackFlushGCPhysPTs. */
2206 STAMPROFILE StatTrackFlushGCPhysPTs;
2207 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2208 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2209 /** Number of times we've been out of user records. */
2210 STAMCOUNTER StatTrackFreeUpOneUser;
2211 /** Nr of flushed entries. */
2212 STAMCOUNTER StatTrackFlushEntry;
2213 /** Nr of updated entries. */
2214 STAMCOUNTER StatTrackFlushEntryKeep;
2215 /** Profiling deref activity related tracking GC physical pages. */
2216 STAMPROFILE StatTrackDerefGCPhys;
2217 /** Number of linear searches for a HCPhys in the ram ranges. */
2218 STAMCOUNTER StatTrackLinearRamSearches;
2219 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2220 STAMCOUNTER StamTrackPhysExtAllocFailures;
2221 /** Profiling the RC/R0 access handler. */
2222 STAMPROFILE StatMonitorRZ;
2223 /** Times we've failed interpreting the instruction. */
2224 STAMCOUNTER StatMonitorRZEmulateInstr;
2225 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2226 STAMPROFILE StatMonitorRZFlushPage;
2227 /* Times we've detected a page table reinit. */
2228 STAMCOUNTER StatMonitorRZFlushReinit;
2229 /** Counting flushes for pages that are modified too often. */
2230 STAMCOUNTER StatMonitorRZFlushModOverflow;
2231 /** Times we've detected fork(). */
2232 STAMCOUNTER StatMonitorRZFork;
2233 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2234 STAMPROFILE StatMonitorRZHandled;
2235 /** Times we've failed interpreting a patch code instruction. */
2236 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2237 /** Times we've failed interpreting a patch code instruction during flushing. */
2238 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2239 /** The number of times we've seen rep prefixes we can't handle. */
2240 STAMCOUNTER StatMonitorRZRepPrefix;
2241 /** Profiling the REP STOSD cases we've handled. */
2242 STAMPROFILE StatMonitorRZRepStosd;
2243 /** Nr of handled PT faults. */
2244 STAMCOUNTER StatMonitorRZFaultPT;
2245 /** Nr of handled PD faults. */
2246 STAMCOUNTER StatMonitorRZFaultPD;
2247 /** Nr of handled PDPT faults. */
2248 STAMCOUNTER StatMonitorRZFaultPDPT;
2249 /** Nr of handled PML4 faults. */
2250 STAMCOUNTER StatMonitorRZFaultPML4;
2251
2252 /** Profiling the R3 access handler. */
2253 STAMPROFILE StatMonitorR3;
2254 /** Times we've failed interpreting the instruction. */
2255 STAMCOUNTER StatMonitorR3EmulateInstr;
2256 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2257 STAMPROFILE StatMonitorR3FlushPage;
2258 /* Times we've detected a page table reinit. */
2259 STAMCOUNTER StatMonitorR3FlushReinit;
2260 /** Counting flushes for pages that are modified too often. */
2261 STAMCOUNTER StatMonitorR3FlushModOverflow;
2262 /** Times we've detected fork(). */
2263 STAMCOUNTER StatMonitorR3Fork;
2264 /** Profiling the R3 access we've handled (except REP STOSD). */
2265 STAMPROFILE StatMonitorR3Handled;
2266 /** The number of times we've seen rep prefixes we can't handle. */
2267 STAMCOUNTER StatMonitorR3RepPrefix;
2268 /** Profiling the REP STOSD cases we've handled. */
2269 STAMPROFILE StatMonitorR3RepStosd;
2270 /** Nr of handled PT faults. */
2271 STAMCOUNTER StatMonitorR3FaultPT;
2272 /** Nr of handled PD faults. */
2273 STAMCOUNTER StatMonitorR3FaultPD;
2274 /** Nr of handled PDPT faults. */
2275 STAMCOUNTER StatMonitorR3FaultPDPT;
2276 /** Nr of handled PML4 faults. */
2277 STAMCOUNTER StatMonitorR3FaultPML4;
2278 /** The number of times we're called in an async thread an need to flush. */
2279 STAMCOUNTER StatMonitorR3Async;
2280 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2281 STAMCOUNTER StatResetDirtyPages;
2282 /** Times we've called pgmPoolAddDirtyPage. */
2283 STAMCOUNTER StatDirtyPage;
2284 /** Times we've had to flush duplicates for dirty page management. */
2285 STAMCOUNTER StatDirtyPageDupFlush;
2286 /** Times we've had to flush because of overflow. */
2287 STAMCOUNTER StatDirtyPageOverFlowFlush;
2288
2289 /** The high wather mark for cModifiedPages. */
2290 uint16_t cModifiedPagesHigh;
2291 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2292
2293 /** The number of cache hits. */
2294 STAMCOUNTER StatCacheHits;
2295 /** The number of cache misses. */
2296 STAMCOUNTER StatCacheMisses;
2297 /** The number of times we've got a conflict of 'kind' in the cache. */
2298 STAMCOUNTER StatCacheKindMismatches;
2299 /** Number of times we've been out of pages. */
2300 STAMCOUNTER StatCacheFreeUpOne;
2301 /** The number of cacheable allocations. */
2302 STAMCOUNTER StatCacheCacheable;
2303 /** The number of uncacheable allocations. */
2304 STAMCOUNTER StatCacheUncacheable;
2305#else
2306 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2307#endif
2308 /** The AVL tree for looking up a page by its HC physical address. */
2309 AVLOHCPHYSTREE HCPhysTree;
2310 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2311 /** Array of pages. (cMaxPages in length)
2312 * The Id is the index into thist array.
2313 */
2314 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2315} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2316AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2317AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2318AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2319#ifdef VBOX_WITH_STATISTICS
2320AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2321#endif
2322AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2323
2324
2325/** @def PGMPOOL_PAGE_2_PTR
2326 * Maps a pool page pool into the current context.
2327 *
2328 * @returns VBox status code.
2329 * @param pVM The VM handle.
2330 * @param pPage The pool page.
2331 *
2332 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2333 * small page window employeed by that function. Be careful.
2334 * @remark There is no need to assert on the result.
2335 */
2336#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2337# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage) RTLOG_COMMA_SRC_POS)
2338#elif defined(VBOX_STRICT)
2339# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2340DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2341{
2342 Assert(pPage && pPage->pvPageR3);
2343 return pPage->pvPageR3;
2344}
2345#else
2346# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2347#endif
2348
2349
2350/** @def PGMPOOL_PAGE_2_PTR_V2
2351 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2352 *
2353 * @returns VBox status code.
2354 * @param pVM The VM handle.
2355 * @param pVCpu The current CPU.
2356 * @param pPage The pool page.
2357 *
2358 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2359 * small page window employeed by that function. Be careful.
2360 * @remark There is no need to assert on the result.
2361 */
2362#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2363# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage) RTLOG_COMMA_SRC_POS)
2364#else
2365# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2366#endif
2367
2368
2369/** @name Per guest page tracking data.
2370 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2371 * is to use more bits for it and split it up later on. But for now we'll play
2372 * safe and change as little as possible.
2373 *
2374 * The 16-bit word has two parts:
2375 *
2376 * The first 14-bit forms the @a idx field. It is either the index of a page in
2377 * the shadow page pool, or and index into the extent list.
2378 *
2379 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2380 * shadow page pool references to the page. If cRefs equals
2381 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2382 * (misnomer) table and not the shadow page pool.
2383 *
2384 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2385 * the 16-bit word.
2386 *
2387 * @{ */
2388/** The shift count for getting to the cRefs part. */
2389#define PGMPOOL_TD_CREFS_SHIFT 14
2390/** The mask applied after shifting the tracking data down by
2391 * PGMPOOL_TD_CREFS_SHIFT. */
2392#define PGMPOOL_TD_CREFS_MASK 0x3
2393/** The cRefs value used to indiciate that the idx is the head of a
2394 * physical cross reference list. */
2395#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2396/** The shift used to get idx. */
2397#define PGMPOOL_TD_IDX_SHIFT 0
2398/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2399#define PGMPOOL_TD_IDX_MASK 0x3fff
2400/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2401 * simply too many mappings of this page. */
2402#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2403
2404/** @def PGMPOOL_TD_MAKE
2405 * Makes a 16-bit tracking data word.
2406 *
2407 * @returns tracking data.
2408 * @param cRefs The @a cRefs field. Must be within bounds!
2409 * @param idx The @a idx field. Must also be within bounds! */
2410#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2411
2412/** @def PGMPOOL_TD_GET_CREFS
2413 * Get the @a cRefs field from a tracking data word.
2414 *
2415 * @returns The @a cRefs field
2416 * @param u16 The tracking data word.
2417 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2418 * non-zero @a u16. */
2419#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2420
2421/** @def PGMPOOL_TD_GET_IDX
2422 * Get the @a idx field from a tracking data word.
2423 *
2424 * @returns The @a idx field
2425 * @param u16 The tracking data word. */
2426#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2427/** @} */
2428
2429
2430/**
2431 * Trees are using self relative offsets as pointers.
2432 * So, all its data, including the root pointer, must be in the heap for HC and GC
2433 * to have the same layout.
2434 */
2435typedef struct PGMTREES
2436{
2437 /** Physical access handlers (AVL range+offsetptr tree). */
2438 AVLROGCPHYSTREE PhysHandlers;
2439 /** Virtual access handlers (AVL range + GC ptr tree). */
2440 AVLROGCPTRTREE VirtHandlers;
2441 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2442 AVLROGCPHYSTREE PhysToVirtHandlers;
2443 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2444 AVLROGCPTRTREE HyperVirtHandlers;
2445} PGMTREES;
2446/** Pointer to PGM trees. */
2447typedef PGMTREES *PPGMTREES;
2448
2449
2450/**
2451 * Page fault guest state for the AMD64 paging mode.
2452 */
2453typedef struct PGMPTWALKCORE
2454{
2455 /** The guest virtual address that is being resolved by the walk
2456 * (input). */
2457 RTGCPTR GCPtr;
2458
2459 /** The guest physcial address that is the result of the walk.
2460 * @remarks only valid if fSucceeded is set. */
2461 RTGCPHYS GCPhys;
2462
2463 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2464 bool fSucceeded;
2465 /** The level problem arrised at.
2466 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2467 * level 8. This is 0 on success. */
2468 uint8_t uLevel;
2469 /** Set if the page isn't present. */
2470 bool fNotPresent;
2471 /** Encountered a bad physical address. */
2472 bool fBadPhysAddr;
2473 /** Set if there was reserved bit violations. */
2474 bool fRsvdError;
2475 /** Set if it involves a big page (2/4 MB). */
2476 bool fBigPage;
2477 /** Set if it involves a gigantic page (1 GB). */
2478 bool fGigantPage;
2479 /** The effect X86_PTE_US flag for the address. */
2480 bool fEffectiveUS;
2481 /** The effect X86_PTE_RW flag for the address. */
2482 bool fEffectiveRW;
2483 /** The effect X86_PTE_NX flag for the address. */
2484 bool fEffectiveNX;
2485} PGMPTWALKCORE;
2486
2487
2488/**
2489 * Guest page table walk for the AMD64 mode.
2490 */
2491typedef struct PGMPTWALKGSTAMD64
2492{
2493 /** The common core. */
2494 PGMPTWALKCORE Core;
2495
2496 PX86PML4 pPml4;
2497 PX86PML4E pPml4e;
2498 X86PML4E Pml4e;
2499
2500 PX86PDPT pPdpt;
2501 PX86PDPE pPdpe;
2502 X86PDPE Pdpe;
2503
2504 PX86PDPAE pPd;
2505 PX86PDEPAE pPde;
2506 X86PDEPAE Pde;
2507
2508 PX86PTPAE pPt;
2509 PX86PTEPAE pPte;
2510 X86PTEPAE Pte;
2511} PGMPTWALKGSTAMD64;
2512/** Pointer to a AMD64 guest page table walk. */
2513typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2514/** Pointer to a const AMD64 guest page table walk. */
2515typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2516
2517/**
2518 * Guest page table walk for the PAE mode.
2519 */
2520typedef struct PGMPTWALKGSTPAE
2521{
2522 /** The common core. */
2523 PGMPTWALKCORE Core;
2524
2525 PX86PDPT pPdpt;
2526 PX86PDPE pPdpe;
2527 X86PDPE Pdpe;
2528
2529 PX86PDPAE pPd;
2530 PX86PDEPAE pPde;
2531 X86PDEPAE Pde;
2532
2533 PX86PTPAE pPt;
2534 PX86PTEPAE pPte;
2535 X86PTEPAE Pte;
2536} PGMPTWALKGSTPAE;
2537/** Pointer to a PAE guest page table walk. */
2538typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2539/** Pointer to a const AMD64 guest page table walk. */
2540typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2541
2542/**
2543 * Guest page table walk for the 32-bit mode.
2544 */
2545typedef struct PGMPTWALKGST32BIT
2546{
2547 /** The common core. */
2548 PGMPTWALKCORE Core;
2549
2550 PX86PD pPd;
2551 PX86PDE pPde;
2552 X86PDE Pde;
2553
2554 PX86PT pPt;
2555 PX86PTE pPte;
2556 X86PTE Pte;
2557} PGMPTWALKGST32BIT;
2558/** Pointer to a 32-bit guest page table walk. */
2559typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2560/** Pointer to a const 32-bit guest page table walk. */
2561typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2562
2563
2564/** @name Paging mode macros
2565 * @{
2566 */
2567#ifdef IN_RC
2568# define PGM_CTX(a,b) a##RC##b
2569# define PGM_CTX_STR(a,b) a "GC" b
2570# define PGM_CTX_DECL(type) VMMRCDECL(type)
2571#else
2572# ifdef IN_RING3
2573# define PGM_CTX(a,b) a##R3##b
2574# define PGM_CTX_STR(a,b) a "R3" b
2575# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2576# else
2577# define PGM_CTX(a,b) a##R0##b
2578# define PGM_CTX_STR(a,b) a "R0" b
2579# define PGM_CTX_DECL(type) VMMDECL(type)
2580# endif
2581#endif
2582
2583#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2584#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2585#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2586#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2587#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2588#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2589#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2590#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2591#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2592#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2593#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2594#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2595#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2596#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2597#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2598#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2599#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2600
2601#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2602#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2603#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2604#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2605#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2606#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2607#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2608#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2609#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2610#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2611#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2612#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2613#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2614#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2615#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2616#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2617#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2618
2619/* Shw_Gst */
2620#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2621#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2622#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2623#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2624#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2625#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2626#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2627#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2628#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2629#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2630#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2631#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2632#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2633#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2634#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2635#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2636#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2637#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2638#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2639
2640#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2641#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2642#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2643#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2644#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2645#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2646#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2647#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2648#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2649#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2650#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2651#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2652#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2653#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2654#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2655#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2656#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2657#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2658#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2659#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2660#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2661#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2662#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2663#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2664#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2665#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2666#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2667#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2668#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2669#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2670#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2671#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2672#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2673#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2674#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2675#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2676#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2677
2678#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2679#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2680/** @} */
2681
2682/**
2683 * Data for each paging mode.
2684 */
2685typedef struct PGMMODEDATA
2686{
2687 /** The guest mode type. */
2688 uint32_t uGstType;
2689 /** The shadow mode type. */
2690 uint32_t uShwType;
2691
2692 /** @name Function pointers for Shadow paging.
2693 * @{
2694 */
2695 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2696 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2697 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2698 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2699
2700 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2701 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2702
2703 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2704 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2705 /** @} */
2706
2707 /** @name Function pointers for Guest paging.
2708 * @{
2709 */
2710 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2711 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2712 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2713 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2714 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2715 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2716 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2717 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2718 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2719 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2720 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2721 /** @} */
2722
2723 /** @name Function pointers for Both Shadow and Guest paging.
2724 * @{
2725 */
2726 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2727 /* no pfnR3BthTrap0eHandler */
2728 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2729 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2730 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2731 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2732#ifdef VBOX_STRICT
2733 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2734#endif
2735 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2736 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2737
2738 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2739 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2740 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2741 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2742 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2743#ifdef VBOX_STRICT
2744 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2745#endif
2746 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2747 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2748
2749 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2750 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2751 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2752 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2753 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2754#ifdef VBOX_STRICT
2755 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2756#endif
2757 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2758 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2759 /** @} */
2760} PGMMODEDATA, *PPGMMODEDATA;
2761
2762
2763#ifdef VBOX_WITH_STATISTICS
2764/**
2765 * PGM statistics.
2766 *
2767 * These lives on the heap when compiled in as they would otherwise waste
2768 * unecessary space in release builds.
2769 */
2770typedef struct PGMSTATS
2771{
2772 /* R3 only: */
2773 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2774 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2775
2776 /* R3+RZ */
2777 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2778 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2779 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2780 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2781 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2782 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2783 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2784 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2785 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2786 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2787 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2788 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2789 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2790 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2791 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2792 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2793 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2794 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2795 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2796 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2797 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2798 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2799 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2800 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2801/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2802 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2803 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2804/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2805
2806 /* RC only: */
2807 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2808 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2809
2810 STAMCOUNTER StatRZPhysRead;
2811 STAMCOUNTER StatRZPhysReadBytes;
2812 STAMCOUNTER StatRZPhysWrite;
2813 STAMCOUNTER StatRZPhysWriteBytes;
2814 STAMCOUNTER StatR3PhysRead;
2815 STAMCOUNTER StatR3PhysReadBytes;
2816 STAMCOUNTER StatR3PhysWrite;
2817 STAMCOUNTER StatR3PhysWriteBytes;
2818 STAMCOUNTER StatRCPhysRead;
2819 STAMCOUNTER StatRCPhysReadBytes;
2820 STAMCOUNTER StatRCPhysWrite;
2821 STAMCOUNTER StatRCPhysWriteBytes;
2822
2823 STAMCOUNTER StatRZPhysSimpleRead;
2824 STAMCOUNTER StatRZPhysSimpleReadBytes;
2825 STAMCOUNTER StatRZPhysSimpleWrite;
2826 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2827 STAMCOUNTER StatR3PhysSimpleRead;
2828 STAMCOUNTER StatR3PhysSimpleReadBytes;
2829 STAMCOUNTER StatR3PhysSimpleWrite;
2830 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2831 STAMCOUNTER StatRCPhysSimpleRead;
2832 STAMCOUNTER StatRCPhysSimpleReadBytes;
2833 STAMCOUNTER StatRCPhysSimpleWrite;
2834 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2835
2836 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2837 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2838 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2839 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2840 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2841 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2842 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2843
2844 /** Time spent by the host OS for large page allocation. */
2845 STAMPROFILE StatAllocLargePage;
2846 /** Time spent clearing the newly allocated large pages. */
2847 STAMPROFILE StatClearLargePage;
2848 /** pgmPhysIsValidLargePage profiling - R3 */
2849 STAMPROFILE StatR3IsValidLargePage;
2850 /** pgmPhysIsValidLargePage profiling - RZ*/
2851 STAMPROFILE StatRZIsValidLargePage;
2852
2853 STAMPROFILE StatChunkAging;
2854 STAMPROFILE StatChunkFindCandidate;
2855 STAMPROFILE StatChunkUnmap;
2856 STAMPROFILE StatChunkMap;
2857} PGMSTATS;
2858#endif /* VBOX_WITH_STATISTICS */
2859
2860
2861/**
2862 * Converts a PGM pointer into a VM pointer.
2863 * @returns Pointer to the VM structure the PGM is part of.
2864 * @param pPGM Pointer to PGM instance data.
2865 */
2866#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2867
2868/**
2869 * PGM Data (part of VM)
2870 */
2871typedef struct PGM
2872{
2873 /** Offset to the VM structure. */
2874 int32_t offVM;
2875 /** Offset of the PGMCPU structure relative to VMCPU. */
2876 int32_t offVCpuPGM;
2877
2878 /** @cfgm{RamPreAlloc, boolean, false}
2879 * Indicates whether the base RAM should all be allocated before starting
2880 * the VM (default), or if it should be allocated when first written to.
2881 */
2882 bool fRamPreAlloc;
2883 /** Indicates whether write monitoring is currently in use.
2884 * This is used to prevent conflicts between live saving and page sharing
2885 * detection. */
2886 bool fPhysWriteMonitoringEngaged;
2887 /** Set if the CPU has less than 52-bit physical address width.
2888 * This is used */
2889 bool fLessThan52PhysicalAddressBits;
2890 /** Set when nested paging is active.
2891 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2892 * compilers optimize the code better. Whether we use nested paging or
2893 * not is something we find out during VMM initialization and we won't
2894 * change this later on. */
2895 bool fNestedPaging;
2896 /** The host paging mode. (This is what SUPLib reports.) */
2897 SUPPAGINGMODE enmHostMode;
2898 /** We're not in a state which permits writes to guest memory.
2899 * (Only used in strict builds.) */
2900 bool fNoMorePhysWrites;
2901 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2902 bool afAlignment1[3];
2903
2904 /** Indicates that PGMR3FinalizeMappings has been called and that further
2905 * PGMR3MapIntermediate calls will be rejected. */
2906 bool fFinalizedMappings;
2907 /** If set no conflict checks are required. */
2908 bool fMappingsFixed;
2909 /** If set if restored as fixed but we were unable to re-fixate at the old
2910 * location because of room or address incompatibilities. */
2911 bool fMappingsFixedRestored;
2912 /** If set, then no mappings are put into the shadow page table.
2913 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2914 bool fMappingsDisabled;
2915 /** Size of fixed mapping.
2916 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2917 uint32_t cbMappingFixed;
2918 /** Generation ID for the RAM ranges. This member is incremented everytime
2919 * a RAM range is linked or unlinked. */
2920 uint32_t volatile idRamRangesGen;
2921
2922 /** Base address (GC) of fixed mapping.
2923 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2924 RTGCPTR GCPtrMappingFixed;
2925 /** The address of the previous RAM range mapping. */
2926 RTGCPTR GCPtrPrevRamRangeMapping;
2927
2928 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2929 RTGCPHYS GCPhys4MBPSEMask;
2930 /** Mask containing the invalid bits of a guest physical address.
2931 * @remarks this does not stop at bit 52. */
2932 RTGCPHYS GCPhysInvAddrMask;
2933
2934
2935 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2936 * This is sorted by physical address and contains no overlapping ranges. */
2937 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2938 /** PGM offset based trees - R3 Ptr. */
2939 R3PTRTYPE(PPGMTREES) pTreesR3;
2940 /** Caching the last physical handler we looked up in R3. */
2941 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2942 /** Shadow Page Pool - R3 Ptr. */
2943 R3PTRTYPE(PPGMPOOL) pPoolR3;
2944 /** Linked list of GC mappings - for HC.
2945 * The list is sorted ascending on address. */
2946 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2947 /** Pointer to the list of ROM ranges - for R3.
2948 * This is sorted by physical address and contains no overlapping ranges. */
2949 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2950 /** Pointer to the list of MMIO2 ranges - for R3.
2951 * Registration order. */
2952 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2953 /** Pointer to SHW+GST mode data (function pointers).
2954 * The index into this table is made up from */
2955 R3PTRTYPE(PPGMMODEDATA) paModeData;
2956 /*RTR3PTR R3PtrAlignment0;*/
2957
2958
2959 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2960 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2961 /** PGM offset based trees - R0 Ptr. */
2962 R0PTRTYPE(PPGMTREES) pTreesR0;
2963 /** Caching the last physical handler we looked up in R0. */
2964 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2965 /** Shadow Page Pool - R0 Ptr. */
2966 R0PTRTYPE(PPGMPOOL) pPoolR0;
2967 /** Linked list of GC mappings - for R0.
2968 * The list is sorted ascending on address. */
2969 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2970 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2971 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2972 /*RTR0PTR R0PtrAlignment0;*/
2973
2974
2975 /** RC pointer corresponding to PGM::pRamRangesR3. */
2976 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2977 /** PGM offset based trees - RC Ptr. */
2978 RCPTRTYPE(PPGMTREES) pTreesRC;
2979 /** Caching the last physical handler we looked up in RC. */
2980 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
2981 /** Shadow Page Pool - RC Ptr. */
2982 RCPTRTYPE(PPGMPOOL) pPoolRC;
2983 /** Linked list of GC mappings - for RC.
2984 * The list is sorted ascending on address. */
2985 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2986 /** RC pointer corresponding to PGM::pRomRangesR3. */
2987 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2988 /*RTRCPTR RCPtrAlignment0;*/
2989 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2990 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2991 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2992 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
2993
2994
2995 /** Pointer to the 5 page CR3 content mapping.
2996 * The first page is always the CR3 (in some form) while the 4 other pages
2997 * are used of the PDs in PAE mode. */
2998 RTGCPTR GCPtrCR3Mapping;
2999
3000 /** @name Intermediate Context
3001 * @{ */
3002 /** Pointer to the intermediate page directory - Normal. */
3003 R3PTRTYPE(PX86PD) pInterPD;
3004 /** Pointer to the intermedate page tables - Normal.
3005 * There are two page tables, one for the identity mapping and one for
3006 * the host context mapping (of the core code). */
3007 R3PTRTYPE(PX86PT) apInterPTs[2];
3008 /** Pointer to the intermedate page tables - PAE. */
3009 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3010 /** Pointer to the intermedate page directory - PAE. */
3011 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3012 /** Pointer to the intermedate page directory - PAE. */
3013 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3014 /** Pointer to the intermedate page-map level 4 - AMD64. */
3015 R3PTRTYPE(PX86PML4) pInterPaePML4;
3016 /** Pointer to the intermedate page directory - AMD64. */
3017 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3018 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3019 RTHCPHYS HCPhysInterPD;
3020 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3021 RTHCPHYS HCPhysInterPaePDPT;
3022 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3023 RTHCPHYS HCPhysInterPaePML4;
3024 /** @} */
3025
3026 /** Base address of the dynamic page mapping area.
3027 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3028 *
3029 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3030 * work out. Some cleaning up of the initialization that would
3031 * remove this memory is yet to be done...
3032 */
3033 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3034 /** The address of the raw-mode context mapping cache. */
3035 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3036 /** The address of the ring-0 mapping cache if we're making use of it. */
3037 RTR0PTR pvR0DynMapUsed;
3038#if HC_ARCH_BITS == 32
3039 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
3040 uint32_t u32Alignment2;
3041#endif
3042
3043 /** PGM critical section.
3044 * This protects the physical & virtual access handlers, ram ranges,
3045 * and the page flag updating (some of it anyway).
3046 */
3047 PDMCRITSECT CritSect;
3048
3049 /**
3050 * Data associated with managing the ring-3 mappings of the allocation chunks.
3051 */
3052 struct
3053 {
3054 /** The chunk tree, ordered by chunk id. */
3055#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3056 R3PTRTYPE(PAVLU32NODECORE) pTree;
3057#else
3058 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3059#endif
3060#if HC_ARCH_BITS == 32
3061 uint32_t u32Alignment;
3062#endif
3063 /** The chunk mapping TLB. */
3064 PGMCHUNKR3MAPTLB Tlb;
3065 /** The number of mapped chunks. */
3066 uint32_t c;
3067 /** The maximum number of mapped chunks.
3068 * @cfgm PGM/MaxRing3Chunks */
3069 uint32_t cMax;
3070 /** The current time. */
3071 uint32_t iNow;
3072 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3073 uint32_t AgeingCountdown;
3074 } ChunkR3Map;
3075
3076 /**
3077 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3078 */
3079 PGMPAGER3MAPTLB PhysTlbHC;
3080
3081 /** @name The zero page.
3082 * @{ */
3083 /** The host physical address of the zero page. */
3084 RTHCPHYS HCPhysZeroPg;
3085 /** The ring-3 mapping of the zero page. */
3086 RTR3PTR pvZeroPgR3;
3087 /** The ring-0 mapping of the zero page. */
3088 RTR0PTR pvZeroPgR0;
3089 /** The GC mapping of the zero page. */
3090 RTRCPTR pvZeroPgRC;
3091 RTRCPTR RCPtrAlignment3;
3092 /** @}*/
3093
3094 /** @name The Invalid MMIO page.
3095 * This page is filled with 0xfeedface.
3096 * @{ */
3097 /** The host physical address of the invalid MMIO page. */
3098 RTHCPHYS HCPhysMmioPg;
3099 /** The host pysical address of the invalid MMIO page pluss all invalid
3100 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3101 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3102 RTHCPHYS HCPhysInvMmioPg;
3103 /** The ring-3 mapping of the invalid MMIO page. */
3104 RTR3PTR pvMmioPgR3;
3105#if HC_ARCH_BITS == 32
3106 RTR3PTR R3PtrAlignment4;
3107#endif
3108 /** @} */
3109
3110
3111 /** The number of handy pages. */
3112 uint32_t cHandyPages;
3113
3114 /** The number of large handy pages. */
3115 uint32_t cLargeHandyPages;
3116
3117 /**
3118 * Array of handy pages.
3119 *
3120 * This array is used in a two way communication between pgmPhysAllocPage
3121 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3122 * an intermediary.
3123 *
3124 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3125 * (The current size of 32 pages, means 128 KB of handy memory.)
3126 */
3127 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3128
3129 /**
3130 * Array of large handy pages. (currently size 1)
3131 *
3132 * This array is used in a two way communication between pgmPhysAllocLargePage
3133 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3134 * an intermediary.
3135 */
3136 GMMPAGEDESC aLargeHandyPage[1];
3137
3138 /**
3139 * Live save data.
3140 */
3141 struct
3142 {
3143 /** Per type statistics. */
3144 struct
3145 {
3146 /** The number of ready pages. */
3147 uint32_t cReadyPages;
3148 /** The number of dirty pages. */
3149 uint32_t cDirtyPages;
3150 /** The number of ready zero pages. */
3151 uint32_t cZeroPages;
3152 /** The number of write monitored pages. */
3153 uint32_t cMonitoredPages;
3154 } Rom,
3155 Mmio2,
3156 Ram;
3157 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3158 uint32_t cIgnoredPages;
3159 /** Indicates that a live save operation is active. */
3160 bool fActive;
3161 /** Padding. */
3162 bool afReserved[2];
3163 /** The next history index. */
3164 uint8_t iDirtyPagesHistory;
3165 /** History of the total amount of dirty pages. */
3166 uint32_t acDirtyPagesHistory[64];
3167 /** Short term dirty page average. */
3168 uint32_t cDirtyPagesShort;
3169 /** Long term dirty page average. */
3170 uint32_t cDirtyPagesLong;
3171 /** The number of saved pages. This is used to get some kind of estimate of the
3172 * link speed so we can decide when we're done. It is reset after the first
3173 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3174 * zero pages. */
3175 uint64_t cSavedPages;
3176 /** The nanosecond timestamp when cSavedPages was 0. */
3177 uint64_t uSaveStartNS;
3178 /** Pages per second (for statistics). */
3179 uint32_t cPagesPerSecond;
3180 uint32_t cAlignment;
3181 } LiveSave;
3182
3183 /** @name Error injection.
3184 * @{ */
3185 /** Inject handy page allocation errors pretending we're completely out of
3186 * memory. */
3187 bool volatile fErrInjHandyPages;
3188 /** Padding. */
3189 bool afReserved[3];
3190 /** @} */
3191
3192 /** @name Release Statistics
3193 * @{ */
3194 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3195 uint32_t cPrivatePages; /**< The number of private pages. */
3196 uint32_t cSharedPages; /**< The number of shared pages. */
3197 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3198 uint32_t cZeroPages; /**< The number of zero backed pages. */
3199 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3200 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3201 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3202 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3203 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3204 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3205 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3206 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3207/* uint32_t aAlignment4[1]; */
3208
3209 /** The number of times we were forced to change the hypervisor region location. */
3210 STAMCOUNTER cRelocations;
3211
3212 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
3213 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3214 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3215 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3216 /** @} */
3217
3218#ifdef VBOX_WITH_STATISTICS
3219 /** @name Statistics on the heap.
3220 * @{ */
3221 R3PTRTYPE(PGMSTATS *) pStatsR3;
3222 R0PTRTYPE(PGMSTATS *) pStatsR0;
3223 RCPTRTYPE(PGMSTATS *) pStatsRC;
3224 RTRCPTR RCPtrAlignment;
3225 /** @} */
3226#endif
3227} PGM;
3228#ifndef IN_TSTVMSTRUCTGC /* HACK */
3229AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3230AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3231AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3232AssertCompileMemberAlignment(PGM, CritSect, 8);
3233AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3234AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3235AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3236AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3237AssertCompileMemberAlignment(PGM, cRelocations, 8);
3238#endif /* !IN_TSTVMSTRUCTGC */
3239/** Pointer to the PGM instance data. */
3240typedef PGM *PPGM;
3241
3242
3243
3244typedef struct PGMCPUSTATS
3245{
3246 /* Common */
3247 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3248 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3249
3250 /* R0 only: */
3251 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3252 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3253
3254 /* RZ only: */
3255 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3256 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3257 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3258 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3259 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3260 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3261 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3262 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3263 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3264 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3265 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3266 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3267 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3268 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3269 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3270 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3271 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3272 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3273 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3274 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3275 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3276 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3277 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3278 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3279 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3280 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3281 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3282 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3283 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3284 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3285 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3286 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3287 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3288 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3289 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3290 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3291 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3292 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3293 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3294 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3295 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3296 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3297 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3298 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3299 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3300 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3301 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3302 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3303 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3304 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3305 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3306 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3307 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3308 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3309 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3310 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3311 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3312 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3313 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3314 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3315 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3316 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restorting to subset flushes. */
3317 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3318 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3319 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3320 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3321 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3322 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3323 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3324 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3325 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3326 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3327 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3328 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3329 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3330 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3331
3332 /* HC - R3 and (maybe) R0: */
3333
3334 /* RZ & R3: */
3335 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3336 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3337 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3338 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3339 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3340 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3341 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3342 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3343 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3344 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3345 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3346 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3347 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3348 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3349 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3350 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3351 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3352 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3353 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3354 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3355 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3356 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3357 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3358 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3359 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3360 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3361 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3362 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3363 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3364 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3365 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3366 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3367 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3368 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3369 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3370 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3371 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3372 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3373 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3374 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3375 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3376 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3377 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3378 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3379 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3380 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3381 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3382
3383 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3384 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3385 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3386 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3387 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3388 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3389 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3390 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3391 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3392 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3393 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3394 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3395 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3396 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3397 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3398 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3399 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3400 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3401 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3402 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3403 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3404 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3405 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3406 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3407 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3408 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3409 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3410 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3411 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3412 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3413 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3414 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3415 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3416 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3417 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3418 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3419 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3420 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3421 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3422 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3423 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3424 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3425 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3426 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3427 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3428 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3429 /** @} */
3430} PGMCPUSTATS;
3431
3432
3433/**
3434 * Converts a PGMCPU pointer into a VM pointer.
3435 * @returns Pointer to the VM structure the PGM is part of.
3436 * @param pPGM Pointer to PGMCPU instance data.
3437 */
3438#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3439
3440/**
3441 * Converts a PGMCPU pointer into a PGM pointer.
3442 * @returns Pointer to the VM structure the PGM is part of.
3443 * @param pPGM Pointer to PGMCPU instance data.
3444 */
3445#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3446
3447/**
3448 * PGMCPU Data (part of VMCPU).
3449 */
3450typedef struct PGMCPU
3451{
3452 /** Offset to the VM structure. */
3453 int32_t offVM;
3454 /** Offset to the VMCPU structure. */
3455 int32_t offVCpu;
3456 /** Offset of the PGM structure relative to VMCPU. */
3457 int32_t offPGM;
3458 uint32_t uPadding0; /**< structure size alignment. */
3459
3460#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3461 /** Automatically tracked physical memory mapping set.
3462 * Ring-0 and strict raw-mode builds. */
3463 PGMMAPSET AutoSet;
3464#endif
3465
3466 /** A20 gate mask.
3467 * Our current approach to A20 emulation is to let REM do it and don't bother
3468 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3469 * But whould need arrise, we'll subject physical addresses to this mask. */
3470 RTGCPHYS GCPhysA20Mask;
3471 /** A20 gate state - boolean! */
3472 bool fA20Enabled;
3473 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3474 bool fNoExecuteEnabled;
3475 /** Unused bits. */
3476 bool afUnused[2];
3477
3478 /** What needs syncing (PGM_SYNC_*).
3479 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3480 * PGMFlushTLB, and PGMR3Load. */
3481 RTUINT fSyncFlags;
3482
3483 /** The shadow paging mode. */
3484 PGMMODE enmShadowMode;
3485 /** The guest paging mode. */
3486 PGMMODE enmGuestMode;
3487
3488 /** The current physical address representing in the guest CR3 register. */
3489 RTGCPHYS GCPhysCR3;
3490
3491 /** @name 32-bit Guest Paging.
3492 * @{ */
3493 /** The guest's page directory, R3 pointer. */
3494 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3495#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3496 /** The guest's page directory, R0 pointer. */
3497 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3498#endif
3499 /** The guest's page directory, static RC mapping. */
3500 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3501 /** Mask containing the MBZ bits of a big page PDE. */
3502 uint32_t fGst32BitMbzBigPdeMask;
3503 /** Set if the page size extension (PSE) is enabled. */
3504 bool fGst32BitPageSizeExtension;
3505 /** Alignment padding. */
3506 bool afAlignment2[3];
3507 /** @} */
3508
3509 /** @name PAE Guest Paging.
3510 * @{ */
3511 /** The guest's page directory pointer table, static RC mapping. */
3512 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3513 /** The guest's page directory pointer table, R3 pointer. */
3514 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3515#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3516 /** The guest's page directory pointer table, R0 pointer. */
3517 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3518#endif
3519
3520 /** The guest's page directories, R3 pointers.
3521 * These are individual pointers and don't have to be adjecent.
3522 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3523 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3524 /** The guest's page directories, R0 pointers.
3525 * Same restrictions as apGstPaePDsR3. */
3526#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3527 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3528#endif
3529 /** The guest's page directories, static GC mapping.
3530 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3531 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3532 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3533 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3534 RTGCPHYS aGCPhysGstPaePDs[4];
3535 /** The physical addresses of the monitored guest page directories (PAE). */
3536 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3537 /** Mask containing the MBZ PTE bits. */
3538 uint64_t fGstPaeMbzPteMask;
3539 /** Mask containing the MBZ PDE bits. */
3540 uint64_t fGstPaeMbzPdeMask;
3541 /** Mask containing the MBZ big page PDE bits. */
3542 uint64_t fGstPaeMbzBigPdeMask;
3543 /** Mask containing the MBZ PDPE bits. */
3544 uint64_t fGstPaeMbzPdpeMask;
3545 /** @} */
3546
3547 /** @name AMD64 Guest Paging.
3548 * @{ */
3549 /** The guest's page directory pointer table, R3 pointer. */
3550 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3551#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3552 /** The guest's page directory pointer table, R0 pointer. */
3553 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3554#else
3555 RTR0PTR alignment6b; /**< alignment equalizer. */
3556#endif
3557 /** Mask containing the MBZ PTE bits. */
3558 uint64_t fGstAmd64MbzPteMask;
3559 /** Mask containing the MBZ PDE bits. */
3560 uint64_t fGstAmd64MbzPdeMask;
3561 /** Mask containing the MBZ big page PDE bits. */
3562 uint64_t fGstAmd64MbzBigPdeMask;
3563 /** Mask containing the MBZ PDPE bits. */
3564 uint64_t fGstAmd64MbzPdpeMask;
3565 /** Mask containing the MBZ big page PDPE bits. */
3566 uint64_t fGstAmd64MbzBigPdpeMask;
3567 /** Mask containing the MBZ PML4E bits. */
3568 uint64_t fGstAmd64MbzPml4eMask;
3569 /** Mask containing the PDPE bits that we shadow. */
3570 uint64_t fGstAmd64ShadowedPdpeMask;
3571 /** Mask containing the PML4E bits that we shadow. */
3572 uint64_t fGstAmd64ShadowedPml4eMask;
3573 /** @} */
3574
3575 /** @name PAE and AMD64 Guest Paging.
3576 * @{ */
3577 /** Mask containing the PTE bits that we shadow. */
3578 uint64_t fGst64ShadowedPteMask;
3579 /** Mask containing the PDE bits that we shadow. */
3580 uint64_t fGst64ShadowedPdeMask;
3581 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3582 uint64_t fGst64ShadowedBigPdeMask;
3583 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3584 uint64_t fGst64ShadowedBigPde4PteMask;
3585 /** @} */
3586
3587 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3588 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3589 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3590 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3591 /** Pointer to the page of the current active CR3 - RC Ptr. */
3592 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3593 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3594 uint32_t iShwUser;
3595 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3596 uint32_t iShwUserTable;
3597# if HC_ARCH_BITS == 64
3598 RTRCPTR alignment6; /**< structure size alignment. */
3599# endif
3600 /** @} */
3601
3602 /** @name Function pointers for Shadow paging.
3603 * @{
3604 */
3605 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3606 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3607 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3608 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3609
3610 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3611 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3612
3613 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3614 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3615
3616 /** @} */
3617
3618 /** @name Function pointers for Guest paging.
3619 * @{
3620 */
3621 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3622 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3623 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3624 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3625 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3626 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3627 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3628 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3629#if HC_ARCH_BITS == 64
3630 RTRCPTR alignment3; /**< structure size alignment. */
3631#endif
3632
3633 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3634 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3635 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3636 /** @} */
3637
3638 /** @name Function pointers for Both Shadow and Guest paging.
3639 * @{
3640 */
3641 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3642 /* no pfnR3BthTrap0eHandler */
3643 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3644 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3645 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3646 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3647 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3648 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3649 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3650
3651 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3652 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3653 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3654 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3655 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3656 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3657 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3658 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3659
3660 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3661 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3662 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3663 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3664 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3665 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3666 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3667 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3668#if 0
3669 RTRCPTR alignment2; /**< structure size alignment. */
3670#endif
3671 /** @} */
3672
3673 /** For saving stack space, the disassembler state is allocated here instead of
3674 * on the stack.
3675 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3676 union
3677 {
3678 /** The disassembler scratch space. */
3679 DISCPUSTATE DisState;
3680 /** Padding. */
3681 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3682 };
3683
3684 /** Count the number of pgm pool access handler calls. */
3685 uint64_t cPoolAccessHandler;
3686
3687 /** @name Release Statistics
3688 * @{ */
3689 /** The number of times the guest has switched mode since last reset or statistics reset. */
3690 STAMCOUNTER cGuestModeChanges;
3691 /** @} */
3692
3693#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3694 /** @name Statistics
3695 * @{ */
3696 /** RC: Pointer to the statistics. */
3697 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3698 /** RC: Which statistic this \#PF should be attributed to. */
3699 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3700 /** R0: Pointer to the statistics. */
3701 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3702 /** R0: Which statistic this \#PF should be attributed to. */
3703 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3704 /** R3: Pointer to the statistics. */
3705 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3706 /** Alignment padding. */
3707 RTR3PTR pPaddingR3;
3708 /** @} */
3709#endif /* VBOX_WITH_STATISTICS */
3710} PGMCPU;
3711/** Pointer to the per-cpu PGM data. */
3712typedef PGMCPU *PPGMCPU;
3713
3714
3715/** @name PGM::fSyncFlags Flags
3716 * @{
3717 */
3718/** Updates the virtual access handler state bit in PGMPAGE. */
3719#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3720/** Always sync CR3. */
3721#define PGM_SYNC_ALWAYS RT_BIT(1)
3722/** Check monitoring on next CR3 (re)load and invalidate page.
3723 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3724#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3725/** Check guest mapping in SyncCR3. */
3726#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3727/** Clear the page pool (a light weight flush). */
3728#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3729#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3730/** @} */
3731
3732
3733RT_C_DECLS_BEGIN
3734
3735int pgmLock(PVM pVM);
3736void pgmUnlock(PVM pVM);
3737
3738int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3739int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3740int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3741PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3742int pgmMapResolveConflicts(PVM pVM);
3743DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3744
3745void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3746bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3747void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3748int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3749DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3750#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3751void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3752#else
3753# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3754#endif
3755DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3756int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3757
3758int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3759int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3760int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3761int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3762int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3763void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3764int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3765int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3766int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3767int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3768int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3769int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3770int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3771VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3772VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3773int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3774
3775#ifdef IN_RING3
3776void pgmR3PhysRelinkRamRanges(PVM pVM);
3777int pgmR3PhysRamPreAllocate(PVM pVM);
3778int pgmR3PhysRamReset(PVM pVM);
3779int pgmR3PhysRomReset(PVM pVM);
3780int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3781int pgmR3PhysRamTerm(PVM pVM);
3782void pgmR3PhysRomTerm(PVM pVM);
3783
3784int pgmR3PoolInit(PVM pVM);
3785void pgmR3PoolRelocate(PVM pVM);
3786void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3787void pgmR3PoolReset(PVM pVM);
3788void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3789DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3790void pgmR3PoolWriteProtectPages(PVM pVM);
3791
3792#endif /* IN_RING3 */
3793#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || IN_RC
3794int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3795int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3796# ifdef LOG_ENABLED
3797void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3798# else
3799void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3800# endif
3801#endif
3802int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
3803 uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3804
3805DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
3806 PPPGMPOOLPAGE ppPage)
3807{
3808 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
3809}
3810
3811void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3812void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3813int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3814void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3815PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3816PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3817int pgmPoolSyncCR3(PVMCPU pVCpu);
3818bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3819void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3820int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3821void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3822uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3823void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3824void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3825int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3826void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3827
3828void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3829void pgmPoolResetDirtyPages(PVM pVM);
3830
3831int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3832int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3833
3834void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3835void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3836int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3837int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3838
3839int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3840int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3841
3842int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3843int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3844int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3845int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3846
3847# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3848DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3849DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3850# endif
3851
3852RT_C_DECLS_END
3853
3854/** @} */
3855
3856#endif
3857
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette