VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 6764

Last change on this file since 6764 was 6764, checked in by vboxsync, 17 years ago

Made !PGMPOOL_WITH_CACHE buildable so I can run OS/2 here.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 128.8 KB
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1/* $Id: PGMInternal.h 6764 2008-02-03 02:15:04Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/stam.h>
25#include <VBox/param.h>
26#include <VBox/vmm.h>
27#include <VBox/mm.h>
28#include <VBox/pdmcritsect.h>
29#include <VBox/pdmapi.h>
30#include <VBox/dis.h>
31#include <VBox/dbgf.h>
32#include <VBox/log.h>
33#include <VBox/gmm.h>
34#include <iprt/avl.h>
35#include <iprt/assert.h>
36#include <iprt/critsect.h>
37
38#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
39# error "Not in PGM! This is an internal header!"
40#endif
41
42
43/** @defgroup grp_pgm_int Internals
44 * @ingroup grp_pgm
45 * @internal
46 * @{
47 */
48
49
50/** @name PGM Compile Time Config
51 * @{
52 */
53
54/**
55 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
56 * Comment it if it will break something.
57 */
58#define PGM_OUT_OF_SYNC_IN_GC
59
60/**
61 * Virtualize the dirty bit
62 * This also makes a half-hearted attempt at the accessed bit. For full
63 * accessed bit virtualization define PGM_SYNC_ACCESSED_BIT.
64 */
65#define PGM_SYNC_DIRTY_BIT
66
67/**
68 * Fully virtualize the accessed bit.
69 * @remark This requires SYNC_DIRTY_ACCESSED_BITS to be defined!
70 */
71#define PGM_SYNC_ACCESSED_BIT
72
73/**
74 * Check and skip global PDEs for non-global flushes
75 */
76#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
77
78/**
79 * Sync N pages instead of a whole page table
80 */
81#define PGM_SYNC_N_PAGES
82
83/**
84 * Number of pages to sync during a page fault
85 *
86 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
87 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
88 */
89#define PGM_SYNC_NR_PAGES 8
90
91/**
92 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
93 */
94#define PGM_MAX_PHYSCACHE_ENTRIES 64
95#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
96
97/**
98 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
99 */
100#define PGM_PHYSMEMACCESS_CACHING
101
102/*
103 * Assert Sanity.
104 */
105#if defined(PGM_SYNC_ACCESSED_BIT) && !defined(PGM_SYNC_DIRTY_BIT)
106# error "PGM_SYNC_ACCESSED_BIT requires PGM_SYNC_DIRTY_BIT!"
107#endif
108
109/** @def PGMPOOL_WITH_CACHE
110 * Enable agressive caching using the page pool.
111 *
112 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
113 */
114//#define PGMPOOL_WITH_CACHE
115
116/** @def PGMPOOL_WITH_MIXED_PT_CR3
117 * When defined, we'll deal with 'uncachable' pages.
118 */
119#ifdef PGMPOOL_WITH_CACHE
120# define PGMPOOL_WITH_MIXED_PT_CR3
121#endif
122
123/** @def PGMPOOL_WITH_MONITORING
124 * Monitor the guest pages which are shadowed.
125 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
126 * be enabled as well.
127 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
128 */
129#ifdef PGMPOOL_WITH_CACHE
130# define PGMPOOL_WITH_MONITORING
131#endif
132
133/** @def PGMPOOL_WITH_GCPHYS_TRACKING
134 * Tracking the of shadow pages mapping guest physical pages.
135 *
136 * This is very expensive, the current cache prototype is trying to figure out
137 * whether it will be acceptable with an agressive caching policy.
138 */
139#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
140# define PGMPOOL_WITH_GCPHYS_TRACKING
141#endif
142
143/** @def PGMPOOL_WITH_USER_TRACKNG
144 * Tracking users of shadow pages. This is required for the linking of shadow page
145 * tables and physical guest addresses.
146 */
147#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
148# define PGMPOOL_WITH_USER_TRACKING
149#endif
150
151/** @def PGMPOOL_CFG_MAX_GROW
152 * The maximum number of pages to add to the pool in one go.
153 */
154#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
155
156/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
157 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
158 */
159#ifdef VBOX_STRICT
160# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
161#endif
162/** @} */
163
164
165/** @name PDPTR and PML4 flags.
166 * These are placed in the three bits available for system programs in
167 * the PDPTR and PML4 entries.
168 * @{ */
169/** The entry is a permanent one and it's must always be present.
170 * Never free such an entry. */
171#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172/** @} */
173
174/** @name Page directory flags.
175 * These are placed in the three bits available for system programs in
176 * the page directory entries.
177 * @{ */
178/** Mapping (hypervisor allocated pagetable). */
179#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
180/** Made read-only to facilitate dirty bit tracking. */
181#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
182/** @} */
183
184/** @name Page flags.
185 * These are placed in the three bits available for system programs in
186 * the page entries.
187 * @{ */
188/** Made read-only to facilitate dirty bit tracking. */
189#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
190
191#ifndef PGM_PTFLAGS_CSAM_VALIDATED
192/** Scanned and approved by CSAM (tm).
193 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
194 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
195#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
196#endif
197/** @} */
198
199/** @name Defines used to indicate the shadow and guest paging in the templates.
200 * @{ */
201#define PGM_TYPE_REAL 1
202#define PGM_TYPE_PROT 2
203#define PGM_TYPE_32BIT 3
204#define PGM_TYPE_PAE 4
205#define PGM_TYPE_AMD64 5
206/** @} */
207
208/** Macro for checking if the guest is using paging.
209 * @param uType PGM_TYPE_*
210 * @remark ASSUMES certain order of the PGM_TYPE_* values.
211 */
212#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT)
213
214
215/** @def PGM_HCPHYS_2_PTR
216 * Maps a HC physical page pool address to a virtual address.
217 *
218 * @returns VBox status code.
219 * @param pVM The VM handle.
220 * @param HCPhys The HC physical address to map to a virtual one.
221 * @param ppv Where to store the virtual address. No need to cast this.
222 *
223 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
224 * small page window employeed by that function. Be careful.
225 * @remark There is no need to assert on the result.
226 */
227#ifdef IN_GC
228# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
229#else
230# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
231#endif
232
233/** @def PGM_GCPHYS_2_PTR
234 * Maps a GC physical page address to a virtual address.
235 *
236 * @returns VBox status code.
237 * @param pVM The VM handle.
238 * @param GCPhys The GC physical address to map to a virtual one.
239 * @param ppv Where to store the virtual address. No need to cast this.
240 *
241 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
242 * small page window employeed by that function. Be careful.
243 * @remark There is no need to assert on the result.
244 */
245#ifdef IN_GC
246# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
247#else
248# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
249#endif
250
251/** @def PGM_GCPHYS_2_PTR_EX
252 * Maps a unaligned GC physical page address to a virtual address.
253 *
254 * @returns VBox status code.
255 * @param pVM The VM handle.
256 * @param GCPhys The GC physical address to map to a virtual one.
257 * @param ppv Where to store the virtual address. No need to cast this.
258 *
259 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
260 * small page window employeed by that function. Be careful.
261 * @remark There is no need to assert on the result.
262 */
263#ifdef IN_GC
264# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
265#else
266# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_INVL_PG
270 * Invalidates a page when in GC does nothing in HC.
271 *
272 * @param GCVirt The virtual address of the page to invalidate.
273 */
274#ifdef IN_GC
275# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
276#else
277# define PGM_INVL_PG(GCVirt) ((void)0)
278#endif
279
280/** @def PGM_INVL_BIG_PG
281 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
282 *
283 * @param GCVirt The virtual address within the page directory to invalidate.
284 */
285#ifdef IN_GC
286# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
287#else
288# define PGM_INVL_BIG_PG(GCVirt) ((void)0)
289#endif
290
291/** @def PGM_INVL_GUEST_TLBS()
292 * Invalidates all guest TLBs.
293 */
294#ifdef IN_GC
295# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
296#else
297# define PGM_INVL_GUEST_TLBS() ((void)0)
298#endif
299
300
301/**
302 * Structure for tracking GC Mappings.
303 *
304 * This structure is used by linked list in both GC and HC.
305 */
306typedef struct PGMMAPPING
307{
308 /** Pointer to next entry. */
309 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
310 /** Pointer to next entry. */
311 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
312 /** Pointer to next entry. */
313 GCPTRTYPE(struct PGMMAPPING *) pNextGC;
314 /** Start Virtual address. */
315 RTGCUINTPTR GCPtr;
316 /** Last Virtual address (inclusive). */
317 RTGCUINTPTR GCPtrLast;
318 /** Range size (bytes). */
319 RTGCUINTPTR cb;
320 /** Pointer to relocation callback function. */
321 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
322 /** User argument to the callback. */
323 R3PTRTYPE(void *) pvUser;
324 /** Mapping description / name. For easing debugging. */
325 R3PTRTYPE(const char *) pszDesc;
326 /** Number of page tables. */
327 RTUINT cPTs;
328#if HC_ARCH_BITS != GC_ARCH_BITS
329 RTUINT uPadding0; /**< Alignment padding. */
330#endif
331 /** Array of page table mapping data. Each entry
332 * describes one page table. The array can be longer
333 * than the declared length.
334 */
335 struct
336 {
337 /** The HC physical address of the page table. */
338 RTHCPHYS HCPhysPT;
339 /** The HC physical address of the first PAE page table. */
340 RTHCPHYS HCPhysPaePT0;
341 /** The HC physical address of the second PAE page table. */
342 RTHCPHYS HCPhysPaePT1;
343 /** The HC virtual address of the 32-bit page table. */
344 R3PTRTYPE(PVBOXPT) pPTR3;
345 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
346 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
347 /** The GC virtual address of the 32-bit page table. */
348 GCPTRTYPE(PVBOXPT) pPTGC;
349 /** The GC virtual address of the two PAE page table. */
350 GCPTRTYPE(PX86PTPAE) paPaePTsGC;
351 /** The GC virtual address of the 32-bit page table. */
352 R0PTRTYPE(PVBOXPT) pPTR0;
353 /** The GC virtual address of the two PAE page table. */
354 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
355 } aPTs[1];
356} PGMMAPPING;
357/** Pointer to structure for tracking GC Mappings. */
358typedef struct PGMMAPPING *PPGMMAPPING;
359
360
361/**
362 * Physical page access handler structure.
363 *
364 * This is used to keep track of physical address ranges
365 * which are being monitored in some kind of way.
366 */
367typedef struct PGMPHYSHANDLER
368{
369 AVLROGCPHYSNODECORE Core;
370 /** Alignment padding. */
371 uint32_t u32Padding;
372 /** Access type. */
373 PGMPHYSHANDLERTYPE enmType;
374 /** Number of pages to update. */
375 uint32_t cPages;
376 /** Pointer to R3 callback function. */
377 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
378 /** User argument for R3 handlers. */
379 R3PTRTYPE(void *) pvUserR3;
380 /** Pointer to R0 callback function. */
381 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
382 /** User argument for R0 handlers. */
383 R0PTRTYPE(void *) pvUserR0;
384 /** Pointer to GC callback function. */
385 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
386 /** User argument for GC handlers. */
387 GCPTRTYPE(void *) pvUserGC;
388 /** Description / Name. For easing debugging. */
389 R3PTRTYPE(const char *) pszDesc;
390#ifdef VBOX_WITH_STATISTICS
391 /** Profiling of this handler. */
392 STAMPROFILE Stat;
393#endif
394} PGMPHYSHANDLER;
395/** Pointer to a physical page access handler structure. */
396typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
397
398
399/**
400 * Cache node for the physical addresses covered by a virtual handler.
401 */
402typedef struct PGMPHYS2VIRTHANDLER
403{
404 /** Core node for the tree based on physical ranges. */
405 AVLROGCPHYSNODECORE Core;
406 /** Offset from this struct to the PGMVIRTHANDLER structure. */
407 RTGCINTPTR offVirtHandler;
408 /** Offset of the next alias relativer to this one.
409 * Bit 0 is used for indicating whether we're in the tree.
410 * Bit 1 is used for indicating that we're the head node.
411 */
412 int32_t offNextAlias;
413} PGMPHYS2VIRTHANDLER;
414/** Pointer to a phys to virtual handler structure. */
415typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
416
417/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
418 * node is in the tree. */
419#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
420/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
421 * node is in the head of an alias chain.
422 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
423#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
424/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
425#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
426
427
428/**
429 * Virtual page access handler structure.
430 *
431 * This is used to keep track of virtual address ranges
432 * which are being monitored in some kind of way.
433 */
434typedef struct PGMVIRTHANDLER
435{
436 /** Core node for the tree based on virtual ranges. */
437 AVLROGCPTRNODECORE Core;
438 /** Number of cache pages. */
439 uint32_t u32Padding;
440 /** Access type. */
441 PGMVIRTHANDLERTYPE enmType;
442 /** Number of cache pages. */
443 uint32_t cPages;
444
445/** @todo The next two members are redundant. It adds some readability though. */
446 /** Start of the range. */
447 RTGCPTR GCPtr;
448 /** End of the range (exclusive). */
449 RTGCPTR GCPtrLast;
450 /** Size of the range (in bytes). */
451 RTGCUINTPTR cb;
452 /** Pointer to the GC callback function. */
453 GCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
454 /** Pointer to the HC callback function for invalidation. */
455 R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
456 /** Pointer to the HC callback function. */
457 R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
458 /** Description / Name. For easing debugging. */
459 R3PTRTYPE(const char *) pszDesc;
460#ifdef VBOX_WITH_STATISTICS
461 /** Profiling of this handler. */
462 STAMPROFILE Stat;
463#endif
464 /** Array of cached physical addresses for the monitored ranged. */
465 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
466} PGMVIRTHANDLER;
467/** Pointer to a virtual page access handler structure. */
468typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
469
470
471/**
472 * A Physical Guest Page tracking structure.
473 *
474 * The format of this structure is complicated because we have to fit a lot
475 * of information into as few bits as possible. The format is also subject
476 * to change (there is one comming up soon). Which means that for we'll be
477 * using PGM_PAGE_GET_* and PGM_PAGE_SET_* macros for all accessess to the
478 * structure.
479 */
480typedef struct PGMPAGE
481{
482 /** The physical address and a whole lot of other stuff. All bits are used! */
483 RTHCPHYS HCPhys;
484 /** The page state. */
485 uint32_t u2State : 2;
486 /** Flag indicating that a write monitored page was written to when set. */
487 uint32_t fWrittenTo : 1;
488 /** For later. */
489 uint32_t fSomethingElse : 1;
490 /** The Page ID. */
491 uint32_t idPage : 28;
492 uint32_t u32B;
493} PGMPAGE;
494AssertCompileSize(PGMPAGE, 16);
495/** Pointer to a physical guest page. */
496typedef PGMPAGE *PPGMPAGE;
497/** Pointer to a const physical guest page. */
498typedef const PGMPAGE *PCPGMPAGE;
499/** Pointer to a physical guest page pointer. */
500typedef PPGMPAGE *PPPGMPAGE;
501
502/** @name The Page state, PGMPAGE::u2State.
503 * @{ */
504/** The zero page.
505 * This is a per-VM page that's never ever mapped writable. */
506#define PGM_PAGE_STATE_ZERO 0
507/** A allocated page.
508 * This is a per-VM page allocated from the page pool.
509 */
510#define PGM_PAGE_STATE_ALLOCATED 1
511/** A allocated page that's being monitored for writes.
512 * The shadow page table mappings are read-only. When a write occurs, the
513 * fWrittenTo member is set, the page remapped as read-write and the state
514 * moved back to allocated. */
515#define PGM_PAGE_STATE_WRITE_MONITORED 2
516/** The page is shared, aka. copy-on-write.
517 * This is a page that's shared with other VMs. */
518#define PGM_PAGE_STATE_SHARED 3
519/** @} */
520
521
522/**
523 * Gets the page state.
524 * @returns page state (PGM_PAGE_STATE_*).
525 * @param pPage Pointer to the physical guest page tracking structure.
526 */
527#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2State )
528
529/**
530 * Sets the page state.
531 * @param pPage Pointer to the physical guest page tracking structure.
532 * @param _uState The new page state.
533 */
534#define PGM_PAGE_SET_STATE(pPage, _uState) \
535 do { (pPage)->u2State = (_uState); } while (0)
536
537
538/**
539 * Gets the host physical address of the guest page.
540 * @returns host physical address (RTHCPHYS).
541 * @param pPage Pointer to the physical guest page tracking structure.
542 */
543#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
544
545/**
546 * Sets the host physical address of the guest page.
547 * @param pPage Pointer to the physical guest page tracking structure.
548 * @param _HCPhys The new host physical address.
549 */
550#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
551 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
552 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
553
554/**
555 * Get the Page ID.
556 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
557 * @param pPage Pointer to the physical guest page tracking structure.
558 */
559#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPage )
560/* later:
561#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
562 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
563*/
564/**
565 * Sets the Page ID.
566 * @param pPage Pointer to the physical guest page tracking structure.
567 */
568#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPage = (_idPage); } while (0)
569/* later:
570#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
571 | ((_idPage) & 0xfff) \
572 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
573*/
574
575/**
576 * Get the Chunk ID.
577 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
578 * @param pPage Pointer to the physical guest page tracking structure.
579 */
580#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPage >> GMM_CHUNKID_SHIFT )
581/* later:
582#if GMM_CHUNKID_SHIFT == 12
583# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
584#elif GMM_CHUNKID_SHIFT > 12
585# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
586#elif GMM_CHUNKID_SHIFT < 12
587# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
588 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
589#else
590# error "GMM_CHUNKID_SHIFT isn't defined or something."
591#endif
592*/
593
594/**
595 * Get the index of the page within the allocaiton chunk.
596 * @returns The page index.
597 * @param pPage Pointer to the physical guest page tracking structure.
598 */
599#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPage & (RT_BIT_32(GMM_CHUNKID_SHIFT) - 1) )
600/* later:
601#if GMM_CHUNKID_SHIFT <= 12
602# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & (RT_BIT_32(GMM_CHUNKID_SHIFT) - 1)) )
603#else
604# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
605 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
606#endif
607*/
608
609/**
610 * Checks if the page is 'reserved'.
611 * @returns true/false.
612 * @param pPage Pointer to the physical guest page tracking structure.
613 */
614#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
615
616/**
617 * Checks if the page is marked for MMIO.
618 * @returns true/false.
619 * @param pPage Pointer to the physical guest page tracking structure.
620 */
621#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
622
623/**
624 * Checks if the page is backed by the ZERO page.
625 * @returns true/false.
626 * @param pPage Pointer to the physical guest page tracking structure.
627 */
628#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2State == PGM_PAGE_STATE_ZERO )
629
630/**
631 * Checks if the page is backed by a SHARED page.
632 * @returns true/false.
633 * @param pPage Pointer to the physical guest page tracking structure.
634 */
635#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2State == PGM_PAGE_STATE_SHARED )
636
637
638
639/**
640 * Ram range for GC Phys to HC Phys conversion.
641 *
642 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
643 * conversions too, but we'll let MM handle that for now.
644 *
645 * This structure is used by linked lists in both GC and HC.
646 */
647typedef struct PGMRAMRANGE
648{
649 /** Pointer to the next RAM range - for HC. */
650 R3R0PTRTYPE(struct PGMRAMRANGE *) pNextHC;
651 /** Pointer to the next RAM range - for GC. */
652 GCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
653 /** Start of the range. Page aligned. */
654 RTGCPHYS GCPhys;
655 /** Last address in the range (inclusive). Page aligned (-1). */
656 RTGCPHYS GCPhysLast;
657 /** Size of the range. (Page aligned of course). */
658 RTGCPHYS cb;
659 /** MM_RAM_* flags */
660 uint32_t fFlags;
661
662 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
663 GCPTRTYPE(PRTHCPTR) pavHCChunkGC;
664 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
665 R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
666
667 /** Start of the HC mapping of the range.
668 * For pure MMIO and dynamically allocated ranges this is NULL, while for all ranges this is a valid pointer. */
669 R3PTRTYPE(void *) pvHC;
670
671 /** Array of physical guest page tracking structures. */
672 PGMPAGE aPages[1];
673} PGMRAMRANGE;
674/** Pointer to Ram range for GC Phys to HC Phys conversion. */
675typedef PGMRAMRANGE *PPGMRAMRANGE;
676
677/** Return hc ptr corresponding to the ram range and physical offset */
678#define PGMRAMRANGE_GETHCPTR(pRam, off) \
679 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
680 : (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
681
682/** @todo r=bird: fix typename. */
683/**
684 * PGMPhysRead/Write cache entry
685 */
686typedef struct PGMPHYSCACHE_ENTRY
687{
688 /** HC pointer to physical page */
689 R3PTRTYPE(uint8_t *) pbHC;
690 /** GC Physical address for cache entry */
691 RTGCPHYS GCPhys;
692#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
693 RTGCPHYS u32Padding0; /**< alignment padding. */
694#endif
695} PGMPHYSCACHE_ENTRY;
696
697/**
698 * PGMPhysRead/Write cache to reduce REM memory access overhead
699 */
700typedef struct PGMPHYSCACHE
701{
702 /** Bitmap of valid cache entries */
703 uint64_t aEntries;
704 /** Cache entries */
705 PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
706} PGMPHYSCACHE;
707
708
709/** Pointer to an allocation chunk ring-3 mapping. */
710typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
711/** Pointer to an allocation chunk ring-3 mapping pointer. */
712typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
713
714/**
715 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
716 *
717 * The primary tree (Core) uses the chunk id as key.
718 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
719 */
720typedef struct PGMCHUNKR3MAP
721{
722 /** The key is the chunk id. */
723 AVLU32NODECORE Core;
724 /** The key is the ageing sequence number. */
725 AVLLU32NODECORE AgeCore;
726 /** The current age thingy. */
727 uint32_t iAge;
728 /** The current reference count. */
729 uint32_t volatile cRefs;
730 /** The current permanent reference count. */
731 uint32_t volatile cPermRefs;
732 /** The mapping address. */
733 void *pv;
734} PGMCHUNKR3MAP;
735
736/**
737 * Allocation chunk ring-3 mapping TLB entry.
738 */
739typedef struct PGMCHUNKR3MAPTLBE
740{
741 /** The chunk id. */
742 uint32_t volatile idChunk;
743#if HC_ARCH_BITS == 64
744 uint32_t u32Padding; /**< alignment padding. */
745#endif
746 /** The chunk map. */
747 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
748} PGMCHUNKR3MAPTLBE;
749/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
750typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
751
752/** The number of TLB entries in PGMCHUNKR3MAPTLB.
753 * @remark Must be a power of two value. */
754#define PGM_CHUNKR3MAPTLB_ENTRIES 32
755
756/**
757 * Allocation chunk ring-3 mapping TLB.
758 *
759 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
760 * At first glance this might look kinda odd since AVL trees are
761 * supposed to give the most optimial lookup times of all trees
762 * due to their balancing. However, take a tree with 1023 nodes
763 * in it, that's 10 levels, meaning that most searches has to go
764 * down 9 levels before they find what they want. This isn't fast
765 * compared to a TLB hit. There is the factor of cache misses,
766 * and of course the problem with trees and branch prediction.
767 * This is why we use TLBs in front of most of the trees.
768 *
769 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
770 * difficult when we switch to inlined AVL trees (from kStuff).
771 */
772typedef struct PGMCHUNKR3MAPTLB
773{
774 /** The TLB entries. */
775 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
776} PGMCHUNKR3MAPTLB;
777
778/**
779 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
780 * @returns Chunk TLB index.
781 * @param idChunk The Chunk ID.
782 */
783#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
784
785
786/**
787 * Ring-3 guest page mapping TLB entry.
788 * @remarks used in ring-0 as well at the moment.
789 */
790typedef struct PGMPAGER3MAPTLBE
791{
792 /** Address of the page. */
793 RTGCPHYS volatile GCPhys;
794#if HC_ARCH_BITS == 64
795 uint32_t u32Padding; /**< alignment padding. */
796#endif
797 /** The guest page. */
798 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
799 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
800 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
801 /** The address */
802 R3R0PTRTYPE(void *) volatile pv;
803} PGMPAGER3MAPTLBE;
804/** Pointer to an entry in the HC physical TLB. */
805typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
806
807
808/** The number of entries in the ring-3 guest page mapping TLB.
809 * @remarks The value must be a power of two. */
810#define PGM_PAGER3MAPTLB_ENTRIES 64
811
812/**
813 * Ring-3 guest page mapping TLB.
814 * @remarks used in ring-0 as well at the moment.
815 */
816typedef struct PGMPAGER3MAPTLB
817{
818 /** The TLB entries. */
819 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
820} PGMPAGER3MAPTLB;
821/** Pointer to the ring-3 guest page mapping TLB. */
822typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
823
824/**
825 * Calculates the index of the TLB entry for the specified guest page.
826 * @returns Physical TLB index.
827 * @param GCPhys The guest physical address.
828 */
829#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
830
831
832/** @name Context neutrual page mapper TLB.
833 *
834 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
835 * code is writting in a kind of context neutrual way. Time will show whether
836 * this actually makes sense or not...
837 *
838 * @{ */
839/** @typedef PPGMPAGEMAPTLB
840 * The page mapper TLB pointer type for the current context. */
841/** @typedef PPGMPAGEMAPTLB
842 * The page mapper TLB entry pointer type for the current context. */
843/** @typedef PPGMPAGEMAPTLB
844 * The page mapper TLB entry pointer pointer type for the current context. */
845/** @def PGMPAGEMAPTLB_ENTRIES
846 * The number of TLB entries in the page mapper TLB for the current context. */
847/** @def PGM_PAGEMAPTLB_IDX
848 * Calculate the TLB index for a guest physical address.
849 * @returns The TLB index.
850 * @param GCPhys The guest physical address. */
851/** @typedef PPGMPAGEMAP
852 * Pointer to a page mapper unit for current context. */
853/** @typedef PPPGMPAGEMAP
854 * Pointer to a page mapper unit pointer for current context. */
855#ifdef IN_GC
856// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
857// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
858// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
859# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
860# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
861 typedef void * PPGMPAGEMAP;
862 typedef void ** PPPGMPAGEMAP;
863//#elif IN_RING0
864// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
865// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
866// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
867//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
868//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
869// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
870// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
871#else
872 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
873 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
874 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
875# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
876# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
877 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
878 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
879#endif
880/** @} */
881
882
883/** @name PGM Pool Indexes.
884 * Aka. the unique shadow page identifier.
885 * @{ */
886/** NIL page pool IDX. */
887#define NIL_PGMPOOL_IDX 0
888/** The first normal index. */
889#define PGMPOOL_IDX_FIRST_SPECIAL 1
890/** Page directory (32-bit root). */
891#define PGMPOOL_IDX_PD 1
892/** The extended PAE page directory (2048 entries, works as root currently). */
893#define PGMPOOL_IDX_PAE_PD 2
894/** Page Directory Pointer Table (PAE root, not currently used). */
895#define PGMPOOL_IDX_PDPTR 3
896/** Page Map Level-4 (64-bit root). */
897#define PGMPOOL_IDX_PML4 4
898/** The first normal index. */
899#define PGMPOOL_IDX_FIRST 5
900/** The last valid index. (inclusive, 14 bits) */
901#define PGMPOOL_IDX_LAST 0x3fff
902/** @} */
903
904/** The NIL index for the parent chain. */
905#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
906
907/**
908 * Node in the chain linking a shadowed page to it's parent (user).
909 */
910#pragma pack(1)
911typedef struct PGMPOOLUSER
912{
913 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
914 uint16_t iNext;
915 /** The user page index. */
916 uint16_t iUser;
917 /** Index into the user table. */
918 uint16_t iUserTable;
919} PGMPOOLUSER, *PPGMPOOLUSER;
920typedef const PGMPOOLUSER *PCPGMPOOLUSER;
921#pragma pack()
922
923
924/** The NIL index for the phys ext chain. */
925#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
926
927/**
928 * Node in the chain of physical cross reference extents.
929 */
930#pragma pack(1)
931typedef struct PGMPOOLPHYSEXT
932{
933 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
934 uint16_t iNext;
935 /** The user page index. */
936 uint16_t aidx[3];
937} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
938typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
939#pragma pack()
940
941
942/**
943 * The kind of page that's being shadowed.
944 */
945typedef enum PGMPOOLKIND
946{
947 /** The virtual invalid 0 entry. */
948 PGMPOOLKIND_INVALID = 0,
949 /** The entry is free (=unused). */
950 PGMPOOLKIND_FREE,
951
952 /** Shw: 32-bit page table; Gst: no paging */
953 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
954 /** Shw: 32-bit page table; Gst: 32-bit page table. */
955 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
956 /** Shw: 32-bit page table; Gst: 4MB page. */
957 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
958 /** Shw: PAE page table; Gst: no paging */
959 PGMPOOLKIND_PAE_PT_FOR_PHYS,
960 /** Shw: PAE page table; Gst: 32-bit page table. */
961 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
962 /** Shw: PAE page table; Gst: Half of a 4MB page. */
963 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
964 /** Shw: PAE page table; Gst: PAE page table. */
965 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
966 /** Shw: PAE page table; Gst: 2MB page. */
967 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
968
969 /** Shw: PAE page directory; Gst: 32-bit page directory. */
970 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
971 /** Shw: PAE page directory; Gst: PAE page directory. */
972 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
973
974 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
975 PGMPOOLKIND_64BIT_PDPTR_FOR_64BIT_PDPTR,
976
977 /** Shw: Root 32-bit page directory. */
978 PGMPOOLKIND_ROOT_32BIT_PD,
979 /** Shw: Root PAE page directory */
980 PGMPOOLKIND_ROOT_PAE_PD,
981 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
982 PGMPOOLKIND_ROOT_PDPTR,
983 /** Shw: Root page map level-4 table. */
984 PGMPOOLKIND_ROOT_PML4,
985
986 /** The last valid entry. */
987 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PML4
988} PGMPOOLKIND;
989
990
991/**
992 * The tracking data for a page in the pool.
993 */
994typedef struct PGMPOOLPAGE
995{
996 /** AVL node code with the (HC) physical address of this page. */
997 AVLOHCPHYSNODECORE Core;
998 /** Pointer to the HC mapping of the page. */
999 R3R0PTRTYPE(void *) pvPageHC;
1000 /** The guest physical address. */
1001 RTGCPHYS GCPhys;
1002 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1003 uint8_t enmKind;
1004 uint8_t bPadding;
1005 /** The index of this page. */
1006 uint16_t idx;
1007 /** The next entry in the list this page currently resides in.
1008 * It's either in the free list or in the GCPhys hash. */
1009 uint16_t iNext;
1010#ifdef PGMPOOL_WITH_USER_TRACKING
1011 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1012 uint16_t iUserHead;
1013 /** The number of present entries. */
1014 uint16_t cPresent;
1015 /** The first entry in the table which is present. */
1016 uint16_t iFirstPresent;
1017#endif
1018#ifdef PGMPOOL_WITH_MONITORING
1019 /** The number of modifications to the monitored page. */
1020 uint16_t cModifications;
1021 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1022 uint16_t iModifiedNext;
1023 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1024 uint16_t iModifiedPrev;
1025 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1026 uint16_t iMonitoredNext;
1027 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1028 uint16_t iMonitoredPrev;
1029#endif
1030#ifdef PGMPOOL_WITH_CACHE
1031 /** The next page in the age list. */
1032 uint16_t iAgeNext;
1033 /** The previous page in the age list. */
1034 uint16_t iAgePrev;
1035#endif /* PGMPOOL_WITH_CACHE */
1036 /** Used to indicate that the page is zeroed. */
1037 bool fZeroed;
1038 /** Used to indicate that a PT has non-global entries. */
1039 bool fSeenNonGlobal;
1040 /** Used to indicate that we're monitoring writes to the guest page. */
1041 bool fMonitored;
1042 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1043 * (All pages are in the age list.) */
1044 bool fCached;
1045 /** This is used by the R3 access handlers when invoked by an async thread.
1046 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1047 bool volatile fReusedFlushPending;
1048 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1049 * In these cases the access handler acts differently and will check
1050 * for mapping conflicts like the normal CR3 handler.
1051 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1052 * replaced by a list of pages which share access handler.
1053 */
1054 bool fCR3Mix;
1055#if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
1056 bool Alignment[4]; /**< Align the structure size on a 64-bit boundrary. */
1057#endif
1058} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1059
1060
1061#ifdef PGMPOOL_WITH_CACHE
1062/** The hash table size. */
1063# define PGMPOOL_HASH_SIZE 0x40
1064/** The hash function. */
1065# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1066#endif
1067
1068
1069/**
1070 * The shadow page pool instance data.
1071 *
1072 * It's all one big allocation made at init time, except for the
1073 * pages that is. The user nodes follows immediatly after the
1074 * page structures.
1075 */
1076typedef struct PGMPOOL
1077{
1078 /** The VM handle - HC Ptr. */
1079 R3R0PTRTYPE(PVM) pVMHC;
1080 /** The VM handle - GC Ptr. */
1081 GCPTRTYPE(PVM) pVMGC;
1082 /** The max pool size. This includes the special IDs. */
1083 uint16_t cMaxPages;
1084 /** The current pool size. */
1085 uint16_t cCurPages;
1086 /** The head of the free page list. */
1087 uint16_t iFreeHead;
1088 /* Padding. */
1089 uint16_t u16Padding;
1090#ifdef PGMPOOL_WITH_USER_TRACKING
1091 /** Head of the chain of free user nodes. */
1092 uint16_t iUserFreeHead;
1093 /** The number of user nodes we've allocated. */
1094 uint16_t cMaxUsers;
1095 /** The number of present page table entries in the entire pool. */
1096 uint32_t cPresent;
1097 /** Pointer to the array of user nodes - GC pointer. */
1098 GCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1099 /** Pointer to the array of user nodes - HC pointer. */
1100 R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1101#endif /* PGMPOOL_WITH_USER_TRACKING */
1102#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1103 /** Head of the chain of free phys ext nodes. */
1104 uint16_t iPhysExtFreeHead;
1105 /** The number of user nodes we've allocated. */
1106 uint16_t cMaxPhysExts;
1107 /** Pointer to the array of physical xref extent - GC pointer. */
1108 GCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1109 /** Pointer to the array of physical xref extent nodes - HC pointer. */
1110 R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1111#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1112#ifdef PGMPOOL_WITH_CACHE
1113 /** Hash table for GCPhys addresses. */
1114 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1115 /** The head of the age list. */
1116 uint16_t iAgeHead;
1117 /** The tail of the age list. */
1118 uint16_t iAgeTail;
1119 /** Set if the cache is enabled. */
1120 bool fCacheEnabled;
1121#endif /* PGMPOOL_WITH_CACHE */
1122#ifdef PGMPOOL_WITH_MONITORING
1123 /** Head of the list of modified pages. */
1124 uint16_t iModifiedHead;
1125 /** The current number of modified pages. */
1126 uint16_t cModifiedPages;
1127 /** Access handler, GC. */
1128 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1129 /** Access handler, R0. */
1130 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1131 /** Access handler, R3. */
1132 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1133 /** The access handler description (HC ptr). */
1134 R3PTRTYPE(const char *) pszAccessHandler;
1135#endif /* PGMPOOL_WITH_MONITORING */
1136 /** The number of pages currently in use. */
1137 uint16_t cUsedPages;
1138#ifdef VBOX_WITH_STATISTICS
1139 /** The high wather mark for cUsedPages. */
1140 uint16_t cUsedPagesHigh;
1141 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1142 /** Profiling pgmPoolAlloc(). */
1143 STAMPROFILEADV StatAlloc;
1144 /** Profiling pgmPoolClearAll(). */
1145 STAMPROFILE StatClearAll;
1146 /** Profiling pgmPoolFlushAllInt(). */
1147 STAMPROFILE StatFlushAllInt;
1148 /** Profiling pgmPoolFlushPage(). */
1149 STAMPROFILE StatFlushPage;
1150 /** Profiling pgmPoolFree(). */
1151 STAMPROFILE StatFree;
1152 /** Profiling time spent zeroing pages. */
1153 STAMPROFILE StatZeroPage;
1154# ifdef PGMPOOL_WITH_USER_TRACKING
1155 /** Profiling of pgmPoolTrackDeref. */
1156 STAMPROFILE StatTrackDeref;
1157 /** Profiling pgmTrackFlushGCPhysPT. */
1158 STAMPROFILE StatTrackFlushGCPhysPT;
1159 /** Profiling pgmTrackFlushGCPhysPTs. */
1160 STAMPROFILE StatTrackFlushGCPhysPTs;
1161 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1162 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1163 /** Number of times we've been out of user records. */
1164 STAMCOUNTER StatTrackFreeUpOneUser;
1165# endif
1166# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1167 /** Profiling deref activity related tracking GC physical pages. */
1168 STAMPROFILE StatTrackDerefGCPhys;
1169 /** Number of linear searches for a HCPhys in the ram ranges. */
1170 STAMCOUNTER StatTrackLinearRamSearches;
1171 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1172 STAMCOUNTER StamTrackPhysExtAllocFailures;
1173# endif
1174# ifdef PGMPOOL_WITH_MONITORING
1175 /** Profiling the GC PT access handler. */
1176 STAMPROFILE StatMonitorGC;
1177 /** Times we've failed interpreting the instruction. */
1178 STAMCOUNTER StatMonitorGCEmulateInstr;
1179 /** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1180 STAMPROFILE StatMonitorGCFlushPage;
1181 /** Times we've detected fork(). */
1182 STAMCOUNTER StatMonitorGCFork;
1183 /** Profiling the GC access we've handled (except REP STOSD). */
1184 STAMPROFILE StatMonitorGCHandled;
1185 /** Times we've failed interpreting a patch code instruction. */
1186 STAMCOUNTER StatMonitorGCIntrFailPatch1;
1187 /** Times we've failed interpreting a patch code instruction during flushing. */
1188 STAMCOUNTER StatMonitorGCIntrFailPatch2;
1189 /** The number of times we've seen rep prefixes we can't handle. */
1190 STAMCOUNTER StatMonitorGCRepPrefix;
1191 /** Profiling the REP STOSD cases we've handled. */
1192 STAMPROFILE StatMonitorGCRepStosd;
1193
1194 /** Profiling the HC PT access handler. */
1195 STAMPROFILE StatMonitorHC;
1196 /** Times we've failed interpreting the instruction. */
1197 STAMCOUNTER StatMonitorHCEmulateInstr;
1198 /** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1199 STAMPROFILE StatMonitorHCFlushPage;
1200 /** Times we've detected fork(). */
1201 STAMCOUNTER StatMonitorHCFork;
1202 /** Profiling the HC access we've handled (except REP STOSD). */
1203 STAMPROFILE StatMonitorHCHandled;
1204 /** The number of times we've seen rep prefixes we can't handle. */
1205 STAMCOUNTER StatMonitorHCRepPrefix;
1206 /** Profiling the REP STOSD cases we've handled. */
1207 STAMPROFILE StatMonitorHCRepStosd;
1208 /** The number of times we're called in an async thread an need to flush. */
1209 STAMCOUNTER StatMonitorHCAsync;
1210 /** The high wather mark for cModifiedPages. */
1211 uint16_t cModifiedPagesHigh;
1212 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1213# endif
1214# ifdef PGMPOOL_WITH_CACHE
1215 /** The number of cache hits. */
1216 STAMCOUNTER StatCacheHits;
1217 /** The number of cache misses. */
1218 STAMCOUNTER StatCacheMisses;
1219 /** The number of times we've got a conflict of 'kind' in the cache. */
1220 STAMCOUNTER StatCacheKindMismatches;
1221 /** Number of times we've been out of pages. */
1222 STAMCOUNTER StatCacheFreeUpOne;
1223 /** The number of cacheable allocations. */
1224 STAMCOUNTER StatCacheCacheable;
1225 /** The number of uncacheable allocations. */
1226 STAMCOUNTER StatCacheUncacheable;
1227# endif
1228#elif HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1229 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1230#endif
1231 /** The AVL tree for looking up a page by its HC physical address. */
1232 AVLOHCPHYSTREE HCPhysTree;
1233 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1234 /** Array of pages. (cMaxPages in length)
1235 * The Id is the index into thist array.
1236 */
1237 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1238} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1239
1240
1241/** @def PGMPOOL_PAGE_2_PTR
1242 * Maps a pool page pool into the current context.
1243 *
1244 * @returns VBox status code.
1245 * @param pVM The VM handle.
1246 * @param pPage The pool page.
1247 *
1248 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1249 * small page window employeed by that function. Be careful.
1250 * @remark There is no need to assert on the result.
1251 */
1252#ifdef IN_GC
1253# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1254#else
1255# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1256#endif
1257
1258
1259/**
1260 * Trees are using self relative offsets as pointers.
1261 * So, all its data, including the root pointer, must be in the heap for HC and GC
1262 * to have the same layout.
1263 */
1264typedef struct PGMTREES
1265{
1266 /** Physical access handlers (AVL range+offsetptr tree). */
1267 AVLROGCPHYSTREE PhysHandlers;
1268 /** Virtual access handlers (AVL range + GC ptr tree). */
1269 AVLROGCPTRTREE VirtHandlers;
1270 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1271 AVLROGCPHYSTREE PhysToVirtHandlers;
1272 uint32_t auPadding[1];
1273} PGMTREES;
1274/** Pointer to PGM trees. */
1275typedef PGMTREES *PPGMTREES;
1276
1277
1278/** @name Paging mode macros
1279 * @{ */
1280#ifdef IN_GC
1281# define PGM_CTX(a,b) a##GC##b
1282# define PGM_CTX_STR(a,b) a "GC" b
1283# define PGM_CTX_DECL(type) PGMGCDECL(type)
1284#else
1285# ifdef IN_RING3
1286# define PGM_CTX(a,b) a##R3##b
1287# define PGM_CTX_STR(a,b) a "R3" b
1288# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1289# else
1290# define PGM_CTX(a,b) a##R0##b
1291# define PGM_CTX_STR(a,b) a "R0" b
1292# define PGM_CTX_DECL(type) PGMDECL(type)
1293# endif
1294#endif
1295
1296#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1297#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1298#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1299#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1300#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1301#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1302#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1303#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1304#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1305#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1306#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1307#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1308#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1309#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1310#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1311#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1312#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1313
1314#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1315#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1316#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1317#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1318#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1319#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1320#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1321#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1322#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1323#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1324#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1325
1326/* Shw_Gst */
1327#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1328#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1329#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1330#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1331#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1332#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1333#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1334#define PGM_BTH_NAME_AMD64_REAL(name) PGM_CTX(pgm,BthAMD64Real##name)
1335#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1336#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1337#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1338#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1339#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1340#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1341#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1342#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1343#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1344#define PGM_BTH_NAME_GC_AMD64_REAL_STR(name) "pgmGCBthAMD64Real" #name
1345#define PGM_BTH_NAME_GC_AMD64_PROT_STR(name) "pgmGCBthAMD64Prot" #name
1346#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1347#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1348#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1349#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1350#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1351#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1352#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1353#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1354#define PGM_BTH_NAME_R0_AMD64_REAL_STR(name) "pgmR0BthAMD64Real" #name
1355#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1356#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1357#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1358#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1359/** @} */
1360
1361/**
1362 * Data for each paging mode.
1363 */
1364typedef struct PGMMODEDATA
1365{
1366 /** The guest mode type. */
1367 uint32_t uGstType;
1368 /** The shadow mode type. */
1369 uint32_t uShwType;
1370
1371 /** @name Function pointers for Shadow paging.
1372 * @{
1373 */
1374 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1375 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1376 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1377 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1378 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1379 DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1380 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1381
1382 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1383 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1384 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1385 DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1386 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1387
1388 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1389 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1390 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1391 DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1392 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1393 /** @} */
1394
1395 /** @name Function pointers for Guest paging.
1396 * @{
1397 */
1398 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1399 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1400 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1401 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1402 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1403 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1404 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1405 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1406 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1407 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1408 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1409 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1410 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1411
1412 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1413 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1414 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1415 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1416 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1417 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1418 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1419 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1420 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1421
1422 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1423 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1424 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1425 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1426 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1427 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1428 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1429 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1430 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1431 /** @} */
1432
1433 /** @name Function pointers for Both Shadow and Guest paging.
1434 * @{
1435 */
1436 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1437 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1438 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1439 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1440 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1441 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1442 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1443#ifdef VBOX_STRICT
1444 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1445#endif
1446
1447 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1448 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1449 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1450 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1451 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1452 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1453#ifdef VBOX_STRICT
1454 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1455#endif
1456
1457 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1458 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1459 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1460 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1461 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1462 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1463#ifdef VBOX_STRICT
1464 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1465#endif
1466 /** @} */
1467} PGMMODEDATA, *PPGMMODEDATA;
1468
1469
1470
1471/**
1472 * Converts a PGM pointer into a VM pointer.
1473 * @returns Pointer to the VM structure the PGM is part of.
1474 * @param pPGM Pointer to PGM instance data.
1475 */
1476#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1477
1478/**
1479 * PGM Data (part of VM)
1480 */
1481typedef struct PGM
1482{
1483 /** Offset to the VM structure. */
1484 RTINT offVM;
1485
1486 /*
1487 * This will be redefined at least two more times before we're done, I'm sure.
1488 * The current code is only to get on with the coding.
1489 * - 2004-06-10: initial version, bird.
1490 * - 2004-07-02: 1st time, bird.
1491 * - 2004-10-18: 2nd time, bird.
1492 * - 2005-07-xx: 3rd time, bird.
1493 */
1494
1495 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1496 GCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1497 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1498 GCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1499
1500 /** The host paging mode. (This is what SUPLib reports.) */
1501 SUPPAGINGMODE enmHostMode;
1502 /** The shadow paging mode. */
1503 PGMMODE enmShadowMode;
1504 /** The guest paging mode. */
1505 PGMMODE enmGuestMode;
1506
1507 /** The current physical address representing in the guest CR3 register. */
1508 RTGCPHYS GCPhysCR3;
1509 /** Pointer to the 5 page CR3 content mapping.
1510 * The first page is always the CR3 (in some form) while the 4 other pages
1511 * are used of the PDs in PAE mode. */
1512 RTGCPTR GCPtrCR3Mapping;
1513 /** The physical address of the currently monitored guest CR3 page.
1514 * When this value is NIL_RTGCPHYS no page is being monitored. */
1515 RTGCPHYS GCPhysGstCR3Monitored;
1516#if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
1517 RTGCPHYS GCPhysPadding0; /**< alignment padding. */
1518#endif
1519
1520 /** @name 32-bit Guest Paging.
1521 * @{ */
1522 /** The guest's page directory, HC pointer. */
1523 R3R0PTRTYPE(PVBOXPD) pGuestPDHC;
1524 /** The guest's page directory, static GC mapping. */
1525 GCPTRTYPE(PVBOXPD) pGuestPDGC;
1526 /** @} */
1527
1528 /** @name PAE Guest Paging.
1529 * @{ */
1530 /** The guest's page directory pointer table, static GC mapping. */
1531 GCPTRTYPE(PX86PDPTR) pGstPaePDPTRGC;
1532 /** The guest's page directory pointer table, HC pointer. */
1533 R3R0PTRTYPE(PX86PDPTR) pGstPaePDPTRHC;
1534 /** The guest's page directories, HC pointers.
1535 * These are individual pointers and doesn't have to be adjecent.
1536 * These doesn't have to be update to date - use pgmGstGetPaePD() to access them. */
1537 R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1538 /** The guest's page directories, static GC mapping.
1539 * Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1540 * These doesn't have to be update to date - use pgmGstGetPaePD() to access them. */
1541 GCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1542 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1543 RTGCPHYS aGCPhysGstPaePDs[4];
1544 /** The physical addresses of the monitored guest page directories (PAE). */
1545 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1546 /** @} */
1547
1548
1549 /** @name 32-bit Shadow Paging
1550 * @{ */
1551 /** The 32-Bit PD - HC Ptr. */
1552 R3R0PTRTYPE(PX86PD) pHC32BitPD;
1553 /** The 32-Bit PD - GC Ptr. */
1554 GCPTRTYPE(PX86PD) pGC32BitPD;
1555#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1556 uint32_t u32Padding1; /**< alignment padding. */
1557#endif
1558 /** The Physical Address (HC) of the 32-Bit PD. */
1559 RTHCPHYS HCPhys32BitPD;
1560 /** @} */
1561
1562 /** @name PAE Shadow Paging
1563 * @{ */
1564 /** The four PDs for the low 4GB - HC Ptr.
1565 * Even though these are 4 pointers, what they point at is a single table.
1566 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
1567 R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
1568 /** The four PDs for the low 4GB - GC Ptr.
1569 * Same kind of mapping as apHCPaePDs. */
1570 GCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
1571 /** The Physical Address (HC) of the four PDs for the low 4GB.
1572 * These are *NOT* 4 contiguous pages. */
1573 RTHCPHYS aHCPhysPaePDs[4];
1574 /** The PAE PDPTR - HC Ptr. */
1575 R3R0PTRTYPE(PX86PDPTR) pHCPaePDPTR;
1576 /** The Physical Address (HC) of the PAE PDPTR. */
1577 RTHCPHYS HCPhysPaePDPTR;
1578 /** The PAE PDPTR - GC Ptr. */
1579 GCPTRTYPE(PX86PDPTR) pGCPaePDPTR;
1580 /** @} */
1581
1582 /** @name AMD64 Shadow Paging
1583 * Extends PAE Paging.
1584 * @{ */
1585 /** The Page Map Level 4 table - HC Ptr. */
1586 GCPTRTYPE(PX86PML4) pGCPaePML4;
1587 /** The Page Map Level 4 table - GC Ptr. */
1588 R3R0PTRTYPE(PX86PML4) pHCPaePML4;
1589 /** The Physical Address (HC) of the Page Map Level 4 table. */
1590 RTHCPHYS HCPhysPaePML4;
1591 /** @}*/
1592
1593 /** @name Function pointers for Shadow paging.
1594 * @{
1595 */
1596 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1597 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1598 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1599 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1600 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1601 DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1602 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1603
1604 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1605 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1606 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1607 DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1608 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1609#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1610 RTGCPTR alignment0; /**< structure size alignment. */
1611#endif
1612
1613 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1614 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1615 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1616 DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1617 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1618
1619 /** @} */
1620
1621 /** @name Function pointers for Guest paging.
1622 * @{
1623 */
1624 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1625 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1626 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1627 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1628 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1629 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1630 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1631 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1632 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1633 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1634 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1635 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1636 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1637
1638 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1639 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1640 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1641 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1642 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1643 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1644 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1645 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1646 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1647#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1648 RTGCPTR alignment3; /**< structure size alignment. */
1649#endif
1650
1651 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1652 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1653 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1654 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1655 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1656 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1657 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1658 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1659 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1660 /** @} */
1661
1662 /** @name Function pointers for Both Shadow and Guest paging.
1663 * @{
1664 */
1665 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1666 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1667 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1668 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1669 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1670 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1671 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1672 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1673
1674 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1675 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1676 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1677 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1678 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1679 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1680 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1681
1682 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1683 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1684 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1685 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1686 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1687 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1688 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1689#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1690 RTGCPTR alignment2; /**< structure size alignment. */
1691#endif
1692 /** @} */
1693
1694 /** Pointer to SHW+GST mode data (function pointers).
1695 * The index into this table is made up from */
1696 R3PTRTYPE(PPGMMODEDATA) paModeData;
1697
1698
1699 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for HC.
1700 * This is sorted by physical address and contains no overlaps.
1701 * The memory locks and other conversions are managed by MM at the moment.
1702 */
1703 R3R0PTRTYPE(PPGMRAMRANGE) pRamRangesHC;
1704 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for GC.
1705 * This is sorted by physical address and contains no overlaps.
1706 * The memory locks and other conversions are managed by MM at the moment.
1707 */
1708 GCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
1709 /** The configured RAM size. */
1710 RTUINT cbRamSize;
1711
1712 /** PGM offset based trees - HC Ptr. */
1713 R3R0PTRTYPE(PPGMTREES) pTreesHC;
1714 /** PGM offset based trees - GC Ptr. */
1715 GCPTRTYPE(PPGMTREES) pTreesGC;
1716
1717 /** Linked list of GC mappings - for GC.
1718 * The list is sorted ascending on address.
1719 */
1720 GCPTRTYPE(PPGMMAPPING) pMappingsGC;
1721 /** Linked list of GC mappings - for HC.
1722 * The list is sorted ascending on address.
1723 */
1724 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
1725 /** Linked list of GC mappings - for R0.
1726 * The list is sorted ascending on address.
1727 */
1728 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
1729
1730 /** If set no conflict checks are required. (boolean) */
1731 bool fMappingsFixed;
1732 /** If set, then no mappings are put into the shadow page table. (boolean) */
1733 bool fDisableMappings;
1734 /** Size of fixed mapping */
1735 uint32_t cbMappingFixed;
1736 /** Base address (GC) of fixed mapping */
1737 RTGCPTR GCPtrMappingFixed;
1738#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1739 uint32_t u32Padding0; /**< alignment padding. */
1740#endif
1741
1742
1743 /** @name Intermediate Context
1744 * @{ */
1745 /** Pointer to the intermediate page directory - Normal. */
1746 R3PTRTYPE(PX86PD) pInterPD;
1747 /** Pointer to the intermedate page tables - Normal.
1748 * There are two page tables, one for the identity mapping and one for
1749 * the host context mapping (of the core code). */
1750 R3PTRTYPE(PX86PT) apInterPTs[2];
1751 /** Pointer to the intermedate page tables - PAE. */
1752 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
1753 /** Pointer to the intermedate page directory - PAE. */
1754 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
1755 /** Pointer to the intermedate page directory - PAE. */
1756 R3PTRTYPE(PX86PDPTR) pInterPaePDPTR;
1757 /** Pointer to the intermedate page-map level 4 - AMD64. */
1758 R3PTRTYPE(PX86PML4) pInterPaePML4;
1759 /** Pointer to the intermedate page directory - AMD64. */
1760 R3PTRTYPE(PX86PDPTR) pInterPaePDPTR64;
1761 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
1762 RTHCPHYS HCPhysInterPD;
1763 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
1764 RTHCPHYS HCPhysInterPaePDPTR;
1765 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
1766 RTHCPHYS HCPhysInterPaePML4;
1767 /** @} */
1768
1769 /** Base address of the dynamic page mapping area.
1770 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
1771 */
1772 GCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
1773 /** The index of the last entry used in the dynamic page mapping area. */
1774 RTUINT iDynPageMapLast;
1775 /** Cache containing the last entries in the dynamic page mapping area.
1776 * The cache size is covering half of the mapping area. */
1777 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
1778
1779 /** A20 gate mask.
1780 * Our current approach to A20 emulation is to let REM do it and don't bother
1781 * anywhere else. The interesting Guests will be operating with it enabled anyway.
1782 * But whould need arrise, we'll subject physical addresses to this mask. */
1783 RTGCPHYS GCPhysA20Mask;
1784 /** A20 gate state - boolean! */
1785 RTUINT fA20Enabled;
1786
1787 /** What needs syncing (PGM_SYNC_*).
1788 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
1789 * PGMFlushTLB, and PGMR3Load. */
1790 RTUINT fSyncFlags;
1791
1792#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1793 RTUINT uPadding3; /**< alignment padding. */
1794#endif
1795 /** PGM critical section.
1796 * This protects the physical & virtual access handlers, ram ranges,
1797 * and the page flag updating (some of it anyway).
1798 */
1799 PDMCRITSECT CritSect;
1800
1801 /** Shadow Page Pool - HC Ptr. */
1802 R3R0PTRTYPE(PPGMPOOL) pPoolHC;
1803 /** Shadow Page Pool - GC Ptr. */
1804 GCPTRTYPE(PPGMPOOL) pPoolGC;
1805
1806 /** We're not in a state which permits writes to guest memory.
1807 * (Only used in strict builds.) */
1808 bool fNoMorePhysWrites;
1809
1810 /** Flush the cache on the next access. */
1811 bool fPhysCacheFlushPending;
1812/** @todo r=bird: Fix member names!*/
1813 /** PGMPhysRead cache */
1814 PGMPHYSCACHE pgmphysreadcache;
1815 /** PGMPhysWrite cache */
1816 PGMPHYSCACHE pgmphyswritecache;
1817
1818 /**
1819 * Data associated with managing the ring-3 mappings of the allocation chunks.
1820 */
1821 struct
1822 {
1823 /** The chunk tree, ordered by chunk id. */
1824 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
1825 /** The chunk mapping TLB. */
1826 PGMCHUNKR3MAPTLB Tlb;
1827 /** The number of mapped chunks. */
1828 uint32_t c;
1829 /** The maximum number of mapped chunks.
1830 * @cfgm PGM/MaxRing3Chunks */
1831 uint32_t cMax;
1832 /** The chunk age tree, ordered by ageing sequence number. */
1833 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
1834 /** The current time. */
1835 uint32_t iNow;
1836 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
1837 uint32_t AgeingCountdown;
1838 } ChunkR3Map;
1839
1840 /**
1841 * The page mapping TLB for ring-3 and (for the time being) ring-0.
1842 */
1843 PGMPAGER3MAPTLB PhysTlbHC;
1844
1845 /** @name The zero page.
1846 * @{ */
1847 /** The host physical address of the zero page. */
1848 RTHCPHYS HCPhysZeroPg;
1849 /** The ring-3 mapping of the zero page. */
1850 RTR3PTR pvZeroPgR3;
1851 /** The ring-0 mapping of the zero page. */
1852 RTR0PTR pvZeroPgR0;
1853 /** The GC mapping of the zero page. */
1854 RTGCPTR pvZeroPgGC;
1855#if GC_ARCH_BITS != 32
1856 uint32_t u32ZeroAlignment; /**< Alignment padding. */
1857#endif
1858 /** @}*/
1859
1860 /** The number of handy pages. */
1861 uint32_t cHandyPages;
1862 /**
1863 * Array of handy pages.
1864 *
1865 * This array is used in a two way communication between pgmPhysAllocPage
1866 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
1867 * an intermediary.
1868 *
1869 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
1870 * (The current size of 32 pages, means 128 KB of handy memory.)
1871 */
1872 GMMPAGEDESC aHandyPages[32];
1873
1874 /** @name Release Statistics
1875 * @{ */
1876 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
1877 uint32_t cPrivatePages; /**< The number of private pages. */
1878 uint32_t cSharedPages; /**< The number of shared pages. */
1879 uint32_t cZeroPages; /**< The number of zero backed pages. */
1880 /** The number of times the guest has switched mode since last reset or statistics reset. */
1881 STAMCOUNTER cGuestModeChanges;
1882 /** @} */
1883
1884#ifdef VBOX_WITH_STATISTICS
1885 /** GC: Which statistic this \#PF should be attributed to. */
1886 GCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
1887 RTGCPTR padding0;
1888 /** HC: Which statistic this \#PF should be attributed to. */
1889 R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
1890 RTHCPTR padding1;
1891 STAMPROFILE StatGCTrap0e; /**< GC: PGMGCTrap0eHandler() profiling. */
1892 STAMPROFILE StatTrap0eCSAM; /**< Profiling of the Trap0eHandler body when the cause is CSAM. */
1893 STAMPROFILE StatTrap0eDirtyAndAccessedBits; /**< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
1894 STAMPROFILE StatTrap0eGuestTrap; /**< Profiling of the Trap0eHandler body when the cause is a guest trap. */
1895 STAMPROFILE StatTrap0eHndPhys; /**< Profiling of the Trap0eHandler body when the cause is a physical handler. */
1896 STAMPROFILE StatTrap0eHndVirt; /**< Profiling of the Trap0eHandler body when the cause is a virtual handler. */
1897 STAMPROFILE StatTrap0eHndUnhandled; /**< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
1898 STAMPROFILE StatTrap0eMisc; /**< Profiling of the Trap0eHandler body when the cause is not known. */
1899 STAMPROFILE StatTrap0eOutOfSync; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
1900 STAMPROFILE StatTrap0eOutOfSyncHndPhys; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
1901 STAMPROFILE StatTrap0eOutOfSyncHndVirt; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
1902 STAMPROFILE StatTrap0eOutOfSyncObsHnd; /**< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
1903 STAMPROFILE StatTrap0eSyncPT; /**< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
1904
1905 STAMCOUNTER StatTrap0eMapHandler; /**< Number of traps due to access handlers in mappings. */
1906 STAMCOUNTER StatGCTrap0eConflicts; /**< GC: The number of times \#PF was caused by an undetected conflict. */
1907
1908 STAMCOUNTER StatGCTrap0eUSNotPresentRead;
1909 STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
1910 STAMCOUNTER StatGCTrap0eUSWrite;
1911 STAMCOUNTER StatGCTrap0eUSReserved;
1912 STAMCOUNTER StatGCTrap0eUSRead;
1913
1914 STAMCOUNTER StatGCTrap0eSVNotPresentRead;
1915 STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
1916 STAMCOUNTER StatGCTrap0eSVWrite;
1917 STAMCOUNTER StatGCTrap0eSVReserved;
1918
1919 STAMCOUNTER StatGCTrap0eUnhandled;
1920 STAMCOUNTER StatGCTrap0eMap;
1921
1922 /** GC: PGMSyncPT() profiling. */
1923 STAMPROFILE StatGCSyncPT;
1924 /** GC: The number of times PGMSyncPT() needed to allocate page tables. */
1925 STAMCOUNTER StatGCSyncPTAlloc;
1926 /** GC: The number of times PGMSyncPT() detected conflicts. */
1927 STAMCOUNTER StatGCSyncPTConflict;
1928 /** GC: The number of times PGMSyncPT() failed. */
1929 STAMCOUNTER StatGCSyncPTFailed;
1930 /** GC: PGMGCInvalidatePage() profiling. */
1931 STAMPROFILE StatGCInvalidatePage;
1932 /** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
1933 STAMCOUNTER StatGCInvalidatePage4KBPages;
1934 /** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
1935 STAMCOUNTER StatGCInvalidatePage4MBPages;
1936 /** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
1937 STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
1938 /** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
1939 STAMCOUNTER StatGCInvalidatePagePDNAs;
1940 /** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
1941 STAMCOUNTER StatGCInvalidatePagePDNPs;
1942 /** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
1943 STAMCOUNTER StatGCInvalidatePagePDMappings;
1944 /** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
1945 STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
1946 /** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
1947 STAMCOUNTER StatGCInvalidatePageSkipped;
1948 /** GC: The number of times user page is out of sync was detected in GC. */
1949 STAMCOUNTER StatGCPageOutOfSyncUser;
1950 /** GC: The number of times supervisor page is out of sync was detected in GC. */
1951 STAMCOUNTER StatGCPageOutOfSyncSupervisor;
1952 /** GC: The number of dynamic page mapping cache hits */
1953 STAMCOUNTER StatDynMapCacheMisses;
1954 /** GC: The number of dynamic page mapping cache misses */
1955 STAMCOUNTER StatDynMapCacheHits;
1956 /** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
1957 STAMCOUNTER StatGCGuestCR3WriteHandled;
1958 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
1959 STAMCOUNTER StatGCGuestCR3WriteUnhandled;
1960 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
1961 STAMCOUNTER StatGCGuestCR3WriteConflict;
1962 /** GC: Number of out-of-sync handled pages. */
1963 STAMCOUNTER StatHandlersOutOfSync;
1964 /** GC: Number of traps due to physical access handlers. */
1965 STAMCOUNTER StatHandlersPhysical;
1966 /** GC: Number of traps due to virtual access handlers. */
1967 STAMCOUNTER StatHandlersVirtual;
1968 /** GC: Number of traps due to virtual access handlers found by physical address. */
1969 STAMCOUNTER StatHandlersVirtualByPhys;
1970 /** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
1971 STAMCOUNTER StatHandlersVirtualUnmarked;
1972 /** GC: Number of traps due to access outside range of monitored page(s). */
1973 STAMCOUNTER StatHandlersUnhandled;
1974
1975 /** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
1976 STAMCOUNTER StatGCGuestROMWriteHandled;
1977 /** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
1978 STAMCOUNTER StatGCGuestROMWriteUnhandled;
1979
1980 /** HC: PGMR3InvalidatePage() profiling. */
1981 STAMPROFILE StatHCInvalidatePage;
1982 /** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
1983 STAMCOUNTER StatHCInvalidatePage4KBPages;
1984 /** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
1985 STAMCOUNTER StatHCInvalidatePage4MBPages;
1986 /** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
1987 STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
1988 /** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
1989 STAMCOUNTER StatHCInvalidatePagePDNAs;
1990 /** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
1991 STAMCOUNTER StatHCInvalidatePagePDNPs;
1992 /** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
1993 STAMCOUNTER StatHCInvalidatePagePDMappings;
1994 /** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
1995 STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
1996 /** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
1997 STAMCOUNTER StatHCInvalidatePageSkipped;
1998 /** HC: PGMR3SyncPT() profiling. */
1999 STAMPROFILE StatHCSyncPT;
2000 /** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2001 STAMPROFILE StatHCResolveConflict;
2002 /** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2003 STAMCOUNTER StatHCDetectedConflicts;
2004 /** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2005 STAMCOUNTER StatHCGuestPDWrite;
2006 /** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2007 STAMCOUNTER StatHCGuestPDWriteConflict;
2008
2009 /** HC: The number of pages marked not present for accessed bit emulation. */
2010 STAMCOUNTER StatHCAccessedPage;
2011 /** HC: The number of pages marked read-only for dirty bit tracking. */
2012 STAMCOUNTER StatHCDirtyPage;
2013 /** HC: The number of pages marked read-only for dirty bit tracking. */
2014 STAMCOUNTER StatHCDirtyPageBig;
2015 /** HC: The number of traps generated for dirty bit tracking. */
2016 STAMCOUNTER StatHCDirtyPageTrap;
2017 /** HC: The number of pages already dirty or readonly. */
2018 STAMCOUNTER StatHCDirtyPageSkipped;
2019
2020 /** GC: The number of pages marked not present for accessed bit emulation. */
2021 STAMCOUNTER StatGCAccessedPage;
2022 /** GC: The number of pages marked read-only for dirty bit tracking. */
2023 STAMCOUNTER StatGCDirtyPage;
2024 /** GC: The number of pages marked read-only for dirty bit tracking. */
2025 STAMCOUNTER StatGCDirtyPageBig;
2026 /** GC: The number of traps generated for dirty bit tracking. */
2027 STAMCOUNTER StatGCDirtyPageTrap;
2028 /** GC: The number of pages already dirty or readonly. */
2029 STAMCOUNTER StatGCDirtyPageSkipped;
2030 /** GC: The number of pages marked dirty because of write accesses. */
2031 STAMCOUNTER StatGCDirtiedPage;
2032 /** GC: The number of pages already marked dirty because of write accesses. */
2033 STAMCOUNTER StatGCPageAlreadyDirty;
2034 /** GC: The number of real pages faults during dirty bit tracking. */
2035 STAMCOUNTER StatGCDirtyTrackRealPF;
2036
2037 /** GC: Profiling of the PGMTrackDirtyBit() body */
2038 STAMPROFILE StatGCDirtyBitTracking;
2039 /** HC: Profiling of the PGMTrackDirtyBit() body */
2040 STAMPROFILE StatHCDirtyBitTracking;
2041
2042 /** GC: Profiling of the PGMGstModifyPage() body */
2043 STAMPROFILE StatGCGstModifyPage;
2044 /** HC: Profiling of the PGMGstModifyPage() body */
2045 STAMPROFILE StatHCGstModifyPage;
2046
2047 /** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2048 STAMCOUNTER StatGCSyncPagePDNAs;
2049 /** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2050 STAMCOUNTER StatGCSyncPagePDOutOfSync;
2051 /** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2052 STAMCOUNTER StatHCSyncPagePDNAs;
2053 /** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2054 STAMCOUNTER StatHCSyncPagePDOutOfSync;
2055
2056 STAMCOUNTER StatSynPT4kGC;
2057 STAMCOUNTER StatSynPT4kHC;
2058 STAMCOUNTER StatSynPT4MGC;
2059 STAMCOUNTER StatSynPT4MHC;
2060
2061 /** Profiling of the PGMFlushTLB() body. */
2062 STAMPROFILE StatFlushTLB;
2063 /** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2064 STAMCOUNTER StatFlushTLBNewCR3;
2065 /** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2066 STAMCOUNTER StatFlushTLBNewCR3Global;
2067 /** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2068 STAMCOUNTER StatFlushTLBSameCR3;
2069 /** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2070 STAMCOUNTER StatFlushTLBSameCR3Global;
2071
2072 STAMPROFILE StatGCSyncCR3; /**< GC: PGMSyncCR3() profiling. */
2073 STAMPROFILE StatGCSyncCR3Handlers; /**< GC: Profiling of the PGMSyncCR3() update handler section. */
2074 STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /**< GC: Profiling of the virtual handler resets. */
2075 STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /**< GC: Profiling of the virtual handler updates. */
2076 STAMCOUNTER StatGCSyncCR3Global; /**< GC: The number of global CR3 syncs. */
2077 STAMCOUNTER StatGCSyncCR3NotGlobal; /**< GC: The number of non-global CR3 syncs. */
2078 STAMCOUNTER StatGCSyncCR3DstFreed; /**< GC: The number of times we've had to free a shadow entry. */
2079 STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /**< GC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2080 STAMCOUNTER StatGCSyncCR3DstNotPresent; /**< GC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2081 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /**< GC: The number of times a global page directory wasn't flushed. */
2082 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /**< GC: The number of times a page table with only global entries wasn't flushed. */
2083 STAMCOUNTER StatGCSyncCR3DstCacheHit; /**< GC: The number of times we got some kind of cache hit on a page table. */
2084
2085 STAMPROFILE StatHCSyncCR3; /**< HC: PGMSyncCR3() profiling. */
2086 STAMPROFILE StatHCSyncCR3Handlers; /**< HC: Profiling of the PGMSyncCR3() update handler section. */
2087 STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /**< HC: Profiling of the virtual handler resets. */
2088 STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /**< HC: Profiling of the virtual handler updates. */
2089 STAMCOUNTER StatHCSyncCR3Global; /**< HC: The number of global CR3 syncs. */
2090 STAMCOUNTER StatHCSyncCR3NotGlobal; /**< HC: The number of non-global CR3 syncs. */
2091 STAMCOUNTER StatHCSyncCR3DstFreed; /**< HC: The number of times we've had to free a shadow entry. */
2092 STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /**< HC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2093 STAMCOUNTER StatHCSyncCR3DstNotPresent; /**< HC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2094 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /**< HC: The number of times a global page directory wasn't flushed. */
2095 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /**< HC: The number of times a page table with only global entries wasn't flushed. */
2096 STAMCOUNTER StatHCSyncCR3DstCacheHit; /**< HC: The number of times we got some kind of cache hit on a page table. */
2097
2098 /** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2099 STAMPROFILE StatVirtHandleSearchByPhysGC;
2100 /** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2101 STAMPROFILE StatVirtHandleSearchByPhysHC;
2102 /** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2103 STAMCOUNTER StatHandlePhysicalReset;
2104
2105 STAMPROFILE StatCheckPageFault;
2106 STAMPROFILE StatLazySyncPT;
2107 STAMPROFILE StatMapping;
2108 STAMPROFILE StatOutOfSync;
2109 STAMPROFILE StatHandlers;
2110 STAMPROFILE StatEIPHandlers;
2111 STAMPROFILE StatHCPrefetch;
2112
2113# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2114 /** The number of first time shadowings. */
2115 STAMCOUNTER StatTrackVirgin;
2116 /** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2117 STAMCOUNTER StatTrackAliased;
2118 /** The number of times we're tracking using cRef2. */
2119 STAMCOUNTER StatTrackAliasedMany;
2120 /** The number of times we're hitting pages which has overflowed cRef2. */
2121 STAMCOUNTER StatTrackAliasedLots;
2122 /** The number of times the extent list grows to long. */
2123 STAMCOUNTER StatTrackOverflows;
2124 /** Profiling of SyncPageWorkerTrackDeref (expensive). */
2125 STAMPROFILE StatTrackDeref;
2126# endif
2127
2128 /** Ring-3/0 page mapper TLB hits. */
2129 STAMCOUNTER StatPageHCMapTlbHits;
2130 /** Ring-3/0 page mapper TLB misses. */
2131 STAMCOUNTER StatPageHCMapTlbMisses;
2132 /** Ring-3/0 chunk mapper TLB hits. */
2133 STAMCOUNTER StatChunkR3MapTlbHits;
2134 /** Ring-3/0 chunk mapper TLB misses. */
2135 STAMCOUNTER StatChunkR3MapTlbMisses;
2136 /** Times a shared page has been replaced by a private one. */
2137 STAMCOUNTER StatPageReplaceShared;
2138 /** Times the zero page has been replaced by a private one. */
2139 STAMCOUNTER StatPageReplaceZero;
2140 /** The number of times we've executed GMMR3AllocateHandyPages. */
2141 STAMCOUNTER StatPageHandyAllocs;
2142
2143 /** Allocated mbs of guest ram */
2144 STAMCOUNTER StatDynRamTotal;
2145 /** Nr of pgmr3PhysGrowRange calls. */
2146 STAMCOUNTER StatDynRamGrow;
2147
2148 STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2149 STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2150 STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2151#endif
2152} PGM, *PPGM;
2153
2154
2155/** @name PGM::fSyncFlags Flags
2156 * @{
2157 */
2158/** Updates the MM_RAM_FLAGS_VIRTUAL_HANDLER page bit. */
2159#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2160/** Always sync CR3. */
2161#define PGM_SYNC_ALWAYS RT_BIT(1)
2162/** Check monitoring on next CR3 (re)load and invalidate page. */
2163#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2164/** Clear the page pool (a light weight flush). */
2165#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2166/** @} */
2167
2168
2169__BEGIN_DECLS
2170
2171PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2172PGMDECL(int) pgmGuestROMWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2173PGMGCDECL(int) pgmCachePTWriteGC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2174int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PVBOXPD pPDSrc, int iPDOld);
2175PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2176void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, int iPDOld, int iPDNew);
2177int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
2178int pgmLock(PVM pVM);
2179void pgmUnlock(PVM pVM);
2180
2181void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2182int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2183DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2184#ifdef VBOX_STRICT
2185void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2186#else
2187# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2188#endif
2189DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2190
2191
2192int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2193#ifdef IN_RING3
2194int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2195#ifndef VBOX_WITH_NEW_PHYS_CODE
2196int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2197#endif
2198
2199int pgmR3PoolInit(PVM pVM);
2200void pgmR3PoolRelocate(PVM pVM);
2201void pgmR3PoolReset(PVM pVM);
2202
2203#endif /* IN_RING3 */
2204#ifdef IN_GC
2205void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2206#endif
2207int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage);
2208PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2209void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint16_t iUserTable);
2210void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable);
2211int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2212void pgmPoolFlushAll(PVM pVM);
2213void pgmPoolClearAll(PVM pVM);
2214void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2215void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2216int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2217PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2218void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2219void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2220uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2221void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2222#ifdef PGMPOOL_WITH_MONITORING
2223# ifdef IN_RING3
2224void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2225# else
2226void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2227# endif
2228int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2229void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2230void pgmPoolMonitorModifiedClearAll(PVM pVM);
2231int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2232int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2233#endif
2234
2235__END_DECLS
2236
2237
2238/**
2239 * Gets the PGMPAGE structure for a guest page.
2240 *
2241 * @returns Pointer to the page on success.
2242 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2243 *
2244 * @param pPGM PGM handle.
2245 * @param GCPhys The GC physical address.
2246 */
2247DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2248{
2249 /*
2250 * Optimize for the first range.
2251 */
2252 PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges);
2253 RTGCPHYS off = GCPhys - pRam->GCPhys;
2254 if (RT_UNLIKELY(off >= pRam->cb))
2255 {
2256 do
2257 {
2258 pRam = CTXSUFF(pRam->pNext);
2259 if (RT_UNLIKELY(!pRam))
2260 return NULL;
2261 off = GCPhys - pRam->GCPhys;
2262 } while (off >= pRam->cb);
2263 }
2264 return &pRam->aPages[off >> PAGE_SHIFT];
2265}
2266
2267
2268/**
2269 * Gets the PGMPAGE structure for a guest page.
2270 *
2271 * Old Phys code: Will make sure the page is present.
2272 *
2273 * @returns VBox status code.
2274 * @retval VINF_SUCCESS and a valid *ppPage on success.
2275 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2276 *
2277 * @param pPGM PGM handle.
2278 * @param GCPhys The GC physical address.
2279 * @param ppPage Where to store the page poitner on success.
2280 */
2281DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2282{
2283 /*
2284 * Optimize for the first range.
2285 */
2286 PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges);
2287 RTGCPHYS off = GCPhys - pRam->GCPhys;
2288 if (RT_UNLIKELY(off >= pRam->cb))
2289 {
2290 do
2291 {
2292 pRam = CTXSUFF(pRam->pNext);
2293 if (RT_UNLIKELY(!pRam))
2294 {
2295 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2296 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2297 }
2298 off = GCPhys - pRam->GCPhys;
2299 } while (off >= pRam->cb);
2300 }
2301 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2302#ifndef VBOX_WITH_NEW_PHYS_CODE
2303
2304 /*
2305 * Make sure it's present.
2306 */
2307 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2308 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2309 {
2310#ifdef IN_RING3
2311 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2312#else
2313 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2314#endif
2315 if (VBOX_FAILURE(rc))
2316 {
2317 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2318 return rc;
2319 }
2320 Assert(rc == VINF_SUCCESS);
2321 }
2322#endif
2323 return VINF_SUCCESS;
2324}
2325
2326
2327
2328
2329/**
2330 * Gets the PGMPAGE structure for a guest page.
2331 *
2332 * Old Phys code: Will make sure the page is present.
2333 *
2334 * @returns VBox status code.
2335 * @retval VINF_SUCCESS and a valid *ppPage on success.
2336 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2337 *
2338 * @param pPGM PGM handle.
2339 * @param GCPhys The GC physical address.
2340 * @param ppPage Where to store the page poitner on success.
2341 * @param ppRamHint Where to read and store the ram list hint.
2342 * The caller initializes this to NULL before the call.
2343 */
2344DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2345{
2346 RTGCPHYS off;
2347 PPGMRAMRANGE pRam = *ppRamHint;
2348 if ( !pRam
2349 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2350 {
2351 pRam = CTXSUFF(pPGM->pRamRanges);
2352 off = GCPhys - pRam->GCPhys;
2353 if (RT_UNLIKELY(off >= pRam->cb))
2354 {
2355 do
2356 {
2357 pRam = CTXSUFF(pRam->pNext);
2358 if (RT_UNLIKELY(!pRam))
2359 {
2360 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2361 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2362 }
2363 off = GCPhys - pRam->GCPhys;
2364 } while (off >= pRam->cb);
2365 }
2366 *ppRamHint = pRam;
2367 }
2368 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2369#ifndef VBOX_WITH_NEW_PHYS_CODE
2370
2371 /*
2372 * Make sure it's present.
2373 */
2374 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2375 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2376 {
2377#ifdef IN_RING3
2378 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2379#else
2380 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2381#endif
2382 if (VBOX_FAILURE(rc))
2383 {
2384 *ppPage = NULL; /* Shut up annoying smart ass. */
2385 return rc;
2386 }
2387 Assert(rc == VINF_SUCCESS);
2388 }
2389#endif
2390 return VINF_SUCCESS;
2391}
2392
2393
2394/**
2395 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2396 *
2397 * @returns Pointer to the page on success.
2398 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2399 *
2400 * @param pPGM PGM handle.
2401 * @param GCPhys The GC physical address.
2402 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
2403 */
2404DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2405{
2406 /*
2407 * Optimize for the first range.
2408 */
2409 PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges);
2410 RTGCPHYS off = GCPhys - pRam->GCPhys;
2411 if (RT_UNLIKELY(off >= pRam->cb))
2412 {
2413 do
2414 {
2415 pRam = CTXSUFF(pRam->pNext);
2416 if (RT_UNLIKELY(!pRam))
2417 return NULL;
2418 off = GCPhys - pRam->GCPhys;
2419 } while (off >= pRam->cb);
2420 }
2421 *ppRam = pRam;
2422 return &pRam->aPages[off >> PAGE_SHIFT];
2423}
2424
2425
2426
2427
2428/**
2429 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2430 *
2431 * @returns Pointer to the page on success.
2432 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2433 *
2434 * @param pPGM PGM handle.
2435 * @param GCPhys The GC physical address.
2436 * @param ppPage Where to store the pointer to the PGMPAGE structure.
2437 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2438 */
2439DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2440{
2441 /*
2442 * Optimize for the first range.
2443 */
2444 PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges);
2445 RTGCPHYS off = GCPhys - pRam->GCPhys;
2446 if (RT_UNLIKELY(off >= pRam->cb))
2447 {
2448 do
2449 {
2450 pRam = CTXSUFF(pRam->pNext);
2451 if (RT_UNLIKELY(!pRam))
2452 {
2453 *ppRam = NULL; /* Shut up silly GCC warnings. */
2454 *ppPage = NULL; /* ditto */
2455 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2456 }
2457 off = GCPhys - pRam->GCPhys;
2458 } while (off >= pRam->cb);
2459 }
2460 *ppRam = pRam;
2461 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2462#ifndef VBOX_WITH_NEW_PHYS_CODE
2463
2464 /*
2465 * Make sure it's present.
2466 */
2467 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2468 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2469 {
2470#ifdef IN_RING3
2471 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2472#else
2473 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2474#endif
2475 if (VBOX_FAILURE(rc))
2476 {
2477 *ppPage = NULL; /* Shut up silly GCC warnings. */
2478 *ppPage = NULL; /* ditto */
2479 return rc;
2480 }
2481 Assert(rc == VINF_SUCCESS);
2482
2483 }
2484#endif
2485 return VINF_SUCCESS;
2486}
2487
2488
2489/**
2490 * Convert GC Phys to HC Phys.
2491 *
2492 * @returns VBox status.
2493 * @param pPGM PGM handle.
2494 * @param GCPhys The GC physical address.
2495 * @param pHCPhys Where to store the corresponding HC physical address.
2496 *
2497 * @deprecated Doesn't deal with zero, shared or write monitored pages.
2498 * Avoid when writing new code!
2499 */
2500DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2501{
2502 PPGMPAGE pPage;
2503 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2504 if (VBOX_FAILURE(rc))
2505 return rc;
2506 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
2507 return VINF_SUCCESS;
2508}
2509
2510
2511#ifndef IN_GC
2512/**
2513 * Queries the Physical TLB entry for a physical guest page,
2514 * attemting to load the TLB entry if necessary.
2515 *
2516 * @returns VBox status code.
2517 * @retval VINF_SUCCESS on success
2518 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2519 * @param pPGM The PGM instance handle.
2520 * @param GCPhys The address of the guest page.
2521 * @param ppTlbe Where to store the pointer to the TLB entry.
2522 */
2523
2524DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
2525{
2526 int rc;
2527 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
2528 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
2529 {
2530 STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
2531 rc = VINF_SUCCESS;
2532 }
2533 else
2534 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
2535 *ppTlbe = pTlbe;
2536 return rc;
2537}
2538#endif /* !IN_GC */
2539
2540
2541#ifndef VBOX_WITH_NEW_PHYS_CODE
2542/**
2543 * Convert GC Phys to HC Virt.
2544 *
2545 * @returns VBox status.
2546 * @param pPGM PGM handle.
2547 * @param GCPhys The GC physical address.
2548 * @param pHCPtr Where to store the corresponding HC virtual address.
2549 *
2550 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
2551 */
2552DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
2553{
2554 PPGMRAMRANGE pRam;
2555 PPGMPAGE pPage;
2556 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
2557 if (VBOX_FAILURE(rc))
2558 {
2559 *pHCPtr = 0; /* Shut up silly GCC warnings. */
2560 return rc;
2561 }
2562 RTGCPHYS off = GCPhys - pRam->GCPhys;
2563
2564 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2565 {
2566 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
2567 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2568 return VINF_SUCCESS;
2569 }
2570 if (pRam->pvHC)
2571 {
2572 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
2573 return VINF_SUCCESS;
2574 }
2575 *pHCPtr = 0; /* Shut up silly GCC warnings. */
2576 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2577}
2578#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2579
2580
2581/**
2582 * Convert GC Phys to HC Virt.
2583 *
2584 * @returns VBox status.
2585 * @param PVM VM handle.
2586 * @param pRam Ram range
2587 * @param GCPhys The GC physical address.
2588 * @param pHCPtr Where to store the corresponding HC virtual address.
2589 *
2590 * @deprecated This will be eliminated. Don't use it.
2591 */
2592DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
2593{
2594 RTGCPHYS off = GCPhys - pRam->GCPhys;
2595 Assert(off < pRam->cb);
2596
2597 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2598 {
2599 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
2600 /* Physical chunk in dynamically allocated range not present? */
2601 if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
2602 {
2603#ifdef IN_RING3
2604 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2605#else
2606 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2607#endif
2608 if (rc != VINF_SUCCESS)
2609 {
2610 *pHCPtr = 0; /* GCC crap */
2611 return rc;
2612 }
2613 }
2614 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2615 return VINF_SUCCESS;
2616 }
2617 if (pRam->pvHC)
2618 {
2619 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
2620 return VINF_SUCCESS;
2621 }
2622 *pHCPtr = 0; /* GCC crap */
2623 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2624}
2625
2626
2627/**
2628 * Convert GC Phys to HC Virt and HC Phys.
2629 *
2630 * @returns VBox status.
2631 * @param pPGM PGM handle.
2632 * @param GCPhys The GC physical address.
2633 * @param pHCPtr Where to store the corresponding HC virtual address.
2634 * @param pHCPhys Where to store the HC Physical address and its flags.
2635 *
2636 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
2637 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
2638 */
2639DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
2640{
2641 PPGMRAMRANGE pRam;
2642 PPGMPAGE pPage;
2643 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
2644 if (VBOX_FAILURE(rc))
2645 {
2646 *pHCPtr = 0; /* Shut up crappy GCC warnings */
2647 *pHCPhys = 0; /* ditto */
2648 return rc;
2649 }
2650 RTGCPHYS off = GCPhys - pRam->GCPhys;
2651
2652 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
2653 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2654 {
2655 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
2656 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2657 return VINF_SUCCESS;
2658 }
2659 if (pRam->pvHC)
2660 {
2661 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
2662 return VINF_SUCCESS;
2663 }
2664 *pHCPtr = 0;
2665 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2666}
2667
2668
2669/**
2670 * Clears flags associated with a RAM address.
2671 *
2672 * @returns VBox status code.
2673 * @param pPGM PGM handle.
2674 * @param GCPhys Guest context physical address.
2675 * @param fFlags fFlags to clear. (Bits 0-11.)
2676 */
2677DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
2678{
2679 PPGMPAGE pPage;
2680 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2681 if (VBOX_FAILURE(rc))
2682 return rc;
2683
2684 fFlags &= ~X86_PTE_PAE_PG_MASK;
2685 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
2686 return VINF_SUCCESS;
2687}
2688
2689
2690/**
2691 * Clears flags associated with a RAM address.
2692 *
2693 * @returns VBox status code.
2694 * @param pPGM PGM handle.
2695 * @param GCPhys Guest context physical address.
2696 * @param fFlags fFlags to clear. (Bits 0-11.)
2697 * @param ppRamHint Where to read and store the ram list hint.
2698 * The caller initializes this to NULL before the call.
2699 */
2700DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
2701{
2702 PPGMPAGE pPage;
2703 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
2704 if (VBOX_FAILURE(rc))
2705 return rc;
2706
2707 fFlags &= ~X86_PTE_PAE_PG_MASK;
2708 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
2709 return VINF_SUCCESS;
2710}
2711
2712/**
2713 * Sets (bitwise OR) flags associated with a RAM address.
2714 *
2715 * @returns VBox status code.
2716 * @param pPGM PGM handle.
2717 * @param GCPhys Guest context physical address.
2718 * @param fFlags fFlags to set clear. (Bits 0-11.)
2719 */
2720DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
2721{
2722 PPGMPAGE pPage;
2723 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2724 if (VBOX_FAILURE(rc))
2725 return rc;
2726
2727 fFlags &= ~X86_PTE_PAE_PG_MASK;
2728 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
2729 return VINF_SUCCESS;
2730}
2731
2732
2733/**
2734 * Sets (bitwise OR) flags associated with a RAM address.
2735 *
2736 * @returns VBox status code.
2737 * @param pPGM PGM handle.
2738 * @param GCPhys Guest context physical address.
2739 * @param fFlags fFlags to set clear. (Bits 0-11.)
2740 * @param ppRamHint Where to read and store the ram list hint.
2741 * The caller initializes this to NULL before the call.
2742 */
2743DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
2744{
2745 PPGMPAGE pPage;
2746 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
2747 if (VBOX_FAILURE(rc))
2748 return rc;
2749
2750 fFlags &= ~X86_PTE_PAE_PG_MASK;
2751 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
2752 return VINF_SUCCESS;
2753}
2754
2755
2756/**
2757 * Gets the page directory for the specified address.
2758 *
2759 * @returns Pointer to the page directory in question.
2760 * @returns NULL if the page directory is not present or on an invalid page.
2761 * @param pPGM Pointer to the PGM instance data.
2762 * @param GCPtr The address.
2763 */
2764DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
2765{
2766 const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2767 if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2768 {
2769 if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2770 return CTXSUFF(pPGM->apGstPaePDs)[iPdPtr];
2771
2772 /* cache is out-of-sync. */
2773 PX86PDPAE pPD;
2774 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2775 if (VBOX_SUCCESS(rc))
2776 return pPD;
2777 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2778 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
2779 }
2780 return NULL;
2781}
2782
2783
2784/**
2785 * Gets the page directory entry for the specified address.
2786 *
2787 * @returns Pointer to the page directory entry in question.
2788 * @returns NULL if the page directory is not present or on an invalid page.
2789 * @param pPGM Pointer to the PGM instance data.
2790 * @param GCPtr The address.
2791 */
2792DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
2793{
2794 const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2795 if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2796 {
2797 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
2798 if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2799 return &CTXSUFF(pPGM->apGstPaePDs)[iPdPtr]->a[iPD];
2800
2801 /* The cache is out-of-sync. */
2802 PX86PDPAE pPD;
2803 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2804 if (VBOX_SUCCESS(rc))
2805 return &pPD->a[iPD];
2806 AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2807 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
2808 }
2809 return NULL;
2810}
2811
2812
2813/**
2814 * Gets the page directory entry for the specified address.
2815 *
2816 * @returns The page directory entry in question.
2817 * @returns A non-present entry if the page directory is not present or on an invalid page.
2818 * @param pPGM Pointer to the PGM instance data.
2819 * @param GCPtr The address.
2820 */
2821DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
2822{
2823 const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2824 if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2825 {
2826 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
2827 if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2828 return CTXSUFF(pPGM->apGstPaePDs)[iPdPtr]->a[iPD].u;
2829
2830 /* cache is out-of-sync. */
2831 PX86PDPAE pPD;
2832 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2833 if (VBOX_SUCCESS(rc))
2834 return pPD->a[iPD].u;
2835 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2836 }
2837 return 0;
2838}
2839
2840
2841/**
2842 * Gets the page directory for the specified address and returns the index into the page directory
2843 *
2844 * @returns Pointer to the page directory in question.
2845 * @returns NULL if the page directory is not present or on an invalid page.
2846 * @param pPGM Pointer to the PGM instance data.
2847 * @param GCPtr The address.
2848 * @param piPD Receives the index into the returned page directory
2849 */
2850DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
2851{
2852 const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2853 if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2854 {
2855 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
2856 if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2857 {
2858 *piPD = iPD;
2859 return CTXSUFF(pPGM->apGstPaePDs)[iPdPtr];
2860 }
2861
2862 /* cache is out-of-sync. */
2863 PX86PDPAE pPD;
2864 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2865 if (VBOX_SUCCESS(rc))
2866 {
2867 *piPD = iPD;
2868 return pPD;
2869 }
2870 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2871 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
2872 }
2873 return NULL;
2874}
2875
2876
2877/**
2878 * Checks if any of the specified page flags are set for the given page.
2879 *
2880 * @returns true if any of the flags are set.
2881 * @returns false if all the flags are clear.
2882 * @param pPGM PGM handle.
2883 * @param GCPhys The GC physical address.
2884 * @param fFlags The flags to check for.
2885 */
2886DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
2887{
2888 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
2889 return pPage
2890 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
2891}
2892
2893
2894/**
2895 * Gets the ram flags for a handler.
2896 *
2897 * @returns The ram flags.
2898 * @param pCur The physical handler in question.
2899 */
2900DECLINLINE(unsigned) pgmHandlerPhysicalCalcFlags(PPGMPHYSHANDLER pCur)
2901{
2902 switch (pCur->enmType)
2903 {
2904 case PGMPHYSHANDLERTYPE_PHYSICAL:
2905 return MM_RAM_FLAGS_PHYSICAL_HANDLER;
2906
2907 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
2908 return MM_RAM_FLAGS_PHYSICAL_HANDLER | MM_RAM_FLAGS_PHYSICAL_WRITE;
2909
2910 case PGMPHYSHANDLERTYPE_MMIO:
2911 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
2912 return MM_RAM_FLAGS_PHYSICAL_HANDLER | MM_RAM_FLAGS_PHYSICAL_ALL;
2913
2914 default:
2915 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
2916 }
2917}
2918
2919
2920/**
2921 * Clears one physical page of a virtual handler
2922 *
2923 * @param pPGM Pointer to the PGM instance.
2924 * @param pCur Virtual handler structure
2925 * @param iPage Physical page index
2926 */
2927DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
2928{
2929 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
2930
2931 /*
2932 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
2933 */
2934#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2935 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
2936 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2937 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
2938#endif
2939 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
2940 {
2941 /* We're the head of the alias chain. */
2942 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
2943#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2944 AssertReleaseMsg(pRemove != NULL,
2945 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2946 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
2947 AssertReleaseMsg(pRemove == pPhys2Virt,
2948 ("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
2949 " got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2950 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
2951 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
2952#endif
2953 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
2954 {
2955 /* Insert the next list in the alias chain into the tree. */
2956 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
2957#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2958 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
2959 ("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2960 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
2961#endif
2962 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
2963 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
2964 AssertRelease(fRc);
2965 }
2966 }
2967 else
2968 {
2969 /* Locate the previous node in the alias chain. */
2970 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
2971#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2972 AssertReleaseMsg(pPrev != pPhys2Virt,
2973 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
2974 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
2975#endif
2976 for (;;)
2977 {
2978 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
2979 if (pNext == pPhys2Virt)
2980 {
2981 /* unlink. */
2982 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
2983 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
2984 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
2985 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
2986 else
2987 {
2988 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
2989 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
2990 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
2991 }
2992 break;
2993 }
2994
2995 /* next */
2996 if (pNext == pPrev)
2997 {
2998#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2999 AssertReleaseMsg(pNext != pPrev,
3000 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3001 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3002#endif
3003 break;
3004 }
3005 pPrev = pNext;
3006 }
3007 }
3008 Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3009 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3010 pPhys2Virt->offNextAlias = 0;
3011 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3012
3013 /*
3014 * Clear the ram flags for this page.
3015 */
3016 int rc = pgmRamFlagsClearByGCPhys(pPGM, pPhys2Virt->Core.Key,
3017 MM_RAM_FLAGS_VIRTUAL_HANDLER | MM_RAM_FLAGS_VIRTUAL_ALL | MM_RAM_FLAGS_VIRTUAL_WRITE);
3018 AssertRC(rc);
3019}
3020
3021
3022/**
3023 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3024 *
3025 * @returns Pointer to the shadow page structure.
3026 * @param pPool The pool.
3027 * @param HCPhys The HC physical address of the shadow page.
3028 */
3029DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3030{
3031 /*
3032 * Look up the page.
3033 */
3034 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3035 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3036 return pPage;
3037}
3038
3039
3040/**
3041 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3042 *
3043 * @returns Pointer to the shadow page structure.
3044 * @param pPool The pool.
3045 * @param idx The pool page index.
3046 */
3047DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3048{
3049 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3050 return &pPool->aPages[idx];
3051}
3052
3053
3054#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3055/**
3056 * Clear references to guest physical memory.
3057 *
3058 * @param pPool The pool.
3059 * @param pPoolPage The pool page.
3060 * @param pPhysPage The physical guest page tracking structure.
3061 */
3062DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3063{
3064 /*
3065 * Just deal with the simple case here.
3066 */
3067#ifdef LOG_ENABLED
3068 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3069#endif
3070 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3071 if (cRefs == 1)
3072 {
3073 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3074 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3075 }
3076 else
3077 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3078 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3079}
3080#endif
3081
3082
3083#ifdef PGMPOOL_WITH_CACHE
3084/**
3085 * Moves the page to the head of the age list.
3086 *
3087 * This is done when the cached page is used in one way or another.
3088 *
3089 * @param pPool The pool.
3090 * @param pPage The cached page.
3091 * @todo inline in PGMInternal.h!
3092 */
3093DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3094{
3095 /*
3096 * Move to the head of the age list.
3097 */
3098 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3099 {
3100 /* unlink */
3101 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3102 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3103 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3104 else
3105 pPool->iAgeTail = pPage->iAgePrev;
3106
3107 /* insert at head */
3108 pPage->iAgePrev = NIL_PGMPOOL_IDX;
3109 pPage->iAgeNext = pPool->iAgeHead;
3110 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3111 pPool->iAgeHead = pPage->idx;
3112 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3113 }
3114}
3115#endif /* PGMPOOL_WITH_CACHE */
3116
3117/**
3118 * Tells if mappings are to be put into the shadow page table or not
3119 *
3120 * @returns boolean result
3121 * @param pVM VM handle.
3122 */
3123
3124DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3125{
3126 return !pPGM->fDisableMappings;
3127}
3128
3129/** @} */
3130
3131#endif
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