PGMInternal.h@ 6829

Last change on this file since 6829 was 6829, checked in by vboxsync, 17 years ago
Addressed the R0/R3 issues with the PGMRAMRANGE structure.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 129.4 KB

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1	/* $Id: PGMInternal.h 6829 2008-02-06 14:06:30Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/stam.h>
25	#include <VBox/param.h>
26	#include <VBox/vmm.h>
27	#include <VBox/mm.h>
28	#include <VBox/pdmcritsect.h>
29	#include <VBox/pdmapi.h>
30	#include <VBox/dis.h>
31	#include <VBox/dbgf.h>
32	#include <VBox/log.h>
33	#include <VBox/gmm.h>
34	#include <iprt/avl.h>
35	#include <iprt/assert.h>
36	#include <iprt/critsect.h>
37
38	#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
39	# error "Not in PGM! This is an internal header!"
40	#endif
41
42
43	/** @defgroup grp_pgm_int Internals
44	* @ingroup grp_pgm
45	* @internal
46	* @{
47	*/
48
49
50	/** @name PGM Compile Time Config
51	* @{
52	*/
53
54	/**
55	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
56	* Comment it if it will break something.
57	*/
58	#define PGM_OUT_OF_SYNC_IN_GC
59
60	/**
61	* Virtualize the dirty bit
62	* This also makes a half-hearted attempt at the accessed bit. For full
63	* accessed bit virtualization define PGM_SYNC_ACCESSED_BIT.
64	*/
65	#define PGM_SYNC_DIRTY_BIT
66
67	/**
68	* Fully virtualize the accessed bit.
69	* @remark This requires SYNC_DIRTY_ACCESSED_BITS to be defined!
70	*/
71	#define PGM_SYNC_ACCESSED_BIT
72
73	/**
74	* Check and skip global PDEs for non-global flushes
75	*/
76	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
77
78	/**
79	* Sync N pages instead of a whole page table
80	*/
81	#define PGM_SYNC_N_PAGES
82
83	/**
84	* Number of pages to sync during a page fault
85	*
86	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
87	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
88	*/
89	#define PGM_SYNC_NR_PAGES 8
90
91	/**
92	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
93	*/
94	#define PGM_MAX_PHYSCACHE_ENTRIES 64
95	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
96
97	/**
98	* Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
99	*/
100	#define PGM_PHYSMEMACCESS_CACHING
101
102	/*
103	* Assert Sanity.
104	*/
105	#if defined(PGM_SYNC_ACCESSED_BIT) && !defined(PGM_SYNC_DIRTY_BIT)
106	# error "PGM_SYNC_ACCESSED_BIT requires PGM_SYNC_DIRTY_BIT!"
107	#endif
108
109	/** @def PGMPOOL_WITH_CACHE
110	* Enable agressive caching using the page pool.
111	*
112	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
113	*/
114	#define PGMPOOL_WITH_CACHE
115
116	/** @def PGMPOOL_WITH_MIXED_PT_CR3
117	* When defined, we'll deal with 'uncachable' pages.
118	*/
119	#ifdef PGMPOOL_WITH_CACHE
120	# define PGMPOOL_WITH_MIXED_PT_CR3
121	#endif
122
123	/** @def PGMPOOL_WITH_MONITORING
124	* Monitor the guest pages which are shadowed.
125	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
126	* be enabled as well.
127	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
128	*/
129	#ifdef PGMPOOL_WITH_CACHE
130	# define PGMPOOL_WITH_MONITORING
131	#endif
132
133	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
134	* Tracking the of shadow pages mapping guest physical pages.
135	*
136	* This is very expensive, the current cache prototype is trying to figure out
137	* whether it will be acceptable with an agressive caching policy.
138	*/
139	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
140	# define PGMPOOL_WITH_GCPHYS_TRACKING
141	#endif
142
143	/** @def PGMPOOL_WITH_USER_TRACKNG
144	* Tracking users of shadow pages. This is required for the linking of shadow page
145	* tables and physical guest addresses.
146	*/
147	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
148	# define PGMPOOL_WITH_USER_TRACKING
149	#endif
150
151	/** @def PGMPOOL_CFG_MAX_GROW
152	* The maximum number of pages to add to the pool in one go.
153	*/
154	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
155
156	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
157	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
158	*/
159	#ifdef VBOX_STRICT
160	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
161	#endif
162	/** @} */
163
164
165	/** @name PDPTR and PML4 flags.
166	* These are placed in the three bits available for system programs in
167	* the PDPTR and PML4 entries.
168	* @{ */
169	/** The entry is a permanent one and it's must always be present.
170	* Never free such an entry. */
171	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172	/** @} */
173
174	/** @name Page directory flags.
175	* These are placed in the three bits available for system programs in
176	* the page directory entries.
177	* @{ */
178	/** Mapping (hypervisor allocated pagetable). */
179	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
180	/** Made read-only to facilitate dirty bit tracking. */
181	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
182	/** @} */
183
184	/** @name Page flags.
185	* These are placed in the three bits available for system programs in
186	* the page entries.
187	* @{ */
188	/** Made read-only to facilitate dirty bit tracking. */
189	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
190
191	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
192	/** Scanned and approved by CSAM (tm).
193	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
194	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
195	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
196	#endif
197	/** @} */
198
199	/** @name Defines used to indicate the shadow and guest paging in the templates.
200	* @{ */
201	#define PGM_TYPE_REAL 1
202	#define PGM_TYPE_PROT 2
203	#define PGM_TYPE_32BIT 3
204	#define PGM_TYPE_PAE 4
205	#define PGM_TYPE_AMD64 5
206	/** @} */
207
208	/** Macro for checking if the guest is using paging.
209	* @param uType PGM_TYPE_*
210	* @remark ASSUMES certain order of the PGM_TYPE_* values.
211	*/
212	#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT)
213
214
215	/** @def PGM_HCPHYS_2_PTR
216	* Maps a HC physical page pool address to a virtual address.
217	*
218	* @returns VBox status code.
219	* @param pVM The VM handle.
220	* @param HCPhys The HC physical address to map to a virtual one.
221	* @param ppv Where to store the virtual address. No need to cast this.
222	*
223	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
224	* small page window employeed by that function. Be careful.
225	* @remark There is no need to assert on the result.
226	*/
227	#ifdef IN_GC
228	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
229	#else
230	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
231	#endif
232
233	/** @def PGM_GCPHYS_2_PTR
234	* Maps a GC physical page address to a virtual address.
235	*
236	* @returns VBox status code.
237	* @param pVM The VM handle.
238	* @param GCPhys The GC physical address to map to a virtual one.
239	* @param ppv Where to store the virtual address. No need to cast this.
240	*
241	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
242	* small page window employeed by that function. Be careful.
243	* @remark There is no need to assert on the result.
244	*/
245	#ifdef IN_GC
246	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
247	#else
248	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only /, (void )(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
249	#endif
250
251	/** @def PGM_GCPHYS_2_PTR_EX
252	* Maps a unaligned GC physical page address to a virtual address.
253	*
254	* @returns VBox status code.
255	* @param pVM The VM handle.
256	* @param GCPhys The GC physical address to map to a virtual one.
257	* @param ppv Where to store the virtual address. No need to cast this.
258	*
259	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
260	* small page window employeed by that function. Be careful.
261	* @remark There is no need to assert on the result.
262	*/
263	#ifdef IN_GC
264	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
265	#else
266	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only /, (void )(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267	#endif
268
269	/** @def PGM_INVL_PG
270	* Invalidates a page when in GC does nothing in HC.
271	*
272	* @param GCVirt The virtual address of the page to invalidate.
273	*/
274	#ifdef IN_GC
275	# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
276	#else
277	# define PGM_INVL_PG(GCVirt) ((void)0)
278	#endif
279
280	/** @def PGM_INVL_BIG_PG
281	* Invalidates a 4MB page directory entry when in GC does nothing in HC.
282	*
283	* @param GCVirt The virtual address within the page directory to invalidate.
284	*/
285	#ifdef IN_GC
286	# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
287	#else
288	# define PGM_INVL_BIG_PG(GCVirt) ((void)0)
289	#endif
290
291	/** @def PGM_INVL_GUEST_TLBS()
292	* Invalidates all guest TLBs.
293	*/
294	#ifdef IN_GC
295	# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
296	#else
297	# define PGM_INVL_GUEST_TLBS() ((void)0)
298	#endif
299
300
301	/**
302	* Structure for tracking GC Mappings.
303	*
304	* This structure is used by linked list in both GC and HC.
305	*/
306	typedef struct PGMMAPPING
307	{
308	/** Pointer to next entry. */
309	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
310	/** Pointer to next entry. */
311	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
312	/** Pointer to next entry. */
313	GCPTRTYPE(struct PGMMAPPING *) pNextGC;
314	/** Start Virtual address. */
315	RTGCUINTPTR GCPtr;
316	/** Last Virtual address (inclusive). */
317	RTGCUINTPTR GCPtrLast;
318	/** Range size (bytes). */
319	RTGCUINTPTR cb;
320	/** Pointer to relocation callback function. */
321	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
322	/** User argument to the callback. */
323	R3PTRTYPE(void *) pvUser;
324	/** Mapping description / name. For easing debugging. */
325	R3PTRTYPE(const char *) pszDesc;
326	/** Number of page tables. */
327	RTUINT cPTs;
328	#if HC_ARCH_BITS != GC_ARCH_BITS
329	RTUINT uPadding0; /*< Alignment padding. /
330	#endif
331	/** Array of page table mapping data. Each entry
332	* describes one page table. The array can be longer
333	* than the declared length.
334	*/
335	struct
336	{
337	/** The HC physical address of the page table. */
338	RTHCPHYS HCPhysPT;
339	/** The HC physical address of the first PAE page table. */
340	RTHCPHYS HCPhysPaePT0;
341	/** The HC physical address of the second PAE page table. */
342	RTHCPHYS HCPhysPaePT1;
343	/** The HC virtual address of the 32-bit page table. */
344	R3PTRTYPE(PVBOXPT) pPTR3;
345	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
346	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
347	/** The GC virtual address of the 32-bit page table. */
348	GCPTRTYPE(PVBOXPT) pPTGC;
349	/** The GC virtual address of the two PAE page table. */
350	GCPTRTYPE(PX86PTPAE) paPaePTsGC;
351	/** The GC virtual address of the 32-bit page table. */
352	R0PTRTYPE(PVBOXPT) pPTR0;
353	/** The GC virtual address of the two PAE page table. */
354	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
355	} aPTs[1];
356	} PGMMAPPING;
357	/** Pointer to structure for tracking GC Mappings. */
358	typedef struct PGMMAPPING *PPGMMAPPING;
359
360
361	/**
362	* Physical page access handler structure.
363	*
364	* This is used to keep track of physical address ranges
365	* which are being monitored in some kind of way.
366	*/
367	typedef struct PGMPHYSHANDLER
368	{
369	AVLROGCPHYSNODECORE Core;
370	/** Alignment padding. */
371	uint32_t u32Padding;
372	/** Access type. */
373	PGMPHYSHANDLERTYPE enmType;
374	/** Number of pages to update. */
375	uint32_t cPages;
376	/** Pointer to R3 callback function. */
377	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
378	/** User argument for R3 handlers. */
379	R3PTRTYPE(void *) pvUserR3;
380	/** Pointer to R0 callback function. */
381	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
382	/** User argument for R0 handlers. */
383	R0PTRTYPE(void *) pvUserR0;
384	/** Pointer to GC callback function. */
385	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
386	/** User argument for GC handlers. */
387	GCPTRTYPE(void *) pvUserGC;
388	/** Description / Name. For easing debugging. */
389	R3PTRTYPE(const char *) pszDesc;
390	#ifdef VBOX_WITH_STATISTICS
391	/** Profiling of this handler. */
392	STAMPROFILE Stat;
393	#endif
394	} PGMPHYSHANDLER;
395	/** Pointer to a physical page access handler structure. */
396	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
397
398
399	/**
400	* Cache node for the physical addresses covered by a virtual handler.
401	*/
402	typedef struct PGMPHYS2VIRTHANDLER
403	{
404	/** Core node for the tree based on physical ranges. */
405	AVLROGCPHYSNODECORE Core;
406	/** Offset from this struct to the PGMVIRTHANDLER structure. */
407	RTGCINTPTR offVirtHandler;
408	/** Offset of the next alias relativer to this one.
409	* Bit 0 is used for indicating whether we're in the tree.
410	* Bit 1 is used for indicating that we're the head node.
411	*/
412	int32_t offNextAlias;
413	} PGMPHYS2VIRTHANDLER;
414	/** Pointer to a phys to virtual handler structure. */
415	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
416
417	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
418	* node is in the tree. */
419	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
420	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
421	* node is in the head of an alias chain.
422	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
423	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
424	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
425	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
426
427
428	/**
429	* Virtual page access handler structure.
430	*
431	* This is used to keep track of virtual address ranges
432	* which are being monitored in some kind of way.
433	*/
434	typedef struct PGMVIRTHANDLER
435	{
436	/** Core node for the tree based on virtual ranges. */
437	AVLROGCPTRNODECORE Core;
438	/** Number of cache pages. */
439	uint32_t u32Padding;
440	/** Access type. */
441	PGMVIRTHANDLERTYPE enmType;
442	/** Number of cache pages. */
443	uint32_t cPages;
444
445	/** @todo The next two members are redundant. It adds some readability though. */
446	/** Start of the range. */
447	RTGCPTR GCPtr;
448	/** End of the range (exclusive). */
449	RTGCPTR GCPtrLast;
450	/** Size of the range (in bytes). */
451	RTGCUINTPTR cb;
452	/** Pointer to the GC callback function. */
453	GCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
454	/** Pointer to the HC callback function for invalidation. */
455	R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
456	/** Pointer to the HC callback function. */
457	R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
458	/** Description / Name. For easing debugging. */
459	R3PTRTYPE(const char *) pszDesc;
460	#ifdef VBOX_WITH_STATISTICS
461	/** Profiling of this handler. */
462	STAMPROFILE Stat;
463	#endif
464	/** Array of cached physical addresses for the monitored ranged. */
465	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
466	} PGMVIRTHANDLER;
467	/** Pointer to a virtual page access handler structure. */
468	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
469
470
471	/**
472	* A Physical Guest Page tracking structure.
473	*
474	* The format of this structure is complicated because we have to fit a lot
475	* of information into as few bits as possible. The format is also subject
476	* to change (there is one comming up soon). Which means that for we'll be
477	* using PGM_PAGE_GET_* and PGM_PAGE_SET_* macros for all accessess to the
478	* structure.
479	*/
480	typedef struct PGMPAGE
481	{
482	/** The physical address and a whole lot of other stuff. All bits are used! */
483	RTHCPHYS HCPhys;
484	/** The page state. */
485	uint32_t u2State : 2;
486	/** Flag indicating that a write monitored page was written to when set. */
487	uint32_t fWrittenTo : 1;
488	/** For later. */
489	uint32_t fSomethingElse : 1;
490	/** The Page ID. */
491	uint32_t idPage : 28;
492	uint32_t u32B;
493	} PGMPAGE;
494	AssertCompileSize(PGMPAGE, 16);
495	/** Pointer to a physical guest page. */
496	typedef PGMPAGE *PPGMPAGE;
497	/** Pointer to a const physical guest page. */
498	typedef const PGMPAGE *PCPGMPAGE;
499	/** Pointer to a physical guest page pointer. */
500	typedef PPGMPAGE *PPPGMPAGE;
501
502	/** @name The Page state, PGMPAGE::u2State.
503	* @{ */
504	/** The zero page.
505	* This is a per-VM page that's never ever mapped writable. */
506	#define PGM_PAGE_STATE_ZERO 0
507	/** A allocated page.
508	* This is a per-VM page allocated from the page pool.
509	*/
510	#define PGM_PAGE_STATE_ALLOCATED 1
511	/** A allocated page that's being monitored for writes.
512	* The shadow page table mappings are read-only. When a write occurs, the
513	* fWrittenTo member is set, the page remapped as read-write and the state
514	* moved back to allocated. */
515	#define PGM_PAGE_STATE_WRITE_MONITORED 2
516	/** The page is shared, aka. copy-on-write.
517	* This is a page that's shared with other VMs. */
518	#define PGM_PAGE_STATE_SHARED 3
519	/** @} */
520
521
522	/**
523	* Gets the page state.
524	* @returns page state (PGM_PAGE_STATE_*).
525	* @param pPage Pointer to the physical guest page tracking structure.
526	*/
527	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2State )
528
529	/**
530	* Sets the page state.
531	* @param pPage Pointer to the physical guest page tracking structure.
532	* @param _uState The new page state.
533	*/
534	#define PGM_PAGE_SET_STATE(pPage, _uState) \
535	do { (pPage)->u2State = (_uState); } while (0)
536
537
538	/**
539	* Gets the host physical address of the guest page.
540	* @returns host physical address (RTHCPHYS).
541	* @param pPage Pointer to the physical guest page tracking structure.
542	*/
543	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
544
545	/**
546	* Sets the host physical address of the guest page.
547	* @param pPage Pointer to the physical guest page tracking structure.
548	* @param _HCPhys The new host physical address.
549	*/
550	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
551	do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
552	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
553
554	/**
555	* Get the Page ID.
556	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
557	* @param pPage Pointer to the physical guest page tracking structure.
558	*/
559	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPage )
560	/* later:
561	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
562	\| ((uint32_t)(pPage)->HCPhys & 0xfff) )
563	*/
564	/**
565	* Sets the Page ID.
566	* @param pPage Pointer to the physical guest page tracking structure.
567	*/
568	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPage = (_idPage); } while (0)
569	/* later:
570	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
571	\| ((_idPage) & 0xfff) \
572	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
573	*/
574
575	/**
576	* Get the Chunk ID.
577	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
578	* @param pPage Pointer to the physical guest page tracking structure.
579	*/
580	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPage >> GMM_CHUNKID_SHIFT )
581	/* later:
582	#if GMM_CHUNKID_SHIFT == 12
583	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
584	#elif GMM_CHUNKID_SHIFT > 12
585	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
586	#elif GMM_CHUNKID_SHIFT < 12
587	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
588	\| ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
589	#else
590	# error "GMM_CHUNKID_SHIFT isn't defined or something."
591	#endif
592	*/
593
594	/**
595	* Get the index of the page within the allocaiton chunk.
596	* @returns The page index.
597	* @param pPage Pointer to the physical guest page tracking structure.
598	*/
599	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPage & (RT_BIT_32(GMM_CHUNKID_SHIFT) - 1) )
600	/* later:
601	#if GMM_CHUNKID_SHIFT <= 12
602	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & (RT_BIT_32(GMM_CHUNKID_SHIFT) - 1)) )
603	#else
604	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
605	\| ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
606	#endif
607	*/
608
609	/**
610	* Checks if the page is 'reserved'.
611	* @returns true/false.
612	* @param pPage Pointer to the physical guest page tracking structure.
613	*/
614	#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
615
616	/**
617	* Checks if the page is marked for MMIO.
618	* @returns true/false.
619	* @param pPage Pointer to the physical guest page tracking structure.
620	*/
621	#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
622
623	/**
624	* Checks if the page is backed by the ZERO page.
625	* @returns true/false.
626	* @param pPage Pointer to the physical guest page tracking structure.
627	*/
628	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2State == PGM_PAGE_STATE_ZERO )
629
630	/**
631	* Checks if the page is backed by a SHARED page.
632	* @returns true/false.
633	* @param pPage Pointer to the physical guest page tracking structure.
634	*/
635	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2State == PGM_PAGE_STATE_SHARED )
636
637
638
639	/**
640	* Ram range for GC Phys to HC Phys conversion.
641	*
642	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
643	* conversions too, but we'll let MM handle that for now.
644	*
645	* This structure is used by linked lists in both GC and HC.
646	*/
647	typedef struct PGMRAMRANGE
648	{
649	/** Pointer to the next RAM range - for R3. */
650	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
651	/** Pointer to the next RAM range - for R0. */
652	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
653	/** Pointer to the next RAM range - for GC. */
654	GCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
655	/** Start of the range. Page aligned. */
656	RTGCPHYS GCPhys;
657	/** Last address in the range (inclusive). Page aligned (-1). */
658	RTGCPHYS GCPhysLast;
659	/** Size of the range. (Page aligned of course). */
660	RTGCPHYS cb;
661	/** MM_RAM_* flags */
662	uint32_t fFlags;
663	#ifdef VBOX_WITH_NEW_PHYS_CODE
664	uint32_t u32Alignment; /*< alignment. /
665	#else
666	/** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
667	GCPTRTYPE(PRTHCPTR) pavHCChunkGC;
668	/** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
669	R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
670	#endif
671	/** Start of the HC mapping of the range.
672	* For pure MMIO and dynamically allocated ranges this is NULL, while for all ranges this is a valid pointer. */
673	R3PTRTYPE(void *) pvHC;
674	/** The range description. */
675	R3PTRTYPE(const char *) pszDesc;
676
677	#ifdef VBOX_WITH_NEW_PHYS_CODE
678	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
679	uint32_t au32Reserved[2];
680	#else
681	# if HC_ARCH_BITS == 32
682	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
683	uint32_t u32Reserved;
684	# endif
685	#endif
686
687	/** Array of physical guest page tracking structures. */
688	PGMPAGE aPages[1];
689	} PGMRAMRANGE;
690	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
691	typedef PGMRAMRANGE *PPGMRAMRANGE;
692
693	/** Return hc ptr corresponding to the ram range and physical offset */
694	#define PGMRAMRANGE_GETHCPTR(pRam, off) \
695	(pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
696	: (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
697
698	/** @todo r=bird: fix typename. */
699	/**
700	* PGMPhysRead/Write cache entry
701	*/
702	typedef struct PGMPHYSCACHE_ENTRY
703	{
704	/** HC pointer to physical page */
705	R3PTRTYPE(uint8_t *) pbHC;
706	/** GC Physical address for cache entry */
707	RTGCPHYS GCPhys;
708	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
709	RTGCPHYS u32Padding0; /*< alignment padding. /
710	#endif
711	} PGMPHYSCACHE_ENTRY;
712
713	/**
714	* PGMPhysRead/Write cache to reduce REM memory access overhead
715	*/
716	typedef struct PGMPHYSCACHE
717	{
718	/** Bitmap of valid cache entries */
719	uint64_t aEntries;
720	/** Cache entries */
721	PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
722	} PGMPHYSCACHE;
723
724
725	/** Pointer to an allocation chunk ring-3 mapping. */
726	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
727	/** Pointer to an allocation chunk ring-3 mapping pointer. */
728	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
729
730	/**
731	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
732	*
733	* The primary tree (Core) uses the chunk id as key.
734	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
735	*/
736	typedef struct PGMCHUNKR3MAP
737	{
738	/** The key is the chunk id. */
739	AVLU32NODECORE Core;
740	/** The key is the ageing sequence number. */
741	AVLLU32NODECORE AgeCore;
742	/** The current age thingy. */
743	uint32_t iAge;
744	/** The current reference count. */
745	uint32_t volatile cRefs;
746	/** The current permanent reference count. */
747	uint32_t volatile cPermRefs;
748	/** The mapping address. */
749	void *pv;
750	} PGMCHUNKR3MAP;
751
752	/**
753	* Allocation chunk ring-3 mapping TLB entry.
754	*/
755	typedef struct PGMCHUNKR3MAPTLBE
756	{
757	/** The chunk id. */
758	uint32_t volatile idChunk;
759	#if HC_ARCH_BITS == 64
760	uint32_t u32Padding; /*< alignment padding. /
761	#endif
762	/** The chunk map. */
763	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
764	} PGMCHUNKR3MAPTLBE;
765	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
766	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
767
768	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
769	* @remark Must be a power of two value. */
770	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
771
772	/**
773	* Allocation chunk ring-3 mapping TLB.
774	*
775	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
776	* At first glance this might look kinda odd since AVL trees are
777	* supposed to give the most optimial lookup times of all trees
778	* due to their balancing. However, take a tree with 1023 nodes
779	* in it, that's 10 levels, meaning that most searches has to go
780	* down 9 levels before they find what they want. This isn't fast
781	* compared to a TLB hit. There is the factor of cache misses,
782	* and of course the problem with trees and branch prediction.
783	* This is why we use TLBs in front of most of the trees.
784	*
785	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
786	* difficult when we switch to inlined AVL trees (from kStuff).
787	*/
788	typedef struct PGMCHUNKR3MAPTLB
789	{
790	/** The TLB entries. */
791	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
792	} PGMCHUNKR3MAPTLB;
793
794	/**
795	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
796	* @returns Chunk TLB index.
797	* @param idChunk The Chunk ID.
798	*/
799	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
800
801
802	/**
803	* Ring-3 guest page mapping TLB entry.
804	* @remarks used in ring-0 as well at the moment.
805	*/
806	typedef struct PGMPAGER3MAPTLBE
807	{
808	/** Address of the page. */
809	RTGCPHYS volatile GCPhys;
810	#if HC_ARCH_BITS == 64
811	uint32_t u32Padding; /*< alignment padding. /
812	#endif
813	/** The guest page. */
814	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
815	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
816	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
817	/** The address */
818	R3R0PTRTYPE(void *) volatile pv;
819	} PGMPAGER3MAPTLBE;
820	/** Pointer to an entry in the HC physical TLB. */
821	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
822
823
824	/** The number of entries in the ring-3 guest page mapping TLB.
825	* @remarks The value must be a power of two. */
826	#define PGM_PAGER3MAPTLB_ENTRIES 64
827
828	/**
829	* Ring-3 guest page mapping TLB.
830	* @remarks used in ring-0 as well at the moment.
831	*/
832	typedef struct PGMPAGER3MAPTLB
833	{
834	/** The TLB entries. */
835	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
836	} PGMPAGER3MAPTLB;
837	/** Pointer to the ring-3 guest page mapping TLB. */
838	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
839
840	/**
841	* Calculates the index of the TLB entry for the specified guest page.
842	* @returns Physical TLB index.
843	* @param GCPhys The guest physical address.
844	*/
845	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
846
847
848	/** @name Context neutrual page mapper TLB.
849	*
850	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
851	* code is writting in a kind of context neutrual way. Time will show whether
852	* this actually makes sense or not...
853	*
854	* @{ */
855	/** @typedef PPGMPAGEMAPTLB
856	* The page mapper TLB pointer type for the current context. */
857	/** @typedef PPGMPAGEMAPTLB
858	* The page mapper TLB entry pointer type for the current context. */
859	/** @typedef PPGMPAGEMAPTLB
860	* The page mapper TLB entry pointer pointer type for the current context. */
861	/** @def PGMPAGEMAPTLB_ENTRIES
862	* The number of TLB entries in the page mapper TLB for the current context. */
863	/** @def PGM_PAGEMAPTLB_IDX
864	* Calculate the TLB index for a guest physical address.
865	* @returns The TLB index.
866	* @param GCPhys The guest physical address. */
867	/** @typedef PPGMPAGEMAP
868	* Pointer to a page mapper unit for current context. */
869	/** @typedef PPPGMPAGEMAP
870	* Pointer to a page mapper unit pointer for current context. */
871	#ifdef IN_GC
872	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
873	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
874	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
875	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
876	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
877	typedef void * PPGMPAGEMAP;
878	typedef void ** PPPGMPAGEMAP;
879	//#elif IN_RING0
880	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
881	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
882	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
883	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
884	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
885	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
886	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
887	#else
888	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
889	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
890	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
891	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
892	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
893	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
894	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
895	#endif
896	/** @} */
897
898
899	/** @name PGM Pool Indexes.
900	* Aka. the unique shadow page identifier.
901	* @{ */
902	/** NIL page pool IDX. */
903	#define NIL_PGMPOOL_IDX 0
904	/** The first normal index. */
905	#define PGMPOOL_IDX_FIRST_SPECIAL 1
906	/** Page directory (32-bit root). */
907	#define PGMPOOL_IDX_PD 1
908	/** The extended PAE page directory (2048 entries, works as root currently). */
909	#define PGMPOOL_IDX_PAE_PD 2
910	/** Page Directory Pointer Table (PAE root, not currently used). */
911	#define PGMPOOL_IDX_PDPTR 3
912	/** Page Map Level-4 (64-bit root). */
913	#define PGMPOOL_IDX_PML4 4
914	/** The first normal index. */
915	#define PGMPOOL_IDX_FIRST 5
916	/** The last valid index. (inclusive, 14 bits) */
917	#define PGMPOOL_IDX_LAST 0x3fff
918	/** @} */
919
920	/** The NIL index for the parent chain. */
921	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
922
923	/**
924	* Node in the chain linking a shadowed page to it's parent (user).
925	*/
926	#pragma pack(1)
927	typedef struct PGMPOOLUSER
928	{
929	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
930	uint16_t iNext;
931	/** The user page index. */
932	uint16_t iUser;
933	/** Index into the user table. */
934	uint16_t iUserTable;
935	} PGMPOOLUSER, *PPGMPOOLUSER;
936	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
937	#pragma pack()
938
939
940	/** The NIL index for the phys ext chain. */
941	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
942
943	/**
944	* Node in the chain of physical cross reference extents.
945	*/
946	#pragma pack(1)
947	typedef struct PGMPOOLPHYSEXT
948	{
949	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
950	uint16_t iNext;
951	/** The user page index. */
952	uint16_t aidx[3];
953	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
954	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
955	#pragma pack()
956
957
958	/**
959	* The kind of page that's being shadowed.
960	*/
961	typedef enum PGMPOOLKIND
962	{
963	/** The virtual invalid 0 entry. */
964	PGMPOOLKIND_INVALID = 0,
965	/** The entry is free (=unused). */
966	PGMPOOLKIND_FREE,
967
968	/** Shw: 32-bit page table; Gst: no paging */
969	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
970	/** Shw: 32-bit page table; Gst: 32-bit page table. */
971	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
972	/** Shw: 32-bit page table; Gst: 4MB page. */
973	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
974	/** Shw: PAE page table; Gst: no paging */
975	PGMPOOLKIND_PAE_PT_FOR_PHYS,
976	/** Shw: PAE page table; Gst: 32-bit page table. */
977	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
978	/** Shw: PAE page table; Gst: Half of a 4MB page. */
979	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
980	/** Shw: PAE page table; Gst: PAE page table. */
981	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
982	/** Shw: PAE page table; Gst: 2MB page. */
983	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
984
985	/** Shw: PAE page directory; Gst: 32-bit page directory. */
986	PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
987	/** Shw: PAE page directory; Gst: PAE page directory. */
988	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
989
990	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
991	PGMPOOLKIND_64BIT_PDPTR_FOR_64BIT_PDPTR,
992
993	/** Shw: Root 32-bit page directory. */
994	PGMPOOLKIND_ROOT_32BIT_PD,
995	/** Shw: Root PAE page directory */
996	PGMPOOLKIND_ROOT_PAE_PD,
997	/** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
998	PGMPOOLKIND_ROOT_PDPTR,
999	/** Shw: Root page map level-4 table. */
1000	PGMPOOLKIND_ROOT_PML4,
1001
1002	/** The last valid entry. */
1003	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PML4
1004	} PGMPOOLKIND;
1005
1006
1007	/**
1008	* The tracking data for a page in the pool.
1009	*/
1010	typedef struct PGMPOOLPAGE
1011	{
1012	/** AVL node code with the (HC) physical address of this page. */
1013	AVLOHCPHYSNODECORE Core;
1014	/** Pointer to the HC mapping of the page. */
1015	R3R0PTRTYPE(void *) pvPageHC;
1016	/** The guest physical address. */
1017	RTGCPHYS GCPhys;
1018	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1019	uint8_t enmKind;
1020	uint8_t bPadding;
1021	/** The index of this page. */
1022	uint16_t idx;
1023	/** The next entry in the list this page currently resides in.
1024	* It's either in the free list or in the GCPhys hash. */
1025	uint16_t iNext;
1026	#ifdef PGMPOOL_WITH_USER_TRACKING
1027	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1028	uint16_t iUserHead;
1029	/** The number of present entries. */
1030	uint16_t cPresent;
1031	/** The first entry in the table which is present. */
1032	uint16_t iFirstPresent;
1033	#endif
1034	#ifdef PGMPOOL_WITH_MONITORING
1035	/** The number of modifications to the monitored page. */
1036	uint16_t cModifications;
1037	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1038	uint16_t iModifiedNext;
1039	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1040	uint16_t iModifiedPrev;
1041	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1042	uint16_t iMonitoredNext;
1043	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1044	uint16_t iMonitoredPrev;
1045	#endif
1046	#ifdef PGMPOOL_WITH_CACHE
1047	/** The next page in the age list. */
1048	uint16_t iAgeNext;
1049	/** The previous page in the age list. */
1050	uint16_t iAgePrev;
1051	#endif /* PGMPOOL_WITH_CACHE */
1052	/** Used to indicate that the page is zeroed. */
1053	bool fZeroed;
1054	/** Used to indicate that a PT has non-global entries. */
1055	bool fSeenNonGlobal;
1056	/** Used to indicate that we're monitoring writes to the guest page. */
1057	bool fMonitored;
1058	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1059	* (All pages are in the age list.) */
1060	bool fCached;
1061	/** This is used by the R3 access handlers when invoked by an async thread.
1062	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1063	bool volatile fReusedFlushPending;
1064	/** Used to indicate that the guest is mapping the page is also used as a CR3.
1065	* In these cases the access handler acts differently and will check
1066	* for mapping conflicts like the normal CR3 handler.
1067	* @todo When we change the CR3 shadowing to use pool pages, this flag can be
1068	* replaced by a list of pages which share access handler.
1069	*/
1070	bool fCR3Mix;
1071	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1072	bool Alignment[4]; /*< Align the structure size on a 64-bit boundrary. /
1073	#endif
1074	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1075
1076
1077	#ifdef PGMPOOL_WITH_CACHE
1078	/** The hash table size. */
1079	# define PGMPOOL_HASH_SIZE 0x40
1080	/** The hash function. */
1081	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1082	#endif
1083
1084
1085	/**
1086	* The shadow page pool instance data.
1087	*
1088	* It's all one big allocation made at init time, except for the
1089	* pages that is. The user nodes follows immediatly after the
1090	* page structures.
1091	*/
1092	typedef struct PGMPOOL
1093	{
1094	/** The VM handle - HC Ptr. */
1095	R3R0PTRTYPE(PVM) pVMHC;
1096	/** The VM handle - GC Ptr. */
1097	GCPTRTYPE(PVM) pVMGC;
1098	/** The max pool size. This includes the special IDs. */
1099	uint16_t cMaxPages;
1100	/** The current pool size. */
1101	uint16_t cCurPages;
1102	/** The head of the free page list. */
1103	uint16_t iFreeHead;
1104	/* Padding. */
1105	uint16_t u16Padding;
1106	#ifdef PGMPOOL_WITH_USER_TRACKING
1107	/** Head of the chain of free user nodes. */
1108	uint16_t iUserFreeHead;
1109	/** The number of user nodes we've allocated. */
1110	uint16_t cMaxUsers;
1111	/** The number of present page table entries in the entire pool. */
1112	uint32_t cPresent;
1113	/** Pointer to the array of user nodes - GC pointer. */
1114	GCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1115	/** Pointer to the array of user nodes - HC pointer. */
1116	R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1117	#endif /* PGMPOOL_WITH_USER_TRACKING */
1118	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1119	/** Head of the chain of free phys ext nodes. */
1120	uint16_t iPhysExtFreeHead;
1121	/** The number of user nodes we've allocated. */
1122	uint16_t cMaxPhysExts;
1123	/** Pointer to the array of physical xref extent - GC pointer. */
1124	GCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1125	/** Pointer to the array of physical xref extent nodes - HC pointer. */
1126	R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1127	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1128	#ifdef PGMPOOL_WITH_CACHE
1129	/** Hash table for GCPhys addresses. */
1130	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1131	/** The head of the age list. */
1132	uint16_t iAgeHead;
1133	/** The tail of the age list. */
1134	uint16_t iAgeTail;
1135	/** Set if the cache is enabled. */
1136	bool fCacheEnabled;
1137	#endif /* PGMPOOL_WITH_CACHE */
1138	#ifdef PGMPOOL_WITH_MONITORING
1139	/** Head of the list of modified pages. */
1140	uint16_t iModifiedHead;
1141	/** The current number of modified pages. */
1142	uint16_t cModifiedPages;
1143	/** Access handler, GC. */
1144	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1145	/** Access handler, R0. */
1146	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1147	/** Access handler, R3. */
1148	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1149	/** The access handler description (HC ptr). */
1150	R3PTRTYPE(const char *) pszAccessHandler;
1151	#endif /* PGMPOOL_WITH_MONITORING */
1152	/** The number of pages currently in use. */
1153	uint16_t cUsedPages;
1154	#ifdef VBOX_WITH_STATISTICS
1155	/** The high wather mark for cUsedPages. */
1156	uint16_t cUsedPagesHigh;
1157	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1158	/** Profiling pgmPoolAlloc(). */
1159	STAMPROFILEADV StatAlloc;
1160	/** Profiling pgmPoolClearAll(). */
1161	STAMPROFILE StatClearAll;
1162	/** Profiling pgmPoolFlushAllInt(). */
1163	STAMPROFILE StatFlushAllInt;
1164	/** Profiling pgmPoolFlushPage(). */
1165	STAMPROFILE StatFlushPage;
1166	/** Profiling pgmPoolFree(). */
1167	STAMPROFILE StatFree;
1168	/** Profiling time spent zeroing pages. */
1169	STAMPROFILE StatZeroPage;
1170	# ifdef PGMPOOL_WITH_USER_TRACKING
1171	/** Profiling of pgmPoolTrackDeref. */
1172	STAMPROFILE StatTrackDeref;
1173	/** Profiling pgmTrackFlushGCPhysPT. */
1174	STAMPROFILE StatTrackFlushGCPhysPT;
1175	/** Profiling pgmTrackFlushGCPhysPTs. */
1176	STAMPROFILE StatTrackFlushGCPhysPTs;
1177	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1178	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1179	/** Number of times we've been out of user records. */
1180	STAMCOUNTER StatTrackFreeUpOneUser;
1181	# endif
1182	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1183	/** Profiling deref activity related tracking GC physical pages. */
1184	STAMPROFILE StatTrackDerefGCPhys;
1185	/** Number of linear searches for a HCPhys in the ram ranges. */
1186	STAMCOUNTER StatTrackLinearRamSearches;
1187	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1188	STAMCOUNTER StamTrackPhysExtAllocFailures;
1189	# endif
1190	# ifdef PGMPOOL_WITH_MONITORING
1191	/** Profiling the GC PT access handler. */
1192	STAMPROFILE StatMonitorGC;
1193	/** Times we've failed interpreting the instruction. */
1194	STAMCOUNTER StatMonitorGCEmulateInstr;
1195	/** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1196	STAMPROFILE StatMonitorGCFlushPage;
1197	/** Times we've detected fork(). */
1198	STAMCOUNTER StatMonitorGCFork;
1199	/** Profiling the GC access we've handled (except REP STOSD). */
1200	STAMPROFILE StatMonitorGCHandled;
1201	/** Times we've failed interpreting a patch code instruction. */
1202	STAMCOUNTER StatMonitorGCIntrFailPatch1;
1203	/** Times we've failed interpreting a patch code instruction during flushing. */
1204	STAMCOUNTER StatMonitorGCIntrFailPatch2;
1205	/** The number of times we've seen rep prefixes we can't handle. */
1206	STAMCOUNTER StatMonitorGCRepPrefix;
1207	/** Profiling the REP STOSD cases we've handled. */
1208	STAMPROFILE StatMonitorGCRepStosd;
1209
1210	/** Profiling the HC PT access handler. */
1211	STAMPROFILE StatMonitorHC;
1212	/** Times we've failed interpreting the instruction. */
1213	STAMCOUNTER StatMonitorHCEmulateInstr;
1214	/** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1215	STAMPROFILE StatMonitorHCFlushPage;
1216	/** Times we've detected fork(). */
1217	STAMCOUNTER StatMonitorHCFork;
1218	/** Profiling the HC access we've handled (except REP STOSD). */
1219	STAMPROFILE StatMonitorHCHandled;
1220	/** The number of times we've seen rep prefixes we can't handle. */
1221	STAMCOUNTER StatMonitorHCRepPrefix;
1222	/** Profiling the REP STOSD cases we've handled. */
1223	STAMPROFILE StatMonitorHCRepStosd;
1224	/** The number of times we're called in an async thread an need to flush. */
1225	STAMCOUNTER StatMonitorHCAsync;
1226	/** The high wather mark for cModifiedPages. */
1227	uint16_t cModifiedPagesHigh;
1228	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1229	# endif
1230	# ifdef PGMPOOL_WITH_CACHE
1231	/** The number of cache hits. */
1232	STAMCOUNTER StatCacheHits;
1233	/** The number of cache misses. */
1234	STAMCOUNTER StatCacheMisses;
1235	/** The number of times we've got a conflict of 'kind' in the cache. */
1236	STAMCOUNTER StatCacheKindMismatches;
1237	/** Number of times we've been out of pages. */
1238	STAMCOUNTER StatCacheFreeUpOne;
1239	/** The number of cacheable allocations. */
1240	STAMCOUNTER StatCacheCacheable;
1241	/** The number of uncacheable allocations. */
1242	STAMCOUNTER StatCacheUncacheable;
1243	# endif
1244	#elif HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1245	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1246	#endif
1247	/** The AVL tree for looking up a page by its HC physical address. */
1248	AVLOHCPHYSTREE HCPhysTree;
1249	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1250	/** Array of pages. (cMaxPages in length)
1251	* The Id is the index into thist array.
1252	*/
1253	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1254	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1255
1256
1257	/** @def PGMPOOL_PAGE_2_PTR
1258	* Maps a pool page pool into the current context.
1259	*
1260	* @returns VBox status code.
1261	* @param pVM The VM handle.
1262	* @param pPage The pool page.
1263	*
1264	* @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1265	* small page window employeed by that function. Be careful.
1266	* @remark There is no need to assert on the result.
1267	*/
1268	#ifdef IN_GC
1269	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1270	#else
1271	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1272	#endif
1273
1274
1275	/**
1276	* Trees are using self relative offsets as pointers.
1277	* So, all its data, including the root pointer, must be in the heap for HC and GC
1278	* to have the same layout.
1279	*/
1280	typedef struct PGMTREES
1281	{
1282	/** Physical access handlers (AVL range+offsetptr tree). */
1283	AVLROGCPHYSTREE PhysHandlers;
1284	/** Virtual access handlers (AVL range + GC ptr tree). */
1285	AVLROGCPTRTREE VirtHandlers;
1286	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1287	AVLROGCPHYSTREE PhysToVirtHandlers;
1288	uint32_t auPadding[1];
1289	} PGMTREES;
1290	/** Pointer to PGM trees. */
1291	typedef PGMTREES *PPGMTREES;
1292
1293
1294	/** @name Paging mode macros
1295	* @{ */
1296	#ifdef IN_GC
1297	# define PGM_CTX(a,b) a##GC##b
1298	# define PGM_CTX_STR(a,b) a "GC" b
1299	# define PGM_CTX_DECL(type) PGMGCDECL(type)
1300	#else
1301	# ifdef IN_RING3
1302	# define PGM_CTX(a,b) a##R3##b
1303	# define PGM_CTX_STR(a,b) a "R3" b
1304	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1305	# else
1306	# define PGM_CTX(a,b) a##R0##b
1307	# define PGM_CTX_STR(a,b) a "R0" b
1308	# define PGM_CTX_DECL(type) PGMDECL(type)
1309	# endif
1310	#endif
1311
1312	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1313	#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1314	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1315	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1316	#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1317	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1318	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1319	#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1320	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1321	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1322	#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1323	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1324	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1325	#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1326	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1327	#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1328	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1329
1330	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1331	#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1332	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1333	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1334	#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1335	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1336	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1337	#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1338	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1339	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1340	#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1341
1342	/* Shw_Gst */
1343	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1344	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1345	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1346	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1347	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1348	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1349	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1350	#define PGM_BTH_NAME_AMD64_REAL(name) PGM_CTX(pgm,BthAMD64Real##name)
1351	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1352	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1353	#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1354	#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1355	#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1356	#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1357	#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1358	#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1359	#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1360	#define PGM_BTH_NAME_GC_AMD64_REAL_STR(name) "pgmGCBthAMD64Real" #name
1361	#define PGM_BTH_NAME_GC_AMD64_PROT_STR(name) "pgmGCBthAMD64Prot" #name
1362	#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1363	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1364	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1365	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1366	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1367	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1368	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1369	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1370	#define PGM_BTH_NAME_R0_AMD64_REAL_STR(name) "pgmR0BthAMD64Real" #name
1371	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1372	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1373	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1374	#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1375	/** @} */
1376
1377	/**
1378	* Data for each paging mode.
1379	*/
1380	typedef struct PGMMODEDATA
1381	{
1382	/** The guest mode type. */
1383	uint32_t uGstType;
1384	/** The shadow mode type. */
1385	uint32_t uShwType;
1386
1387	/** @name Function pointers for Shadow paging.
1388	* @{
1389	*/
1390	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1391	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1392	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1393	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1394	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1395	DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1396	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1397
1398	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1399	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1400	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1401	DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1402	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1403
1404	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1405	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1406	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1407	DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1408	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1409	/** @} */
1410
1411	/** @name Function pointers for Guest paging.
1412	* @{
1413	*/
1414	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1415	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1416	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1417	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1418	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1419	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1420	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1421	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1422	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1423	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1424	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1425	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1426	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1427
1428	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1429	DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1430	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1431	DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1432	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1433	DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1434	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1435	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1436	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1437
1438	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1439	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1440	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1441	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1442	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1443	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1444	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1445	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1446	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1447	/** @} */
1448
1449	/** @name Function pointers for Both Shadow and Guest paging.
1450	* @{
1451	*/
1452	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1453	DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1454	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1455	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1456	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1457	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1458	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1459	#ifdef VBOX_STRICT
1460	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1461	#endif
1462
1463	DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1464	DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1465	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1466	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1467	DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1468	DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1469	#ifdef VBOX_STRICT
1470	DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1471	#endif
1472
1473	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1474	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1475	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1476	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1477	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1478	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1479	#ifdef VBOX_STRICT
1480	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1481	#endif
1482	/** @} */
1483	} PGMMODEDATA, *PPGMMODEDATA;
1484
1485
1486
1487	/**
1488	* Converts a PGM pointer into a VM pointer.
1489	* @returns Pointer to the VM structure the PGM is part of.
1490	* @param pPGM Pointer to PGM instance data.
1491	*/
1492	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1493
1494	/**
1495	* PGM Data (part of VM)
1496	*/
1497	typedef struct PGM
1498	{
1499	/** Offset to the VM structure. */
1500	RTINT offVM;
1501
1502	/*
1503	* This will be redefined at least two more times before we're done, I'm sure.
1504	* The current code is only to get on with the coding.
1505	* - 2004-06-10: initial version, bird.
1506	* - 2004-07-02: 1st time, bird.
1507	* - 2004-10-18: 2nd time, bird.
1508	* - 2005-07-xx: 3rd time, bird.
1509	*/
1510
1511	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1512	GCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1513	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1514	GCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1515
1516	/** The host paging mode. (This is what SUPLib reports.) */
1517	SUPPAGINGMODE enmHostMode;
1518	/** The shadow paging mode. */
1519	PGMMODE enmShadowMode;
1520	/** The guest paging mode. */
1521	PGMMODE enmGuestMode;
1522
1523	/** The current physical address representing in the guest CR3 register. */
1524	RTGCPHYS GCPhysCR3;
1525	/** Pointer to the 5 page CR3 content mapping.
1526	* The first page is always the CR3 (in some form) while the 4 other pages
1527	* are used of the PDs in PAE mode. */
1528	RTGCPTR GCPtrCR3Mapping;
1529	/** The physical address of the currently monitored guest CR3 page.
1530	* When this value is NIL_RTGCPHYS no page is being monitored. */
1531	RTGCPHYS GCPhysGstCR3Monitored;
1532	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1533	RTGCPHYS GCPhysPadding0; /*< alignment padding. /
1534	#endif
1535
1536	/** @name 32-bit Guest Paging.
1537	* @{ */
1538	/** The guest's page directory, HC pointer. */
1539	R3R0PTRTYPE(PVBOXPD) pGuestPDHC;
1540	/** The guest's page directory, static GC mapping. */
1541	GCPTRTYPE(PVBOXPD) pGuestPDGC;
1542	/** @} */
1543
1544	/** @name PAE Guest Paging.
1545	* @{ */
1546	/** The guest's page directory pointer table, static GC mapping. */
1547	GCPTRTYPE(PX86PDPTR) pGstPaePDPTRGC;
1548	/** The guest's page directory pointer table, HC pointer. */
1549	R3R0PTRTYPE(PX86PDPTR) pGstPaePDPTRHC;
1550	/** The guest's page directories, HC pointers.
1551	* These are individual pointers and doesn't have to be adjecent.
1552	* These doesn't have to be update to date - use pgmGstGetPaePD() to access them. */
1553	R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1554	/** The guest's page directories, static GC mapping.
1555	* Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1556	* These doesn't have to be update to date - use pgmGstGetPaePD() to access them. */
1557	GCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1558	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1559	RTGCPHYS aGCPhysGstPaePDs[4];
1560	/** The physical addresses of the monitored guest page directories (PAE). */
1561	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1562	/** @} */
1563
1564
1565	/** @name 32-bit Shadow Paging
1566	* @{ */
1567	/** The 32-Bit PD - HC Ptr. */
1568	R3R0PTRTYPE(PX86PD) pHC32BitPD;
1569	/** The 32-Bit PD - GC Ptr. */
1570	GCPTRTYPE(PX86PD) pGC32BitPD;
1571	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1572	uint32_t u32Padding1; /*< alignment padding. /
1573	#endif
1574	/** The Physical Address (HC) of the 32-Bit PD. */
1575	RTHCPHYS HCPhys32BitPD;
1576	/** @} */
1577
1578	/** @name PAE Shadow Paging
1579	* @{ */
1580	/** The four PDs for the low 4GB - HC Ptr.
1581	* Even though these are 4 pointers, what they point at is a single table.
1582	* Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
1583	R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
1584	/** The four PDs for the low 4GB - GC Ptr.
1585	* Same kind of mapping as apHCPaePDs. */
1586	GCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
1587	/** The Physical Address (HC) of the four PDs for the low 4GB.
1588	* These are NOT 4 contiguous pages. */
1589	RTHCPHYS aHCPhysPaePDs[4];
1590	/** The PAE PDPTR - HC Ptr. */
1591	R3R0PTRTYPE(PX86PDPTR) pHCPaePDPTR;
1592	/** The Physical Address (HC) of the PAE PDPTR. */
1593	RTHCPHYS HCPhysPaePDPTR;
1594	/** The PAE PDPTR - GC Ptr. */
1595	GCPTRTYPE(PX86PDPTR) pGCPaePDPTR;
1596	/** @} */
1597
1598	/** @name AMD64 Shadow Paging
1599	* Extends PAE Paging.
1600	* @{ */
1601	/** The Page Map Level 4 table - HC Ptr. */
1602	GCPTRTYPE(PX86PML4) pGCPaePML4;
1603	/** The Page Map Level 4 table - GC Ptr. */
1604	R3R0PTRTYPE(PX86PML4) pHCPaePML4;
1605	/** The Physical Address (HC) of the Page Map Level 4 table. */
1606	RTHCPHYS HCPhysPaePML4;
1607	/** @}*/
1608
1609	/** @name Function pointers for Shadow paging.
1610	* @{
1611	*/
1612	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1613	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1614	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1615	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1616	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1617	DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1618	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1619
1620	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1621	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1622	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1623	DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1624	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1625	#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1626	RTGCPTR alignment0; /*< structure size alignment. /
1627	#endif
1628
1629	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1630	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1631	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1632	DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1633	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1634
1635	/** @} */
1636
1637	/** @name Function pointers for Guest paging.
1638	* @{
1639	*/
1640	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1641	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1642	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1643	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1644	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1645	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1646	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1647	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1648	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1649	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1650	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1651	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1652	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1653
1654	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1655	DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1656	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1657	DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1658	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1659	DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1660	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1661	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1662	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1663	#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1664	RTGCPTR alignment3; /*< structure size alignment. /
1665	#endif
1666
1667	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1668	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1669	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1670	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1671	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1672	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1673	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1674	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1675	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1676	/** @} */
1677
1678	/** @name Function pointers for Both Shadow and Guest paging.
1679	* @{
1680	*/
1681	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1682	DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1683	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1684	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1685	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1686	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1687	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1688	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1689
1690	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1691	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1692	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1693	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1694	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1695	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1696	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1697
1698	DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1699	DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1700	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1701	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1702	DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1703	DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1704	DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1705	#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1706	RTGCPTR alignment2; /*< structure size alignment. /
1707	#endif
1708	/** @} */
1709
1710	/** Pointer to SHW+GST mode data (function pointers).
1711	* The index into this table is made up from */
1712	R3PTRTYPE(PPGMMODEDATA) paModeData;
1713
1714
1715	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
1716	* This is sorted by physical address and contains no overlaps.
1717	* The memory locks and other conversions are managed by MM at the moment.
1718	*/
1719	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
1720	/** R0 pointer corresponding to PGM::pRamRangesR3. */
1721	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
1722	/** GC pointer corresponding to PGM::pRamRangesR3. */
1723	GCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
1724	/** The configured RAM size. */
1725	RTUINT cbRamSize;
1726
1727	/** PGM offset based trees - HC Ptr. */
1728	R3R0PTRTYPE(PPGMTREES) pTreesHC;
1729	/** PGM offset based trees - GC Ptr. */
1730	GCPTRTYPE(PPGMTREES) pTreesGC;
1731
1732	/** Linked list of GC mappings - for GC.
1733	* The list is sorted ascending on address.
1734	*/
1735	GCPTRTYPE(PPGMMAPPING) pMappingsGC;
1736	/** Linked list of GC mappings - for HC.
1737	* The list is sorted ascending on address.
1738	*/
1739	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
1740	/** Linked list of GC mappings - for R0.
1741	* The list is sorted ascending on address.
1742	*/
1743	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
1744
1745	/** If set no conflict checks are required. (boolean) */
1746	bool fMappingsFixed;
1747	/** If set, then no mappings are put into the shadow page table. (boolean) */
1748	bool fDisableMappings;
1749	/** Size of fixed mapping */
1750	uint32_t cbMappingFixed;
1751	/** Base address (GC) of fixed mapping */
1752	RTGCPTR GCPtrMappingFixed;
1753	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1754	uint32_t u32Padding0; /*< alignment padding. /
1755	#endif
1756
1757
1758	/** @name Intermediate Context
1759	* @{ */
1760	/** Pointer to the intermediate page directory - Normal. */
1761	R3PTRTYPE(PX86PD) pInterPD;
1762	/** Pointer to the intermedate page tables - Normal.
1763	* There are two page tables, one for the identity mapping and one for
1764	* the host context mapping (of the core code). */
1765	R3PTRTYPE(PX86PT) apInterPTs[2];
1766	/** Pointer to the intermedate page tables - PAE. */
1767	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
1768	/** Pointer to the intermedate page directory - PAE. */
1769	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
1770	/** Pointer to the intermedate page directory - PAE. */
1771	R3PTRTYPE(PX86PDPTR) pInterPaePDPTR;
1772	/** Pointer to the intermedate page-map level 4 - AMD64. */
1773	R3PTRTYPE(PX86PML4) pInterPaePML4;
1774	/** Pointer to the intermedate page directory - AMD64. */
1775	R3PTRTYPE(PX86PDPTR) pInterPaePDPTR64;
1776	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
1777	RTHCPHYS HCPhysInterPD;
1778	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
1779	RTHCPHYS HCPhysInterPaePDPTR;
1780	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
1781	RTHCPHYS HCPhysInterPaePML4;
1782	/** @} */
1783
1784	/** Base address of the dynamic page mapping area.
1785	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
1786	*/
1787	GCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
1788	/** The index of the last entry used in the dynamic page mapping area. */
1789	RTUINT iDynPageMapLast;
1790	/** Cache containing the last entries in the dynamic page mapping area.
1791	* The cache size is covering half of the mapping area. */
1792	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
1793
1794	/** A20 gate mask.
1795	* Our current approach to A20 emulation is to let REM do it and don't bother
1796	* anywhere else. The interesting Guests will be operating with it enabled anyway.
1797	* But whould need arrise, we'll subject physical addresses to this mask. */
1798	RTGCPHYS GCPhysA20Mask;
1799	/** A20 gate state - boolean! */
1800	RTUINT fA20Enabled;
1801
1802	/** What needs syncing (PGM_SYNC_*).
1803	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
1804	* PGMFlushTLB, and PGMR3Load. */
1805	RTUINT fSyncFlags;
1806
1807	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1808	RTUINT uPadding3; /*< alignment padding. /
1809	#endif
1810	/** PGM critical section.
1811	* This protects the physical & virtual access handlers, ram ranges,
1812	* and the page flag updating (some of it anyway).
1813	*/
1814	PDMCRITSECT CritSect;
1815
1816	/** Shadow Page Pool - HC Ptr. */
1817	R3R0PTRTYPE(PPGMPOOL) pPoolHC;
1818	/** Shadow Page Pool - GC Ptr. */
1819	GCPTRTYPE(PPGMPOOL) pPoolGC;
1820
1821	/** We're not in a state which permits writes to guest memory.
1822	* (Only used in strict builds.) */
1823	bool fNoMorePhysWrites;
1824
1825	/** Flush the cache on the next access. */
1826	bool fPhysCacheFlushPending;
1827	/** @todo r=bird: Fix member names!*/
1828	/** PGMPhysRead cache */
1829	PGMPHYSCACHE pgmphysreadcache;
1830	/** PGMPhysWrite cache */
1831	PGMPHYSCACHE pgmphyswritecache;
1832
1833	/**
1834	* Data associated with managing the ring-3 mappings of the allocation chunks.
1835	*/
1836	struct
1837	{
1838	/** The chunk tree, ordered by chunk id. */
1839	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
1840	/** The chunk mapping TLB. */
1841	PGMCHUNKR3MAPTLB Tlb;
1842	/** The number of mapped chunks. */
1843	uint32_t c;
1844	/** The maximum number of mapped chunks.
1845	* @cfgm PGM/MaxRing3Chunks */
1846	uint32_t cMax;
1847	/** The chunk age tree, ordered by ageing sequence number. */
1848	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
1849	/** The current time. */
1850	uint32_t iNow;
1851	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
1852	uint32_t AgeingCountdown;
1853	} ChunkR3Map;
1854
1855	/**
1856	* The page mapping TLB for ring-3 and (for the time being) ring-0.
1857	*/
1858	PGMPAGER3MAPTLB PhysTlbHC;
1859
1860	/** @name The zero page.
1861	* @{ */
1862	/** The host physical address of the zero page. */
1863	RTHCPHYS HCPhysZeroPg;
1864	/** The ring-3 mapping of the zero page. */
1865	RTR3PTR pvZeroPgR3;
1866	/** The ring-0 mapping of the zero page. */
1867	RTR0PTR pvZeroPgR0;
1868	/** The GC mapping of the zero page. */
1869	RTGCPTR pvZeroPgGC;
1870	#if GC_ARCH_BITS != 32
1871	uint32_t u32ZeroAlignment; /*< Alignment padding. /
1872	#endif
1873	/** @}*/
1874
1875	/** The number of handy pages. */
1876	uint32_t cHandyPages;
1877	/**
1878	* Array of handy pages.
1879	*
1880	* This array is used in a two way communication between pgmPhysAllocPage
1881	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
1882	* an intermediary.
1883	*
1884	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
1885	* (The current size of 32 pages, means 128 KB of handy memory.)
1886	*/
1887	GMMPAGEDESC aHandyPages[32];
1888
1889	/** @name Release Statistics
1890	* @{ */
1891	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
1892	uint32_t cPrivatePages; /*< The number of private pages. /
1893	uint32_t cSharedPages; /*< The number of shared pages. /
1894	uint32_t cZeroPages; /*< The number of zero backed pages. /
1895	/** The number of times the guest has switched mode since last reset or statistics reset. */
1896	STAMCOUNTER cGuestModeChanges;
1897	/** @} */
1898
1899	#ifdef VBOX_WITH_STATISTICS
1900	/** GC: Which statistic this \#PF should be attributed to. */
1901	GCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
1902	RTGCPTR padding0;
1903	/** HC: Which statistic this \#PF should be attributed to. */
1904	R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
1905	RTHCPTR padding1;
1906	STAMPROFILE StatGCTrap0e; /*< GC: PGMGCTrap0eHandler() profiling. /
1907	STAMPROFILE StatTrap0eCSAM; /*< Profiling of the Trap0eHandler body when the cause is CSAM. /
1908	STAMPROFILE StatTrap0eDirtyAndAccessedBits; /*< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
1909	STAMPROFILE StatTrap0eGuestTrap; /*< Profiling of the Trap0eHandler body when the cause is a guest trap. /
1910	STAMPROFILE StatTrap0eHndPhys; /*< Profiling of the Trap0eHandler body when the cause is a physical handler. /
1911	STAMPROFILE StatTrap0eHndVirt; /*< Profiling of the Trap0eHandler body when the cause is a virtual handler. /
1912	STAMPROFILE StatTrap0eHndUnhandled; /*< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
1913	STAMPROFILE StatTrap0eMisc; /*< Profiling of the Trap0eHandler body when the cause is not known. /
1914	STAMPROFILE StatTrap0eOutOfSync; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
1915	STAMPROFILE StatTrap0eOutOfSyncHndPhys; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
1916	STAMPROFILE StatTrap0eOutOfSyncHndVirt; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
1917	STAMPROFILE StatTrap0eOutOfSyncObsHnd; /*< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
1918	STAMPROFILE StatTrap0eSyncPT; /*< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
1919
1920	STAMCOUNTER StatTrap0eMapHandler; /*< Number of traps due to access handlers in mappings. /
1921	STAMCOUNTER StatGCTrap0eConflicts; /*< GC: The number of times \#PF was caused by an undetected conflict. /
1922
1923	STAMCOUNTER StatGCTrap0eUSNotPresentRead;
1924	STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
1925	STAMCOUNTER StatGCTrap0eUSWrite;
1926	STAMCOUNTER StatGCTrap0eUSReserved;
1927	STAMCOUNTER StatGCTrap0eUSRead;
1928
1929	STAMCOUNTER StatGCTrap0eSVNotPresentRead;
1930	STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
1931	STAMCOUNTER StatGCTrap0eSVWrite;
1932	STAMCOUNTER StatGCTrap0eSVReserved;
1933
1934	STAMCOUNTER StatGCTrap0eUnhandled;
1935	STAMCOUNTER StatGCTrap0eMap;
1936
1937	/** GC: PGMSyncPT() profiling. */
1938	STAMPROFILE StatGCSyncPT;
1939	/** GC: The number of times PGMSyncPT() needed to allocate page tables. */
1940	STAMCOUNTER StatGCSyncPTAlloc;
1941	/** GC: The number of times PGMSyncPT() detected conflicts. */
1942	STAMCOUNTER StatGCSyncPTConflict;
1943	/** GC: The number of times PGMSyncPT() failed. */
1944	STAMCOUNTER StatGCSyncPTFailed;
1945	/** GC: PGMGCInvalidatePage() profiling. */
1946	STAMPROFILE StatGCInvalidatePage;
1947	/** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
1948	STAMCOUNTER StatGCInvalidatePage4KBPages;
1949	/** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
1950	STAMCOUNTER StatGCInvalidatePage4MBPages;
1951	/** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
1952	STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
1953	/** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
1954	STAMCOUNTER StatGCInvalidatePagePDNAs;
1955	/** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
1956	STAMCOUNTER StatGCInvalidatePagePDNPs;
1957	/** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
1958	STAMCOUNTER StatGCInvalidatePagePDMappings;
1959	/** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
1960	STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
1961	/** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
1962	STAMCOUNTER StatGCInvalidatePageSkipped;
1963	/** GC: The number of times user page is out of sync was detected in GC. */
1964	STAMCOUNTER StatGCPageOutOfSyncUser;
1965	/** GC: The number of times supervisor page is out of sync was detected in GC. */
1966	STAMCOUNTER StatGCPageOutOfSyncSupervisor;
1967	/** GC: The number of dynamic page mapping cache hits */
1968	STAMCOUNTER StatDynMapCacheMisses;
1969	/** GC: The number of dynamic page mapping cache misses */
1970	STAMCOUNTER StatDynMapCacheHits;
1971	/** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
1972	STAMCOUNTER StatGCGuestCR3WriteHandled;
1973	/** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
1974	STAMCOUNTER StatGCGuestCR3WriteUnhandled;
1975	/** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
1976	STAMCOUNTER StatGCGuestCR3WriteConflict;
1977	/** GC: Number of out-of-sync handled pages. */
1978	STAMCOUNTER StatHandlersOutOfSync;
1979	/** GC: Number of traps due to physical access handlers. */
1980	STAMCOUNTER StatHandlersPhysical;
1981	/** GC: Number of traps due to virtual access handlers. */
1982	STAMCOUNTER StatHandlersVirtual;
1983	/** GC: Number of traps due to virtual access handlers found by physical address. */
1984	STAMCOUNTER StatHandlersVirtualByPhys;
1985	/** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
1986	STAMCOUNTER StatHandlersVirtualUnmarked;
1987	/** GC: Number of traps due to access outside range of monitored page(s). */
1988	STAMCOUNTER StatHandlersUnhandled;
1989
1990	/** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
1991	STAMCOUNTER StatGCGuestROMWriteHandled;
1992	/** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
1993	STAMCOUNTER StatGCGuestROMWriteUnhandled;
1994
1995	/** HC: PGMR3InvalidatePage() profiling. */
1996	STAMPROFILE StatHCInvalidatePage;
1997	/** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
1998	STAMCOUNTER StatHCInvalidatePage4KBPages;
1999	/** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
2000	STAMCOUNTER StatHCInvalidatePage4MBPages;
2001	/** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
2002	STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
2003	/** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
2004	STAMCOUNTER StatHCInvalidatePagePDNAs;
2005	/** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
2006	STAMCOUNTER StatHCInvalidatePagePDNPs;
2007	/** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
2008	STAMCOUNTER StatHCInvalidatePagePDMappings;
2009	/** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2010	STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
2011	/** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2012	STAMCOUNTER StatHCInvalidatePageSkipped;
2013	/** HC: PGMR3SyncPT() profiling. */
2014	STAMPROFILE StatHCSyncPT;
2015	/** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2016	STAMPROFILE StatHCResolveConflict;
2017	/** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2018	STAMCOUNTER StatHCDetectedConflicts;
2019	/** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2020	STAMCOUNTER StatHCGuestPDWrite;
2021	/** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2022	STAMCOUNTER StatHCGuestPDWriteConflict;
2023
2024	/** HC: The number of pages marked not present for accessed bit emulation. */
2025	STAMCOUNTER StatHCAccessedPage;
2026	/** HC: The number of pages marked read-only for dirty bit tracking. */
2027	STAMCOUNTER StatHCDirtyPage;
2028	/** HC: The number of pages marked read-only for dirty bit tracking. */
2029	STAMCOUNTER StatHCDirtyPageBig;
2030	/** HC: The number of traps generated for dirty bit tracking. */
2031	STAMCOUNTER StatHCDirtyPageTrap;
2032	/** HC: The number of pages already dirty or readonly. */
2033	STAMCOUNTER StatHCDirtyPageSkipped;
2034
2035	/** GC: The number of pages marked not present for accessed bit emulation. */
2036	STAMCOUNTER StatGCAccessedPage;
2037	/** GC: The number of pages marked read-only for dirty bit tracking. */
2038	STAMCOUNTER StatGCDirtyPage;
2039	/** GC: The number of pages marked read-only for dirty bit tracking. */
2040	STAMCOUNTER StatGCDirtyPageBig;
2041	/** GC: The number of traps generated for dirty bit tracking. */
2042	STAMCOUNTER StatGCDirtyPageTrap;
2043	/** GC: The number of pages already dirty or readonly. */
2044	STAMCOUNTER StatGCDirtyPageSkipped;
2045	/** GC: The number of pages marked dirty because of write accesses. */
2046	STAMCOUNTER StatGCDirtiedPage;
2047	/** GC: The number of pages already marked dirty because of write accesses. */
2048	STAMCOUNTER StatGCPageAlreadyDirty;
2049	/** GC: The number of real pages faults during dirty bit tracking. */
2050	STAMCOUNTER StatGCDirtyTrackRealPF;
2051
2052	/** GC: Profiling of the PGMTrackDirtyBit() body */
2053	STAMPROFILE StatGCDirtyBitTracking;
2054	/** HC: Profiling of the PGMTrackDirtyBit() body */
2055	STAMPROFILE StatHCDirtyBitTracking;
2056
2057	/** GC: Profiling of the PGMGstModifyPage() body */
2058	STAMPROFILE StatGCGstModifyPage;
2059	/** HC: Profiling of the PGMGstModifyPage() body */
2060	STAMPROFILE StatHCGstModifyPage;
2061
2062	/** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2063	STAMCOUNTER StatGCSyncPagePDNAs;
2064	/** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2065	STAMCOUNTER StatGCSyncPagePDOutOfSync;
2066	/** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2067	STAMCOUNTER StatHCSyncPagePDNAs;
2068	/** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2069	STAMCOUNTER StatHCSyncPagePDOutOfSync;
2070
2071	STAMCOUNTER StatSynPT4kGC;
2072	STAMCOUNTER StatSynPT4kHC;
2073	STAMCOUNTER StatSynPT4MGC;
2074	STAMCOUNTER StatSynPT4MHC;
2075
2076	/** Profiling of the PGMFlushTLB() body. */
2077	STAMPROFILE StatFlushTLB;
2078	/** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2079	STAMCOUNTER StatFlushTLBNewCR3;
2080	/** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2081	STAMCOUNTER StatFlushTLBNewCR3Global;
2082	/** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2083	STAMCOUNTER StatFlushTLBSameCR3;
2084	/** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2085	STAMCOUNTER StatFlushTLBSameCR3Global;
2086
2087	STAMPROFILE StatGCSyncCR3; /*< GC: PGMSyncCR3() profiling. /
2088	STAMPROFILE StatGCSyncCR3Handlers; /*< GC: Profiling of the PGMSyncCR3() update handler section. /
2089	STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /*< GC: Profiling of the virtual handler resets. /
2090	STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /*< GC: Profiling of the virtual handler updates. /
2091	STAMCOUNTER StatGCSyncCR3Global; /*< GC: The number of global CR3 syncs. /
2092	STAMCOUNTER StatGCSyncCR3NotGlobal; /*< GC: The number of non-global CR3 syncs. /
2093	STAMCOUNTER StatGCSyncCR3DstFreed; /*< GC: The number of times we've had to free a shadow entry. /
2094	STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /*< GC: The number of times we've had to free a shadow entry for which the source entry was not present. /
2095	STAMCOUNTER StatGCSyncCR3DstNotPresent; /*< GC: The number of times we've encountered a not present shadow entry for a present guest entry. /
2096	STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /*< GC: The number of times a global page directory wasn't flushed. /
2097	STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /*< GC: The number of times a page table with only global entries wasn't flushed. /
2098	STAMCOUNTER StatGCSyncCR3DstCacheHit; /*< GC: The number of times we got some kind of cache hit on a page table. /
2099
2100	STAMPROFILE StatHCSyncCR3; /*< HC: PGMSyncCR3() profiling. /
2101	STAMPROFILE StatHCSyncCR3Handlers; /*< HC: Profiling of the PGMSyncCR3() update handler section. /
2102	STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /*< HC: Profiling of the virtual handler resets. /
2103	STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /*< HC: Profiling of the virtual handler updates. /
2104	STAMCOUNTER StatHCSyncCR3Global; /*< HC: The number of global CR3 syncs. /
2105	STAMCOUNTER StatHCSyncCR3NotGlobal; /*< HC: The number of non-global CR3 syncs. /
2106	STAMCOUNTER StatHCSyncCR3DstFreed; /*< HC: The number of times we've had to free a shadow entry. /
2107	STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /*< HC: The number of times we've had to free a shadow entry for which the source entry was not present. /
2108	STAMCOUNTER StatHCSyncCR3DstNotPresent; /*< HC: The number of times we've encountered a not present shadow entry for a present guest entry. /
2109	STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /*< HC: The number of times a global page directory wasn't flushed. /
2110	STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /*< HC: The number of times a page table with only global entries wasn't flushed. /
2111	STAMCOUNTER StatHCSyncCR3DstCacheHit; /*< HC: The number of times we got some kind of cache hit on a page table. /
2112
2113	/** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2114	STAMPROFILE StatVirtHandleSearchByPhysGC;
2115	/** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2116	STAMPROFILE StatVirtHandleSearchByPhysHC;
2117	/** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2118	STAMCOUNTER StatHandlePhysicalReset;
2119
2120	STAMPROFILE StatCheckPageFault;
2121	STAMPROFILE StatLazySyncPT;
2122	STAMPROFILE StatMapping;
2123	STAMPROFILE StatOutOfSync;
2124	STAMPROFILE StatHandlers;
2125	STAMPROFILE StatEIPHandlers;
2126	STAMPROFILE StatHCPrefetch;
2127
2128	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2129	/** The number of first time shadowings. */
2130	STAMCOUNTER StatTrackVirgin;
2131	/** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2132	STAMCOUNTER StatTrackAliased;
2133	/** The number of times we're tracking using cRef2. */
2134	STAMCOUNTER StatTrackAliasedMany;
2135	/** The number of times we're hitting pages which has overflowed cRef2. */
2136	STAMCOUNTER StatTrackAliasedLots;
2137	/** The number of times the extent list grows to long. */
2138	STAMCOUNTER StatTrackOverflows;
2139	/** Profiling of SyncPageWorkerTrackDeref (expensive). */
2140	STAMPROFILE StatTrackDeref;
2141	# endif
2142
2143	/** Ring-3/0 page mapper TLB hits. */
2144	STAMCOUNTER StatPageHCMapTlbHits;
2145	/** Ring-3/0 page mapper TLB misses. */
2146	STAMCOUNTER StatPageHCMapTlbMisses;
2147	/** Ring-3/0 chunk mapper TLB hits. */
2148	STAMCOUNTER StatChunkR3MapTlbHits;
2149	/** Ring-3/0 chunk mapper TLB misses. */
2150	STAMCOUNTER StatChunkR3MapTlbMisses;
2151	/** Times a shared page has been replaced by a private one. */
2152	STAMCOUNTER StatPageReplaceShared;
2153	/** Times the zero page has been replaced by a private one. */
2154	STAMCOUNTER StatPageReplaceZero;
2155	/** The number of times we've executed GMMR3AllocateHandyPages. */
2156	STAMCOUNTER StatPageHandyAllocs;
2157
2158	/** Allocated mbs of guest ram */
2159	STAMCOUNTER StatDynRamTotal;
2160	/** Nr of pgmr3PhysGrowRange calls. */
2161	STAMCOUNTER StatDynRamGrow;
2162
2163	STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2164	STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2165	STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2166	#endif
2167	} PGM, *PPGM;
2168
2169
2170	/** @name PGM::fSyncFlags Flags
2171	* @{
2172	*/
2173	/** Updates the MM_RAM_FLAGS_VIRTUAL_HANDLER page bit. */
2174	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2175	/** Always sync CR3. */
2176	#define PGM_SYNC_ALWAYS RT_BIT(1)
2177	/** Check monitoring on next CR3 (re)load and invalidate page. */
2178	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2179	/** Clear the page pool (a light weight flush). */
2180	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2181	/** @} */
2182
2183
2184	__BEGIN_DECLS
2185
2186	PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2187	PGMDECL(int) pgmGuestROMWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2188	PGMGCDECL(int) pgmCachePTWriteGC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2189	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PVBOXPD pPDSrc, int iPDOld);
2190	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2191	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, int iPDOld, int iPDNew);
2192	int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
2193	int pgmLock(PVM pVM);
2194	void pgmUnlock(PVM pVM);
2195
2196	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2197	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2198	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2199	#ifdef VBOX_STRICT
2200	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2201	#else
2202	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2203	#endif
2204	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2205
2206
2207	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2208	#ifdef IN_RING3
2209	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2210	#ifndef VBOX_WITH_NEW_PHYS_CODE
2211	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2212	#endif
2213
2214	int pgmR3PoolInit(PVM pVM);
2215	void pgmR3PoolRelocate(PVM pVM);
2216	void pgmR3PoolReset(PVM pVM);
2217
2218	#endif /* IN_RING3 */
2219	#ifdef IN_GC
2220	void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2221	#endif
2222	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage);
2223	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2224	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint16_t iUserTable);
2225	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable);
2226	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2227	void pgmPoolFlushAll(PVM pVM);
2228	void pgmPoolClearAll(PVM pVM);
2229	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2230	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2231	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2232	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2233	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2234	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2235	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2236	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2237	#ifdef PGMPOOL_WITH_MONITORING
2238	# ifdef IN_RING3
2239	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2240	# else
2241	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2242	# endif
2243	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2244	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2245	void pgmPoolMonitorModifiedClearAll(PVM pVM);
2246	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2247	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2248	#endif
2249
2250	__END_DECLS
2251
2252
2253	/**
2254	* Gets the PGMPAGE structure for a guest page.
2255	*
2256	* @returns Pointer to the page on success.
2257	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2258	*
2259	* @param pPGM PGM handle.
2260	* @param GCPhys The GC physical address.
2261	*/
2262	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2263	{
2264	/*
2265	* Optimize for the first range.
2266	*/
2267	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2268	RTGCPHYS off = GCPhys - pRam->GCPhys;
2269	if (RT_UNLIKELY(off >= pRam->cb))
2270	{
2271	do
2272	{
2273	pRam = CTXALLSUFF(pRam->pNext);
2274	if (RT_UNLIKELY(!pRam))
2275	return NULL;
2276	off = GCPhys - pRam->GCPhys;
2277	} while (off >= pRam->cb);
2278	}
2279	return &pRam->aPages[off >> PAGE_SHIFT];
2280	}
2281
2282
2283	/**
2284	* Gets the PGMPAGE structure for a guest page.
2285	*
2286	* Old Phys code: Will make sure the page is present.
2287	*
2288	* @returns VBox status code.
2289	* @retval VINF_SUCCESS and a valid *ppPage on success.
2290	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2291	*
2292	* @param pPGM PGM handle.
2293	* @param GCPhys The GC physical address.
2294	* @param ppPage Where to store the page poitner on success.
2295	*/
2296	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2297	{
2298	/*
2299	* Optimize for the first range.
2300	*/
2301	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2302	RTGCPHYS off = GCPhys - pRam->GCPhys;
2303	if (RT_UNLIKELY(off >= pRam->cb))
2304	{
2305	do
2306	{
2307	pRam = CTXALLSUFF(pRam->pNext);
2308	if (RT_UNLIKELY(!pRam))
2309	{
2310	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
2311	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2312	}
2313	off = GCPhys - pRam->GCPhys;
2314	} while (off >= pRam->cb);
2315	}
2316	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2317	#ifndef VBOX_WITH_NEW_PHYS_CODE
2318
2319	/*
2320	* Make sure it's present.
2321	*/
2322	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2323	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2324	{
2325	#ifdef IN_RING3
2326	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2327	#else
2328	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2329	#endif
2330	if (VBOX_FAILURE(rc))
2331	{
2332	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
2333	return rc;
2334	}
2335	Assert(rc == VINF_SUCCESS);
2336	}
2337	#endif
2338	return VINF_SUCCESS;
2339	}
2340
2341
2342
2343
2344	/**
2345	* Gets the PGMPAGE structure for a guest page.
2346	*
2347	* Old Phys code: Will make sure the page is present.
2348	*
2349	* @returns VBox status code.
2350	* @retval VINF_SUCCESS and a valid *ppPage on success.
2351	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2352	*
2353	* @param pPGM PGM handle.
2354	* @param GCPhys The GC physical address.
2355	* @param ppPage Where to store the page poitner on success.
2356	* @param ppRamHint Where to read and store the ram list hint.
2357	* The caller initializes this to NULL before the call.
2358	*/
2359	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2360	{
2361	RTGCPHYS off;
2362	PPGMRAMRANGE pRam = *ppRamHint;
2363	if ( !pRam
2364	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2365	{
2366	pRam = CTXALLSUFF(pPGM->pRamRanges);
2367	off = GCPhys - pRam->GCPhys;
2368	if (RT_UNLIKELY(off >= pRam->cb))
2369	{
2370	do
2371	{
2372	pRam = CTXALLSUFF(pRam->pNext);
2373	if (RT_UNLIKELY(!pRam))
2374	{
2375	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
2376	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2377	}
2378	off = GCPhys - pRam->GCPhys;
2379	} while (off >= pRam->cb);
2380	}
2381	*ppRamHint = pRam;
2382	}
2383	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2384	#ifndef VBOX_WITH_NEW_PHYS_CODE
2385
2386	/*
2387	* Make sure it's present.
2388	*/
2389	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2390	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2391	{
2392	#ifdef IN_RING3
2393	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2394	#else
2395	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2396	#endif
2397	if (VBOX_FAILURE(rc))
2398	{
2399	ppPage = NULL; / Shut up annoying smart ass. */
2400	return rc;
2401	}
2402	Assert(rc == VINF_SUCCESS);
2403	}
2404	#endif
2405	return VINF_SUCCESS;
2406	}
2407
2408
2409	/**
2410	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2411	*
2412	* @returns Pointer to the page on success.
2413	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2414	*
2415	* @param pPGM PGM handle.
2416	* @param GCPhys The GC physical address.
2417	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
2418	*/
2419	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2420	{
2421	/*
2422	* Optimize for the first range.
2423	*/
2424	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2425	RTGCPHYS off = GCPhys - pRam->GCPhys;
2426	if (RT_UNLIKELY(off >= pRam->cb))
2427	{
2428	do
2429	{
2430	pRam = CTXALLSUFF(pRam->pNext);
2431	if (RT_UNLIKELY(!pRam))
2432	return NULL;
2433	off = GCPhys - pRam->GCPhys;
2434	} while (off >= pRam->cb);
2435	}
2436	*ppRam = pRam;
2437	return &pRam->aPages[off >> PAGE_SHIFT];
2438	}
2439
2440
2441
2442
2443	/**
2444	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2445	*
2446	* @returns Pointer to the page on success.
2447	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2448	*
2449	* @param pPGM PGM handle.
2450	* @param GCPhys The GC physical address.
2451	* @param ppPage Where to store the pointer to the PGMPAGE structure.
2452	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2453	*/
2454	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2455	{
2456	/*
2457	* Optimize for the first range.
2458	*/
2459	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2460	RTGCPHYS off = GCPhys - pRam->GCPhys;
2461	if (RT_UNLIKELY(off >= pRam->cb))
2462	{
2463	do
2464	{
2465	pRam = CTXALLSUFF(pRam->pNext);
2466	if (RT_UNLIKELY(!pRam))
2467	{
2468	ppRam = NULL; / Shut up silly GCC warnings. */
2469	ppPage = NULL; / ditto */
2470	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2471	}
2472	off = GCPhys - pRam->GCPhys;
2473	} while (off >= pRam->cb);
2474	}
2475	*ppRam = pRam;
2476	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2477	#ifndef VBOX_WITH_NEW_PHYS_CODE
2478
2479	/*
2480	* Make sure it's present.
2481	*/
2482	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2483	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2484	{
2485	#ifdef IN_RING3
2486	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2487	#else
2488	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2489	#endif
2490	if (VBOX_FAILURE(rc))
2491	{
2492	ppPage = NULL; / Shut up silly GCC warnings. */
2493	ppPage = NULL; / ditto */
2494	return rc;
2495	}
2496	Assert(rc == VINF_SUCCESS);
2497
2498	}
2499	#endif
2500	return VINF_SUCCESS;
2501	}
2502
2503
2504	/**
2505	* Convert GC Phys to HC Phys.
2506	*
2507	* @returns VBox status.
2508	* @param pPGM PGM handle.
2509	* @param GCPhys The GC physical address.
2510	* @param pHCPhys Where to store the corresponding HC physical address.
2511	*
2512	* @deprecated Doesn't deal with zero, shared or write monitored pages.
2513	* Avoid when writing new code!
2514	*/
2515	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2516	{
2517	PPGMPAGE pPage;
2518	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2519	if (VBOX_FAILURE(rc))
2520	return rc;
2521	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
2522	return VINF_SUCCESS;
2523	}
2524
2525
2526	#ifndef IN_GC
2527	/**
2528	* Queries the Physical TLB entry for a physical guest page,
2529	* attemting to load the TLB entry if necessary.
2530	*
2531	* @returns VBox status code.
2532	* @retval VINF_SUCCESS on success
2533	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2534	* @param pPGM The PGM instance handle.
2535	* @param GCPhys The address of the guest page.
2536	* @param ppTlbe Where to store the pointer to the TLB entry.
2537	*/
2538
2539	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
2540	{
2541	int rc;
2542	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
2543	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
2544	{
2545	STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
2546	rc = VINF_SUCCESS;
2547	}
2548	else
2549	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
2550	*ppTlbe = pTlbe;
2551	return rc;
2552	}
2553	#endif /* !IN_GC */
2554
2555
2556	#ifndef VBOX_WITH_NEW_PHYS_CODE
2557	/**
2558	* Convert GC Phys to HC Virt.
2559	*
2560	* @returns VBox status.
2561	* @param pPGM PGM handle.
2562	* @param GCPhys The GC physical address.
2563	* @param pHCPtr Where to store the corresponding HC virtual address.
2564	*
2565	* @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
2566	*/
2567	DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
2568	{
2569	PPGMRAMRANGE pRam;
2570	PPGMPAGE pPage;
2571	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
2572	if (VBOX_FAILURE(rc))
2573	{
2574	pHCPtr = 0; / Shut up silly GCC warnings. */
2575	return rc;
2576	}
2577	RTGCPHYS off = GCPhys - pRam->GCPhys;
2578
2579	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2580	{
2581	unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
2582	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2583	return VINF_SUCCESS;
2584	}
2585	if (pRam->pvHC)
2586	{
2587	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
2588	return VINF_SUCCESS;
2589	}
2590	pHCPtr = 0; / Shut up silly GCC warnings. */
2591	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2592	}
2593	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2594
2595
2596	/**
2597	* Convert GC Phys to HC Virt.
2598	*
2599	* @returns VBox status.
2600	* @param PVM VM handle.
2601	* @param pRam Ram range
2602	* @param GCPhys The GC physical address.
2603	* @param pHCPtr Where to store the corresponding HC virtual address.
2604	*
2605	* @deprecated This will be eliminated. Don't use it.
2606	*/
2607	DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
2608	{
2609	RTGCPHYS off = GCPhys - pRam->GCPhys;
2610	Assert(off < pRam->cb);
2611
2612	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2613	{
2614	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
2615	/* Physical chunk in dynamically allocated range not present? */
2616	if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
2617	{
2618	#ifdef IN_RING3
2619	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2620	#else
2621	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2622	#endif
2623	if (rc != VINF_SUCCESS)
2624	{
2625	pHCPtr = 0; / GCC crap */
2626	return rc;
2627	}
2628	}
2629	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2630	return VINF_SUCCESS;
2631	}
2632	if (pRam->pvHC)
2633	{
2634	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
2635	return VINF_SUCCESS;
2636	}
2637	pHCPtr = 0; / GCC crap */
2638	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2639	}
2640
2641
2642	/**
2643	* Convert GC Phys to HC Virt and HC Phys.
2644	*
2645	* @returns VBox status.
2646	* @param pPGM PGM handle.
2647	* @param GCPhys The GC physical address.
2648	* @param pHCPtr Where to store the corresponding HC virtual address.
2649	* @param pHCPhys Where to store the HC Physical address and its flags.
2650	*
2651	* @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
2652	* and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
2653	*/
2654	DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
2655	{
2656	PPGMRAMRANGE pRam;
2657	PPGMPAGE pPage;
2658	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
2659	if (VBOX_FAILURE(rc))
2660	{
2661	pHCPtr = 0; / Shut up crappy GCC warnings */
2662	pHCPhys = 0; / ditto */
2663	return rc;
2664	}
2665	RTGCPHYS off = GCPhys - pRam->GCPhys;
2666
2667	pHCPhys = pPage->HCPhys; /* @todo PAGE FLAGS */
2668	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2669	{
2670	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
2671	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2672	return VINF_SUCCESS;
2673	}
2674	if (pRam->pvHC)
2675	{
2676	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
2677	return VINF_SUCCESS;
2678	}
2679	*pHCPtr = 0;
2680	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2681	}
2682
2683
2684	/**
2685	* Clears flags associated with a RAM address.
2686	*
2687	* @returns VBox status code.
2688	* @param pPGM PGM handle.
2689	* @param GCPhys Guest context physical address.
2690	* @param fFlags fFlags to clear. (Bits 0-11.)
2691	*/
2692	DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
2693	{
2694	PPGMPAGE pPage;
2695	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2696	if (VBOX_FAILURE(rc))
2697	return rc;
2698
2699	fFlags &= ~X86_PTE_PAE_PG_MASK;
2700	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
2701	return VINF_SUCCESS;
2702	}
2703
2704
2705	/**
2706	* Clears flags associated with a RAM address.
2707	*
2708	* @returns VBox status code.
2709	* @param pPGM PGM handle.
2710	* @param GCPhys Guest context physical address.
2711	* @param fFlags fFlags to clear. (Bits 0-11.)
2712	* @param ppRamHint Where to read and store the ram list hint.
2713	* The caller initializes this to NULL before the call.
2714	*/
2715	DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
2716	{
2717	PPGMPAGE pPage;
2718	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
2719	if (VBOX_FAILURE(rc))
2720	return rc;
2721
2722	fFlags &= ~X86_PTE_PAE_PG_MASK;
2723	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
2724	return VINF_SUCCESS;
2725	}
2726
2727	/**
2728	* Sets (bitwise OR) flags associated with a RAM address.
2729	*
2730	* @returns VBox status code.
2731	* @param pPGM PGM handle.
2732	* @param GCPhys Guest context physical address.
2733	* @param fFlags fFlags to set clear. (Bits 0-11.)
2734	*/
2735	DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
2736	{
2737	PPGMPAGE pPage;
2738	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2739	if (VBOX_FAILURE(rc))
2740	return rc;
2741
2742	fFlags &= ~X86_PTE_PAE_PG_MASK;
2743	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
2744	return VINF_SUCCESS;
2745	}
2746
2747
2748	/**
2749	* Sets (bitwise OR) flags associated with a RAM address.
2750	*
2751	* @returns VBox status code.
2752	* @param pPGM PGM handle.
2753	* @param GCPhys Guest context physical address.
2754	* @param fFlags fFlags to set clear. (Bits 0-11.)
2755	* @param ppRamHint Where to read and store the ram list hint.
2756	* The caller initializes this to NULL before the call.
2757	*/
2758	DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
2759	{
2760	PPGMPAGE pPage;
2761	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
2762	if (VBOX_FAILURE(rc))
2763	return rc;
2764
2765	fFlags &= ~X86_PTE_PAE_PG_MASK;
2766	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
2767	return VINF_SUCCESS;
2768	}
2769
2770
2771	/**
2772	* Gets the page directory for the specified address.
2773	*
2774	* @returns Pointer to the page directory in question.
2775	* @returns NULL if the page directory is not present or on an invalid page.
2776	* @param pPGM Pointer to the PGM instance data.
2777	* @param GCPtr The address.
2778	*/
2779	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
2780	{
2781	const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2782	if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2783	{
2784	if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2785	return CTXSUFF(pPGM->apGstPaePDs)[iPdPtr];
2786
2787	/* cache is out-of-sync. */
2788	PX86PDPAE pPD;
2789	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2790	if (VBOX_SUCCESS(rc))
2791	return pPD;
2792	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2793	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
2794	}
2795	return NULL;
2796	}
2797
2798
2799	/**
2800	* Gets the page directory entry for the specified address.
2801	*
2802	* @returns Pointer to the page directory entry in question.
2803	* @returns NULL if the page directory is not present or on an invalid page.
2804	* @param pPGM Pointer to the PGM instance data.
2805	* @param GCPtr The address.
2806	*/
2807	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
2808	{
2809	const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2810	if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2811	{
2812	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
2813	if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2814	return &CTXSUFF(pPGM->apGstPaePDs)[iPdPtr]->a[iPD];
2815
2816	/* The cache is out-of-sync. */
2817	PX86PDPAE pPD;
2818	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2819	if (VBOX_SUCCESS(rc))
2820	return &pPD->a[iPD];
2821	AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2822	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
2823	}
2824	return NULL;
2825	}
2826
2827
2828	/**
2829	* Gets the page directory entry for the specified address.
2830	*
2831	* @returns The page directory entry in question.
2832	* @returns A non-present entry if the page directory is not present or on an invalid page.
2833	* @param pPGM Pointer to the PGM instance data.
2834	* @param GCPtr The address.
2835	*/
2836	DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
2837	{
2838	const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2839	if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2840	{
2841	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
2842	if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2843	return CTXSUFF(pPGM->apGstPaePDs)[iPdPtr]->a[iPD].u;
2844
2845	/* cache is out-of-sync. */
2846	PX86PDPAE pPD;
2847	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2848	if (VBOX_SUCCESS(rc))
2849	return pPD->a[iPD].u;
2850	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2851	}
2852	return 0;
2853	}
2854
2855
2856	/**
2857	* Gets the page directory for the specified address and returns the index into the page directory
2858	*
2859	* @returns Pointer to the page directory in question.
2860	* @returns NULL if the page directory is not present or on an invalid page.
2861	* @param pPGM Pointer to the PGM instance data.
2862	* @param GCPtr The address.
2863	* @param piPD Receives the index into the returned page directory
2864	*/
2865	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
2866	{
2867	const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2868	if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2869	{
2870	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
2871	if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2872	{
2873	*piPD = iPD;
2874	return CTXSUFF(pPGM->apGstPaePDs)[iPdPtr];
2875	}
2876
2877	/* cache is out-of-sync. */
2878	PX86PDPAE pPD;
2879	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2880	if (VBOX_SUCCESS(rc))
2881	{
2882	*piPD = iPD;
2883	return pPD;
2884	}
2885	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2886	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
2887	}
2888	return NULL;
2889	}
2890
2891
2892	/**
2893	* Checks if any of the specified page flags are set for the given page.
2894	*
2895	* @returns true if any of the flags are set.
2896	* @returns false if all the flags are clear.
2897	* @param pPGM PGM handle.
2898	* @param GCPhys The GC physical address.
2899	* @param fFlags The flags to check for.
2900	*/
2901	DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
2902	{
2903	PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
2904	return pPage
2905	&& (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
2906	}
2907
2908
2909	/**
2910	* Gets the ram flags for a handler.
2911	*
2912	* @returns The ram flags.
2913	* @param pCur The physical handler in question.
2914	*/
2915	DECLINLINE(unsigned) pgmHandlerPhysicalCalcFlags(PPGMPHYSHANDLER pCur)
2916	{
2917	switch (pCur->enmType)
2918	{
2919	case PGMPHYSHANDLERTYPE_PHYSICAL:
2920	return MM_RAM_FLAGS_PHYSICAL_HANDLER;
2921
2922	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
2923	return MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE;
2924
2925	case PGMPHYSHANDLERTYPE_MMIO:
2926	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
2927	return MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_ALL;
2928
2929	default:
2930	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
2931	}
2932	}
2933
2934
2935	/**
2936	* Clears one physical page of a virtual handler
2937	*
2938	* @param pPGM Pointer to the PGM instance.
2939	* @param pCur Virtual handler structure
2940	* @param iPage Physical page index
2941	*/
2942	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
2943	{
2944	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
2945
2946	/*
2947	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
2948	*/
2949	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2950	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
2951	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2952	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
2953	#endif
2954	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
2955	{
2956	/* We're the head of the alias chain. */
2957	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
2958	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2959	AssertReleaseMsg(pRemove != NULL,
2960	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2961	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
2962	AssertReleaseMsg(pRemove == pPhys2Virt,
2963	("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
2964	" got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2965	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
2966	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
2967	#endif
2968	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
2969	{
2970	/* Insert the next list in the alias chain into the tree. */
2971	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
2972	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2973	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
2974	("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2975	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
2976	#endif
2977	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
2978	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
2979	AssertRelease(fRc);
2980	}
2981	}
2982	else
2983	{
2984	/* Locate the previous node in the alias chain. */
2985	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
2986	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2987	AssertReleaseMsg(pPrev != pPhys2Virt,
2988	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
2989	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
2990	#endif
2991	for (;;)
2992	{
2993	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
2994	if (pNext == pPhys2Virt)
2995	{
2996	/* unlink. */
2997	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
2998	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
2999	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3000	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3001	else
3002	{
3003	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3004	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3005	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3006	}
3007	break;
3008	}
3009
3010	/* next */
3011	if (pNext == pPrev)
3012	{
3013	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3014	AssertReleaseMsg(pNext != pPrev,
3015	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3016	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3017	#endif
3018	break;
3019	}
3020	pPrev = pNext;
3021	}
3022	}
3023	Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3024	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3025	pPhys2Virt->offNextAlias = 0;
3026	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3027
3028	/*
3029	* Clear the ram flags for this page.
3030	*/
3031	int rc = pgmRamFlagsClearByGCPhys(pPGM, pPhys2Virt->Core.Key,
3032	MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_VIRTUAL_WRITE);
3033	AssertRC(rc);
3034	}
3035
3036
3037	/**
3038	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
3039	*
3040	* @returns Pointer to the shadow page structure.
3041	* @param pPool The pool.
3042	* @param HCPhys The HC physical address of the shadow page.
3043	*/
3044	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3045	{
3046	/*
3047	* Look up the page.
3048	*/
3049	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3050	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3051	return pPage;
3052	}
3053
3054
3055	/**
3056	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
3057	*
3058	* @returns Pointer to the shadow page structure.
3059	* @param pPool The pool.
3060	* @param idx The pool page index.
3061	*/
3062	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3063	{
3064	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3065	return &pPool->aPages[idx];
3066	}
3067
3068
3069	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3070	/**
3071	* Clear references to guest physical memory.
3072	*
3073	* @param pPool The pool.
3074	* @param pPoolPage The pool page.
3075	* @param pPhysPage The physical guest page tracking structure.
3076	*/
3077	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3078	{
3079	/*
3080	* Just deal with the simple case here.
3081	*/
3082	#ifdef LOG_ENABLED
3083	const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3084	#endif
3085	const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3086	if (cRefs == 1)
3087	{
3088	Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3089	pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3090	}
3091	else
3092	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3093	LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3094	}
3095	#endif
3096
3097
3098	#ifdef PGMPOOL_WITH_CACHE
3099	/**
3100	* Moves the page to the head of the age list.
3101	*
3102	* This is done when the cached page is used in one way or another.
3103	*
3104	* @param pPool The pool.
3105	* @param pPage The cached page.
3106	* @todo inline in PGMInternal.h!
3107	*/
3108	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3109	{
3110	/*
3111	* Move to the head of the age list.
3112	*/
3113	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3114	{
3115	/* unlink */
3116	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3117	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3118	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3119	else
3120	pPool->iAgeTail = pPage->iAgePrev;
3121
3122	/* insert at head */
3123	pPage->iAgePrev = NIL_PGMPOOL_IDX;
3124	pPage->iAgeNext = pPool->iAgeHead;
3125	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3126	pPool->iAgeHead = pPage->idx;
3127	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3128	}
3129	}
3130	#endif /* PGMPOOL_WITH_CACHE */
3131
3132	/**
3133	* Tells if mappings are to be put into the shadow page table or not
3134	*
3135	* @returns boolean result
3136	* @param pVM VM handle.
3137	*/
3138
3139	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3140	{
3141	return !pPGM->fDisableMappings;
3142	}
3143
3144	/** @} */
3145
3146	#endif

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 6829

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