PGMInternal.h@ 8533

Last change on this file since 8533 was 8533, checked in by vboxsync, 17 years ago
Start of 64 bits paging support
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1	/* $Id: PGMInternal.h 8533 2008-05-02 16:04:51Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <iprt/avl.h>
39	#include <iprt/assert.h>
40	#include <iprt/critsect.h>
41
42	#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
43	# error "Not in PGM! This is an internal header!"
44	#endif
45
46
47	/** @defgroup grp_pgm_int Internals
48	* @ingroup grp_pgm
49	* @internal
50	* @{
51	*/
52
53
54	/** @name PGM Compile Time Config
55	* @{
56	*/
57
58	/**
59	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
60	* Comment it if it will break something.
61	*/
62	#define PGM_OUT_OF_SYNC_IN_GC
63
64	/**
65	* Virtualize the dirty bit
66	* This also makes a half-hearted attempt at the accessed bit. For full
67	* accessed bit virtualization define PGM_SYNC_ACCESSED_BIT.
68	*/
69	#define PGM_SYNC_DIRTY_BIT
70
71	/**
72	* Fully virtualize the accessed bit.
73	* @remark This requires SYNC_DIRTY_ACCESSED_BITS to be defined!
74	*/
75	#define PGM_SYNC_ACCESSED_BIT
76
77	/**
78	* Check and skip global PDEs for non-global flushes
79	*/
80	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
81
82	/**
83	* Sync N pages instead of a whole page table
84	*/
85	#define PGM_SYNC_N_PAGES
86
87	/**
88	* Number of pages to sync during a page fault
89	*
90	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
91	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
92	*/
93	#define PGM_SYNC_NR_PAGES 8
94
95	/**
96	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
97	*/
98	#define PGM_MAX_PHYSCACHE_ENTRIES 64
99	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
100
101	/**
102	* Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
103	*/
104	#define PGM_PHYSMEMACCESS_CACHING
105
106	/*
107	* Assert Sanity.
108	*/
109	#if defined(PGM_SYNC_ACCESSED_BIT) && !defined(PGM_SYNC_DIRTY_BIT)
110	# error "PGM_SYNC_ACCESSED_BIT requires PGM_SYNC_DIRTY_BIT!"
111	#endif
112
113	/** @def PGMPOOL_WITH_CACHE
114	* Enable agressive caching using the page pool.
115	*
116	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
117	*/
118	#define PGMPOOL_WITH_CACHE
119
120	/** @def PGMPOOL_WITH_MIXED_PT_CR3
121	* When defined, we'll deal with 'uncachable' pages.
122	*/
123	#ifdef PGMPOOL_WITH_CACHE
124	# define PGMPOOL_WITH_MIXED_PT_CR3
125	#endif
126
127	/** @def PGMPOOL_WITH_MONITORING
128	* Monitor the guest pages which are shadowed.
129	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
130	* be enabled as well.
131	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
132	*/
133	#ifdef PGMPOOL_WITH_CACHE
134	# define PGMPOOL_WITH_MONITORING
135	#endif
136
137	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
138	* Tracking the of shadow pages mapping guest physical pages.
139	*
140	* This is very expensive, the current cache prototype is trying to figure out
141	* whether it will be acceptable with an agressive caching policy.
142	*/
143	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
144	# define PGMPOOL_WITH_GCPHYS_TRACKING
145	#endif
146
147	/** @def PGMPOOL_WITH_USER_TRACKNG
148	* Tracking users of shadow pages. This is required for the linking of shadow page
149	* tables and physical guest addresses.
150	*/
151	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
152	# define PGMPOOL_WITH_USER_TRACKING
153	#endif
154
155	/** @def PGMPOOL_CFG_MAX_GROW
156	* The maximum number of pages to add to the pool in one go.
157	*/
158	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
159
160	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
161	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
162	*/
163	#ifdef VBOX_STRICT
164	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
165	#endif
166	/** @} */
167
168
169	/** @name PDPT and PML4 flags.
170	* These are placed in the three bits available for system programs in
171	* the PDPT and PML4 entries.
172	* @{ */
173	/** The entry is a permanent one and it's must always be present.
174	* Never free such an entry. */
175	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
176	/** Mapping (hypervisor allocated pagetable). */
177	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
178	/** @} */
179
180	/** @name Page directory flags.
181	* These are placed in the three bits available for system programs in
182	* the page directory entries.
183	* @{ */
184	/** Mapping (hypervisor allocated pagetable). */
185	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
186	/** Made read-only to facilitate dirty bit tracking. */
187	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
188	/** @} */
189
190	/** @name Page flags.
191	* These are placed in the three bits available for system programs in
192	* the page entries.
193	* @{ */
194	/** Made read-only to facilitate dirty bit tracking. */
195	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
196
197	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
198	/** Scanned and approved by CSAM (tm).
199	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
200	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
201	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
202	#endif
203	/** @} */
204
205	/** @name Defines used to indicate the shadow and guest paging in the templates.
206	* @{ */
207	#define PGM_TYPE_REAL 1
208	#define PGM_TYPE_PROT 2
209	#define PGM_TYPE_32BIT 3
210	#define PGM_TYPE_PAE 4
211	#define PGM_TYPE_AMD64 5
212	/** @} */
213
214	/** Macro for checking if the guest is using paging.
215	* @param uType PGM_TYPE_*
216	* @remark ASSUMES certain order of the PGM_TYPE_* values.
217	*/
218	#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT)
219
220	/** Macro for checking if the guest supports the NX bit.
221	* @param uType PGM_TYPE_*
222	* @remark ASSUMES certain order of the PGM_TYPE_* values.
223	*/
224	#define PGM_WITH_NX(uType) ((uType) >= PGM_TYPE_PAE)
225
226
227	/** @def PGM_HCPHYS_2_PTR
228	* Maps a HC physical page pool address to a virtual address.
229	*
230	* @returns VBox status code.
231	* @param pVM The VM handle.
232	* @param HCPhys The HC physical address to map to a virtual one.
233	* @param ppv Where to store the virtual address. No need to cast this.
234	*
235	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
236	* small page window employeed by that function. Be careful.
237	* @remark There is no need to assert on the result.
238	*/
239	#ifdef IN_GC
240	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
241	#else
242	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
243	#endif
244
245	/** @def PGM_GCPHYS_2_PTR
246	* Maps a GC physical page address to a virtual address.
247	*
248	* @returns VBox status code.
249	* @param pVM The VM handle.
250	* @param GCPhys The GC physical address to map to a virtual one.
251	* @param ppv Where to store the virtual address. No need to cast this.
252	*
253	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
254	* small page window employeed by that function. Be careful.
255	* @remark There is no need to assert on the result.
256	*/
257	#ifdef IN_GC
258	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
259	#else
260	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only /, (void )(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
261	#endif
262
263	/** @def PGM_GCPHYS_2_PTR_EX
264	* Maps a unaligned GC physical page address to a virtual address.
265	*
266	* @returns VBox status code.
267	* @param pVM The VM handle.
268	* @param GCPhys The GC physical address to map to a virtual one.
269	* @param ppv Where to store the virtual address. No need to cast this.
270	*
271	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
272	* small page window employeed by that function. Be careful.
273	* @remark There is no need to assert on the result.
274	*/
275	#ifdef IN_GC
276	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
277	#else
278	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only /, (void )(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
279	#endif
280
281	/** @def PGM_INVL_PG
282	* Invalidates a page when in GC does nothing in HC.
283	*
284	* @param GCVirt The virtual address of the page to invalidate.
285	*/
286	#ifdef IN_GC
287	# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
288	#else
289	# define PGM_INVL_PG(GCVirt) ((void)0)
290	#endif
291
292	/** @def PGM_INVL_BIG_PG
293	* Invalidates a 4MB page directory entry when in GC does nothing in HC.
294	*
295	* @param GCVirt The virtual address within the page directory to invalidate.
296	*/
297	#ifdef IN_GC
298	# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
299	#else
300	# define PGM_INVL_BIG_PG(GCVirt) ((void)0)
301	#endif
302
303	/** @def PGM_INVL_GUEST_TLBS()
304	* Invalidates all guest TLBs.
305	*/
306	#ifdef IN_GC
307	# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
308	#else
309	# define PGM_INVL_GUEST_TLBS() ((void)0)
310	#endif
311
312
313	/**
314	* Structure for tracking GC Mappings.
315	*
316	* This structure is used by linked list in both GC and HC.
317	*/
318	typedef struct PGMMAPPING
319	{
320	/** Pointer to next entry. */
321	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
322	/** Pointer to next entry. */
323	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
324	/** Pointer to next entry. */
325	GCPTRTYPE(struct PGMMAPPING *) pNextGC;
326	/** Start Virtual address. */
327	RTGCUINTPTR GCPtr;
328	/** Last Virtual address (inclusive). */
329	RTGCUINTPTR GCPtrLast;
330	/** Range size (bytes). */
331	RTGCUINTPTR cb;
332	/** Pointer to relocation callback function. */
333	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
334	/** User argument to the callback. */
335	R3PTRTYPE(void *) pvUser;
336	/** Mapping description / name. For easing debugging. */
337	R3PTRTYPE(const char *) pszDesc;
338	/** Number of page tables. */
339	RTUINT cPTs;
340	#if HC_ARCH_BITS != GC_ARCH_BITS
341	RTUINT uPadding0; /*< Alignment padding. /
342	#endif
343	/** Array of page table mapping data. Each entry
344	* describes one page table. The array can be longer
345	* than the declared length.
346	*/
347	struct
348	{
349	/** The HC physical address of the page table. */
350	RTHCPHYS HCPhysPT;
351	/** The HC physical address of the first PAE page table. */
352	RTHCPHYS HCPhysPaePT0;
353	/** The HC physical address of the second PAE page table. */
354	RTHCPHYS HCPhysPaePT1;
355	/** The HC virtual address of the 32-bit page table. */
356	R3PTRTYPE(PX86PT) pPTR3;
357	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
358	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
359	/** The GC virtual address of the 32-bit page table. */
360	GCPTRTYPE(PX86PT) pPTGC;
361	/** The GC virtual address of the two PAE page table. */
362	GCPTRTYPE(PX86PTPAE) paPaePTsGC;
363	/** The GC virtual address of the 32-bit page table. */
364	R0PTRTYPE(PX86PT) pPTR0;
365	/** The GC virtual address of the two PAE page table. */
366	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
367	} aPTs[1];
368	} PGMMAPPING;
369	/** Pointer to structure for tracking GC Mappings. */
370	typedef struct PGMMAPPING *PPGMMAPPING;
371
372
373	/**
374	* Physical page access handler structure.
375	*
376	* This is used to keep track of physical address ranges
377	* which are being monitored in some kind of way.
378	*/
379	typedef struct PGMPHYSHANDLER
380	{
381	AVLROGCPHYSNODECORE Core;
382	/** Access type. */
383	PGMPHYSHANDLERTYPE enmType;
384	/** Number of pages to update. */
385	uint32_t cPages;
386	/** Pointer to R3 callback function. */
387	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
388	/** User argument for R3 handlers. */
389	R3PTRTYPE(void *) pvUserR3;
390	/** Pointer to R0 callback function. */
391	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
392	/** User argument for R0 handlers. */
393	R0PTRTYPE(void *) pvUserR0;
394	/** Pointer to GC callback function. */
395	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
396	/** User argument for GC handlers. */
397	GCPTRTYPE(void *) pvUserGC;
398	/** Description / Name. For easing debugging. */
399	R3PTRTYPE(const char *) pszDesc;
400	#ifdef VBOX_WITH_STATISTICS
401	/** Profiling of this handler. */
402	STAMPROFILE Stat;
403	#endif
404	} PGMPHYSHANDLER;
405	/** Pointer to a physical page access handler structure. */
406	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
407
408
409	/**
410	* Cache node for the physical addresses covered by a virtual handler.
411	*/
412	typedef struct PGMPHYS2VIRTHANDLER
413	{
414	/** Core node for the tree based on physical ranges. */
415	AVLROGCPHYSNODECORE Core;
416	/** Offset from this struct to the PGMVIRTHANDLER structure. */
417	int32_t offVirtHandler;
418	/** Offset of the next alias relative to this one.
419	* Bit 0 is used for indicating whether we're in the tree.
420	* Bit 1 is used for indicating that we're the head node.
421	*/
422	int32_t offNextAlias;
423	} PGMPHYS2VIRTHANDLER;
424	/** Pointer to a phys to virtual handler structure. */
425	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
426
427	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
428	* node is in the tree. */
429	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
430	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
431	* node is in the head of an alias chain.
432	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
433	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
434	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
435	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
436
437
438	/**
439	* Virtual page access handler structure.
440	*
441	* This is used to keep track of virtual address ranges
442	* which are being monitored in some kind of way.
443	*/
444	typedef struct PGMVIRTHANDLER
445	{
446	/** Core node for the tree based on virtual ranges. */
447	AVLROGCPTRNODECORE Core;
448	/** Number of cache pages. */
449	uint32_t u32Padding;
450	/** Access type. */
451	PGMVIRTHANDLERTYPE enmType;
452	/** Number of cache pages. */
453	uint32_t cPages;
454
455	/** @todo The next two members are redundant. It adds some readability though. */
456	/** Start of the range. */
457	RTGCPTR GCPtr;
458	/** End of the range (exclusive). */
459	RTGCPTR GCPtrLast;
460	/** Size of the range (in bytes). */
461	RTGCUINTPTR cb;
462	/** Pointer to the GC callback function. */
463	GCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
464	/** Pointer to the HC callback function for invalidation. */
465	R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
466	/** Pointer to the HC callback function. */
467	R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
468	/** Description / Name. For easing debugging. */
469	R3PTRTYPE(const char *) pszDesc;
470	#ifdef VBOX_WITH_STATISTICS
471	/** Profiling of this handler. */
472	STAMPROFILE Stat;
473	#endif
474	/** Array of cached physical addresses for the monitored ranged. */
475	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
476	} PGMVIRTHANDLER;
477	/** Pointer to a virtual page access handler structure. */
478	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
479
480
481	/**
482	* Page type.
483	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
484	* @todo convert to \#defines.
485	*/
486	typedef enum PGMPAGETYPE
487	{
488	/** The usual invalid zero entry. */
489	PGMPAGETYPE_INVALID = 0,
490	/** RAM page. (RWX) */
491	PGMPAGETYPE_RAM,
492	/** MMIO2 page. (RWX) */
493	PGMPAGETYPE_MMIO2,
494	/** Shadowed ROM. (RWX) */
495	PGMPAGETYPE_ROM_SHADOW,
496	/** ROM page. (R-X) */
497	PGMPAGETYPE_ROM,
498	/** MMIO page. (---) */
499	PGMPAGETYPE_MMIO,
500	/** End of valid entries. */
501	PGMPAGETYPE_END
502	} PGMPAGETYPE;
503	AssertCompile(PGMPAGETYPE_END < 7);
504
505	/** @name Page type predicates.
506	* @{ */
507	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
508	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
509	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
510	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
511	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
512	/** @} */
513
514
515	/**
516	* A Physical Guest Page tracking structure.
517	*
518	* The format of this structure is complicated because we have to fit a lot
519	* of information into as few bits as possible. The format is also subject
520	* to change (there is one comming up soon). Which means that for we'll be
521	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
522	* accessess to the structure.
523	*/
524	typedef struct PGMPAGE
525	{
526	/** The physical address and a whole lot of other stuff. All bits are used! */
527	RTHCPHYS HCPhys;
528	/** The page state. */
529	uint32_t u2StateX : 2;
530	/** Flag indicating that a write monitored page was written to when set. */
531	uint32_t fWrittenToX : 1;
532	/** For later. */
533	uint32_t fSomethingElse : 1;
534	/** The Page ID.
535	* @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
536	* The HCPhys will be 100% static. */
537	uint32_t idPageX : 28;
538	/** The page type (PGMPAGETYPE). */
539	uint32_t u3Type : 3;
540	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
541	uint32_t u2HandlerPhysStateX : 2;
542	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
543	uint32_t u2HandlerVirtStateX : 2;
544	uint32_t u29B : 25;
545	} PGMPAGE;
546	AssertCompileSize(PGMPAGE, 16);
547	/** Pointer to a physical guest page. */
548	typedef PGMPAGE *PPGMPAGE;
549	/** Pointer to a const physical guest page. */
550	typedef const PGMPAGE *PCPGMPAGE;
551	/** Pointer to a physical guest page pointer. */
552	typedef PPGMPAGE *PPPGMPAGE;
553
554
555	/**
556	* Clears the page structure.
557	* @param pPage Pointer to the physical guest page tracking structure.
558	*/
559	#define PGM_PAGE_CLEAR(pPage) \
560	do { \
561	(pPage)->HCPhys = 0; \
562	(pPage)->u2StateX = 0; \
563	(pPage)->fWrittenToX = 0; \
564	(pPage)->fSomethingElse = 0; \
565	(pPage)->idPageX = 0; \
566	(pPage)->u3Type = 0; \
567	(pPage)->u29B = 0; \
568	} while (0)
569
570	/**
571	* Initializes the page structure.
572	* @param pPage Pointer to the physical guest page tracking structure.
573	*/
574	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
575	do { \
576	(pPage)->HCPhys = (_HCPhys); \
577	(pPage)->u2StateX = (_uState); \
578	(pPage)->fWrittenToX = 0; \
579	(pPage)->fSomethingElse = 0; \
580	(pPage)->idPageX = (_idPage); \
581	/(pPage)->u3Type = (_uType); - later / \
582	PGM_PAGE_SET_TYPE(pPage, _uType); \
583	(pPage)->u29B = 0; \
584	} while (0)
585
586	/**
587	* Initializes the page structure of a ZERO page.
588	* @param pPage Pointer to the physical guest page tracking structure.
589	*/
590	#ifdef VBOX_WITH_NEW_PHYS_CODE
591	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
592	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
593	#else
594	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
595	PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
596	#endif
597	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
598	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
599	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
600
601
602	/** @name The Page state, PGMPAGE::u2StateX.
603	* @{ */
604	/** The zero page.
605	* This is a per-VM page that's never ever mapped writable. */
606	#define PGM_PAGE_STATE_ZERO 0
607	/** A allocated page.
608	* This is a per-VM page allocated from the page pool (or wherever
609	* we get MMIO2 pages from if the type is MMIO2).
610	*/
611	#define PGM_PAGE_STATE_ALLOCATED 1
612	/** A allocated page that's being monitored for writes.
613	* The shadow page table mappings are read-only. When a write occurs, the
614	* fWrittenTo member is set, the page remapped as read-write and the state
615	* moved back to allocated. */
616	#define PGM_PAGE_STATE_WRITE_MONITORED 2
617	/** The page is shared, aka. copy-on-write.
618	* This is a page that's shared with other VMs. */
619	#define PGM_PAGE_STATE_SHARED 3
620	/** @} */
621
622
623	/**
624	* Gets the page state.
625	* @returns page state (PGM_PAGE_STATE_*).
626	* @param pPage Pointer to the physical guest page tracking structure.
627	*/
628	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
629
630	/**
631	* Sets the page state.
632	* @param pPage Pointer to the physical guest page tracking structure.
633	* @param _uState The new page state.
634	*/
635	#define PGM_PAGE_SET_STATE(pPage, _uState) \
636	do { (pPage)->u2StateX = (_uState); } while (0)
637
638
639	/**
640	* Gets the host physical address of the guest page.
641	* @returns host physical address (RTHCPHYS).
642	* @param pPage Pointer to the physical guest page tracking structure.
643	*/
644	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
645
646	/**
647	* Sets the host physical address of the guest page.
648	* @param pPage Pointer to the physical guest page tracking structure.
649	* @param _HCPhys The new host physical address.
650	*/
651	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
652	do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
653	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
654
655	/**
656	* Get the Page ID.
657	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
658	* @param pPage Pointer to the physical guest page tracking structure.
659	*/
660	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
661	/* later:
662	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
663	\| ((uint32_t)(pPage)->HCPhys & 0xfff) )
664	*/
665	/**
666	* Sets the Page ID.
667	* @param pPage Pointer to the physical guest page tracking structure.
668	*/
669	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
670	/* later:
671	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
672	\| ((_idPage) & 0xfff) \
673	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
674	*/
675
676	/**
677	* Get the Chunk ID.
678	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
679	* @param pPage Pointer to the physical guest page tracking structure.
680	*/
681	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
682	/* later:
683	#if GMM_CHUNKID_SHIFT == 12
684	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
685	#elif GMM_CHUNKID_SHIFT > 12
686	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
687	#elif GMM_CHUNKID_SHIFT < 12
688	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
689	\| ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
690	#else
691	# error "GMM_CHUNKID_SHIFT isn't defined or something."
692	#endif
693	*/
694
695	/**
696	* Get the index of the page within the allocaiton chunk.
697	* @returns The page index.
698	* @param pPage Pointer to the physical guest page tracking structure.
699	*/
700	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
701	/* later:
702	#if GMM_CHUNKID_SHIFT <= 12
703	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
704	#else
705	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
706	\| ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
707	#endif
708	*/
709
710
711	/**
712	* Gets the page type.
713	* @returns The page type.
714	* @param pPage Pointer to the physical guest page tracking structure.
715	*/
716	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
717
718	/**
719	* Sets the page type.
720	* @param pPage Pointer to the physical guest page tracking structure.
721	* @param _enmType The new page type (PGMPAGETYPE).
722	*/
723	#ifdef VBOX_WITH_NEW_PHYS_CODE
724	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
725	do { (pPage)->u3Type = (_enmType); } while (0)
726	#else
727	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
728	do { \
729	(pPage)->u3Type = (_enmType); \
730	if ((_enmType) == PGMPAGETYPE_ROM) \
731	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM; \
732	else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
733	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2; \
734	else if ((_enmType) == PGMPAGETYPE_MMIO2) \
735	(pPage)->HCPhys \|= MM_RAM_FLAGS_MMIO2; \
736	} while (0)
737	#endif
738
739
740	/**
741	* Checks if the page is 'reserved'.
742	* @returns true/false.
743	* @param pPage Pointer to the physical guest page tracking structure.
744	*/
745	#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
746
747	/**
748	* Checks if the page is marked for MMIO.
749	* @returns true/false.
750	* @param pPage Pointer to the physical guest page tracking structure.
751	*/
752	#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
753
754	/**
755	* Checks if the page is backed by the ZERO page.
756	* @returns true/false.
757	* @param pPage Pointer to the physical guest page tracking structure.
758	*/
759	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
760
761	/**
762	* Checks if the page is backed by a SHARED page.
763	* @returns true/false.
764	* @param pPage Pointer to the physical guest page tracking structure.
765	*/
766	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
767
768
769	/**
770	* Marks the paget as written to (for GMM change monitoring).
771	* @param pPage Pointer to the physical guest page tracking structure.
772	*/
773	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
774
775	/**
776	* Clears the written-to indicator.
777	* @param pPage Pointer to the physical guest page tracking structure.
778	*/
779	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
780
781	/**
782	* Checks if the page was marked as written-to.
783	* @returns true/false.
784	* @param pPage Pointer to the physical guest page tracking structure.
785	*/
786	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
787
788
789	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
790	*
791	* @remarks The values are assigned in order of priority, so we can calculate
792	* the correct state for a page with different handlers installed.
793	* @{ */
794	/** No handler installed. */
795	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
796	/** Monitoring is temporarily disabled. */
797	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
798	/** Write access is monitored. */
799	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
800	/** All access is monitored. */
801	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
802	/** @} */
803
804	/**
805	* Gets the physical access handler state of a page.
806	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
807	* @param pPage Pointer to the physical guest page tracking structure.
808	*/
809	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
810
811	/**
812	* Sets the physical access handler state of a page.
813	* @param pPage Pointer to the physical guest page tracking structure.
814	* @param _uState The new state value.
815	*/
816	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
817	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
818
819	/**
820	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
821	* @returns true/false
822	* @param pPage Pointer to the physical guest page tracking structure.
823	*/
824	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
825
826	/**
827	* Checks if the page has any active physical access handlers.
828	* @returns true/false
829	* @param pPage Pointer to the physical guest page tracking structure.
830	*/
831	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
832
833
834	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
835	*
836	* @remarks The values are assigned in order of priority, so we can calculate
837	* the correct state for a page with different handlers installed.
838	* @{ */
839	/** No handler installed. */
840	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
841	/* 1 is reserved so the lineup is identical with the physical ones. */
842	/** Write access is monitored. */
843	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
844	/** All access is monitored. */
845	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
846	/** @} */
847
848	/**
849	* Gets the virtual access handler state of a page.
850	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
851	* @param pPage Pointer to the physical guest page tracking structure.
852	*/
853	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
854
855	/**
856	* Sets the virtual access handler state of a page.
857	* @param pPage Pointer to the physical guest page tracking structure.
858	* @param _uState The new state value.
859	*/
860	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
861	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
862
863	/**
864	* Checks if the page has any virtual access handlers.
865	* @returns true/false
866	* @param pPage Pointer to the physical guest page tracking structure.
867	*/
868	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
869
870	/**
871	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
872	* virtual handlers.
873	* @returns true/false
874	* @param pPage Pointer to the physical guest page tracking structure.
875	*/
876	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
877
878
879
880	/**
881	* Checks if the page has any access handlers, including temporarily disabled ones.
882	* @returns true/false
883	* @param pPage Pointer to the physical guest page tracking structure.
884	*/
885	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
886	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
887	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
888
889	/**
890	* Checks if the page has any active access handlers.
891	* @returns true/false
892	* @param pPage Pointer to the physical guest page tracking structure.
893	*/
894	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
895	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
896	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
897
898	/**
899	* Checks if the page has any active access handlers catching all accesses.
900	* @returns true/false
901	* @param pPage Pointer to the physical guest page tracking structure.
902	*/
903	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
904	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
905	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
906
907
908	/**
909	* Ram range for GC Phys to HC Phys conversion.
910	*
911	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
912	* conversions too, but we'll let MM handle that for now.
913	*
914	* This structure is used by linked lists in both GC and HC.
915	*/
916	typedef struct PGMRAMRANGE
917	{
918	/** Pointer to the next RAM range - for R3. */
919	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
920	/** Pointer to the next RAM range - for R0. */
921	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
922	/** Pointer to the next RAM range - for GC. */
923	GCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
924	#if GC_ARCH_BITS == 32
925	/** Pointer alignment. */
926	RTGCPTR GCPtrAlignment;
927	#endif
928	/** Start of the range. Page aligned. */
929	RTGCPHYS GCPhys;
930	/** Last address in the range (inclusive). Page aligned (-1). */
931	RTGCPHYS GCPhysLast;
932	/** Size of the range. (Page aligned of course). */
933	RTGCPHYS cb;
934	/** MM_RAM_* flags */
935	uint32_t fFlags;
936	#ifdef VBOX_WITH_NEW_PHYS_CODE
937	uint32_t u32Alignment; /*< alignment. /
938	#else
939	/** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
940	GCPTRTYPE(PRTHCPTR) pavHCChunkGC;
941	/** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
942	R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
943	#endif
944	/** Start of the HC mapping of the range. This is only used for MMIO2. */
945	R3PTRTYPE(void *) pvHC;
946	/** The range description. */
947	R3PTRTYPE(const char *) pszDesc;
948
949	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
950	#ifdef VBOX_WITH_NEW_PHYS_CODE
951	uint32_t au32Reserved[2];
952	#elif HC_ARCH_BITS == 32
953	uint32_t au32Reserved[1];
954	#endif
955
956	/** Array of physical guest page tracking structures. */
957	PGMPAGE aPages[1];
958	} PGMRAMRANGE;
959	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
960	typedef PGMRAMRANGE *PPGMRAMRANGE;
961
962	/** Return hc ptr corresponding to the ram range and physical offset */
963	#define PGMRAMRANGE_GETHCPTR(pRam, off) \
964	(pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
965	: (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
966
967	/**
968	* Per page tracking structure for ROM image.
969	*
970	* A ROM image may have a shadow page, in which case we may have
971	* two pages backing it. This structure contains the PGMPAGE for
972	* both while PGMRAMRANGE have a copy of the active one. It is
973	* important that these aren't out of sync in any regard other
974	* than page pool tracking data.
975	*/
976	typedef struct PGMROMPAGE
977	{
978	/** The page structure for the virgin ROM page. */
979	PGMPAGE Virgin;
980	/** The page structure for the shadow RAM page. */
981	PGMPAGE Shadow;
982	/** The current protection setting. */
983	PGMROMPROT enmProt;
984	/** Pad the structure size to a multiple of 8. */
985	uint32_t u32Padding;
986	} PGMROMPAGE;
987	/** Pointer to a ROM page tracking structure. */
988	typedef PGMROMPAGE *PPGMROMPAGE;
989
990
991	/**
992	* A registered ROM image.
993	*
994	* This is needed to keep track of ROM image since they generally
995	* intrude into a PGMRAMRANGE. It also keeps track of additional
996	* info like the two page sets (read-only virgin and read-write shadow),
997	* the current state of each page.
998	*
999	* Because access handlers cannot easily be executed in a different
1000	* context, the ROM ranges needs to be accessible and in all contexts.
1001	*/
1002	typedef struct PGMROMRANGE
1003	{
1004	/** Pointer to the next range - R3. */
1005	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1006	/** Pointer to the next range - R0. */
1007	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1008	/** Pointer to the next range - GC. */
1009	GCPTRTYPE(struct PGMROMRANGE *) pNextGC;
1010	#if GC_ARCH_BITS == 32
1011	RTGCPTR GCPtrAlignment; /*< Pointer alignment. /
1012	#endif
1013	/** Address of the range. */
1014	RTGCPHYS GCPhys;
1015	/** Address of the last byte in the range. */
1016	RTGCPHYS GCPhysLast;
1017	/** Size of the range. */
1018	RTGCPHYS cb;
1019	/** The flags (PGMPHYS_ROM_FLAG_). /
1020	uint32_t fFlags;
1021	/*< Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. /
1022	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1023	/** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1024	* This is used for strictness checks. */
1025	R3PTRTYPE(const void *) pvOriginal;
1026	/** The ROM description. */
1027	R3PTRTYPE(const char *) pszDesc;
1028	/** The per page tracking structures. */
1029	PGMROMPAGE aPages[1];
1030	} PGMROMRANGE;
1031	/** Pointer to a ROM range. */
1032	typedef PGMROMRANGE *PPGMROMRANGE;
1033
1034
1035	/**
1036	* A registered MMIO2 (= Device RAM) range.
1037	*
1038	* There are a few reason why we need to keep track of these
1039	* registrations. One of them is the deregistration & cleanup
1040	* stuff, while another is that the PGMRAMRANGE associated with
1041	* such a region may have to be removed from the ram range list.
1042	*
1043	* Overlapping with a RAM range has to be 100% or none at all. The
1044	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1045	* meditation will be raised if a partial overlap or an overlap of
1046	* ROM pages is encountered. On an overlap we will free all the
1047	* existing RAM pages and put in the ram range pages instead.
1048	*/
1049	typedef struct PGMMMIO2RANGE
1050	{
1051	/** The owner of the range. (a device) */
1052	PPDMDEVINSR3 pDevInsR3;
1053	/** Pointer to the ring-3 mapping of the allocation. */
1054	RTR3PTR pvR3;
1055	/** Pointer to the next range - R3. */
1056	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1057	/** Whether it's mapped or not. */
1058	bool fMapped;
1059	/** Whether it's overlapping or not. */
1060	bool fOverlapping;
1061	/** The PCI region number.
1062	* @remarks This ASSUMES that nobody will ever really need to have multiple
1063	* PCI devices with matching MMIO region numbers on a single device. */
1064	uint8_t iRegion;
1065	/*< Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. /
1066	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1067	/** The associated RAM range. */
1068	PGMRAMRANGE RamRange;
1069	} PGMMMIO2RANGE;
1070	/** Pointer to a MMIO2 range. */
1071	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1072
1073
1074
1075
1076	/** @todo r=bird: fix typename. */
1077	/**
1078	* PGMPhysRead/Write cache entry
1079	*/
1080	typedef struct PGMPHYSCACHE_ENTRY
1081	{
1082	/** HC pointer to physical page */
1083	R3PTRTYPE(uint8_t *) pbHC;
1084	/** GC Physical address for cache entry */
1085	RTGCPHYS GCPhys;
1086	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1087	RTGCPHYS u32Padding0; /*< alignment padding. /
1088	#endif
1089	} PGMPHYSCACHE_ENTRY;
1090
1091	/**
1092	* PGMPhysRead/Write cache to reduce REM memory access overhead
1093	*/
1094	typedef struct PGMPHYSCACHE
1095	{
1096	/** Bitmap of valid cache entries */
1097	uint64_t aEntries;
1098	/** Cache entries */
1099	PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1100	} PGMPHYSCACHE;
1101
1102
1103	/** Pointer to an allocation chunk ring-3 mapping. */
1104	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1105	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1106	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1107
1108	/**
1109	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1110	*
1111	* The primary tree (Core) uses the chunk id as key.
1112	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1113	*/
1114	typedef struct PGMCHUNKR3MAP
1115	{
1116	/** The key is the chunk id. */
1117	AVLU32NODECORE Core;
1118	/** The key is the ageing sequence number. */
1119	AVLLU32NODECORE AgeCore;
1120	/** The current age thingy. */
1121	uint32_t iAge;
1122	/** The current reference count. */
1123	uint32_t volatile cRefs;
1124	/** The current permanent reference count. */
1125	uint32_t volatile cPermRefs;
1126	/** The mapping address. */
1127	void *pv;
1128	} PGMCHUNKR3MAP;
1129
1130	/**
1131	* Allocation chunk ring-3 mapping TLB entry.
1132	*/
1133	typedef struct PGMCHUNKR3MAPTLBE
1134	{
1135	/** The chunk id. */
1136	uint32_t volatile idChunk;
1137	#if HC_ARCH_BITS == 64
1138	uint32_t u32Padding; /*< alignment padding. /
1139	#endif
1140	/** The chunk map. */
1141	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1142	} PGMCHUNKR3MAPTLBE;
1143	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1144	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1145
1146	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1147	* @remark Must be a power of two value. */
1148	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1149
1150	/**
1151	* Allocation chunk ring-3 mapping TLB.
1152	*
1153	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1154	* At first glance this might look kinda odd since AVL trees are
1155	* supposed to give the most optimial lookup times of all trees
1156	* due to their balancing. However, take a tree with 1023 nodes
1157	* in it, that's 10 levels, meaning that most searches has to go
1158	* down 9 levels before they find what they want. This isn't fast
1159	* compared to a TLB hit. There is the factor of cache misses,
1160	* and of course the problem with trees and branch prediction.
1161	* This is why we use TLBs in front of most of the trees.
1162	*
1163	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1164	* difficult when we switch to inlined AVL trees (from kStuff).
1165	*/
1166	typedef struct PGMCHUNKR3MAPTLB
1167	{
1168	/** The TLB entries. */
1169	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1170	} PGMCHUNKR3MAPTLB;
1171
1172	/**
1173	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1174	* @returns Chunk TLB index.
1175	* @param idChunk The Chunk ID.
1176	*/
1177	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1178
1179
1180	/**
1181	* Ring-3 guest page mapping TLB entry.
1182	* @remarks used in ring-0 as well at the moment.
1183	*/
1184	typedef struct PGMPAGER3MAPTLBE
1185	{
1186	/** Address of the page. */
1187	RTGCPHYS volatile GCPhys;
1188	/** The guest page. */
1189	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1190	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1191	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1192	/** The address */
1193	R3R0PTRTYPE(void *) volatile pv;
1194	#if HC_ARCH_BITS == 32
1195	uint32_t u32Padding; /*< alignment padding. /
1196	#endif
1197	} PGMPAGER3MAPTLBE;
1198	/** Pointer to an entry in the HC physical TLB. */
1199	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1200
1201
1202	/** The number of entries in the ring-3 guest page mapping TLB.
1203	* @remarks The value must be a power of two. */
1204	#define PGM_PAGER3MAPTLB_ENTRIES 64
1205
1206	/**
1207	* Ring-3 guest page mapping TLB.
1208	* @remarks used in ring-0 as well at the moment.
1209	*/
1210	typedef struct PGMPAGER3MAPTLB
1211	{
1212	/** The TLB entries. */
1213	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1214	} PGMPAGER3MAPTLB;
1215	/** Pointer to the ring-3 guest page mapping TLB. */
1216	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1217
1218	/**
1219	* Calculates the index of the TLB entry for the specified guest page.
1220	* @returns Physical TLB index.
1221	* @param GCPhys The guest physical address.
1222	*/
1223	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1224
1225
1226	/** @name Context neutrual page mapper TLB.
1227	*
1228	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1229	* code is writting in a kind of context neutrual way. Time will show whether
1230	* this actually makes sense or not...
1231	*
1232	* @{ */
1233	/** @typedef PPGMPAGEMAPTLB
1234	* The page mapper TLB pointer type for the current context. */
1235	/** @typedef PPGMPAGEMAPTLB
1236	* The page mapper TLB entry pointer type for the current context. */
1237	/** @typedef PPGMPAGEMAPTLB
1238	* The page mapper TLB entry pointer pointer type for the current context. */
1239	/** @def PGMPAGEMAPTLB_ENTRIES
1240	* The number of TLB entries in the page mapper TLB for the current context. */
1241	/** @def PGM_PAGEMAPTLB_IDX
1242	* Calculate the TLB index for a guest physical address.
1243	* @returns The TLB index.
1244	* @param GCPhys The guest physical address. */
1245	/** @typedef PPGMPAGEMAP
1246	* Pointer to a page mapper unit for current context. */
1247	/** @typedef PPPGMPAGEMAP
1248	* Pointer to a page mapper unit pointer for current context. */
1249	#ifdef IN_GC
1250	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1251	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1252	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1253	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1254	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1255	typedef void * PPGMPAGEMAP;
1256	typedef void ** PPPGMPAGEMAP;
1257	//#elif IN_RING0
1258	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1259	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1260	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1261	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1262	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1263	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1264	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1265	#else
1266	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1267	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1268	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1269	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1270	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1271	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1272	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1273	#endif
1274	/** @} */
1275
1276
1277	/** @name PGM Pool Indexes.
1278	* Aka. the unique shadow page identifier.
1279	* @{ */
1280	/** NIL page pool IDX. */
1281	#define NIL_PGMPOOL_IDX 0
1282	/** The first normal index. */
1283	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1284	/** Page directory (32-bit root). */
1285	#define PGMPOOL_IDX_PD 1
1286	/** The extended PAE page directory (2048 entries, works as root currently). */
1287	#define PGMPOOL_IDX_PAE_PD 2
1288	/** PAE Page Directory Table 0. */
1289	#define PGMPOOL_IDX_PAE_PD_0 3
1290	/** PAE Page Directory Table 1. */
1291	#define PGMPOOL_IDX_PAE_PD_1 4
1292	/** PAE Page Directory Table 2. */
1293	#define PGMPOOL_IDX_PAE_PD_2 5
1294	/** PAE Page Directory Table 3. */
1295	#define PGMPOOL_IDX_PAE_PD_3 6
1296	/** Page Directory Pointer Table (PAE root, not currently used). */
1297	#define PGMPOOL_IDX_PDPT 7
1298	/** Page Map Level-4 (64-bit root). */
1299	#define PGMPOOL_IDX_PML4 8
1300	/** The first normal index. */
1301	#define PGMPOOL_IDX_FIRST 9
1302	/** The last valid index. (inclusive, 14 bits) */
1303	#define PGMPOOL_IDX_LAST 0x3fff
1304	/** @} */
1305
1306	/** The NIL index for the parent chain. */
1307	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1308
1309	/**
1310	* Node in the chain linking a shadowed page to it's parent (user).
1311	*/
1312	#pragma pack(1)
1313	typedef struct PGMPOOLUSER
1314	{
1315	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1316	uint16_t iNext;
1317	/** The user page index. */
1318	uint16_t iUser;
1319	/** Index into the user table. */
1320	uint16_t iUserTable;
1321	} PGMPOOLUSER, *PPGMPOOLUSER;
1322	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1323	#pragma pack()
1324
1325
1326	/** The NIL index for the phys ext chain. */
1327	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1328
1329	/**
1330	* Node in the chain of physical cross reference extents.
1331	*/
1332	#pragma pack(1)
1333	typedef struct PGMPOOLPHYSEXT
1334	{
1335	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1336	uint16_t iNext;
1337	/** The user page index. */
1338	uint16_t aidx[3];
1339	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1340	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1341	#pragma pack()
1342
1343
1344	/**
1345	* The kind of page that's being shadowed.
1346	*/
1347	typedef enum PGMPOOLKIND
1348	{
1349	/** The virtual invalid 0 entry. */
1350	PGMPOOLKIND_INVALID = 0,
1351	/** The entry is free (=unused). */
1352	PGMPOOLKIND_FREE,
1353
1354	/** Shw: 32-bit page table; Gst: no paging */
1355	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1356	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1357	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1358	/** Shw: 32-bit page table; Gst: 4MB page. */
1359	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1360	/** Shw: PAE page table; Gst: no paging */
1361	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1362	/** Shw: PAE page table; Gst: 32-bit page table. */
1363	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1364	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1365	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1366	/** Shw: PAE page table; Gst: PAE page table. */
1367	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1368	/** Shw: PAE page table; Gst: 2MB page. */
1369	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1370
1371	/** Shw: PAE page directory; Gst: 32-bit page directory. */
1372	PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1373	/** Shw: PAE page directory; Gst: PAE page directory. */
1374	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1375
1376	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1377	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1378	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1379	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1380
1381	/** Shw: Root 32-bit page directory. */
1382	PGMPOOLKIND_ROOT_32BIT_PD,
1383	/** Shw: Root PAE page directory */
1384	PGMPOOLKIND_ROOT_PAE_PD,
1385	/** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1386	PGMPOOLKIND_ROOT_PDPT,
1387	/** Shw: Root page map level-4 table. */
1388	PGMPOOLKIND_ROOT_PML4,
1389
1390	/** The last valid entry. */
1391	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PML4
1392	} PGMPOOLKIND;
1393
1394
1395	/**
1396	* The tracking data for a page in the pool.
1397	*/
1398	typedef struct PGMPOOLPAGE
1399	{
1400	/** AVL node code with the (HC) physical address of this page. */
1401	AVLOHCPHYSNODECORE Core;
1402	/** Pointer to the HC mapping of the page. */
1403	R3R0PTRTYPE(void *) pvPageHC;
1404	/** The guest physical address. */
1405	RTGCPHYS GCPhys;
1406	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1407	uint8_t enmKind;
1408	uint8_t bPadding;
1409	/** The index of this page. */
1410	uint16_t idx;
1411	/** The next entry in the list this page currently resides in.
1412	* It's either in the free list or in the GCPhys hash. */
1413	uint16_t iNext;
1414	#ifdef PGMPOOL_WITH_USER_TRACKING
1415	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1416	uint16_t iUserHead;
1417	/** The number of present entries. */
1418	uint16_t cPresent;
1419	/** The first entry in the table which is present. */
1420	uint16_t iFirstPresent;
1421	#endif
1422	#ifdef PGMPOOL_WITH_MONITORING
1423	/** The number of modifications to the monitored page. */
1424	uint16_t cModifications;
1425	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1426	uint16_t iModifiedNext;
1427	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1428	uint16_t iModifiedPrev;
1429	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1430	uint16_t iMonitoredNext;
1431	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1432	uint16_t iMonitoredPrev;
1433	#endif
1434	#ifdef PGMPOOL_WITH_CACHE
1435	/** The next page in the age list. */
1436	uint16_t iAgeNext;
1437	/** The previous page in the age list. */
1438	uint16_t iAgePrev;
1439	#endif /* PGMPOOL_WITH_CACHE */
1440	/** Used to indicate that the page is zeroed. */
1441	bool fZeroed;
1442	/** Used to indicate that a PT has non-global entries. */
1443	bool fSeenNonGlobal;
1444	/** Used to indicate that we're monitoring writes to the guest page. */
1445	bool fMonitored;
1446	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1447	* (All pages are in the age list.) */
1448	bool fCached;
1449	/** This is used by the R3 access handlers when invoked by an async thread.
1450	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1451	bool volatile fReusedFlushPending;
1452	/** Used to indicate that the guest is mapping the page is also used as a CR3.
1453	* In these cases the access handler acts differently and will check
1454	* for mapping conflicts like the normal CR3 handler.
1455	* @todo When we change the CR3 shadowing to use pool pages, this flag can be
1456	* replaced by a list of pages which share access handler.
1457	*/
1458	bool fCR3Mix;
1459	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1460
1461
1462	#ifdef PGMPOOL_WITH_CACHE
1463	/** The hash table size. */
1464	# define PGMPOOL_HASH_SIZE 0x40
1465	/** The hash function. */
1466	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1467	#endif
1468
1469
1470	/**
1471	* The shadow page pool instance data.
1472	*
1473	* It's all one big allocation made at init time, except for the
1474	* pages that is. The user nodes follows immediatly after the
1475	* page structures.
1476	*/
1477	typedef struct PGMPOOL
1478	{
1479	/** The VM handle - HC Ptr. */
1480	R3R0PTRTYPE(PVM) pVMHC;
1481	/** The VM handle - GC Ptr. */
1482	GCPTRTYPE(PVM) pVMGC;
1483	/** The max pool size. This includes the special IDs. */
1484	uint16_t cMaxPages;
1485	/** The current pool size. */
1486	uint16_t cCurPages;
1487	/** The head of the free page list. */
1488	uint16_t iFreeHead;
1489	/* Padding. */
1490	uint16_t u16Padding;
1491	#ifdef PGMPOOL_WITH_USER_TRACKING
1492	/** Head of the chain of free user nodes. */
1493	uint16_t iUserFreeHead;
1494	/** The number of user nodes we've allocated. */
1495	uint16_t cMaxUsers;
1496	/** The number of present page table entries in the entire pool. */
1497	uint32_t cPresent;
1498	/** Pointer to the array of user nodes - GC pointer. */
1499	GCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1500	/** Pointer to the array of user nodes - HC pointer. */
1501	R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1502	#endif /* PGMPOOL_WITH_USER_TRACKING */
1503	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1504	/** Head of the chain of free phys ext nodes. */
1505	uint16_t iPhysExtFreeHead;
1506	/** The number of user nodes we've allocated. */
1507	uint16_t cMaxPhysExts;
1508	/** Pointer to the array of physical xref extent - GC pointer. */
1509	GCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1510	/** Pointer to the array of physical xref extent nodes - HC pointer. */
1511	R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1512	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1513	#ifdef PGMPOOL_WITH_CACHE
1514	/** Hash table for GCPhys addresses. */
1515	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1516	/** The head of the age list. */
1517	uint16_t iAgeHead;
1518	/** The tail of the age list. */
1519	uint16_t iAgeTail;
1520	/** Set if the cache is enabled. */
1521	bool fCacheEnabled;
1522	#endif /* PGMPOOL_WITH_CACHE */
1523	#ifdef PGMPOOL_WITH_MONITORING
1524	/** Head of the list of modified pages. */
1525	uint16_t iModifiedHead;
1526	/** The current number of modified pages. */
1527	uint16_t cModifiedPages;
1528	/** Access handler, GC. */
1529	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1530	/** Access handler, R0. */
1531	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1532	/** Access handler, R3. */
1533	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1534	/** The access handler description (HC ptr). */
1535	R3PTRTYPE(const char *) pszAccessHandler;
1536	#endif /* PGMPOOL_WITH_MONITORING */
1537	/** The number of pages currently in use. */
1538	uint16_t cUsedPages;
1539	#ifdef VBOX_WITH_STATISTICS
1540	/** The high wather mark for cUsedPages. */
1541	uint16_t cUsedPagesHigh;
1542	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1543	/** Profiling pgmPoolAlloc(). */
1544	STAMPROFILEADV StatAlloc;
1545	/** Profiling pgmPoolClearAll(). */
1546	STAMPROFILE StatClearAll;
1547	/** Profiling pgmPoolFlushAllInt(). */
1548	STAMPROFILE StatFlushAllInt;
1549	/** Profiling pgmPoolFlushPage(). */
1550	STAMPROFILE StatFlushPage;
1551	/** Profiling pgmPoolFree(). */
1552	STAMPROFILE StatFree;
1553	/** Profiling time spent zeroing pages. */
1554	STAMPROFILE StatZeroPage;
1555	# ifdef PGMPOOL_WITH_USER_TRACKING
1556	/** Profiling of pgmPoolTrackDeref. */
1557	STAMPROFILE StatTrackDeref;
1558	/** Profiling pgmTrackFlushGCPhysPT. */
1559	STAMPROFILE StatTrackFlushGCPhysPT;
1560	/** Profiling pgmTrackFlushGCPhysPTs. */
1561	STAMPROFILE StatTrackFlushGCPhysPTs;
1562	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1563	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1564	/** Number of times we've been out of user records. */
1565	STAMCOUNTER StatTrackFreeUpOneUser;
1566	# endif
1567	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1568	/** Profiling deref activity related tracking GC physical pages. */
1569	STAMPROFILE StatTrackDerefGCPhys;
1570	/** Number of linear searches for a HCPhys in the ram ranges. */
1571	STAMCOUNTER StatTrackLinearRamSearches;
1572	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1573	STAMCOUNTER StamTrackPhysExtAllocFailures;
1574	# endif
1575	# ifdef PGMPOOL_WITH_MONITORING
1576	/** Profiling the GC PT access handler. */
1577	STAMPROFILE StatMonitorGC;
1578	/** Times we've failed interpreting the instruction. */
1579	STAMCOUNTER StatMonitorGCEmulateInstr;
1580	/** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1581	STAMPROFILE StatMonitorGCFlushPage;
1582	/** Times we've detected fork(). */
1583	STAMCOUNTER StatMonitorGCFork;
1584	/** Profiling the GC access we've handled (except REP STOSD). */
1585	STAMPROFILE StatMonitorGCHandled;
1586	/** Times we've failed interpreting a patch code instruction. */
1587	STAMCOUNTER StatMonitorGCIntrFailPatch1;
1588	/** Times we've failed interpreting a patch code instruction during flushing. */
1589	STAMCOUNTER StatMonitorGCIntrFailPatch2;
1590	/** The number of times we've seen rep prefixes we can't handle. */
1591	STAMCOUNTER StatMonitorGCRepPrefix;
1592	/** Profiling the REP STOSD cases we've handled. */
1593	STAMPROFILE StatMonitorGCRepStosd;
1594
1595	/** Profiling the HC PT access handler. */
1596	STAMPROFILE StatMonitorHC;
1597	/** Times we've failed interpreting the instruction. */
1598	STAMCOUNTER StatMonitorHCEmulateInstr;
1599	/** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1600	STAMPROFILE StatMonitorHCFlushPage;
1601	/** Times we've detected fork(). */
1602	STAMCOUNTER StatMonitorHCFork;
1603	/** Profiling the HC access we've handled (except REP STOSD). */
1604	STAMPROFILE StatMonitorHCHandled;
1605	/** The number of times we've seen rep prefixes we can't handle. */
1606	STAMCOUNTER StatMonitorHCRepPrefix;
1607	/** Profiling the REP STOSD cases we've handled. */
1608	STAMPROFILE StatMonitorHCRepStosd;
1609	/** The number of times we're called in an async thread an need to flush. */
1610	STAMCOUNTER StatMonitorHCAsync;
1611	/** The high wather mark for cModifiedPages. */
1612	uint16_t cModifiedPagesHigh;
1613	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1614	# endif
1615	# ifdef PGMPOOL_WITH_CACHE
1616	/** The number of cache hits. */
1617	STAMCOUNTER StatCacheHits;
1618	/** The number of cache misses. */
1619	STAMCOUNTER StatCacheMisses;
1620	/** The number of times we've got a conflict of 'kind' in the cache. */
1621	STAMCOUNTER StatCacheKindMismatches;
1622	/** Number of times we've been out of pages. */
1623	STAMCOUNTER StatCacheFreeUpOne;
1624	/** The number of cacheable allocations. */
1625	STAMCOUNTER StatCacheCacheable;
1626	/** The number of uncacheable allocations. */
1627	STAMCOUNTER StatCacheUncacheable;
1628	# endif
1629	#elif HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1630	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1631	#endif
1632	/** The AVL tree for looking up a page by its HC physical address. */
1633	AVLOHCPHYSTREE HCPhysTree;
1634	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1635	/** Array of pages. (cMaxPages in length)
1636	* The Id is the index into thist array.
1637	*/
1638	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1639	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1640
1641
1642	/** @def PGMPOOL_PAGE_2_PTR
1643	* Maps a pool page pool into the current context.
1644	*
1645	* @returns VBox status code.
1646	* @param pVM The VM handle.
1647	* @param pPage The pool page.
1648	*
1649	* @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1650	* small page window employeed by that function. Be careful.
1651	* @remark There is no need to assert on the result.
1652	*/
1653	#ifdef IN_GC
1654	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1655	#else
1656	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1657	#endif
1658
1659
1660	/**
1661	* Trees are using self relative offsets as pointers.
1662	* So, all its data, including the root pointer, must be in the heap for HC and GC
1663	* to have the same layout.
1664	*/
1665	typedef struct PGMTREES
1666	{
1667	/** Physical access handlers (AVL range+offsetptr tree). */
1668	AVLROGCPHYSTREE PhysHandlers;
1669	/** Virtual access handlers (AVL range + GC ptr tree). */
1670	AVLROGCPTRTREE VirtHandlers;
1671	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1672	AVLROGCPHYSTREE PhysToVirtHandlers;
1673	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1674	AVLROGCPTRTREE HyperVirtHandlers;
1675	} PGMTREES;
1676	/** Pointer to PGM trees. */
1677	typedef PGMTREES *PPGMTREES;
1678
1679
1680	/** @name Paging mode macros
1681	* @{ */
1682	#ifdef IN_GC
1683	# define PGM_CTX(a,b) a##GC##b
1684	# define PGM_CTX_STR(a,b) a "GC" b
1685	# define PGM_CTX_DECL(type) PGMGCDECL(type)
1686	#else
1687	# ifdef IN_RING3
1688	# define PGM_CTX(a,b) a##R3##b
1689	# define PGM_CTX_STR(a,b) a "R3" b
1690	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1691	# else
1692	# define PGM_CTX(a,b) a##R0##b
1693	# define PGM_CTX_STR(a,b) a "R0" b
1694	# define PGM_CTX_DECL(type) PGMDECL(type)
1695	# endif
1696	#endif
1697
1698	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1699	#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1700	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1701	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1702	#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1703	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1704	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1705	#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1706	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1707	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1708	#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1709	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1710	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1711	#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1712	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1713	#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1714	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1715
1716	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1717	#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1718	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1719	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1720	#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1721	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1722	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1723	#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1724	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1725	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1726	#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1727
1728	/* Shw_Gst */
1729	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1730	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1731	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1732	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1733	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1734	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1735	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1736	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1737	#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1738	#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1739	#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1740	#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1741	#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1742	#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1743	#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1744	#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1745	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1746	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1747	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1748	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1749	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1750	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1751	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1752	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1753	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1754	#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1755	/** @} */
1756
1757	/**
1758	* Data for each paging mode.
1759	*/
1760	typedef struct PGMMODEDATA
1761	{
1762	/** The guest mode type. */
1763	uint32_t uGstType;
1764	/** The shadow mode type. */
1765	uint32_t uShwType;
1766
1767	/** @name Function pointers for Shadow paging.
1768	* @{
1769	*/
1770	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1771	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1772	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1773	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1774	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1775	DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1776	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1777
1778	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1779	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1780	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1781	DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1782	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1783
1784	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1785	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1786	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1787	DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1788	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1789	/** @} */
1790
1791	/** @name Function pointers for Guest paging.
1792	* @{
1793	*/
1794	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1795	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1796	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1797	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1798	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1799	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1800	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1801	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1802	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1803	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1804	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1805	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1806	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1807
1808	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1809	DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1810	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1811	DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1812	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1813	DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1814	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1815	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1816	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1817
1818	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1819	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1820	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1821	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1822	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1823	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1824	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1825	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1826	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1827	/** @} */
1828
1829	/** @name Function pointers for Both Shadow and Guest paging.
1830	* @{
1831	*/
1832	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1833	DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1834	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1835	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1836	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1837	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1838	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1839	#ifdef VBOX_STRICT
1840	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1841	#endif
1842
1843	DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1844	DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1845	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1846	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1847	DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1848	DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1849	#ifdef VBOX_STRICT
1850	DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1851	#endif
1852
1853	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1854	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1855	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1856	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1857	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1858	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1859	#ifdef VBOX_STRICT
1860	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1861	#endif
1862	/** @} */
1863	} PGMMODEDATA, *PPGMMODEDATA;
1864
1865
1866
1867	/**
1868	* Converts a PGM pointer into a VM pointer.
1869	* @returns Pointer to the VM structure the PGM is part of.
1870	* @param pPGM Pointer to PGM instance data.
1871	*/
1872	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1873
1874	/**
1875	* PGM Data (part of VM)
1876	*/
1877	typedef struct PGM
1878	{
1879	/** Offset to the VM structure. */
1880	RTINT offVM;
1881
1882	/*
1883	* This will be redefined at least two more times before we're done, I'm sure.
1884	* The current code is only to get on with the coding.
1885	* - 2004-06-10: initial version, bird.
1886	* - 2004-07-02: 1st time, bird.
1887	* - 2004-10-18: 2nd time, bird.
1888	* - 2005-07-xx: 3rd time, bird.
1889	*/
1890
1891	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1892	GCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1893	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1894	GCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1895
1896	/** The host paging mode. (This is what SUPLib reports.) */
1897	SUPPAGINGMODE enmHostMode;
1898	/** The shadow paging mode. */
1899	PGMMODE enmShadowMode;
1900	/** The guest paging mode. */
1901	PGMMODE enmGuestMode;
1902
1903	/** The current physical address representing in the guest CR3 register. */
1904	RTGCPHYS GCPhysCR3;
1905	/** Pointer to the 5 page CR3 content mapping.
1906	* The first page is always the CR3 (in some form) while the 4 other pages
1907	* are used of the PDs in PAE mode. */
1908	RTGCPTR GCPtrCR3Mapping;
1909	#if HC_ARCH_BITS == 64
1910	uint32_t u32Alignment;
1911	#endif
1912	/** The physical address of the currently monitored guest CR3 page.
1913	* When this value is NIL_RTGCPHYS no page is being monitored. */
1914	RTGCPHYS GCPhysGstCR3Monitored;
1915
1916	/** @name 32-bit Guest Paging.
1917	* @{ */
1918	/** The guest's page directory, HC pointer. */
1919	R3R0PTRTYPE(PX86PD) pGuestPDHC;
1920	/** The guest's page directory, static GC mapping. */
1921	GCPTRTYPE(PX86PD) pGuestPDGC;
1922	/** @} */
1923
1924	/** @name PAE Guest Paging.
1925	* @{ */
1926	/** The guest's page directory pointer table, static GC mapping. */
1927	GCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
1928	/** The guest's page directory pointer table, HC pointer. */
1929	R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1930	/** The guest's page directories, HC pointers.
1931	* These are individual pointers and don't have to be adjecent.
1932	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1933	R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1934	/** The guest's page directories, static GC mapping.
1935	* Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1936	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1937	GCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1938	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1939	RTGCPHYS aGCPhysGstPaePDs[4];
1940	/** The physical addresses of the monitored guest page directories (PAE). */
1941	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1942	/** @} */
1943
1944	/** @name AMD64 Guest Paging.
1945	* @{ */
1946	/** The guest's page directory pointer table, HC pointer. */
1947	R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
1948	/** @} */
1949
1950	/** @name 32-bit Shadow Paging
1951	* @{ */
1952	/** The 32-Bit PD - HC Ptr. */
1953	R3R0PTRTYPE(PX86PD) pHC32BitPD;
1954	/** The 32-Bit PD - GC Ptr. */
1955	GCPTRTYPE(PX86PD) pGC32BitPD;
1956	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1957	uint32_t u32Padding1; /*< alignment padding. /
1958	#endif
1959	/** The Physical Address (HC) of the 32-Bit PD. */
1960	RTHCPHYS HCPhys32BitPD;
1961	/** @} */
1962
1963	/** @name PAE Shadow Paging
1964	* @{ */
1965	/** The four PDs for the low 4GB - HC Ptr.
1966	* Even though these are 4 pointers, what they point at is a single table.
1967	* Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
1968	R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
1969	/** The four PDs for the low 4GB - GC Ptr.
1970	* Same kind of mapping as apHCPaePDs. */
1971	GCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
1972	/** The Physical Address (HC) of the four PDs for the low 4GB.
1973	* These are NOT 4 contiguous pages. */
1974	RTHCPHYS aHCPhysPaePDs[4];
1975	/** The PAE PDP - HC Ptr. */
1976	R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
1977	/** The Physical Address (HC) of the PAE PDPT. */
1978	RTHCPHYS HCPhysPaePDPT;
1979	/** The PAE PDPT - GC Ptr. */
1980	GCPTRTYPE(PX86PDPT) pGCPaePDPT;
1981	/** @} */
1982
1983	/** @name AMD64 Shadow Paging
1984	* Extends PAE Paging.
1985	* @{ */
1986	#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1987	RTGCPTR alignment5; /*< structure size alignment. /
1988	#endif
1989	/** The Page Map Level 4 table - HC Ptr. */
1990	R3R0PTRTYPE(PX86PML4) pHCPaePML4;
1991	/** The Physical Address (HC) of the Page Map Level 4 table. */
1992	RTHCPHYS HCPhysPaePML4;
1993	/** @}*/
1994
1995	/** @name Function pointers for Shadow paging.
1996	* @{
1997	*/
1998	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1999	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2000	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2001	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2002	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
2003	DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
2004	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
2005
2006	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2007	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2008	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
2009	DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
2010	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
2011	#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2012	RTGCPTR alignment0; /*< structure size alignment. /
2013	#endif
2014
2015	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2016	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2017	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
2018	DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
2019	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
2020
2021	/** @} */
2022
2023	/** @name Function pointers for Guest paging.
2024	* @{
2025	*/
2026	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2027	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2028	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2029	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2030	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2031	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2032	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2033	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2034	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2035	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2036	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2037	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2038	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2039
2040	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2041	DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2042	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2043	DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2044	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
2045	DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2046	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
2047	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
2048	GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
2049	#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2050	RTGCPTR alignment3; /*< structure size alignment. /
2051	#endif
2052
2053	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2054	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2055	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2056	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2057	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2058	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2059	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2060	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2061	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2062	/** @} */
2063
2064	/** @name Function pointers for Both Shadow and Guest paging.
2065	* @{
2066	*/
2067	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2068	DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2069	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2070	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2071	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2072	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2073	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2074	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2075
2076	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2077	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2078	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2079	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2080	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2081	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2082	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2083
2084	DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2085	DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2086	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2087	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2088	DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2089	DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2090	DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2091	#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2092	RTGCPTR alignment2; /*< structure size alignment. /
2093	#endif
2094	/** @} */
2095
2096	/** Pointer to SHW+GST mode data (function pointers).
2097	* The index into this table is made up from */
2098	R3PTRTYPE(PPGMMODEDATA) paModeData;
2099
2100	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2101	* This is sorted by physical address and contains no overlapping ranges. */
2102	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2103	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2104	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2105	/** GC pointer corresponding to PGM::pRamRangesR3. */
2106	GCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
2107	/** The configured RAM size. */
2108	RTUINT cbRamSize;
2109
2110	/** Pointer to the list of ROM ranges - for R3.
2111	* This is sorted by physical address and contains no overlapping ranges. */
2112	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2113	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2114	R0PTRTYPE(PPGMRAMRANGE) pRomRangesR0;
2115	/** GC pointer corresponding to PGM::pRomRangesR3. */
2116	GCPTRTYPE(PPGMRAMRANGE) pRomRangesGC;
2117	/** Alignment padding. */
2118	RTGCPTR GCPtrPadding2;
2119
2120	/** Pointer to the list of MMIO2 ranges - for R3.
2121	* Registration order. */
2122	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2123
2124	/** PGM offset based trees - HC Ptr. */
2125	R3R0PTRTYPE(PPGMTREES) pTreesHC;
2126	/** PGM offset based trees - GC Ptr. */
2127	GCPTRTYPE(PPGMTREES) pTreesGC;
2128
2129	/** Linked list of GC mappings - for GC.
2130	* The list is sorted ascending on address.
2131	*/
2132	GCPTRTYPE(PPGMMAPPING) pMappingsGC;
2133	/** Linked list of GC mappings - for HC.
2134	* The list is sorted ascending on address.
2135	*/
2136	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2137	/** Linked list of GC mappings - for R0.
2138	* The list is sorted ascending on address.
2139	*/
2140	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2141
2142	/** If set no conflict checks are required. (boolean) */
2143	bool fMappingsFixed;
2144	/** If set, then no mappings are put into the shadow page table. (boolean) */
2145	bool fDisableMappings;
2146	/** Size of fixed mapping */
2147	uint32_t cbMappingFixed;
2148	/** Base address (GC) of fixed mapping */
2149	RTGCPTR GCPtrMappingFixed;
2150	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2151	uint32_t u32Padding0; /*< alignment padding. /
2152	#endif
2153
2154
2155	/** @name Intermediate Context
2156	* @{ */
2157	/** Pointer to the intermediate page directory - Normal. */
2158	R3PTRTYPE(PX86PD) pInterPD;
2159	/** Pointer to the intermedate page tables - Normal.
2160	* There are two page tables, one for the identity mapping and one for
2161	* the host context mapping (of the core code). */
2162	R3PTRTYPE(PX86PT) apInterPTs[2];
2163	/** Pointer to the intermedate page tables - PAE. */
2164	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2165	/** Pointer to the intermedate page directory - PAE. */
2166	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2167	/** Pointer to the intermedate page directory - PAE. */
2168	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2169	/** Pointer to the intermedate page-map level 4 - AMD64. */
2170	R3PTRTYPE(PX86PML4) pInterPaePML4;
2171	/** Pointer to the intermedate page directory - AMD64. */
2172	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2173	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2174	RTHCPHYS HCPhysInterPD;
2175	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2176	RTHCPHYS HCPhysInterPaePDPT;
2177	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2178	RTHCPHYS HCPhysInterPaePML4;
2179	/** @} */
2180
2181	/** Base address of the dynamic page mapping area.
2182	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2183	*/
2184	GCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2185	/** The index of the last entry used in the dynamic page mapping area. */
2186	RTUINT iDynPageMapLast;
2187	/** Cache containing the last entries in the dynamic page mapping area.
2188	* The cache size is covering half of the mapping area. */
2189	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2190
2191	/** A20 gate mask.
2192	* Our current approach to A20 emulation is to let REM do it and don't bother
2193	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2194	* But whould need arrise, we'll subject physical addresses to this mask. */
2195	RTGCPHYS GCPhysA20Mask;
2196	/** A20 gate state - boolean! */
2197	RTUINT fA20Enabled;
2198
2199	/** What needs syncing (PGM_SYNC_*).
2200	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2201	* PGMFlushTLB, and PGMR3Load. */
2202	RTUINT fSyncFlags;
2203
2204	/** PGM critical section.
2205	* This protects the physical & virtual access handlers, ram ranges,
2206	* and the page flag updating (some of it anyway).
2207	*/
2208	PDMCRITSECT CritSect;
2209
2210	/** Shadow Page Pool - HC Ptr. */
2211	R3R0PTRTYPE(PPGMPOOL) pPoolHC;
2212	/** Shadow Page Pool - GC Ptr. */
2213	GCPTRTYPE(PPGMPOOL) pPoolGC;
2214
2215	/** We're not in a state which permits writes to guest memory.
2216	* (Only used in strict builds.) */
2217	bool fNoMorePhysWrites;
2218
2219	/** Flush the cache on the next access. */
2220	bool fPhysCacheFlushPending;
2221	/** @todo r=bird: Fix member names!*/
2222	/** PGMPhysRead cache */
2223	PGMPHYSCACHE pgmphysreadcache;
2224	/** PGMPhysWrite cache */
2225	PGMPHYSCACHE pgmphyswritecache;
2226
2227	/**
2228	* Data associated with managing the ring-3 mappings of the allocation chunks.
2229	*/
2230	struct
2231	{
2232	/** The chunk tree, ordered by chunk id. */
2233	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2234	/** The chunk mapping TLB. */
2235	PGMCHUNKR3MAPTLB Tlb;
2236	/** The number of mapped chunks. */
2237	uint32_t c;
2238	/** The maximum number of mapped chunks.
2239	* @cfgm PGM/MaxRing3Chunks */
2240	uint32_t cMax;
2241	/** The chunk age tree, ordered by ageing sequence number. */
2242	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2243	/** The current time. */
2244	uint32_t iNow;
2245	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2246	uint32_t AgeingCountdown;
2247	} ChunkR3Map;
2248
2249	/**
2250	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2251	*/
2252	PGMPAGER3MAPTLB PhysTlbHC;
2253
2254	/** @name The zero page.
2255	* @{ */
2256	/** The host physical address of the zero page. */
2257	RTHCPHYS HCPhysZeroPg;
2258	/** The ring-3 mapping of the zero page. */
2259	RTR3PTR pvZeroPgR3;
2260	/** The ring-0 mapping of the zero page. */
2261	RTR0PTR pvZeroPgR0;
2262	/** The GC mapping of the zero page. */
2263	RTGCPTR pvZeroPgGC;
2264	#if GC_ARCH_BITS != 32
2265	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2266	#endif
2267	/** @}*/
2268
2269	/** The number of handy pages. */
2270	uint32_t cHandyPages;
2271	/**
2272	* Array of handy pages.
2273	*
2274	* This array is used in a two way communication between pgmPhysAllocPage
2275	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2276	* an intermediary.
2277	*
2278	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2279	* (The current size of 32 pages, means 128 KB of handy memory.)
2280	*/
2281	GMMPAGEDESC aHandyPages[32];
2282
2283	/** @name Release Statistics
2284	* @{ */
2285	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2286	uint32_t cPrivatePages; /*< The number of private pages. /
2287	uint32_t cSharedPages; /*< The number of shared pages. /
2288	uint32_t cZeroPages; /*< The number of zero backed pages. /
2289	/** The number of times the guest has switched mode since last reset or statistics reset. */
2290	STAMCOUNTER cGuestModeChanges;
2291	/** @} */
2292
2293	#ifdef VBOX_WITH_STATISTICS
2294	/** GC: Which statistic this \#PF should be attributed to. */
2295	GCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
2296	RTGCPTR padding0;
2297	/** HC: Which statistic this \#PF should be attributed to. */
2298	R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
2299	RTHCPTR padding1;
2300	STAMPROFILE StatGCTrap0e; /*< GC: PGMGCTrap0eHandler() profiling. /
2301	STAMPROFILE StatTrap0eCSAM; /*< Profiling of the Trap0eHandler body when the cause is CSAM. /
2302	STAMPROFILE StatTrap0eDirtyAndAccessedBits; /*< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2303	STAMPROFILE StatTrap0eGuestTrap; /*< Profiling of the Trap0eHandler body when the cause is a guest trap. /
2304	STAMPROFILE StatTrap0eHndPhys; /*< Profiling of the Trap0eHandler body when the cause is a physical handler. /
2305	STAMPROFILE StatTrap0eHndVirt; /*< Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2306	STAMPROFILE StatTrap0eHndUnhandled; /*< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2307	STAMPROFILE StatTrap0eMisc; /*< Profiling of the Trap0eHandler body when the cause is not known. /
2308	STAMPROFILE StatTrap0eOutOfSync; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2309	STAMPROFILE StatTrap0eOutOfSyncHndPhys; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2310	STAMPROFILE StatTrap0eOutOfSyncHndVirt; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2311	STAMPROFILE StatTrap0eOutOfSyncObsHnd; /*< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2312	STAMPROFILE StatTrap0eSyncPT; /*< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2313
2314	STAMCOUNTER StatTrap0eMapHandler; /*< Number of traps due to access handlers in mappings. /
2315	STAMCOUNTER StatGCTrap0eConflicts; /*< GC: The number of times \#PF was caused by an undetected conflict. /
2316
2317	STAMCOUNTER StatGCTrap0eUSNotPresentRead;
2318	STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
2319	STAMCOUNTER StatGCTrap0eUSWrite;
2320	STAMCOUNTER StatGCTrap0eUSReserved;
2321	STAMCOUNTER StatGCTrap0eUSNXE;
2322	STAMCOUNTER StatGCTrap0eUSRead;
2323
2324	STAMCOUNTER StatGCTrap0eSVNotPresentRead;
2325	STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
2326	STAMCOUNTER StatGCTrap0eSVWrite;
2327	STAMCOUNTER StatGCTrap0eSVReserved;
2328	STAMCOUNTER StatGCTrap0eSNXE;
2329
2330	STAMCOUNTER StatTrap0eWPEmulGC;
2331	STAMCOUNTER StatTrap0eWPEmulR3;
2332
2333	STAMCOUNTER StatGCTrap0eUnhandled;
2334	STAMCOUNTER StatGCTrap0eMap;
2335
2336	/** GC: PGMSyncPT() profiling. */
2337	STAMPROFILE StatGCSyncPT;
2338	/** GC: The number of times PGMSyncPT() needed to allocate page tables. */
2339	STAMCOUNTER StatGCSyncPTAlloc;
2340	/** GC: The number of times PGMSyncPT() detected conflicts. */
2341	STAMCOUNTER StatGCSyncPTConflict;
2342	/** GC: The number of times PGMSyncPT() failed. */
2343	STAMCOUNTER StatGCSyncPTFailed;
2344	/** GC: PGMGCInvalidatePage() profiling. */
2345	STAMPROFILE StatGCInvalidatePage;
2346	/** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
2347	STAMCOUNTER StatGCInvalidatePage4KBPages;
2348	/** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
2349	STAMCOUNTER StatGCInvalidatePage4MBPages;
2350	/** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
2351	STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
2352	/** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
2353	STAMCOUNTER StatGCInvalidatePagePDNAs;
2354	/** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
2355	STAMCOUNTER StatGCInvalidatePagePDNPs;
2356	/** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
2357	STAMCOUNTER StatGCInvalidatePagePDMappings;
2358	/** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2359	STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
2360	/** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2361	STAMCOUNTER StatGCInvalidatePageSkipped;
2362	/** GC: The number of times user page is out of sync was detected in GC. */
2363	STAMCOUNTER StatGCPageOutOfSyncUser;
2364	/** GC: The number of times supervisor page is out of sync was detected in GC. */
2365	STAMCOUNTER StatGCPageOutOfSyncSupervisor;
2366	/** GC: The number of dynamic page mapping cache hits */
2367	STAMCOUNTER StatDynMapCacheMisses;
2368	/** GC: The number of dynamic page mapping cache misses */
2369	STAMCOUNTER StatDynMapCacheHits;
2370	/** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
2371	STAMCOUNTER StatGCGuestCR3WriteHandled;
2372	/** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
2373	STAMCOUNTER StatGCGuestCR3WriteUnhandled;
2374	/** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
2375	STAMCOUNTER StatGCGuestCR3WriteConflict;
2376	/** GC: Number of out-of-sync handled pages. */
2377	STAMCOUNTER StatHandlersOutOfSync;
2378	/** GC: Number of traps due to physical access handlers. */
2379	STAMCOUNTER StatHandlersPhysical;
2380	/** GC: Number of traps due to virtual access handlers. */
2381	STAMCOUNTER StatHandlersVirtual;
2382	/** GC: Number of traps due to virtual access handlers found by physical address. */
2383	STAMCOUNTER StatHandlersVirtualByPhys;
2384	/** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2385	STAMCOUNTER StatHandlersVirtualUnmarked;
2386	/** GC: Number of traps due to access outside range of monitored page(s). */
2387	STAMCOUNTER StatHandlersUnhandled;
2388	/** GC: Number of traps due to access to invalid physical memory. */
2389	STAMCOUNTER StatHandlersInvalid;
2390
2391	/** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
2392	STAMCOUNTER StatGCGuestROMWriteHandled;
2393	/** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
2394	STAMCOUNTER StatGCGuestROMWriteUnhandled;
2395
2396	/** HC: PGMR3InvalidatePage() profiling. */
2397	STAMPROFILE StatHCInvalidatePage;
2398	/** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
2399	STAMCOUNTER StatHCInvalidatePage4KBPages;
2400	/** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
2401	STAMCOUNTER StatHCInvalidatePage4MBPages;
2402	/** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
2403	STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
2404	/** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
2405	STAMCOUNTER StatHCInvalidatePagePDNAs;
2406	/** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
2407	STAMCOUNTER StatHCInvalidatePagePDNPs;
2408	/** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
2409	STAMCOUNTER StatHCInvalidatePagePDMappings;
2410	/** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2411	STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
2412	/** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2413	STAMCOUNTER StatHCInvalidatePageSkipped;
2414	/** HC: PGMR3SyncPT() profiling. */
2415	STAMPROFILE StatHCSyncPT;
2416	/** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2417	STAMPROFILE StatHCResolveConflict;
2418	/** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2419	STAMCOUNTER StatHCDetectedConflicts;
2420	/** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2421	STAMCOUNTER StatHCGuestPDWrite;
2422	/** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2423	STAMCOUNTER StatHCGuestPDWriteConflict;
2424
2425	/** HC: The number of pages marked not present for accessed bit emulation. */
2426	STAMCOUNTER StatHCAccessedPage;
2427	/** HC: The number of pages marked read-only for dirty bit tracking. */
2428	STAMCOUNTER StatHCDirtyPage;
2429	/** HC: The number of pages marked read-only for dirty bit tracking. */
2430	STAMCOUNTER StatHCDirtyPageBig;
2431	/** HC: The number of traps generated for dirty bit tracking. */
2432	STAMCOUNTER StatHCDirtyPageTrap;
2433	/** HC: The number of pages already dirty or readonly. */
2434	STAMCOUNTER StatHCDirtyPageSkipped;
2435
2436	/** GC: The number of pages marked not present for accessed bit emulation. */
2437	STAMCOUNTER StatGCAccessedPage;
2438	/** GC: The number of pages marked read-only for dirty bit tracking. */
2439	STAMCOUNTER StatGCDirtyPage;
2440	/** GC: The number of pages marked read-only for dirty bit tracking. */
2441	STAMCOUNTER StatGCDirtyPageBig;
2442	/** GC: The number of traps generated for dirty bit tracking. */
2443	STAMCOUNTER StatGCDirtyPageTrap;
2444	/** GC: The number of pages already dirty or readonly. */
2445	STAMCOUNTER StatGCDirtyPageSkipped;
2446	/** GC: The number of pages marked dirty because of write accesses. */
2447	STAMCOUNTER StatGCDirtiedPage;
2448	/** GC: The number of pages already marked dirty because of write accesses. */
2449	STAMCOUNTER StatGCPageAlreadyDirty;
2450	/** GC: The number of real pages faults during dirty bit tracking. */
2451	STAMCOUNTER StatGCDirtyTrackRealPF;
2452
2453	/** GC: Profiling of the PGMTrackDirtyBit() body */
2454	STAMPROFILE StatGCDirtyBitTracking;
2455	/** HC: Profiling of the PGMTrackDirtyBit() body */
2456	STAMPROFILE StatHCDirtyBitTracking;
2457
2458	/** GC: Profiling of the PGMGstModifyPage() body */
2459	STAMPROFILE StatGCGstModifyPage;
2460	/** HC: Profiling of the PGMGstModifyPage() body */
2461	STAMPROFILE StatHCGstModifyPage;
2462
2463	/** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2464	STAMCOUNTER StatGCSyncPagePDNAs;
2465	/** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2466	STAMCOUNTER StatGCSyncPagePDOutOfSync;
2467	/** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2468	STAMCOUNTER StatHCSyncPagePDNAs;
2469	/** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2470	STAMCOUNTER StatHCSyncPagePDOutOfSync;
2471
2472	STAMCOUNTER StatSynPT4kGC;
2473	STAMCOUNTER StatSynPT4kHC;
2474	STAMCOUNTER StatSynPT4MGC;
2475	STAMCOUNTER StatSynPT4MHC;
2476
2477	/** Profiling of the PGMFlushTLB() body. */
2478	STAMPROFILE StatFlushTLB;
2479	/** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2480	STAMCOUNTER StatFlushTLBNewCR3;
2481	/** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2482	STAMCOUNTER StatFlushTLBNewCR3Global;
2483	/** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2484	STAMCOUNTER StatFlushTLBSameCR3;
2485	/** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2486	STAMCOUNTER StatFlushTLBSameCR3Global;
2487
2488	STAMPROFILE StatGCSyncCR3; /*< GC: PGMSyncCR3() profiling. /
2489	STAMPROFILE StatGCSyncCR3Handlers; /*< GC: Profiling of the PGMSyncCR3() update handler section. /
2490	STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /*< GC: Profiling of the virtual handler resets. /
2491	STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /*< GC: Profiling of the virtual handler updates. /
2492	STAMCOUNTER StatGCSyncCR3Global; /*< GC: The number of global CR3 syncs. /
2493	STAMCOUNTER StatGCSyncCR3NotGlobal; /*< GC: The number of non-global CR3 syncs. /
2494	STAMCOUNTER StatGCSyncCR3DstFreed; /*< GC: The number of times we've had to free a shadow entry. /
2495	STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /*< GC: The number of times we've had to free a shadow entry for which the source entry was not present. /
2496	STAMCOUNTER StatGCSyncCR3DstNotPresent; /*< GC: The number of times we've encountered a not present shadow entry for a present guest entry. /
2497	STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /*< GC: The number of times a global page directory wasn't flushed. /
2498	STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /*< GC: The number of times a page table with only global entries wasn't flushed. /
2499	STAMCOUNTER StatGCSyncCR3DstCacheHit; /*< GC: The number of times we got some kind of cache hit on a page table. /
2500
2501	STAMPROFILE StatHCSyncCR3; /*< HC: PGMSyncCR3() profiling. /
2502	STAMPROFILE StatHCSyncCR3Handlers; /*< HC: Profiling of the PGMSyncCR3() update handler section. /
2503	STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /*< HC: Profiling of the virtual handler resets. /
2504	STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /*< HC: Profiling of the virtual handler updates. /
2505	STAMCOUNTER StatHCSyncCR3Global; /*< HC: The number of global CR3 syncs. /
2506	STAMCOUNTER StatHCSyncCR3NotGlobal; /*< HC: The number of non-global CR3 syncs. /
2507	STAMCOUNTER StatHCSyncCR3DstFreed; /*< HC: The number of times we've had to free a shadow entry. /
2508	STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /*< HC: The number of times we've had to free a shadow entry for which the source entry was not present. /
2509	STAMCOUNTER StatHCSyncCR3DstNotPresent; /*< HC: The number of times we've encountered a not present shadow entry for a present guest entry. /
2510	STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /*< HC: The number of times a global page directory wasn't flushed. /
2511	STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /*< HC: The number of times a page table with only global entries wasn't flushed. /
2512	STAMCOUNTER StatHCSyncCR3DstCacheHit; /*< HC: The number of times we got some kind of cache hit on a page table. /
2513
2514	/** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2515	STAMPROFILE StatVirtHandleSearchByPhysGC;
2516	/** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2517	STAMPROFILE StatVirtHandleSearchByPhysHC;
2518	/** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2519	STAMCOUNTER StatHandlePhysicalReset;
2520
2521	STAMPROFILE StatCheckPageFault;
2522	STAMPROFILE StatLazySyncPT;
2523	STAMPROFILE StatMapping;
2524	STAMPROFILE StatOutOfSync;
2525	STAMPROFILE StatHandlers;
2526	STAMPROFILE StatEIPHandlers;
2527	STAMPROFILE StatHCPrefetch;
2528
2529	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2530	/** The number of first time shadowings. */
2531	STAMCOUNTER StatTrackVirgin;
2532	/** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2533	STAMCOUNTER StatTrackAliased;
2534	/** The number of times we're tracking using cRef2. */
2535	STAMCOUNTER StatTrackAliasedMany;
2536	/** The number of times we're hitting pages which has overflowed cRef2. */
2537	STAMCOUNTER StatTrackAliasedLots;
2538	/** The number of times the extent list grows to long. */
2539	STAMCOUNTER StatTrackOverflows;
2540	/** Profiling of SyncPageWorkerTrackDeref (expensive). */
2541	STAMPROFILE StatTrackDeref;
2542	# endif
2543
2544	/** Ring-3/0 page mapper TLB hits. */
2545	STAMCOUNTER StatPageHCMapTlbHits;
2546	/** Ring-3/0 page mapper TLB misses. */
2547	STAMCOUNTER StatPageHCMapTlbMisses;
2548	/** Ring-3/0 chunk mapper TLB hits. */
2549	STAMCOUNTER StatChunkR3MapTlbHits;
2550	/** Ring-3/0 chunk mapper TLB misses. */
2551	STAMCOUNTER StatChunkR3MapTlbMisses;
2552	/** Times a shared page has been replaced by a private one. */
2553	STAMCOUNTER StatPageReplaceShared;
2554	/** Times the zero page has been replaced by a private one. */
2555	STAMCOUNTER StatPageReplaceZero;
2556	/** The number of times we've executed GMMR3AllocateHandyPages. */
2557	STAMCOUNTER StatPageHandyAllocs;
2558
2559	/** Allocated mbs of guest ram */
2560	STAMCOUNTER StatDynRamTotal;
2561	/** Nr of pgmr3PhysGrowRange calls. */
2562	STAMCOUNTER StatDynRamGrow;
2563
2564	STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2565	STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2566	STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2567	#endif
2568	} PGM, *PPGM;
2569
2570
2571	/** @name PGM::fSyncFlags Flags
2572	* @{
2573	*/
2574	/** Updates the virtual access handler state bit in PGMPAGE. */
2575	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2576	/** Always sync CR3. */
2577	#define PGM_SYNC_ALWAYS RT_BIT(1)
2578	/** Check monitoring on next CR3 (re)load and invalidate page. */
2579	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2580	/** Clear the page pool (a light weight flush). */
2581	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2582	/** @} */
2583
2584
2585	__BEGIN_DECLS
2586
2587	int pgmLock(PVM pVM);
2588	void pgmUnlock(PVM pVM);
2589
2590	PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2591	PGMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2592	int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
2593
2594	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2595	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2596	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2597	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2598	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2599
2600	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2601	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2602	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2603	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
2604	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2605	#else
2606	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2607	#endif
2608	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2609
2610
2611	void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2612	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2613	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2614	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2615	#ifdef IN_RING3
2616	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2617	int pgmR3PhysRamReset(PVM pVM);
2618	int pgmR3PhysRomReset(PVM pVM);
2619	#ifndef VBOX_WITH_NEW_PHYS_CODE
2620	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2621	#endif
2622
2623	int pgmR3PoolInit(PVM pVM);
2624	void pgmR3PoolRelocate(PVM pVM);
2625	void pgmR3PoolReset(PVM pVM);
2626
2627	#endif /* IN_RING3 */
2628	#ifdef IN_GC
2629	void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2630	#endif
2631	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage);
2632	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2633	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint16_t iUserTable);
2634	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable);
2635	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2636	void pgmPoolFlushAll(PVM pVM);
2637	void pgmPoolClearAll(PVM pVM);
2638	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2639	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2640	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2641	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2642	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2643	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2644	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2645	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2646	#ifdef PGMPOOL_WITH_MONITORING
2647	# ifdef IN_RING3
2648	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2649	# else
2650	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2651	# endif
2652	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2653	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2654	void pgmPoolMonitorModifiedClearAll(PVM pVM);
2655	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2656	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2657	#endif
2658
2659	__END_DECLS
2660
2661
2662	/**
2663	* Gets the PGMRAMRANGE structure for a guest page.
2664	*
2665	* @returns Pointer to the RAM range on success.
2666	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2667	*
2668	* @param pPGM PGM handle.
2669	* @param GCPhys The GC physical address.
2670	*/
2671	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2672	{
2673	/*
2674	* Optimize for the first range.
2675	*/
2676	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2677	RTGCPHYS off = GCPhys - pRam->GCPhys;
2678	if (RT_UNLIKELY(off >= pRam->cb))
2679	{
2680	do
2681	{
2682	pRam = CTXALLSUFF(pRam->pNext);
2683	if (RT_UNLIKELY(!pRam))
2684	break;
2685	off = GCPhys - pRam->GCPhys;
2686	} while (off >= pRam->cb);
2687	}
2688	return pRam;
2689	}
2690
2691
2692	/**
2693	* Gets the PGMPAGE structure for a guest page.
2694	*
2695	* @returns Pointer to the page on success.
2696	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2697	*
2698	* @param pPGM PGM handle.
2699	* @param GCPhys The GC physical address.
2700	*/
2701	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2702	{
2703	/*
2704	* Optimize for the first range.
2705	*/
2706	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2707	RTGCPHYS off = GCPhys - pRam->GCPhys;
2708	if (RT_UNLIKELY(off >= pRam->cb))
2709	{
2710	do
2711	{
2712	pRam = CTXALLSUFF(pRam->pNext);
2713	if (RT_UNLIKELY(!pRam))
2714	return NULL;
2715	off = GCPhys - pRam->GCPhys;
2716	} while (off >= pRam->cb);
2717	}
2718	return &pRam->aPages[off >> PAGE_SHIFT];
2719	}
2720
2721
2722	/**
2723	* Gets the PGMPAGE structure for a guest page.
2724	*
2725	* Old Phys code: Will make sure the page is present.
2726	*
2727	* @returns VBox status code.
2728	* @retval VINF_SUCCESS and a valid *ppPage on success.
2729	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2730	*
2731	* @param pPGM PGM handle.
2732	* @param GCPhys The GC physical address.
2733	* @param ppPage Where to store the page poitner on success.
2734	*/
2735	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2736	{
2737	/*
2738	* Optimize for the first range.
2739	*/
2740	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2741	RTGCPHYS off = GCPhys - pRam->GCPhys;
2742	if (RT_UNLIKELY(off >= pRam->cb))
2743	{
2744	do
2745	{
2746	pRam = CTXALLSUFF(pRam->pNext);
2747	if (RT_UNLIKELY(!pRam))
2748	{
2749	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
2750	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2751	}
2752	off = GCPhys - pRam->GCPhys;
2753	} while (off >= pRam->cb);
2754	}
2755	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2756	#ifndef VBOX_WITH_NEW_PHYS_CODE
2757
2758	/*
2759	* Make sure it's present.
2760	*/
2761	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2762	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2763	{
2764	#ifdef IN_RING3
2765	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2766	#else
2767	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2768	#endif
2769	if (VBOX_FAILURE(rc))
2770	{
2771	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
2772	return rc;
2773	}
2774	Assert(rc == VINF_SUCCESS);
2775	}
2776	#endif
2777	return VINF_SUCCESS;
2778	}
2779
2780
2781
2782
2783	/**
2784	* Gets the PGMPAGE structure for a guest page.
2785	*
2786	* Old Phys code: Will make sure the page is present.
2787	*
2788	* @returns VBox status code.
2789	* @retval VINF_SUCCESS and a valid *ppPage on success.
2790	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2791	*
2792	* @param pPGM PGM handle.
2793	* @param GCPhys The GC physical address.
2794	* @param ppPage Where to store the page poitner on success.
2795	* @param ppRamHint Where to read and store the ram list hint.
2796	* The caller initializes this to NULL before the call.
2797	*/
2798	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2799	{
2800	RTGCPHYS off;
2801	PPGMRAMRANGE pRam = *ppRamHint;
2802	if ( !pRam
2803	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2804	{
2805	pRam = CTXALLSUFF(pPGM->pRamRanges);
2806	off = GCPhys - pRam->GCPhys;
2807	if (RT_UNLIKELY(off >= pRam->cb))
2808	{
2809	do
2810	{
2811	pRam = CTXALLSUFF(pRam->pNext);
2812	if (RT_UNLIKELY(!pRam))
2813	{
2814	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
2815	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2816	}
2817	off = GCPhys - pRam->GCPhys;
2818	} while (off >= pRam->cb);
2819	}
2820	*ppRamHint = pRam;
2821	}
2822	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2823	#ifndef VBOX_WITH_NEW_PHYS_CODE
2824
2825	/*
2826	* Make sure it's present.
2827	*/
2828	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2829	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2830	{
2831	#ifdef IN_RING3
2832	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2833	#else
2834	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2835	#endif
2836	if (VBOX_FAILURE(rc))
2837	{
2838	ppPage = NULL; / Shut up annoying smart ass. */
2839	return rc;
2840	}
2841	Assert(rc == VINF_SUCCESS);
2842	}
2843	#endif
2844	return VINF_SUCCESS;
2845	}
2846
2847
2848	/**
2849	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2850	*
2851	* @returns Pointer to the page on success.
2852	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2853	*
2854	* @param pPGM PGM handle.
2855	* @param GCPhys The GC physical address.
2856	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
2857	*/
2858	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2859	{
2860	/*
2861	* Optimize for the first range.
2862	*/
2863	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2864	RTGCPHYS off = GCPhys - pRam->GCPhys;
2865	if (RT_UNLIKELY(off >= pRam->cb))
2866	{
2867	do
2868	{
2869	pRam = CTXALLSUFF(pRam->pNext);
2870	if (RT_UNLIKELY(!pRam))
2871	return NULL;
2872	off = GCPhys - pRam->GCPhys;
2873	} while (off >= pRam->cb);
2874	}
2875	*ppRam = pRam;
2876	return &pRam->aPages[off >> PAGE_SHIFT];
2877	}
2878
2879
2880
2881
2882	/**
2883	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2884	*
2885	* @returns Pointer to the page on success.
2886	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2887	*
2888	* @param pPGM PGM handle.
2889	* @param GCPhys The GC physical address.
2890	* @param ppPage Where to store the pointer to the PGMPAGE structure.
2891	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2892	*/
2893	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2894	{
2895	/*
2896	* Optimize for the first range.
2897	*/
2898	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2899	RTGCPHYS off = GCPhys - pRam->GCPhys;
2900	if (RT_UNLIKELY(off >= pRam->cb))
2901	{
2902	do
2903	{
2904	pRam = CTXALLSUFF(pRam->pNext);
2905	if (RT_UNLIKELY(!pRam))
2906	{
2907	ppRam = NULL; / Shut up silly GCC warnings. */
2908	ppPage = NULL; / ditto */
2909	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2910	}
2911	off = GCPhys - pRam->GCPhys;
2912	} while (off >= pRam->cb);
2913	}
2914	*ppRam = pRam;
2915	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2916	#ifndef VBOX_WITH_NEW_PHYS_CODE
2917
2918	/*
2919	* Make sure it's present.
2920	*/
2921	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2922	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2923	{
2924	#ifdef IN_RING3
2925	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2926	#else
2927	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2928	#endif
2929	if (VBOX_FAILURE(rc))
2930	{
2931	ppPage = NULL; / Shut up silly GCC warnings. */
2932	ppPage = NULL; / ditto */
2933	return rc;
2934	}
2935	Assert(rc == VINF_SUCCESS);
2936
2937	}
2938	#endif
2939	return VINF_SUCCESS;
2940	}
2941
2942
2943	/**
2944	* Convert GC Phys to HC Phys.
2945	*
2946	* @returns VBox status.
2947	* @param pPGM PGM handle.
2948	* @param GCPhys The GC physical address.
2949	* @param pHCPhys Where to store the corresponding HC physical address.
2950	*
2951	* @deprecated Doesn't deal with zero, shared or write monitored pages.
2952	* Avoid when writing new code!
2953	*/
2954	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2955	{
2956	PPGMPAGE pPage;
2957	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2958	if (VBOX_FAILURE(rc))
2959	return rc;
2960	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
2961	return VINF_SUCCESS;
2962	}
2963
2964
2965	#ifndef IN_GC
2966	/**
2967	* Queries the Physical TLB entry for a physical guest page,
2968	* attemting to load the TLB entry if necessary.
2969	*
2970	* @returns VBox status code.
2971	* @retval VINF_SUCCESS on success
2972	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2973	* @param pPGM The PGM instance handle.
2974	* @param GCPhys The address of the guest page.
2975	* @param ppTlbe Where to store the pointer to the TLB entry.
2976	*/
2977
2978	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
2979	{
2980	int rc;
2981	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
2982	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
2983	{
2984	STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
2985	rc = VINF_SUCCESS;
2986	}
2987	else
2988	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
2989	*ppTlbe = pTlbe;
2990	return rc;
2991	}
2992	#endif /* !IN_GC */
2993
2994
2995	#ifndef VBOX_WITH_NEW_PHYS_CODE
2996	/**
2997	* Convert GC Phys to HC Virt.
2998	*
2999	* @returns VBox status.
3000	* @param pPGM PGM handle.
3001	* @param GCPhys The GC physical address.
3002	* @param pHCPtr Where to store the corresponding HC virtual address.
3003	*
3004	* @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
3005	*/
3006	DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3007	{
3008	PPGMRAMRANGE pRam;
3009	PPGMPAGE pPage;
3010	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3011	if (VBOX_FAILURE(rc))
3012	{
3013	pHCPtr = 0; / Shut up silly GCC warnings. */
3014	return rc;
3015	}
3016	RTGCPHYS off = GCPhys - pRam->GCPhys;
3017
3018	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3019	{
3020	unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3021	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3022	return VINF_SUCCESS;
3023	}
3024	if (pRam->pvHC)
3025	{
3026	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3027	return VINF_SUCCESS;
3028	}
3029	pHCPtr = 0; / Shut up silly GCC warnings. */
3030	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3031	}
3032	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3033
3034
3035	/**
3036	* Convert GC Phys to HC Virt.
3037	*
3038	* @returns VBox status.
3039	* @param PVM VM handle.
3040	* @param pRam Ram range
3041	* @param GCPhys The GC physical address.
3042	* @param pHCPtr Where to store the corresponding HC virtual address.
3043	*
3044	* @deprecated This will be eliminated. Don't use it.
3045	*/
3046	DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3047	{
3048	RTGCPHYS off = GCPhys - pRam->GCPhys;
3049	Assert(off < pRam->cb);
3050
3051	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3052	{
3053	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3054	/* Physical chunk in dynamically allocated range not present? */
3055	if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
3056	{
3057	#ifdef IN_RING3
3058	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3059	#else
3060	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3061	#endif
3062	if (rc != VINF_SUCCESS)
3063	{
3064	pHCPtr = 0; / GCC crap */
3065	return rc;
3066	}
3067	}
3068	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3069	return VINF_SUCCESS;
3070	}
3071	if (pRam->pvHC)
3072	{
3073	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3074	return VINF_SUCCESS;
3075	}
3076	pHCPtr = 0; / GCC crap */
3077	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3078	}
3079
3080
3081	/**
3082	* Convert GC Phys to HC Virt and HC Phys.
3083	*
3084	* @returns VBox status.
3085	* @param pPGM PGM handle.
3086	* @param GCPhys The GC physical address.
3087	* @param pHCPtr Where to store the corresponding HC virtual address.
3088	* @param pHCPhys Where to store the HC Physical address and its flags.
3089	*
3090	* @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3091	* and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3092	*/
3093	DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3094	{
3095	PPGMRAMRANGE pRam;
3096	PPGMPAGE pPage;
3097	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3098	if (VBOX_FAILURE(rc))
3099	{
3100	pHCPtr = 0; / Shut up crappy GCC warnings */
3101	pHCPhys = 0; / ditto */
3102	return rc;
3103	}
3104	RTGCPHYS off = GCPhys - pRam->GCPhys;
3105
3106	pHCPhys = pPage->HCPhys; /* @todo PAGE FLAGS */
3107	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3108	{
3109	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3110	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3111	return VINF_SUCCESS;
3112	}
3113	if (pRam->pvHC)
3114	{
3115	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3116	return VINF_SUCCESS;
3117	}
3118	*pHCPtr = 0;
3119	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3120	}
3121
3122
3123	/**
3124	* Clears flags associated with a RAM address.
3125	*
3126	* @returns VBox status code.
3127	* @param pPGM PGM handle.
3128	* @param GCPhys Guest context physical address.
3129	* @param fFlags fFlags to clear. (Bits 0-11.)
3130	*/
3131	DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3132	{
3133	PPGMPAGE pPage;
3134	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3135	if (VBOX_FAILURE(rc))
3136	return rc;
3137
3138	fFlags &= ~X86_PTE_PAE_PG_MASK;
3139	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3140	return VINF_SUCCESS;
3141	}
3142
3143
3144	/**
3145	* Clears flags associated with a RAM address.
3146	*
3147	* @returns VBox status code.
3148	* @param pPGM PGM handle.
3149	* @param GCPhys Guest context physical address.
3150	* @param fFlags fFlags to clear. (Bits 0-11.)
3151	* @param ppRamHint Where to read and store the ram list hint.
3152	* The caller initializes this to NULL before the call.
3153	*/
3154	DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3155	{
3156	PPGMPAGE pPage;
3157	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3158	if (VBOX_FAILURE(rc))
3159	return rc;
3160
3161	fFlags &= ~X86_PTE_PAE_PG_MASK;
3162	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3163	return VINF_SUCCESS;
3164	}
3165
3166	/**
3167	* Sets (bitwise OR) flags associated with a RAM address.
3168	*
3169	* @returns VBox status code.
3170	* @param pPGM PGM handle.
3171	* @param GCPhys Guest context physical address.
3172	* @param fFlags fFlags to set clear. (Bits 0-11.)
3173	*/
3174	DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3175	{
3176	PPGMPAGE pPage;
3177	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3178	if (VBOX_FAILURE(rc))
3179	return rc;
3180
3181	fFlags &= ~X86_PTE_PAE_PG_MASK;
3182	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3183	return VINF_SUCCESS;
3184	}
3185
3186
3187	/**
3188	* Sets (bitwise OR) flags associated with a RAM address.
3189	*
3190	* @returns VBox status code.
3191	* @param pPGM PGM handle.
3192	* @param GCPhys Guest context physical address.
3193	* @param fFlags fFlags to set clear. (Bits 0-11.)
3194	* @param ppRamHint Where to read and store the ram list hint.
3195	* The caller initializes this to NULL before the call.
3196	*/
3197	DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3198	{
3199	PPGMPAGE pPage;
3200	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3201	if (VBOX_FAILURE(rc))
3202	return rc;
3203
3204	fFlags &= ~X86_PTE_PAE_PG_MASK;
3205	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3206	return VINF_SUCCESS;
3207	}
3208
3209
3210	/**
3211	* Gets the page directory for the specified address.
3212	*
3213	* @returns Pointer to the page directory in question.
3214	* @returns NULL if the page directory is not present or on an invalid page.
3215	* @param pPGM Pointer to the PGM instance data.
3216	* @param GCPtr The address.
3217	*/
3218	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3219	{
3220	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3221	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3222	{
3223	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3224	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3225
3226	/* cache is out-of-sync. */
3227	PX86PDPAE pPD;
3228	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3229	if (VBOX_SUCCESS(rc))
3230	return pPD;
3231	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3232	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3233	}
3234	return NULL;
3235	}
3236
3237
3238	/**
3239	* Gets the page directory entry for the specified address.
3240	*
3241	* @returns Pointer to the page directory entry in question.
3242	* @returns NULL if the page directory is not present or on an invalid page.
3243	* @param pPGM Pointer to the PGM instance data.
3244	* @param GCPtr The address.
3245	*/
3246	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3247	{
3248	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3249	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3250	{
3251	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3252	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3253	return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3254
3255	/* The cache is out-of-sync. */
3256	PX86PDPAE pPD;
3257	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3258	if (VBOX_SUCCESS(rc))
3259	return &pPD->a[iPD];
3260	AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3261	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3262	}
3263	return NULL;
3264	}
3265
3266
3267	/**
3268	* Gets the page directory entry for the specified address.
3269	*
3270	* @returns The page directory entry in question.
3271	* @returns A non-present entry if the page directory is not present or on an invalid page.
3272	* @param pPGM Pointer to the PGM instance data.
3273	* @param GCPtr The address.
3274	*/
3275	DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3276	{
3277	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3278	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3279	{
3280	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3281	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3282	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3283
3284	/* cache is out-of-sync. */
3285	PX86PDPAE pPD;
3286	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3287	if (VBOX_SUCCESS(rc))
3288	return pPD->a[iPD].u;
3289	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3290	}
3291	return 0ULL;
3292	}
3293
3294
3295	/**
3296	* Gets the page directory pointer table entry for the specified address
3297	* and returns the index into the page directory
3298	*
3299	* @returns Pointer to the page directory in question.
3300	* @returns NULL if the page directory is not present or on an invalid page.
3301	* @param pPGM Pointer to the PGM instance data.
3302	* @param GCPtr The address.
3303	* @param piPD Receives the index into the returned page directory
3304	*/
3305	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3306	{
3307	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3308	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3309	{
3310	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3311	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3312	{
3313	*piPD = iPD;
3314	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3315	}
3316
3317	/* cache is out-of-sync. */
3318	PX86PDPAE pPD;
3319	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3320	if (VBOX_SUCCESS(rc))
3321	{
3322	*piPD = iPD;
3323	return pPD;
3324	}
3325	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3326	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3327	}
3328	return NULL;
3329	}
3330
3331	#ifndef IN_GC
3332	/**
3333	* Gets the page directory pointer entry for the specified address.
3334	*
3335	* @returns Pointer to the page directory pointer entry in question.
3336	* @returns NULL if the page directory is not present or on an invalid page.
3337	* @param pPGM Pointer to the PGM instance data.
3338	* @param GCPtr The address.
3339	* @param ppPml4e Page Map Level-4 Entry (out)
3340	*/
3341	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e)
3342	{
3343	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3344
3345	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3346	if ((*ppPml4e)->n.u1Present)
3347	{
3348	PX86PDPT pPdpt;
3349	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdpt);
3350	if (VBOX_FAILURE(rc))
3351	{
3352	AssertFailed();
3353	return NULL;
3354	}
3355	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3356	return &pPdpt->a[iPdPt];
3357	}
3358	return NULL;
3359	}
3360
3361	/**
3362	* Gets the page directory entry for the specified address.
3363	*
3364	* @returns The page directory entry in question.
3365	* @returns A non-present entry if the page directory is not present or on an invalid page.
3366	* @param pPGM Pointer to the PGM instance data.
3367	* @param GCPtr The address.
3368	* @param ppPml4e Page Map Level-4 Entry (out)
3369	* @param pPdpe Page directory pointer table entry (out)
3370	*/
3371	DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3372	{
3373	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3374
3375	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3376	if ((*ppPml4e)->n.u1Present)
3377	{
3378	PX86PDPT pPdptTemp;
3379	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3380	if (VBOX_FAILURE(rc))
3381	{
3382	AssertFailed();
3383	return 0ULL;
3384	}
3385
3386	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3387	*pPdpe = pPdptTemp->a[iPdPt];
3388	if (pPdpe->n.u1Present)
3389	{
3390	PX86PDPAE pPD;
3391
3392	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3393	if (VBOX_FAILURE(rc))
3394	{
3395	AssertFailed();
3396	return 0ULL;
3397	}
3398	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3399	return pPD->a[iPD].u;
3400	}
3401	}
3402	return 0ULL;
3403	}
3404
3405	/**
3406	* Gets the page directory entry for the specified address.
3407	*
3408	* @returns The page directory entry in question.
3409	* @returns A non-present entry if the page directory is not present or on an invalid page.
3410	* @param pPGM Pointer to the PGM instance data.
3411	* @param GCPtr The address.
3412	*/
3413	DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3414	{
3415	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3416
3417	if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3418	{
3419	PX86PDPT pPdptTemp;
3420	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3421	if (VBOX_FAILURE(rc))
3422	{
3423	AssertFailed();
3424	return 0ULL;
3425	}
3426
3427	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3428	if (pPdptTemp->a[iPdPt].n.u1Present)
3429	{
3430	PX86PDPAE pPD;
3431
3432	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3433	if (VBOX_FAILURE(rc))
3434	{
3435	AssertFailed();
3436	return 0ULL;
3437	}
3438	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3439	return pPD->a[iPD].u;
3440	}
3441	}
3442	return 0ULL;
3443	}
3444
3445	/**
3446	* Gets the page directory entry for the specified address.
3447	*
3448	* @returns Pointer to the page directory entry in question.
3449	* @returns NULL if the page directory is not present or on an invalid page.
3450	* @param pPGM Pointer to the PGM instance data.
3451	* @param GCPtr The address.
3452	*/
3453	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3454	{
3455	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3456
3457	if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3458	{
3459	PX86PDPT pPdptTemp;
3460	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3461	if (VBOX_FAILURE(rc))
3462	{
3463	AssertFailed();
3464	return NULL;
3465	}
3466
3467	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3468	if (pPdptTemp->a[iPdPt].n.u1Present)
3469	{
3470	PX86PDPAE pPD;
3471
3472	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3473	if (VBOX_FAILURE(rc))
3474	{
3475	AssertFailed();
3476	return NULL;
3477	}
3478	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3479	return &pPD->a[iPD];
3480	}
3481	}
3482	return NULL;
3483	}
3484
3485
3486	/**
3487	* Gets the GUEST page directory pointer for the specified address.
3488	*
3489	* @returns The page directory in question.
3490	* @returns NULL if the page directory is not present or on an invalid page.
3491	* @param pPGM Pointer to the PGM instance data.
3492	* @param GCPtr The address.
3493	* @param ppPml4e Page Map Level-4 Entry (out)
3494	* @param pPdpe Page directory pointer table entry (out)
3495	* @param piPD Receives the index into the returned page directory
3496	*/
3497	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
3498	{
3499	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3500
3501	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3502	if ((*ppPml4e)->n.u1Present)
3503	{
3504	PX86PDPT pPdptTemp;
3505	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3506	if (VBOX_FAILURE(rc))
3507	{
3508	AssertFailed();
3509	return 0ULL;
3510	}
3511
3512	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3513	*pPdpe = pPdptTemp->a[iPdPt];
3514	if (pPdpe->n.u1Present)
3515	{
3516	PX86PDPAE pPD;
3517
3518	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3519	if (VBOX_FAILURE(rc))
3520	{
3521	AssertFailed();
3522	return 0ULL;
3523	}
3524	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3525	return pPD;
3526	}
3527	}
3528	return 0ULL;
3529	}
3530	#endif /* !IN_GC */
3531
3532	/**
3533	* Checks if any of the specified page flags are set for the given page.
3534	*
3535	* @returns true if any of the flags are set.
3536	* @returns false if all the flags are clear.
3537	* @param pPGM PGM handle.
3538	* @param GCPhys The GC physical address.
3539	* @param fFlags The flags to check for.
3540	*/
3541	DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3542	{
3543	PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3544	return pPage
3545	&& (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3546	}
3547
3548
3549	/**
3550	* Gets the page state for a physical handler.
3551	*
3552	* @returns The physical handler page state.
3553	* @param pCur The physical handler in question.
3554	*/
3555	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3556	{
3557	switch (pCur->enmType)
3558	{
3559	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3560	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3561
3562	case PGMPHYSHANDLERTYPE_MMIO:
3563	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3564	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3565
3566	default:
3567	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3568	}
3569	}
3570
3571
3572	/**
3573	* Gets the page state for a virtual handler.
3574	*
3575	* @returns The virtual handler page state.
3576	* @param pCur The virtual handler in question.
3577	* @remarks This should never be used on a hypervisor access handler.
3578	*/
3579	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3580	{
3581	switch (pCur->enmType)
3582	{
3583	case PGMVIRTHANDLERTYPE_WRITE:
3584	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3585	case PGMVIRTHANDLERTYPE_ALL:
3586	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3587	default:
3588	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3589	}
3590	}
3591
3592
3593	/**
3594	* Clears one physical page of a virtual handler
3595	*
3596	* @param pPGM Pointer to the PGM instance.
3597	* @param pCur Virtual handler structure
3598	* @param iPage Physical page index
3599	*
3600	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3601	* need to care about other handlers in the same page.
3602	*/
3603	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3604	{
3605	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3606
3607	/*
3608	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
3609	*/
3610	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3611	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3612	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3613	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3614	#endif
3615	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3616	{
3617	/* We're the head of the alias chain. */
3618	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3619	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3620	AssertReleaseMsg(pRemove != NULL,
3621	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3622	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3623	AssertReleaseMsg(pRemove == pPhys2Virt,
3624	("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3625	" got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3626	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3627	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3628	#endif
3629	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3630	{
3631	/* Insert the next list in the alias chain into the tree. */
3632	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3633	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3634	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3635	("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3636	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3637	#endif
3638	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
3639	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3640	AssertRelease(fRc);
3641	}
3642	}
3643	else
3644	{
3645	/* Locate the previous node in the alias chain. */
3646	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3647	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3648	AssertReleaseMsg(pPrev != pPhys2Virt,
3649	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3650	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3651	#endif
3652	for (;;)
3653	{
3654	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3655	if (pNext == pPhys2Virt)
3656	{
3657	/* unlink. */
3658	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3659	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3660	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3661	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3662	else
3663	{
3664	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3665	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3666	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3667	}
3668	break;
3669	}
3670
3671	/* next */
3672	if (pNext == pPrev)
3673	{
3674	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3675	AssertReleaseMsg(pNext != pPrev,
3676	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3677	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3678	#endif
3679	break;
3680	}
3681	pPrev = pNext;
3682	}
3683	}
3684	Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3685	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3686	pPhys2Virt->offNextAlias = 0;
3687	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3688
3689	/*
3690	* Clear the ram flags for this page.
3691	*/
3692	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3693	AssertReturnVoid(pPage);
3694	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3695	}
3696
3697
3698	/**
3699	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
3700	*
3701	* @returns Pointer to the shadow page structure.
3702	* @param pPool The pool.
3703	* @param HCPhys The HC physical address of the shadow page.
3704	*/
3705	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3706	{
3707	/*
3708	* Look up the page.
3709	*/
3710	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3711	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3712	return pPage;
3713	}
3714
3715
3716	/**
3717	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
3718	*
3719	* @returns Pointer to the shadow page structure.
3720	* @param pPool The pool.
3721	* @param idx The pool page index.
3722	*/
3723	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3724	{
3725	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3726	return &pPool->aPages[idx];
3727	}
3728
3729
3730	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3731	/**
3732	* Clear references to guest physical memory.
3733	*
3734	* @param pPool The pool.
3735	* @param pPoolPage The pool page.
3736	* @param pPhysPage The physical guest page tracking structure.
3737	*/
3738	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3739	{
3740	/*
3741	* Just deal with the simple case here.
3742	*/
3743	#ifdef LOG_ENABLED
3744	const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3745	#endif
3746	const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3747	if (cRefs == 1)
3748	{
3749	Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3750	pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3751	}
3752	else
3753	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3754	LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3755	}
3756	#endif
3757
3758
3759	#ifdef PGMPOOL_WITH_CACHE
3760	/**
3761	* Moves the page to the head of the age list.
3762	*
3763	* This is done when the cached page is used in one way or another.
3764	*
3765	* @param pPool The pool.
3766	* @param pPage The cached page.
3767	* @todo inline in PGMInternal.h!
3768	*/
3769	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3770	{
3771	/*
3772	* Move to the head of the age list.
3773	*/
3774	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3775	{
3776	/* unlink */
3777	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3778	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3779	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3780	else
3781	pPool->iAgeTail = pPage->iAgePrev;
3782
3783	/* insert at head */
3784	pPage->iAgePrev = NIL_PGMPOOL_IDX;
3785	pPage->iAgeNext = pPool->iAgeHead;
3786	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3787	pPool->iAgeHead = pPage->idx;
3788	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3789	}
3790	}
3791	#endif /* PGMPOOL_WITH_CACHE */
3792
3793	/**
3794	* Tells if mappings are to be put into the shadow page table or not
3795	*
3796	* @returns boolean result
3797	* @param pVM VM handle.
3798	*/
3799
3800	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3801	{
3802	#ifdef IN_RING0
3803	/* There are no mappings in VT-x and AMD-V mode. */
3804	Assert(pPGM->fDisableMappings);
3805	return false;
3806	#else
3807	return !pPGM->fDisableMappings;
3808	#endif
3809	}
3810
3811	/** @} */
3812
3813	#endif

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 8533

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