VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 8860

Last change on this file since 8860 was 8853, checked in by vboxsync, 17 years ago

Manual page invalidation or TLB flush is required for AMD-V.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 150.1 KB
Line 
1/* $Id: PGMInternal.h 8853 2008-05-15 13:57:31Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
44# error "Not in PGM! This is an internal header!"
45#endif
46
47
48/** @defgroup grp_pgm_int Internals
49 * @ingroup grp_pgm
50 * @internal
51 * @{
52 */
53
54
55/** @name PGM Compile Time Config
56 * @{
57 */
58
59/**
60 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
61 * Comment it if it will break something.
62 */
63#define PGM_OUT_OF_SYNC_IN_GC
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Sync N pages instead of a whole page table
72 */
73#define PGM_SYNC_N_PAGES
74
75/**
76 * Number of pages to sync during a page fault
77 *
78 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
79 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
80 */
81#define PGM_SYNC_NR_PAGES 8
82
83/**
84 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
85 */
86#define PGM_MAX_PHYSCACHE_ENTRIES 64
87#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
88
89/**
90 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
91 */
92#define PGM_PHYSMEMACCESS_CACHING
93
94/** @def PGMPOOL_WITH_CACHE
95 * Enable agressive caching using the page pool.
96 *
97 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
98 */
99#define PGMPOOL_WITH_CACHE
100
101/** @def PGMPOOL_WITH_MIXED_PT_CR3
102 * When defined, we'll deal with 'uncachable' pages.
103 */
104#ifdef PGMPOOL_WITH_CACHE
105# define PGMPOOL_WITH_MIXED_PT_CR3
106#endif
107
108/** @def PGMPOOL_WITH_MONITORING
109 * Monitor the guest pages which are shadowed.
110 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
111 * be enabled as well.
112 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
113 */
114#ifdef PGMPOOL_WITH_CACHE
115# define PGMPOOL_WITH_MONITORING
116#endif
117
118/** @def PGMPOOL_WITH_GCPHYS_TRACKING
119 * Tracking the of shadow pages mapping guest physical pages.
120 *
121 * This is very expensive, the current cache prototype is trying to figure out
122 * whether it will be acceptable with an agressive caching policy.
123 */
124#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
125# define PGMPOOL_WITH_GCPHYS_TRACKING
126#endif
127
128/** @def PGMPOOL_WITH_USER_TRACKNG
129 * Tracking users of shadow pages. This is required for the linking of shadow page
130 * tables and physical guest addresses.
131 */
132#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
133# define PGMPOOL_WITH_USER_TRACKING
134#endif
135
136/** @def PGMPOOL_CFG_MAX_GROW
137 * The maximum number of pages to add to the pool in one go.
138 */
139#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
140
141/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
142 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
143 */
144#ifdef VBOX_STRICT
145# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
146#endif
147/** @} */
148
149
150/** @name PDPT and PML4 flags.
151 * These are placed in the three bits available for system programs in
152 * the PDPT and PML4 entries.
153 * @{ */
154/** The entry is a permanent one and it's must always be present.
155 * Never free such an entry. */
156#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
157/** Mapping (hypervisor allocated pagetable). */
158#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
159/** @} */
160
161/** @name Page directory flags.
162 * These are placed in the three bits available for system programs in
163 * the page directory entries.
164 * @{ */
165/** Mapping (hypervisor allocated pagetable). */
166#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
167/** Made read-only to facilitate dirty bit tracking. */
168#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
169/** @} */
170
171/** @name Page flags.
172 * These are placed in the three bits available for system programs in
173 * the page entries.
174 * @{ */
175/** Made read-only to facilitate dirty bit tracking. */
176#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
177
178#ifndef PGM_PTFLAGS_CSAM_VALIDATED
179/** Scanned and approved by CSAM (tm).
180 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
181 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
182#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
183#endif
184/** @} */
185
186/** @name Defines used to indicate the shadow and guest paging in the templates.
187 * @{ */
188#define PGM_TYPE_REAL 1
189#define PGM_TYPE_PROT 2
190#define PGM_TYPE_32BIT 3
191#define PGM_TYPE_PAE 4
192#define PGM_TYPE_AMD64 5
193/** @} */
194
195/** Macro for checking if the guest is using paging.
196 * @param uType PGM_TYPE_*
197 * @remark ASSUMES certain order of the PGM_TYPE_* values.
198 */
199#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT)
200
201/** Macro for checking if the guest supports the NX bit.
202 * @param uType PGM_TYPE_*
203 * @remark ASSUMES certain order of the PGM_TYPE_* values.
204 */
205#define PGM_WITH_NX(uType) ((uType) >= PGM_TYPE_PAE)
206
207
208/** @def PGM_HCPHYS_2_PTR
209 * Maps a HC physical page pool address to a virtual address.
210 *
211 * @returns VBox status code.
212 * @param pVM The VM handle.
213 * @param HCPhys The HC physical address to map to a virtual one.
214 * @param ppv Where to store the virtual address. No need to cast this.
215 *
216 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
217 * small page window employeed by that function. Be careful.
218 * @remark There is no need to assert on the result.
219 */
220#ifdef IN_GC
221# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
222#else
223# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
224#endif
225
226/** @def PGM_GCPHYS_2_PTR
227 * Maps a GC physical page address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param GCPhys The GC physical address to map to a virtual one.
232 * @param ppv Where to store the virtual address. No need to cast this.
233 *
234 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
235 * small page window employeed by that function. Be careful.
236 * @remark There is no need to assert on the result.
237 */
238#ifdef IN_GC
239# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
240#else
241# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
242#endif
243
244/** @def PGM_GCPHYS_2_PTR_EX
245 * Maps a unaligned GC physical page address to a virtual address.
246 *
247 * @returns VBox status code.
248 * @param pVM The VM handle.
249 * @param GCPhys The GC physical address to map to a virtual one.
250 * @param ppv Where to store the virtual address. No need to cast this.
251 *
252 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
253 * small page window employeed by that function. Be careful.
254 * @remark There is no need to assert on the result.
255 */
256#ifdef IN_GC
257# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
258#else
259# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
260#endif
261
262/** @def PGM_INVL_PG
263 * Invalidates a page when in GC does nothing in HC.
264 *
265 * @param GCVirt The virtual address of the page to invalidate.
266 */
267#ifdef IN_GC
268# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
269#elif defined(IN_RING0)
270# define PGM_INVL_PG(GCVirt) HWACCMR0InvalidatePage(pVM, (RTGCPTR)(GCVirt))
271#else
272# define PGM_INVL_PG(GCVirt) ((void)0)
273#endif
274
275/** @def PGM_INVL_BIG_PG
276 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
277 *
278 * @param GCVirt The virtual address within the page directory to invalidate.
279 */
280#ifdef IN_GC
281# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
282#elif defined(IN_RING0)
283# define PGM_INVL_BIG_PG(GCVirt) HWACCMR0FlushTLB(pVM)
284#else
285# define PGM_INVL_BIG_PG(GCVirt) ((void)0)
286#endif
287
288/** @def PGM_INVL_GUEST_TLBS()
289 * Invalidates all guest TLBs.
290 */
291#ifdef IN_GC
292# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
293#elif defined(IN_RING0)
294# define PGM_INVL_GUEST_TLBS() HWACCMR0FlushTLB(pVM)
295#else
296# define PGM_INVL_GUEST_TLBS() ((void)0)
297#endif
298
299
300/**
301 * Structure for tracking GC Mappings.
302 *
303 * This structure is used by linked list in both GC and HC.
304 */
305typedef struct PGMMAPPING
306{
307 /** Pointer to next entry. */
308 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
309 /** Pointer to next entry. */
310 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
311 /** Pointer to next entry. */
312 GCPTRTYPE(struct PGMMAPPING *) pNextGC;
313 /** Start Virtual address. */
314 RTGCUINTPTR GCPtr;
315 /** Last Virtual address (inclusive). */
316 RTGCUINTPTR GCPtrLast;
317 /** Range size (bytes). */
318 RTGCUINTPTR cb;
319 /** Pointer to relocation callback function. */
320 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
321 /** User argument to the callback. */
322 R3PTRTYPE(void *) pvUser;
323 /** Mapping description / name. For easing debugging. */
324 R3PTRTYPE(const char *) pszDesc;
325 /** Number of page tables. */
326 RTUINT cPTs;
327#if HC_ARCH_BITS != GC_ARCH_BITS
328 RTUINT uPadding0; /**< Alignment padding. */
329#endif
330 /** Array of page table mapping data. Each entry
331 * describes one page table. The array can be longer
332 * than the declared length.
333 */
334 struct
335 {
336 /** The HC physical address of the page table. */
337 RTHCPHYS HCPhysPT;
338 /** The HC physical address of the first PAE page table. */
339 RTHCPHYS HCPhysPaePT0;
340 /** The HC physical address of the second PAE page table. */
341 RTHCPHYS HCPhysPaePT1;
342 /** The HC virtual address of the 32-bit page table. */
343 R3PTRTYPE(PX86PT) pPTR3;
344 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
345 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
346 /** The GC virtual address of the 32-bit page table. */
347 GCPTRTYPE(PX86PT) pPTGC;
348 /** The GC virtual address of the two PAE page table. */
349 GCPTRTYPE(PX86PTPAE) paPaePTsGC;
350 /** The GC virtual address of the 32-bit page table. */
351 R0PTRTYPE(PX86PT) pPTR0;
352 /** The GC virtual address of the two PAE page table. */
353 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
354 } aPTs[1];
355} PGMMAPPING;
356/** Pointer to structure for tracking GC Mappings. */
357typedef struct PGMMAPPING *PPGMMAPPING;
358
359
360/**
361 * Physical page access handler structure.
362 *
363 * This is used to keep track of physical address ranges
364 * which are being monitored in some kind of way.
365 */
366typedef struct PGMPHYSHANDLER
367{
368 AVLROGCPHYSNODECORE Core;
369 /** Access type. */
370 PGMPHYSHANDLERTYPE enmType;
371 /** Number of pages to update. */
372 uint32_t cPages;
373 /** Pointer to R3 callback function. */
374 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
375 /** User argument for R3 handlers. */
376 R3PTRTYPE(void *) pvUserR3;
377 /** Pointer to R0 callback function. */
378 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
379 /** User argument for R0 handlers. */
380 R0PTRTYPE(void *) pvUserR0;
381 /** Pointer to GC callback function. */
382 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
383 /** User argument for GC handlers. */
384 GCPTRTYPE(void *) pvUserGC;
385 /** Description / Name. For easing debugging. */
386 R3PTRTYPE(const char *) pszDesc;
387#ifdef VBOX_WITH_STATISTICS
388 /** Profiling of this handler. */
389 STAMPROFILE Stat;
390#endif
391} PGMPHYSHANDLER;
392/** Pointer to a physical page access handler structure. */
393typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
394
395
396/**
397 * Cache node for the physical addresses covered by a virtual handler.
398 */
399typedef struct PGMPHYS2VIRTHANDLER
400{
401 /** Core node for the tree based on physical ranges. */
402 AVLROGCPHYSNODECORE Core;
403 /** Offset from this struct to the PGMVIRTHANDLER structure. */
404 int32_t offVirtHandler;
405 /** Offset of the next alias relative to this one.
406 * Bit 0 is used for indicating whether we're in the tree.
407 * Bit 1 is used for indicating that we're the head node.
408 */
409 int32_t offNextAlias;
410} PGMPHYS2VIRTHANDLER;
411/** Pointer to a phys to virtual handler structure. */
412typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
413
414/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
415 * node is in the tree. */
416#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
417/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
418 * node is in the head of an alias chain.
419 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
420#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
421/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
422#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
423
424
425/**
426 * Virtual page access handler structure.
427 *
428 * This is used to keep track of virtual address ranges
429 * which are being monitored in some kind of way.
430 */
431typedef struct PGMVIRTHANDLER
432{
433 /** Core node for the tree based on virtual ranges. */
434 AVLROGCPTRNODECORE Core;
435 /** Number of cache pages. */
436 uint32_t u32Padding;
437 /** Access type. */
438 PGMVIRTHANDLERTYPE enmType;
439 /** Number of cache pages. */
440 uint32_t cPages;
441
442/** @todo The next two members are redundant. It adds some readability though. */
443 /** Start of the range. */
444 RTGCPTR GCPtr;
445 /** End of the range (exclusive). */
446 RTGCPTR GCPtrLast;
447 /** Size of the range (in bytes). */
448 RTGCUINTPTR cb;
449 /** Pointer to the GC callback function. */
450 GCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
451 /** Pointer to the HC callback function for invalidation. */
452 R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
453 /** Pointer to the HC callback function. */
454 R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
455 /** Description / Name. For easing debugging. */
456 R3PTRTYPE(const char *) pszDesc;
457#ifdef VBOX_WITH_STATISTICS
458 /** Profiling of this handler. */
459 STAMPROFILE Stat;
460#endif
461 /** Array of cached physical addresses for the monitored ranged. */
462 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
463} PGMVIRTHANDLER;
464/** Pointer to a virtual page access handler structure. */
465typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
466
467
468/**
469 * Page type.
470 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
471 * @todo convert to \#defines.
472 */
473typedef enum PGMPAGETYPE
474{
475 /** The usual invalid zero entry. */
476 PGMPAGETYPE_INVALID = 0,
477 /** RAM page. (RWX) */
478 PGMPAGETYPE_RAM,
479 /** MMIO2 page. (RWX) */
480 PGMPAGETYPE_MMIO2,
481 /** Shadowed ROM. (RWX) */
482 PGMPAGETYPE_ROM_SHADOW,
483 /** ROM page. (R-X) */
484 PGMPAGETYPE_ROM,
485 /** MMIO page. (---) */
486 PGMPAGETYPE_MMIO,
487 /** End of valid entries. */
488 PGMPAGETYPE_END
489} PGMPAGETYPE;
490AssertCompile(PGMPAGETYPE_END < 7);
491
492/** @name Page type predicates.
493 * @{ */
494#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
495#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
496#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
497#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
498#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
499/** @} */
500
501
502/**
503 * A Physical Guest Page tracking structure.
504 *
505 * The format of this structure is complicated because we have to fit a lot
506 * of information into as few bits as possible. The format is also subject
507 * to change (there is one comming up soon). Which means that for we'll be
508 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
509 * accessess to the structure.
510 */
511typedef struct PGMPAGE
512{
513 /** The physical address and a whole lot of other stuff. All bits are used! */
514 RTHCPHYS HCPhys;
515 /** The page state. */
516 uint32_t u2StateX : 2;
517 /** Flag indicating that a write monitored page was written to when set. */
518 uint32_t fWrittenToX : 1;
519 /** For later. */
520 uint32_t fSomethingElse : 1;
521 /** The Page ID.
522 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
523 * The HCPhys will be 100% static. */
524 uint32_t idPageX : 28;
525 /** The page type (PGMPAGETYPE). */
526 uint32_t u3Type : 3;
527 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
528 uint32_t u2HandlerPhysStateX : 2;
529 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
530 uint32_t u2HandlerVirtStateX : 2;
531 uint32_t u29B : 25;
532} PGMPAGE;
533AssertCompileSize(PGMPAGE, 16);
534/** Pointer to a physical guest page. */
535typedef PGMPAGE *PPGMPAGE;
536/** Pointer to a const physical guest page. */
537typedef const PGMPAGE *PCPGMPAGE;
538/** Pointer to a physical guest page pointer. */
539typedef PPGMPAGE *PPPGMPAGE;
540
541
542/**
543 * Clears the page structure.
544 * @param pPage Pointer to the physical guest page tracking structure.
545 */
546#define PGM_PAGE_CLEAR(pPage) \
547 do { \
548 (pPage)->HCPhys = 0; \
549 (pPage)->u2StateX = 0; \
550 (pPage)->fWrittenToX = 0; \
551 (pPage)->fSomethingElse = 0; \
552 (pPage)->idPageX = 0; \
553 (pPage)->u3Type = 0; \
554 (pPage)->u29B = 0; \
555 } while (0)
556
557/**
558 * Initializes the page structure.
559 * @param pPage Pointer to the physical guest page tracking structure.
560 */
561#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
562 do { \
563 (pPage)->HCPhys = (_HCPhys); \
564 (pPage)->u2StateX = (_uState); \
565 (pPage)->fWrittenToX = 0; \
566 (pPage)->fSomethingElse = 0; \
567 (pPage)->idPageX = (_idPage); \
568 /*(pPage)->u3Type = (_uType); - later */ \
569 PGM_PAGE_SET_TYPE(pPage, _uType); \
570 (pPage)->u29B = 0; \
571 } while (0)
572
573/**
574 * Initializes the page structure of a ZERO page.
575 * @param pPage Pointer to the physical guest page tracking structure.
576 */
577#ifdef VBOX_WITH_NEW_PHYS_CODE
578# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
579 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
580#else
581# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
582 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
583#endif
584/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
585# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
586 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
587
588
589/** @name The Page state, PGMPAGE::u2StateX.
590 * @{ */
591/** The zero page.
592 * This is a per-VM page that's never ever mapped writable. */
593#define PGM_PAGE_STATE_ZERO 0
594/** A allocated page.
595 * This is a per-VM page allocated from the page pool (or wherever
596 * we get MMIO2 pages from if the type is MMIO2).
597 */
598#define PGM_PAGE_STATE_ALLOCATED 1
599/** A allocated page that's being monitored for writes.
600 * The shadow page table mappings are read-only. When a write occurs, the
601 * fWrittenTo member is set, the page remapped as read-write and the state
602 * moved back to allocated. */
603#define PGM_PAGE_STATE_WRITE_MONITORED 2
604/** The page is shared, aka. copy-on-write.
605 * This is a page that's shared with other VMs. */
606#define PGM_PAGE_STATE_SHARED 3
607/** @} */
608
609
610/**
611 * Gets the page state.
612 * @returns page state (PGM_PAGE_STATE_*).
613 * @param pPage Pointer to the physical guest page tracking structure.
614 */
615#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
616
617/**
618 * Sets the page state.
619 * @param pPage Pointer to the physical guest page tracking structure.
620 * @param _uState The new page state.
621 */
622#define PGM_PAGE_SET_STATE(pPage, _uState) \
623 do { (pPage)->u2StateX = (_uState); } while (0)
624
625
626/**
627 * Gets the host physical address of the guest page.
628 * @returns host physical address (RTHCPHYS).
629 * @param pPage Pointer to the physical guest page tracking structure.
630 */
631#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
632
633/**
634 * Sets the host physical address of the guest page.
635 * @param pPage Pointer to the physical guest page tracking structure.
636 * @param _HCPhys The new host physical address.
637 */
638#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
639 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
640 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
641
642/**
643 * Get the Page ID.
644 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
645 * @param pPage Pointer to the physical guest page tracking structure.
646 */
647#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
648/* later:
649#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
650 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
651*/
652/**
653 * Sets the Page ID.
654 * @param pPage Pointer to the physical guest page tracking structure.
655 */
656#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
657/* later:
658#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
659 | ((_idPage) & 0xfff) \
660 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
661*/
662
663/**
664 * Get the Chunk ID.
665 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
666 * @param pPage Pointer to the physical guest page tracking structure.
667 */
668#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
669/* later:
670#if GMM_CHUNKID_SHIFT == 12
671# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
672#elif GMM_CHUNKID_SHIFT > 12
673# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
674#elif GMM_CHUNKID_SHIFT < 12
675# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
676 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
677#else
678# error "GMM_CHUNKID_SHIFT isn't defined or something."
679#endif
680*/
681
682/**
683 * Get the index of the page within the allocaiton chunk.
684 * @returns The page index.
685 * @param pPage Pointer to the physical guest page tracking structure.
686 */
687#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
688/* later:
689#if GMM_CHUNKID_SHIFT <= 12
690# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
691#else
692# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
693 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
694#endif
695*/
696
697
698/**
699 * Gets the page type.
700 * @returns The page type.
701 * @param pPage Pointer to the physical guest page tracking structure.
702 */
703#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
704
705/**
706 * Sets the page type.
707 * @param pPage Pointer to the physical guest page tracking structure.
708 * @param _enmType The new page type (PGMPAGETYPE).
709 */
710#ifdef VBOX_WITH_NEW_PHYS_CODE
711#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
712 do { (pPage)->u3Type = (_enmType); } while (0)
713#else
714#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
715 do { \
716 (pPage)->u3Type = (_enmType); \
717 if ((_enmType) == PGMPAGETYPE_ROM) \
718 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
719 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
720 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
721 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
722 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
723 } while (0)
724#endif
725
726
727/**
728 * Checks if the page is 'reserved'.
729 * @returns true/false.
730 * @param pPage Pointer to the physical guest page tracking structure.
731 */
732#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
733
734/**
735 * Checks if the page is marked for MMIO.
736 * @returns true/false.
737 * @param pPage Pointer to the physical guest page tracking structure.
738 */
739#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
740
741/**
742 * Checks if the page is backed by the ZERO page.
743 * @returns true/false.
744 * @param pPage Pointer to the physical guest page tracking structure.
745 */
746#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
747
748/**
749 * Checks if the page is backed by a SHARED page.
750 * @returns true/false.
751 * @param pPage Pointer to the physical guest page tracking structure.
752 */
753#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
754
755
756/**
757 * Marks the paget as written to (for GMM change monitoring).
758 * @param pPage Pointer to the physical guest page tracking structure.
759 */
760#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
761
762/**
763 * Clears the written-to indicator.
764 * @param pPage Pointer to the physical guest page tracking structure.
765 */
766#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
767
768/**
769 * Checks if the page was marked as written-to.
770 * @returns true/false.
771 * @param pPage Pointer to the physical guest page tracking structure.
772 */
773#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
774
775
776/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
777 *
778 * @remarks The values are assigned in order of priority, so we can calculate
779 * the correct state for a page with different handlers installed.
780 * @{ */
781/** No handler installed. */
782#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
783/** Monitoring is temporarily disabled. */
784#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
785/** Write access is monitored. */
786#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
787/** All access is monitored. */
788#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
789/** @} */
790
791/**
792 * Gets the physical access handler state of a page.
793 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
794 * @param pPage Pointer to the physical guest page tracking structure.
795 */
796#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
797
798/**
799 * Sets the physical access handler state of a page.
800 * @param pPage Pointer to the physical guest page tracking structure.
801 * @param _uState The new state value.
802 */
803#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
804 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
805
806/**
807 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
808 * @returns true/false
809 * @param pPage Pointer to the physical guest page tracking structure.
810 */
811#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
812
813/**
814 * Checks if the page has any active physical access handlers.
815 * @returns true/false
816 * @param pPage Pointer to the physical guest page tracking structure.
817 */
818#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
819
820
821/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
822 *
823 * @remarks The values are assigned in order of priority, so we can calculate
824 * the correct state for a page with different handlers installed.
825 * @{ */
826/** No handler installed. */
827#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
828/* 1 is reserved so the lineup is identical with the physical ones. */
829/** Write access is monitored. */
830#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
831/** All access is monitored. */
832#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
833/** @} */
834
835/**
836 * Gets the virtual access handler state of a page.
837 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
838 * @param pPage Pointer to the physical guest page tracking structure.
839 */
840#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
841
842/**
843 * Sets the virtual access handler state of a page.
844 * @param pPage Pointer to the physical guest page tracking structure.
845 * @param _uState The new state value.
846 */
847#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
848 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
849
850/**
851 * Checks if the page has any virtual access handlers.
852 * @returns true/false
853 * @param pPage Pointer to the physical guest page tracking structure.
854 */
855#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
856
857/**
858 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
859 * virtual handlers.
860 * @returns true/false
861 * @param pPage Pointer to the physical guest page tracking structure.
862 */
863#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
864
865
866
867/**
868 * Checks if the page has any access handlers, including temporarily disabled ones.
869 * @returns true/false
870 * @param pPage Pointer to the physical guest page tracking structure.
871 */
872#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
873 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
874 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
875
876/**
877 * Checks if the page has any active access handlers.
878 * @returns true/false
879 * @param pPage Pointer to the physical guest page tracking structure.
880 */
881#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
882 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
883 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
884
885/**
886 * Checks if the page has any active access handlers catching all accesses.
887 * @returns true/false
888 * @param pPage Pointer to the physical guest page tracking structure.
889 */
890#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
891 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
892 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
893
894
895/**
896 * Ram range for GC Phys to HC Phys conversion.
897 *
898 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
899 * conversions too, but we'll let MM handle that for now.
900 *
901 * This structure is used by linked lists in both GC and HC.
902 */
903typedef struct PGMRAMRANGE
904{
905 /** Pointer to the next RAM range - for R3. */
906 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
907 /** Pointer to the next RAM range - for R0. */
908 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
909 /** Pointer to the next RAM range - for GC. */
910 GCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
911#if GC_ARCH_BITS == 32
912 /** Pointer alignment. */
913 RTGCPTR GCPtrAlignment;
914#endif
915 /** Start of the range. Page aligned. */
916 RTGCPHYS GCPhys;
917 /** Last address in the range (inclusive). Page aligned (-1). */
918 RTGCPHYS GCPhysLast;
919 /** Size of the range. (Page aligned of course). */
920 RTGCPHYS cb;
921 /** MM_RAM_* flags */
922 uint32_t fFlags;
923#ifdef VBOX_WITH_NEW_PHYS_CODE
924 uint32_t u32Alignment; /**< alignment. */
925#else
926 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
927 GCPTRTYPE(PRTHCPTR) pavHCChunkGC;
928 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
929 R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
930#endif
931 /** Start of the HC mapping of the range. This is only used for MMIO2. */
932 R3PTRTYPE(void *) pvHC;
933 /** The range description. */
934 R3PTRTYPE(const char *) pszDesc;
935
936 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
937#ifdef VBOX_WITH_NEW_PHYS_CODE
938 uint32_t au32Reserved[2];
939#elif HC_ARCH_BITS == 32
940 uint32_t au32Reserved[1];
941#endif
942
943 /** Array of physical guest page tracking structures. */
944 PGMPAGE aPages[1];
945} PGMRAMRANGE;
946/** Pointer to Ram range for GC Phys to HC Phys conversion. */
947typedef PGMRAMRANGE *PPGMRAMRANGE;
948
949/** Return hc ptr corresponding to the ram range and physical offset */
950#define PGMRAMRANGE_GETHCPTR(pRam, off) \
951 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
952 : (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
953
954/**
955 * Per page tracking structure for ROM image.
956 *
957 * A ROM image may have a shadow page, in which case we may have
958 * two pages backing it. This structure contains the PGMPAGE for
959 * both while PGMRAMRANGE have a copy of the active one. It is
960 * important that these aren't out of sync in any regard other
961 * than page pool tracking data.
962 */
963typedef struct PGMROMPAGE
964{
965 /** The page structure for the virgin ROM page. */
966 PGMPAGE Virgin;
967 /** The page structure for the shadow RAM page. */
968 PGMPAGE Shadow;
969 /** The current protection setting. */
970 PGMROMPROT enmProt;
971 /** Pad the structure size to a multiple of 8. */
972 uint32_t u32Padding;
973} PGMROMPAGE;
974/** Pointer to a ROM page tracking structure. */
975typedef PGMROMPAGE *PPGMROMPAGE;
976
977
978/**
979 * A registered ROM image.
980 *
981 * This is needed to keep track of ROM image since they generally
982 * intrude into a PGMRAMRANGE. It also keeps track of additional
983 * info like the two page sets (read-only virgin and read-write shadow),
984 * the current state of each page.
985 *
986 * Because access handlers cannot easily be executed in a different
987 * context, the ROM ranges needs to be accessible and in all contexts.
988 */
989typedef struct PGMROMRANGE
990{
991 /** Pointer to the next range - R3. */
992 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
993 /** Pointer to the next range - R0. */
994 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
995 /** Pointer to the next range - GC. */
996 GCPTRTYPE(struct PGMROMRANGE *) pNextGC;
997#if GC_ARCH_BITS == 32
998 RTGCPTR GCPtrAlignment; /**< Pointer alignment. */
999#endif
1000 /** Address of the range. */
1001 RTGCPHYS GCPhys;
1002 /** Address of the last byte in the range. */
1003 RTGCPHYS GCPhysLast;
1004 /** Size of the range. */
1005 RTGCPHYS cb;
1006 /** The flags (PGMPHYS_ROM_FLAG_*). */
1007 uint32_t fFlags;
1008 /**< Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1009 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1010 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1011 * This is used for strictness checks. */
1012 R3PTRTYPE(const void *) pvOriginal;
1013 /** The ROM description. */
1014 R3PTRTYPE(const char *) pszDesc;
1015 /** The per page tracking structures. */
1016 PGMROMPAGE aPages[1];
1017} PGMROMRANGE;
1018/** Pointer to a ROM range. */
1019typedef PGMROMRANGE *PPGMROMRANGE;
1020
1021
1022/**
1023 * A registered MMIO2 (= Device RAM) range.
1024 *
1025 * There are a few reason why we need to keep track of these
1026 * registrations. One of them is the deregistration & cleanup
1027 * stuff, while another is that the PGMRAMRANGE associated with
1028 * such a region may have to be removed from the ram range list.
1029 *
1030 * Overlapping with a RAM range has to be 100% or none at all. The
1031 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1032 * meditation will be raised if a partial overlap or an overlap of
1033 * ROM pages is encountered. On an overlap we will free all the
1034 * existing RAM pages and put in the ram range pages instead.
1035 */
1036typedef struct PGMMMIO2RANGE
1037{
1038 /** The owner of the range. (a device) */
1039 PPDMDEVINSR3 pDevInsR3;
1040 /** Pointer to the ring-3 mapping of the allocation. */
1041 RTR3PTR pvR3;
1042 /** Pointer to the next range - R3. */
1043 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1044 /** Whether it's mapped or not. */
1045 bool fMapped;
1046 /** Whether it's overlapping or not. */
1047 bool fOverlapping;
1048 /** The PCI region number.
1049 * @remarks This ASSUMES that nobody will ever really need to have multiple
1050 * PCI devices with matching MMIO region numbers on a single device. */
1051 uint8_t iRegion;
1052 /**< Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1053 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1054 /** The associated RAM range. */
1055 PGMRAMRANGE RamRange;
1056} PGMMMIO2RANGE;
1057/** Pointer to a MMIO2 range. */
1058typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1059
1060
1061
1062
1063/** @todo r=bird: fix typename. */
1064/**
1065 * PGMPhysRead/Write cache entry
1066 */
1067typedef struct PGMPHYSCACHE_ENTRY
1068{
1069 /** HC pointer to physical page */
1070 R3PTRTYPE(uint8_t *) pbHC;
1071 /** GC Physical address for cache entry */
1072 RTGCPHYS GCPhys;
1073#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1074 RTGCPHYS u32Padding0; /**< alignment padding. */
1075#endif
1076} PGMPHYSCACHE_ENTRY;
1077
1078/**
1079 * PGMPhysRead/Write cache to reduce REM memory access overhead
1080 */
1081typedef struct PGMPHYSCACHE
1082{
1083 /** Bitmap of valid cache entries */
1084 uint64_t aEntries;
1085 /** Cache entries */
1086 PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1087} PGMPHYSCACHE;
1088
1089
1090/** Pointer to an allocation chunk ring-3 mapping. */
1091typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1092/** Pointer to an allocation chunk ring-3 mapping pointer. */
1093typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1094
1095/**
1096 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1097 *
1098 * The primary tree (Core) uses the chunk id as key.
1099 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1100 */
1101typedef struct PGMCHUNKR3MAP
1102{
1103 /** The key is the chunk id. */
1104 AVLU32NODECORE Core;
1105 /** The key is the ageing sequence number. */
1106 AVLLU32NODECORE AgeCore;
1107 /** The current age thingy. */
1108 uint32_t iAge;
1109 /** The current reference count. */
1110 uint32_t volatile cRefs;
1111 /** The current permanent reference count. */
1112 uint32_t volatile cPermRefs;
1113 /** The mapping address. */
1114 void *pv;
1115} PGMCHUNKR3MAP;
1116
1117/**
1118 * Allocation chunk ring-3 mapping TLB entry.
1119 */
1120typedef struct PGMCHUNKR3MAPTLBE
1121{
1122 /** The chunk id. */
1123 uint32_t volatile idChunk;
1124#if HC_ARCH_BITS == 64
1125 uint32_t u32Padding; /**< alignment padding. */
1126#endif
1127 /** The chunk map. */
1128 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1129} PGMCHUNKR3MAPTLBE;
1130/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1131typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1132
1133/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1134 * @remark Must be a power of two value. */
1135#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1136
1137/**
1138 * Allocation chunk ring-3 mapping TLB.
1139 *
1140 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1141 * At first glance this might look kinda odd since AVL trees are
1142 * supposed to give the most optimial lookup times of all trees
1143 * due to their balancing. However, take a tree with 1023 nodes
1144 * in it, that's 10 levels, meaning that most searches has to go
1145 * down 9 levels before they find what they want. This isn't fast
1146 * compared to a TLB hit. There is the factor of cache misses,
1147 * and of course the problem with trees and branch prediction.
1148 * This is why we use TLBs in front of most of the trees.
1149 *
1150 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1151 * difficult when we switch to inlined AVL trees (from kStuff).
1152 */
1153typedef struct PGMCHUNKR3MAPTLB
1154{
1155 /** The TLB entries. */
1156 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1157} PGMCHUNKR3MAPTLB;
1158
1159/**
1160 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1161 * @returns Chunk TLB index.
1162 * @param idChunk The Chunk ID.
1163 */
1164#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1165
1166
1167/**
1168 * Ring-3 guest page mapping TLB entry.
1169 * @remarks used in ring-0 as well at the moment.
1170 */
1171typedef struct PGMPAGER3MAPTLBE
1172{
1173 /** Address of the page. */
1174 RTGCPHYS volatile GCPhys;
1175 /** The guest page. */
1176 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1177 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1178 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1179 /** The address */
1180 R3R0PTRTYPE(void *) volatile pv;
1181#if HC_ARCH_BITS == 32
1182 uint32_t u32Padding; /**< alignment padding. */
1183#endif
1184} PGMPAGER3MAPTLBE;
1185/** Pointer to an entry in the HC physical TLB. */
1186typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1187
1188
1189/** The number of entries in the ring-3 guest page mapping TLB.
1190 * @remarks The value must be a power of two. */
1191#define PGM_PAGER3MAPTLB_ENTRIES 64
1192
1193/**
1194 * Ring-3 guest page mapping TLB.
1195 * @remarks used in ring-0 as well at the moment.
1196 */
1197typedef struct PGMPAGER3MAPTLB
1198{
1199 /** The TLB entries. */
1200 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1201} PGMPAGER3MAPTLB;
1202/** Pointer to the ring-3 guest page mapping TLB. */
1203typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1204
1205/**
1206 * Calculates the index of the TLB entry for the specified guest page.
1207 * @returns Physical TLB index.
1208 * @param GCPhys The guest physical address.
1209 */
1210#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1211
1212
1213/** @name Context neutrual page mapper TLB.
1214 *
1215 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1216 * code is writting in a kind of context neutrual way. Time will show whether
1217 * this actually makes sense or not...
1218 *
1219 * @{ */
1220/** @typedef PPGMPAGEMAPTLB
1221 * The page mapper TLB pointer type for the current context. */
1222/** @typedef PPGMPAGEMAPTLB
1223 * The page mapper TLB entry pointer type for the current context. */
1224/** @typedef PPGMPAGEMAPTLB
1225 * The page mapper TLB entry pointer pointer type for the current context. */
1226/** @def PGMPAGEMAPTLB_ENTRIES
1227 * The number of TLB entries in the page mapper TLB for the current context. */
1228/** @def PGM_PAGEMAPTLB_IDX
1229 * Calculate the TLB index for a guest physical address.
1230 * @returns The TLB index.
1231 * @param GCPhys The guest physical address. */
1232/** @typedef PPGMPAGEMAP
1233 * Pointer to a page mapper unit for current context. */
1234/** @typedef PPPGMPAGEMAP
1235 * Pointer to a page mapper unit pointer for current context. */
1236#ifdef IN_GC
1237// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1238// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1239// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1240# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1241# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1242 typedef void * PPGMPAGEMAP;
1243 typedef void ** PPPGMPAGEMAP;
1244//#elif IN_RING0
1245// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1246// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1247// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1248//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1249//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1250// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1251// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1252#else
1253 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1254 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1255 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1256# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1257# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1258 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1259 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1260#endif
1261/** @} */
1262
1263
1264/** @name PGM Pool Indexes.
1265 * Aka. the unique shadow page identifier.
1266 * @{ */
1267/** NIL page pool IDX. */
1268#define NIL_PGMPOOL_IDX 0
1269/** The first normal index. */
1270#define PGMPOOL_IDX_FIRST_SPECIAL 1
1271/** Page directory (32-bit root). */
1272#define PGMPOOL_IDX_PD 1
1273/** The extended PAE page directory (2048 entries, works as root currently). */
1274#define PGMPOOL_IDX_PAE_PD 2
1275 /** PAE Page Directory Table 0. */
1276#define PGMPOOL_IDX_PAE_PD_0 3
1277 /** PAE Page Directory Table 1. */
1278#define PGMPOOL_IDX_PAE_PD_1 4
1279 /** PAE Page Directory Table 2. */
1280#define PGMPOOL_IDX_PAE_PD_2 5
1281 /** PAE Page Directory Table 3. */
1282#define PGMPOOL_IDX_PAE_PD_3 6
1283/** Page Directory Pointer Table (PAE root, not currently used). */
1284#define PGMPOOL_IDX_PDPT 7
1285/** Page Map Level-4 (64-bit root). */
1286#define PGMPOOL_IDX_PML4 8
1287/** The first normal index. */
1288#define PGMPOOL_IDX_FIRST 9
1289/** The last valid index. (inclusive, 14 bits) */
1290#define PGMPOOL_IDX_LAST 0x3fff
1291/** @} */
1292
1293/** The NIL index for the parent chain. */
1294#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1295
1296/**
1297 * Node in the chain linking a shadowed page to it's parent (user).
1298 */
1299#pragma pack(1)
1300typedef struct PGMPOOLUSER
1301{
1302 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1303 uint16_t iNext;
1304 /** The user page index. */
1305 uint16_t iUser;
1306 /** Index into the user table. */
1307 uint16_t iUserTable;
1308} PGMPOOLUSER, *PPGMPOOLUSER;
1309typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1310#pragma pack()
1311
1312
1313/** The NIL index for the phys ext chain. */
1314#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1315
1316/**
1317 * Node in the chain of physical cross reference extents.
1318 */
1319#pragma pack(1)
1320typedef struct PGMPOOLPHYSEXT
1321{
1322 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1323 uint16_t iNext;
1324 /** The user page index. */
1325 uint16_t aidx[3];
1326} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1327typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1328#pragma pack()
1329
1330
1331/**
1332 * The kind of page that's being shadowed.
1333 */
1334typedef enum PGMPOOLKIND
1335{
1336 /** The virtual invalid 0 entry. */
1337 PGMPOOLKIND_INVALID = 0,
1338 /** The entry is free (=unused). */
1339 PGMPOOLKIND_FREE,
1340
1341 /** Shw: 32-bit page table; Gst: no paging */
1342 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1343 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1344 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1345 /** Shw: 32-bit page table; Gst: 4MB page. */
1346 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1347 /** Shw: PAE page table; Gst: no paging */
1348 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1349 /** Shw: PAE page table; Gst: 32-bit page table. */
1350 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1351 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1352 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1353 /** Shw: PAE page table; Gst: PAE page table. */
1354 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1355 /** Shw: PAE page table; Gst: 2MB page. */
1356 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1357
1358 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1359 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1360 /** Shw: PAE page directory; Gst: PAE page directory. */
1361 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1362
1363 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1364 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1365 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1366 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1367
1368 /** Shw: Root 32-bit page directory. */
1369 PGMPOOLKIND_ROOT_32BIT_PD,
1370 /** Shw: Root PAE page directory */
1371 PGMPOOLKIND_ROOT_PAE_PD,
1372 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1373 PGMPOOLKIND_ROOT_PDPT,
1374 /** Shw: Root page map level-4 table. */
1375 PGMPOOLKIND_ROOT_PML4,
1376
1377 /** The last valid entry. */
1378 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PML4
1379} PGMPOOLKIND;
1380
1381
1382/**
1383 * The tracking data for a page in the pool.
1384 */
1385typedef struct PGMPOOLPAGE
1386{
1387 /** AVL node code with the (HC) physical address of this page. */
1388 AVLOHCPHYSNODECORE Core;
1389 /** Pointer to the HC mapping of the page. */
1390 R3R0PTRTYPE(void *) pvPageHC;
1391 /** The guest physical address. */
1392 RTGCPHYS GCPhys;
1393 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1394 uint8_t enmKind;
1395 uint8_t bPadding;
1396 /** The index of this page. */
1397 uint16_t idx;
1398 /** The next entry in the list this page currently resides in.
1399 * It's either in the free list or in the GCPhys hash. */
1400 uint16_t iNext;
1401#ifdef PGMPOOL_WITH_USER_TRACKING
1402 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1403 uint16_t iUserHead;
1404 /** The number of present entries. */
1405 uint16_t cPresent;
1406 /** The first entry in the table which is present. */
1407 uint16_t iFirstPresent;
1408#endif
1409#ifdef PGMPOOL_WITH_MONITORING
1410 /** The number of modifications to the monitored page. */
1411 uint16_t cModifications;
1412 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1413 uint16_t iModifiedNext;
1414 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1415 uint16_t iModifiedPrev;
1416 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1417 uint16_t iMonitoredNext;
1418 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1419 uint16_t iMonitoredPrev;
1420#endif
1421#ifdef PGMPOOL_WITH_CACHE
1422 /** The next page in the age list. */
1423 uint16_t iAgeNext;
1424 /** The previous page in the age list. */
1425 uint16_t iAgePrev;
1426#endif /* PGMPOOL_WITH_CACHE */
1427 /** Used to indicate that the page is zeroed. */
1428 bool fZeroed;
1429 /** Used to indicate that a PT has non-global entries. */
1430 bool fSeenNonGlobal;
1431 /** Used to indicate that we're monitoring writes to the guest page. */
1432 bool fMonitored;
1433 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1434 * (All pages are in the age list.) */
1435 bool fCached;
1436 /** This is used by the R3 access handlers when invoked by an async thread.
1437 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1438 bool volatile fReusedFlushPending;
1439 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1440 * In these cases the access handler acts differently and will check
1441 * for mapping conflicts like the normal CR3 handler.
1442 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1443 * replaced by a list of pages which share access handler.
1444 */
1445 bool fCR3Mix;
1446} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1447
1448
1449#ifdef PGMPOOL_WITH_CACHE
1450/** The hash table size. */
1451# define PGMPOOL_HASH_SIZE 0x40
1452/** The hash function. */
1453# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1454#endif
1455
1456
1457/**
1458 * The shadow page pool instance data.
1459 *
1460 * It's all one big allocation made at init time, except for the
1461 * pages that is. The user nodes follows immediatly after the
1462 * page structures.
1463 */
1464typedef struct PGMPOOL
1465{
1466 /** The VM handle - HC Ptr. */
1467 R3R0PTRTYPE(PVM) pVMHC;
1468 /** The VM handle - GC Ptr. */
1469 GCPTRTYPE(PVM) pVMGC;
1470 /** The max pool size. This includes the special IDs. */
1471 uint16_t cMaxPages;
1472 /** The current pool size. */
1473 uint16_t cCurPages;
1474 /** The head of the free page list. */
1475 uint16_t iFreeHead;
1476 /* Padding. */
1477 uint16_t u16Padding;
1478#ifdef PGMPOOL_WITH_USER_TRACKING
1479 /** Head of the chain of free user nodes. */
1480 uint16_t iUserFreeHead;
1481 /** The number of user nodes we've allocated. */
1482 uint16_t cMaxUsers;
1483 /** The number of present page table entries in the entire pool. */
1484 uint32_t cPresent;
1485 /** Pointer to the array of user nodes - GC pointer. */
1486 GCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1487 /** Pointer to the array of user nodes - HC pointer. */
1488 R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1489#endif /* PGMPOOL_WITH_USER_TRACKING */
1490#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1491 /** Head of the chain of free phys ext nodes. */
1492 uint16_t iPhysExtFreeHead;
1493 /** The number of user nodes we've allocated. */
1494 uint16_t cMaxPhysExts;
1495 /** Pointer to the array of physical xref extent - GC pointer. */
1496 GCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1497 /** Pointer to the array of physical xref extent nodes - HC pointer. */
1498 R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1499#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1500#ifdef PGMPOOL_WITH_CACHE
1501 /** Hash table for GCPhys addresses. */
1502 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1503 /** The head of the age list. */
1504 uint16_t iAgeHead;
1505 /** The tail of the age list. */
1506 uint16_t iAgeTail;
1507 /** Set if the cache is enabled. */
1508 bool fCacheEnabled;
1509#endif /* PGMPOOL_WITH_CACHE */
1510#ifdef PGMPOOL_WITH_MONITORING
1511 /** Head of the list of modified pages. */
1512 uint16_t iModifiedHead;
1513 /** The current number of modified pages. */
1514 uint16_t cModifiedPages;
1515 /** Access handler, GC. */
1516 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1517 /** Access handler, R0. */
1518 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1519 /** Access handler, R3. */
1520 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1521 /** The access handler description (HC ptr). */
1522 R3PTRTYPE(const char *) pszAccessHandler;
1523#endif /* PGMPOOL_WITH_MONITORING */
1524 /** The number of pages currently in use. */
1525 uint16_t cUsedPages;
1526#ifdef VBOX_WITH_STATISTICS
1527 /** The high wather mark for cUsedPages. */
1528 uint16_t cUsedPagesHigh;
1529 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1530 /** Profiling pgmPoolAlloc(). */
1531 STAMPROFILEADV StatAlloc;
1532 /** Profiling pgmPoolClearAll(). */
1533 STAMPROFILE StatClearAll;
1534 /** Profiling pgmPoolFlushAllInt(). */
1535 STAMPROFILE StatFlushAllInt;
1536 /** Profiling pgmPoolFlushPage(). */
1537 STAMPROFILE StatFlushPage;
1538 /** Profiling pgmPoolFree(). */
1539 STAMPROFILE StatFree;
1540 /** Profiling time spent zeroing pages. */
1541 STAMPROFILE StatZeroPage;
1542# ifdef PGMPOOL_WITH_USER_TRACKING
1543 /** Profiling of pgmPoolTrackDeref. */
1544 STAMPROFILE StatTrackDeref;
1545 /** Profiling pgmTrackFlushGCPhysPT. */
1546 STAMPROFILE StatTrackFlushGCPhysPT;
1547 /** Profiling pgmTrackFlushGCPhysPTs. */
1548 STAMPROFILE StatTrackFlushGCPhysPTs;
1549 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1550 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1551 /** Number of times we've been out of user records. */
1552 STAMCOUNTER StatTrackFreeUpOneUser;
1553# endif
1554# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1555 /** Profiling deref activity related tracking GC physical pages. */
1556 STAMPROFILE StatTrackDerefGCPhys;
1557 /** Number of linear searches for a HCPhys in the ram ranges. */
1558 STAMCOUNTER StatTrackLinearRamSearches;
1559 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1560 STAMCOUNTER StamTrackPhysExtAllocFailures;
1561# endif
1562# ifdef PGMPOOL_WITH_MONITORING
1563 /** Profiling the GC PT access handler. */
1564 STAMPROFILE StatMonitorGC;
1565 /** Times we've failed interpreting the instruction. */
1566 STAMCOUNTER StatMonitorGCEmulateInstr;
1567 /** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1568 STAMPROFILE StatMonitorGCFlushPage;
1569 /** Times we've detected fork(). */
1570 STAMCOUNTER StatMonitorGCFork;
1571 /** Profiling the GC access we've handled (except REP STOSD). */
1572 STAMPROFILE StatMonitorGCHandled;
1573 /** Times we've failed interpreting a patch code instruction. */
1574 STAMCOUNTER StatMonitorGCIntrFailPatch1;
1575 /** Times we've failed interpreting a patch code instruction during flushing. */
1576 STAMCOUNTER StatMonitorGCIntrFailPatch2;
1577 /** The number of times we've seen rep prefixes we can't handle. */
1578 STAMCOUNTER StatMonitorGCRepPrefix;
1579 /** Profiling the REP STOSD cases we've handled. */
1580 STAMPROFILE StatMonitorGCRepStosd;
1581
1582 /** Profiling the HC PT access handler. */
1583 STAMPROFILE StatMonitorHC;
1584 /** Times we've failed interpreting the instruction. */
1585 STAMCOUNTER StatMonitorHCEmulateInstr;
1586 /** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1587 STAMPROFILE StatMonitorHCFlushPage;
1588 /** Times we've detected fork(). */
1589 STAMCOUNTER StatMonitorHCFork;
1590 /** Profiling the HC access we've handled (except REP STOSD). */
1591 STAMPROFILE StatMonitorHCHandled;
1592 /** The number of times we've seen rep prefixes we can't handle. */
1593 STAMCOUNTER StatMonitorHCRepPrefix;
1594 /** Profiling the REP STOSD cases we've handled. */
1595 STAMPROFILE StatMonitorHCRepStosd;
1596 /** The number of times we're called in an async thread an need to flush. */
1597 STAMCOUNTER StatMonitorHCAsync;
1598 /** The high wather mark for cModifiedPages. */
1599 uint16_t cModifiedPagesHigh;
1600 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1601# endif
1602# ifdef PGMPOOL_WITH_CACHE
1603 /** The number of cache hits. */
1604 STAMCOUNTER StatCacheHits;
1605 /** The number of cache misses. */
1606 STAMCOUNTER StatCacheMisses;
1607 /** The number of times we've got a conflict of 'kind' in the cache. */
1608 STAMCOUNTER StatCacheKindMismatches;
1609 /** Number of times we've been out of pages. */
1610 STAMCOUNTER StatCacheFreeUpOne;
1611 /** The number of cacheable allocations. */
1612 STAMCOUNTER StatCacheCacheable;
1613 /** The number of uncacheable allocations. */
1614 STAMCOUNTER StatCacheUncacheable;
1615# endif
1616#elif HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1617 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1618#endif
1619 /** The AVL tree for looking up a page by its HC physical address. */
1620 AVLOHCPHYSTREE HCPhysTree;
1621 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1622 /** Array of pages. (cMaxPages in length)
1623 * The Id is the index into thist array.
1624 */
1625 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1626} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1627
1628
1629/** @def PGMPOOL_PAGE_2_PTR
1630 * Maps a pool page pool into the current context.
1631 *
1632 * @returns VBox status code.
1633 * @param pVM The VM handle.
1634 * @param pPage The pool page.
1635 *
1636 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1637 * small page window employeed by that function. Be careful.
1638 * @remark There is no need to assert on the result.
1639 */
1640#ifdef IN_GC
1641# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1642#else
1643# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1644#endif
1645
1646
1647/**
1648 * Trees are using self relative offsets as pointers.
1649 * So, all its data, including the root pointer, must be in the heap for HC and GC
1650 * to have the same layout.
1651 */
1652typedef struct PGMTREES
1653{
1654 /** Physical access handlers (AVL range+offsetptr tree). */
1655 AVLROGCPHYSTREE PhysHandlers;
1656 /** Virtual access handlers (AVL range + GC ptr tree). */
1657 AVLROGCPTRTREE VirtHandlers;
1658 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1659 AVLROGCPHYSTREE PhysToVirtHandlers;
1660 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1661 AVLROGCPTRTREE HyperVirtHandlers;
1662} PGMTREES;
1663/** Pointer to PGM trees. */
1664typedef PGMTREES *PPGMTREES;
1665
1666
1667/** @name Paging mode macros
1668 * @{ */
1669#ifdef IN_GC
1670# define PGM_CTX(a,b) a##GC##b
1671# define PGM_CTX_STR(a,b) a "GC" b
1672# define PGM_CTX_DECL(type) PGMGCDECL(type)
1673#else
1674# ifdef IN_RING3
1675# define PGM_CTX(a,b) a##R3##b
1676# define PGM_CTX_STR(a,b) a "R3" b
1677# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1678# else
1679# define PGM_CTX(a,b) a##R0##b
1680# define PGM_CTX_STR(a,b) a "R0" b
1681# define PGM_CTX_DECL(type) PGMDECL(type)
1682# endif
1683#endif
1684
1685#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1686#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1687#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1688#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1689#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1690#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1691#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1692#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1693#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1694#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1695#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1696#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1697#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1698#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1699#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1700#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1701#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1702
1703#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1704#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1705#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1706#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1707#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1708#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1709#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1710#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1711#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1712#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1713#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1714
1715/* Shw_Gst */
1716#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1717#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1718#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1719#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1720#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1721#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1722#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1723#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1724#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1725#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1726#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1727#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1728#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1729#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1730#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1731#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1732#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1733#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1734#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1735#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1736#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1737#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1738#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1739#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1740#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1741#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1742/** @} */
1743
1744/**
1745 * Data for each paging mode.
1746 */
1747typedef struct PGMMODEDATA
1748{
1749 /** The guest mode type. */
1750 uint32_t uGstType;
1751 /** The shadow mode type. */
1752 uint32_t uShwType;
1753
1754 /** @name Function pointers for Shadow paging.
1755 * @{
1756 */
1757 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1758 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1759 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1760 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1761
1762 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1763 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1764
1765 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1766 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1767 /** @} */
1768
1769 /** @name Function pointers for Guest paging.
1770 * @{
1771 */
1772 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1773 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1774 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1775 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1776 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1777 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1778 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1779 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1780 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1781 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1782 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1783 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1784 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1785
1786 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1787 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1788 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1789 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1790 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1791 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1792 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1793 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1794 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1795
1796 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1797 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1798 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1799 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1800 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1801 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1802 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1803 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1804 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1805 /** @} */
1806
1807 /** @name Function pointers for Both Shadow and Guest paging.
1808 * @{
1809 */
1810 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1811 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1812 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1813 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1814 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1815 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1816 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1817#ifdef VBOX_STRICT
1818 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1819#endif
1820
1821 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1822 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1823 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1824 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1825 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1826 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1827#ifdef VBOX_STRICT
1828 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1829#endif
1830
1831 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1832 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1833 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1834 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1835 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1836 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1837#ifdef VBOX_STRICT
1838 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1839#endif
1840 /** @} */
1841} PGMMODEDATA, *PPGMMODEDATA;
1842
1843
1844
1845/**
1846 * Converts a PGM pointer into a VM pointer.
1847 * @returns Pointer to the VM structure the PGM is part of.
1848 * @param pPGM Pointer to PGM instance data.
1849 */
1850#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1851
1852/**
1853 * PGM Data (part of VM)
1854 */
1855typedef struct PGM
1856{
1857 /** Offset to the VM structure. */
1858 RTINT offVM;
1859
1860 /*
1861 * This will be redefined at least two more times before we're done, I'm sure.
1862 * The current code is only to get on with the coding.
1863 * - 2004-06-10: initial version, bird.
1864 * - 2004-07-02: 1st time, bird.
1865 * - 2004-10-18: 2nd time, bird.
1866 * - 2005-07-xx: 3rd time, bird.
1867 */
1868
1869 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1870 GCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1871 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1872 GCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1873
1874 /** The host paging mode. (This is what SUPLib reports.) */
1875 SUPPAGINGMODE enmHostMode;
1876 /** The shadow paging mode. */
1877 PGMMODE enmShadowMode;
1878 /** The guest paging mode. */
1879 PGMMODE enmGuestMode;
1880
1881 /** The current physical address representing in the guest CR3 register. */
1882 RTGCPHYS GCPhysCR3;
1883 /** Pointer to the 5 page CR3 content mapping.
1884 * The first page is always the CR3 (in some form) while the 4 other pages
1885 * are used of the PDs in PAE mode. */
1886 RTGCPTR GCPtrCR3Mapping;
1887#if HC_ARCH_BITS == 64
1888 uint32_t u32Alignment;
1889#endif
1890 /** The physical address of the currently monitored guest CR3 page.
1891 * When this value is NIL_RTGCPHYS no page is being monitored. */
1892 RTGCPHYS GCPhysGstCR3Monitored;
1893
1894 /** @name 32-bit Guest Paging.
1895 * @{ */
1896 /** The guest's page directory, HC pointer. */
1897 R3R0PTRTYPE(PX86PD) pGuestPDHC;
1898 /** The guest's page directory, static GC mapping. */
1899 GCPTRTYPE(PX86PD) pGuestPDGC;
1900 /** @} */
1901
1902 /** @name PAE Guest Paging.
1903 * @{ */
1904 /** The guest's page directory pointer table, static GC mapping. */
1905 GCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
1906 /** The guest's page directory pointer table, HC pointer. */
1907 R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1908 /** The guest's page directories, HC pointers.
1909 * These are individual pointers and don't have to be adjecent.
1910 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1911 R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1912 /** The guest's page directories, static GC mapping.
1913 * Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1914 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1915 GCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1916 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1917 RTGCPHYS aGCPhysGstPaePDs[4];
1918 /** The physical addresses of the monitored guest page directories (PAE). */
1919 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1920 /** @} */
1921
1922 /** @name AMD64 Guest Paging.
1923 * @{ */
1924 /** The guest's page directory pointer table, HC pointer. */
1925 R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
1926 /** @} */
1927
1928 /** @name 32-bit Shadow Paging
1929 * @{ */
1930 /** The 32-Bit PD - HC Ptr. */
1931 R3R0PTRTYPE(PX86PD) pHC32BitPD;
1932 /** The 32-Bit PD - GC Ptr. */
1933 GCPTRTYPE(PX86PD) pGC32BitPD;
1934#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1935 uint32_t u32Padding1; /**< alignment padding. */
1936#endif
1937 /** The Physical Address (HC) of the 32-Bit PD. */
1938 RTHCPHYS HCPhys32BitPD;
1939 /** @} */
1940
1941 /** @name PAE Shadow Paging
1942 * @{ */
1943 /** The four PDs for the low 4GB - HC Ptr.
1944 * Even though these are 4 pointers, what they point at is a single table.
1945 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
1946 R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
1947 /** The four PDs for the low 4GB - GC Ptr.
1948 * Same kind of mapping as apHCPaePDs. */
1949 GCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
1950 /** The Physical Address (HC) of the four PDs for the low 4GB.
1951 * These are *NOT* 4 contiguous pages. */
1952 RTHCPHYS aHCPhysPaePDs[4];
1953 /** The PAE PDP - HC Ptr. */
1954 R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
1955 /** The Physical Address (HC) of the PAE PDPT. */
1956 RTHCPHYS HCPhysPaePDPT;
1957 /** The PAE PDPT - GC Ptr. */
1958 GCPTRTYPE(PX86PDPT) pGCPaePDPT;
1959 /** @} */
1960
1961 /** @name AMD64 Shadow Paging
1962 * Extends PAE Paging.
1963 * @{ */
1964#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1965 RTGCPTR alignment5; /**< structure size alignment. */
1966#endif
1967 /** The Page Map Level 4 table - HC Ptr. */
1968 R3R0PTRTYPE(PX86PML4) pHCPaePML4;
1969 /** The Physical Address (HC) of the Page Map Level 4 table. */
1970 RTHCPHYS HCPhysPaePML4;
1971 /** @}*/
1972
1973 /** @name Function pointers for Shadow paging.
1974 * @{
1975 */
1976 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1977 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1978 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1979 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1980
1981 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1982 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1983
1984 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1985 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1986
1987 /** @} */
1988
1989 /** @name Function pointers for Guest paging.
1990 * @{
1991 */
1992 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1993 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1994 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1995 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1996 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1997 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1998 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1999 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2000 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2001 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2002 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2003 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2004 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2005
2006 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2007 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2008 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2009 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2010 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
2011 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2012 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
2013 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
2014 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
2015#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2016 RTGCPTR alignment3; /**< structure size alignment. */
2017#endif
2018
2019 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2020 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2021 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2022 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2023 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2024 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2025 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2026 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2027 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2028 /** @} */
2029
2030 /** @name Function pointers for Both Shadow and Guest paging.
2031 * @{
2032 */
2033 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2034 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2035 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2036 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2037 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2038 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2039 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2040 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2041
2042 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2043 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2044 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2045 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2046 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2047 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2048 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2049
2050 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2051 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2052 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2053 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2054 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2055 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2056 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2057#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2058 RTGCPTR alignment2; /**< structure size alignment. */
2059#endif
2060 /** @} */
2061
2062 /** Pointer to SHW+GST mode data (function pointers).
2063 * The index into this table is made up from */
2064 R3PTRTYPE(PPGMMODEDATA) paModeData;
2065
2066 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2067 * This is sorted by physical address and contains no overlapping ranges. */
2068 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2069 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2070 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2071 /** GC pointer corresponding to PGM::pRamRangesR3. */
2072 GCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
2073 /** The configured RAM size. */
2074 RTUINT cbRamSize;
2075
2076 /** Pointer to the list of ROM ranges - for R3.
2077 * This is sorted by physical address and contains no overlapping ranges. */
2078 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2079 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2080 R0PTRTYPE(PPGMRAMRANGE) pRomRangesR0;
2081 /** GC pointer corresponding to PGM::pRomRangesR3. */
2082 GCPTRTYPE(PPGMRAMRANGE) pRomRangesGC;
2083 /** Alignment padding. */
2084 RTGCPTR GCPtrPadding2;
2085
2086 /** Pointer to the list of MMIO2 ranges - for R3.
2087 * Registration order. */
2088 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2089
2090 /** PGM offset based trees - HC Ptr. */
2091 R3R0PTRTYPE(PPGMTREES) pTreesHC;
2092 /** PGM offset based trees - GC Ptr. */
2093 GCPTRTYPE(PPGMTREES) pTreesGC;
2094
2095 /** Linked list of GC mappings - for GC.
2096 * The list is sorted ascending on address.
2097 */
2098 GCPTRTYPE(PPGMMAPPING) pMappingsGC;
2099 /** Linked list of GC mappings - for HC.
2100 * The list is sorted ascending on address.
2101 */
2102 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2103 /** Linked list of GC mappings - for R0.
2104 * The list is sorted ascending on address.
2105 */
2106 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2107
2108 /** If set no conflict checks are required. (boolean) */
2109 bool fMappingsFixed;
2110 /** If set, then no mappings are put into the shadow page table. (boolean) */
2111 bool fDisableMappings;
2112 /** Size of fixed mapping */
2113 uint32_t cbMappingFixed;
2114 /** Base address (GC) of fixed mapping */
2115 RTGCPTR GCPtrMappingFixed;
2116#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2117 uint32_t u32Padding0; /**< alignment padding. */
2118#endif
2119
2120
2121 /** @name Intermediate Context
2122 * @{ */
2123 /** Pointer to the intermediate page directory - Normal. */
2124 R3PTRTYPE(PX86PD) pInterPD;
2125 /** Pointer to the intermedate page tables - Normal.
2126 * There are two page tables, one for the identity mapping and one for
2127 * the host context mapping (of the core code). */
2128 R3PTRTYPE(PX86PT) apInterPTs[2];
2129 /** Pointer to the intermedate page tables - PAE. */
2130 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2131 /** Pointer to the intermedate page directory - PAE. */
2132 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2133 /** Pointer to the intermedate page directory - PAE. */
2134 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2135 /** Pointer to the intermedate page-map level 4 - AMD64. */
2136 R3PTRTYPE(PX86PML4) pInterPaePML4;
2137 /** Pointer to the intermedate page directory - AMD64. */
2138 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2139 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2140 RTHCPHYS HCPhysInterPD;
2141 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2142 RTHCPHYS HCPhysInterPaePDPT;
2143 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2144 RTHCPHYS HCPhysInterPaePML4;
2145 /** @} */
2146
2147 /** Base address of the dynamic page mapping area.
2148 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2149 */
2150 GCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2151 /** The index of the last entry used in the dynamic page mapping area. */
2152 RTUINT iDynPageMapLast;
2153 /** Cache containing the last entries in the dynamic page mapping area.
2154 * The cache size is covering half of the mapping area. */
2155 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2156
2157 /** A20 gate mask.
2158 * Our current approach to A20 emulation is to let REM do it and don't bother
2159 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2160 * But whould need arrise, we'll subject physical addresses to this mask. */
2161 RTGCPHYS GCPhysA20Mask;
2162 /** A20 gate state - boolean! */
2163 RTUINT fA20Enabled;
2164
2165 /** What needs syncing (PGM_SYNC_*).
2166 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2167 * PGMFlushTLB, and PGMR3Load. */
2168 RTUINT fSyncFlags;
2169
2170 /** PGM critical section.
2171 * This protects the physical & virtual access handlers, ram ranges,
2172 * and the page flag updating (some of it anyway).
2173 */
2174 PDMCRITSECT CritSect;
2175
2176 /** Shadow Page Pool - HC Ptr. */
2177 R3R0PTRTYPE(PPGMPOOL) pPoolHC;
2178 /** Shadow Page Pool - GC Ptr. */
2179 GCPTRTYPE(PPGMPOOL) pPoolGC;
2180
2181 /** We're not in a state which permits writes to guest memory.
2182 * (Only used in strict builds.) */
2183 bool fNoMorePhysWrites;
2184
2185 /** Flush the cache on the next access. */
2186 bool fPhysCacheFlushPending;
2187/** @todo r=bird: Fix member names!*/
2188 /** PGMPhysRead cache */
2189 PGMPHYSCACHE pgmphysreadcache;
2190 /** PGMPhysWrite cache */
2191 PGMPHYSCACHE pgmphyswritecache;
2192
2193 /**
2194 * Data associated with managing the ring-3 mappings of the allocation chunks.
2195 */
2196 struct
2197 {
2198 /** The chunk tree, ordered by chunk id. */
2199 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2200 /** The chunk mapping TLB. */
2201 PGMCHUNKR3MAPTLB Tlb;
2202 /** The number of mapped chunks. */
2203 uint32_t c;
2204 /** The maximum number of mapped chunks.
2205 * @cfgm PGM/MaxRing3Chunks */
2206 uint32_t cMax;
2207 /** The chunk age tree, ordered by ageing sequence number. */
2208 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2209 /** The current time. */
2210 uint32_t iNow;
2211 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2212 uint32_t AgeingCountdown;
2213 } ChunkR3Map;
2214
2215 /**
2216 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2217 */
2218 PGMPAGER3MAPTLB PhysTlbHC;
2219
2220 /** @name The zero page.
2221 * @{ */
2222 /** The host physical address of the zero page. */
2223 RTHCPHYS HCPhysZeroPg;
2224 /** The ring-3 mapping of the zero page. */
2225 RTR3PTR pvZeroPgR3;
2226 /** The ring-0 mapping of the zero page. */
2227 RTR0PTR pvZeroPgR0;
2228 /** The GC mapping of the zero page. */
2229 RTGCPTR pvZeroPgGC;
2230#if GC_ARCH_BITS != 32
2231 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2232#endif
2233 /** @}*/
2234
2235 /** The number of handy pages. */
2236 uint32_t cHandyPages;
2237 /**
2238 * Array of handy pages.
2239 *
2240 * This array is used in a two way communication between pgmPhysAllocPage
2241 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2242 * an intermediary.
2243 *
2244 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2245 * (The current size of 32 pages, means 128 KB of handy memory.)
2246 */
2247 GMMPAGEDESC aHandyPages[32];
2248
2249 /** @name Release Statistics
2250 * @{ */
2251 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2252 uint32_t cPrivatePages; /**< The number of private pages. */
2253 uint32_t cSharedPages; /**< The number of shared pages. */
2254 uint32_t cZeroPages; /**< The number of zero backed pages. */
2255 /** The number of times the guest has switched mode since last reset or statistics reset. */
2256 STAMCOUNTER cGuestModeChanges;
2257 /** @} */
2258
2259#ifdef VBOX_WITH_STATISTICS
2260 /** GC: Which statistic this \#PF should be attributed to. */
2261 GCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
2262 RTGCPTR padding0;
2263 /** HC: Which statistic this \#PF should be attributed to. */
2264 R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
2265 RTHCPTR padding1;
2266 STAMPROFILE StatGCTrap0e; /**< GC: PGMGCTrap0eHandler() profiling. */
2267 STAMPROFILE StatTrap0eCSAM; /**< Profiling of the Trap0eHandler body when the cause is CSAM. */
2268 STAMPROFILE StatTrap0eDirtyAndAccessedBits; /**< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2269 STAMPROFILE StatTrap0eGuestTrap; /**< Profiling of the Trap0eHandler body when the cause is a guest trap. */
2270 STAMPROFILE StatTrap0eHndPhys; /**< Profiling of the Trap0eHandler body when the cause is a physical handler. */
2271 STAMPROFILE StatTrap0eHndVirt; /**< Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2272 STAMPROFILE StatTrap0eHndUnhandled; /**< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2273 STAMPROFILE StatTrap0eMisc; /**< Profiling of the Trap0eHandler body when the cause is not known. */
2274 STAMPROFILE StatTrap0eOutOfSync; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2275 STAMPROFILE StatTrap0eOutOfSyncHndPhys; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2276 STAMPROFILE StatTrap0eOutOfSyncHndVirt; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2277 STAMPROFILE StatTrap0eOutOfSyncObsHnd; /**< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2278 STAMPROFILE StatTrap0eSyncPT; /**< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2279
2280 STAMCOUNTER StatTrap0eMapHandler; /**< Number of traps due to access handlers in mappings. */
2281 STAMCOUNTER StatGCTrap0eConflicts; /**< GC: The number of times \#PF was caused by an undetected conflict. */
2282
2283 STAMCOUNTER StatGCTrap0eUSNotPresentRead;
2284 STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
2285 STAMCOUNTER StatGCTrap0eUSWrite;
2286 STAMCOUNTER StatGCTrap0eUSReserved;
2287 STAMCOUNTER StatGCTrap0eUSNXE;
2288 STAMCOUNTER StatGCTrap0eUSRead;
2289
2290 STAMCOUNTER StatGCTrap0eSVNotPresentRead;
2291 STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
2292 STAMCOUNTER StatGCTrap0eSVWrite;
2293 STAMCOUNTER StatGCTrap0eSVReserved;
2294 STAMCOUNTER StatGCTrap0eSNXE;
2295
2296 STAMCOUNTER StatTrap0eWPEmulGC;
2297 STAMCOUNTER StatTrap0eWPEmulR3;
2298
2299 STAMCOUNTER StatGCTrap0eUnhandled;
2300 STAMCOUNTER StatGCTrap0eMap;
2301
2302 /** GC: PGMSyncPT() profiling. */
2303 STAMPROFILE StatGCSyncPT;
2304 /** GC: The number of times PGMSyncPT() needed to allocate page tables. */
2305 STAMCOUNTER StatGCSyncPTAlloc;
2306 /** GC: The number of times PGMSyncPT() detected conflicts. */
2307 STAMCOUNTER StatGCSyncPTConflict;
2308 /** GC: The number of times PGMSyncPT() failed. */
2309 STAMCOUNTER StatGCSyncPTFailed;
2310 /** GC: PGMGCInvalidatePage() profiling. */
2311 STAMPROFILE StatGCInvalidatePage;
2312 /** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
2313 STAMCOUNTER StatGCInvalidatePage4KBPages;
2314 /** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
2315 STAMCOUNTER StatGCInvalidatePage4MBPages;
2316 /** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
2317 STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
2318 /** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
2319 STAMCOUNTER StatGCInvalidatePagePDNAs;
2320 /** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
2321 STAMCOUNTER StatGCInvalidatePagePDNPs;
2322 /** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
2323 STAMCOUNTER StatGCInvalidatePagePDMappings;
2324 /** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2325 STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
2326 /** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2327 STAMCOUNTER StatGCInvalidatePageSkipped;
2328 /** GC: The number of times user page is out of sync was detected in GC. */
2329 STAMCOUNTER StatGCPageOutOfSyncUser;
2330 /** GC: The number of times supervisor page is out of sync was detected in GC. */
2331 STAMCOUNTER StatGCPageOutOfSyncSupervisor;
2332 /** GC: The number of dynamic page mapping cache hits */
2333 STAMCOUNTER StatDynMapCacheMisses;
2334 /** GC: The number of dynamic page mapping cache misses */
2335 STAMCOUNTER StatDynMapCacheHits;
2336 /** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
2337 STAMCOUNTER StatGCGuestCR3WriteHandled;
2338 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
2339 STAMCOUNTER StatGCGuestCR3WriteUnhandled;
2340 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
2341 STAMCOUNTER StatGCGuestCR3WriteConflict;
2342 /** GC: Number of out-of-sync handled pages. */
2343 STAMCOUNTER StatHandlersOutOfSync;
2344 /** GC: Number of traps due to physical access handlers. */
2345 STAMCOUNTER StatHandlersPhysical;
2346 /** GC: Number of traps due to virtual access handlers. */
2347 STAMCOUNTER StatHandlersVirtual;
2348 /** GC: Number of traps due to virtual access handlers found by physical address. */
2349 STAMCOUNTER StatHandlersVirtualByPhys;
2350 /** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2351 STAMCOUNTER StatHandlersVirtualUnmarked;
2352 /** GC: Number of traps due to access outside range of monitored page(s). */
2353 STAMCOUNTER StatHandlersUnhandled;
2354 /** GC: Number of traps due to access to invalid physical memory. */
2355 STAMCOUNTER StatHandlersInvalid;
2356
2357 /** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
2358 STAMCOUNTER StatGCGuestROMWriteHandled;
2359 /** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
2360 STAMCOUNTER StatGCGuestROMWriteUnhandled;
2361
2362 /** HC: PGMR3InvalidatePage() profiling. */
2363 STAMPROFILE StatHCInvalidatePage;
2364 /** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
2365 STAMCOUNTER StatHCInvalidatePage4KBPages;
2366 /** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
2367 STAMCOUNTER StatHCInvalidatePage4MBPages;
2368 /** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
2369 STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
2370 /** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
2371 STAMCOUNTER StatHCInvalidatePagePDNAs;
2372 /** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
2373 STAMCOUNTER StatHCInvalidatePagePDNPs;
2374 /** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
2375 STAMCOUNTER StatHCInvalidatePagePDMappings;
2376 /** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2377 STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
2378 /** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2379 STAMCOUNTER StatHCInvalidatePageSkipped;
2380 /** HC: PGMR3SyncPT() profiling. */
2381 STAMPROFILE StatHCSyncPT;
2382 /** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2383 STAMPROFILE StatHCResolveConflict;
2384 /** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2385 STAMCOUNTER StatHCDetectedConflicts;
2386 /** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2387 STAMCOUNTER StatHCGuestPDWrite;
2388 /** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2389 STAMCOUNTER StatHCGuestPDWriteConflict;
2390
2391 /** HC: The number of pages marked not present for accessed bit emulation. */
2392 STAMCOUNTER StatHCAccessedPage;
2393 /** HC: The number of pages marked read-only for dirty bit tracking. */
2394 STAMCOUNTER StatHCDirtyPage;
2395 /** HC: The number of pages marked read-only for dirty bit tracking. */
2396 STAMCOUNTER StatHCDirtyPageBig;
2397 /** HC: The number of traps generated for dirty bit tracking. */
2398 STAMCOUNTER StatHCDirtyPageTrap;
2399 /** HC: The number of pages already dirty or readonly. */
2400 STAMCOUNTER StatHCDirtyPageSkipped;
2401
2402 /** GC: The number of pages marked not present for accessed bit emulation. */
2403 STAMCOUNTER StatGCAccessedPage;
2404 /** GC: The number of pages marked read-only for dirty bit tracking. */
2405 STAMCOUNTER StatGCDirtyPage;
2406 /** GC: The number of pages marked read-only for dirty bit tracking. */
2407 STAMCOUNTER StatGCDirtyPageBig;
2408 /** GC: The number of traps generated for dirty bit tracking. */
2409 STAMCOUNTER StatGCDirtyPageTrap;
2410 /** GC: The number of pages already dirty or readonly. */
2411 STAMCOUNTER StatGCDirtyPageSkipped;
2412 /** GC: The number of pages marked dirty because of write accesses. */
2413 STAMCOUNTER StatGCDirtiedPage;
2414 /** GC: The number of pages already marked dirty because of write accesses. */
2415 STAMCOUNTER StatGCPageAlreadyDirty;
2416 /** GC: The number of real pages faults during dirty bit tracking. */
2417 STAMCOUNTER StatGCDirtyTrackRealPF;
2418
2419 /** GC: Profiling of the PGMTrackDirtyBit() body */
2420 STAMPROFILE StatGCDirtyBitTracking;
2421 /** HC: Profiling of the PGMTrackDirtyBit() body */
2422 STAMPROFILE StatHCDirtyBitTracking;
2423
2424 /** GC: Profiling of the PGMGstModifyPage() body */
2425 STAMPROFILE StatGCGstModifyPage;
2426 /** HC: Profiling of the PGMGstModifyPage() body */
2427 STAMPROFILE StatHCGstModifyPage;
2428
2429 /** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2430 STAMCOUNTER StatGCSyncPagePDNAs;
2431 /** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2432 STAMCOUNTER StatGCSyncPagePDOutOfSync;
2433 /** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2434 STAMCOUNTER StatHCSyncPagePDNAs;
2435 /** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2436 STAMCOUNTER StatHCSyncPagePDOutOfSync;
2437
2438 STAMCOUNTER StatSynPT4kGC;
2439 STAMCOUNTER StatSynPT4kHC;
2440 STAMCOUNTER StatSynPT4MGC;
2441 STAMCOUNTER StatSynPT4MHC;
2442
2443 /** Profiling of the PGMFlushTLB() body. */
2444 STAMPROFILE StatFlushTLB;
2445 /** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2446 STAMCOUNTER StatFlushTLBNewCR3;
2447 /** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2448 STAMCOUNTER StatFlushTLBNewCR3Global;
2449 /** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2450 STAMCOUNTER StatFlushTLBSameCR3;
2451 /** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2452 STAMCOUNTER StatFlushTLBSameCR3Global;
2453
2454 STAMPROFILE StatGCSyncCR3; /**< GC: PGMSyncCR3() profiling. */
2455 STAMPROFILE StatGCSyncCR3Handlers; /**< GC: Profiling of the PGMSyncCR3() update handler section. */
2456 STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /**< GC: Profiling of the virtual handler resets. */
2457 STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /**< GC: Profiling of the virtual handler updates. */
2458 STAMCOUNTER StatGCSyncCR3Global; /**< GC: The number of global CR3 syncs. */
2459 STAMCOUNTER StatGCSyncCR3NotGlobal; /**< GC: The number of non-global CR3 syncs. */
2460 STAMCOUNTER StatGCSyncCR3DstFreed; /**< GC: The number of times we've had to free a shadow entry. */
2461 STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /**< GC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2462 STAMCOUNTER StatGCSyncCR3DstNotPresent; /**< GC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2463 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /**< GC: The number of times a global page directory wasn't flushed. */
2464 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /**< GC: The number of times a page table with only global entries wasn't flushed. */
2465 STAMCOUNTER StatGCSyncCR3DstCacheHit; /**< GC: The number of times we got some kind of cache hit on a page table. */
2466
2467 STAMPROFILE StatHCSyncCR3; /**< HC: PGMSyncCR3() profiling. */
2468 STAMPROFILE StatHCSyncCR3Handlers; /**< HC: Profiling of the PGMSyncCR3() update handler section. */
2469 STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /**< HC: Profiling of the virtual handler resets. */
2470 STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /**< HC: Profiling of the virtual handler updates. */
2471 STAMCOUNTER StatHCSyncCR3Global; /**< HC: The number of global CR3 syncs. */
2472 STAMCOUNTER StatHCSyncCR3NotGlobal; /**< HC: The number of non-global CR3 syncs. */
2473 STAMCOUNTER StatHCSyncCR3DstFreed; /**< HC: The number of times we've had to free a shadow entry. */
2474 STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /**< HC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2475 STAMCOUNTER StatHCSyncCR3DstNotPresent; /**< HC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2476 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /**< HC: The number of times a global page directory wasn't flushed. */
2477 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /**< HC: The number of times a page table with only global entries wasn't flushed. */
2478 STAMCOUNTER StatHCSyncCR3DstCacheHit; /**< HC: The number of times we got some kind of cache hit on a page table. */
2479
2480 /** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2481 STAMPROFILE StatVirtHandleSearchByPhysGC;
2482 /** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2483 STAMPROFILE StatVirtHandleSearchByPhysHC;
2484 /** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2485 STAMCOUNTER StatHandlePhysicalReset;
2486
2487 STAMPROFILE StatCheckPageFault;
2488 STAMPROFILE StatLazySyncPT;
2489 STAMPROFILE StatMapping;
2490 STAMPROFILE StatOutOfSync;
2491 STAMPROFILE StatHandlers;
2492 STAMPROFILE StatEIPHandlers;
2493 STAMPROFILE StatHCPrefetch;
2494
2495# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2496 /** The number of first time shadowings. */
2497 STAMCOUNTER StatTrackVirgin;
2498 /** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2499 STAMCOUNTER StatTrackAliased;
2500 /** The number of times we're tracking using cRef2. */
2501 STAMCOUNTER StatTrackAliasedMany;
2502 /** The number of times we're hitting pages which has overflowed cRef2. */
2503 STAMCOUNTER StatTrackAliasedLots;
2504 /** The number of times the extent list grows to long. */
2505 STAMCOUNTER StatTrackOverflows;
2506 /** Profiling of SyncPageWorkerTrackDeref (expensive). */
2507 STAMPROFILE StatTrackDeref;
2508# endif
2509
2510 /** Ring-3/0 page mapper TLB hits. */
2511 STAMCOUNTER StatPageHCMapTlbHits;
2512 /** Ring-3/0 page mapper TLB misses. */
2513 STAMCOUNTER StatPageHCMapTlbMisses;
2514 /** Ring-3/0 chunk mapper TLB hits. */
2515 STAMCOUNTER StatChunkR3MapTlbHits;
2516 /** Ring-3/0 chunk mapper TLB misses. */
2517 STAMCOUNTER StatChunkR3MapTlbMisses;
2518 /** Times a shared page has been replaced by a private one. */
2519 STAMCOUNTER StatPageReplaceShared;
2520 /** Times the zero page has been replaced by a private one. */
2521 STAMCOUNTER StatPageReplaceZero;
2522 /** The number of times we've executed GMMR3AllocateHandyPages. */
2523 STAMCOUNTER StatPageHandyAllocs;
2524
2525 /** Allocated mbs of guest ram */
2526 STAMCOUNTER StatDynRamTotal;
2527 /** Nr of pgmr3PhysGrowRange calls. */
2528 STAMCOUNTER StatDynRamGrow;
2529
2530 STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2531 STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2532 STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2533#endif
2534} PGM, *PPGM;
2535
2536
2537/** @name PGM::fSyncFlags Flags
2538 * @{
2539 */
2540/** Updates the virtual access handler state bit in PGMPAGE. */
2541#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2542/** Always sync CR3. */
2543#define PGM_SYNC_ALWAYS RT_BIT(1)
2544/** Check monitoring on next CR3 (re)load and invalidate page. */
2545#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2546/** Clear the page pool (a light weight flush). */
2547#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2548/** @} */
2549
2550
2551__BEGIN_DECLS
2552
2553int pgmLock(PVM pVM);
2554void pgmUnlock(PVM pVM);
2555
2556PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2557PGMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2558int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
2559
2560int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2561int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2562PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2563void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2564DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2565
2566void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2567int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2568DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2569#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2570void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2571#else
2572# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2573#endif
2574DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2575
2576
2577void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2578int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2579int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2580int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2581#ifdef IN_RING3
2582int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2583int pgmR3PhysRamReset(PVM pVM);
2584int pgmR3PhysRomReset(PVM pVM);
2585#ifndef VBOX_WITH_NEW_PHYS_CODE
2586int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2587#endif
2588
2589int pgmR3PoolInit(PVM pVM);
2590void pgmR3PoolRelocate(PVM pVM);
2591void pgmR3PoolReset(PVM pVM);
2592
2593#endif /* IN_RING3 */
2594#ifdef IN_GC
2595void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2596#endif
2597int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage);
2598PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2599void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint16_t iUserTable);
2600void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable);
2601int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2602void pgmPoolFlushAll(PVM pVM);
2603void pgmPoolClearAll(PVM pVM);
2604void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2605void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2606int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2607PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2608void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2609void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2610uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2611void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2612#ifdef PGMPOOL_WITH_MONITORING
2613# ifdef IN_RING3
2614void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2615# else
2616void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2617# endif
2618int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2619void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2620void pgmPoolMonitorModifiedClearAll(PVM pVM);
2621int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2622int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2623#endif
2624
2625__END_DECLS
2626
2627
2628/**
2629 * Gets the PGMRAMRANGE structure for a guest page.
2630 *
2631 * @returns Pointer to the RAM range on success.
2632 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2633 *
2634 * @param pPGM PGM handle.
2635 * @param GCPhys The GC physical address.
2636 */
2637DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2638{
2639 /*
2640 * Optimize for the first range.
2641 */
2642 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2643 RTGCPHYS off = GCPhys - pRam->GCPhys;
2644 if (RT_UNLIKELY(off >= pRam->cb))
2645 {
2646 do
2647 {
2648 pRam = CTXALLSUFF(pRam->pNext);
2649 if (RT_UNLIKELY(!pRam))
2650 break;
2651 off = GCPhys - pRam->GCPhys;
2652 } while (off >= pRam->cb);
2653 }
2654 return pRam;
2655}
2656
2657
2658/**
2659 * Gets the PGMPAGE structure for a guest page.
2660 *
2661 * @returns Pointer to the page on success.
2662 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2663 *
2664 * @param pPGM PGM handle.
2665 * @param GCPhys The GC physical address.
2666 */
2667DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2668{
2669 /*
2670 * Optimize for the first range.
2671 */
2672 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2673 RTGCPHYS off = GCPhys - pRam->GCPhys;
2674 if (RT_UNLIKELY(off >= pRam->cb))
2675 {
2676 do
2677 {
2678 pRam = CTXALLSUFF(pRam->pNext);
2679 if (RT_UNLIKELY(!pRam))
2680 return NULL;
2681 off = GCPhys - pRam->GCPhys;
2682 } while (off >= pRam->cb);
2683 }
2684 return &pRam->aPages[off >> PAGE_SHIFT];
2685}
2686
2687
2688/**
2689 * Gets the PGMPAGE structure for a guest page.
2690 *
2691 * Old Phys code: Will make sure the page is present.
2692 *
2693 * @returns VBox status code.
2694 * @retval VINF_SUCCESS and a valid *ppPage on success.
2695 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2696 *
2697 * @param pPGM PGM handle.
2698 * @param GCPhys The GC physical address.
2699 * @param ppPage Where to store the page poitner on success.
2700 */
2701DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2702{
2703 /*
2704 * Optimize for the first range.
2705 */
2706 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2707 RTGCPHYS off = GCPhys - pRam->GCPhys;
2708 if (RT_UNLIKELY(off >= pRam->cb))
2709 {
2710 do
2711 {
2712 pRam = CTXALLSUFF(pRam->pNext);
2713 if (RT_UNLIKELY(!pRam))
2714 {
2715 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2716 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2717 }
2718 off = GCPhys - pRam->GCPhys;
2719 } while (off >= pRam->cb);
2720 }
2721 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2722#ifndef VBOX_WITH_NEW_PHYS_CODE
2723
2724 /*
2725 * Make sure it's present.
2726 */
2727 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2728 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2729 {
2730#ifdef IN_RING3
2731 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2732#else
2733 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2734#endif
2735 if (VBOX_FAILURE(rc))
2736 {
2737 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2738 return rc;
2739 }
2740 Assert(rc == VINF_SUCCESS);
2741 }
2742#endif
2743 return VINF_SUCCESS;
2744}
2745
2746
2747
2748
2749/**
2750 * Gets the PGMPAGE structure for a guest page.
2751 *
2752 * Old Phys code: Will make sure the page is present.
2753 *
2754 * @returns VBox status code.
2755 * @retval VINF_SUCCESS and a valid *ppPage on success.
2756 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2757 *
2758 * @param pPGM PGM handle.
2759 * @param GCPhys The GC physical address.
2760 * @param ppPage Where to store the page poitner on success.
2761 * @param ppRamHint Where to read and store the ram list hint.
2762 * The caller initializes this to NULL before the call.
2763 */
2764DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2765{
2766 RTGCPHYS off;
2767 PPGMRAMRANGE pRam = *ppRamHint;
2768 if ( !pRam
2769 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2770 {
2771 pRam = CTXALLSUFF(pPGM->pRamRanges);
2772 off = GCPhys - pRam->GCPhys;
2773 if (RT_UNLIKELY(off >= pRam->cb))
2774 {
2775 do
2776 {
2777 pRam = CTXALLSUFF(pRam->pNext);
2778 if (RT_UNLIKELY(!pRam))
2779 {
2780 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2781 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2782 }
2783 off = GCPhys - pRam->GCPhys;
2784 } while (off >= pRam->cb);
2785 }
2786 *ppRamHint = pRam;
2787 }
2788 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2789#ifndef VBOX_WITH_NEW_PHYS_CODE
2790
2791 /*
2792 * Make sure it's present.
2793 */
2794 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2795 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2796 {
2797#ifdef IN_RING3
2798 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2799#else
2800 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2801#endif
2802 if (VBOX_FAILURE(rc))
2803 {
2804 *ppPage = NULL; /* Shut up annoying smart ass. */
2805 return rc;
2806 }
2807 Assert(rc == VINF_SUCCESS);
2808 }
2809#endif
2810 return VINF_SUCCESS;
2811}
2812
2813
2814/**
2815 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2816 *
2817 * @returns Pointer to the page on success.
2818 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2819 *
2820 * @param pPGM PGM handle.
2821 * @param GCPhys The GC physical address.
2822 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
2823 */
2824DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2825{
2826 /*
2827 * Optimize for the first range.
2828 */
2829 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2830 RTGCPHYS off = GCPhys - pRam->GCPhys;
2831 if (RT_UNLIKELY(off >= pRam->cb))
2832 {
2833 do
2834 {
2835 pRam = CTXALLSUFF(pRam->pNext);
2836 if (RT_UNLIKELY(!pRam))
2837 return NULL;
2838 off = GCPhys - pRam->GCPhys;
2839 } while (off >= pRam->cb);
2840 }
2841 *ppRam = pRam;
2842 return &pRam->aPages[off >> PAGE_SHIFT];
2843}
2844
2845
2846
2847
2848/**
2849 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2850 *
2851 * @returns Pointer to the page on success.
2852 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2853 *
2854 * @param pPGM PGM handle.
2855 * @param GCPhys The GC physical address.
2856 * @param ppPage Where to store the pointer to the PGMPAGE structure.
2857 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2858 */
2859DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2860{
2861 /*
2862 * Optimize for the first range.
2863 */
2864 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2865 RTGCPHYS off = GCPhys - pRam->GCPhys;
2866 if (RT_UNLIKELY(off >= pRam->cb))
2867 {
2868 do
2869 {
2870 pRam = CTXALLSUFF(pRam->pNext);
2871 if (RT_UNLIKELY(!pRam))
2872 {
2873 *ppRam = NULL; /* Shut up silly GCC warnings. */
2874 *ppPage = NULL; /* ditto */
2875 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2876 }
2877 off = GCPhys - pRam->GCPhys;
2878 } while (off >= pRam->cb);
2879 }
2880 *ppRam = pRam;
2881 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2882#ifndef VBOX_WITH_NEW_PHYS_CODE
2883
2884 /*
2885 * Make sure it's present.
2886 */
2887 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2888 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2889 {
2890#ifdef IN_RING3
2891 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2892#else
2893 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2894#endif
2895 if (VBOX_FAILURE(rc))
2896 {
2897 *ppPage = NULL; /* Shut up silly GCC warnings. */
2898 *ppPage = NULL; /* ditto */
2899 return rc;
2900 }
2901 Assert(rc == VINF_SUCCESS);
2902
2903 }
2904#endif
2905 return VINF_SUCCESS;
2906}
2907
2908
2909/**
2910 * Convert GC Phys to HC Phys.
2911 *
2912 * @returns VBox status.
2913 * @param pPGM PGM handle.
2914 * @param GCPhys The GC physical address.
2915 * @param pHCPhys Where to store the corresponding HC physical address.
2916 *
2917 * @deprecated Doesn't deal with zero, shared or write monitored pages.
2918 * Avoid when writing new code!
2919 */
2920DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2921{
2922 PPGMPAGE pPage;
2923 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2924 if (VBOX_FAILURE(rc))
2925 return rc;
2926 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
2927 return VINF_SUCCESS;
2928}
2929
2930
2931#ifndef IN_GC
2932/**
2933 * Queries the Physical TLB entry for a physical guest page,
2934 * attemting to load the TLB entry if necessary.
2935 *
2936 * @returns VBox status code.
2937 * @retval VINF_SUCCESS on success
2938 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2939 * @param pPGM The PGM instance handle.
2940 * @param GCPhys The address of the guest page.
2941 * @param ppTlbe Where to store the pointer to the TLB entry.
2942 */
2943
2944DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
2945{
2946 int rc;
2947 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
2948 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
2949 {
2950 STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
2951 rc = VINF_SUCCESS;
2952 }
2953 else
2954 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
2955 *ppTlbe = pTlbe;
2956 return rc;
2957}
2958#endif /* !IN_GC */
2959
2960
2961#ifndef VBOX_WITH_NEW_PHYS_CODE
2962/**
2963 * Convert GC Phys to HC Virt.
2964 *
2965 * @returns VBox status.
2966 * @param pPGM PGM handle.
2967 * @param GCPhys The GC physical address.
2968 * @param pHCPtr Where to store the corresponding HC virtual address.
2969 *
2970 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
2971 */
2972DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
2973{
2974 PPGMRAMRANGE pRam;
2975 PPGMPAGE pPage;
2976 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
2977 if (VBOX_FAILURE(rc))
2978 {
2979 *pHCPtr = 0; /* Shut up silly GCC warnings. */
2980 return rc;
2981 }
2982 RTGCPHYS off = GCPhys - pRam->GCPhys;
2983
2984 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2985 {
2986 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
2987 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2988 return VINF_SUCCESS;
2989 }
2990 if (pRam->pvHC)
2991 {
2992 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
2993 return VINF_SUCCESS;
2994 }
2995 *pHCPtr = 0; /* Shut up silly GCC warnings. */
2996 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2997}
2998#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2999
3000
3001/**
3002 * Convert GC Phys to HC Virt.
3003 *
3004 * @returns VBox status.
3005 * @param PVM VM handle.
3006 * @param pRam Ram range
3007 * @param GCPhys The GC physical address.
3008 * @param pHCPtr Where to store the corresponding HC virtual address.
3009 *
3010 * @deprecated This will be eliminated. Don't use it.
3011 */
3012DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3013{
3014 RTGCPHYS off = GCPhys - pRam->GCPhys;
3015 Assert(off < pRam->cb);
3016
3017 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3018 {
3019 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3020 /* Physical chunk in dynamically allocated range not present? */
3021 if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
3022 {
3023#ifdef IN_RING3
3024 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3025#else
3026 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3027#endif
3028 if (rc != VINF_SUCCESS)
3029 {
3030 *pHCPtr = 0; /* GCC crap */
3031 return rc;
3032 }
3033 }
3034 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3035 return VINF_SUCCESS;
3036 }
3037 if (pRam->pvHC)
3038 {
3039 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3040 return VINF_SUCCESS;
3041 }
3042 *pHCPtr = 0; /* GCC crap */
3043 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3044}
3045
3046
3047/**
3048 * Convert GC Phys to HC Virt and HC Phys.
3049 *
3050 * @returns VBox status.
3051 * @param pPGM PGM handle.
3052 * @param GCPhys The GC physical address.
3053 * @param pHCPtr Where to store the corresponding HC virtual address.
3054 * @param pHCPhys Where to store the HC Physical address and its flags.
3055 *
3056 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3057 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3058 */
3059DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3060{
3061 PPGMRAMRANGE pRam;
3062 PPGMPAGE pPage;
3063 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3064 if (VBOX_FAILURE(rc))
3065 {
3066 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3067 *pHCPhys = 0; /* ditto */
3068 return rc;
3069 }
3070 RTGCPHYS off = GCPhys - pRam->GCPhys;
3071
3072 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3073 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3074 {
3075 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3076 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3077 return VINF_SUCCESS;
3078 }
3079 if (pRam->pvHC)
3080 {
3081 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3082 return VINF_SUCCESS;
3083 }
3084 *pHCPtr = 0;
3085 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3086}
3087
3088
3089/**
3090 * Clears flags associated with a RAM address.
3091 *
3092 * @returns VBox status code.
3093 * @param pPGM PGM handle.
3094 * @param GCPhys Guest context physical address.
3095 * @param fFlags fFlags to clear. (Bits 0-11.)
3096 */
3097DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3098{
3099 PPGMPAGE pPage;
3100 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3101 if (VBOX_FAILURE(rc))
3102 return rc;
3103
3104 fFlags &= ~X86_PTE_PAE_PG_MASK;
3105 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3106 return VINF_SUCCESS;
3107}
3108
3109
3110/**
3111 * Clears flags associated with a RAM address.
3112 *
3113 * @returns VBox status code.
3114 * @param pPGM PGM handle.
3115 * @param GCPhys Guest context physical address.
3116 * @param fFlags fFlags to clear. (Bits 0-11.)
3117 * @param ppRamHint Where to read and store the ram list hint.
3118 * The caller initializes this to NULL before the call.
3119 */
3120DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3121{
3122 PPGMPAGE pPage;
3123 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3124 if (VBOX_FAILURE(rc))
3125 return rc;
3126
3127 fFlags &= ~X86_PTE_PAE_PG_MASK;
3128 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3129 return VINF_SUCCESS;
3130}
3131
3132/**
3133 * Sets (bitwise OR) flags associated with a RAM address.
3134 *
3135 * @returns VBox status code.
3136 * @param pPGM PGM handle.
3137 * @param GCPhys Guest context physical address.
3138 * @param fFlags fFlags to set clear. (Bits 0-11.)
3139 */
3140DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3141{
3142 PPGMPAGE pPage;
3143 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3144 if (VBOX_FAILURE(rc))
3145 return rc;
3146
3147 fFlags &= ~X86_PTE_PAE_PG_MASK;
3148 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3149 return VINF_SUCCESS;
3150}
3151
3152
3153/**
3154 * Sets (bitwise OR) flags associated with a RAM address.
3155 *
3156 * @returns VBox status code.
3157 * @param pPGM PGM handle.
3158 * @param GCPhys Guest context physical address.
3159 * @param fFlags fFlags to set clear. (Bits 0-11.)
3160 * @param ppRamHint Where to read and store the ram list hint.
3161 * The caller initializes this to NULL before the call.
3162 */
3163DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3164{
3165 PPGMPAGE pPage;
3166 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3167 if (VBOX_FAILURE(rc))
3168 return rc;
3169
3170 fFlags &= ~X86_PTE_PAE_PG_MASK;
3171 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3172 return VINF_SUCCESS;
3173}
3174
3175
3176/**
3177 * Gets the page directory for the specified address.
3178 *
3179 * @returns Pointer to the page directory in question.
3180 * @returns NULL if the page directory is not present or on an invalid page.
3181 * @param pPGM Pointer to the PGM instance data.
3182 * @param GCPtr The address.
3183 */
3184DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3185{
3186 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3187 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3188 {
3189 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3190 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3191
3192 /* cache is out-of-sync. */
3193 PX86PDPAE pPD;
3194 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3195 if (VBOX_SUCCESS(rc))
3196 return pPD;
3197 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3198 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3199 }
3200 return NULL;
3201}
3202
3203
3204/**
3205 * Gets the page directory entry for the specified address.
3206 *
3207 * @returns Pointer to the page directory entry in question.
3208 * @returns NULL if the page directory is not present or on an invalid page.
3209 * @param pPGM Pointer to the PGM instance data.
3210 * @param GCPtr The address.
3211 */
3212DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3213{
3214 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3215 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3216 {
3217 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3218 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3219 return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3220
3221 /* The cache is out-of-sync. */
3222 PX86PDPAE pPD;
3223 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3224 if (VBOX_SUCCESS(rc))
3225 return &pPD->a[iPD];
3226 AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3227 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3228 }
3229 return NULL;
3230}
3231
3232
3233/**
3234 * Gets the page directory entry for the specified address.
3235 *
3236 * @returns The page directory entry in question.
3237 * @returns A non-present entry if the page directory is not present or on an invalid page.
3238 * @param pPGM Pointer to the PGM instance data.
3239 * @param GCPtr The address.
3240 */
3241DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3242{
3243 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3244 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3245 {
3246 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3247 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3248 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3249
3250 /* cache is out-of-sync. */
3251 PX86PDPAE pPD;
3252 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3253 if (VBOX_SUCCESS(rc))
3254 return pPD->a[iPD].u;
3255 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3256 }
3257 return 0ULL;
3258}
3259
3260
3261/**
3262 * Gets the page directory pointer table entry for the specified address
3263 * and returns the index into the page directory
3264 *
3265 * @returns Pointer to the page directory in question.
3266 * @returns NULL if the page directory is not present or on an invalid page.
3267 * @param pPGM Pointer to the PGM instance data.
3268 * @param GCPtr The address.
3269 * @param piPD Receives the index into the returned page directory
3270 */
3271DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3272{
3273 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3274 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3275 {
3276 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3277 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3278 {
3279 *piPD = iPD;
3280 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3281 }
3282
3283 /* cache is out-of-sync. */
3284 PX86PDPAE pPD;
3285 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3286 if (VBOX_SUCCESS(rc))
3287 {
3288 *piPD = iPD;
3289 return pPD;
3290 }
3291 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3292 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3293 }
3294 return NULL;
3295}
3296
3297#ifndef IN_GC
3298/**
3299 * Gets the page directory pointer entry for the specified address.
3300 *
3301 * @returns Pointer to the page directory pointer entry in question.
3302 * @returns NULL if the page directory is not present or on an invalid page.
3303 * @param pPGM Pointer to the PGM instance data.
3304 * @param GCPtr The address.
3305 * @param ppPml4e Page Map Level-4 Entry (out)
3306 */
3307DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e)
3308{
3309 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3310
3311 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3312 if ((*ppPml4e)->n.u1Present)
3313 {
3314 PX86PDPT pPdpt;
3315 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdpt);
3316 if (VBOX_FAILURE(rc))
3317 {
3318 AssertFailed();
3319 return NULL;
3320 }
3321 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3322 return &pPdpt->a[iPdPt];
3323 }
3324 return NULL;
3325}
3326
3327/**
3328 * Gets the page directory entry for the specified address.
3329 *
3330 * @returns The page directory entry in question.
3331 * @returns A non-present entry if the page directory is not present or on an invalid page.
3332 * @param pPGM Pointer to the PGM instance data.
3333 * @param GCPtr The address.
3334 * @param ppPml4e Page Map Level-4 Entry (out)
3335 * @param pPdpe Page directory pointer table entry (out)
3336 */
3337DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3338{
3339 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3340
3341 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3342 if ((*ppPml4e)->n.u1Present)
3343 {
3344 PX86PDPT pPdptTemp;
3345 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3346 if (VBOX_FAILURE(rc))
3347 {
3348 AssertFailed();
3349 return 0ULL;
3350 }
3351
3352 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3353 *pPdpe = pPdptTemp->a[iPdPt];
3354 if (pPdpe->n.u1Present)
3355 {
3356 PX86PDPAE pPD;
3357
3358 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3359 if (VBOX_FAILURE(rc))
3360 {
3361 AssertFailed();
3362 return 0ULL;
3363 }
3364 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3365 return pPD->a[iPD].u;
3366 }
3367 }
3368 return 0ULL;
3369}
3370
3371/**
3372 * Gets the page directory entry for the specified address.
3373 *
3374 * @returns The page directory entry in question.
3375 * @returns A non-present entry if the page directory is not present or on an invalid page.
3376 * @param pPGM Pointer to the PGM instance data.
3377 * @param GCPtr The address.
3378 */
3379DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3380{
3381 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3382
3383 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3384 {
3385 PX86PDPT pPdptTemp;
3386 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3387 if (VBOX_FAILURE(rc))
3388 {
3389 AssertFailed();
3390 return 0ULL;
3391 }
3392
3393 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3394 if (pPdptTemp->a[iPdPt].n.u1Present)
3395 {
3396 PX86PDPAE pPD;
3397
3398 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3399 if (VBOX_FAILURE(rc))
3400 {
3401 AssertFailed();
3402 return 0ULL;
3403 }
3404 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3405 return pPD->a[iPD].u;
3406 }
3407 }
3408 return 0ULL;
3409}
3410
3411/**
3412 * Gets the page directory entry for the specified address.
3413 *
3414 * @returns Pointer to the page directory entry in question.
3415 * @returns NULL if the page directory is not present or on an invalid page.
3416 * @param pPGM Pointer to the PGM instance data.
3417 * @param GCPtr The address.
3418 */
3419DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3420{
3421 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3422
3423 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3424 {
3425 PX86PDPT pPdptTemp;
3426 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3427 if (VBOX_FAILURE(rc))
3428 {
3429 AssertFailed();
3430 return NULL;
3431 }
3432
3433 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3434 if (pPdptTemp->a[iPdPt].n.u1Present)
3435 {
3436 PX86PDPAE pPD;
3437
3438 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3439 if (VBOX_FAILURE(rc))
3440 {
3441 AssertFailed();
3442 return NULL;
3443 }
3444 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3445 return &pPD->a[iPD];
3446 }
3447 }
3448 return NULL;
3449}
3450
3451
3452/**
3453 * Gets the GUEST page directory pointer for the specified address.
3454 *
3455 * @returns The page directory in question.
3456 * @returns NULL if the page directory is not present or on an invalid page.
3457 * @param pPGM Pointer to the PGM instance data.
3458 * @param GCPtr The address.
3459 * @param ppPml4e Page Map Level-4 Entry (out)
3460 * @param pPdpe Page directory pointer table entry (out)
3461 * @param piPD Receives the index into the returned page directory
3462 */
3463DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
3464{
3465 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3466
3467 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3468 if ((*ppPml4e)->n.u1Present)
3469 {
3470 PX86PDPT pPdptTemp;
3471 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3472 if (VBOX_FAILURE(rc))
3473 {
3474 AssertFailed();
3475 return 0ULL;
3476 }
3477
3478 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3479 *pPdpe = pPdptTemp->a[iPdPt];
3480 if (pPdpe->n.u1Present)
3481 {
3482 PX86PDPAE pPD;
3483
3484 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3485 if (VBOX_FAILURE(rc))
3486 {
3487 AssertFailed();
3488 return 0ULL;
3489 }
3490 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3491 return pPD;
3492 }
3493 }
3494 return 0ULL;
3495}
3496#endif /* !IN_GC */
3497
3498/**
3499 * Checks if any of the specified page flags are set for the given page.
3500 *
3501 * @returns true if any of the flags are set.
3502 * @returns false if all the flags are clear.
3503 * @param pPGM PGM handle.
3504 * @param GCPhys The GC physical address.
3505 * @param fFlags The flags to check for.
3506 */
3507DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3508{
3509 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3510 return pPage
3511 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3512}
3513
3514
3515/**
3516 * Gets the page state for a physical handler.
3517 *
3518 * @returns The physical handler page state.
3519 * @param pCur The physical handler in question.
3520 */
3521DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3522{
3523 switch (pCur->enmType)
3524 {
3525 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3526 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3527
3528 case PGMPHYSHANDLERTYPE_MMIO:
3529 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3530 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3531
3532 default:
3533 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3534 }
3535}
3536
3537
3538/**
3539 * Gets the page state for a virtual handler.
3540 *
3541 * @returns The virtual handler page state.
3542 * @param pCur The virtual handler in question.
3543 * @remarks This should never be used on a hypervisor access handler.
3544 */
3545DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3546{
3547 switch (pCur->enmType)
3548 {
3549 case PGMVIRTHANDLERTYPE_WRITE:
3550 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3551 case PGMVIRTHANDLERTYPE_ALL:
3552 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3553 default:
3554 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3555 }
3556}
3557
3558
3559/**
3560 * Clears one physical page of a virtual handler
3561 *
3562 * @param pPGM Pointer to the PGM instance.
3563 * @param pCur Virtual handler structure
3564 * @param iPage Physical page index
3565 *
3566 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3567 * need to care about other handlers in the same page.
3568 */
3569DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3570{
3571 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3572
3573 /*
3574 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
3575 */
3576#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3577 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3578 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3579 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3580#endif
3581 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3582 {
3583 /* We're the head of the alias chain. */
3584 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3585#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3586 AssertReleaseMsg(pRemove != NULL,
3587 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3588 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3589 AssertReleaseMsg(pRemove == pPhys2Virt,
3590 ("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3591 " got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3592 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3593 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3594#endif
3595 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3596 {
3597 /* Insert the next list in the alias chain into the tree. */
3598 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3599#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3600 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3601 ("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3602 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3603#endif
3604 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
3605 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3606 AssertRelease(fRc);
3607 }
3608 }
3609 else
3610 {
3611 /* Locate the previous node in the alias chain. */
3612 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3613#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3614 AssertReleaseMsg(pPrev != pPhys2Virt,
3615 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3616 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3617#endif
3618 for (;;)
3619 {
3620 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3621 if (pNext == pPhys2Virt)
3622 {
3623 /* unlink. */
3624 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3625 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3626 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3627 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3628 else
3629 {
3630 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3631 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3632 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3633 }
3634 break;
3635 }
3636
3637 /* next */
3638 if (pNext == pPrev)
3639 {
3640#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3641 AssertReleaseMsg(pNext != pPrev,
3642 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3643 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3644#endif
3645 break;
3646 }
3647 pPrev = pNext;
3648 }
3649 }
3650 Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3651 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3652 pPhys2Virt->offNextAlias = 0;
3653 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3654
3655 /*
3656 * Clear the ram flags for this page.
3657 */
3658 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3659 AssertReturnVoid(pPage);
3660 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3661}
3662
3663
3664/**
3665 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3666 *
3667 * @returns Pointer to the shadow page structure.
3668 * @param pPool The pool.
3669 * @param HCPhys The HC physical address of the shadow page.
3670 */
3671DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3672{
3673 /*
3674 * Look up the page.
3675 */
3676 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3677 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3678 return pPage;
3679}
3680
3681
3682/**
3683 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3684 *
3685 * @returns Pointer to the shadow page structure.
3686 * @param pPool The pool.
3687 * @param idx The pool page index.
3688 */
3689DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3690{
3691 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3692 return &pPool->aPages[idx];
3693}
3694
3695
3696#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3697/**
3698 * Clear references to guest physical memory.
3699 *
3700 * @param pPool The pool.
3701 * @param pPoolPage The pool page.
3702 * @param pPhysPage The physical guest page tracking structure.
3703 */
3704DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3705{
3706 /*
3707 * Just deal with the simple case here.
3708 */
3709#ifdef LOG_ENABLED
3710 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3711#endif
3712 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3713 if (cRefs == 1)
3714 {
3715 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3716 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3717 }
3718 else
3719 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3720 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3721}
3722#endif
3723
3724
3725#ifdef PGMPOOL_WITH_CACHE
3726/**
3727 * Moves the page to the head of the age list.
3728 *
3729 * This is done when the cached page is used in one way or another.
3730 *
3731 * @param pPool The pool.
3732 * @param pPage The cached page.
3733 * @todo inline in PGMInternal.h!
3734 */
3735DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3736{
3737 /*
3738 * Move to the head of the age list.
3739 */
3740 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3741 {
3742 /* unlink */
3743 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3744 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3745 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3746 else
3747 pPool->iAgeTail = pPage->iAgePrev;
3748
3749 /* insert at head */
3750 pPage->iAgePrev = NIL_PGMPOOL_IDX;
3751 pPage->iAgeNext = pPool->iAgeHead;
3752 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3753 pPool->iAgeHead = pPage->idx;
3754 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3755 }
3756}
3757#endif /* PGMPOOL_WITH_CACHE */
3758
3759/**
3760 * Tells if mappings are to be put into the shadow page table or not
3761 *
3762 * @returns boolean result
3763 * @param pVM VM handle.
3764 */
3765
3766DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3767{
3768#ifdef IN_RING0
3769 /* There are no mappings in VT-x and AMD-V mode. */
3770 Assert(pPGM->fDisableMappings);
3771 return false;
3772#else
3773 return !pPGM->fDisableMappings;
3774#endif
3775}
3776
3777/** @} */
3778
3779#endif
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette