VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 9016

Last change on this file since 9016 was 9008, checked in by vboxsync, 17 years ago

Changes for proper flushing of the TLB for physical registration changes.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 150.3 KB
Line 
1/* $Id: PGMInternal.h 9008 2008-05-21 10:17:41Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
44# error "Not in PGM! This is an internal header!"
45#endif
46
47
48/** @defgroup grp_pgm_int Internals
49 * @ingroup grp_pgm
50 * @internal
51 * @{
52 */
53
54
55/** @name PGM Compile Time Config
56 * @{
57 */
58
59/**
60 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
61 * Comment it if it will break something.
62 */
63#define PGM_OUT_OF_SYNC_IN_GC
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Sync N pages instead of a whole page table
72 */
73#define PGM_SYNC_N_PAGES
74
75/**
76 * Number of pages to sync during a page fault
77 *
78 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
79 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
80 */
81#define PGM_SYNC_NR_PAGES 8
82
83/**
84 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
85 */
86#define PGM_MAX_PHYSCACHE_ENTRIES 64
87#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
88
89/**
90 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
91 */
92#define PGM_PHYSMEMACCESS_CACHING
93
94/** @def PGMPOOL_WITH_CACHE
95 * Enable agressive caching using the page pool.
96 *
97 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
98 */
99#define PGMPOOL_WITH_CACHE
100
101/** @def PGMPOOL_WITH_MIXED_PT_CR3
102 * When defined, we'll deal with 'uncachable' pages.
103 */
104#ifdef PGMPOOL_WITH_CACHE
105# define PGMPOOL_WITH_MIXED_PT_CR3
106#endif
107
108/** @def PGMPOOL_WITH_MONITORING
109 * Monitor the guest pages which are shadowed.
110 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
111 * be enabled as well.
112 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
113 */
114#ifdef PGMPOOL_WITH_CACHE
115# define PGMPOOL_WITH_MONITORING
116#endif
117
118/** @def PGMPOOL_WITH_GCPHYS_TRACKING
119 * Tracking the of shadow pages mapping guest physical pages.
120 *
121 * This is very expensive, the current cache prototype is trying to figure out
122 * whether it will be acceptable with an agressive caching policy.
123 */
124#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
125# define PGMPOOL_WITH_GCPHYS_TRACKING
126#endif
127
128/** @def PGMPOOL_WITH_USER_TRACKNG
129 * Tracking users of shadow pages. This is required for the linking of shadow page
130 * tables and physical guest addresses.
131 */
132#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
133# define PGMPOOL_WITH_USER_TRACKING
134#endif
135
136/** @def PGMPOOL_CFG_MAX_GROW
137 * The maximum number of pages to add to the pool in one go.
138 */
139#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
140
141/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
142 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
143 */
144#ifdef VBOX_STRICT
145# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
146#endif
147/** @} */
148
149
150/** @name PDPT and PML4 flags.
151 * These are placed in the three bits available for system programs in
152 * the PDPT and PML4 entries.
153 * @{ */
154/** The entry is a permanent one and it's must always be present.
155 * Never free such an entry. */
156#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
157/** Mapping (hypervisor allocated pagetable). */
158#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
159/** @} */
160
161/** @name Page directory flags.
162 * These are placed in the three bits available for system programs in
163 * the page directory entries.
164 * @{ */
165/** Mapping (hypervisor allocated pagetable). */
166#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
167/** Made read-only to facilitate dirty bit tracking. */
168#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
169/** @} */
170
171/** @name Page flags.
172 * These are placed in the three bits available for system programs in
173 * the page entries.
174 * @{ */
175/** Made read-only to facilitate dirty bit tracking. */
176#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
177
178#ifndef PGM_PTFLAGS_CSAM_VALIDATED
179/** Scanned and approved by CSAM (tm).
180 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
181 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
182#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
183#endif
184/** @} */
185
186/** @name Defines used to indicate the shadow and guest paging in the templates.
187 * @{ */
188#define PGM_TYPE_REAL 1
189#define PGM_TYPE_PROT 2
190#define PGM_TYPE_32BIT 3
191#define PGM_TYPE_PAE 4
192#define PGM_TYPE_AMD64 5
193/** @} */
194
195/** Macro for checking if the guest is using paging.
196 * @param uType PGM_TYPE_*
197 * @remark ASSUMES certain order of the PGM_TYPE_* values.
198 */
199#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT)
200
201/** Macro for checking if the guest supports the NX bit.
202 * @param uType PGM_TYPE_*
203 * @remark ASSUMES certain order of the PGM_TYPE_* values.
204 */
205#define PGM_WITH_NX(uType) ((uType) >= PGM_TYPE_PAE)
206
207
208/** @def PGM_HCPHYS_2_PTR
209 * Maps a HC physical page pool address to a virtual address.
210 *
211 * @returns VBox status code.
212 * @param pVM The VM handle.
213 * @param HCPhys The HC physical address to map to a virtual one.
214 * @param ppv Where to store the virtual address. No need to cast this.
215 *
216 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
217 * small page window employeed by that function. Be careful.
218 * @remark There is no need to assert on the result.
219 */
220#ifdef IN_GC
221# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
222#else
223# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
224#endif
225
226/** @def PGM_GCPHYS_2_PTR
227 * Maps a GC physical page address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param GCPhys The GC physical address to map to a virtual one.
232 * @param ppv Where to store the virtual address. No need to cast this.
233 *
234 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
235 * small page window employeed by that function. Be careful.
236 * @remark There is no need to assert on the result.
237 */
238#ifdef IN_GC
239# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
240#else
241# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
242#endif
243
244/** @def PGM_GCPHYS_2_PTR_EX
245 * Maps a unaligned GC physical page address to a virtual address.
246 *
247 * @returns VBox status code.
248 * @param pVM The VM handle.
249 * @param GCPhys The GC physical address to map to a virtual one.
250 * @param ppv Where to store the virtual address. No need to cast this.
251 *
252 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
253 * small page window employeed by that function. Be careful.
254 * @remark There is no need to assert on the result.
255 */
256#ifdef IN_GC
257# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
258#else
259# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
260#endif
261
262/** @def PGM_INVL_PG
263 * Invalidates a page when in GC does nothing in HC.
264 *
265 * @param GCVirt The virtual address of the page to invalidate.
266 */
267#ifdef IN_GC
268# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
269#elif defined(IN_RING0)
270# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
271#else
272# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
273#endif
274
275/** @def PGM_INVL_BIG_PG
276 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
277 *
278 * @param GCVirt The virtual address within the page directory to invalidate.
279 */
280#ifdef IN_GC
281# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
282#elif defined(IN_RING0)
283# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
284#else
285# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
286#endif
287
288/** @def PGM_INVL_GUEST_TLBS()
289 * Invalidates all guest TLBs.
290 */
291#ifdef IN_GC
292# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
293#elif defined(IN_RING0)
294# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
295#else
296# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
297#endif
298
299
300/**
301 * Structure for tracking GC Mappings.
302 *
303 * This structure is used by linked list in both GC and HC.
304 */
305typedef struct PGMMAPPING
306{
307 /** Pointer to next entry. */
308 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
309 /** Pointer to next entry. */
310 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
311 /** Pointer to next entry. */
312 GCPTRTYPE(struct PGMMAPPING *) pNextGC;
313 /** Start Virtual address. */
314 RTGCUINTPTR GCPtr;
315 /** Last Virtual address (inclusive). */
316 RTGCUINTPTR GCPtrLast;
317 /** Range size (bytes). */
318 RTGCUINTPTR cb;
319 /** Pointer to relocation callback function. */
320 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
321 /** User argument to the callback. */
322 R3PTRTYPE(void *) pvUser;
323 /** Mapping description / name. For easing debugging. */
324 R3PTRTYPE(const char *) pszDesc;
325 /** Number of page tables. */
326 RTUINT cPTs;
327#if HC_ARCH_BITS != GC_ARCH_BITS
328 RTUINT uPadding0; /**< Alignment padding. */
329#endif
330 /** Array of page table mapping data. Each entry
331 * describes one page table. The array can be longer
332 * than the declared length.
333 */
334 struct
335 {
336 /** The HC physical address of the page table. */
337 RTHCPHYS HCPhysPT;
338 /** The HC physical address of the first PAE page table. */
339 RTHCPHYS HCPhysPaePT0;
340 /** The HC physical address of the second PAE page table. */
341 RTHCPHYS HCPhysPaePT1;
342 /** The HC virtual address of the 32-bit page table. */
343 R3PTRTYPE(PX86PT) pPTR3;
344 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
345 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
346 /** The GC virtual address of the 32-bit page table. */
347 GCPTRTYPE(PX86PT) pPTGC;
348 /** The GC virtual address of the two PAE page table. */
349 GCPTRTYPE(PX86PTPAE) paPaePTsGC;
350 /** The GC virtual address of the 32-bit page table. */
351 R0PTRTYPE(PX86PT) pPTR0;
352 /** The GC virtual address of the two PAE page table. */
353 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
354 } aPTs[1];
355} PGMMAPPING;
356/** Pointer to structure for tracking GC Mappings. */
357typedef struct PGMMAPPING *PPGMMAPPING;
358
359
360/**
361 * Physical page access handler structure.
362 *
363 * This is used to keep track of physical address ranges
364 * which are being monitored in some kind of way.
365 */
366typedef struct PGMPHYSHANDLER
367{
368 AVLROGCPHYSNODECORE Core;
369 /** Access type. */
370 PGMPHYSHANDLERTYPE enmType;
371 /** Number of pages to update. */
372 uint32_t cPages;
373 /** Pointer to R3 callback function. */
374 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
375 /** User argument for R3 handlers. */
376 R3PTRTYPE(void *) pvUserR3;
377 /** Pointer to R0 callback function. */
378 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
379 /** User argument for R0 handlers. */
380 R0PTRTYPE(void *) pvUserR0;
381 /** Pointer to GC callback function. */
382 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
383 /** User argument for GC handlers. */
384 GCPTRTYPE(void *) pvUserGC;
385 /** Description / Name. For easing debugging. */
386 R3PTRTYPE(const char *) pszDesc;
387#ifdef VBOX_WITH_STATISTICS
388 /** Profiling of this handler. */
389 STAMPROFILE Stat;
390#endif
391} PGMPHYSHANDLER;
392/** Pointer to a physical page access handler structure. */
393typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
394
395
396/**
397 * Cache node for the physical addresses covered by a virtual handler.
398 */
399typedef struct PGMPHYS2VIRTHANDLER
400{
401 /** Core node for the tree based on physical ranges. */
402 AVLROGCPHYSNODECORE Core;
403 /** Offset from this struct to the PGMVIRTHANDLER structure. */
404 int32_t offVirtHandler;
405 /** Offset of the next alias relative to this one.
406 * Bit 0 is used for indicating whether we're in the tree.
407 * Bit 1 is used for indicating that we're the head node.
408 */
409 int32_t offNextAlias;
410} PGMPHYS2VIRTHANDLER;
411/** Pointer to a phys to virtual handler structure. */
412typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
413
414/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
415 * node is in the tree. */
416#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
417/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
418 * node is in the head of an alias chain.
419 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
420#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
421/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
422#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
423
424
425/**
426 * Virtual page access handler structure.
427 *
428 * This is used to keep track of virtual address ranges
429 * which are being monitored in some kind of way.
430 */
431typedef struct PGMVIRTHANDLER
432{
433 /** Core node for the tree based on virtual ranges. */
434 AVLROGCPTRNODECORE Core;
435 /** Number of cache pages. */
436 uint32_t u32Padding;
437 /** Access type. */
438 PGMVIRTHANDLERTYPE enmType;
439 /** Number of cache pages. */
440 uint32_t cPages;
441
442/** @todo The next two members are redundant. It adds some readability though. */
443 /** Start of the range. */
444 RTGCPTR GCPtr;
445 /** End of the range (exclusive). */
446 RTGCPTR GCPtrLast;
447 /** Size of the range (in bytes). */
448 RTGCUINTPTR cb;
449 /** Pointer to the GC callback function. */
450 GCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
451 /** Pointer to the HC callback function for invalidation. */
452 R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
453 /** Pointer to the HC callback function. */
454 R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
455 /** Description / Name. For easing debugging. */
456 R3PTRTYPE(const char *) pszDesc;
457#ifdef VBOX_WITH_STATISTICS
458 /** Profiling of this handler. */
459 STAMPROFILE Stat;
460#endif
461 /** Array of cached physical addresses for the monitored ranged. */
462 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
463} PGMVIRTHANDLER;
464/** Pointer to a virtual page access handler structure. */
465typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
466
467
468/**
469 * Page type.
470 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
471 * @todo convert to \#defines.
472 */
473typedef enum PGMPAGETYPE
474{
475 /** The usual invalid zero entry. */
476 PGMPAGETYPE_INVALID = 0,
477 /** RAM page. (RWX) */
478 PGMPAGETYPE_RAM,
479 /** MMIO2 page. (RWX) */
480 PGMPAGETYPE_MMIO2,
481 /** Shadowed ROM. (RWX) */
482 PGMPAGETYPE_ROM_SHADOW,
483 /** ROM page. (R-X) */
484 PGMPAGETYPE_ROM,
485 /** MMIO page. (---) */
486 PGMPAGETYPE_MMIO,
487 /** End of valid entries. */
488 PGMPAGETYPE_END
489} PGMPAGETYPE;
490AssertCompile(PGMPAGETYPE_END < 7);
491
492/** @name Page type predicates.
493 * @{ */
494#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
495#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
496#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
497#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
498#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
499/** @} */
500
501
502/**
503 * A Physical Guest Page tracking structure.
504 *
505 * The format of this structure is complicated because we have to fit a lot
506 * of information into as few bits as possible. The format is also subject
507 * to change (there is one comming up soon). Which means that for we'll be
508 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
509 * accessess to the structure.
510 */
511typedef struct PGMPAGE
512{
513 /** The physical address and a whole lot of other stuff. All bits are used! */
514 RTHCPHYS HCPhys;
515 /** The page state. */
516 uint32_t u2StateX : 2;
517 /** Flag indicating that a write monitored page was written to when set. */
518 uint32_t fWrittenToX : 1;
519 /** For later. */
520 uint32_t fSomethingElse : 1;
521 /** The Page ID.
522 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
523 * The HCPhys will be 100% static. */
524 uint32_t idPageX : 28;
525 /** The page type (PGMPAGETYPE). */
526 uint32_t u3Type : 3;
527 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
528 uint32_t u2HandlerPhysStateX : 2;
529 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
530 uint32_t u2HandlerVirtStateX : 2;
531 uint32_t u29B : 25;
532} PGMPAGE;
533AssertCompileSize(PGMPAGE, 16);
534/** Pointer to a physical guest page. */
535typedef PGMPAGE *PPGMPAGE;
536/** Pointer to a const physical guest page. */
537typedef const PGMPAGE *PCPGMPAGE;
538/** Pointer to a physical guest page pointer. */
539typedef PPGMPAGE *PPPGMPAGE;
540
541
542/**
543 * Clears the page structure.
544 * @param pPage Pointer to the physical guest page tracking structure.
545 */
546#define PGM_PAGE_CLEAR(pPage) \
547 do { \
548 (pPage)->HCPhys = 0; \
549 (pPage)->u2StateX = 0; \
550 (pPage)->fWrittenToX = 0; \
551 (pPage)->fSomethingElse = 0; \
552 (pPage)->idPageX = 0; \
553 (pPage)->u3Type = 0; \
554 (pPage)->u29B = 0; \
555 } while (0)
556
557/**
558 * Initializes the page structure.
559 * @param pPage Pointer to the physical guest page tracking structure.
560 */
561#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
562 do { \
563 (pPage)->HCPhys = (_HCPhys); \
564 (pPage)->u2StateX = (_uState); \
565 (pPage)->fWrittenToX = 0; \
566 (pPage)->fSomethingElse = 0; \
567 (pPage)->idPageX = (_idPage); \
568 /*(pPage)->u3Type = (_uType); - later */ \
569 PGM_PAGE_SET_TYPE(pPage, _uType); \
570 (pPage)->u29B = 0; \
571 } while (0)
572
573/**
574 * Initializes the page structure of a ZERO page.
575 * @param pPage Pointer to the physical guest page tracking structure.
576 */
577#ifdef VBOX_WITH_NEW_PHYS_CODE
578# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
579 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
580#else
581# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
582 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
583#endif
584/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
585# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
586 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
587
588
589/** @name The Page state, PGMPAGE::u2StateX.
590 * @{ */
591/** The zero page.
592 * This is a per-VM page that's never ever mapped writable. */
593#define PGM_PAGE_STATE_ZERO 0
594/** A allocated page.
595 * This is a per-VM page allocated from the page pool (or wherever
596 * we get MMIO2 pages from if the type is MMIO2).
597 */
598#define PGM_PAGE_STATE_ALLOCATED 1
599/** A allocated page that's being monitored for writes.
600 * The shadow page table mappings are read-only. When a write occurs, the
601 * fWrittenTo member is set, the page remapped as read-write and the state
602 * moved back to allocated. */
603#define PGM_PAGE_STATE_WRITE_MONITORED 2
604/** The page is shared, aka. copy-on-write.
605 * This is a page that's shared with other VMs. */
606#define PGM_PAGE_STATE_SHARED 3
607/** @} */
608
609
610/**
611 * Gets the page state.
612 * @returns page state (PGM_PAGE_STATE_*).
613 * @param pPage Pointer to the physical guest page tracking structure.
614 */
615#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
616
617/**
618 * Sets the page state.
619 * @param pPage Pointer to the physical guest page tracking structure.
620 * @param _uState The new page state.
621 */
622#define PGM_PAGE_SET_STATE(pPage, _uState) \
623 do { (pPage)->u2StateX = (_uState); } while (0)
624
625
626/**
627 * Gets the host physical address of the guest page.
628 * @returns host physical address (RTHCPHYS).
629 * @param pPage Pointer to the physical guest page tracking structure.
630 */
631#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
632
633/**
634 * Sets the host physical address of the guest page.
635 * @param pPage Pointer to the physical guest page tracking structure.
636 * @param _HCPhys The new host physical address.
637 */
638#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
639 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
640 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
641
642/**
643 * Get the Page ID.
644 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
645 * @param pPage Pointer to the physical guest page tracking structure.
646 */
647#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
648/* later:
649#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
650 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
651*/
652/**
653 * Sets the Page ID.
654 * @param pPage Pointer to the physical guest page tracking structure.
655 */
656#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
657/* later:
658#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
659 | ((_idPage) & 0xfff) \
660 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
661*/
662
663/**
664 * Get the Chunk ID.
665 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
666 * @param pPage Pointer to the physical guest page tracking structure.
667 */
668#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
669/* later:
670#if GMM_CHUNKID_SHIFT == 12
671# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
672#elif GMM_CHUNKID_SHIFT > 12
673# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
674#elif GMM_CHUNKID_SHIFT < 12
675# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
676 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
677#else
678# error "GMM_CHUNKID_SHIFT isn't defined or something."
679#endif
680*/
681
682/**
683 * Get the index of the page within the allocaiton chunk.
684 * @returns The page index.
685 * @param pPage Pointer to the physical guest page tracking structure.
686 */
687#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
688/* later:
689#if GMM_CHUNKID_SHIFT <= 12
690# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
691#else
692# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
693 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
694#endif
695*/
696
697
698/**
699 * Gets the page type.
700 * @returns The page type.
701 * @param pPage Pointer to the physical guest page tracking structure.
702 */
703#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
704
705/**
706 * Sets the page type.
707 * @param pPage Pointer to the physical guest page tracking structure.
708 * @param _enmType The new page type (PGMPAGETYPE).
709 */
710#ifdef VBOX_WITH_NEW_PHYS_CODE
711#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
712 do { (pPage)->u3Type = (_enmType); } while (0)
713#else
714#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
715 do { \
716 (pPage)->u3Type = (_enmType); \
717 if ((_enmType) == PGMPAGETYPE_ROM) \
718 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
719 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
720 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
721 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
722 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
723 } while (0)
724#endif
725
726
727/**
728 * Checks if the page is 'reserved'.
729 * @returns true/false.
730 * @param pPage Pointer to the physical guest page tracking structure.
731 */
732#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
733
734/**
735 * Checks if the page is marked for MMIO.
736 * @returns true/false.
737 * @param pPage Pointer to the physical guest page tracking structure.
738 */
739#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
740
741/**
742 * Checks if the page is backed by the ZERO page.
743 * @returns true/false.
744 * @param pPage Pointer to the physical guest page tracking structure.
745 */
746#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
747
748/**
749 * Checks if the page is backed by a SHARED page.
750 * @returns true/false.
751 * @param pPage Pointer to the physical guest page tracking structure.
752 */
753#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
754
755
756/**
757 * Marks the paget as written to (for GMM change monitoring).
758 * @param pPage Pointer to the physical guest page tracking structure.
759 */
760#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
761
762/**
763 * Clears the written-to indicator.
764 * @param pPage Pointer to the physical guest page tracking structure.
765 */
766#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
767
768/**
769 * Checks if the page was marked as written-to.
770 * @returns true/false.
771 * @param pPage Pointer to the physical guest page tracking structure.
772 */
773#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
774
775
776/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
777 *
778 * @remarks The values are assigned in order of priority, so we can calculate
779 * the correct state for a page with different handlers installed.
780 * @{ */
781/** No handler installed. */
782#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
783/** Monitoring is temporarily disabled. */
784#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
785/** Write access is monitored. */
786#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
787/** All access is monitored. */
788#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
789/** @} */
790
791/**
792 * Gets the physical access handler state of a page.
793 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
794 * @param pPage Pointer to the physical guest page tracking structure.
795 */
796#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
797
798/**
799 * Sets the physical access handler state of a page.
800 * @param pPage Pointer to the physical guest page tracking structure.
801 * @param _uState The new state value.
802 */
803#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
804 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
805
806/**
807 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
808 * @returns true/false
809 * @param pPage Pointer to the physical guest page tracking structure.
810 */
811#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
812
813/**
814 * Checks if the page has any active physical access handlers.
815 * @returns true/false
816 * @param pPage Pointer to the physical guest page tracking structure.
817 */
818#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
819
820
821/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
822 *
823 * @remarks The values are assigned in order of priority, so we can calculate
824 * the correct state for a page with different handlers installed.
825 * @{ */
826/** No handler installed. */
827#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
828/* 1 is reserved so the lineup is identical with the physical ones. */
829/** Write access is monitored. */
830#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
831/** All access is monitored. */
832#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
833/** @} */
834
835/**
836 * Gets the virtual access handler state of a page.
837 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
838 * @param pPage Pointer to the physical guest page tracking structure.
839 */
840#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
841
842/**
843 * Sets the virtual access handler state of a page.
844 * @param pPage Pointer to the physical guest page tracking structure.
845 * @param _uState The new state value.
846 */
847#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
848 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
849
850/**
851 * Checks if the page has any virtual access handlers.
852 * @returns true/false
853 * @param pPage Pointer to the physical guest page tracking structure.
854 */
855#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
856
857/**
858 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
859 * virtual handlers.
860 * @returns true/false
861 * @param pPage Pointer to the physical guest page tracking structure.
862 */
863#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
864
865
866
867/**
868 * Checks if the page has any access handlers, including temporarily disabled ones.
869 * @returns true/false
870 * @param pPage Pointer to the physical guest page tracking structure.
871 */
872#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
873 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
874 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
875
876/**
877 * Checks if the page has any active access handlers.
878 * @returns true/false
879 * @param pPage Pointer to the physical guest page tracking structure.
880 */
881#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
882 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
883 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
884
885/**
886 * Checks if the page has any active access handlers catching all accesses.
887 * @returns true/false
888 * @param pPage Pointer to the physical guest page tracking structure.
889 */
890#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
891 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
892 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
893
894
895/**
896 * Ram range for GC Phys to HC Phys conversion.
897 *
898 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
899 * conversions too, but we'll let MM handle that for now.
900 *
901 * This structure is used by linked lists in both GC and HC.
902 */
903typedef struct PGMRAMRANGE
904{
905 /** Pointer to the next RAM range - for R3. */
906 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
907 /** Pointer to the next RAM range - for R0. */
908 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
909 /** Pointer to the next RAM range - for GC. */
910 GCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
911#if GC_ARCH_BITS == 32
912 /** Pointer alignment. */
913 RTGCPTR GCPtrAlignment;
914#endif
915 /** Start of the range. Page aligned. */
916 RTGCPHYS GCPhys;
917 /** Last address in the range (inclusive). Page aligned (-1). */
918 RTGCPHYS GCPhysLast;
919 /** Size of the range. (Page aligned of course). */
920 RTGCPHYS cb;
921 /** MM_RAM_* flags */
922 uint32_t fFlags;
923#ifdef VBOX_WITH_NEW_PHYS_CODE
924 uint32_t u32Alignment; /**< alignment. */
925#else
926 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
927 GCPTRTYPE(PRTHCPTR) pavHCChunkGC;
928 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
929 R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
930#endif
931 /** Start of the HC mapping of the range. This is only used for MMIO2. */
932 R3PTRTYPE(void *) pvHC;
933 /** The range description. */
934 R3PTRTYPE(const char *) pszDesc;
935
936 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
937#ifdef VBOX_WITH_NEW_PHYS_CODE
938 uint32_t au32Reserved[2];
939#elif HC_ARCH_BITS == 32
940 uint32_t au32Reserved[1];
941#endif
942
943 /** Array of physical guest page tracking structures. */
944 PGMPAGE aPages[1];
945} PGMRAMRANGE;
946/** Pointer to Ram range for GC Phys to HC Phys conversion. */
947typedef PGMRAMRANGE *PPGMRAMRANGE;
948
949/** Return hc ptr corresponding to the ram range and physical offset */
950#define PGMRAMRANGE_GETHCPTR(pRam, off) \
951 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
952 : (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
953
954/**
955 * Per page tracking structure for ROM image.
956 *
957 * A ROM image may have a shadow page, in which case we may have
958 * two pages backing it. This structure contains the PGMPAGE for
959 * both while PGMRAMRANGE have a copy of the active one. It is
960 * important that these aren't out of sync in any regard other
961 * than page pool tracking data.
962 */
963typedef struct PGMROMPAGE
964{
965 /** The page structure for the virgin ROM page. */
966 PGMPAGE Virgin;
967 /** The page structure for the shadow RAM page. */
968 PGMPAGE Shadow;
969 /** The current protection setting. */
970 PGMROMPROT enmProt;
971 /** Pad the structure size to a multiple of 8. */
972 uint32_t u32Padding;
973} PGMROMPAGE;
974/** Pointer to a ROM page tracking structure. */
975typedef PGMROMPAGE *PPGMROMPAGE;
976
977
978/**
979 * A registered ROM image.
980 *
981 * This is needed to keep track of ROM image since they generally
982 * intrude into a PGMRAMRANGE. It also keeps track of additional
983 * info like the two page sets (read-only virgin and read-write shadow),
984 * the current state of each page.
985 *
986 * Because access handlers cannot easily be executed in a different
987 * context, the ROM ranges needs to be accessible and in all contexts.
988 */
989typedef struct PGMROMRANGE
990{
991 /** Pointer to the next range - R3. */
992 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
993 /** Pointer to the next range - R0. */
994 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
995 /** Pointer to the next range - GC. */
996 GCPTRTYPE(struct PGMROMRANGE *) pNextGC;
997#if GC_ARCH_BITS == 32
998 RTGCPTR GCPtrAlignment; /**< Pointer alignment. */
999#endif
1000 /** Address of the range. */
1001 RTGCPHYS GCPhys;
1002 /** Address of the last byte in the range. */
1003 RTGCPHYS GCPhysLast;
1004 /** Size of the range. */
1005 RTGCPHYS cb;
1006 /** The flags (PGMPHYS_ROM_FLAG_*). */
1007 uint32_t fFlags;
1008 /**< Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1009 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1010 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1011 * This is used for strictness checks. */
1012 R3PTRTYPE(const void *) pvOriginal;
1013 /** The ROM description. */
1014 R3PTRTYPE(const char *) pszDesc;
1015 /** The per page tracking structures. */
1016 PGMROMPAGE aPages[1];
1017} PGMROMRANGE;
1018/** Pointer to a ROM range. */
1019typedef PGMROMRANGE *PPGMROMRANGE;
1020
1021
1022/**
1023 * A registered MMIO2 (= Device RAM) range.
1024 *
1025 * There are a few reason why we need to keep track of these
1026 * registrations. One of them is the deregistration & cleanup
1027 * stuff, while another is that the PGMRAMRANGE associated with
1028 * such a region may have to be removed from the ram range list.
1029 *
1030 * Overlapping with a RAM range has to be 100% or none at all. The
1031 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1032 * meditation will be raised if a partial overlap or an overlap of
1033 * ROM pages is encountered. On an overlap we will free all the
1034 * existing RAM pages and put in the ram range pages instead.
1035 */
1036typedef struct PGMMMIO2RANGE
1037{
1038 /** The owner of the range. (a device) */
1039 PPDMDEVINSR3 pDevInsR3;
1040 /** Pointer to the ring-3 mapping of the allocation. */
1041 RTR3PTR pvR3;
1042 /** Pointer to the next range - R3. */
1043 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1044 /** Whether it's mapped or not. */
1045 bool fMapped;
1046 /** Whether it's overlapping or not. */
1047 bool fOverlapping;
1048 /** The PCI region number.
1049 * @remarks This ASSUMES that nobody will ever really need to have multiple
1050 * PCI devices with matching MMIO region numbers on a single device. */
1051 uint8_t iRegion;
1052 /**< Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1053 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1054 /** The associated RAM range. */
1055 PGMRAMRANGE RamRange;
1056} PGMMMIO2RANGE;
1057/** Pointer to a MMIO2 range. */
1058typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1059
1060
1061
1062
1063/** @todo r=bird: fix typename. */
1064/**
1065 * PGMPhysRead/Write cache entry
1066 */
1067typedef struct PGMPHYSCACHE_ENTRY
1068{
1069 /** HC pointer to physical page */
1070 R3PTRTYPE(uint8_t *) pbHC;
1071 /** GC Physical address for cache entry */
1072 RTGCPHYS GCPhys;
1073#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1074 RTGCPHYS u32Padding0; /**< alignment padding. */
1075#endif
1076} PGMPHYSCACHE_ENTRY;
1077
1078/**
1079 * PGMPhysRead/Write cache to reduce REM memory access overhead
1080 */
1081typedef struct PGMPHYSCACHE
1082{
1083 /** Bitmap of valid cache entries */
1084 uint64_t aEntries;
1085 /** Cache entries */
1086 PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1087} PGMPHYSCACHE;
1088
1089
1090/** Pointer to an allocation chunk ring-3 mapping. */
1091typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1092/** Pointer to an allocation chunk ring-3 mapping pointer. */
1093typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1094
1095/**
1096 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1097 *
1098 * The primary tree (Core) uses the chunk id as key.
1099 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1100 */
1101typedef struct PGMCHUNKR3MAP
1102{
1103 /** The key is the chunk id. */
1104 AVLU32NODECORE Core;
1105 /** The key is the ageing sequence number. */
1106 AVLLU32NODECORE AgeCore;
1107 /** The current age thingy. */
1108 uint32_t iAge;
1109 /** The current reference count. */
1110 uint32_t volatile cRefs;
1111 /** The current permanent reference count. */
1112 uint32_t volatile cPermRefs;
1113 /** The mapping address. */
1114 void *pv;
1115} PGMCHUNKR3MAP;
1116
1117/**
1118 * Allocation chunk ring-3 mapping TLB entry.
1119 */
1120typedef struct PGMCHUNKR3MAPTLBE
1121{
1122 /** The chunk id. */
1123 uint32_t volatile idChunk;
1124#if HC_ARCH_BITS == 64
1125 uint32_t u32Padding; /**< alignment padding. */
1126#endif
1127 /** The chunk map. */
1128 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1129} PGMCHUNKR3MAPTLBE;
1130/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1131typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1132
1133/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1134 * @remark Must be a power of two value. */
1135#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1136
1137/**
1138 * Allocation chunk ring-3 mapping TLB.
1139 *
1140 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1141 * At first glance this might look kinda odd since AVL trees are
1142 * supposed to give the most optimial lookup times of all trees
1143 * due to their balancing. However, take a tree with 1023 nodes
1144 * in it, that's 10 levels, meaning that most searches has to go
1145 * down 9 levels before they find what they want. This isn't fast
1146 * compared to a TLB hit. There is the factor of cache misses,
1147 * and of course the problem with trees and branch prediction.
1148 * This is why we use TLBs in front of most of the trees.
1149 *
1150 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1151 * difficult when we switch to inlined AVL trees (from kStuff).
1152 */
1153typedef struct PGMCHUNKR3MAPTLB
1154{
1155 /** The TLB entries. */
1156 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1157} PGMCHUNKR3MAPTLB;
1158
1159/**
1160 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1161 * @returns Chunk TLB index.
1162 * @param idChunk The Chunk ID.
1163 */
1164#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1165
1166
1167/**
1168 * Ring-3 guest page mapping TLB entry.
1169 * @remarks used in ring-0 as well at the moment.
1170 */
1171typedef struct PGMPAGER3MAPTLBE
1172{
1173 /** Address of the page. */
1174 RTGCPHYS volatile GCPhys;
1175 /** The guest page. */
1176 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1177 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1178 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1179 /** The address */
1180 R3R0PTRTYPE(void *) volatile pv;
1181#if HC_ARCH_BITS == 32
1182 uint32_t u32Padding; /**< alignment padding. */
1183#endif
1184} PGMPAGER3MAPTLBE;
1185/** Pointer to an entry in the HC physical TLB. */
1186typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1187
1188
1189/** The number of entries in the ring-3 guest page mapping TLB.
1190 * @remarks The value must be a power of two. */
1191#define PGM_PAGER3MAPTLB_ENTRIES 64
1192
1193/**
1194 * Ring-3 guest page mapping TLB.
1195 * @remarks used in ring-0 as well at the moment.
1196 */
1197typedef struct PGMPAGER3MAPTLB
1198{
1199 /** The TLB entries. */
1200 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1201} PGMPAGER3MAPTLB;
1202/** Pointer to the ring-3 guest page mapping TLB. */
1203typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1204
1205/**
1206 * Calculates the index of the TLB entry for the specified guest page.
1207 * @returns Physical TLB index.
1208 * @param GCPhys The guest physical address.
1209 */
1210#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1211
1212
1213/** @name Context neutrual page mapper TLB.
1214 *
1215 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1216 * code is writting in a kind of context neutrual way. Time will show whether
1217 * this actually makes sense or not...
1218 *
1219 * @{ */
1220/** @typedef PPGMPAGEMAPTLB
1221 * The page mapper TLB pointer type for the current context. */
1222/** @typedef PPGMPAGEMAPTLB
1223 * The page mapper TLB entry pointer type for the current context. */
1224/** @typedef PPGMPAGEMAPTLB
1225 * The page mapper TLB entry pointer pointer type for the current context. */
1226/** @def PGMPAGEMAPTLB_ENTRIES
1227 * The number of TLB entries in the page mapper TLB for the current context. */
1228/** @def PGM_PAGEMAPTLB_IDX
1229 * Calculate the TLB index for a guest physical address.
1230 * @returns The TLB index.
1231 * @param GCPhys The guest physical address. */
1232/** @typedef PPGMPAGEMAP
1233 * Pointer to a page mapper unit for current context. */
1234/** @typedef PPPGMPAGEMAP
1235 * Pointer to a page mapper unit pointer for current context. */
1236#ifdef IN_GC
1237// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1238// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1239// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1240# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1241# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1242 typedef void * PPGMPAGEMAP;
1243 typedef void ** PPPGMPAGEMAP;
1244//#elif IN_RING0
1245// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1246// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1247// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1248//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1249//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1250// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1251// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1252#else
1253 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1254 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1255 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1256# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1257# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1258 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1259 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1260#endif
1261/** @} */
1262
1263
1264/** @name PGM Pool Indexes.
1265 * Aka. the unique shadow page identifier.
1266 * @{ */
1267/** NIL page pool IDX. */
1268#define NIL_PGMPOOL_IDX 0
1269/** The first normal index. */
1270#define PGMPOOL_IDX_FIRST_SPECIAL 1
1271/** Page directory (32-bit root). */
1272#define PGMPOOL_IDX_PD 1
1273/** The extended PAE page directory (2048 entries, works as root currently). */
1274#define PGMPOOL_IDX_PAE_PD 2
1275 /** PAE Page Directory Table 0. */
1276#define PGMPOOL_IDX_PAE_PD_0 3
1277 /** PAE Page Directory Table 1. */
1278#define PGMPOOL_IDX_PAE_PD_1 4
1279 /** PAE Page Directory Table 2. */
1280#define PGMPOOL_IDX_PAE_PD_2 5
1281 /** PAE Page Directory Table 3. */
1282#define PGMPOOL_IDX_PAE_PD_3 6
1283/** Page Directory Pointer Table (PAE root, not currently used). */
1284#define PGMPOOL_IDX_PDPT 7
1285/** Page Map Level-4 (64-bit root). */
1286#define PGMPOOL_IDX_PML4 8
1287/** The first normal index. */
1288#define PGMPOOL_IDX_FIRST 9
1289/** The last valid index. (inclusive, 14 bits) */
1290#define PGMPOOL_IDX_LAST 0x3fff
1291/** @} */
1292
1293/** The NIL index for the parent chain. */
1294#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1295
1296/**
1297 * Node in the chain linking a shadowed page to it's parent (user).
1298 */
1299#pragma pack(1)
1300typedef struct PGMPOOLUSER
1301{
1302 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1303 uint16_t iNext;
1304 /** The user page index. */
1305 uint16_t iUser;
1306 /** Index into the user table. */
1307 uint16_t iUserTable;
1308} PGMPOOLUSER, *PPGMPOOLUSER;
1309typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1310#pragma pack()
1311
1312
1313/** The NIL index for the phys ext chain. */
1314#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1315
1316/**
1317 * Node in the chain of physical cross reference extents.
1318 */
1319#pragma pack(1)
1320typedef struct PGMPOOLPHYSEXT
1321{
1322 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1323 uint16_t iNext;
1324 /** The user page index. */
1325 uint16_t aidx[3];
1326} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1327typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1328#pragma pack()
1329
1330
1331/**
1332 * The kind of page that's being shadowed.
1333 */
1334typedef enum PGMPOOLKIND
1335{
1336 /** The virtual invalid 0 entry. */
1337 PGMPOOLKIND_INVALID = 0,
1338 /** The entry is free (=unused). */
1339 PGMPOOLKIND_FREE,
1340
1341 /** Shw: 32-bit page table; Gst: no paging */
1342 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1343 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1344 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1345 /** Shw: 32-bit page table; Gst: 4MB page. */
1346 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1347 /** Shw: PAE page table; Gst: no paging */
1348 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1349 /** Shw: PAE page table; Gst: 32-bit page table. */
1350 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1351 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1352 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1353 /** Shw: PAE page table; Gst: PAE page table. */
1354 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1355 /** Shw: PAE page table; Gst: 2MB page. */
1356 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1357
1358 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1359 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1360 /** Shw: PAE page directory; Gst: PAE page directory. */
1361 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1362
1363 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1364 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1365 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1366 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1367
1368 /** Shw: Root 32-bit page directory. */
1369 PGMPOOLKIND_ROOT_32BIT_PD,
1370 /** Shw: Root PAE page directory */
1371 PGMPOOLKIND_ROOT_PAE_PD,
1372 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1373 PGMPOOLKIND_ROOT_PDPT,
1374 /** Shw: Root page map level-4 table. */
1375 PGMPOOLKIND_ROOT_PML4,
1376
1377 /** The last valid entry. */
1378 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PML4
1379} PGMPOOLKIND;
1380
1381
1382/**
1383 * The tracking data for a page in the pool.
1384 */
1385typedef struct PGMPOOLPAGE
1386{
1387 /** AVL node code with the (HC) physical address of this page. */
1388 AVLOHCPHYSNODECORE Core;
1389 /** Pointer to the HC mapping of the page. */
1390 R3R0PTRTYPE(void *) pvPageHC;
1391 /** The guest physical address. */
1392 RTGCPHYS GCPhys;
1393 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1394 uint8_t enmKind;
1395 uint8_t bPadding;
1396 /** The index of this page. */
1397 uint16_t idx;
1398 /** The next entry in the list this page currently resides in.
1399 * It's either in the free list or in the GCPhys hash. */
1400 uint16_t iNext;
1401#ifdef PGMPOOL_WITH_USER_TRACKING
1402 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1403 uint16_t iUserHead;
1404 /** The number of present entries. */
1405 uint16_t cPresent;
1406 /** The first entry in the table which is present. */
1407 uint16_t iFirstPresent;
1408#endif
1409#ifdef PGMPOOL_WITH_MONITORING
1410 /** The number of modifications to the monitored page. */
1411 uint16_t cModifications;
1412 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1413 uint16_t iModifiedNext;
1414 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1415 uint16_t iModifiedPrev;
1416 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1417 uint16_t iMonitoredNext;
1418 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1419 uint16_t iMonitoredPrev;
1420#endif
1421#ifdef PGMPOOL_WITH_CACHE
1422 /** The next page in the age list. */
1423 uint16_t iAgeNext;
1424 /** The previous page in the age list. */
1425 uint16_t iAgePrev;
1426#endif /* PGMPOOL_WITH_CACHE */
1427 /** Used to indicate that the page is zeroed. */
1428 bool fZeroed;
1429 /** Used to indicate that a PT has non-global entries. */
1430 bool fSeenNonGlobal;
1431 /** Used to indicate that we're monitoring writes to the guest page. */
1432 bool fMonitored;
1433 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1434 * (All pages are in the age list.) */
1435 bool fCached;
1436 /** This is used by the R3 access handlers when invoked by an async thread.
1437 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1438 bool volatile fReusedFlushPending;
1439 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1440 * In these cases the access handler acts differently and will check
1441 * for mapping conflicts like the normal CR3 handler.
1442 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1443 * replaced by a list of pages which share access handler.
1444 */
1445 bool fCR3Mix;
1446} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1447
1448
1449#ifdef PGMPOOL_WITH_CACHE
1450/** The hash table size. */
1451# define PGMPOOL_HASH_SIZE 0x40
1452/** The hash function. */
1453# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1454#endif
1455
1456
1457/**
1458 * The shadow page pool instance data.
1459 *
1460 * It's all one big allocation made at init time, except for the
1461 * pages that is. The user nodes follows immediatly after the
1462 * page structures.
1463 */
1464typedef struct PGMPOOL
1465{
1466 /** The VM handle - HC Ptr. */
1467 R3R0PTRTYPE(PVM) pVMHC;
1468 /** The VM handle - GC Ptr. */
1469 GCPTRTYPE(PVM) pVMGC;
1470 /** The max pool size. This includes the special IDs. */
1471 uint16_t cMaxPages;
1472 /** The current pool size. */
1473 uint16_t cCurPages;
1474 /** The head of the free page list. */
1475 uint16_t iFreeHead;
1476 /* Padding. */
1477 uint16_t u16Padding;
1478#ifdef PGMPOOL_WITH_USER_TRACKING
1479 /** Head of the chain of free user nodes. */
1480 uint16_t iUserFreeHead;
1481 /** The number of user nodes we've allocated. */
1482 uint16_t cMaxUsers;
1483 /** The number of present page table entries in the entire pool. */
1484 uint32_t cPresent;
1485 /** Pointer to the array of user nodes - GC pointer. */
1486 GCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1487 /** Pointer to the array of user nodes - HC pointer. */
1488 R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1489#endif /* PGMPOOL_WITH_USER_TRACKING */
1490#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1491 /** Head of the chain of free phys ext nodes. */
1492 uint16_t iPhysExtFreeHead;
1493 /** The number of user nodes we've allocated. */
1494 uint16_t cMaxPhysExts;
1495 /** Pointer to the array of physical xref extent - GC pointer. */
1496 GCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1497 /** Pointer to the array of physical xref extent nodes - HC pointer. */
1498 R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1499#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1500#ifdef PGMPOOL_WITH_CACHE
1501 /** Hash table for GCPhys addresses. */
1502 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1503 /** The head of the age list. */
1504 uint16_t iAgeHead;
1505 /** The tail of the age list. */
1506 uint16_t iAgeTail;
1507 /** Set if the cache is enabled. */
1508 bool fCacheEnabled;
1509#endif /* PGMPOOL_WITH_CACHE */
1510#ifdef PGMPOOL_WITH_MONITORING
1511 /** Head of the list of modified pages. */
1512 uint16_t iModifiedHead;
1513 /** The current number of modified pages. */
1514 uint16_t cModifiedPages;
1515 /** Access handler, GC. */
1516 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1517 /** Access handler, R0. */
1518 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1519 /** Access handler, R3. */
1520 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1521 /** The access handler description (HC ptr). */
1522 R3PTRTYPE(const char *) pszAccessHandler;
1523#endif /* PGMPOOL_WITH_MONITORING */
1524 /** The number of pages currently in use. */
1525 uint16_t cUsedPages;
1526#ifdef VBOX_WITH_STATISTICS
1527 /** The high wather mark for cUsedPages. */
1528 uint16_t cUsedPagesHigh;
1529 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1530 /** Profiling pgmPoolAlloc(). */
1531 STAMPROFILEADV StatAlloc;
1532 /** Profiling pgmPoolClearAll(). */
1533 STAMPROFILE StatClearAll;
1534 /** Profiling pgmPoolFlushAllInt(). */
1535 STAMPROFILE StatFlushAllInt;
1536 /** Profiling pgmPoolFlushPage(). */
1537 STAMPROFILE StatFlushPage;
1538 /** Profiling pgmPoolFree(). */
1539 STAMPROFILE StatFree;
1540 /** Profiling time spent zeroing pages. */
1541 STAMPROFILE StatZeroPage;
1542# ifdef PGMPOOL_WITH_USER_TRACKING
1543 /** Profiling of pgmPoolTrackDeref. */
1544 STAMPROFILE StatTrackDeref;
1545 /** Profiling pgmTrackFlushGCPhysPT. */
1546 STAMPROFILE StatTrackFlushGCPhysPT;
1547 /** Profiling pgmTrackFlushGCPhysPTs. */
1548 STAMPROFILE StatTrackFlushGCPhysPTs;
1549 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1550 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1551 /** Number of times we've been out of user records. */
1552 STAMCOUNTER StatTrackFreeUpOneUser;
1553# endif
1554# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1555 /** Profiling deref activity related tracking GC physical pages. */
1556 STAMPROFILE StatTrackDerefGCPhys;
1557 /** Number of linear searches for a HCPhys in the ram ranges. */
1558 STAMCOUNTER StatTrackLinearRamSearches;
1559 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1560 STAMCOUNTER StamTrackPhysExtAllocFailures;
1561# endif
1562# ifdef PGMPOOL_WITH_MONITORING
1563 /** Profiling the GC PT access handler. */
1564 STAMPROFILE StatMonitorGC;
1565 /** Times we've failed interpreting the instruction. */
1566 STAMCOUNTER StatMonitorGCEmulateInstr;
1567 /** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1568 STAMPROFILE StatMonitorGCFlushPage;
1569 /** Times we've detected fork(). */
1570 STAMCOUNTER StatMonitorGCFork;
1571 /** Profiling the GC access we've handled (except REP STOSD). */
1572 STAMPROFILE StatMonitorGCHandled;
1573 /** Times we've failed interpreting a patch code instruction. */
1574 STAMCOUNTER StatMonitorGCIntrFailPatch1;
1575 /** Times we've failed interpreting a patch code instruction during flushing. */
1576 STAMCOUNTER StatMonitorGCIntrFailPatch2;
1577 /** The number of times we've seen rep prefixes we can't handle. */
1578 STAMCOUNTER StatMonitorGCRepPrefix;
1579 /** Profiling the REP STOSD cases we've handled. */
1580 STAMPROFILE StatMonitorGCRepStosd;
1581
1582 /** Profiling the HC PT access handler. */
1583 STAMPROFILE StatMonitorHC;
1584 /** Times we've failed interpreting the instruction. */
1585 STAMCOUNTER StatMonitorHCEmulateInstr;
1586 /** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1587 STAMPROFILE StatMonitorHCFlushPage;
1588 /** Times we've detected fork(). */
1589 STAMCOUNTER StatMonitorHCFork;
1590 /** Profiling the HC access we've handled (except REP STOSD). */
1591 STAMPROFILE StatMonitorHCHandled;
1592 /** The number of times we've seen rep prefixes we can't handle. */
1593 STAMCOUNTER StatMonitorHCRepPrefix;
1594 /** Profiling the REP STOSD cases we've handled. */
1595 STAMPROFILE StatMonitorHCRepStosd;
1596 /** The number of times we're called in an async thread an need to flush. */
1597 STAMCOUNTER StatMonitorHCAsync;
1598 /** The high wather mark for cModifiedPages. */
1599 uint16_t cModifiedPagesHigh;
1600 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1601# endif
1602# ifdef PGMPOOL_WITH_CACHE
1603 /** The number of cache hits. */
1604 STAMCOUNTER StatCacheHits;
1605 /** The number of cache misses. */
1606 STAMCOUNTER StatCacheMisses;
1607 /** The number of times we've got a conflict of 'kind' in the cache. */
1608 STAMCOUNTER StatCacheKindMismatches;
1609 /** Number of times we've been out of pages. */
1610 STAMCOUNTER StatCacheFreeUpOne;
1611 /** The number of cacheable allocations. */
1612 STAMCOUNTER StatCacheCacheable;
1613 /** The number of uncacheable allocations. */
1614 STAMCOUNTER StatCacheUncacheable;
1615# endif
1616#elif HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1617 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1618#endif
1619 /** The AVL tree for looking up a page by its HC physical address. */
1620 AVLOHCPHYSTREE HCPhysTree;
1621 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1622 /** Array of pages. (cMaxPages in length)
1623 * The Id is the index into thist array.
1624 */
1625 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1626} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1627
1628
1629/** @def PGMPOOL_PAGE_2_PTR
1630 * Maps a pool page pool into the current context.
1631 *
1632 * @returns VBox status code.
1633 * @param pVM The VM handle.
1634 * @param pPage The pool page.
1635 *
1636 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1637 * small page window employeed by that function. Be careful.
1638 * @remark There is no need to assert on the result.
1639 */
1640#ifdef IN_GC
1641# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1642#else
1643# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1644#endif
1645
1646
1647/**
1648 * Trees are using self relative offsets as pointers.
1649 * So, all its data, including the root pointer, must be in the heap for HC and GC
1650 * to have the same layout.
1651 */
1652typedef struct PGMTREES
1653{
1654 /** Physical access handlers (AVL range+offsetptr tree). */
1655 AVLROGCPHYSTREE PhysHandlers;
1656 /** Virtual access handlers (AVL range + GC ptr tree). */
1657 AVLROGCPTRTREE VirtHandlers;
1658 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1659 AVLROGCPHYSTREE PhysToVirtHandlers;
1660 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1661 AVLROGCPTRTREE HyperVirtHandlers;
1662} PGMTREES;
1663/** Pointer to PGM trees. */
1664typedef PGMTREES *PPGMTREES;
1665
1666
1667/** @name Paging mode macros
1668 * @{ */
1669#ifdef IN_GC
1670# define PGM_CTX(a,b) a##GC##b
1671# define PGM_CTX_STR(a,b) a "GC" b
1672# define PGM_CTX_DECL(type) PGMGCDECL(type)
1673#else
1674# ifdef IN_RING3
1675# define PGM_CTX(a,b) a##R3##b
1676# define PGM_CTX_STR(a,b) a "R3" b
1677# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1678# else
1679# define PGM_CTX(a,b) a##R0##b
1680# define PGM_CTX_STR(a,b) a "R0" b
1681# define PGM_CTX_DECL(type) PGMDECL(type)
1682# endif
1683#endif
1684
1685#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1686#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1687#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1688#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1689#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1690#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1691#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1692#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1693#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1694#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1695#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1696#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1697#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1698#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1699#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1700#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1701#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1702
1703#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1704#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1705#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1706#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1707#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1708#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1709#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1710#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1711#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1712#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1713#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1714
1715/* Shw_Gst */
1716#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1717#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1718#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1719#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1720#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1721#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1722#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1723#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1724#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1725#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1726#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1727#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1728#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1729#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1730#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1731#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1732#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1733#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1734#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1735#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1736#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1737#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1738#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1739#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1740#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1741#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1742#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1743#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1744/** @} */
1745
1746/**
1747 * Data for each paging mode.
1748 */
1749typedef struct PGMMODEDATA
1750{
1751 /** The guest mode type. */
1752 uint32_t uGstType;
1753 /** The shadow mode type. */
1754 uint32_t uShwType;
1755
1756 /** @name Function pointers for Shadow paging.
1757 * @{
1758 */
1759 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1760 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1761 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1762 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1763
1764 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1765 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1766
1767 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1768 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1769 /** @} */
1770
1771 /** @name Function pointers for Guest paging.
1772 * @{
1773 */
1774 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1775 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1776 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1777 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1778 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1779 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1780 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1781 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1782 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1783 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1784 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1785 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1786 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1787
1788 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1789 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1790 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1791 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1792 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1793 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1794 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1795 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1796 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1797
1798 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1799 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1800 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1801 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1802 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1803 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1804 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1805 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1806 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1807 /** @} */
1808
1809 /** @name Function pointers for Both Shadow and Guest paging.
1810 * @{
1811 */
1812 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1813 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1814 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1815 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1816 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1817 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1818 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1819#ifdef VBOX_STRICT
1820 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1821#endif
1822
1823 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1824 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1825 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1826 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1827 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1828 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1829#ifdef VBOX_STRICT
1830 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1831#endif
1832
1833 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1834 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1835 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1836 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1837 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1838 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1839#ifdef VBOX_STRICT
1840 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1841#endif
1842 /** @} */
1843} PGMMODEDATA, *PPGMMODEDATA;
1844
1845
1846
1847/**
1848 * Converts a PGM pointer into a VM pointer.
1849 * @returns Pointer to the VM structure the PGM is part of.
1850 * @param pPGM Pointer to PGM instance data.
1851 */
1852#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1853
1854/**
1855 * PGM Data (part of VM)
1856 */
1857typedef struct PGM
1858{
1859 /** Offset to the VM structure. */
1860 RTINT offVM;
1861
1862 /*
1863 * This will be redefined at least two more times before we're done, I'm sure.
1864 * The current code is only to get on with the coding.
1865 * - 2004-06-10: initial version, bird.
1866 * - 2004-07-02: 1st time, bird.
1867 * - 2004-10-18: 2nd time, bird.
1868 * - 2005-07-xx: 3rd time, bird.
1869 */
1870
1871 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1872 GCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1873 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1874 GCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1875
1876 /** The host paging mode. (This is what SUPLib reports.) */
1877 SUPPAGINGMODE enmHostMode;
1878 /** The shadow paging mode. */
1879 PGMMODE enmShadowMode;
1880 /** The guest paging mode. */
1881 PGMMODE enmGuestMode;
1882
1883 /** The current physical address representing in the guest CR3 register. */
1884 RTGCPHYS GCPhysCR3;
1885 /** Pointer to the 5 page CR3 content mapping.
1886 * The first page is always the CR3 (in some form) while the 4 other pages
1887 * are used of the PDs in PAE mode. */
1888 RTGCPTR GCPtrCR3Mapping;
1889#if HC_ARCH_BITS == 64
1890 uint32_t u32Alignment;
1891#endif
1892 /** The physical address of the currently monitored guest CR3 page.
1893 * When this value is NIL_RTGCPHYS no page is being monitored. */
1894 RTGCPHYS GCPhysGstCR3Monitored;
1895
1896 /** @name 32-bit Guest Paging.
1897 * @{ */
1898 /** The guest's page directory, HC pointer. */
1899 R3R0PTRTYPE(PX86PD) pGuestPDHC;
1900 /** The guest's page directory, static GC mapping. */
1901 GCPTRTYPE(PX86PD) pGuestPDGC;
1902 /** @} */
1903
1904 /** @name PAE Guest Paging.
1905 * @{ */
1906 /** The guest's page directory pointer table, static GC mapping. */
1907 GCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
1908 /** The guest's page directory pointer table, HC pointer. */
1909 R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1910 /** The guest's page directories, HC pointers.
1911 * These are individual pointers and don't have to be adjecent.
1912 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1913 R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1914 /** The guest's page directories, static GC mapping.
1915 * Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1916 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1917 GCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1918 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1919 RTGCPHYS aGCPhysGstPaePDs[4];
1920 /** The physical addresses of the monitored guest page directories (PAE). */
1921 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1922 /** @} */
1923
1924 /** @name AMD64 Guest Paging.
1925 * @{ */
1926 /** The guest's page directory pointer table, HC pointer. */
1927 R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
1928 /** @} */
1929
1930 /** @name 32-bit Shadow Paging
1931 * @{ */
1932 /** The 32-Bit PD - HC Ptr. */
1933 R3R0PTRTYPE(PX86PD) pHC32BitPD;
1934 /** The 32-Bit PD - GC Ptr. */
1935 GCPTRTYPE(PX86PD) pGC32BitPD;
1936#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1937 uint32_t u32Padding1; /**< alignment padding. */
1938#endif
1939 /** The Physical Address (HC) of the 32-Bit PD. */
1940 RTHCPHYS HCPhys32BitPD;
1941 /** @} */
1942
1943 /** @name PAE Shadow Paging
1944 * @{ */
1945 /** The four PDs for the low 4GB - HC Ptr.
1946 * Even though these are 4 pointers, what they point at is a single table.
1947 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
1948 R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
1949 /** The four PDs for the low 4GB - GC Ptr.
1950 * Same kind of mapping as apHCPaePDs. */
1951 GCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
1952 /** The Physical Address (HC) of the four PDs for the low 4GB.
1953 * These are *NOT* 4 contiguous pages. */
1954 RTHCPHYS aHCPhysPaePDs[4];
1955 /** The PAE PDP - HC Ptr. */
1956 R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
1957 /** The Physical Address (HC) of the PAE PDPT. */
1958 RTHCPHYS HCPhysPaePDPT;
1959 /** The PAE PDPT - GC Ptr. */
1960 GCPTRTYPE(PX86PDPT) pGCPaePDPT;
1961 /** @} */
1962
1963 /** @name AMD64 Shadow Paging
1964 * Extends PAE Paging.
1965 * @{ */
1966#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1967 RTGCPTR alignment5; /**< structure size alignment. */
1968#endif
1969 /** The Page Map Level 4 table - HC Ptr. */
1970 R3R0PTRTYPE(PX86PML4) pHCPaePML4;
1971 /** The Physical Address (HC) of the Page Map Level 4 table. */
1972 RTHCPHYS HCPhysPaePML4;
1973 /** @}*/
1974
1975 /** @name Function pointers for Shadow paging.
1976 * @{
1977 */
1978 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1979 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1980 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1981 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1982
1983 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1984 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1985
1986 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1987 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1988
1989 /** @} */
1990
1991 /** @name Function pointers for Guest paging.
1992 * @{
1993 */
1994 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1995 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1996 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1997 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1998 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1999 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2000 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2001 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2002 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2003 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2004 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2005 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2006 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2007
2008 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2009 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2010 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2011 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2012 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
2013 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2014 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
2015 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
2016 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
2017#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2018 RTGCPTR alignment3; /**< structure size alignment. */
2019#endif
2020
2021 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2022 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2023 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2024 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2025 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2026 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2027 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2028 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2029 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2030 /** @} */
2031
2032 /** @name Function pointers for Both Shadow and Guest paging.
2033 * @{
2034 */
2035 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2036 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2037 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2038 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2039 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2040 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2041 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2042 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2043
2044 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2045 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2046 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2047 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2048 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2049 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2050 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2051
2052 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2053 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2054 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2055 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2056 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2057 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2058 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2059#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2060 RTGCPTR alignment2; /**< structure size alignment. */
2061#endif
2062 /** @} */
2063
2064 /** Pointer to SHW+GST mode data (function pointers).
2065 * The index into this table is made up from */
2066 R3PTRTYPE(PPGMMODEDATA) paModeData;
2067
2068 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2069 * This is sorted by physical address and contains no overlapping ranges. */
2070 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2071 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2072 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2073 /** GC pointer corresponding to PGM::pRamRangesR3. */
2074 GCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
2075 /** The configured RAM size. */
2076 RTUINT cbRamSize;
2077
2078 /** Pointer to the list of ROM ranges - for R3.
2079 * This is sorted by physical address and contains no overlapping ranges. */
2080 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2081 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2082 R0PTRTYPE(PPGMRAMRANGE) pRomRangesR0;
2083 /** GC pointer corresponding to PGM::pRomRangesR3. */
2084 GCPTRTYPE(PPGMRAMRANGE) pRomRangesGC;
2085 /** Alignment padding. */
2086 RTGCPTR GCPtrPadding2;
2087
2088 /** Pointer to the list of MMIO2 ranges - for R3.
2089 * Registration order. */
2090 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2091
2092 /** PGM offset based trees - HC Ptr. */
2093 R3R0PTRTYPE(PPGMTREES) pTreesHC;
2094 /** PGM offset based trees - GC Ptr. */
2095 GCPTRTYPE(PPGMTREES) pTreesGC;
2096
2097 /** Linked list of GC mappings - for GC.
2098 * The list is sorted ascending on address.
2099 */
2100 GCPTRTYPE(PPGMMAPPING) pMappingsGC;
2101 /** Linked list of GC mappings - for HC.
2102 * The list is sorted ascending on address.
2103 */
2104 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2105 /** Linked list of GC mappings - for R0.
2106 * The list is sorted ascending on address.
2107 */
2108 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2109
2110 /** If set no conflict checks are required. (boolean) */
2111 bool fMappingsFixed;
2112 /** If set, then no mappings are put into the shadow page table. (boolean) */
2113 bool fDisableMappings;
2114 /** Size of fixed mapping */
2115 uint32_t cbMappingFixed;
2116 /** Base address (GC) of fixed mapping */
2117 RTGCPTR GCPtrMappingFixed;
2118#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2119 uint32_t u32Padding0; /**< alignment padding. */
2120#endif
2121
2122
2123 /** @name Intermediate Context
2124 * @{ */
2125 /** Pointer to the intermediate page directory - Normal. */
2126 R3PTRTYPE(PX86PD) pInterPD;
2127 /** Pointer to the intermedate page tables - Normal.
2128 * There are two page tables, one for the identity mapping and one for
2129 * the host context mapping (of the core code). */
2130 R3PTRTYPE(PX86PT) apInterPTs[2];
2131 /** Pointer to the intermedate page tables - PAE. */
2132 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2133 /** Pointer to the intermedate page directory - PAE. */
2134 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2135 /** Pointer to the intermedate page directory - PAE. */
2136 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2137 /** Pointer to the intermedate page-map level 4 - AMD64. */
2138 R3PTRTYPE(PX86PML4) pInterPaePML4;
2139 /** Pointer to the intermedate page directory - AMD64. */
2140 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2141 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2142 RTHCPHYS HCPhysInterPD;
2143 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2144 RTHCPHYS HCPhysInterPaePDPT;
2145 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2146 RTHCPHYS HCPhysInterPaePML4;
2147 /** @} */
2148
2149 /** Base address of the dynamic page mapping area.
2150 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2151 */
2152 GCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2153 /** The index of the last entry used in the dynamic page mapping area. */
2154 RTUINT iDynPageMapLast;
2155 /** Cache containing the last entries in the dynamic page mapping area.
2156 * The cache size is covering half of the mapping area. */
2157 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2158
2159 /** A20 gate mask.
2160 * Our current approach to A20 emulation is to let REM do it and don't bother
2161 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2162 * But whould need arrise, we'll subject physical addresses to this mask. */
2163 RTGCPHYS GCPhysA20Mask;
2164 /** A20 gate state - boolean! */
2165 RTUINT fA20Enabled;
2166
2167 /** What needs syncing (PGM_SYNC_*).
2168 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2169 * PGMFlushTLB, and PGMR3Load. */
2170 RTUINT fSyncFlags;
2171
2172 /** PGM critical section.
2173 * This protects the physical & virtual access handlers, ram ranges,
2174 * and the page flag updating (some of it anyway).
2175 */
2176 PDMCRITSECT CritSect;
2177
2178 /** Shadow Page Pool - HC Ptr. */
2179 R3R0PTRTYPE(PPGMPOOL) pPoolHC;
2180 /** Shadow Page Pool - GC Ptr. */
2181 GCPTRTYPE(PPGMPOOL) pPoolGC;
2182
2183 /** We're not in a state which permits writes to guest memory.
2184 * (Only used in strict builds.) */
2185 bool fNoMorePhysWrites;
2186
2187 /** Flush the cache on the next access. */
2188 bool fPhysCacheFlushPending;
2189/** @todo r=bird: Fix member names!*/
2190 /** PGMPhysRead cache */
2191 PGMPHYSCACHE pgmphysreadcache;
2192 /** PGMPhysWrite cache */
2193 PGMPHYSCACHE pgmphyswritecache;
2194
2195 /**
2196 * Data associated with managing the ring-3 mappings of the allocation chunks.
2197 */
2198 struct
2199 {
2200 /** The chunk tree, ordered by chunk id. */
2201 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2202 /** The chunk mapping TLB. */
2203 PGMCHUNKR3MAPTLB Tlb;
2204 /** The number of mapped chunks. */
2205 uint32_t c;
2206 /** The maximum number of mapped chunks.
2207 * @cfgm PGM/MaxRing3Chunks */
2208 uint32_t cMax;
2209 /** The chunk age tree, ordered by ageing sequence number. */
2210 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2211 /** The current time. */
2212 uint32_t iNow;
2213 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2214 uint32_t AgeingCountdown;
2215 } ChunkR3Map;
2216
2217 /**
2218 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2219 */
2220 PGMPAGER3MAPTLB PhysTlbHC;
2221
2222 /** @name The zero page.
2223 * @{ */
2224 /** The host physical address of the zero page. */
2225 RTHCPHYS HCPhysZeroPg;
2226 /** The ring-3 mapping of the zero page. */
2227 RTR3PTR pvZeroPgR3;
2228 /** The ring-0 mapping of the zero page. */
2229 RTR0PTR pvZeroPgR0;
2230 /** The GC mapping of the zero page. */
2231 RTGCPTR pvZeroPgGC;
2232#if GC_ARCH_BITS != 32
2233 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2234#endif
2235 /** @}*/
2236
2237 /** The number of handy pages. */
2238 uint32_t cHandyPages;
2239 /**
2240 * Array of handy pages.
2241 *
2242 * This array is used in a two way communication between pgmPhysAllocPage
2243 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2244 * an intermediary.
2245 *
2246 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2247 * (The current size of 32 pages, means 128 KB of handy memory.)
2248 */
2249 GMMPAGEDESC aHandyPages[32];
2250
2251 /** @name Release Statistics
2252 * @{ */
2253 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2254 uint32_t cPrivatePages; /**< The number of private pages. */
2255 uint32_t cSharedPages; /**< The number of shared pages. */
2256 uint32_t cZeroPages; /**< The number of zero backed pages. */
2257 /** The number of times the guest has switched mode since last reset or statistics reset. */
2258 STAMCOUNTER cGuestModeChanges;
2259 /** @} */
2260
2261#ifdef VBOX_WITH_STATISTICS
2262 /** GC: Which statistic this \#PF should be attributed to. */
2263 GCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
2264 RTGCPTR padding0;
2265 /** HC: Which statistic this \#PF should be attributed to. */
2266 R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
2267 RTHCPTR padding1;
2268 STAMPROFILE StatGCTrap0e; /**< GC: PGMGCTrap0eHandler() profiling. */
2269 STAMPROFILE StatTrap0eCSAM; /**< Profiling of the Trap0eHandler body when the cause is CSAM. */
2270 STAMPROFILE StatTrap0eDirtyAndAccessedBits; /**< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2271 STAMPROFILE StatTrap0eGuestTrap; /**< Profiling of the Trap0eHandler body when the cause is a guest trap. */
2272 STAMPROFILE StatTrap0eHndPhys; /**< Profiling of the Trap0eHandler body when the cause is a physical handler. */
2273 STAMPROFILE StatTrap0eHndVirt; /**< Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2274 STAMPROFILE StatTrap0eHndUnhandled; /**< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2275 STAMPROFILE StatTrap0eMisc; /**< Profiling of the Trap0eHandler body when the cause is not known. */
2276 STAMPROFILE StatTrap0eOutOfSync; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2277 STAMPROFILE StatTrap0eOutOfSyncHndPhys; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2278 STAMPROFILE StatTrap0eOutOfSyncHndVirt; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2279 STAMPROFILE StatTrap0eOutOfSyncObsHnd; /**< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2280 STAMPROFILE StatTrap0eSyncPT; /**< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2281
2282 STAMCOUNTER StatTrap0eMapHandler; /**< Number of traps due to access handlers in mappings. */
2283 STAMCOUNTER StatGCTrap0eConflicts; /**< GC: The number of times \#PF was caused by an undetected conflict. */
2284
2285 STAMCOUNTER StatGCTrap0eUSNotPresentRead;
2286 STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
2287 STAMCOUNTER StatGCTrap0eUSWrite;
2288 STAMCOUNTER StatGCTrap0eUSReserved;
2289 STAMCOUNTER StatGCTrap0eUSNXE;
2290 STAMCOUNTER StatGCTrap0eUSRead;
2291
2292 STAMCOUNTER StatGCTrap0eSVNotPresentRead;
2293 STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
2294 STAMCOUNTER StatGCTrap0eSVWrite;
2295 STAMCOUNTER StatGCTrap0eSVReserved;
2296 STAMCOUNTER StatGCTrap0eSNXE;
2297
2298 STAMCOUNTER StatTrap0eWPEmulGC;
2299 STAMCOUNTER StatTrap0eWPEmulR3;
2300
2301 STAMCOUNTER StatGCTrap0eUnhandled;
2302 STAMCOUNTER StatGCTrap0eMap;
2303
2304 /** GC: PGMSyncPT() profiling. */
2305 STAMPROFILE StatGCSyncPT;
2306 /** GC: The number of times PGMSyncPT() needed to allocate page tables. */
2307 STAMCOUNTER StatGCSyncPTAlloc;
2308 /** GC: The number of times PGMSyncPT() detected conflicts. */
2309 STAMCOUNTER StatGCSyncPTConflict;
2310 /** GC: The number of times PGMSyncPT() failed. */
2311 STAMCOUNTER StatGCSyncPTFailed;
2312 /** GC: PGMGCInvalidatePage() profiling. */
2313 STAMPROFILE StatGCInvalidatePage;
2314 /** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
2315 STAMCOUNTER StatGCInvalidatePage4KBPages;
2316 /** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
2317 STAMCOUNTER StatGCInvalidatePage4MBPages;
2318 /** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
2319 STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
2320 /** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
2321 STAMCOUNTER StatGCInvalidatePagePDNAs;
2322 /** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
2323 STAMCOUNTER StatGCInvalidatePagePDNPs;
2324 /** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
2325 STAMCOUNTER StatGCInvalidatePagePDMappings;
2326 /** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2327 STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
2328 /** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2329 STAMCOUNTER StatGCInvalidatePageSkipped;
2330 /** GC: The number of times user page is out of sync was detected in GC. */
2331 STAMCOUNTER StatGCPageOutOfSyncUser;
2332 /** GC: The number of times supervisor page is out of sync was detected in GC. */
2333 STAMCOUNTER StatGCPageOutOfSyncSupervisor;
2334 /** GC: The number of dynamic page mapping cache hits */
2335 STAMCOUNTER StatDynMapCacheMisses;
2336 /** GC: The number of dynamic page mapping cache misses */
2337 STAMCOUNTER StatDynMapCacheHits;
2338 /** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
2339 STAMCOUNTER StatGCGuestCR3WriteHandled;
2340 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
2341 STAMCOUNTER StatGCGuestCR3WriteUnhandled;
2342 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
2343 STAMCOUNTER StatGCGuestCR3WriteConflict;
2344 /** GC: Number of out-of-sync handled pages. */
2345 STAMCOUNTER StatHandlersOutOfSync;
2346 /** GC: Number of traps due to physical access handlers. */
2347 STAMCOUNTER StatHandlersPhysical;
2348 /** GC: Number of traps due to virtual access handlers. */
2349 STAMCOUNTER StatHandlersVirtual;
2350 /** GC: Number of traps due to virtual access handlers found by physical address. */
2351 STAMCOUNTER StatHandlersVirtualByPhys;
2352 /** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2353 STAMCOUNTER StatHandlersVirtualUnmarked;
2354 /** GC: Number of traps due to access outside range of monitored page(s). */
2355 STAMCOUNTER StatHandlersUnhandled;
2356 /** GC: Number of traps due to access to invalid physical memory. */
2357 STAMCOUNTER StatHandlersInvalid;
2358
2359 /** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
2360 STAMCOUNTER StatGCGuestROMWriteHandled;
2361 /** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
2362 STAMCOUNTER StatGCGuestROMWriteUnhandled;
2363
2364 /** HC: PGMR3InvalidatePage() profiling. */
2365 STAMPROFILE StatHCInvalidatePage;
2366 /** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
2367 STAMCOUNTER StatHCInvalidatePage4KBPages;
2368 /** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
2369 STAMCOUNTER StatHCInvalidatePage4MBPages;
2370 /** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
2371 STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
2372 /** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
2373 STAMCOUNTER StatHCInvalidatePagePDNAs;
2374 /** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
2375 STAMCOUNTER StatHCInvalidatePagePDNPs;
2376 /** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
2377 STAMCOUNTER StatHCInvalidatePagePDMappings;
2378 /** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2379 STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
2380 /** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2381 STAMCOUNTER StatHCInvalidatePageSkipped;
2382 /** HC: PGMR3SyncPT() profiling. */
2383 STAMPROFILE StatHCSyncPT;
2384 /** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2385 STAMPROFILE StatHCResolveConflict;
2386 /** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2387 STAMCOUNTER StatHCDetectedConflicts;
2388 /** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2389 STAMCOUNTER StatHCGuestPDWrite;
2390 /** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2391 STAMCOUNTER StatHCGuestPDWriteConflict;
2392
2393 /** HC: The number of pages marked not present for accessed bit emulation. */
2394 STAMCOUNTER StatHCAccessedPage;
2395 /** HC: The number of pages marked read-only for dirty bit tracking. */
2396 STAMCOUNTER StatHCDirtyPage;
2397 /** HC: The number of pages marked read-only for dirty bit tracking. */
2398 STAMCOUNTER StatHCDirtyPageBig;
2399 /** HC: The number of traps generated for dirty bit tracking. */
2400 STAMCOUNTER StatHCDirtyPageTrap;
2401 /** HC: The number of pages already dirty or readonly. */
2402 STAMCOUNTER StatHCDirtyPageSkipped;
2403
2404 /** GC: The number of pages marked not present for accessed bit emulation. */
2405 STAMCOUNTER StatGCAccessedPage;
2406 /** GC: The number of pages marked read-only for dirty bit tracking. */
2407 STAMCOUNTER StatGCDirtyPage;
2408 /** GC: The number of pages marked read-only for dirty bit tracking. */
2409 STAMCOUNTER StatGCDirtyPageBig;
2410 /** GC: The number of traps generated for dirty bit tracking. */
2411 STAMCOUNTER StatGCDirtyPageTrap;
2412 /** GC: The number of pages already dirty or readonly. */
2413 STAMCOUNTER StatGCDirtyPageSkipped;
2414 /** GC: The number of pages marked dirty because of write accesses. */
2415 STAMCOUNTER StatGCDirtiedPage;
2416 /** GC: The number of pages already marked dirty because of write accesses. */
2417 STAMCOUNTER StatGCPageAlreadyDirty;
2418 /** GC: The number of real pages faults during dirty bit tracking. */
2419 STAMCOUNTER StatGCDirtyTrackRealPF;
2420
2421 /** GC: Profiling of the PGMTrackDirtyBit() body */
2422 STAMPROFILE StatGCDirtyBitTracking;
2423 /** HC: Profiling of the PGMTrackDirtyBit() body */
2424 STAMPROFILE StatHCDirtyBitTracking;
2425
2426 /** GC: Profiling of the PGMGstModifyPage() body */
2427 STAMPROFILE StatGCGstModifyPage;
2428 /** HC: Profiling of the PGMGstModifyPage() body */
2429 STAMPROFILE StatHCGstModifyPage;
2430
2431 /** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2432 STAMCOUNTER StatGCSyncPagePDNAs;
2433 /** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2434 STAMCOUNTER StatGCSyncPagePDOutOfSync;
2435 /** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2436 STAMCOUNTER StatHCSyncPagePDNAs;
2437 /** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2438 STAMCOUNTER StatHCSyncPagePDOutOfSync;
2439
2440 STAMCOUNTER StatSynPT4kGC;
2441 STAMCOUNTER StatSynPT4kHC;
2442 STAMCOUNTER StatSynPT4MGC;
2443 STAMCOUNTER StatSynPT4MHC;
2444
2445 /** Profiling of the PGMFlushTLB() body. */
2446 STAMPROFILE StatFlushTLB;
2447 /** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2448 STAMCOUNTER StatFlushTLBNewCR3;
2449 /** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2450 STAMCOUNTER StatFlushTLBNewCR3Global;
2451 /** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2452 STAMCOUNTER StatFlushTLBSameCR3;
2453 /** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2454 STAMCOUNTER StatFlushTLBSameCR3Global;
2455
2456 STAMPROFILE StatGCSyncCR3; /**< GC: PGMSyncCR3() profiling. */
2457 STAMPROFILE StatGCSyncCR3Handlers; /**< GC: Profiling of the PGMSyncCR3() update handler section. */
2458 STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /**< GC: Profiling of the virtual handler resets. */
2459 STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /**< GC: Profiling of the virtual handler updates. */
2460 STAMCOUNTER StatGCSyncCR3Global; /**< GC: The number of global CR3 syncs. */
2461 STAMCOUNTER StatGCSyncCR3NotGlobal; /**< GC: The number of non-global CR3 syncs. */
2462 STAMCOUNTER StatGCSyncCR3DstFreed; /**< GC: The number of times we've had to free a shadow entry. */
2463 STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /**< GC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2464 STAMCOUNTER StatGCSyncCR3DstNotPresent; /**< GC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2465 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /**< GC: The number of times a global page directory wasn't flushed. */
2466 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /**< GC: The number of times a page table with only global entries wasn't flushed. */
2467 STAMCOUNTER StatGCSyncCR3DstCacheHit; /**< GC: The number of times we got some kind of cache hit on a page table. */
2468
2469 STAMPROFILE StatHCSyncCR3; /**< HC: PGMSyncCR3() profiling. */
2470 STAMPROFILE StatHCSyncCR3Handlers; /**< HC: Profiling of the PGMSyncCR3() update handler section. */
2471 STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /**< HC: Profiling of the virtual handler resets. */
2472 STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /**< HC: Profiling of the virtual handler updates. */
2473 STAMCOUNTER StatHCSyncCR3Global; /**< HC: The number of global CR3 syncs. */
2474 STAMCOUNTER StatHCSyncCR3NotGlobal; /**< HC: The number of non-global CR3 syncs. */
2475 STAMCOUNTER StatHCSyncCR3DstFreed; /**< HC: The number of times we've had to free a shadow entry. */
2476 STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /**< HC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2477 STAMCOUNTER StatHCSyncCR3DstNotPresent; /**< HC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2478 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /**< HC: The number of times a global page directory wasn't flushed. */
2479 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /**< HC: The number of times a page table with only global entries wasn't flushed. */
2480 STAMCOUNTER StatHCSyncCR3DstCacheHit; /**< HC: The number of times we got some kind of cache hit on a page table. */
2481
2482 /** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2483 STAMPROFILE StatVirtHandleSearchByPhysGC;
2484 /** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2485 STAMPROFILE StatVirtHandleSearchByPhysHC;
2486 /** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2487 STAMCOUNTER StatHandlePhysicalReset;
2488
2489 STAMPROFILE StatCheckPageFault;
2490 STAMPROFILE StatLazySyncPT;
2491 STAMPROFILE StatMapping;
2492 STAMPROFILE StatOutOfSync;
2493 STAMPROFILE StatHandlers;
2494 STAMPROFILE StatEIPHandlers;
2495 STAMPROFILE StatHCPrefetch;
2496
2497# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2498 /** The number of first time shadowings. */
2499 STAMCOUNTER StatTrackVirgin;
2500 /** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2501 STAMCOUNTER StatTrackAliased;
2502 /** The number of times we're tracking using cRef2. */
2503 STAMCOUNTER StatTrackAliasedMany;
2504 /** The number of times we're hitting pages which has overflowed cRef2. */
2505 STAMCOUNTER StatTrackAliasedLots;
2506 /** The number of times the extent list grows to long. */
2507 STAMCOUNTER StatTrackOverflows;
2508 /** Profiling of SyncPageWorkerTrackDeref (expensive). */
2509 STAMPROFILE StatTrackDeref;
2510# endif
2511
2512 /** Ring-3/0 page mapper TLB hits. */
2513 STAMCOUNTER StatPageHCMapTlbHits;
2514 /** Ring-3/0 page mapper TLB misses. */
2515 STAMCOUNTER StatPageHCMapTlbMisses;
2516 /** Ring-3/0 chunk mapper TLB hits. */
2517 STAMCOUNTER StatChunkR3MapTlbHits;
2518 /** Ring-3/0 chunk mapper TLB misses. */
2519 STAMCOUNTER StatChunkR3MapTlbMisses;
2520 /** Times a shared page has been replaced by a private one. */
2521 STAMCOUNTER StatPageReplaceShared;
2522 /** Times the zero page has been replaced by a private one. */
2523 STAMCOUNTER StatPageReplaceZero;
2524 /** The number of times we've executed GMMR3AllocateHandyPages. */
2525 STAMCOUNTER StatPageHandyAllocs;
2526
2527 /** Allocated mbs of guest ram */
2528 STAMCOUNTER StatDynRamTotal;
2529 /** Nr of pgmr3PhysGrowRange calls. */
2530 STAMCOUNTER StatDynRamGrow;
2531
2532 STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2533 STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2534 STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2535#endif
2536} PGM, *PPGM;
2537
2538
2539/** @name PGM::fSyncFlags Flags
2540 * @{
2541 */
2542/** Updates the virtual access handler state bit in PGMPAGE. */
2543#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2544/** Always sync CR3. */
2545#define PGM_SYNC_ALWAYS RT_BIT(1)
2546/** Check monitoring on next CR3 (re)load and invalidate page. */
2547#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2548/** Clear the page pool (a light weight flush). */
2549#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2550/** @} */
2551
2552
2553__BEGIN_DECLS
2554
2555int pgmLock(PVM pVM);
2556void pgmUnlock(PVM pVM);
2557
2558PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2559PGMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2560int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
2561
2562int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2563int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2564PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2565void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2566DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2567
2568void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2569int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2570DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2571#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2572void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2573#else
2574# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2575#endif
2576DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2577
2578
2579void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2580int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2581int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2582int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2583#ifdef IN_RING3
2584int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2585int pgmR3PhysRamReset(PVM pVM);
2586int pgmR3PhysRomReset(PVM pVM);
2587#ifndef VBOX_WITH_NEW_PHYS_CODE
2588int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2589#endif
2590
2591int pgmR3PoolInit(PVM pVM);
2592void pgmR3PoolRelocate(PVM pVM);
2593void pgmR3PoolReset(PVM pVM);
2594
2595#endif /* IN_RING3 */
2596#ifdef IN_GC
2597void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2598#endif
2599int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage);
2600PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2601void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint16_t iUserTable);
2602void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable);
2603int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2604void pgmPoolFlushAll(PVM pVM);
2605void pgmPoolClearAll(PVM pVM);
2606void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2607void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2608int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2609PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2610void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2611void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2612uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2613void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2614#ifdef PGMPOOL_WITH_MONITORING
2615# ifdef IN_RING3
2616void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2617# else
2618void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2619# endif
2620int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2621void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2622void pgmPoolMonitorModifiedClearAll(PVM pVM);
2623int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2624int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2625#endif
2626
2627__END_DECLS
2628
2629
2630/**
2631 * Gets the PGMRAMRANGE structure for a guest page.
2632 *
2633 * @returns Pointer to the RAM range on success.
2634 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2635 *
2636 * @param pPGM PGM handle.
2637 * @param GCPhys The GC physical address.
2638 */
2639DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2640{
2641 /*
2642 * Optimize for the first range.
2643 */
2644 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2645 RTGCPHYS off = GCPhys - pRam->GCPhys;
2646 if (RT_UNLIKELY(off >= pRam->cb))
2647 {
2648 do
2649 {
2650 pRam = CTXALLSUFF(pRam->pNext);
2651 if (RT_UNLIKELY(!pRam))
2652 break;
2653 off = GCPhys - pRam->GCPhys;
2654 } while (off >= pRam->cb);
2655 }
2656 return pRam;
2657}
2658
2659
2660/**
2661 * Gets the PGMPAGE structure for a guest page.
2662 *
2663 * @returns Pointer to the page on success.
2664 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2665 *
2666 * @param pPGM PGM handle.
2667 * @param GCPhys The GC physical address.
2668 */
2669DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2670{
2671 /*
2672 * Optimize for the first range.
2673 */
2674 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2675 RTGCPHYS off = GCPhys - pRam->GCPhys;
2676 if (RT_UNLIKELY(off >= pRam->cb))
2677 {
2678 do
2679 {
2680 pRam = CTXALLSUFF(pRam->pNext);
2681 if (RT_UNLIKELY(!pRam))
2682 return NULL;
2683 off = GCPhys - pRam->GCPhys;
2684 } while (off >= pRam->cb);
2685 }
2686 return &pRam->aPages[off >> PAGE_SHIFT];
2687}
2688
2689
2690/**
2691 * Gets the PGMPAGE structure for a guest page.
2692 *
2693 * Old Phys code: Will make sure the page is present.
2694 *
2695 * @returns VBox status code.
2696 * @retval VINF_SUCCESS and a valid *ppPage on success.
2697 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2698 *
2699 * @param pPGM PGM handle.
2700 * @param GCPhys The GC physical address.
2701 * @param ppPage Where to store the page poitner on success.
2702 */
2703DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2704{
2705 /*
2706 * Optimize for the first range.
2707 */
2708 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2709 RTGCPHYS off = GCPhys - pRam->GCPhys;
2710 if (RT_UNLIKELY(off >= pRam->cb))
2711 {
2712 do
2713 {
2714 pRam = CTXALLSUFF(pRam->pNext);
2715 if (RT_UNLIKELY(!pRam))
2716 {
2717 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2718 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2719 }
2720 off = GCPhys - pRam->GCPhys;
2721 } while (off >= pRam->cb);
2722 }
2723 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2724#ifndef VBOX_WITH_NEW_PHYS_CODE
2725
2726 /*
2727 * Make sure it's present.
2728 */
2729 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2730 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2731 {
2732#ifdef IN_RING3
2733 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2734#else
2735 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2736#endif
2737 if (VBOX_FAILURE(rc))
2738 {
2739 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2740 return rc;
2741 }
2742 Assert(rc == VINF_SUCCESS);
2743 }
2744#endif
2745 return VINF_SUCCESS;
2746}
2747
2748
2749
2750
2751/**
2752 * Gets the PGMPAGE structure for a guest page.
2753 *
2754 * Old Phys code: Will make sure the page is present.
2755 *
2756 * @returns VBox status code.
2757 * @retval VINF_SUCCESS and a valid *ppPage on success.
2758 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2759 *
2760 * @param pPGM PGM handle.
2761 * @param GCPhys The GC physical address.
2762 * @param ppPage Where to store the page poitner on success.
2763 * @param ppRamHint Where to read and store the ram list hint.
2764 * The caller initializes this to NULL before the call.
2765 */
2766DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2767{
2768 RTGCPHYS off;
2769 PPGMRAMRANGE pRam = *ppRamHint;
2770 if ( !pRam
2771 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2772 {
2773 pRam = CTXALLSUFF(pPGM->pRamRanges);
2774 off = GCPhys - pRam->GCPhys;
2775 if (RT_UNLIKELY(off >= pRam->cb))
2776 {
2777 do
2778 {
2779 pRam = CTXALLSUFF(pRam->pNext);
2780 if (RT_UNLIKELY(!pRam))
2781 {
2782 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2783 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2784 }
2785 off = GCPhys - pRam->GCPhys;
2786 } while (off >= pRam->cb);
2787 }
2788 *ppRamHint = pRam;
2789 }
2790 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2791#ifndef VBOX_WITH_NEW_PHYS_CODE
2792
2793 /*
2794 * Make sure it's present.
2795 */
2796 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2797 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2798 {
2799#ifdef IN_RING3
2800 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2801#else
2802 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2803#endif
2804 if (VBOX_FAILURE(rc))
2805 {
2806 *ppPage = NULL; /* Shut up annoying smart ass. */
2807 return rc;
2808 }
2809 Assert(rc == VINF_SUCCESS);
2810 }
2811#endif
2812 return VINF_SUCCESS;
2813}
2814
2815
2816/**
2817 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2818 *
2819 * @returns Pointer to the page on success.
2820 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2821 *
2822 * @param pPGM PGM handle.
2823 * @param GCPhys The GC physical address.
2824 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
2825 */
2826DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2827{
2828 /*
2829 * Optimize for the first range.
2830 */
2831 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2832 RTGCPHYS off = GCPhys - pRam->GCPhys;
2833 if (RT_UNLIKELY(off >= pRam->cb))
2834 {
2835 do
2836 {
2837 pRam = CTXALLSUFF(pRam->pNext);
2838 if (RT_UNLIKELY(!pRam))
2839 return NULL;
2840 off = GCPhys - pRam->GCPhys;
2841 } while (off >= pRam->cb);
2842 }
2843 *ppRam = pRam;
2844 return &pRam->aPages[off >> PAGE_SHIFT];
2845}
2846
2847
2848
2849
2850/**
2851 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2852 *
2853 * @returns Pointer to the page on success.
2854 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2855 *
2856 * @param pPGM PGM handle.
2857 * @param GCPhys The GC physical address.
2858 * @param ppPage Where to store the pointer to the PGMPAGE structure.
2859 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2860 */
2861DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2862{
2863 /*
2864 * Optimize for the first range.
2865 */
2866 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2867 RTGCPHYS off = GCPhys - pRam->GCPhys;
2868 if (RT_UNLIKELY(off >= pRam->cb))
2869 {
2870 do
2871 {
2872 pRam = CTXALLSUFF(pRam->pNext);
2873 if (RT_UNLIKELY(!pRam))
2874 {
2875 *ppRam = NULL; /* Shut up silly GCC warnings. */
2876 *ppPage = NULL; /* ditto */
2877 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2878 }
2879 off = GCPhys - pRam->GCPhys;
2880 } while (off >= pRam->cb);
2881 }
2882 *ppRam = pRam;
2883 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2884#ifndef VBOX_WITH_NEW_PHYS_CODE
2885
2886 /*
2887 * Make sure it's present.
2888 */
2889 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2890 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2891 {
2892#ifdef IN_RING3
2893 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2894#else
2895 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2896#endif
2897 if (VBOX_FAILURE(rc))
2898 {
2899 *ppPage = NULL; /* Shut up silly GCC warnings. */
2900 *ppPage = NULL; /* ditto */
2901 return rc;
2902 }
2903 Assert(rc == VINF_SUCCESS);
2904
2905 }
2906#endif
2907 return VINF_SUCCESS;
2908}
2909
2910
2911/**
2912 * Convert GC Phys to HC Phys.
2913 *
2914 * @returns VBox status.
2915 * @param pPGM PGM handle.
2916 * @param GCPhys The GC physical address.
2917 * @param pHCPhys Where to store the corresponding HC physical address.
2918 *
2919 * @deprecated Doesn't deal with zero, shared or write monitored pages.
2920 * Avoid when writing new code!
2921 */
2922DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2923{
2924 PPGMPAGE pPage;
2925 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2926 if (VBOX_FAILURE(rc))
2927 return rc;
2928 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
2929 return VINF_SUCCESS;
2930}
2931
2932
2933#ifndef IN_GC
2934/**
2935 * Queries the Physical TLB entry for a physical guest page,
2936 * attemting to load the TLB entry if necessary.
2937 *
2938 * @returns VBox status code.
2939 * @retval VINF_SUCCESS on success
2940 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2941 * @param pPGM The PGM instance handle.
2942 * @param GCPhys The address of the guest page.
2943 * @param ppTlbe Where to store the pointer to the TLB entry.
2944 */
2945
2946DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
2947{
2948 int rc;
2949 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
2950 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
2951 {
2952 STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
2953 rc = VINF_SUCCESS;
2954 }
2955 else
2956 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
2957 *ppTlbe = pTlbe;
2958 return rc;
2959}
2960#endif /* !IN_GC */
2961
2962
2963#ifndef VBOX_WITH_NEW_PHYS_CODE
2964/**
2965 * Convert GC Phys to HC Virt.
2966 *
2967 * @returns VBox status.
2968 * @param pPGM PGM handle.
2969 * @param GCPhys The GC physical address.
2970 * @param pHCPtr Where to store the corresponding HC virtual address.
2971 *
2972 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
2973 */
2974DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
2975{
2976 PPGMRAMRANGE pRam;
2977 PPGMPAGE pPage;
2978 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
2979 if (VBOX_FAILURE(rc))
2980 {
2981 *pHCPtr = 0; /* Shut up silly GCC warnings. */
2982 return rc;
2983 }
2984 RTGCPHYS off = GCPhys - pRam->GCPhys;
2985
2986 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2987 {
2988 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
2989 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2990 return VINF_SUCCESS;
2991 }
2992 if (pRam->pvHC)
2993 {
2994 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
2995 return VINF_SUCCESS;
2996 }
2997 *pHCPtr = 0; /* Shut up silly GCC warnings. */
2998 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2999}
3000#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3001
3002
3003/**
3004 * Convert GC Phys to HC Virt.
3005 *
3006 * @returns VBox status.
3007 * @param PVM VM handle.
3008 * @param pRam Ram range
3009 * @param GCPhys The GC physical address.
3010 * @param pHCPtr Where to store the corresponding HC virtual address.
3011 *
3012 * @deprecated This will be eliminated. Don't use it.
3013 */
3014DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3015{
3016 RTGCPHYS off = GCPhys - pRam->GCPhys;
3017 Assert(off < pRam->cb);
3018
3019 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3020 {
3021 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3022 /* Physical chunk in dynamically allocated range not present? */
3023 if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
3024 {
3025#ifdef IN_RING3
3026 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3027#else
3028 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3029#endif
3030 if (rc != VINF_SUCCESS)
3031 {
3032 *pHCPtr = 0; /* GCC crap */
3033 return rc;
3034 }
3035 }
3036 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3037 return VINF_SUCCESS;
3038 }
3039 if (pRam->pvHC)
3040 {
3041 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3042 return VINF_SUCCESS;
3043 }
3044 *pHCPtr = 0; /* GCC crap */
3045 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3046}
3047
3048
3049/**
3050 * Convert GC Phys to HC Virt and HC Phys.
3051 *
3052 * @returns VBox status.
3053 * @param pPGM PGM handle.
3054 * @param GCPhys The GC physical address.
3055 * @param pHCPtr Where to store the corresponding HC virtual address.
3056 * @param pHCPhys Where to store the HC Physical address and its flags.
3057 *
3058 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3059 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3060 */
3061DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3062{
3063 PPGMRAMRANGE pRam;
3064 PPGMPAGE pPage;
3065 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3066 if (VBOX_FAILURE(rc))
3067 {
3068 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3069 *pHCPhys = 0; /* ditto */
3070 return rc;
3071 }
3072 RTGCPHYS off = GCPhys - pRam->GCPhys;
3073
3074 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3075 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3076 {
3077 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3078 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3079 return VINF_SUCCESS;
3080 }
3081 if (pRam->pvHC)
3082 {
3083 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3084 return VINF_SUCCESS;
3085 }
3086 *pHCPtr = 0;
3087 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3088}
3089
3090
3091/**
3092 * Clears flags associated with a RAM address.
3093 *
3094 * @returns VBox status code.
3095 * @param pPGM PGM handle.
3096 * @param GCPhys Guest context physical address.
3097 * @param fFlags fFlags to clear. (Bits 0-11.)
3098 */
3099DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3100{
3101 PPGMPAGE pPage;
3102 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3103 if (VBOX_FAILURE(rc))
3104 return rc;
3105
3106 fFlags &= ~X86_PTE_PAE_PG_MASK;
3107 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3108 return VINF_SUCCESS;
3109}
3110
3111
3112/**
3113 * Clears flags associated with a RAM address.
3114 *
3115 * @returns VBox status code.
3116 * @param pPGM PGM handle.
3117 * @param GCPhys Guest context physical address.
3118 * @param fFlags fFlags to clear. (Bits 0-11.)
3119 * @param ppRamHint Where to read and store the ram list hint.
3120 * The caller initializes this to NULL before the call.
3121 */
3122DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3123{
3124 PPGMPAGE pPage;
3125 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3126 if (VBOX_FAILURE(rc))
3127 return rc;
3128
3129 fFlags &= ~X86_PTE_PAE_PG_MASK;
3130 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3131 return VINF_SUCCESS;
3132}
3133
3134/**
3135 * Sets (bitwise OR) flags associated with a RAM address.
3136 *
3137 * @returns VBox status code.
3138 * @param pPGM PGM handle.
3139 * @param GCPhys Guest context physical address.
3140 * @param fFlags fFlags to set clear. (Bits 0-11.)
3141 */
3142DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3143{
3144 PPGMPAGE pPage;
3145 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3146 if (VBOX_FAILURE(rc))
3147 return rc;
3148
3149 fFlags &= ~X86_PTE_PAE_PG_MASK;
3150 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3151 return VINF_SUCCESS;
3152}
3153
3154
3155/**
3156 * Sets (bitwise OR) flags associated with a RAM address.
3157 *
3158 * @returns VBox status code.
3159 * @param pPGM PGM handle.
3160 * @param GCPhys Guest context physical address.
3161 * @param fFlags fFlags to set clear. (Bits 0-11.)
3162 * @param ppRamHint Where to read and store the ram list hint.
3163 * The caller initializes this to NULL before the call.
3164 */
3165DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3166{
3167 PPGMPAGE pPage;
3168 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3169 if (VBOX_FAILURE(rc))
3170 return rc;
3171
3172 fFlags &= ~X86_PTE_PAE_PG_MASK;
3173 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3174 return VINF_SUCCESS;
3175}
3176
3177
3178/**
3179 * Gets the page directory for the specified address.
3180 *
3181 * @returns Pointer to the page directory in question.
3182 * @returns NULL if the page directory is not present or on an invalid page.
3183 * @param pPGM Pointer to the PGM instance data.
3184 * @param GCPtr The address.
3185 */
3186DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3187{
3188 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3189 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3190 {
3191 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3192 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3193
3194 /* cache is out-of-sync. */
3195 PX86PDPAE pPD;
3196 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3197 if (VBOX_SUCCESS(rc))
3198 return pPD;
3199 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3200 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3201 }
3202 return NULL;
3203}
3204
3205
3206/**
3207 * Gets the page directory entry for the specified address.
3208 *
3209 * @returns Pointer to the page directory entry in question.
3210 * @returns NULL if the page directory is not present or on an invalid page.
3211 * @param pPGM Pointer to the PGM instance data.
3212 * @param GCPtr The address.
3213 */
3214DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3215{
3216 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3217 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3218 {
3219 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3220 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3221 return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3222
3223 /* The cache is out-of-sync. */
3224 PX86PDPAE pPD;
3225 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3226 if (VBOX_SUCCESS(rc))
3227 return &pPD->a[iPD];
3228 AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3229 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3230 }
3231 return NULL;
3232}
3233
3234
3235/**
3236 * Gets the page directory entry for the specified address.
3237 *
3238 * @returns The page directory entry in question.
3239 * @returns A non-present entry if the page directory is not present or on an invalid page.
3240 * @param pPGM Pointer to the PGM instance data.
3241 * @param GCPtr The address.
3242 */
3243DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3244{
3245 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3246 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3247 {
3248 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3249 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3250 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3251
3252 /* cache is out-of-sync. */
3253 PX86PDPAE pPD;
3254 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3255 if (VBOX_SUCCESS(rc))
3256 return pPD->a[iPD].u;
3257 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3258 }
3259 return 0ULL;
3260}
3261
3262
3263/**
3264 * Gets the page directory pointer table entry for the specified address
3265 * and returns the index into the page directory
3266 *
3267 * @returns Pointer to the page directory in question.
3268 * @returns NULL if the page directory is not present or on an invalid page.
3269 * @param pPGM Pointer to the PGM instance data.
3270 * @param GCPtr The address.
3271 * @param piPD Receives the index into the returned page directory
3272 */
3273DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3274{
3275 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3276 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3277 {
3278 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3279 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3280 {
3281 *piPD = iPD;
3282 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3283 }
3284
3285 /* cache is out-of-sync. */
3286 PX86PDPAE pPD;
3287 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3288 if (VBOX_SUCCESS(rc))
3289 {
3290 *piPD = iPD;
3291 return pPD;
3292 }
3293 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3294 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3295 }
3296 return NULL;
3297}
3298
3299#ifndef IN_GC
3300/**
3301 * Gets the page directory pointer entry for the specified address.
3302 *
3303 * @returns Pointer to the page directory pointer entry in question.
3304 * @returns NULL if the page directory is not present or on an invalid page.
3305 * @param pPGM Pointer to the PGM instance data.
3306 * @param GCPtr The address.
3307 * @param ppPml4e Page Map Level-4 Entry (out)
3308 */
3309DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e)
3310{
3311 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3312
3313 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3314 if ((*ppPml4e)->n.u1Present)
3315 {
3316 PX86PDPT pPdpt;
3317 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdpt);
3318 if (VBOX_FAILURE(rc))
3319 {
3320 AssertFailed();
3321 return NULL;
3322 }
3323 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3324 return &pPdpt->a[iPdPt];
3325 }
3326 return NULL;
3327}
3328
3329/**
3330 * Gets the page directory entry for the specified address.
3331 *
3332 * @returns The page directory entry in question.
3333 * @returns A non-present entry if the page directory is not present or on an invalid page.
3334 * @param pPGM Pointer to the PGM instance data.
3335 * @param GCPtr The address.
3336 * @param ppPml4e Page Map Level-4 Entry (out)
3337 * @param pPdpe Page directory pointer table entry (out)
3338 */
3339DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3340{
3341 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3342
3343 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3344 if ((*ppPml4e)->n.u1Present)
3345 {
3346 PX86PDPT pPdptTemp;
3347 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3348 if (VBOX_FAILURE(rc))
3349 {
3350 AssertFailed();
3351 return 0ULL;
3352 }
3353
3354 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3355 *pPdpe = pPdptTemp->a[iPdPt];
3356 if (pPdpe->n.u1Present)
3357 {
3358 PX86PDPAE pPD;
3359
3360 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3361 if (VBOX_FAILURE(rc))
3362 {
3363 AssertFailed();
3364 return 0ULL;
3365 }
3366 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3367 return pPD->a[iPD].u;
3368 }
3369 }
3370 return 0ULL;
3371}
3372
3373/**
3374 * Gets the page directory entry for the specified address.
3375 *
3376 * @returns The page directory entry in question.
3377 * @returns A non-present entry if the page directory is not present or on an invalid page.
3378 * @param pPGM Pointer to the PGM instance data.
3379 * @param GCPtr The address.
3380 */
3381DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3382{
3383 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3384
3385 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3386 {
3387 PX86PDPT pPdptTemp;
3388 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3389 if (VBOX_FAILURE(rc))
3390 {
3391 AssertFailed();
3392 return 0ULL;
3393 }
3394
3395 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3396 if (pPdptTemp->a[iPdPt].n.u1Present)
3397 {
3398 PX86PDPAE pPD;
3399
3400 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3401 if (VBOX_FAILURE(rc))
3402 {
3403 AssertFailed();
3404 return 0ULL;
3405 }
3406 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3407 return pPD->a[iPD].u;
3408 }
3409 }
3410 return 0ULL;
3411}
3412
3413/**
3414 * Gets the page directory entry for the specified address.
3415 *
3416 * @returns Pointer to the page directory entry in question.
3417 * @returns NULL if the page directory is not present or on an invalid page.
3418 * @param pPGM Pointer to the PGM instance data.
3419 * @param GCPtr The address.
3420 */
3421DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3422{
3423 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3424
3425 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3426 {
3427 PX86PDPT pPdptTemp;
3428 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3429 if (VBOX_FAILURE(rc))
3430 {
3431 AssertFailed();
3432 return NULL;
3433 }
3434
3435 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3436 if (pPdptTemp->a[iPdPt].n.u1Present)
3437 {
3438 PX86PDPAE pPD;
3439
3440 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3441 if (VBOX_FAILURE(rc))
3442 {
3443 AssertFailed();
3444 return NULL;
3445 }
3446 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3447 return &pPD->a[iPD];
3448 }
3449 }
3450 return NULL;
3451}
3452
3453
3454/**
3455 * Gets the GUEST page directory pointer for the specified address.
3456 *
3457 * @returns The page directory in question.
3458 * @returns NULL if the page directory is not present or on an invalid page.
3459 * @param pPGM Pointer to the PGM instance data.
3460 * @param GCPtr The address.
3461 * @param ppPml4e Page Map Level-4 Entry (out)
3462 * @param pPdpe Page directory pointer table entry (out)
3463 * @param piPD Receives the index into the returned page directory
3464 */
3465DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
3466{
3467 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3468
3469 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3470 if ((*ppPml4e)->n.u1Present)
3471 {
3472 PX86PDPT pPdptTemp;
3473 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3474 if (VBOX_FAILURE(rc))
3475 {
3476 AssertFailed();
3477 return 0ULL;
3478 }
3479
3480 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3481 *pPdpe = pPdptTemp->a[iPdPt];
3482 if (pPdpe->n.u1Present)
3483 {
3484 PX86PDPAE pPD;
3485
3486 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3487 if (VBOX_FAILURE(rc))
3488 {
3489 AssertFailed();
3490 return 0ULL;
3491 }
3492 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3493 return pPD;
3494 }
3495 }
3496 return 0ULL;
3497}
3498#endif /* !IN_GC */
3499
3500/**
3501 * Checks if any of the specified page flags are set for the given page.
3502 *
3503 * @returns true if any of the flags are set.
3504 * @returns false if all the flags are clear.
3505 * @param pPGM PGM handle.
3506 * @param GCPhys The GC physical address.
3507 * @param fFlags The flags to check for.
3508 */
3509DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3510{
3511 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3512 return pPage
3513 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3514}
3515
3516
3517/**
3518 * Gets the page state for a physical handler.
3519 *
3520 * @returns The physical handler page state.
3521 * @param pCur The physical handler in question.
3522 */
3523DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3524{
3525 switch (pCur->enmType)
3526 {
3527 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3528 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3529
3530 case PGMPHYSHANDLERTYPE_MMIO:
3531 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3532 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3533
3534 default:
3535 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3536 }
3537}
3538
3539
3540/**
3541 * Gets the page state for a virtual handler.
3542 *
3543 * @returns The virtual handler page state.
3544 * @param pCur The virtual handler in question.
3545 * @remarks This should never be used on a hypervisor access handler.
3546 */
3547DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3548{
3549 switch (pCur->enmType)
3550 {
3551 case PGMVIRTHANDLERTYPE_WRITE:
3552 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3553 case PGMVIRTHANDLERTYPE_ALL:
3554 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3555 default:
3556 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3557 }
3558}
3559
3560
3561/**
3562 * Clears one physical page of a virtual handler
3563 *
3564 * @param pPGM Pointer to the PGM instance.
3565 * @param pCur Virtual handler structure
3566 * @param iPage Physical page index
3567 *
3568 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3569 * need to care about other handlers in the same page.
3570 */
3571DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3572{
3573 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3574
3575 /*
3576 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
3577 */
3578#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3579 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3580 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3581 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3582#endif
3583 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3584 {
3585 /* We're the head of the alias chain. */
3586 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3587#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3588 AssertReleaseMsg(pRemove != NULL,
3589 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3590 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3591 AssertReleaseMsg(pRemove == pPhys2Virt,
3592 ("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3593 " got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3594 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3595 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3596#endif
3597 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3598 {
3599 /* Insert the next list in the alias chain into the tree. */
3600 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3601#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3602 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3603 ("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3604 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3605#endif
3606 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
3607 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3608 AssertRelease(fRc);
3609 }
3610 }
3611 else
3612 {
3613 /* Locate the previous node in the alias chain. */
3614 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3615#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3616 AssertReleaseMsg(pPrev != pPhys2Virt,
3617 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3618 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3619#endif
3620 for (;;)
3621 {
3622 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3623 if (pNext == pPhys2Virt)
3624 {
3625 /* unlink. */
3626 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3627 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3628 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3629 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3630 else
3631 {
3632 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3633 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3634 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3635 }
3636 break;
3637 }
3638
3639 /* next */
3640 if (pNext == pPrev)
3641 {
3642#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3643 AssertReleaseMsg(pNext != pPrev,
3644 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3645 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3646#endif
3647 break;
3648 }
3649 pPrev = pNext;
3650 }
3651 }
3652 Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3653 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3654 pPhys2Virt->offNextAlias = 0;
3655 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3656
3657 /*
3658 * Clear the ram flags for this page.
3659 */
3660 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3661 AssertReturnVoid(pPage);
3662 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3663}
3664
3665
3666/**
3667 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3668 *
3669 * @returns Pointer to the shadow page structure.
3670 * @param pPool The pool.
3671 * @param HCPhys The HC physical address of the shadow page.
3672 */
3673DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3674{
3675 /*
3676 * Look up the page.
3677 */
3678 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3679 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3680 return pPage;
3681}
3682
3683
3684/**
3685 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3686 *
3687 * @returns Pointer to the shadow page structure.
3688 * @param pPool The pool.
3689 * @param idx The pool page index.
3690 */
3691DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3692{
3693 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3694 return &pPool->aPages[idx];
3695}
3696
3697
3698#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3699/**
3700 * Clear references to guest physical memory.
3701 *
3702 * @param pPool The pool.
3703 * @param pPoolPage The pool page.
3704 * @param pPhysPage The physical guest page tracking structure.
3705 */
3706DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3707{
3708 /*
3709 * Just deal with the simple case here.
3710 */
3711#ifdef LOG_ENABLED
3712 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3713#endif
3714 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3715 if (cRefs == 1)
3716 {
3717 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3718 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3719 }
3720 else
3721 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3722 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3723}
3724#endif
3725
3726
3727#ifdef PGMPOOL_WITH_CACHE
3728/**
3729 * Moves the page to the head of the age list.
3730 *
3731 * This is done when the cached page is used in one way or another.
3732 *
3733 * @param pPool The pool.
3734 * @param pPage The cached page.
3735 * @todo inline in PGMInternal.h!
3736 */
3737DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3738{
3739 /*
3740 * Move to the head of the age list.
3741 */
3742 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3743 {
3744 /* unlink */
3745 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3746 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3747 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3748 else
3749 pPool->iAgeTail = pPage->iAgePrev;
3750
3751 /* insert at head */
3752 pPage->iAgePrev = NIL_PGMPOOL_IDX;
3753 pPage->iAgeNext = pPool->iAgeHead;
3754 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3755 pPool->iAgeHead = pPage->idx;
3756 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3757 }
3758}
3759#endif /* PGMPOOL_WITH_CACHE */
3760
3761/**
3762 * Tells if mappings are to be put into the shadow page table or not
3763 *
3764 * @returns boolean result
3765 * @param pVM VM handle.
3766 */
3767
3768DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3769{
3770#ifdef IN_RING0
3771 /* There are no mappings in VT-x and AMD-V mode. */
3772 Assert(pPGM->fDisableMappings);
3773 return false;
3774#else
3775 return !pPGM->fDisableMappings;
3776#endif
3777}
3778
3779/** @} */
3780
3781#endif
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette