VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 9176

Last change on this file since 9176 was 9026, checked in by vboxsync, 17 years ago

More updates for nested paging. (setting up the paging mode)
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 151.6 KB
Line 
1/* $Id: PGMInternal.h 9026 2008-05-21 15:33:04Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
44# error "Not in PGM! This is an internal header!"
45#endif
46
47
48/** @defgroup grp_pgm_int Internals
49 * @ingroup grp_pgm
50 * @internal
51 * @{
52 */
53
54
55/** @name PGM Compile Time Config
56 * @{
57 */
58
59/**
60 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
61 * Comment it if it will break something.
62 */
63#define PGM_OUT_OF_SYNC_IN_GC
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Sync N pages instead of a whole page table
72 */
73#define PGM_SYNC_N_PAGES
74
75/**
76 * Number of pages to sync during a page fault
77 *
78 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
79 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
80 */
81#define PGM_SYNC_NR_PAGES 8
82
83/**
84 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
85 */
86#define PGM_MAX_PHYSCACHE_ENTRIES 64
87#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
88
89/**
90 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
91 */
92#define PGM_PHYSMEMACCESS_CACHING
93
94/** @def PGMPOOL_WITH_CACHE
95 * Enable agressive caching using the page pool.
96 *
97 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
98 */
99#define PGMPOOL_WITH_CACHE
100
101/** @def PGMPOOL_WITH_MIXED_PT_CR3
102 * When defined, we'll deal with 'uncachable' pages.
103 */
104#ifdef PGMPOOL_WITH_CACHE
105# define PGMPOOL_WITH_MIXED_PT_CR3
106#endif
107
108/** @def PGMPOOL_WITH_MONITORING
109 * Monitor the guest pages which are shadowed.
110 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
111 * be enabled as well.
112 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
113 */
114#ifdef PGMPOOL_WITH_CACHE
115# define PGMPOOL_WITH_MONITORING
116#endif
117
118/** @def PGMPOOL_WITH_GCPHYS_TRACKING
119 * Tracking the of shadow pages mapping guest physical pages.
120 *
121 * This is very expensive, the current cache prototype is trying to figure out
122 * whether it will be acceptable with an agressive caching policy.
123 */
124#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
125# define PGMPOOL_WITH_GCPHYS_TRACKING
126#endif
127
128/** @def PGMPOOL_WITH_USER_TRACKNG
129 * Tracking users of shadow pages. This is required for the linking of shadow page
130 * tables and physical guest addresses.
131 */
132#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
133# define PGMPOOL_WITH_USER_TRACKING
134#endif
135
136/** @def PGMPOOL_CFG_MAX_GROW
137 * The maximum number of pages to add to the pool in one go.
138 */
139#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
140
141/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
142 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
143 */
144#ifdef VBOX_STRICT
145# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
146#endif
147/** @} */
148
149
150/** @name PDPT and PML4 flags.
151 * These are placed in the three bits available for system programs in
152 * the PDPT and PML4 entries.
153 * @{ */
154/** The entry is a permanent one and it's must always be present.
155 * Never free such an entry. */
156#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
157/** Mapping (hypervisor allocated pagetable). */
158#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
159/** @} */
160
161/** @name Page directory flags.
162 * These are placed in the three bits available for system programs in
163 * the page directory entries.
164 * @{ */
165/** Mapping (hypervisor allocated pagetable). */
166#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
167/** Made read-only to facilitate dirty bit tracking. */
168#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
169/** @} */
170
171/** @name Page flags.
172 * These are placed in the three bits available for system programs in
173 * the page entries.
174 * @{ */
175/** Made read-only to facilitate dirty bit tracking. */
176#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
177
178#ifndef PGM_PTFLAGS_CSAM_VALIDATED
179/** Scanned and approved by CSAM (tm).
180 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
181 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
182#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
183#endif
184/** @} */
185
186/** @name Defines used to indicate the shadow and guest paging in the templates.
187 * @{ */
188#define PGM_TYPE_REAL 1
189#define PGM_TYPE_PROT 2
190#define PGM_TYPE_32BIT 3
191#define PGM_TYPE_PAE 4
192#define PGM_TYPE_AMD64 5
193#define PGM_TYPE_NESTED 6
194/** @} */
195
196/** Macro for checking if the guest is using paging.
197 * @param uType PGM_TYPE_*
198 * @remark ASSUMES certain order of the PGM_TYPE_* values.
199 */
200#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT && (uType) != PGM_TYPE_NESTED)
201
202/** Macro for checking if the guest supports the NX bit.
203 * @param uType PGM_TYPE_*
204 * @remark ASSUMES certain order of the PGM_TYPE_* values.
205 */
206#define PGM_WITH_NX(uType) ((uType) >= PGM_TYPE_PAE && (uType) != PGM_TYPE_NESTED)
207
208
209/** @def PGM_HCPHYS_2_PTR
210 * Maps a HC physical page pool address to a virtual address.
211 *
212 * @returns VBox status code.
213 * @param pVM The VM handle.
214 * @param HCPhys The HC physical address to map to a virtual one.
215 * @param ppv Where to store the virtual address. No need to cast this.
216 *
217 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
218 * small page window employeed by that function. Be careful.
219 * @remark There is no need to assert on the result.
220 */
221#ifdef IN_GC
222# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
223#else
224# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
225#endif
226
227/** @def PGM_GCPHYS_2_PTR
228 * Maps a GC physical page address to a virtual address.
229 *
230 * @returns VBox status code.
231 * @param pVM The VM handle.
232 * @param GCPhys The GC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast this.
234 *
235 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
236 * small page window employeed by that function. Be careful.
237 * @remark There is no need to assert on the result.
238 */
239#ifdef IN_GC
240# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
241#else
242# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
243#endif
244
245/** @def PGM_GCPHYS_2_PTR_EX
246 * Maps a unaligned GC physical page address to a virtual address.
247 *
248 * @returns VBox status code.
249 * @param pVM The VM handle.
250 * @param GCPhys The GC physical address to map to a virtual one.
251 * @param ppv Where to store the virtual address. No need to cast this.
252 *
253 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
254 * small page window employeed by that function. Be careful.
255 * @remark There is no need to assert on the result.
256 */
257#ifdef IN_GC
258# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
259#else
260# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
261#endif
262
263/** @def PGM_INVL_PG
264 * Invalidates a page when in GC does nothing in HC.
265 *
266 * @param GCVirt The virtual address of the page to invalidate.
267 */
268#ifdef IN_GC
269# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
270#elif defined(IN_RING0)
271# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
272#else
273# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
274#endif
275
276/** @def PGM_INVL_BIG_PG
277 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
278 *
279 * @param GCVirt The virtual address within the page directory to invalidate.
280 */
281#ifdef IN_GC
282# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
283#elif defined(IN_RING0)
284# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
285#else
286# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
287#endif
288
289/** @def PGM_INVL_GUEST_TLBS()
290 * Invalidates all guest TLBs.
291 */
292#ifdef IN_GC
293# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
294#elif defined(IN_RING0)
295# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
296#else
297# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
298#endif
299
300
301/**
302 * Structure for tracking GC Mappings.
303 *
304 * This structure is used by linked list in both GC and HC.
305 */
306typedef struct PGMMAPPING
307{
308 /** Pointer to next entry. */
309 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
310 /** Pointer to next entry. */
311 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
312 /** Pointer to next entry. */
313 GCPTRTYPE(struct PGMMAPPING *) pNextGC;
314 /** Start Virtual address. */
315 RTGCUINTPTR GCPtr;
316 /** Last Virtual address (inclusive). */
317 RTGCUINTPTR GCPtrLast;
318 /** Range size (bytes). */
319 RTGCUINTPTR cb;
320 /** Pointer to relocation callback function. */
321 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
322 /** User argument to the callback. */
323 R3PTRTYPE(void *) pvUser;
324 /** Mapping description / name. For easing debugging. */
325 R3PTRTYPE(const char *) pszDesc;
326 /** Number of page tables. */
327 RTUINT cPTs;
328#if HC_ARCH_BITS != GC_ARCH_BITS
329 RTUINT uPadding0; /**< Alignment padding. */
330#endif
331 /** Array of page table mapping data. Each entry
332 * describes one page table. The array can be longer
333 * than the declared length.
334 */
335 struct
336 {
337 /** The HC physical address of the page table. */
338 RTHCPHYS HCPhysPT;
339 /** The HC physical address of the first PAE page table. */
340 RTHCPHYS HCPhysPaePT0;
341 /** The HC physical address of the second PAE page table. */
342 RTHCPHYS HCPhysPaePT1;
343 /** The HC virtual address of the 32-bit page table. */
344 R3PTRTYPE(PX86PT) pPTR3;
345 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
346 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
347 /** The GC virtual address of the 32-bit page table. */
348 GCPTRTYPE(PX86PT) pPTGC;
349 /** The GC virtual address of the two PAE page table. */
350 GCPTRTYPE(PX86PTPAE) paPaePTsGC;
351 /** The GC virtual address of the 32-bit page table. */
352 R0PTRTYPE(PX86PT) pPTR0;
353 /** The GC virtual address of the two PAE page table. */
354 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
355 } aPTs[1];
356} PGMMAPPING;
357/** Pointer to structure for tracking GC Mappings. */
358typedef struct PGMMAPPING *PPGMMAPPING;
359
360
361/**
362 * Physical page access handler structure.
363 *
364 * This is used to keep track of physical address ranges
365 * which are being monitored in some kind of way.
366 */
367typedef struct PGMPHYSHANDLER
368{
369 AVLROGCPHYSNODECORE Core;
370 /** Access type. */
371 PGMPHYSHANDLERTYPE enmType;
372 /** Number of pages to update. */
373 uint32_t cPages;
374 /** Pointer to R3 callback function. */
375 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
376 /** User argument for R3 handlers. */
377 R3PTRTYPE(void *) pvUserR3;
378 /** Pointer to R0 callback function. */
379 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
380 /** User argument for R0 handlers. */
381 R0PTRTYPE(void *) pvUserR0;
382 /** Pointer to GC callback function. */
383 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
384 /** User argument for GC handlers. */
385 GCPTRTYPE(void *) pvUserGC;
386 /** Description / Name. For easing debugging. */
387 R3PTRTYPE(const char *) pszDesc;
388#ifdef VBOX_WITH_STATISTICS
389 /** Profiling of this handler. */
390 STAMPROFILE Stat;
391#endif
392} PGMPHYSHANDLER;
393/** Pointer to a physical page access handler structure. */
394typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
395
396
397/**
398 * Cache node for the physical addresses covered by a virtual handler.
399 */
400typedef struct PGMPHYS2VIRTHANDLER
401{
402 /** Core node for the tree based on physical ranges. */
403 AVLROGCPHYSNODECORE Core;
404 /** Offset from this struct to the PGMVIRTHANDLER structure. */
405 int32_t offVirtHandler;
406 /** Offset of the next alias relative to this one.
407 * Bit 0 is used for indicating whether we're in the tree.
408 * Bit 1 is used for indicating that we're the head node.
409 */
410 int32_t offNextAlias;
411} PGMPHYS2VIRTHANDLER;
412/** Pointer to a phys to virtual handler structure. */
413typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
414
415/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
416 * node is in the tree. */
417#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
418/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
419 * node is in the head of an alias chain.
420 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
421#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
422/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
423#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
424
425
426/**
427 * Virtual page access handler structure.
428 *
429 * This is used to keep track of virtual address ranges
430 * which are being monitored in some kind of way.
431 */
432typedef struct PGMVIRTHANDLER
433{
434 /** Core node for the tree based on virtual ranges. */
435 AVLROGCPTRNODECORE Core;
436 /** Number of cache pages. */
437 uint32_t u32Padding;
438 /** Access type. */
439 PGMVIRTHANDLERTYPE enmType;
440 /** Number of cache pages. */
441 uint32_t cPages;
442
443/** @todo The next two members are redundant. It adds some readability though. */
444 /** Start of the range. */
445 RTGCPTR GCPtr;
446 /** End of the range (exclusive). */
447 RTGCPTR GCPtrLast;
448 /** Size of the range (in bytes). */
449 RTGCUINTPTR cb;
450 /** Pointer to the GC callback function. */
451 GCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
452 /** Pointer to the HC callback function for invalidation. */
453 R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
454 /** Pointer to the HC callback function. */
455 R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
456 /** Description / Name. For easing debugging. */
457 R3PTRTYPE(const char *) pszDesc;
458#ifdef VBOX_WITH_STATISTICS
459 /** Profiling of this handler. */
460 STAMPROFILE Stat;
461#endif
462 /** Array of cached physical addresses for the monitored ranged. */
463 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
464} PGMVIRTHANDLER;
465/** Pointer to a virtual page access handler structure. */
466typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
467
468
469/**
470 * Page type.
471 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
472 * @todo convert to \#defines.
473 */
474typedef enum PGMPAGETYPE
475{
476 /** The usual invalid zero entry. */
477 PGMPAGETYPE_INVALID = 0,
478 /** RAM page. (RWX) */
479 PGMPAGETYPE_RAM,
480 /** MMIO2 page. (RWX) */
481 PGMPAGETYPE_MMIO2,
482 /** Shadowed ROM. (RWX) */
483 PGMPAGETYPE_ROM_SHADOW,
484 /** ROM page. (R-X) */
485 PGMPAGETYPE_ROM,
486 /** MMIO page. (---) */
487 PGMPAGETYPE_MMIO,
488 /** End of valid entries. */
489 PGMPAGETYPE_END
490} PGMPAGETYPE;
491AssertCompile(PGMPAGETYPE_END < 7);
492
493/** @name Page type predicates.
494 * @{ */
495#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
496#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
497#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
498#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
499#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
500/** @} */
501
502
503/**
504 * A Physical Guest Page tracking structure.
505 *
506 * The format of this structure is complicated because we have to fit a lot
507 * of information into as few bits as possible. The format is also subject
508 * to change (there is one comming up soon). Which means that for we'll be
509 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
510 * accessess to the structure.
511 */
512typedef struct PGMPAGE
513{
514 /** The physical address and a whole lot of other stuff. All bits are used! */
515 RTHCPHYS HCPhys;
516 /** The page state. */
517 uint32_t u2StateX : 2;
518 /** Flag indicating that a write monitored page was written to when set. */
519 uint32_t fWrittenToX : 1;
520 /** For later. */
521 uint32_t fSomethingElse : 1;
522 /** The Page ID.
523 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
524 * The HCPhys will be 100% static. */
525 uint32_t idPageX : 28;
526 /** The page type (PGMPAGETYPE). */
527 uint32_t u3Type : 3;
528 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
529 uint32_t u2HandlerPhysStateX : 2;
530 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
531 uint32_t u2HandlerVirtStateX : 2;
532 uint32_t u29B : 25;
533} PGMPAGE;
534AssertCompileSize(PGMPAGE, 16);
535/** Pointer to a physical guest page. */
536typedef PGMPAGE *PPGMPAGE;
537/** Pointer to a const physical guest page. */
538typedef const PGMPAGE *PCPGMPAGE;
539/** Pointer to a physical guest page pointer. */
540typedef PPGMPAGE *PPPGMPAGE;
541
542
543/**
544 * Clears the page structure.
545 * @param pPage Pointer to the physical guest page tracking structure.
546 */
547#define PGM_PAGE_CLEAR(pPage) \
548 do { \
549 (pPage)->HCPhys = 0; \
550 (pPage)->u2StateX = 0; \
551 (pPage)->fWrittenToX = 0; \
552 (pPage)->fSomethingElse = 0; \
553 (pPage)->idPageX = 0; \
554 (pPage)->u3Type = 0; \
555 (pPage)->u29B = 0; \
556 } while (0)
557
558/**
559 * Initializes the page structure.
560 * @param pPage Pointer to the physical guest page tracking structure.
561 */
562#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
563 do { \
564 (pPage)->HCPhys = (_HCPhys); \
565 (pPage)->u2StateX = (_uState); \
566 (pPage)->fWrittenToX = 0; \
567 (pPage)->fSomethingElse = 0; \
568 (pPage)->idPageX = (_idPage); \
569 /*(pPage)->u3Type = (_uType); - later */ \
570 PGM_PAGE_SET_TYPE(pPage, _uType); \
571 (pPage)->u29B = 0; \
572 } while (0)
573
574/**
575 * Initializes the page structure of a ZERO page.
576 * @param pPage Pointer to the physical guest page tracking structure.
577 */
578#ifdef VBOX_WITH_NEW_PHYS_CODE
579# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
580 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
581#else
582# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
583 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
584#endif
585/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
586# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
587 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
588
589
590/** @name The Page state, PGMPAGE::u2StateX.
591 * @{ */
592/** The zero page.
593 * This is a per-VM page that's never ever mapped writable. */
594#define PGM_PAGE_STATE_ZERO 0
595/** A allocated page.
596 * This is a per-VM page allocated from the page pool (or wherever
597 * we get MMIO2 pages from if the type is MMIO2).
598 */
599#define PGM_PAGE_STATE_ALLOCATED 1
600/** A allocated page that's being monitored for writes.
601 * The shadow page table mappings are read-only. When a write occurs, the
602 * fWrittenTo member is set, the page remapped as read-write and the state
603 * moved back to allocated. */
604#define PGM_PAGE_STATE_WRITE_MONITORED 2
605/** The page is shared, aka. copy-on-write.
606 * This is a page that's shared with other VMs. */
607#define PGM_PAGE_STATE_SHARED 3
608/** @} */
609
610
611/**
612 * Gets the page state.
613 * @returns page state (PGM_PAGE_STATE_*).
614 * @param pPage Pointer to the physical guest page tracking structure.
615 */
616#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
617
618/**
619 * Sets the page state.
620 * @param pPage Pointer to the physical guest page tracking structure.
621 * @param _uState The new page state.
622 */
623#define PGM_PAGE_SET_STATE(pPage, _uState) \
624 do { (pPage)->u2StateX = (_uState); } while (0)
625
626
627/**
628 * Gets the host physical address of the guest page.
629 * @returns host physical address (RTHCPHYS).
630 * @param pPage Pointer to the physical guest page tracking structure.
631 */
632#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
633
634/**
635 * Sets the host physical address of the guest page.
636 * @param pPage Pointer to the physical guest page tracking structure.
637 * @param _HCPhys The new host physical address.
638 */
639#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
640 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
641 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
642
643/**
644 * Get the Page ID.
645 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
646 * @param pPage Pointer to the physical guest page tracking structure.
647 */
648#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
649/* later:
650#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
651 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
652*/
653/**
654 * Sets the Page ID.
655 * @param pPage Pointer to the physical guest page tracking structure.
656 */
657#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
658/* later:
659#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
660 | ((_idPage) & 0xfff) \
661 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
662*/
663
664/**
665 * Get the Chunk ID.
666 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
667 * @param pPage Pointer to the physical guest page tracking structure.
668 */
669#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
670/* later:
671#if GMM_CHUNKID_SHIFT == 12
672# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
673#elif GMM_CHUNKID_SHIFT > 12
674# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
675#elif GMM_CHUNKID_SHIFT < 12
676# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
677 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
678#else
679# error "GMM_CHUNKID_SHIFT isn't defined or something."
680#endif
681*/
682
683/**
684 * Get the index of the page within the allocaiton chunk.
685 * @returns The page index.
686 * @param pPage Pointer to the physical guest page tracking structure.
687 */
688#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
689/* later:
690#if GMM_CHUNKID_SHIFT <= 12
691# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
692#else
693# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
694 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
695#endif
696*/
697
698
699/**
700 * Gets the page type.
701 * @returns The page type.
702 * @param pPage Pointer to the physical guest page tracking structure.
703 */
704#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
705
706/**
707 * Sets the page type.
708 * @param pPage Pointer to the physical guest page tracking structure.
709 * @param _enmType The new page type (PGMPAGETYPE).
710 */
711#ifdef VBOX_WITH_NEW_PHYS_CODE
712#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
713 do { (pPage)->u3Type = (_enmType); } while (0)
714#else
715#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
716 do { \
717 (pPage)->u3Type = (_enmType); \
718 if ((_enmType) == PGMPAGETYPE_ROM) \
719 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
720 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
721 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
722 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
723 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
724 } while (0)
725#endif
726
727
728/**
729 * Checks if the page is 'reserved'.
730 * @returns true/false.
731 * @param pPage Pointer to the physical guest page tracking structure.
732 */
733#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
734
735/**
736 * Checks if the page is marked for MMIO.
737 * @returns true/false.
738 * @param pPage Pointer to the physical guest page tracking structure.
739 */
740#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
741
742/**
743 * Checks if the page is backed by the ZERO page.
744 * @returns true/false.
745 * @param pPage Pointer to the physical guest page tracking structure.
746 */
747#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
748
749/**
750 * Checks if the page is backed by a SHARED page.
751 * @returns true/false.
752 * @param pPage Pointer to the physical guest page tracking structure.
753 */
754#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
755
756
757/**
758 * Marks the paget as written to (for GMM change monitoring).
759 * @param pPage Pointer to the physical guest page tracking structure.
760 */
761#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
762
763/**
764 * Clears the written-to indicator.
765 * @param pPage Pointer to the physical guest page tracking structure.
766 */
767#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
768
769/**
770 * Checks if the page was marked as written-to.
771 * @returns true/false.
772 * @param pPage Pointer to the physical guest page tracking structure.
773 */
774#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
775
776
777/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
778 *
779 * @remarks The values are assigned in order of priority, so we can calculate
780 * the correct state for a page with different handlers installed.
781 * @{ */
782/** No handler installed. */
783#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
784/** Monitoring is temporarily disabled. */
785#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
786/** Write access is monitored. */
787#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
788/** All access is monitored. */
789#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
790/** @} */
791
792/**
793 * Gets the physical access handler state of a page.
794 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
795 * @param pPage Pointer to the physical guest page tracking structure.
796 */
797#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
798
799/**
800 * Sets the physical access handler state of a page.
801 * @param pPage Pointer to the physical guest page tracking structure.
802 * @param _uState The new state value.
803 */
804#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
805 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
806
807/**
808 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
809 * @returns true/false
810 * @param pPage Pointer to the physical guest page tracking structure.
811 */
812#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
813
814/**
815 * Checks if the page has any active physical access handlers.
816 * @returns true/false
817 * @param pPage Pointer to the physical guest page tracking structure.
818 */
819#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
820
821
822/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
823 *
824 * @remarks The values are assigned in order of priority, so we can calculate
825 * the correct state for a page with different handlers installed.
826 * @{ */
827/** No handler installed. */
828#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
829/* 1 is reserved so the lineup is identical with the physical ones. */
830/** Write access is monitored. */
831#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
832/** All access is monitored. */
833#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
834/** @} */
835
836/**
837 * Gets the virtual access handler state of a page.
838 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
839 * @param pPage Pointer to the physical guest page tracking structure.
840 */
841#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
842
843/**
844 * Sets the virtual access handler state of a page.
845 * @param pPage Pointer to the physical guest page tracking structure.
846 * @param _uState The new state value.
847 */
848#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
849 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
850
851/**
852 * Checks if the page has any virtual access handlers.
853 * @returns true/false
854 * @param pPage Pointer to the physical guest page tracking structure.
855 */
856#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
857
858/**
859 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
860 * virtual handlers.
861 * @returns true/false
862 * @param pPage Pointer to the physical guest page tracking structure.
863 */
864#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
865
866
867
868/**
869 * Checks if the page has any access handlers, including temporarily disabled ones.
870 * @returns true/false
871 * @param pPage Pointer to the physical guest page tracking structure.
872 */
873#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
874 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
875 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
876
877/**
878 * Checks if the page has any active access handlers.
879 * @returns true/false
880 * @param pPage Pointer to the physical guest page tracking structure.
881 */
882#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
883 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
884 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
885
886/**
887 * Checks if the page has any active access handlers catching all accesses.
888 * @returns true/false
889 * @param pPage Pointer to the physical guest page tracking structure.
890 */
891#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
892 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
893 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
894
895
896/**
897 * Ram range for GC Phys to HC Phys conversion.
898 *
899 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
900 * conversions too, but we'll let MM handle that for now.
901 *
902 * This structure is used by linked lists in both GC and HC.
903 */
904typedef struct PGMRAMRANGE
905{
906 /** Pointer to the next RAM range - for R3. */
907 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
908 /** Pointer to the next RAM range - for R0. */
909 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
910 /** Pointer to the next RAM range - for GC. */
911 GCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
912#if GC_ARCH_BITS == 32
913 /** Pointer alignment. */
914 RTGCPTR GCPtrAlignment;
915#endif
916 /** Start of the range. Page aligned. */
917 RTGCPHYS GCPhys;
918 /** Last address in the range (inclusive). Page aligned (-1). */
919 RTGCPHYS GCPhysLast;
920 /** Size of the range. (Page aligned of course). */
921 RTGCPHYS cb;
922 /** MM_RAM_* flags */
923 uint32_t fFlags;
924#ifdef VBOX_WITH_NEW_PHYS_CODE
925 uint32_t u32Alignment; /**< alignment. */
926#else
927 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
928 GCPTRTYPE(PRTHCPTR) pavHCChunkGC;
929 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
930 R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
931#endif
932 /** Start of the HC mapping of the range. This is only used for MMIO2. */
933 R3PTRTYPE(void *) pvHC;
934 /** The range description. */
935 R3PTRTYPE(const char *) pszDesc;
936
937 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
938#ifdef VBOX_WITH_NEW_PHYS_CODE
939 uint32_t au32Reserved[2];
940#elif HC_ARCH_BITS == 32
941 uint32_t au32Reserved[1];
942#endif
943
944 /** Array of physical guest page tracking structures. */
945 PGMPAGE aPages[1];
946} PGMRAMRANGE;
947/** Pointer to Ram range for GC Phys to HC Phys conversion. */
948typedef PGMRAMRANGE *PPGMRAMRANGE;
949
950/** Return hc ptr corresponding to the ram range and physical offset */
951#define PGMRAMRANGE_GETHCPTR(pRam, off) \
952 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
953 : (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
954
955/**
956 * Per page tracking structure for ROM image.
957 *
958 * A ROM image may have a shadow page, in which case we may have
959 * two pages backing it. This structure contains the PGMPAGE for
960 * both while PGMRAMRANGE have a copy of the active one. It is
961 * important that these aren't out of sync in any regard other
962 * than page pool tracking data.
963 */
964typedef struct PGMROMPAGE
965{
966 /** The page structure for the virgin ROM page. */
967 PGMPAGE Virgin;
968 /** The page structure for the shadow RAM page. */
969 PGMPAGE Shadow;
970 /** The current protection setting. */
971 PGMROMPROT enmProt;
972 /** Pad the structure size to a multiple of 8. */
973 uint32_t u32Padding;
974} PGMROMPAGE;
975/** Pointer to a ROM page tracking structure. */
976typedef PGMROMPAGE *PPGMROMPAGE;
977
978
979/**
980 * A registered ROM image.
981 *
982 * This is needed to keep track of ROM image since they generally
983 * intrude into a PGMRAMRANGE. It also keeps track of additional
984 * info like the two page sets (read-only virgin and read-write shadow),
985 * the current state of each page.
986 *
987 * Because access handlers cannot easily be executed in a different
988 * context, the ROM ranges needs to be accessible and in all contexts.
989 */
990typedef struct PGMROMRANGE
991{
992 /** Pointer to the next range - R3. */
993 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
994 /** Pointer to the next range - R0. */
995 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
996 /** Pointer to the next range - GC. */
997 GCPTRTYPE(struct PGMROMRANGE *) pNextGC;
998#if GC_ARCH_BITS == 32
999 RTGCPTR GCPtrAlignment; /**< Pointer alignment. */
1000#endif
1001 /** Address of the range. */
1002 RTGCPHYS GCPhys;
1003 /** Address of the last byte in the range. */
1004 RTGCPHYS GCPhysLast;
1005 /** Size of the range. */
1006 RTGCPHYS cb;
1007 /** The flags (PGMPHYS_ROM_FLAG_*). */
1008 uint32_t fFlags;
1009 /**< Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1010 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1011 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1012 * This is used for strictness checks. */
1013 R3PTRTYPE(const void *) pvOriginal;
1014 /** The ROM description. */
1015 R3PTRTYPE(const char *) pszDesc;
1016 /** The per page tracking structures. */
1017 PGMROMPAGE aPages[1];
1018} PGMROMRANGE;
1019/** Pointer to a ROM range. */
1020typedef PGMROMRANGE *PPGMROMRANGE;
1021
1022
1023/**
1024 * A registered MMIO2 (= Device RAM) range.
1025 *
1026 * There are a few reason why we need to keep track of these
1027 * registrations. One of them is the deregistration & cleanup
1028 * stuff, while another is that the PGMRAMRANGE associated with
1029 * such a region may have to be removed from the ram range list.
1030 *
1031 * Overlapping with a RAM range has to be 100% or none at all. The
1032 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1033 * meditation will be raised if a partial overlap or an overlap of
1034 * ROM pages is encountered. On an overlap we will free all the
1035 * existing RAM pages and put in the ram range pages instead.
1036 */
1037typedef struct PGMMMIO2RANGE
1038{
1039 /** The owner of the range. (a device) */
1040 PPDMDEVINSR3 pDevInsR3;
1041 /** Pointer to the ring-3 mapping of the allocation. */
1042 RTR3PTR pvR3;
1043 /** Pointer to the next range - R3. */
1044 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1045 /** Whether it's mapped or not. */
1046 bool fMapped;
1047 /** Whether it's overlapping or not. */
1048 bool fOverlapping;
1049 /** The PCI region number.
1050 * @remarks This ASSUMES that nobody will ever really need to have multiple
1051 * PCI devices with matching MMIO region numbers on a single device. */
1052 uint8_t iRegion;
1053 /**< Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1054 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1055 /** The associated RAM range. */
1056 PGMRAMRANGE RamRange;
1057} PGMMMIO2RANGE;
1058/** Pointer to a MMIO2 range. */
1059typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1060
1061
1062
1063
1064/** @todo r=bird: fix typename. */
1065/**
1066 * PGMPhysRead/Write cache entry
1067 */
1068typedef struct PGMPHYSCACHE_ENTRY
1069{
1070 /** HC pointer to physical page */
1071 R3PTRTYPE(uint8_t *) pbHC;
1072 /** GC Physical address for cache entry */
1073 RTGCPHYS GCPhys;
1074#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1075 RTGCPHYS u32Padding0; /**< alignment padding. */
1076#endif
1077} PGMPHYSCACHE_ENTRY;
1078
1079/**
1080 * PGMPhysRead/Write cache to reduce REM memory access overhead
1081 */
1082typedef struct PGMPHYSCACHE
1083{
1084 /** Bitmap of valid cache entries */
1085 uint64_t aEntries;
1086 /** Cache entries */
1087 PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1088} PGMPHYSCACHE;
1089
1090
1091/** Pointer to an allocation chunk ring-3 mapping. */
1092typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1093/** Pointer to an allocation chunk ring-3 mapping pointer. */
1094typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1095
1096/**
1097 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1098 *
1099 * The primary tree (Core) uses the chunk id as key.
1100 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1101 */
1102typedef struct PGMCHUNKR3MAP
1103{
1104 /** The key is the chunk id. */
1105 AVLU32NODECORE Core;
1106 /** The key is the ageing sequence number. */
1107 AVLLU32NODECORE AgeCore;
1108 /** The current age thingy. */
1109 uint32_t iAge;
1110 /** The current reference count. */
1111 uint32_t volatile cRefs;
1112 /** The current permanent reference count. */
1113 uint32_t volatile cPermRefs;
1114 /** The mapping address. */
1115 void *pv;
1116} PGMCHUNKR3MAP;
1117
1118/**
1119 * Allocation chunk ring-3 mapping TLB entry.
1120 */
1121typedef struct PGMCHUNKR3MAPTLBE
1122{
1123 /** The chunk id. */
1124 uint32_t volatile idChunk;
1125#if HC_ARCH_BITS == 64
1126 uint32_t u32Padding; /**< alignment padding. */
1127#endif
1128 /** The chunk map. */
1129 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1130} PGMCHUNKR3MAPTLBE;
1131/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1132typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1133
1134/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1135 * @remark Must be a power of two value. */
1136#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1137
1138/**
1139 * Allocation chunk ring-3 mapping TLB.
1140 *
1141 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1142 * At first glance this might look kinda odd since AVL trees are
1143 * supposed to give the most optimial lookup times of all trees
1144 * due to their balancing. However, take a tree with 1023 nodes
1145 * in it, that's 10 levels, meaning that most searches has to go
1146 * down 9 levels before they find what they want. This isn't fast
1147 * compared to a TLB hit. There is the factor of cache misses,
1148 * and of course the problem with trees and branch prediction.
1149 * This is why we use TLBs in front of most of the trees.
1150 *
1151 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1152 * difficult when we switch to inlined AVL trees (from kStuff).
1153 */
1154typedef struct PGMCHUNKR3MAPTLB
1155{
1156 /** The TLB entries. */
1157 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1158} PGMCHUNKR3MAPTLB;
1159
1160/**
1161 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1162 * @returns Chunk TLB index.
1163 * @param idChunk The Chunk ID.
1164 */
1165#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1166
1167
1168/**
1169 * Ring-3 guest page mapping TLB entry.
1170 * @remarks used in ring-0 as well at the moment.
1171 */
1172typedef struct PGMPAGER3MAPTLBE
1173{
1174 /** Address of the page. */
1175 RTGCPHYS volatile GCPhys;
1176 /** The guest page. */
1177 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1178 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1179 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1180 /** The address */
1181 R3R0PTRTYPE(void *) volatile pv;
1182#if HC_ARCH_BITS == 32
1183 uint32_t u32Padding; /**< alignment padding. */
1184#endif
1185} PGMPAGER3MAPTLBE;
1186/** Pointer to an entry in the HC physical TLB. */
1187typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1188
1189
1190/** The number of entries in the ring-3 guest page mapping TLB.
1191 * @remarks The value must be a power of two. */
1192#define PGM_PAGER3MAPTLB_ENTRIES 64
1193
1194/**
1195 * Ring-3 guest page mapping TLB.
1196 * @remarks used in ring-0 as well at the moment.
1197 */
1198typedef struct PGMPAGER3MAPTLB
1199{
1200 /** The TLB entries. */
1201 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1202} PGMPAGER3MAPTLB;
1203/** Pointer to the ring-3 guest page mapping TLB. */
1204typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1205
1206/**
1207 * Calculates the index of the TLB entry for the specified guest page.
1208 * @returns Physical TLB index.
1209 * @param GCPhys The guest physical address.
1210 */
1211#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1212
1213
1214/** @name Context neutrual page mapper TLB.
1215 *
1216 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1217 * code is writting in a kind of context neutrual way. Time will show whether
1218 * this actually makes sense or not...
1219 *
1220 * @{ */
1221/** @typedef PPGMPAGEMAPTLB
1222 * The page mapper TLB pointer type for the current context. */
1223/** @typedef PPGMPAGEMAPTLB
1224 * The page mapper TLB entry pointer type for the current context. */
1225/** @typedef PPGMPAGEMAPTLB
1226 * The page mapper TLB entry pointer pointer type for the current context. */
1227/** @def PGMPAGEMAPTLB_ENTRIES
1228 * The number of TLB entries in the page mapper TLB for the current context. */
1229/** @def PGM_PAGEMAPTLB_IDX
1230 * Calculate the TLB index for a guest physical address.
1231 * @returns The TLB index.
1232 * @param GCPhys The guest physical address. */
1233/** @typedef PPGMPAGEMAP
1234 * Pointer to a page mapper unit for current context. */
1235/** @typedef PPPGMPAGEMAP
1236 * Pointer to a page mapper unit pointer for current context. */
1237#ifdef IN_GC
1238// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1239// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1240// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1241# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1242# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1243 typedef void * PPGMPAGEMAP;
1244 typedef void ** PPPGMPAGEMAP;
1245//#elif IN_RING0
1246// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1247// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1248// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1249//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1250//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1251// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1252// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1253#else
1254 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1255 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1256 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1257# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1258# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1259 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1260 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1261#endif
1262/** @} */
1263
1264
1265/** @name PGM Pool Indexes.
1266 * Aka. the unique shadow page identifier.
1267 * @{ */
1268/** NIL page pool IDX. */
1269#define NIL_PGMPOOL_IDX 0
1270/** The first normal index. */
1271#define PGMPOOL_IDX_FIRST_SPECIAL 1
1272/** Page directory (32-bit root). */
1273#define PGMPOOL_IDX_PD 1
1274/** The extended PAE page directory (2048 entries, works as root currently). */
1275#define PGMPOOL_IDX_PAE_PD 2
1276 /** PAE Page Directory Table 0. */
1277#define PGMPOOL_IDX_PAE_PD_0 3
1278 /** PAE Page Directory Table 1. */
1279#define PGMPOOL_IDX_PAE_PD_1 4
1280 /** PAE Page Directory Table 2. */
1281#define PGMPOOL_IDX_PAE_PD_2 5
1282 /** PAE Page Directory Table 3. */
1283#define PGMPOOL_IDX_PAE_PD_3 6
1284/** Page Directory Pointer Table (PAE root, not currently used). */
1285#define PGMPOOL_IDX_PDPT 7
1286/** Page Map Level-4 (64-bit root). */
1287#define PGMPOOL_IDX_PML4 8
1288/** The first normal index. */
1289#define PGMPOOL_IDX_FIRST 9
1290/** The last valid index. (inclusive, 14 bits) */
1291#define PGMPOOL_IDX_LAST 0x3fff
1292/** @} */
1293
1294/** The NIL index for the parent chain. */
1295#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1296
1297/**
1298 * Node in the chain linking a shadowed page to it's parent (user).
1299 */
1300#pragma pack(1)
1301typedef struct PGMPOOLUSER
1302{
1303 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1304 uint16_t iNext;
1305 /** The user page index. */
1306 uint16_t iUser;
1307 /** Index into the user table. */
1308 uint16_t iUserTable;
1309} PGMPOOLUSER, *PPGMPOOLUSER;
1310typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1311#pragma pack()
1312
1313
1314/** The NIL index for the phys ext chain. */
1315#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1316
1317/**
1318 * Node in the chain of physical cross reference extents.
1319 */
1320#pragma pack(1)
1321typedef struct PGMPOOLPHYSEXT
1322{
1323 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1324 uint16_t iNext;
1325 /** The user page index. */
1326 uint16_t aidx[3];
1327} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1328typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1329#pragma pack()
1330
1331
1332/**
1333 * The kind of page that's being shadowed.
1334 */
1335typedef enum PGMPOOLKIND
1336{
1337 /** The virtual invalid 0 entry. */
1338 PGMPOOLKIND_INVALID = 0,
1339 /** The entry is free (=unused). */
1340 PGMPOOLKIND_FREE,
1341
1342 /** Shw: 32-bit page table; Gst: no paging */
1343 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1344 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1345 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1346 /** Shw: 32-bit page table; Gst: 4MB page. */
1347 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1348 /** Shw: PAE page table; Gst: no paging */
1349 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1350 /** Shw: PAE page table; Gst: 32-bit page table. */
1351 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1352 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1353 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1354 /** Shw: PAE page table; Gst: PAE page table. */
1355 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1356 /** Shw: PAE page table; Gst: 2MB page. */
1357 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1358
1359 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1360 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1361 /** Shw: PAE page directory; Gst: PAE page directory. */
1362 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1363
1364 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1365 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1366 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1367 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1368
1369 /** Shw: Root 32-bit page directory. */
1370 PGMPOOLKIND_ROOT_32BIT_PD,
1371 /** Shw: Root PAE page directory */
1372 PGMPOOLKIND_ROOT_PAE_PD,
1373 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1374 PGMPOOLKIND_ROOT_PDPT,
1375 /** Shw: Root page map level-4 table. */
1376 PGMPOOLKIND_ROOT_PML4,
1377
1378 /** The last valid entry. */
1379 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PML4
1380} PGMPOOLKIND;
1381
1382
1383/**
1384 * The tracking data for a page in the pool.
1385 */
1386typedef struct PGMPOOLPAGE
1387{
1388 /** AVL node code with the (HC) physical address of this page. */
1389 AVLOHCPHYSNODECORE Core;
1390 /** Pointer to the HC mapping of the page. */
1391 R3R0PTRTYPE(void *) pvPageHC;
1392 /** The guest physical address. */
1393 RTGCPHYS GCPhys;
1394 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1395 uint8_t enmKind;
1396 uint8_t bPadding;
1397 /** The index of this page. */
1398 uint16_t idx;
1399 /** The next entry in the list this page currently resides in.
1400 * It's either in the free list or in the GCPhys hash. */
1401 uint16_t iNext;
1402#ifdef PGMPOOL_WITH_USER_TRACKING
1403 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1404 uint16_t iUserHead;
1405 /** The number of present entries. */
1406 uint16_t cPresent;
1407 /** The first entry in the table which is present. */
1408 uint16_t iFirstPresent;
1409#endif
1410#ifdef PGMPOOL_WITH_MONITORING
1411 /** The number of modifications to the monitored page. */
1412 uint16_t cModifications;
1413 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1414 uint16_t iModifiedNext;
1415 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1416 uint16_t iModifiedPrev;
1417 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1418 uint16_t iMonitoredNext;
1419 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1420 uint16_t iMonitoredPrev;
1421#endif
1422#ifdef PGMPOOL_WITH_CACHE
1423 /** The next page in the age list. */
1424 uint16_t iAgeNext;
1425 /** The previous page in the age list. */
1426 uint16_t iAgePrev;
1427#endif /* PGMPOOL_WITH_CACHE */
1428 /** Used to indicate that the page is zeroed. */
1429 bool fZeroed;
1430 /** Used to indicate that a PT has non-global entries. */
1431 bool fSeenNonGlobal;
1432 /** Used to indicate that we're monitoring writes to the guest page. */
1433 bool fMonitored;
1434 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1435 * (All pages are in the age list.) */
1436 bool fCached;
1437 /** This is used by the R3 access handlers when invoked by an async thread.
1438 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1439 bool volatile fReusedFlushPending;
1440 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1441 * In these cases the access handler acts differently and will check
1442 * for mapping conflicts like the normal CR3 handler.
1443 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1444 * replaced by a list of pages which share access handler.
1445 */
1446 bool fCR3Mix;
1447} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1448
1449
1450#ifdef PGMPOOL_WITH_CACHE
1451/** The hash table size. */
1452# define PGMPOOL_HASH_SIZE 0x40
1453/** The hash function. */
1454# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1455#endif
1456
1457
1458/**
1459 * The shadow page pool instance data.
1460 *
1461 * It's all one big allocation made at init time, except for the
1462 * pages that is. The user nodes follows immediatly after the
1463 * page structures.
1464 */
1465typedef struct PGMPOOL
1466{
1467 /** The VM handle - HC Ptr. */
1468 R3R0PTRTYPE(PVM) pVMHC;
1469 /** The VM handle - GC Ptr. */
1470 GCPTRTYPE(PVM) pVMGC;
1471 /** The max pool size. This includes the special IDs. */
1472 uint16_t cMaxPages;
1473 /** The current pool size. */
1474 uint16_t cCurPages;
1475 /** The head of the free page list. */
1476 uint16_t iFreeHead;
1477 /* Padding. */
1478 uint16_t u16Padding;
1479#ifdef PGMPOOL_WITH_USER_TRACKING
1480 /** Head of the chain of free user nodes. */
1481 uint16_t iUserFreeHead;
1482 /** The number of user nodes we've allocated. */
1483 uint16_t cMaxUsers;
1484 /** The number of present page table entries in the entire pool. */
1485 uint32_t cPresent;
1486 /** Pointer to the array of user nodes - GC pointer. */
1487 GCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1488 /** Pointer to the array of user nodes - HC pointer. */
1489 R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1490#endif /* PGMPOOL_WITH_USER_TRACKING */
1491#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1492 /** Head of the chain of free phys ext nodes. */
1493 uint16_t iPhysExtFreeHead;
1494 /** The number of user nodes we've allocated. */
1495 uint16_t cMaxPhysExts;
1496 /** Pointer to the array of physical xref extent - GC pointer. */
1497 GCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1498 /** Pointer to the array of physical xref extent nodes - HC pointer. */
1499 R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1500#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1501#ifdef PGMPOOL_WITH_CACHE
1502 /** Hash table for GCPhys addresses. */
1503 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1504 /** The head of the age list. */
1505 uint16_t iAgeHead;
1506 /** The tail of the age list. */
1507 uint16_t iAgeTail;
1508 /** Set if the cache is enabled. */
1509 bool fCacheEnabled;
1510#endif /* PGMPOOL_WITH_CACHE */
1511#ifdef PGMPOOL_WITH_MONITORING
1512 /** Head of the list of modified pages. */
1513 uint16_t iModifiedHead;
1514 /** The current number of modified pages. */
1515 uint16_t cModifiedPages;
1516 /** Access handler, GC. */
1517 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1518 /** Access handler, R0. */
1519 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1520 /** Access handler, R3. */
1521 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1522 /** The access handler description (HC ptr). */
1523 R3PTRTYPE(const char *) pszAccessHandler;
1524#endif /* PGMPOOL_WITH_MONITORING */
1525 /** The number of pages currently in use. */
1526 uint16_t cUsedPages;
1527#ifdef VBOX_WITH_STATISTICS
1528 /** The high wather mark for cUsedPages. */
1529 uint16_t cUsedPagesHigh;
1530 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1531 /** Profiling pgmPoolAlloc(). */
1532 STAMPROFILEADV StatAlloc;
1533 /** Profiling pgmPoolClearAll(). */
1534 STAMPROFILE StatClearAll;
1535 /** Profiling pgmPoolFlushAllInt(). */
1536 STAMPROFILE StatFlushAllInt;
1537 /** Profiling pgmPoolFlushPage(). */
1538 STAMPROFILE StatFlushPage;
1539 /** Profiling pgmPoolFree(). */
1540 STAMPROFILE StatFree;
1541 /** Profiling time spent zeroing pages. */
1542 STAMPROFILE StatZeroPage;
1543# ifdef PGMPOOL_WITH_USER_TRACKING
1544 /** Profiling of pgmPoolTrackDeref. */
1545 STAMPROFILE StatTrackDeref;
1546 /** Profiling pgmTrackFlushGCPhysPT. */
1547 STAMPROFILE StatTrackFlushGCPhysPT;
1548 /** Profiling pgmTrackFlushGCPhysPTs. */
1549 STAMPROFILE StatTrackFlushGCPhysPTs;
1550 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1551 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1552 /** Number of times we've been out of user records. */
1553 STAMCOUNTER StatTrackFreeUpOneUser;
1554# endif
1555# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1556 /** Profiling deref activity related tracking GC physical pages. */
1557 STAMPROFILE StatTrackDerefGCPhys;
1558 /** Number of linear searches for a HCPhys in the ram ranges. */
1559 STAMCOUNTER StatTrackLinearRamSearches;
1560 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1561 STAMCOUNTER StamTrackPhysExtAllocFailures;
1562# endif
1563# ifdef PGMPOOL_WITH_MONITORING
1564 /** Profiling the GC PT access handler. */
1565 STAMPROFILE StatMonitorGC;
1566 /** Times we've failed interpreting the instruction. */
1567 STAMCOUNTER StatMonitorGCEmulateInstr;
1568 /** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1569 STAMPROFILE StatMonitorGCFlushPage;
1570 /** Times we've detected fork(). */
1571 STAMCOUNTER StatMonitorGCFork;
1572 /** Profiling the GC access we've handled (except REP STOSD). */
1573 STAMPROFILE StatMonitorGCHandled;
1574 /** Times we've failed interpreting a patch code instruction. */
1575 STAMCOUNTER StatMonitorGCIntrFailPatch1;
1576 /** Times we've failed interpreting a patch code instruction during flushing. */
1577 STAMCOUNTER StatMonitorGCIntrFailPatch2;
1578 /** The number of times we've seen rep prefixes we can't handle. */
1579 STAMCOUNTER StatMonitorGCRepPrefix;
1580 /** Profiling the REP STOSD cases we've handled. */
1581 STAMPROFILE StatMonitorGCRepStosd;
1582
1583 /** Profiling the HC PT access handler. */
1584 STAMPROFILE StatMonitorHC;
1585 /** Times we've failed interpreting the instruction. */
1586 STAMCOUNTER StatMonitorHCEmulateInstr;
1587 /** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1588 STAMPROFILE StatMonitorHCFlushPage;
1589 /** Times we've detected fork(). */
1590 STAMCOUNTER StatMonitorHCFork;
1591 /** Profiling the HC access we've handled (except REP STOSD). */
1592 STAMPROFILE StatMonitorHCHandled;
1593 /** The number of times we've seen rep prefixes we can't handle. */
1594 STAMCOUNTER StatMonitorHCRepPrefix;
1595 /** Profiling the REP STOSD cases we've handled. */
1596 STAMPROFILE StatMonitorHCRepStosd;
1597 /** The number of times we're called in an async thread an need to flush. */
1598 STAMCOUNTER StatMonitorHCAsync;
1599 /** The high wather mark for cModifiedPages. */
1600 uint16_t cModifiedPagesHigh;
1601 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1602# endif
1603# ifdef PGMPOOL_WITH_CACHE
1604 /** The number of cache hits. */
1605 STAMCOUNTER StatCacheHits;
1606 /** The number of cache misses. */
1607 STAMCOUNTER StatCacheMisses;
1608 /** The number of times we've got a conflict of 'kind' in the cache. */
1609 STAMCOUNTER StatCacheKindMismatches;
1610 /** Number of times we've been out of pages. */
1611 STAMCOUNTER StatCacheFreeUpOne;
1612 /** The number of cacheable allocations. */
1613 STAMCOUNTER StatCacheCacheable;
1614 /** The number of uncacheable allocations. */
1615 STAMCOUNTER StatCacheUncacheable;
1616# endif
1617#elif HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1618 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1619#endif
1620 /** The AVL tree for looking up a page by its HC physical address. */
1621 AVLOHCPHYSTREE HCPhysTree;
1622 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1623 /** Array of pages. (cMaxPages in length)
1624 * The Id is the index into thist array.
1625 */
1626 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1627} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1628
1629
1630/** @def PGMPOOL_PAGE_2_PTR
1631 * Maps a pool page pool into the current context.
1632 *
1633 * @returns VBox status code.
1634 * @param pVM The VM handle.
1635 * @param pPage The pool page.
1636 *
1637 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1638 * small page window employeed by that function. Be careful.
1639 * @remark There is no need to assert on the result.
1640 */
1641#ifdef IN_GC
1642# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1643#else
1644# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1645#endif
1646
1647
1648/**
1649 * Trees are using self relative offsets as pointers.
1650 * So, all its data, including the root pointer, must be in the heap for HC and GC
1651 * to have the same layout.
1652 */
1653typedef struct PGMTREES
1654{
1655 /** Physical access handlers (AVL range+offsetptr tree). */
1656 AVLROGCPHYSTREE PhysHandlers;
1657 /** Virtual access handlers (AVL range + GC ptr tree). */
1658 AVLROGCPTRTREE VirtHandlers;
1659 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1660 AVLROGCPHYSTREE PhysToVirtHandlers;
1661 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1662 AVLROGCPTRTREE HyperVirtHandlers;
1663} PGMTREES;
1664/** Pointer to PGM trees. */
1665typedef PGMTREES *PPGMTREES;
1666
1667
1668/** @name Paging mode macros
1669 * @{ */
1670#ifdef IN_GC
1671# define PGM_CTX(a,b) a##GC##b
1672# define PGM_CTX_STR(a,b) a "GC" b
1673# define PGM_CTX_DECL(type) PGMGCDECL(type)
1674#else
1675# ifdef IN_RING3
1676# define PGM_CTX(a,b) a##R3##b
1677# define PGM_CTX_STR(a,b) a "R3" b
1678# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1679# else
1680# define PGM_CTX(a,b) a##R0##b
1681# define PGM_CTX_STR(a,b) a "R0" b
1682# define PGM_CTX_DECL(type) PGMDECL(type)
1683# endif
1684#endif
1685
1686#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1687#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1688#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1689#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1690#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1691#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1692#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1693#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1694#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1695#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1696#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1697#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1698#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1699#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1700#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1701#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1702#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1703
1704#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1705#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1706#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1707#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1708#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1709#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1710#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1711#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1712#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1713#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1714#define PGM_SHW_NAME_GC_NESTED_STR(name) "pgmGCShwNested" #name
1715#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1716#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1717#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1718
1719/* Shw_Gst */
1720#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1721#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1722#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1723#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1724#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1725#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1726#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1727#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1728#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1729#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1730#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1731#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1732#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1733#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1734
1735#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1736#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1737#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1738#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1739#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1740#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1741#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1742#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1743#define PGM_BTH_NAME_GC_NESTED_REAL_STR(name) "pgmGCBthNestedReal" #name
1744#define PGM_BTH_NAME_GC_NESTED_PROT_STR(name) "pgmGCBthNestedProt" #name
1745#define PGM_BTH_NAME_GC_NESTED_32BIT_STR(name) "pgmGCBthNested32Bit" #name
1746#define PGM_BTH_NAME_GC_NESTED_PAE_STR(name) "pgmGCBthNestedPAE" #name
1747#define PGM_BTH_NAME_GC_NESTED_AMD64_STR(name) "pgmGCBthNestedAMD64" #name
1748#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1749#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1750#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1751#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1752#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1753#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1754#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1755#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1756#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1757#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1758#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1759#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1760#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1761#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
1762
1763#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1764#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1765/** @} */
1766
1767/**
1768 * Data for each paging mode.
1769 */
1770typedef struct PGMMODEDATA
1771{
1772 /** The guest mode type. */
1773 uint32_t uGstType;
1774 /** The shadow mode type. */
1775 uint32_t uShwType;
1776
1777 /** @name Function pointers for Shadow paging.
1778 * @{
1779 */
1780 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1781 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1782 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1783 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1784
1785 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1786 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1787
1788 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1789 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1790 /** @} */
1791
1792 /** @name Function pointers for Guest paging.
1793 * @{
1794 */
1795 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1796 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1797 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1798 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1799 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1800 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1801 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1802 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1803 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1804 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1805 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1806 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1807 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1808
1809 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1810 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1811 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1812 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1813 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1814 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1815 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1816 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1817 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1818
1819 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1820 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1821 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1822 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1823 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1824 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1825 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1826 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1827 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1828 /** @} */
1829
1830 /** @name Function pointers for Both Shadow and Guest paging.
1831 * @{
1832 */
1833 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1834 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1835 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1836 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1837 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1838 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1839 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1840#ifdef VBOX_STRICT
1841 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1842#endif
1843
1844 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1845 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1846 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1847 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1848 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1849 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1850#ifdef VBOX_STRICT
1851 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1852#endif
1853
1854 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1855 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1856 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1857 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1858 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1859 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1860#ifdef VBOX_STRICT
1861 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1862#endif
1863 /** @} */
1864} PGMMODEDATA, *PPGMMODEDATA;
1865
1866
1867
1868/**
1869 * Converts a PGM pointer into a VM pointer.
1870 * @returns Pointer to the VM structure the PGM is part of.
1871 * @param pPGM Pointer to PGM instance data.
1872 */
1873#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1874
1875/**
1876 * PGM Data (part of VM)
1877 */
1878typedef struct PGM
1879{
1880 /** Offset to the VM structure. */
1881 RTINT offVM;
1882
1883 /*
1884 * This will be redefined at least two more times before we're done, I'm sure.
1885 * The current code is only to get on with the coding.
1886 * - 2004-06-10: initial version, bird.
1887 * - 2004-07-02: 1st time, bird.
1888 * - 2004-10-18: 2nd time, bird.
1889 * - 2005-07-xx: 3rd time, bird.
1890 */
1891
1892 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1893 GCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1894 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1895 GCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1896
1897 /** The host paging mode. (This is what SUPLib reports.) */
1898 SUPPAGINGMODE enmHostMode;
1899 /** The shadow paging mode. */
1900 PGMMODE enmShadowMode;
1901 /** The guest paging mode. */
1902 PGMMODE enmGuestMode;
1903
1904 /** The current physical address representing in the guest CR3 register. */
1905 RTGCPHYS GCPhysCR3;
1906 /** Pointer to the 5 page CR3 content mapping.
1907 * The first page is always the CR3 (in some form) while the 4 other pages
1908 * are used of the PDs in PAE mode. */
1909 RTGCPTR GCPtrCR3Mapping;
1910#if HC_ARCH_BITS == 64
1911 uint32_t u32Alignment;
1912#endif
1913 /** The physical address of the currently monitored guest CR3 page.
1914 * When this value is NIL_RTGCPHYS no page is being monitored. */
1915 RTGCPHYS GCPhysGstCR3Monitored;
1916
1917 /** @name 32-bit Guest Paging.
1918 * @{ */
1919 /** The guest's page directory, HC pointer. */
1920 R3R0PTRTYPE(PX86PD) pGuestPDHC;
1921 /** The guest's page directory, static GC mapping. */
1922 GCPTRTYPE(PX86PD) pGuestPDGC;
1923 /** @} */
1924
1925 /** @name PAE Guest Paging.
1926 * @{ */
1927 /** The guest's page directory pointer table, static GC mapping. */
1928 GCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
1929 /** The guest's page directory pointer table, HC pointer. */
1930 R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1931 /** The guest's page directories, HC pointers.
1932 * These are individual pointers and don't have to be adjecent.
1933 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1934 R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1935 /** The guest's page directories, static GC mapping.
1936 * Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1937 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1938 GCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1939 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1940 RTGCPHYS aGCPhysGstPaePDs[4];
1941 /** The physical addresses of the monitored guest page directories (PAE). */
1942 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1943 /** @} */
1944
1945 /** @name AMD64 Guest Paging.
1946 * @{ */
1947 /** The guest's page directory pointer table, HC pointer. */
1948 R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
1949 /** @} */
1950
1951 /** @name 32-bit Shadow Paging
1952 * @{ */
1953 /** The 32-Bit PD - HC Ptr. */
1954 R3R0PTRTYPE(PX86PD) pHC32BitPD;
1955 /** The 32-Bit PD - GC Ptr. */
1956 GCPTRTYPE(PX86PD) pGC32BitPD;
1957#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1958 uint32_t u32Padding1; /**< alignment padding. */
1959#endif
1960 /** The Physical Address (HC) of the 32-Bit PD. */
1961 RTHCPHYS HCPhys32BitPD;
1962 /** @} */
1963
1964 /** @name PAE Shadow Paging
1965 * @{ */
1966 /** The four PDs for the low 4GB - HC Ptr.
1967 * Even though these are 4 pointers, what they point at is a single table.
1968 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
1969 R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
1970 /** The four PDs for the low 4GB - GC Ptr.
1971 * Same kind of mapping as apHCPaePDs. */
1972 GCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
1973 /** The Physical Address (HC) of the four PDs for the low 4GB.
1974 * These are *NOT* 4 contiguous pages. */
1975 RTHCPHYS aHCPhysPaePDs[4];
1976 /** The PAE PDP - HC Ptr. */
1977 R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
1978 /** The Physical Address (HC) of the PAE PDPT. */
1979 RTHCPHYS HCPhysPaePDPT;
1980 /** The PAE PDPT - GC Ptr. */
1981 GCPTRTYPE(PX86PDPT) pGCPaePDPT;
1982 /** @} */
1983
1984 /** @name AMD64 Shadow Paging
1985 * Extends PAE Paging.
1986 * @{ */
1987#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1988 RTGCPTR alignment5; /**< structure size alignment. */
1989#endif
1990 /** The Page Map Level 4 table - HC Ptr. */
1991 R3R0PTRTYPE(PX86PML4) pHCPaePML4;
1992 /** The Physical Address (HC) of the Page Map Level 4 table. */
1993 RTHCPHYS HCPhysPaePML4;
1994 /** @}*/
1995
1996 /** @name Function pointers for Shadow paging.
1997 * @{
1998 */
1999 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2000 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2001 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2002 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2003
2004 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2005 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2006
2007 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2008 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2009
2010 /** @} */
2011
2012 /** @name Function pointers for Guest paging.
2013 * @{
2014 */
2015 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2016 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2017 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2018 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2019 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2020 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2021 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2022 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2023 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2024 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2025 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2026 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2027 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2028
2029 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2030 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2031 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2032 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2033 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
2034 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2035 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
2036 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
2037 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
2038#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2039 RTGCPTR alignment3; /**< structure size alignment. */
2040#endif
2041
2042 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2043 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2044 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2045 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2046 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2047 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2048 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2049 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2050 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2051 /** @} */
2052
2053 /** @name Function pointers for Both Shadow and Guest paging.
2054 * @{
2055 */
2056 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2057 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2058 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2059 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2060 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2061 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2062 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2063 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2064
2065 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2066 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2067 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2068 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2069 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2070 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2071 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2072
2073 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2074 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2075 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2076 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2077 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2078 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2079 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2080#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2081 RTGCPTR alignment2; /**< structure size alignment. */
2082#endif
2083 /** @} */
2084
2085 /** Pointer to SHW+GST mode data (function pointers).
2086 * The index into this table is made up from */
2087 R3PTRTYPE(PPGMMODEDATA) paModeData;
2088
2089 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2090 * This is sorted by physical address and contains no overlapping ranges. */
2091 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2092 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2093 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2094 /** GC pointer corresponding to PGM::pRamRangesR3. */
2095 GCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
2096 /** The configured RAM size. */
2097 RTUINT cbRamSize;
2098
2099 /** Pointer to the list of ROM ranges - for R3.
2100 * This is sorted by physical address and contains no overlapping ranges. */
2101 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2102 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2103 R0PTRTYPE(PPGMRAMRANGE) pRomRangesR0;
2104 /** GC pointer corresponding to PGM::pRomRangesR3. */
2105 GCPTRTYPE(PPGMRAMRANGE) pRomRangesGC;
2106 /** Alignment padding. */
2107 RTGCPTR GCPtrPadding2;
2108
2109 /** Pointer to the list of MMIO2 ranges - for R3.
2110 * Registration order. */
2111 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2112
2113 /** PGM offset based trees - HC Ptr. */
2114 R3R0PTRTYPE(PPGMTREES) pTreesHC;
2115 /** PGM offset based trees - GC Ptr. */
2116 GCPTRTYPE(PPGMTREES) pTreesGC;
2117
2118 /** Linked list of GC mappings - for GC.
2119 * The list is sorted ascending on address.
2120 */
2121 GCPTRTYPE(PPGMMAPPING) pMappingsGC;
2122 /** Linked list of GC mappings - for HC.
2123 * The list is sorted ascending on address.
2124 */
2125 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2126 /** Linked list of GC mappings - for R0.
2127 * The list is sorted ascending on address.
2128 */
2129 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2130
2131 /** If set no conflict checks are required. (boolean) */
2132 bool fMappingsFixed;
2133 /** If set, then no mappings are put into the shadow page table. (boolean) */
2134 bool fDisableMappings;
2135 /** Size of fixed mapping */
2136 uint32_t cbMappingFixed;
2137 /** Base address (GC) of fixed mapping */
2138 RTGCPTR GCPtrMappingFixed;
2139#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2140 uint32_t u32Padding0; /**< alignment padding. */
2141#endif
2142
2143
2144 /** @name Intermediate Context
2145 * @{ */
2146 /** Pointer to the intermediate page directory - Normal. */
2147 R3PTRTYPE(PX86PD) pInterPD;
2148 /** Pointer to the intermedate page tables - Normal.
2149 * There are two page tables, one for the identity mapping and one for
2150 * the host context mapping (of the core code). */
2151 R3PTRTYPE(PX86PT) apInterPTs[2];
2152 /** Pointer to the intermedate page tables - PAE. */
2153 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2154 /** Pointer to the intermedate page directory - PAE. */
2155 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2156 /** Pointer to the intermedate page directory - PAE. */
2157 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2158 /** Pointer to the intermedate page-map level 4 - AMD64. */
2159 R3PTRTYPE(PX86PML4) pInterPaePML4;
2160 /** Pointer to the intermedate page directory - AMD64. */
2161 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2162 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2163 RTHCPHYS HCPhysInterPD;
2164 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2165 RTHCPHYS HCPhysInterPaePDPT;
2166 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2167 RTHCPHYS HCPhysInterPaePML4;
2168 /** @} */
2169
2170 /** Base address of the dynamic page mapping area.
2171 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2172 */
2173 GCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2174 /** The index of the last entry used in the dynamic page mapping area. */
2175 RTUINT iDynPageMapLast;
2176 /** Cache containing the last entries in the dynamic page mapping area.
2177 * The cache size is covering half of the mapping area. */
2178 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2179
2180 /** A20 gate mask.
2181 * Our current approach to A20 emulation is to let REM do it and don't bother
2182 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2183 * But whould need arrise, we'll subject physical addresses to this mask. */
2184 RTGCPHYS GCPhysA20Mask;
2185 /** A20 gate state - boolean! */
2186 RTUINT fA20Enabled;
2187
2188 /** What needs syncing (PGM_SYNC_*).
2189 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2190 * PGMFlushTLB, and PGMR3Load. */
2191 RTUINT fSyncFlags;
2192
2193 /** PGM critical section.
2194 * This protects the physical & virtual access handlers, ram ranges,
2195 * and the page flag updating (some of it anyway).
2196 */
2197 PDMCRITSECT CritSect;
2198
2199 /** Shadow Page Pool - HC Ptr. */
2200 R3R0PTRTYPE(PPGMPOOL) pPoolHC;
2201 /** Shadow Page Pool - GC Ptr. */
2202 GCPTRTYPE(PPGMPOOL) pPoolGC;
2203
2204 /** We're not in a state which permits writes to guest memory.
2205 * (Only used in strict builds.) */
2206 bool fNoMorePhysWrites;
2207
2208 /** Flush the cache on the next access. */
2209 bool fPhysCacheFlushPending;
2210/** @todo r=bird: Fix member names!*/
2211 /** PGMPhysRead cache */
2212 PGMPHYSCACHE pgmphysreadcache;
2213 /** PGMPhysWrite cache */
2214 PGMPHYSCACHE pgmphyswritecache;
2215
2216 /**
2217 * Data associated with managing the ring-3 mappings of the allocation chunks.
2218 */
2219 struct
2220 {
2221 /** The chunk tree, ordered by chunk id. */
2222 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2223 /** The chunk mapping TLB. */
2224 PGMCHUNKR3MAPTLB Tlb;
2225 /** The number of mapped chunks. */
2226 uint32_t c;
2227 /** The maximum number of mapped chunks.
2228 * @cfgm PGM/MaxRing3Chunks */
2229 uint32_t cMax;
2230 /** The chunk age tree, ordered by ageing sequence number. */
2231 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2232 /** The current time. */
2233 uint32_t iNow;
2234 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2235 uint32_t AgeingCountdown;
2236 } ChunkR3Map;
2237
2238 /**
2239 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2240 */
2241 PGMPAGER3MAPTLB PhysTlbHC;
2242
2243 /** @name The zero page.
2244 * @{ */
2245 /** The host physical address of the zero page. */
2246 RTHCPHYS HCPhysZeroPg;
2247 /** The ring-3 mapping of the zero page. */
2248 RTR3PTR pvZeroPgR3;
2249 /** The ring-0 mapping of the zero page. */
2250 RTR0PTR pvZeroPgR0;
2251 /** The GC mapping of the zero page. */
2252 RTGCPTR pvZeroPgGC;
2253#if GC_ARCH_BITS != 32
2254 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2255#endif
2256 /** @}*/
2257
2258 /** The number of handy pages. */
2259 uint32_t cHandyPages;
2260 /**
2261 * Array of handy pages.
2262 *
2263 * This array is used in a two way communication between pgmPhysAllocPage
2264 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2265 * an intermediary.
2266 *
2267 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2268 * (The current size of 32 pages, means 128 KB of handy memory.)
2269 */
2270 GMMPAGEDESC aHandyPages[32];
2271
2272 /** @name Release Statistics
2273 * @{ */
2274 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2275 uint32_t cPrivatePages; /**< The number of private pages. */
2276 uint32_t cSharedPages; /**< The number of shared pages. */
2277 uint32_t cZeroPages; /**< The number of zero backed pages. */
2278 /** The number of times the guest has switched mode since last reset or statistics reset. */
2279 STAMCOUNTER cGuestModeChanges;
2280 /** @} */
2281
2282#ifdef VBOX_WITH_STATISTICS
2283 /** GC: Which statistic this \#PF should be attributed to. */
2284 GCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
2285 RTGCPTR padding0;
2286 /** HC: Which statistic this \#PF should be attributed to. */
2287 R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
2288 RTHCPTR padding1;
2289 STAMPROFILE StatGCTrap0e; /**< GC: PGMGCTrap0eHandler() profiling. */
2290 STAMPROFILE StatTrap0eCSAM; /**< Profiling of the Trap0eHandler body when the cause is CSAM. */
2291 STAMPROFILE StatTrap0eDirtyAndAccessedBits; /**< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2292 STAMPROFILE StatTrap0eGuestTrap; /**< Profiling of the Trap0eHandler body when the cause is a guest trap. */
2293 STAMPROFILE StatTrap0eHndPhys; /**< Profiling of the Trap0eHandler body when the cause is a physical handler. */
2294 STAMPROFILE StatTrap0eHndVirt; /**< Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2295 STAMPROFILE StatTrap0eHndUnhandled; /**< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2296 STAMPROFILE StatTrap0eMisc; /**< Profiling of the Trap0eHandler body when the cause is not known. */
2297 STAMPROFILE StatTrap0eOutOfSync; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2298 STAMPROFILE StatTrap0eOutOfSyncHndPhys; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2299 STAMPROFILE StatTrap0eOutOfSyncHndVirt; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2300 STAMPROFILE StatTrap0eOutOfSyncObsHnd; /**< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2301 STAMPROFILE StatTrap0eSyncPT; /**< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2302
2303 STAMCOUNTER StatTrap0eMapHandler; /**< Number of traps due to access handlers in mappings. */
2304 STAMCOUNTER StatGCTrap0eConflicts; /**< GC: The number of times \#PF was caused by an undetected conflict. */
2305
2306 STAMCOUNTER StatGCTrap0eUSNotPresentRead;
2307 STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
2308 STAMCOUNTER StatGCTrap0eUSWrite;
2309 STAMCOUNTER StatGCTrap0eUSReserved;
2310 STAMCOUNTER StatGCTrap0eUSNXE;
2311 STAMCOUNTER StatGCTrap0eUSRead;
2312
2313 STAMCOUNTER StatGCTrap0eSVNotPresentRead;
2314 STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
2315 STAMCOUNTER StatGCTrap0eSVWrite;
2316 STAMCOUNTER StatGCTrap0eSVReserved;
2317 STAMCOUNTER StatGCTrap0eSNXE;
2318
2319 STAMCOUNTER StatTrap0eWPEmulGC;
2320 STAMCOUNTER StatTrap0eWPEmulR3;
2321
2322 STAMCOUNTER StatGCTrap0eUnhandled;
2323 STAMCOUNTER StatGCTrap0eMap;
2324
2325 /** GC: PGMSyncPT() profiling. */
2326 STAMPROFILE StatGCSyncPT;
2327 /** GC: The number of times PGMSyncPT() needed to allocate page tables. */
2328 STAMCOUNTER StatGCSyncPTAlloc;
2329 /** GC: The number of times PGMSyncPT() detected conflicts. */
2330 STAMCOUNTER StatGCSyncPTConflict;
2331 /** GC: The number of times PGMSyncPT() failed. */
2332 STAMCOUNTER StatGCSyncPTFailed;
2333 /** GC: PGMGCInvalidatePage() profiling. */
2334 STAMPROFILE StatGCInvalidatePage;
2335 /** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
2336 STAMCOUNTER StatGCInvalidatePage4KBPages;
2337 /** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
2338 STAMCOUNTER StatGCInvalidatePage4MBPages;
2339 /** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
2340 STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
2341 /** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
2342 STAMCOUNTER StatGCInvalidatePagePDNAs;
2343 /** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
2344 STAMCOUNTER StatGCInvalidatePagePDNPs;
2345 /** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
2346 STAMCOUNTER StatGCInvalidatePagePDMappings;
2347 /** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2348 STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
2349 /** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2350 STAMCOUNTER StatGCInvalidatePageSkipped;
2351 /** GC: The number of times user page is out of sync was detected in GC. */
2352 STAMCOUNTER StatGCPageOutOfSyncUser;
2353 /** GC: The number of times supervisor page is out of sync was detected in GC. */
2354 STAMCOUNTER StatGCPageOutOfSyncSupervisor;
2355 /** GC: The number of dynamic page mapping cache hits */
2356 STAMCOUNTER StatDynMapCacheMisses;
2357 /** GC: The number of dynamic page mapping cache misses */
2358 STAMCOUNTER StatDynMapCacheHits;
2359 /** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
2360 STAMCOUNTER StatGCGuestCR3WriteHandled;
2361 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
2362 STAMCOUNTER StatGCGuestCR3WriteUnhandled;
2363 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
2364 STAMCOUNTER StatGCGuestCR3WriteConflict;
2365 /** GC: Number of out-of-sync handled pages. */
2366 STAMCOUNTER StatHandlersOutOfSync;
2367 /** GC: Number of traps due to physical access handlers. */
2368 STAMCOUNTER StatHandlersPhysical;
2369 /** GC: Number of traps due to virtual access handlers. */
2370 STAMCOUNTER StatHandlersVirtual;
2371 /** GC: Number of traps due to virtual access handlers found by physical address. */
2372 STAMCOUNTER StatHandlersVirtualByPhys;
2373 /** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2374 STAMCOUNTER StatHandlersVirtualUnmarked;
2375 /** GC: Number of traps due to access outside range of monitored page(s). */
2376 STAMCOUNTER StatHandlersUnhandled;
2377 /** GC: Number of traps due to access to invalid physical memory. */
2378 STAMCOUNTER StatHandlersInvalid;
2379
2380 /** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
2381 STAMCOUNTER StatGCGuestROMWriteHandled;
2382 /** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
2383 STAMCOUNTER StatGCGuestROMWriteUnhandled;
2384
2385 /** HC: PGMR3InvalidatePage() profiling. */
2386 STAMPROFILE StatHCInvalidatePage;
2387 /** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
2388 STAMCOUNTER StatHCInvalidatePage4KBPages;
2389 /** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
2390 STAMCOUNTER StatHCInvalidatePage4MBPages;
2391 /** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
2392 STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
2393 /** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
2394 STAMCOUNTER StatHCInvalidatePagePDNAs;
2395 /** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
2396 STAMCOUNTER StatHCInvalidatePagePDNPs;
2397 /** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
2398 STAMCOUNTER StatHCInvalidatePagePDMappings;
2399 /** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2400 STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
2401 /** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2402 STAMCOUNTER StatHCInvalidatePageSkipped;
2403 /** HC: PGMR3SyncPT() profiling. */
2404 STAMPROFILE StatHCSyncPT;
2405 /** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2406 STAMPROFILE StatHCResolveConflict;
2407 /** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2408 STAMCOUNTER StatHCDetectedConflicts;
2409 /** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2410 STAMCOUNTER StatHCGuestPDWrite;
2411 /** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2412 STAMCOUNTER StatHCGuestPDWriteConflict;
2413
2414 /** HC: The number of pages marked not present for accessed bit emulation. */
2415 STAMCOUNTER StatHCAccessedPage;
2416 /** HC: The number of pages marked read-only for dirty bit tracking. */
2417 STAMCOUNTER StatHCDirtyPage;
2418 /** HC: The number of pages marked read-only for dirty bit tracking. */
2419 STAMCOUNTER StatHCDirtyPageBig;
2420 /** HC: The number of traps generated for dirty bit tracking. */
2421 STAMCOUNTER StatHCDirtyPageTrap;
2422 /** HC: The number of pages already dirty or readonly. */
2423 STAMCOUNTER StatHCDirtyPageSkipped;
2424
2425 /** GC: The number of pages marked not present for accessed bit emulation. */
2426 STAMCOUNTER StatGCAccessedPage;
2427 /** GC: The number of pages marked read-only for dirty bit tracking. */
2428 STAMCOUNTER StatGCDirtyPage;
2429 /** GC: The number of pages marked read-only for dirty bit tracking. */
2430 STAMCOUNTER StatGCDirtyPageBig;
2431 /** GC: The number of traps generated for dirty bit tracking. */
2432 STAMCOUNTER StatGCDirtyPageTrap;
2433 /** GC: The number of pages already dirty or readonly. */
2434 STAMCOUNTER StatGCDirtyPageSkipped;
2435 /** GC: The number of pages marked dirty because of write accesses. */
2436 STAMCOUNTER StatGCDirtiedPage;
2437 /** GC: The number of pages already marked dirty because of write accesses. */
2438 STAMCOUNTER StatGCPageAlreadyDirty;
2439 /** GC: The number of real pages faults during dirty bit tracking. */
2440 STAMCOUNTER StatGCDirtyTrackRealPF;
2441
2442 /** GC: Profiling of the PGMTrackDirtyBit() body */
2443 STAMPROFILE StatGCDirtyBitTracking;
2444 /** HC: Profiling of the PGMTrackDirtyBit() body */
2445 STAMPROFILE StatHCDirtyBitTracking;
2446
2447 /** GC: Profiling of the PGMGstModifyPage() body */
2448 STAMPROFILE StatGCGstModifyPage;
2449 /** HC: Profiling of the PGMGstModifyPage() body */
2450 STAMPROFILE StatHCGstModifyPage;
2451
2452 /** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2453 STAMCOUNTER StatGCSyncPagePDNAs;
2454 /** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2455 STAMCOUNTER StatGCSyncPagePDOutOfSync;
2456 /** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2457 STAMCOUNTER StatHCSyncPagePDNAs;
2458 /** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2459 STAMCOUNTER StatHCSyncPagePDOutOfSync;
2460
2461 STAMCOUNTER StatSynPT4kGC;
2462 STAMCOUNTER StatSynPT4kHC;
2463 STAMCOUNTER StatSynPT4MGC;
2464 STAMCOUNTER StatSynPT4MHC;
2465
2466 /** Profiling of the PGMFlushTLB() body. */
2467 STAMPROFILE StatFlushTLB;
2468 /** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2469 STAMCOUNTER StatFlushTLBNewCR3;
2470 /** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2471 STAMCOUNTER StatFlushTLBNewCR3Global;
2472 /** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2473 STAMCOUNTER StatFlushTLBSameCR3;
2474 /** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2475 STAMCOUNTER StatFlushTLBSameCR3Global;
2476
2477 STAMPROFILE StatGCSyncCR3; /**< GC: PGMSyncCR3() profiling. */
2478 STAMPROFILE StatGCSyncCR3Handlers; /**< GC: Profiling of the PGMSyncCR3() update handler section. */
2479 STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /**< GC: Profiling of the virtual handler resets. */
2480 STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /**< GC: Profiling of the virtual handler updates. */
2481 STAMCOUNTER StatGCSyncCR3Global; /**< GC: The number of global CR3 syncs. */
2482 STAMCOUNTER StatGCSyncCR3NotGlobal; /**< GC: The number of non-global CR3 syncs. */
2483 STAMCOUNTER StatGCSyncCR3DstFreed; /**< GC: The number of times we've had to free a shadow entry. */
2484 STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /**< GC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2485 STAMCOUNTER StatGCSyncCR3DstNotPresent; /**< GC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2486 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /**< GC: The number of times a global page directory wasn't flushed. */
2487 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /**< GC: The number of times a page table with only global entries wasn't flushed. */
2488 STAMCOUNTER StatGCSyncCR3DstCacheHit; /**< GC: The number of times we got some kind of cache hit on a page table. */
2489
2490 STAMPROFILE StatHCSyncCR3; /**< HC: PGMSyncCR3() profiling. */
2491 STAMPROFILE StatHCSyncCR3Handlers; /**< HC: Profiling of the PGMSyncCR3() update handler section. */
2492 STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /**< HC: Profiling of the virtual handler resets. */
2493 STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /**< HC: Profiling of the virtual handler updates. */
2494 STAMCOUNTER StatHCSyncCR3Global; /**< HC: The number of global CR3 syncs. */
2495 STAMCOUNTER StatHCSyncCR3NotGlobal; /**< HC: The number of non-global CR3 syncs. */
2496 STAMCOUNTER StatHCSyncCR3DstFreed; /**< HC: The number of times we've had to free a shadow entry. */
2497 STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /**< HC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2498 STAMCOUNTER StatHCSyncCR3DstNotPresent; /**< HC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2499 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /**< HC: The number of times a global page directory wasn't flushed. */
2500 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /**< HC: The number of times a page table with only global entries wasn't flushed. */
2501 STAMCOUNTER StatHCSyncCR3DstCacheHit; /**< HC: The number of times we got some kind of cache hit on a page table. */
2502
2503 /** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2504 STAMPROFILE StatVirtHandleSearchByPhysGC;
2505 /** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2506 STAMPROFILE StatVirtHandleSearchByPhysHC;
2507 /** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2508 STAMCOUNTER StatHandlePhysicalReset;
2509
2510 STAMPROFILE StatCheckPageFault;
2511 STAMPROFILE StatLazySyncPT;
2512 STAMPROFILE StatMapping;
2513 STAMPROFILE StatOutOfSync;
2514 STAMPROFILE StatHandlers;
2515 STAMPROFILE StatEIPHandlers;
2516 STAMPROFILE StatHCPrefetch;
2517
2518# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2519 /** The number of first time shadowings. */
2520 STAMCOUNTER StatTrackVirgin;
2521 /** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2522 STAMCOUNTER StatTrackAliased;
2523 /** The number of times we're tracking using cRef2. */
2524 STAMCOUNTER StatTrackAliasedMany;
2525 /** The number of times we're hitting pages which has overflowed cRef2. */
2526 STAMCOUNTER StatTrackAliasedLots;
2527 /** The number of times the extent list grows to long. */
2528 STAMCOUNTER StatTrackOverflows;
2529 /** Profiling of SyncPageWorkerTrackDeref (expensive). */
2530 STAMPROFILE StatTrackDeref;
2531# endif
2532
2533 /** Ring-3/0 page mapper TLB hits. */
2534 STAMCOUNTER StatPageHCMapTlbHits;
2535 /** Ring-3/0 page mapper TLB misses. */
2536 STAMCOUNTER StatPageHCMapTlbMisses;
2537 /** Ring-3/0 chunk mapper TLB hits. */
2538 STAMCOUNTER StatChunkR3MapTlbHits;
2539 /** Ring-3/0 chunk mapper TLB misses. */
2540 STAMCOUNTER StatChunkR3MapTlbMisses;
2541 /** Times a shared page has been replaced by a private one. */
2542 STAMCOUNTER StatPageReplaceShared;
2543 /** Times the zero page has been replaced by a private one. */
2544 STAMCOUNTER StatPageReplaceZero;
2545 /** The number of times we've executed GMMR3AllocateHandyPages. */
2546 STAMCOUNTER StatPageHandyAllocs;
2547
2548 /** Allocated mbs of guest ram */
2549 STAMCOUNTER StatDynRamTotal;
2550 /** Nr of pgmr3PhysGrowRange calls. */
2551 STAMCOUNTER StatDynRamGrow;
2552
2553 STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2554 STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2555 STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2556#endif
2557} PGM, *PPGM;
2558
2559
2560/** @name PGM::fSyncFlags Flags
2561 * @{
2562 */
2563/** Updates the virtual access handler state bit in PGMPAGE. */
2564#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2565/** Always sync CR3. */
2566#define PGM_SYNC_ALWAYS RT_BIT(1)
2567/** Check monitoring on next CR3 (re)load and invalidate page. */
2568#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2569/** Clear the page pool (a light weight flush). */
2570#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2571/** @} */
2572
2573
2574__BEGIN_DECLS
2575
2576int pgmLock(PVM pVM);
2577void pgmUnlock(PVM pVM);
2578
2579PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2580PGMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2581
2582int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2583int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2584PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2585void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2586DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2587
2588void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2589int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2590DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2591#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2592void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2593#else
2594# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2595#endif
2596DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2597
2598
2599void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2600int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2601int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2602int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2603#ifdef IN_RING3
2604int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2605int pgmR3PhysRamReset(PVM pVM);
2606int pgmR3PhysRomReset(PVM pVM);
2607#ifndef VBOX_WITH_NEW_PHYS_CODE
2608int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2609#endif
2610
2611int pgmR3PoolInit(PVM pVM);
2612void pgmR3PoolRelocate(PVM pVM);
2613void pgmR3PoolReset(PVM pVM);
2614
2615#endif /* IN_RING3 */
2616#ifdef IN_GC
2617void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2618#endif
2619int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage);
2620PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2621void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint16_t iUserTable);
2622void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable);
2623int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2624void pgmPoolFlushAll(PVM pVM);
2625void pgmPoolClearAll(PVM pVM);
2626void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2627void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2628int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2629PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2630void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2631void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2632uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2633void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2634#ifdef PGMPOOL_WITH_MONITORING
2635# ifdef IN_RING3
2636void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2637# else
2638void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2639# endif
2640int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2641void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2642void pgmPoolMonitorModifiedClearAll(PVM pVM);
2643int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2644int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2645#endif
2646
2647__END_DECLS
2648
2649
2650/**
2651 * Gets the PGMRAMRANGE structure for a guest page.
2652 *
2653 * @returns Pointer to the RAM range on success.
2654 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2655 *
2656 * @param pPGM PGM handle.
2657 * @param GCPhys The GC physical address.
2658 */
2659DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2660{
2661 /*
2662 * Optimize for the first range.
2663 */
2664 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2665 RTGCPHYS off = GCPhys - pRam->GCPhys;
2666 if (RT_UNLIKELY(off >= pRam->cb))
2667 {
2668 do
2669 {
2670 pRam = CTXALLSUFF(pRam->pNext);
2671 if (RT_UNLIKELY(!pRam))
2672 break;
2673 off = GCPhys - pRam->GCPhys;
2674 } while (off >= pRam->cb);
2675 }
2676 return pRam;
2677}
2678
2679
2680/**
2681 * Gets the PGMPAGE structure for a guest page.
2682 *
2683 * @returns Pointer to the page on success.
2684 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2685 *
2686 * @param pPGM PGM handle.
2687 * @param GCPhys The GC physical address.
2688 */
2689DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2690{
2691 /*
2692 * Optimize for the first range.
2693 */
2694 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2695 RTGCPHYS off = GCPhys - pRam->GCPhys;
2696 if (RT_UNLIKELY(off >= pRam->cb))
2697 {
2698 do
2699 {
2700 pRam = CTXALLSUFF(pRam->pNext);
2701 if (RT_UNLIKELY(!pRam))
2702 return NULL;
2703 off = GCPhys - pRam->GCPhys;
2704 } while (off >= pRam->cb);
2705 }
2706 return &pRam->aPages[off >> PAGE_SHIFT];
2707}
2708
2709
2710/**
2711 * Gets the PGMPAGE structure for a guest page.
2712 *
2713 * Old Phys code: Will make sure the page is present.
2714 *
2715 * @returns VBox status code.
2716 * @retval VINF_SUCCESS and a valid *ppPage on success.
2717 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2718 *
2719 * @param pPGM PGM handle.
2720 * @param GCPhys The GC physical address.
2721 * @param ppPage Where to store the page poitner on success.
2722 */
2723DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2724{
2725 /*
2726 * Optimize for the first range.
2727 */
2728 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2729 RTGCPHYS off = GCPhys - pRam->GCPhys;
2730 if (RT_UNLIKELY(off >= pRam->cb))
2731 {
2732 do
2733 {
2734 pRam = CTXALLSUFF(pRam->pNext);
2735 if (RT_UNLIKELY(!pRam))
2736 {
2737 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2738 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2739 }
2740 off = GCPhys - pRam->GCPhys;
2741 } while (off >= pRam->cb);
2742 }
2743 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2744#ifndef VBOX_WITH_NEW_PHYS_CODE
2745
2746 /*
2747 * Make sure it's present.
2748 */
2749 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2750 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2751 {
2752#ifdef IN_RING3
2753 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2754#else
2755 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2756#endif
2757 if (VBOX_FAILURE(rc))
2758 {
2759 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2760 return rc;
2761 }
2762 Assert(rc == VINF_SUCCESS);
2763 }
2764#endif
2765 return VINF_SUCCESS;
2766}
2767
2768
2769
2770
2771/**
2772 * Gets the PGMPAGE structure for a guest page.
2773 *
2774 * Old Phys code: Will make sure the page is present.
2775 *
2776 * @returns VBox status code.
2777 * @retval VINF_SUCCESS and a valid *ppPage on success.
2778 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2779 *
2780 * @param pPGM PGM handle.
2781 * @param GCPhys The GC physical address.
2782 * @param ppPage Where to store the page poitner on success.
2783 * @param ppRamHint Where to read and store the ram list hint.
2784 * The caller initializes this to NULL before the call.
2785 */
2786DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2787{
2788 RTGCPHYS off;
2789 PPGMRAMRANGE pRam = *ppRamHint;
2790 if ( !pRam
2791 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2792 {
2793 pRam = CTXALLSUFF(pPGM->pRamRanges);
2794 off = GCPhys - pRam->GCPhys;
2795 if (RT_UNLIKELY(off >= pRam->cb))
2796 {
2797 do
2798 {
2799 pRam = CTXALLSUFF(pRam->pNext);
2800 if (RT_UNLIKELY(!pRam))
2801 {
2802 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2803 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2804 }
2805 off = GCPhys - pRam->GCPhys;
2806 } while (off >= pRam->cb);
2807 }
2808 *ppRamHint = pRam;
2809 }
2810 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2811#ifndef VBOX_WITH_NEW_PHYS_CODE
2812
2813 /*
2814 * Make sure it's present.
2815 */
2816 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2817 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2818 {
2819#ifdef IN_RING3
2820 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2821#else
2822 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2823#endif
2824 if (VBOX_FAILURE(rc))
2825 {
2826 *ppPage = NULL; /* Shut up annoying smart ass. */
2827 return rc;
2828 }
2829 Assert(rc == VINF_SUCCESS);
2830 }
2831#endif
2832 return VINF_SUCCESS;
2833}
2834
2835
2836/**
2837 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2838 *
2839 * @returns Pointer to the page on success.
2840 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2841 *
2842 * @param pPGM PGM handle.
2843 * @param GCPhys The GC physical address.
2844 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
2845 */
2846DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2847{
2848 /*
2849 * Optimize for the first range.
2850 */
2851 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2852 RTGCPHYS off = GCPhys - pRam->GCPhys;
2853 if (RT_UNLIKELY(off >= pRam->cb))
2854 {
2855 do
2856 {
2857 pRam = CTXALLSUFF(pRam->pNext);
2858 if (RT_UNLIKELY(!pRam))
2859 return NULL;
2860 off = GCPhys - pRam->GCPhys;
2861 } while (off >= pRam->cb);
2862 }
2863 *ppRam = pRam;
2864 return &pRam->aPages[off >> PAGE_SHIFT];
2865}
2866
2867
2868
2869
2870/**
2871 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2872 *
2873 * @returns Pointer to the page on success.
2874 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2875 *
2876 * @param pPGM PGM handle.
2877 * @param GCPhys The GC physical address.
2878 * @param ppPage Where to store the pointer to the PGMPAGE structure.
2879 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2880 */
2881DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2882{
2883 /*
2884 * Optimize for the first range.
2885 */
2886 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2887 RTGCPHYS off = GCPhys - pRam->GCPhys;
2888 if (RT_UNLIKELY(off >= pRam->cb))
2889 {
2890 do
2891 {
2892 pRam = CTXALLSUFF(pRam->pNext);
2893 if (RT_UNLIKELY(!pRam))
2894 {
2895 *ppRam = NULL; /* Shut up silly GCC warnings. */
2896 *ppPage = NULL; /* ditto */
2897 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2898 }
2899 off = GCPhys - pRam->GCPhys;
2900 } while (off >= pRam->cb);
2901 }
2902 *ppRam = pRam;
2903 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2904#ifndef VBOX_WITH_NEW_PHYS_CODE
2905
2906 /*
2907 * Make sure it's present.
2908 */
2909 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2910 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2911 {
2912#ifdef IN_RING3
2913 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2914#else
2915 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2916#endif
2917 if (VBOX_FAILURE(rc))
2918 {
2919 *ppPage = NULL; /* Shut up silly GCC warnings. */
2920 *ppPage = NULL; /* ditto */
2921 return rc;
2922 }
2923 Assert(rc == VINF_SUCCESS);
2924
2925 }
2926#endif
2927 return VINF_SUCCESS;
2928}
2929
2930
2931/**
2932 * Convert GC Phys to HC Phys.
2933 *
2934 * @returns VBox status.
2935 * @param pPGM PGM handle.
2936 * @param GCPhys The GC physical address.
2937 * @param pHCPhys Where to store the corresponding HC physical address.
2938 *
2939 * @deprecated Doesn't deal with zero, shared or write monitored pages.
2940 * Avoid when writing new code!
2941 */
2942DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2943{
2944 PPGMPAGE pPage;
2945 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2946 if (VBOX_FAILURE(rc))
2947 return rc;
2948 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
2949 return VINF_SUCCESS;
2950}
2951
2952
2953#ifndef IN_GC
2954/**
2955 * Queries the Physical TLB entry for a physical guest page,
2956 * attemting to load the TLB entry if necessary.
2957 *
2958 * @returns VBox status code.
2959 * @retval VINF_SUCCESS on success
2960 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2961 * @param pPGM The PGM instance handle.
2962 * @param GCPhys The address of the guest page.
2963 * @param ppTlbe Where to store the pointer to the TLB entry.
2964 */
2965
2966DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
2967{
2968 int rc;
2969 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
2970 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
2971 {
2972 STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
2973 rc = VINF_SUCCESS;
2974 }
2975 else
2976 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
2977 *ppTlbe = pTlbe;
2978 return rc;
2979}
2980#endif /* !IN_GC */
2981
2982
2983#ifndef VBOX_WITH_NEW_PHYS_CODE
2984/**
2985 * Convert GC Phys to HC Virt.
2986 *
2987 * @returns VBox status.
2988 * @param pPGM PGM handle.
2989 * @param GCPhys The GC physical address.
2990 * @param pHCPtr Where to store the corresponding HC virtual address.
2991 *
2992 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
2993 */
2994DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
2995{
2996 PPGMRAMRANGE pRam;
2997 PPGMPAGE pPage;
2998 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
2999 if (VBOX_FAILURE(rc))
3000 {
3001 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3002 return rc;
3003 }
3004 RTGCPHYS off = GCPhys - pRam->GCPhys;
3005
3006 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3007 {
3008 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3009 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3010 return VINF_SUCCESS;
3011 }
3012 if (pRam->pvHC)
3013 {
3014 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3015 return VINF_SUCCESS;
3016 }
3017 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3018 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3019}
3020#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3021
3022
3023/**
3024 * Convert GC Phys to HC Virt.
3025 *
3026 * @returns VBox status.
3027 * @param PVM VM handle.
3028 * @param pRam Ram range
3029 * @param GCPhys The GC physical address.
3030 * @param pHCPtr Where to store the corresponding HC virtual address.
3031 *
3032 * @deprecated This will be eliminated. Don't use it.
3033 */
3034DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3035{
3036 RTGCPHYS off = GCPhys - pRam->GCPhys;
3037 Assert(off < pRam->cb);
3038
3039 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3040 {
3041 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3042 /* Physical chunk in dynamically allocated range not present? */
3043 if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
3044 {
3045#ifdef IN_RING3
3046 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3047#else
3048 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3049#endif
3050 if (rc != VINF_SUCCESS)
3051 {
3052 *pHCPtr = 0; /* GCC crap */
3053 return rc;
3054 }
3055 }
3056 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3057 return VINF_SUCCESS;
3058 }
3059 if (pRam->pvHC)
3060 {
3061 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3062 return VINF_SUCCESS;
3063 }
3064 *pHCPtr = 0; /* GCC crap */
3065 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3066}
3067
3068
3069/**
3070 * Convert GC Phys to HC Virt and HC Phys.
3071 *
3072 * @returns VBox status.
3073 * @param pPGM PGM handle.
3074 * @param GCPhys The GC physical address.
3075 * @param pHCPtr Where to store the corresponding HC virtual address.
3076 * @param pHCPhys Where to store the HC Physical address and its flags.
3077 *
3078 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3079 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3080 */
3081DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3082{
3083 PPGMRAMRANGE pRam;
3084 PPGMPAGE pPage;
3085 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3086 if (VBOX_FAILURE(rc))
3087 {
3088 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3089 *pHCPhys = 0; /* ditto */
3090 return rc;
3091 }
3092 RTGCPHYS off = GCPhys - pRam->GCPhys;
3093
3094 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3095 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3096 {
3097 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3098 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3099 return VINF_SUCCESS;
3100 }
3101 if (pRam->pvHC)
3102 {
3103 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3104 return VINF_SUCCESS;
3105 }
3106 *pHCPtr = 0;
3107 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3108}
3109
3110
3111/**
3112 * Clears flags associated with a RAM address.
3113 *
3114 * @returns VBox status code.
3115 * @param pPGM PGM handle.
3116 * @param GCPhys Guest context physical address.
3117 * @param fFlags fFlags to clear. (Bits 0-11.)
3118 */
3119DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3120{
3121 PPGMPAGE pPage;
3122 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3123 if (VBOX_FAILURE(rc))
3124 return rc;
3125
3126 fFlags &= ~X86_PTE_PAE_PG_MASK;
3127 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3128 return VINF_SUCCESS;
3129}
3130
3131
3132/**
3133 * Clears flags associated with a RAM address.
3134 *
3135 * @returns VBox status code.
3136 * @param pPGM PGM handle.
3137 * @param GCPhys Guest context physical address.
3138 * @param fFlags fFlags to clear. (Bits 0-11.)
3139 * @param ppRamHint Where to read and store the ram list hint.
3140 * The caller initializes this to NULL before the call.
3141 */
3142DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3143{
3144 PPGMPAGE pPage;
3145 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3146 if (VBOX_FAILURE(rc))
3147 return rc;
3148
3149 fFlags &= ~X86_PTE_PAE_PG_MASK;
3150 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3151 return VINF_SUCCESS;
3152}
3153
3154/**
3155 * Sets (bitwise OR) flags associated with a RAM address.
3156 *
3157 * @returns VBox status code.
3158 * @param pPGM PGM handle.
3159 * @param GCPhys Guest context physical address.
3160 * @param fFlags fFlags to set clear. (Bits 0-11.)
3161 */
3162DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3163{
3164 PPGMPAGE pPage;
3165 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3166 if (VBOX_FAILURE(rc))
3167 return rc;
3168
3169 fFlags &= ~X86_PTE_PAE_PG_MASK;
3170 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3171 return VINF_SUCCESS;
3172}
3173
3174
3175/**
3176 * Sets (bitwise OR) flags associated with a RAM address.
3177 *
3178 * @returns VBox status code.
3179 * @param pPGM PGM handle.
3180 * @param GCPhys Guest context physical address.
3181 * @param fFlags fFlags to set clear. (Bits 0-11.)
3182 * @param ppRamHint Where to read and store the ram list hint.
3183 * The caller initializes this to NULL before the call.
3184 */
3185DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3186{
3187 PPGMPAGE pPage;
3188 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3189 if (VBOX_FAILURE(rc))
3190 return rc;
3191
3192 fFlags &= ~X86_PTE_PAE_PG_MASK;
3193 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3194 return VINF_SUCCESS;
3195}
3196
3197
3198/**
3199 * Gets the page directory for the specified address.
3200 *
3201 * @returns Pointer to the page directory in question.
3202 * @returns NULL if the page directory is not present or on an invalid page.
3203 * @param pPGM Pointer to the PGM instance data.
3204 * @param GCPtr The address.
3205 */
3206DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3207{
3208 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3209 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3210 {
3211 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3212 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3213
3214 /* cache is out-of-sync. */
3215 PX86PDPAE pPD;
3216 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3217 if (VBOX_SUCCESS(rc))
3218 return pPD;
3219 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3220 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3221 }
3222 return NULL;
3223}
3224
3225
3226/**
3227 * Gets the page directory entry for the specified address.
3228 *
3229 * @returns Pointer to the page directory entry in question.
3230 * @returns NULL if the page directory is not present or on an invalid page.
3231 * @param pPGM Pointer to the PGM instance data.
3232 * @param GCPtr The address.
3233 */
3234DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3235{
3236 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3237 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3238 {
3239 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3240 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3241 return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3242
3243 /* The cache is out-of-sync. */
3244 PX86PDPAE pPD;
3245 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3246 if (VBOX_SUCCESS(rc))
3247 return &pPD->a[iPD];
3248 AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3249 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3250 }
3251 return NULL;
3252}
3253
3254
3255/**
3256 * Gets the page directory entry for the specified address.
3257 *
3258 * @returns The page directory entry in question.
3259 * @returns A non-present entry if the page directory is not present or on an invalid page.
3260 * @param pPGM Pointer to the PGM instance data.
3261 * @param GCPtr The address.
3262 */
3263DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3264{
3265 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3266 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3267 {
3268 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3269 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3270 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3271
3272 /* cache is out-of-sync. */
3273 PX86PDPAE pPD;
3274 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3275 if (VBOX_SUCCESS(rc))
3276 return pPD->a[iPD].u;
3277 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3278 }
3279 return 0ULL;
3280}
3281
3282
3283/**
3284 * Gets the page directory pointer table entry for the specified address
3285 * and returns the index into the page directory
3286 *
3287 * @returns Pointer to the page directory in question.
3288 * @returns NULL if the page directory is not present or on an invalid page.
3289 * @param pPGM Pointer to the PGM instance data.
3290 * @param GCPtr The address.
3291 * @param piPD Receives the index into the returned page directory
3292 */
3293DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3294{
3295 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3296 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3297 {
3298 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3299 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3300 {
3301 *piPD = iPD;
3302 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3303 }
3304
3305 /* cache is out-of-sync. */
3306 PX86PDPAE pPD;
3307 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3308 if (VBOX_SUCCESS(rc))
3309 {
3310 *piPD = iPD;
3311 return pPD;
3312 }
3313 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3314 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3315 }
3316 return NULL;
3317}
3318
3319#ifndef IN_GC
3320/**
3321 * Gets the page directory pointer entry for the specified address.
3322 *
3323 * @returns Pointer to the page directory pointer entry in question.
3324 * @returns NULL if the page directory is not present or on an invalid page.
3325 * @param pPGM Pointer to the PGM instance data.
3326 * @param GCPtr The address.
3327 * @param ppPml4e Page Map Level-4 Entry (out)
3328 */
3329DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e)
3330{
3331 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3332
3333 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3334 if ((*ppPml4e)->n.u1Present)
3335 {
3336 PX86PDPT pPdpt;
3337 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdpt);
3338 if (VBOX_FAILURE(rc))
3339 {
3340 AssertFailed();
3341 return NULL;
3342 }
3343 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3344 return &pPdpt->a[iPdPt];
3345 }
3346 return NULL;
3347}
3348
3349/**
3350 * Gets the page directory entry for the specified address.
3351 *
3352 * @returns The page directory entry in question.
3353 * @returns A non-present entry if the page directory is not present or on an invalid page.
3354 * @param pPGM Pointer to the PGM instance data.
3355 * @param GCPtr The address.
3356 * @param ppPml4e Page Map Level-4 Entry (out)
3357 * @param pPdpe Page directory pointer table entry (out)
3358 */
3359DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3360{
3361 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3362
3363 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3364 if ((*ppPml4e)->n.u1Present)
3365 {
3366 PX86PDPT pPdptTemp;
3367 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3368 if (VBOX_FAILURE(rc))
3369 {
3370 AssertFailed();
3371 return 0ULL;
3372 }
3373
3374 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3375 *pPdpe = pPdptTemp->a[iPdPt];
3376 if (pPdpe->n.u1Present)
3377 {
3378 PX86PDPAE pPD;
3379
3380 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3381 if (VBOX_FAILURE(rc))
3382 {
3383 AssertFailed();
3384 return 0ULL;
3385 }
3386 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3387 return pPD->a[iPD].u;
3388 }
3389 }
3390 return 0ULL;
3391}
3392
3393/**
3394 * Gets the page directory entry for the specified address.
3395 *
3396 * @returns The page directory entry in question.
3397 * @returns A non-present entry if the page directory is not present or on an invalid page.
3398 * @param pPGM Pointer to the PGM instance data.
3399 * @param GCPtr The address.
3400 */
3401DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3402{
3403 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3404
3405 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3406 {
3407 PX86PDPT pPdptTemp;
3408 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3409 if (VBOX_FAILURE(rc))
3410 {
3411 AssertFailed();
3412 return 0ULL;
3413 }
3414
3415 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3416 if (pPdptTemp->a[iPdPt].n.u1Present)
3417 {
3418 PX86PDPAE pPD;
3419
3420 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3421 if (VBOX_FAILURE(rc))
3422 {
3423 AssertFailed();
3424 return 0ULL;
3425 }
3426 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3427 return pPD->a[iPD].u;
3428 }
3429 }
3430 return 0ULL;
3431}
3432
3433/**
3434 * Gets the page directory entry for the specified address.
3435 *
3436 * @returns Pointer to the page directory entry in question.
3437 * @returns NULL if the page directory is not present or on an invalid page.
3438 * @param pPGM Pointer to the PGM instance data.
3439 * @param GCPtr The address.
3440 */
3441DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3442{
3443 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3444
3445 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3446 {
3447 PX86PDPT pPdptTemp;
3448 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3449 if (VBOX_FAILURE(rc))
3450 {
3451 AssertFailed();
3452 return NULL;
3453 }
3454
3455 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3456 if (pPdptTemp->a[iPdPt].n.u1Present)
3457 {
3458 PX86PDPAE pPD;
3459
3460 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3461 if (VBOX_FAILURE(rc))
3462 {
3463 AssertFailed();
3464 return NULL;
3465 }
3466 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3467 return &pPD->a[iPD];
3468 }
3469 }
3470 return NULL;
3471}
3472
3473
3474/**
3475 * Gets the GUEST page directory pointer for the specified address.
3476 *
3477 * @returns The page directory in question.
3478 * @returns NULL if the page directory is not present or on an invalid page.
3479 * @param pPGM Pointer to the PGM instance data.
3480 * @param GCPtr The address.
3481 * @param ppPml4e Page Map Level-4 Entry (out)
3482 * @param pPdpe Page directory pointer table entry (out)
3483 * @param piPD Receives the index into the returned page directory
3484 */
3485DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
3486{
3487 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3488
3489 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3490 if ((*ppPml4e)->n.u1Present)
3491 {
3492 PX86PDPT pPdptTemp;
3493 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3494 if (VBOX_FAILURE(rc))
3495 {
3496 AssertFailed();
3497 return 0ULL;
3498 }
3499
3500 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3501 *pPdpe = pPdptTemp->a[iPdPt];
3502 if (pPdpe->n.u1Present)
3503 {
3504 PX86PDPAE pPD;
3505
3506 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3507 if (VBOX_FAILURE(rc))
3508 {
3509 AssertFailed();
3510 return 0ULL;
3511 }
3512 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3513 return pPD;
3514 }
3515 }
3516 return 0ULL;
3517}
3518#endif /* !IN_GC */
3519
3520/**
3521 * Checks if any of the specified page flags are set for the given page.
3522 *
3523 * @returns true if any of the flags are set.
3524 * @returns false if all the flags are clear.
3525 * @param pPGM PGM handle.
3526 * @param GCPhys The GC physical address.
3527 * @param fFlags The flags to check for.
3528 */
3529DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3530{
3531 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3532 return pPage
3533 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3534}
3535
3536
3537/**
3538 * Gets the page state for a physical handler.
3539 *
3540 * @returns The physical handler page state.
3541 * @param pCur The physical handler in question.
3542 */
3543DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3544{
3545 switch (pCur->enmType)
3546 {
3547 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3548 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3549
3550 case PGMPHYSHANDLERTYPE_MMIO:
3551 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3552 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3553
3554 default:
3555 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3556 }
3557}
3558
3559
3560/**
3561 * Gets the page state for a virtual handler.
3562 *
3563 * @returns The virtual handler page state.
3564 * @param pCur The virtual handler in question.
3565 * @remarks This should never be used on a hypervisor access handler.
3566 */
3567DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3568{
3569 switch (pCur->enmType)
3570 {
3571 case PGMVIRTHANDLERTYPE_WRITE:
3572 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3573 case PGMVIRTHANDLERTYPE_ALL:
3574 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3575 default:
3576 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3577 }
3578}
3579
3580
3581/**
3582 * Clears one physical page of a virtual handler
3583 *
3584 * @param pPGM Pointer to the PGM instance.
3585 * @param pCur Virtual handler structure
3586 * @param iPage Physical page index
3587 *
3588 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3589 * need to care about other handlers in the same page.
3590 */
3591DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3592{
3593 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3594
3595 /*
3596 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
3597 */
3598#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3599 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3600 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3601 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3602#endif
3603 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3604 {
3605 /* We're the head of the alias chain. */
3606 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3607#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3608 AssertReleaseMsg(pRemove != NULL,
3609 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3610 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3611 AssertReleaseMsg(pRemove == pPhys2Virt,
3612 ("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3613 " got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3614 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3615 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3616#endif
3617 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3618 {
3619 /* Insert the next list in the alias chain into the tree. */
3620 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3621#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3622 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3623 ("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3624 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3625#endif
3626 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
3627 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3628 AssertRelease(fRc);
3629 }
3630 }
3631 else
3632 {
3633 /* Locate the previous node in the alias chain. */
3634 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3635#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3636 AssertReleaseMsg(pPrev != pPhys2Virt,
3637 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3638 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3639#endif
3640 for (;;)
3641 {
3642 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3643 if (pNext == pPhys2Virt)
3644 {
3645 /* unlink. */
3646 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3647 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3648 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3649 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3650 else
3651 {
3652 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3653 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3654 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3655 }
3656 break;
3657 }
3658
3659 /* next */
3660 if (pNext == pPrev)
3661 {
3662#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3663 AssertReleaseMsg(pNext != pPrev,
3664 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3665 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3666#endif
3667 break;
3668 }
3669 pPrev = pNext;
3670 }
3671 }
3672 Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3673 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3674 pPhys2Virt->offNextAlias = 0;
3675 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3676
3677 /*
3678 * Clear the ram flags for this page.
3679 */
3680 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3681 AssertReturnVoid(pPage);
3682 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3683}
3684
3685
3686/**
3687 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3688 *
3689 * @returns Pointer to the shadow page structure.
3690 * @param pPool The pool.
3691 * @param HCPhys The HC physical address of the shadow page.
3692 */
3693DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3694{
3695 /*
3696 * Look up the page.
3697 */
3698 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3699 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3700 return pPage;
3701}
3702
3703
3704/**
3705 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3706 *
3707 * @returns Pointer to the shadow page structure.
3708 * @param pPool The pool.
3709 * @param idx The pool page index.
3710 */
3711DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3712{
3713 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3714 return &pPool->aPages[idx];
3715}
3716
3717
3718#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3719/**
3720 * Clear references to guest physical memory.
3721 *
3722 * @param pPool The pool.
3723 * @param pPoolPage The pool page.
3724 * @param pPhysPage The physical guest page tracking structure.
3725 */
3726DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3727{
3728 /*
3729 * Just deal with the simple case here.
3730 */
3731#ifdef LOG_ENABLED
3732 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3733#endif
3734 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3735 if (cRefs == 1)
3736 {
3737 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3738 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3739 }
3740 else
3741 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3742 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3743}
3744#endif
3745
3746
3747#ifdef PGMPOOL_WITH_CACHE
3748/**
3749 * Moves the page to the head of the age list.
3750 *
3751 * This is done when the cached page is used in one way or another.
3752 *
3753 * @param pPool The pool.
3754 * @param pPage The cached page.
3755 * @todo inline in PGMInternal.h!
3756 */
3757DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3758{
3759 /*
3760 * Move to the head of the age list.
3761 */
3762 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3763 {
3764 /* unlink */
3765 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3766 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3767 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3768 else
3769 pPool->iAgeTail = pPage->iAgePrev;
3770
3771 /* insert at head */
3772 pPage->iAgePrev = NIL_PGMPOOL_IDX;
3773 pPage->iAgeNext = pPool->iAgeHead;
3774 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3775 pPool->iAgeHead = pPage->idx;
3776 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3777 }
3778}
3779#endif /* PGMPOOL_WITH_CACHE */
3780
3781/**
3782 * Tells if mappings are to be put into the shadow page table or not
3783 *
3784 * @returns boolean result
3785 * @param pVM VM handle.
3786 */
3787
3788DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3789{
3790#ifdef IN_RING0
3791 /* There are no mappings in VT-x and AMD-V mode. */
3792 Assert(pPGM->fDisableMappings);
3793 return false;
3794#else
3795 return !pPGM->fDisableMappings;
3796#endif
3797}
3798
3799/** @} */
3800
3801#endif
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette