VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 9705

Last change on this file since 9705 was 9692, checked in by vboxsync, 17 years ago

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1/* $Id: PGMInternal.h 9692 2008-06-13 16:03:19Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
44# error "Not in PGM! This is an internal header!"
45#endif
46
47
48/** @defgroup grp_pgm_int Internals
49 * @ingroup grp_pgm
50 * @internal
51 * @{
52 */
53
54
55/** @name PGM Compile Time Config
56 * @{
57 */
58
59/**
60 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
61 * Comment it if it will break something.
62 */
63#define PGM_OUT_OF_SYNC_IN_GC
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Sync N pages instead of a whole page table
72 */
73#define PGM_SYNC_N_PAGES
74
75/**
76 * Number of pages to sync during a page fault
77 *
78 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
79 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
80 */
81#define PGM_SYNC_NR_PAGES 8
82
83/**
84 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
85 */
86#define PGM_MAX_PHYSCACHE_ENTRIES 64
87#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
88
89/**
90 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
91 */
92#define PGM_PHYSMEMACCESS_CACHING
93
94/** @def PGMPOOL_WITH_CACHE
95 * Enable agressive caching using the page pool.
96 *
97 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
98 */
99#define PGMPOOL_WITH_CACHE
100
101/** @def PGMPOOL_WITH_MIXED_PT_CR3
102 * When defined, we'll deal with 'uncachable' pages.
103 */
104#ifdef PGMPOOL_WITH_CACHE
105# define PGMPOOL_WITH_MIXED_PT_CR3
106#endif
107
108/** @def PGMPOOL_WITH_MONITORING
109 * Monitor the guest pages which are shadowed.
110 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
111 * be enabled as well.
112 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
113 */
114#ifdef PGMPOOL_WITH_CACHE
115# define PGMPOOL_WITH_MONITORING
116#endif
117
118/** @def PGMPOOL_WITH_GCPHYS_TRACKING
119 * Tracking the of shadow pages mapping guest physical pages.
120 *
121 * This is very expensive, the current cache prototype is trying to figure out
122 * whether it will be acceptable with an agressive caching policy.
123 */
124#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
125# define PGMPOOL_WITH_GCPHYS_TRACKING
126#endif
127
128/** @def PGMPOOL_WITH_USER_TRACKNG
129 * Tracking users of shadow pages. This is required for the linking of shadow page
130 * tables and physical guest addresses.
131 */
132#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
133# define PGMPOOL_WITH_USER_TRACKING
134#endif
135
136/** @def PGMPOOL_CFG_MAX_GROW
137 * The maximum number of pages to add to the pool in one go.
138 */
139#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
140
141/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
142 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
143 */
144#ifdef VBOX_STRICT
145# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
146#endif
147/** @} */
148
149
150/** @name PDPT and PML4 flags.
151 * These are placed in the three bits available for system programs in
152 * the PDPT and PML4 entries.
153 * @{ */
154/** The entry is a permanent one and it's must always be present.
155 * Never free such an entry. */
156#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
157/** Mapping (hypervisor allocated pagetable). */
158#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
159/** @} */
160
161/** @name Page directory flags.
162 * These are placed in the three bits available for system programs in
163 * the page directory entries.
164 * @{ */
165/** Mapping (hypervisor allocated pagetable). */
166#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
167/** Made read-only to facilitate dirty bit tracking. */
168#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
169/** @} */
170
171/** @name Page flags.
172 * These are placed in the three bits available for system programs in
173 * the page entries.
174 * @{ */
175/** Made read-only to facilitate dirty bit tracking. */
176#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
177
178#ifndef PGM_PTFLAGS_CSAM_VALIDATED
179/** Scanned and approved by CSAM (tm).
180 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
181 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
182#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
183#endif
184/** @} */
185
186/** @name Defines used to indicate the shadow and guest paging in the templates.
187 * @{ */
188#define PGM_TYPE_REAL 1
189#define PGM_TYPE_PROT 2
190#define PGM_TYPE_32BIT 3
191#define PGM_TYPE_PAE 4
192#define PGM_TYPE_AMD64 5
193#define PGM_TYPE_NESTED 6
194/** @} */
195
196/** Macro for checking if the guest is using paging.
197 * @param uType PGM_TYPE_*
198 * @remark ASSUMES certain order of the PGM_TYPE_* values.
199 */
200#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT && (uType) != PGM_TYPE_NESTED)
201
202/** Macro for checking if the guest supports the NX bit.
203 * @param uType PGM_TYPE_*
204 * @remark ASSUMES certain order of the PGM_TYPE_* values.
205 */
206#define PGM_WITH_NX(uType) ((uType) >= PGM_TYPE_PAE && (uType) != PGM_TYPE_NESTED)
207
208
209/** @def PGM_HCPHYS_2_PTR
210 * Maps a HC physical page pool address to a virtual address.
211 *
212 * @returns VBox status code.
213 * @param pVM The VM handle.
214 * @param HCPhys The HC physical address to map to a virtual one.
215 * @param ppv Where to store the virtual address. No need to cast this.
216 *
217 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
218 * small page window employeed by that function. Be careful.
219 * @remark There is no need to assert on the result.
220 */
221#ifdef IN_GC
222# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
223#else
224# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
225#endif
226
227/** @def PGM_GCPHYS_2_PTR
228 * Maps a GC physical page address to a virtual address.
229 *
230 * @returns VBox status code.
231 * @param pVM The VM handle.
232 * @param GCPhys The GC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast this.
234 *
235 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
236 * small page window employeed by that function. Be careful.
237 * @remark There is no need to assert on the result.
238 */
239#ifdef IN_GC
240# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
241#else
242# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
243#endif
244
245/** @def PGM_GCPHYS_2_PTR_EX
246 * Maps a unaligned GC physical page address to a virtual address.
247 *
248 * @returns VBox status code.
249 * @param pVM The VM handle.
250 * @param GCPhys The GC physical address to map to a virtual one.
251 * @param ppv Where to store the virtual address. No need to cast this.
252 *
253 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
254 * small page window employeed by that function. Be careful.
255 * @remark There is no need to assert on the result.
256 */
257#ifdef IN_GC
258# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
259#else
260# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
261#endif
262
263/** @def PGM_INVL_PG
264 * Invalidates a page when in GC does nothing in HC.
265 *
266 * @param GCVirt The virtual address of the page to invalidate.
267 */
268#ifdef IN_GC
269# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
270#elif defined(IN_RING0)
271# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
272#else
273# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
274#endif
275
276/** @def PGM_INVL_BIG_PG
277 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
278 *
279 * @param GCVirt The virtual address within the page directory to invalidate.
280 */
281#ifdef IN_GC
282# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
283#elif defined(IN_RING0)
284# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
285#else
286# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
287#endif
288
289/** @def PGM_INVL_GUEST_TLBS()
290 * Invalidates all guest TLBs.
291 */
292#ifdef IN_GC
293# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
294#elif defined(IN_RING0)
295# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
296#else
297# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
298#endif
299
300
301/**
302 * Structure for tracking GC Mappings.
303 *
304 * This structure is used by linked list in both GC and HC.
305 */
306typedef struct PGMMAPPING
307{
308 /** Pointer to next entry. */
309 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
310 /** Pointer to next entry. */
311 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
312 /** Pointer to next entry. */
313 RCPTRTYPE(struct PGMMAPPING *) pNextGC;
314#if GC_ARCH_BITS == 64
315 RTRCPTR padding0;
316#endif
317 /** Start Virtual address. */
318 RTGCUINTPTR GCPtr;
319 /** Last Virtual address (inclusive). */
320 RTGCUINTPTR GCPtrLast;
321 /** Range size (bytes). */
322 RTGCUINTPTR cb;
323 /** Pointer to relocation callback function. */
324 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
325 /** User argument to the callback. */
326 R3PTRTYPE(void *) pvUser;
327 /** Mapping description / name. For easing debugging. */
328 R3PTRTYPE(const char *) pszDesc;
329 /** Number of page tables. */
330 RTUINT cPTs;
331#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
332 RTUINT uPadding1; /**< Alignment padding. */
333#endif
334 /** Array of page table mapping data. Each entry
335 * describes one page table. The array can be longer
336 * than the declared length.
337 */
338 struct
339 {
340 /** The HC physical address of the page table. */
341 RTHCPHYS HCPhysPT;
342 /** The HC physical address of the first PAE page table. */
343 RTHCPHYS HCPhysPaePT0;
344 /** The HC physical address of the second PAE page table. */
345 RTHCPHYS HCPhysPaePT1;
346 /** The HC virtual address of the 32-bit page table. */
347 R3PTRTYPE(PX86PT) pPTR3;
348 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
349 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
350 /** The GC virtual address of the 32-bit page table. */
351 RCPTRTYPE(PX86PT) pPTGC;
352 /** The GC virtual address of the two PAE page table. */
353 RCPTRTYPE(PX86PTPAE) paPaePTsGC;
354 /** The GC virtual address of the 32-bit page table. */
355 R0PTRTYPE(PX86PT) pPTR0;
356 /** The GC virtual address of the two PAE page table. */
357 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
358 } aPTs[1];
359} PGMMAPPING;
360/** Pointer to structure for tracking GC Mappings. */
361typedef struct PGMMAPPING *PPGMMAPPING;
362
363
364/**
365 * Physical page access handler structure.
366 *
367 * This is used to keep track of physical address ranges
368 * which are being monitored in some kind of way.
369 */
370typedef struct PGMPHYSHANDLER
371{
372 AVLROGCPHYSNODECORE Core;
373 /** Access type. */
374 PGMPHYSHANDLERTYPE enmType;
375 /** Number of pages to update. */
376 uint32_t cPages;
377 /** Pointer to R3 callback function. */
378 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
379 /** User argument for R3 handlers. */
380 R3PTRTYPE(void *) pvUserR3;
381 /** Pointer to R0 callback function. */
382 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
383 /** User argument for R0 handlers. */
384 R0PTRTYPE(void *) pvUserR0;
385 /** Pointer to GC callback function. */
386 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
387 /** User argument for GC handlers. */
388 RCPTRTYPE(void *) pvUserGC;
389 /** Description / Name. For easing debugging. */
390 R3PTRTYPE(const char *) pszDesc;
391#ifdef VBOX_WITH_STATISTICS
392 /** Profiling of this handler. */
393 STAMPROFILE Stat;
394#endif
395} PGMPHYSHANDLER;
396/** Pointer to a physical page access handler structure. */
397typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
398
399
400/**
401 * Cache node for the physical addresses covered by a virtual handler.
402 */
403typedef struct PGMPHYS2VIRTHANDLER
404{
405 /** Core node for the tree based on physical ranges. */
406 AVLROGCPHYSNODECORE Core;
407 /** Offset from this struct to the PGMVIRTHANDLER structure. */
408 int32_t offVirtHandler;
409 /** Offset of the next alias relative to this one.
410 * Bit 0 is used for indicating whether we're in the tree.
411 * Bit 1 is used for indicating that we're the head node.
412 */
413 int32_t offNextAlias;
414} PGMPHYS2VIRTHANDLER;
415/** Pointer to a phys to virtual handler structure. */
416typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
417
418/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
419 * node is in the tree. */
420#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
421/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
422 * node is in the head of an alias chain.
423 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
424#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
425/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
426#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
427
428
429/**
430 * Virtual page access handler structure.
431 *
432 * This is used to keep track of virtual address ranges
433 * which are being monitored in some kind of way.
434 */
435typedef struct PGMVIRTHANDLER
436{
437 /** Core node for the tree based on virtual ranges. */
438 AVLROGCPTRNODECORE Core;
439 /** Number of cache pages. */
440 uint32_t u32Padding;
441 /** Access type. */
442 PGMVIRTHANDLERTYPE enmType;
443 /** Number of cache pages. */
444 uint32_t cPages;
445#if GC_ARCH_BITS == 64
446 uint32_t padding0;
447#endif
448/** @todo The next two members are redundant. It adds some readability though. */
449 /** Start of the range. */
450 RTGCPTR GCPtr;
451 /** End of the range (exclusive). */
452 RTGCPTR GCPtrLast;
453 /** Size of the range (in bytes). */
454 RTGCUINTPTR cb;
455 /** Pointer to the GC callback function. */
456 RCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
457#if GC_ARCH_BITS == 64
458 RTRCPTR padding1;
459#endif
460 /** Pointer to the HC callback function for invalidation. */
461 R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
462 /** Pointer to the HC callback function. */
463 R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
464 /** Description / Name. For easing debugging. */
465 R3PTRTYPE(const char *) pszDesc;
466#ifdef VBOX_WITH_STATISTICS
467 /** Profiling of this handler. */
468 STAMPROFILE Stat;
469#endif
470 /** Array of cached physical addresses for the monitored ranged. */
471 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
472} PGMVIRTHANDLER;
473/** Pointer to a virtual page access handler structure. */
474typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
475
476
477/**
478 * Page type.
479 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
480 * @todo convert to \#defines.
481 */
482typedef enum PGMPAGETYPE
483{
484 /** The usual invalid zero entry. */
485 PGMPAGETYPE_INVALID = 0,
486 /** RAM page. (RWX) */
487 PGMPAGETYPE_RAM,
488 /** MMIO2 page. (RWX) */
489 PGMPAGETYPE_MMIO2,
490 /** Shadowed ROM. (RWX) */
491 PGMPAGETYPE_ROM_SHADOW,
492 /** ROM page. (R-X) */
493 PGMPAGETYPE_ROM,
494 /** MMIO page. (---) */
495 PGMPAGETYPE_MMIO,
496 /** End of valid entries. */
497 PGMPAGETYPE_END
498} PGMPAGETYPE;
499AssertCompile(PGMPAGETYPE_END < 7);
500
501/** @name Page type predicates.
502 * @{ */
503#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
504#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
505#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
506#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
507#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
508/** @} */
509
510
511/**
512 * A Physical Guest Page tracking structure.
513 *
514 * The format of this structure is complicated because we have to fit a lot
515 * of information into as few bits as possible. The format is also subject
516 * to change (there is one comming up soon). Which means that for we'll be
517 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
518 * accessess to the structure.
519 */
520typedef struct PGMPAGE
521{
522 /** The physical address and a whole lot of other stuff. All bits are used! */
523 RTHCPHYS HCPhys;
524 /** The page state. */
525 uint32_t u2StateX : 2;
526 /** Flag indicating that a write monitored page was written to when set. */
527 uint32_t fWrittenToX : 1;
528 /** For later. */
529 uint32_t fSomethingElse : 1;
530 /** The Page ID.
531 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
532 * The HCPhys will be 100% static. */
533 uint32_t idPageX : 28;
534 /** The page type (PGMPAGETYPE). */
535 uint32_t u3Type : 3;
536 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
537 uint32_t u2HandlerPhysStateX : 2;
538 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
539 uint32_t u2HandlerVirtStateX : 2;
540 uint32_t u29B : 25;
541} PGMPAGE;
542AssertCompileSize(PGMPAGE, 16);
543/** Pointer to a physical guest page. */
544typedef PGMPAGE *PPGMPAGE;
545/** Pointer to a const physical guest page. */
546typedef const PGMPAGE *PCPGMPAGE;
547/** Pointer to a physical guest page pointer. */
548typedef PPGMPAGE *PPPGMPAGE;
549
550
551/**
552 * Clears the page structure.
553 * @param pPage Pointer to the physical guest page tracking structure.
554 */
555#define PGM_PAGE_CLEAR(pPage) \
556 do { \
557 (pPage)->HCPhys = 0; \
558 (pPage)->u2StateX = 0; \
559 (pPage)->fWrittenToX = 0; \
560 (pPage)->fSomethingElse = 0; \
561 (pPage)->idPageX = 0; \
562 (pPage)->u3Type = 0; \
563 (pPage)->u29B = 0; \
564 } while (0)
565
566/**
567 * Initializes the page structure.
568 * @param pPage Pointer to the physical guest page tracking structure.
569 */
570#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
571 do { \
572 (pPage)->HCPhys = (_HCPhys); \
573 (pPage)->u2StateX = (_uState); \
574 (pPage)->fWrittenToX = 0; \
575 (pPage)->fSomethingElse = 0; \
576 (pPage)->idPageX = (_idPage); \
577 /*(pPage)->u3Type = (_uType); - later */ \
578 PGM_PAGE_SET_TYPE(pPage, _uType); \
579 (pPage)->u29B = 0; \
580 } while (0)
581
582/**
583 * Initializes the page structure of a ZERO page.
584 * @param pPage Pointer to the physical guest page tracking structure.
585 */
586#ifdef VBOX_WITH_NEW_PHYS_CODE
587# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
588 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
589#else
590# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
591 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
592#endif
593/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
594# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
595 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
596
597
598/** @name The Page state, PGMPAGE::u2StateX.
599 * @{ */
600/** The zero page.
601 * This is a per-VM page that's never ever mapped writable. */
602#define PGM_PAGE_STATE_ZERO 0
603/** A allocated page.
604 * This is a per-VM page allocated from the page pool (or wherever
605 * we get MMIO2 pages from if the type is MMIO2).
606 */
607#define PGM_PAGE_STATE_ALLOCATED 1
608/** A allocated page that's being monitored for writes.
609 * The shadow page table mappings are read-only. When a write occurs, the
610 * fWrittenTo member is set, the page remapped as read-write and the state
611 * moved back to allocated. */
612#define PGM_PAGE_STATE_WRITE_MONITORED 2
613/** The page is shared, aka. copy-on-write.
614 * This is a page that's shared with other VMs. */
615#define PGM_PAGE_STATE_SHARED 3
616/** @} */
617
618
619/**
620 * Gets the page state.
621 * @returns page state (PGM_PAGE_STATE_*).
622 * @param pPage Pointer to the physical guest page tracking structure.
623 */
624#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
625
626/**
627 * Sets the page state.
628 * @param pPage Pointer to the physical guest page tracking structure.
629 * @param _uState The new page state.
630 */
631#define PGM_PAGE_SET_STATE(pPage, _uState) \
632 do { (pPage)->u2StateX = (_uState); } while (0)
633
634
635/**
636 * Gets the host physical address of the guest page.
637 * @returns host physical address (RTHCPHYS).
638 * @param pPage Pointer to the physical guest page tracking structure.
639 */
640#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
641
642/**
643 * Sets the host physical address of the guest page.
644 * @param pPage Pointer to the physical guest page tracking structure.
645 * @param _HCPhys The new host physical address.
646 */
647#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
648 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
649 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
650
651/**
652 * Get the Page ID.
653 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
654 * @param pPage Pointer to the physical guest page tracking structure.
655 */
656#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
657/* later:
658#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
659 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
660*/
661/**
662 * Sets the Page ID.
663 * @param pPage Pointer to the physical guest page tracking structure.
664 */
665#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
666/* later:
667#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
668 | ((_idPage) & 0xfff) \
669 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
670*/
671
672/**
673 * Get the Chunk ID.
674 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
675 * @param pPage Pointer to the physical guest page tracking structure.
676 */
677#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
678/* later:
679#if GMM_CHUNKID_SHIFT == 12
680# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
681#elif GMM_CHUNKID_SHIFT > 12
682# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
683#elif GMM_CHUNKID_SHIFT < 12
684# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
685 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
686#else
687# error "GMM_CHUNKID_SHIFT isn't defined or something."
688#endif
689*/
690
691/**
692 * Get the index of the page within the allocaiton chunk.
693 * @returns The page index.
694 * @param pPage Pointer to the physical guest page tracking structure.
695 */
696#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
697/* later:
698#if GMM_CHUNKID_SHIFT <= 12
699# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
700#else
701# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
702 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
703#endif
704*/
705
706
707/**
708 * Gets the page type.
709 * @returns The page type.
710 * @param pPage Pointer to the physical guest page tracking structure.
711 */
712#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
713
714/**
715 * Sets the page type.
716 * @param pPage Pointer to the physical guest page tracking structure.
717 * @param _enmType The new page type (PGMPAGETYPE).
718 */
719#ifdef VBOX_WITH_NEW_PHYS_CODE
720#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
721 do { (pPage)->u3Type = (_enmType); } while (0)
722#else
723#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
724 do { \
725 (pPage)->u3Type = (_enmType); \
726 if ((_enmType) == PGMPAGETYPE_ROM) \
727 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
728 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
729 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
730 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
731 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
732 } while (0)
733#endif
734
735
736/**
737 * Checks if the page is 'reserved'.
738 * @returns true/false.
739 * @param pPage Pointer to the physical guest page tracking structure.
740 */
741#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
742
743/**
744 * Checks if the page is marked for MMIO.
745 * @returns true/false.
746 * @param pPage Pointer to the physical guest page tracking structure.
747 */
748#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
749
750/**
751 * Checks if the page is backed by the ZERO page.
752 * @returns true/false.
753 * @param pPage Pointer to the physical guest page tracking structure.
754 */
755#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
756
757/**
758 * Checks if the page is backed by a SHARED page.
759 * @returns true/false.
760 * @param pPage Pointer to the physical guest page tracking structure.
761 */
762#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
763
764
765/**
766 * Marks the paget as written to (for GMM change monitoring).
767 * @param pPage Pointer to the physical guest page tracking structure.
768 */
769#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
770
771/**
772 * Clears the written-to indicator.
773 * @param pPage Pointer to the physical guest page tracking structure.
774 */
775#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
776
777/**
778 * Checks if the page was marked as written-to.
779 * @returns true/false.
780 * @param pPage Pointer to the physical guest page tracking structure.
781 */
782#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
783
784
785/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
786 *
787 * @remarks The values are assigned in order of priority, so we can calculate
788 * the correct state for a page with different handlers installed.
789 * @{ */
790/** No handler installed. */
791#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
792/** Monitoring is temporarily disabled. */
793#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
794/** Write access is monitored. */
795#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
796/** All access is monitored. */
797#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
798/** @} */
799
800/**
801 * Gets the physical access handler state of a page.
802 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
803 * @param pPage Pointer to the physical guest page tracking structure.
804 */
805#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
806
807/**
808 * Sets the physical access handler state of a page.
809 * @param pPage Pointer to the physical guest page tracking structure.
810 * @param _uState The new state value.
811 */
812#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
813 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
814
815/**
816 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
817 * @returns true/false
818 * @param pPage Pointer to the physical guest page tracking structure.
819 */
820#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
821
822/**
823 * Checks if the page has any active physical access handlers.
824 * @returns true/false
825 * @param pPage Pointer to the physical guest page tracking structure.
826 */
827#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
828
829
830/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
831 *
832 * @remarks The values are assigned in order of priority, so we can calculate
833 * the correct state for a page with different handlers installed.
834 * @{ */
835/** No handler installed. */
836#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
837/* 1 is reserved so the lineup is identical with the physical ones. */
838/** Write access is monitored. */
839#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
840/** All access is monitored. */
841#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
842/** @} */
843
844/**
845 * Gets the virtual access handler state of a page.
846 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
847 * @param pPage Pointer to the physical guest page tracking structure.
848 */
849#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
850
851/**
852 * Sets the virtual access handler state of a page.
853 * @param pPage Pointer to the physical guest page tracking structure.
854 * @param _uState The new state value.
855 */
856#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
857 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
858
859/**
860 * Checks if the page has any virtual access handlers.
861 * @returns true/false
862 * @param pPage Pointer to the physical guest page tracking structure.
863 */
864#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
865
866/**
867 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
868 * virtual handlers.
869 * @returns true/false
870 * @param pPage Pointer to the physical guest page tracking structure.
871 */
872#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
873
874
875
876/**
877 * Checks if the page has any access handlers, including temporarily disabled ones.
878 * @returns true/false
879 * @param pPage Pointer to the physical guest page tracking structure.
880 */
881#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
882 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
883 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
884
885/**
886 * Checks if the page has any active access handlers.
887 * @returns true/false
888 * @param pPage Pointer to the physical guest page tracking structure.
889 */
890#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
891 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
892 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
893
894/**
895 * Checks if the page has any active access handlers catching all accesses.
896 * @returns true/false
897 * @param pPage Pointer to the physical guest page tracking structure.
898 */
899#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
900 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
901 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
902
903
904/**
905 * Ram range for GC Phys to HC Phys conversion.
906 *
907 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
908 * conversions too, but we'll let MM handle that for now.
909 *
910 * This structure is used by linked lists in both GC and HC.
911 */
912typedef struct PGMRAMRANGE
913{
914 /** Pointer to the next RAM range - for R3. */
915 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
916 /** Pointer to the next RAM range - for R0. */
917 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
918 /** Pointer to the next RAM range - for GC. */
919 RCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
920 /** Pointer alignment. */
921 RTRCPTR GCPtrAlignment;
922 /** Start of the range. Page aligned. */
923 RTGCPHYS GCPhys;
924 /** Last address in the range (inclusive). Page aligned (-1). */
925 RTGCPHYS GCPhysLast;
926 /** Size of the range. (Page aligned of course). */
927 RTGCPHYS cb;
928 /** MM_RAM_* flags */
929 uint32_t fFlags;
930#ifdef VBOX_WITH_NEW_PHYS_CODE
931 uint32_t u32Alignment; /**< alignment. */
932#else
933 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
934 RCPTRTYPE(PRTHCPTR) pavHCChunkGC;
935 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
936 R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
937#endif
938 /** Start of the HC mapping of the range. This is only used for MMIO2. */
939 R3PTRTYPE(void *) pvHC;
940 /** The range description. */
941 R3PTRTYPE(const char *) pszDesc;
942
943 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
944#ifdef VBOX_WITH_NEW_PHYS_CODE
945 uint32_t au32Reserved[2];
946#elif HC_ARCH_BITS == 32
947 uint32_t au32Reserved[1];
948#endif
949
950 /** Array of physical guest page tracking structures. */
951 PGMPAGE aPages[1];
952} PGMRAMRANGE;
953/** Pointer to Ram range for GC Phys to HC Phys conversion. */
954typedef PGMRAMRANGE *PPGMRAMRANGE;
955
956/** Return hc ptr corresponding to the ram range and physical offset */
957#define PGMRAMRANGE_GETHCPTR(pRam, off) \
958 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
959 : (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
960
961/**
962 * Per page tracking structure for ROM image.
963 *
964 * A ROM image may have a shadow page, in which case we may have
965 * two pages backing it. This structure contains the PGMPAGE for
966 * both while PGMRAMRANGE have a copy of the active one. It is
967 * important that these aren't out of sync in any regard other
968 * than page pool tracking data.
969 */
970typedef struct PGMROMPAGE
971{
972 /** The page structure for the virgin ROM page. */
973 PGMPAGE Virgin;
974 /** The page structure for the shadow RAM page. */
975 PGMPAGE Shadow;
976 /** The current protection setting. */
977 PGMROMPROT enmProt;
978 /** Pad the structure size to a multiple of 8. */
979 uint32_t u32Padding;
980} PGMROMPAGE;
981/** Pointer to a ROM page tracking structure. */
982typedef PGMROMPAGE *PPGMROMPAGE;
983
984
985/**
986 * A registered ROM image.
987 *
988 * This is needed to keep track of ROM image since they generally
989 * intrude into a PGMRAMRANGE. It also keeps track of additional
990 * info like the two page sets (read-only virgin and read-write shadow),
991 * the current state of each page.
992 *
993 * Because access handlers cannot easily be executed in a different
994 * context, the ROM ranges needs to be accessible and in all contexts.
995 */
996typedef struct PGMROMRANGE
997{
998 /** Pointer to the next range - R3. */
999 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1000 /** Pointer to the next range - R0. */
1001 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1002 /** Pointer to the next range - GC. */
1003 RCPTRTYPE(struct PGMROMRANGE *) pNextGC;
1004 /** Pointer alignment */
1005 RTRCPTR GCPtrAlignment;
1006 /** Address of the range. */
1007 RTGCPHYS GCPhys;
1008 /** Address of the last byte in the range. */
1009 RTGCPHYS GCPhysLast;
1010 /** Size of the range. */
1011 RTGCPHYS cb;
1012 /** The flags (PGMPHYS_ROM_FLAG_*). */
1013 uint32_t fFlags;
1014 /**< Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1015 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1016 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1017 * This is used for strictness checks. */
1018 R3PTRTYPE(const void *) pvOriginal;
1019 /** The ROM description. */
1020 R3PTRTYPE(const char *) pszDesc;
1021 /** The per page tracking structures. */
1022 PGMROMPAGE aPages[1];
1023} PGMROMRANGE;
1024/** Pointer to a ROM range. */
1025typedef PGMROMRANGE *PPGMROMRANGE;
1026
1027
1028/**
1029 * A registered MMIO2 (= Device RAM) range.
1030 *
1031 * There are a few reason why we need to keep track of these
1032 * registrations. One of them is the deregistration & cleanup
1033 * stuff, while another is that the PGMRAMRANGE associated with
1034 * such a region may have to be removed from the ram range list.
1035 *
1036 * Overlapping with a RAM range has to be 100% or none at all. The
1037 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1038 * meditation will be raised if a partial overlap or an overlap of
1039 * ROM pages is encountered. On an overlap we will free all the
1040 * existing RAM pages and put in the ram range pages instead.
1041 */
1042typedef struct PGMMMIO2RANGE
1043{
1044 /** The owner of the range. (a device) */
1045 PPDMDEVINSR3 pDevInsR3;
1046 /** Pointer to the ring-3 mapping of the allocation. */
1047 RTR3PTR pvR3;
1048 /** Pointer to the next range - R3. */
1049 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1050 /** Whether it's mapped or not. */
1051 bool fMapped;
1052 /** Whether it's overlapping or not. */
1053 bool fOverlapping;
1054 /** The PCI region number.
1055 * @remarks This ASSUMES that nobody will ever really need to have multiple
1056 * PCI devices with matching MMIO region numbers on a single device. */
1057 uint8_t iRegion;
1058 /**< Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1059 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1060 /** The associated RAM range. */
1061 PGMRAMRANGE RamRange;
1062} PGMMMIO2RANGE;
1063/** Pointer to a MMIO2 range. */
1064typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1065
1066
1067
1068
1069/** @todo r=bird: fix typename. */
1070/**
1071 * PGMPhysRead/Write cache entry
1072 */
1073typedef struct PGMPHYSCACHE_ENTRY
1074{
1075 /** HC pointer to physical page */
1076 R3PTRTYPE(uint8_t *) pbHC;
1077 /** GC Physical address for cache entry */
1078 RTGCPHYS GCPhys;
1079#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1080 RTGCPHYS u32Padding0; /**< alignment padding. */
1081#endif
1082} PGMPHYSCACHE_ENTRY;
1083
1084/**
1085 * PGMPhysRead/Write cache to reduce REM memory access overhead
1086 */
1087typedef struct PGMPHYSCACHE
1088{
1089 /** Bitmap of valid cache entries */
1090 uint64_t aEntries;
1091 /** Cache entries */
1092 PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1093} PGMPHYSCACHE;
1094
1095
1096/** Pointer to an allocation chunk ring-3 mapping. */
1097typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1098/** Pointer to an allocation chunk ring-3 mapping pointer. */
1099typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1100
1101/**
1102 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1103 *
1104 * The primary tree (Core) uses the chunk id as key.
1105 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1106 */
1107typedef struct PGMCHUNKR3MAP
1108{
1109 /** The key is the chunk id. */
1110 AVLU32NODECORE Core;
1111 /** The key is the ageing sequence number. */
1112 AVLLU32NODECORE AgeCore;
1113 /** The current age thingy. */
1114 uint32_t iAge;
1115 /** The current reference count. */
1116 uint32_t volatile cRefs;
1117 /** The current permanent reference count. */
1118 uint32_t volatile cPermRefs;
1119 /** The mapping address. */
1120 void *pv;
1121} PGMCHUNKR3MAP;
1122
1123/**
1124 * Allocation chunk ring-3 mapping TLB entry.
1125 */
1126typedef struct PGMCHUNKR3MAPTLBE
1127{
1128 /** The chunk id. */
1129 uint32_t volatile idChunk;
1130#if HC_ARCH_BITS == 64
1131 uint32_t u32Padding; /**< alignment padding. */
1132#endif
1133 /** The chunk map. */
1134 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1135} PGMCHUNKR3MAPTLBE;
1136/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1137typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1138
1139/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1140 * @remark Must be a power of two value. */
1141#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1142
1143/**
1144 * Allocation chunk ring-3 mapping TLB.
1145 *
1146 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1147 * At first glance this might look kinda odd since AVL trees are
1148 * supposed to give the most optimial lookup times of all trees
1149 * due to their balancing. However, take a tree with 1023 nodes
1150 * in it, that's 10 levels, meaning that most searches has to go
1151 * down 9 levels before they find what they want. This isn't fast
1152 * compared to a TLB hit. There is the factor of cache misses,
1153 * and of course the problem with trees and branch prediction.
1154 * This is why we use TLBs in front of most of the trees.
1155 *
1156 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1157 * difficult when we switch to inlined AVL trees (from kStuff).
1158 */
1159typedef struct PGMCHUNKR3MAPTLB
1160{
1161 /** The TLB entries. */
1162 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1163} PGMCHUNKR3MAPTLB;
1164
1165/**
1166 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1167 * @returns Chunk TLB index.
1168 * @param idChunk The Chunk ID.
1169 */
1170#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1171
1172
1173/**
1174 * Ring-3 guest page mapping TLB entry.
1175 * @remarks used in ring-0 as well at the moment.
1176 */
1177typedef struct PGMPAGER3MAPTLBE
1178{
1179 /** Address of the page. */
1180 RTGCPHYS volatile GCPhys;
1181 /** The guest page. */
1182 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1183 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1184 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1185 /** The address */
1186 R3R0PTRTYPE(void *) volatile pv;
1187#if HC_ARCH_BITS == 32
1188 uint32_t u32Padding; /**< alignment padding. */
1189#endif
1190} PGMPAGER3MAPTLBE;
1191/** Pointer to an entry in the HC physical TLB. */
1192typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1193
1194
1195/** The number of entries in the ring-3 guest page mapping TLB.
1196 * @remarks The value must be a power of two. */
1197#define PGM_PAGER3MAPTLB_ENTRIES 64
1198
1199/**
1200 * Ring-3 guest page mapping TLB.
1201 * @remarks used in ring-0 as well at the moment.
1202 */
1203typedef struct PGMPAGER3MAPTLB
1204{
1205 /** The TLB entries. */
1206 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1207} PGMPAGER3MAPTLB;
1208/** Pointer to the ring-3 guest page mapping TLB. */
1209typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1210
1211/**
1212 * Calculates the index of the TLB entry for the specified guest page.
1213 * @returns Physical TLB index.
1214 * @param GCPhys The guest physical address.
1215 */
1216#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1217
1218
1219/** @name Context neutrual page mapper TLB.
1220 *
1221 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1222 * code is writting in a kind of context neutrual way. Time will show whether
1223 * this actually makes sense or not...
1224 *
1225 * @{ */
1226/** @typedef PPGMPAGEMAPTLB
1227 * The page mapper TLB pointer type for the current context. */
1228/** @typedef PPGMPAGEMAPTLB
1229 * The page mapper TLB entry pointer type for the current context. */
1230/** @typedef PPGMPAGEMAPTLB
1231 * The page mapper TLB entry pointer pointer type for the current context. */
1232/** @def PGMPAGEMAPTLB_ENTRIES
1233 * The number of TLB entries in the page mapper TLB for the current context. */
1234/** @def PGM_PAGEMAPTLB_IDX
1235 * Calculate the TLB index for a guest physical address.
1236 * @returns The TLB index.
1237 * @param GCPhys The guest physical address. */
1238/** @typedef PPGMPAGEMAP
1239 * Pointer to a page mapper unit for current context. */
1240/** @typedef PPPGMPAGEMAP
1241 * Pointer to a page mapper unit pointer for current context. */
1242#ifdef IN_GC
1243// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1244// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1245// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1246# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1247# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1248 typedef void * PPGMPAGEMAP;
1249 typedef void ** PPPGMPAGEMAP;
1250//#elif IN_RING0
1251// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1252// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1253// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1254//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1255//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1256// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1257// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1258#else
1259 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1260 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1261 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1262# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1263# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1264 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1265 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1266#endif
1267/** @} */
1268
1269
1270/** @name PGM Pool Indexes.
1271 * Aka. the unique shadow page identifier.
1272 * @{ */
1273/** NIL page pool IDX. */
1274#define NIL_PGMPOOL_IDX 0
1275/** The first normal index. */
1276#define PGMPOOL_IDX_FIRST_SPECIAL 1
1277/** Page directory (32-bit root). */
1278#define PGMPOOL_IDX_PD 1
1279/** The extended PAE page directory (2048 entries, works as root currently). */
1280#define PGMPOOL_IDX_PAE_PD 2
1281/** PAE Page Directory Table 0. */
1282#define PGMPOOL_IDX_PAE_PD_0 3
1283/** PAE Page Directory Table 1. */
1284#define PGMPOOL_IDX_PAE_PD_1 4
1285/** PAE Page Directory Table 2. */
1286#define PGMPOOL_IDX_PAE_PD_2 5
1287/** PAE Page Directory Table 3. */
1288#define PGMPOOL_IDX_PAE_PD_3 6
1289/** Page Directory Pointer Table (PAE root, not currently used). */
1290#define PGMPOOL_IDX_PDPT 7
1291/** Page Map Level-4 (64-bit root). */
1292#define PGMPOOL_IDX_PML4 8
1293/** The first normal index. */
1294#define PGMPOOL_IDX_FIRST 9
1295/** The last valid index. (inclusive, 14 bits) */
1296#define PGMPOOL_IDX_LAST 0x3fff
1297/** @} */
1298
1299/** The NIL index for the parent chain. */
1300#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1301
1302/**
1303 * Node in the chain linking a shadowed page to it's parent (user).
1304 */
1305#pragma pack(1)
1306typedef struct PGMPOOLUSER
1307{
1308 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1309 uint16_t iNext;
1310 /** The user page index. */
1311 uint32_t iUser;
1312 /** Index into the user table. */
1313 uint32_t iUserTable;
1314} PGMPOOLUSER, *PPGMPOOLUSER;
1315typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1316#pragma pack()
1317
1318
1319/** The NIL index for the phys ext chain. */
1320#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1321
1322/**
1323 * Node in the chain of physical cross reference extents.
1324 */
1325#pragma pack(1)
1326typedef struct PGMPOOLPHYSEXT
1327{
1328 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1329 uint16_t iNext;
1330 /** The user page index. */
1331 uint16_t aidx[3];
1332} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1333typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1334#pragma pack()
1335
1336
1337/**
1338 * The kind of page that's being shadowed.
1339 */
1340typedef enum PGMPOOLKIND
1341{
1342 /** The virtual invalid 0 entry. */
1343 PGMPOOLKIND_INVALID = 0,
1344 /** The entry is free (=unused). */
1345 PGMPOOLKIND_FREE,
1346
1347 /** Shw: 32-bit page table; Gst: no paging */
1348 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1349 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1350 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1351 /** Shw: 32-bit page table; Gst: 4MB page. */
1352 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1353 /** Shw: PAE page table; Gst: no paging */
1354 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1355 /** Shw: PAE page table; Gst: 32-bit page table. */
1356 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1357 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1358 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1359 /** Shw: PAE page table; Gst: PAE page table. */
1360 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1361 /** Shw: PAE page table; Gst: 2MB page. */
1362 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1363
1364 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1365 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1366 /** Shw: PAE page directory; Gst: PAE page directory. */
1367 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1368
1369 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1370 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1371 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1372 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1373
1374 /** Shw: Root 32-bit page directory. */
1375 PGMPOOLKIND_ROOT_32BIT_PD,
1376 /** Shw: Root PAE page directory */
1377 PGMPOOLKIND_ROOT_PAE_PD,
1378 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1379 PGMPOOLKIND_ROOT_PDPT,
1380 /** Shw: Root page map level-4 table. */
1381 PGMPOOLKIND_ROOT_PML4,
1382
1383 /** The last valid entry. */
1384 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PML4
1385} PGMPOOLKIND;
1386
1387
1388/**
1389 * The tracking data for a page in the pool.
1390 */
1391typedef struct PGMPOOLPAGE
1392{
1393 /** AVL node code with the (HC) physical address of this page. */
1394 AVLOHCPHYSNODECORE Core;
1395 /** Pointer to the HC mapping of the page. */
1396 R3R0PTRTYPE(void *) pvPageHC;
1397 /** The guest physical address. */
1398#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1399 uint32_t Alignment0;
1400#endif
1401 RTGCPHYS GCPhys;
1402 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1403 uint8_t enmKind;
1404 uint8_t bPadding;
1405 /** The index of this page. */
1406 uint16_t idx;
1407 /** The next entry in the list this page currently resides in.
1408 * It's either in the free list or in the GCPhys hash. */
1409 uint16_t iNext;
1410#ifdef PGMPOOL_WITH_USER_TRACKING
1411 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1412 uint16_t iUserHead;
1413 /** The number of present entries. */
1414 uint16_t cPresent;
1415 /** The first entry in the table which is present. */
1416 uint16_t iFirstPresent;
1417#endif
1418#ifdef PGMPOOL_WITH_MONITORING
1419 /** The number of modifications to the monitored page. */
1420 uint16_t cModifications;
1421 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1422 uint16_t iModifiedNext;
1423 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1424 uint16_t iModifiedPrev;
1425 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1426 uint16_t iMonitoredNext;
1427 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1428 uint16_t iMonitoredPrev;
1429#endif
1430#ifdef PGMPOOL_WITH_CACHE
1431 /** The next page in the age list. */
1432 uint16_t iAgeNext;
1433 /** The previous page in the age list. */
1434 uint16_t iAgePrev;
1435#endif /* PGMPOOL_WITH_CACHE */
1436 /** Used to indicate that the page is zeroed. */
1437 bool fZeroed;
1438 /** Used to indicate that a PT has non-global entries. */
1439 bool fSeenNonGlobal;
1440 /** Used to indicate that we're monitoring writes to the guest page. */
1441 bool fMonitored;
1442 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1443 * (All pages are in the age list.) */
1444 bool fCached;
1445 /** This is used by the R3 access handlers when invoked by an async thread.
1446 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1447 bool volatile fReusedFlushPending;
1448 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1449 * In these cases the access handler acts differently and will check
1450 * for mapping conflicts like the normal CR3 handler.
1451 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1452 * replaced by a list of pages which share access handler.
1453 */
1454 bool fCR3Mix;
1455} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1456
1457
1458#ifdef PGMPOOL_WITH_CACHE
1459/** The hash table size. */
1460# define PGMPOOL_HASH_SIZE 0x40
1461/** The hash function. */
1462# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1463#endif
1464
1465
1466/**
1467 * The shadow page pool instance data.
1468 *
1469 * It's all one big allocation made at init time, except for the
1470 * pages that is. The user nodes follows immediatly after the
1471 * page structures.
1472 */
1473typedef struct PGMPOOL
1474{
1475 /** The VM handle - HC Ptr. */
1476 R3R0PTRTYPE(PVM) pVMHC;
1477 /** The VM handle - GC Ptr. */
1478 RCPTRTYPE(PVM) pVMGC;
1479 /** The max pool size. This includes the special IDs. */
1480 uint16_t cMaxPages;
1481 /** The current pool size. */
1482 uint16_t cCurPages;
1483 /** The head of the free page list. */
1484 uint16_t iFreeHead;
1485 /* Padding. */
1486 uint16_t u16Padding;
1487#ifdef PGMPOOL_WITH_USER_TRACKING
1488 /** Head of the chain of free user nodes. */
1489 uint16_t iUserFreeHead;
1490 /** The number of user nodes we've allocated. */
1491 uint16_t cMaxUsers;
1492 /** The number of present page table entries in the entire pool. */
1493 uint32_t cPresent;
1494 /** Pointer to the array of user nodes - GC pointer. */
1495 RCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1496 /** Pointer to the array of user nodes - HC pointer. */
1497 R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1498#endif /* PGMPOOL_WITH_USER_TRACKING */
1499#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1500 /** Head of the chain of free phys ext nodes. */
1501 uint16_t iPhysExtFreeHead;
1502 /** The number of user nodes we've allocated. */
1503 uint16_t cMaxPhysExts;
1504 /** Pointer to the array of physical xref extent - GC pointer. */
1505 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1506 /** Pointer to the array of physical xref extent nodes - HC pointer. */
1507 R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1508#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1509#ifdef PGMPOOL_WITH_CACHE
1510 /** Hash table for GCPhys addresses. */
1511 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1512 /** The head of the age list. */
1513 uint16_t iAgeHead;
1514 /** The tail of the age list. */
1515 uint16_t iAgeTail;
1516 /** Set if the cache is enabled. */
1517 bool fCacheEnabled;
1518#endif /* PGMPOOL_WITH_CACHE */
1519#ifdef PGMPOOL_WITH_MONITORING
1520 /** Head of the list of modified pages. */
1521 uint16_t iModifiedHead;
1522 /** The current number of modified pages. */
1523 uint16_t cModifiedPages;
1524 /** Access handler, GC. */
1525 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1526 /** Access handler, R0. */
1527 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1528 /** Access handler, R3. */
1529 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1530 /** The access handler description (HC ptr). */
1531 R3PTRTYPE(const char *) pszAccessHandler;
1532#endif /* PGMPOOL_WITH_MONITORING */
1533 /** The number of pages currently in use. */
1534 uint16_t cUsedPages;
1535#ifdef VBOX_WITH_STATISTICS
1536 /** The high wather mark for cUsedPages. */
1537 uint16_t cUsedPagesHigh;
1538 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1539 /** Profiling pgmPoolAlloc(). */
1540 STAMPROFILEADV StatAlloc;
1541 /** Profiling pgmPoolClearAll(). */
1542 STAMPROFILE StatClearAll;
1543 /** Profiling pgmPoolFlushAllInt(). */
1544 STAMPROFILE StatFlushAllInt;
1545 /** Profiling pgmPoolFlushPage(). */
1546 STAMPROFILE StatFlushPage;
1547 /** Profiling pgmPoolFree(). */
1548 STAMPROFILE StatFree;
1549 /** Profiling time spent zeroing pages. */
1550 STAMPROFILE StatZeroPage;
1551# ifdef PGMPOOL_WITH_USER_TRACKING
1552 /** Profiling of pgmPoolTrackDeref. */
1553 STAMPROFILE StatTrackDeref;
1554 /** Profiling pgmTrackFlushGCPhysPT. */
1555 STAMPROFILE StatTrackFlushGCPhysPT;
1556 /** Profiling pgmTrackFlushGCPhysPTs. */
1557 STAMPROFILE StatTrackFlushGCPhysPTs;
1558 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1559 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1560 /** Number of times we've been out of user records. */
1561 STAMCOUNTER StatTrackFreeUpOneUser;
1562# endif
1563# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1564 /** Profiling deref activity related tracking GC physical pages. */
1565 STAMPROFILE StatTrackDerefGCPhys;
1566 /** Number of linear searches for a HCPhys in the ram ranges. */
1567 STAMCOUNTER StatTrackLinearRamSearches;
1568 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1569 STAMCOUNTER StamTrackPhysExtAllocFailures;
1570# endif
1571# ifdef PGMPOOL_WITH_MONITORING
1572 /** Profiling the GC PT access handler. */
1573 STAMPROFILE StatMonitorGC;
1574 /** Times we've failed interpreting the instruction. */
1575 STAMCOUNTER StatMonitorGCEmulateInstr;
1576 /** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1577 STAMPROFILE StatMonitorGCFlushPage;
1578 /** Times we've detected fork(). */
1579 STAMCOUNTER StatMonitorGCFork;
1580 /** Profiling the GC access we've handled (except REP STOSD). */
1581 STAMPROFILE StatMonitorGCHandled;
1582 /** Times we've failed interpreting a patch code instruction. */
1583 STAMCOUNTER StatMonitorGCIntrFailPatch1;
1584 /** Times we've failed interpreting a patch code instruction during flushing. */
1585 STAMCOUNTER StatMonitorGCIntrFailPatch2;
1586 /** The number of times we've seen rep prefixes we can't handle. */
1587 STAMCOUNTER StatMonitorGCRepPrefix;
1588 /** Profiling the REP STOSD cases we've handled. */
1589 STAMPROFILE StatMonitorGCRepStosd;
1590
1591 /** Profiling the HC PT access handler. */
1592 STAMPROFILE StatMonitorHC;
1593 /** Times we've failed interpreting the instruction. */
1594 STAMCOUNTER StatMonitorHCEmulateInstr;
1595 /** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1596 STAMPROFILE StatMonitorHCFlushPage;
1597 /** Times we've detected fork(). */
1598 STAMCOUNTER StatMonitorHCFork;
1599 /** Profiling the HC access we've handled (except REP STOSD). */
1600 STAMPROFILE StatMonitorHCHandled;
1601 /** The number of times we've seen rep prefixes we can't handle. */
1602 STAMCOUNTER StatMonitorHCRepPrefix;
1603 /** Profiling the REP STOSD cases we've handled. */
1604 STAMPROFILE StatMonitorHCRepStosd;
1605 /** The number of times we're called in an async thread an need to flush. */
1606 STAMCOUNTER StatMonitorHCAsync;
1607 /** The high wather mark for cModifiedPages. */
1608 uint16_t cModifiedPagesHigh;
1609 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1610# endif
1611# ifdef PGMPOOL_WITH_CACHE
1612 /** The number of cache hits. */
1613 STAMCOUNTER StatCacheHits;
1614 /** The number of cache misses. */
1615 STAMCOUNTER StatCacheMisses;
1616 /** The number of times we've got a conflict of 'kind' in the cache. */
1617 STAMCOUNTER StatCacheKindMismatches;
1618 /** Number of times we've been out of pages. */
1619 STAMCOUNTER StatCacheFreeUpOne;
1620 /** The number of cacheable allocations. */
1621 STAMCOUNTER StatCacheCacheable;
1622 /** The number of uncacheable allocations. */
1623 STAMCOUNTER StatCacheUncacheable;
1624# endif
1625#elif HC_ARCH_BITS == 64
1626 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1627#endif
1628 /** The AVL tree for looking up a page by its HC physical address. */
1629 AVLOHCPHYSTREE HCPhysTree;
1630 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1631 /** Array of pages. (cMaxPages in length)
1632 * The Id is the index into thist array.
1633 */
1634 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1635} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1636
1637
1638/** @def PGMPOOL_PAGE_2_PTR
1639 * Maps a pool page pool into the current context.
1640 *
1641 * @returns VBox status code.
1642 * @param pVM The VM handle.
1643 * @param pPage The pool page.
1644 *
1645 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1646 * small page window employeed by that function. Be careful.
1647 * @remark There is no need to assert on the result.
1648 */
1649#ifdef IN_GC
1650# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1651#else
1652# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1653#endif
1654
1655
1656/**
1657 * Trees are using self relative offsets as pointers.
1658 * So, all its data, including the root pointer, must be in the heap for HC and GC
1659 * to have the same layout.
1660 */
1661typedef struct PGMTREES
1662{
1663 /** Physical access handlers (AVL range+offsetptr tree). */
1664 AVLROGCPHYSTREE PhysHandlers;
1665 /** Virtual access handlers (AVL range + GC ptr tree). */
1666 AVLROGCPTRTREE VirtHandlers;
1667 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1668 AVLROGCPHYSTREE PhysToVirtHandlers;
1669 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1670 AVLROGCPTRTREE HyperVirtHandlers;
1671} PGMTREES;
1672/** Pointer to PGM trees. */
1673typedef PGMTREES *PPGMTREES;
1674
1675
1676/** @name Paging mode macros
1677 * @{ */
1678#ifdef IN_GC
1679# define PGM_CTX(a,b) a##GC##b
1680# define PGM_CTX_STR(a,b) a "GC" b
1681# define PGM_CTX_DECL(type) PGMGCDECL(type)
1682#else
1683# ifdef IN_RING3
1684# define PGM_CTX(a,b) a##R3##b
1685# define PGM_CTX_STR(a,b) a "R3" b
1686# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1687# else
1688# define PGM_CTX(a,b) a##R0##b
1689# define PGM_CTX_STR(a,b) a "R0" b
1690# define PGM_CTX_DECL(type) PGMDECL(type)
1691# endif
1692#endif
1693
1694#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1695#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1696#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1697#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1698#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1699#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1700#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1701#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1702#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1703#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1704#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1705#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1706#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1707#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1708#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1709#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1710#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1711
1712#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1713#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1714#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1715#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1716#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1717#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1718#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1719#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1720#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1721#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1722#define PGM_SHW_NAME_GC_NESTED_STR(name) "pgmGCShwNested" #name
1723#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1724#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1725#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1726
1727/* Shw_Gst */
1728#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1729#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1730#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1731#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1732#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1733#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1734#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1735#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1736#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1737#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1738#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1739#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1740#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1741#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1742
1743#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1744#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1745#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1746#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1747#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1748#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1749#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1750#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1751#define PGM_BTH_NAME_GC_NESTED_REAL_STR(name) "pgmGCBthNestedReal" #name
1752#define PGM_BTH_NAME_GC_NESTED_PROT_STR(name) "pgmGCBthNestedProt" #name
1753#define PGM_BTH_NAME_GC_NESTED_32BIT_STR(name) "pgmGCBthNested32Bit" #name
1754#define PGM_BTH_NAME_GC_NESTED_PAE_STR(name) "pgmGCBthNestedPAE" #name
1755#define PGM_BTH_NAME_GC_NESTED_AMD64_STR(name) "pgmGCBthNestedAMD64" #name
1756#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1757#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1758#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1759#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1760#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1761#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1762#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1763#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1764#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1765#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1766#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1767#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1768#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1769#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
1770
1771#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1772#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1773/** @} */
1774
1775/**
1776 * Data for each paging mode.
1777 */
1778typedef struct PGMMODEDATA
1779{
1780 /** The guest mode type. */
1781 uint32_t uGstType;
1782 /** The shadow mode type. */
1783 uint32_t uShwType;
1784
1785 /** @name Function pointers for Shadow paging.
1786 * @{
1787 */
1788 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1789 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1790 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1791 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1792
1793 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1794 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1795
1796 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1797 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1798 /** @} */
1799
1800 /** @name Function pointers for Guest paging.
1801 * @{
1802 */
1803 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1804 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1805 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1806 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1807 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1808 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1809 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1810 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1811 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1812 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1813 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1814 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1815 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1816
1817 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1818 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1819 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1820 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1821 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1822 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1823 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1824 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1825 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1826
1827 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1828 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1829 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1830 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1831 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1832 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1833 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1834 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1835 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1836 /** @} */
1837
1838 /** @name Function pointers for Both Shadow and Guest paging.
1839 * @{
1840 */
1841 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1842 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1843 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1844 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1845 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1846 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1847 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1848#ifdef VBOX_STRICT
1849 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1850#endif
1851
1852 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1853 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1854 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1855 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1856 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1857 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1858#ifdef VBOX_STRICT
1859 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1860#endif
1861
1862 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1863 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1864 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1865 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1866 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1867 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1868#ifdef VBOX_STRICT
1869 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1870#endif
1871 /** @} */
1872} PGMMODEDATA, *PPGMMODEDATA;
1873
1874
1875
1876/**
1877 * Converts a PGM pointer into a VM pointer.
1878 * @returns Pointer to the VM structure the PGM is part of.
1879 * @param pPGM Pointer to PGM instance data.
1880 */
1881#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1882
1883/**
1884 * PGM Data (part of VM)
1885 */
1886typedef struct PGM
1887{
1888 /** Offset to the VM structure. */
1889 RTINT offVM;
1890
1891 /*
1892 * This will be redefined at least two more times before we're done, I'm sure.
1893 * The current code is only to get on with the coding.
1894 * - 2004-06-10: initial version, bird.
1895 * - 2004-07-02: 1st time, bird.
1896 * - 2004-10-18: 2nd time, bird.
1897 * - 2005-07-xx: 3rd time, bird.
1898 */
1899
1900 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1901 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1902 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1903 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1904
1905 /** The host paging mode. (This is what SUPLib reports.) */
1906 SUPPAGINGMODE enmHostMode;
1907 /** The shadow paging mode. */
1908 PGMMODE enmShadowMode;
1909 /** The guest paging mode. */
1910 PGMMODE enmGuestMode;
1911
1912 /** The current physical address representing in the guest CR3 register. */
1913 RTGCPHYS GCPhysCR3;
1914 /** Pointer to the 5 page CR3 content mapping.
1915 * The first page is always the CR3 (in some form) while the 4 other pages
1916 * are used of the PDs in PAE mode. */
1917 RTGCPTR GCPtrCR3Mapping;
1918#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1919 uint32_t u32Alignment;
1920#endif
1921 /** The physical address of the currently monitored guest CR3 page.
1922 * When this value is NIL_RTGCPHYS no page is being monitored. */
1923 RTGCPHYS GCPhysGstCR3Monitored;
1924
1925 /** @name 32-bit Guest Paging.
1926 * @{ */
1927 /** The guest's page directory, HC pointer. */
1928 R3R0PTRTYPE(PX86PD) pGuestPDHC;
1929 /** The guest's page directory, static GC mapping. */
1930 RCPTRTYPE(PX86PD) pGuestPDGC;
1931 /** @} */
1932
1933 /** @name PAE Guest Paging.
1934 * @{ */
1935 /** The guest's page directory pointer table, static GC mapping. */
1936 RCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
1937 /** The guest's page directory pointer table, HC pointer. */
1938 R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1939 /** The guest's page directories, HC pointers.
1940 * These are individual pointers and don't have to be adjecent.
1941 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1942 R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1943 /** The guest's page directories, static GC mapping.
1944 * Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1945 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1946 RCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1947 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1948 RTGCPHYS aGCPhysGstPaePDs[4];
1949 /** The physical addresses of the monitored guest page directories (PAE). */
1950 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1951 /** @} */
1952
1953 /** @name AMD64 Guest Paging.
1954 * @{ */
1955 /** The guest's page directory pointer table, HC pointer. */
1956 R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
1957 /** @} */
1958
1959 /** @name 32-bit Shadow Paging
1960 * @{ */
1961 /** The 32-Bit PD - HC Ptr. */
1962 R3R0PTRTYPE(PX86PD) pHC32BitPD;
1963 /** The 32-Bit PD - GC Ptr. */
1964 RCPTRTYPE(PX86PD) pGC32BitPD;
1965#if HC_ARCH_BITS == 64
1966 uint32_t u32Padding1; /**< alignment padding. */
1967#endif
1968 /** The Physical Address (HC) of the 32-Bit PD. */
1969 RTHCPHYS HCPhys32BitPD;
1970 /** @} */
1971
1972 /** @name PAE Shadow Paging
1973 * @{ */
1974 /** The four PDs for the low 4GB - HC Ptr.
1975 * Even though these are 4 pointers, what they point at is a single table.
1976 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
1977 R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
1978 /** The four PDs for the low 4GB - GC Ptr.
1979 * Same kind of mapping as apHCPaePDs. */
1980 RCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
1981 /** The Physical Address (HC) of the four PDs for the low 4GB.
1982 * These are *NOT* 4 contiguous pages. */
1983 RTHCPHYS aHCPhysPaePDs[4];
1984 /** The PAE PDP - HC Ptr. */
1985 R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
1986 /** The Physical Address (HC) of the PAE PDPT. */
1987 RTHCPHYS HCPhysPaePDPT;
1988 /** The PAE PDPT - GC Ptr. */
1989 RCPTRTYPE(PX86PDPT) pGCPaePDPT;
1990 /** @} */
1991
1992 /** @name AMD64 Shadow Paging
1993 * Extends PAE Paging.
1994 * @{ */
1995#if HC_ARCH_BITS == 64
1996 RTRCPTR alignment5; /**< structure size alignment. */
1997#endif
1998 /** The Page Map Level 4 table - HC Ptr. */
1999 R3R0PTRTYPE(PX86PML4) pHCPaePML4;
2000 /** The Physical Address (HC) of the Page Map Level 4 table. */
2001 RTHCPHYS HCPhysPaePML4;
2002 /** @}*/
2003
2004 /** @name Function pointers for Shadow paging.
2005 * @{
2006 */
2007 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2008 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2009 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2010 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2011
2012 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2013 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2014
2015 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2016 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2017
2018 /** @} */
2019
2020 /** @name Function pointers for Guest paging.
2021 * @{
2022 */
2023 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2024 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2025 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2026 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2027 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2028 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2029 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2030 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2031 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2032 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2033 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2034 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2035 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2036
2037 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2038 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2039 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2040 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2041 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
2042 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2043 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
2044 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
2045 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
2046#if HC_ARCH_BITS == 64
2047 RTRCPTR alignment3; /**< structure size alignment. */
2048#endif
2049
2050 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2051 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2052 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2053 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2054 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2055 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2056 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2057 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2058 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2059 /** @} */
2060
2061 /** @name Function pointers for Both Shadow and Guest paging.
2062 * @{
2063 */
2064 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2065 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2066 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2067 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2068 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2069 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2070 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2071 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2072
2073 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2074 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2075 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2076 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2077 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2078 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2079 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2080
2081 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2082 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2083 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2084 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2085 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2086 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2087 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2088#if HC_ARCH_BITS == 64
2089 RTRCPTR alignment2; /**< structure size alignment. */
2090#endif
2091 /** @} */
2092
2093 /** Pointer to SHW+GST mode data (function pointers).
2094 * The index into this table is made up from */
2095 R3PTRTYPE(PPGMMODEDATA) paModeData;
2096
2097 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2098 * This is sorted by physical address and contains no overlapping ranges. */
2099 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2100 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2101 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2102 /** GC pointer corresponding to PGM::pRamRangesR3. */
2103 RCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
2104 /** The configured RAM size. */
2105 RTUINT cbRamSize;
2106
2107 /** Pointer to the list of ROM ranges - for R3.
2108 * This is sorted by physical address and contains no overlapping ranges. */
2109 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2110 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2111 R0PTRTYPE(PPGMRAMRANGE) pRomRangesR0;
2112 /** GC pointer corresponding to PGM::pRomRangesR3. */
2113 RCPTRTYPE(PPGMRAMRANGE) pRomRangesGC;
2114 /** Alignment padding. */
2115 RTRCPTR GCPtrPadding2;
2116
2117 /** Pointer to the list of MMIO2 ranges - for R3.
2118 * Registration order. */
2119 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2120
2121 /** PGM offset based trees - HC Ptr. */
2122 R3R0PTRTYPE(PPGMTREES) pTreesHC;
2123 /** PGM offset based trees - GC Ptr. */
2124 RCPTRTYPE(PPGMTREES) pTreesGC;
2125
2126 /** Linked list of GC mappings - for GC.
2127 * The list is sorted ascending on address.
2128 */
2129 RCPTRTYPE(PPGMMAPPING) pMappingsGC;
2130 /** Linked list of GC mappings - for HC.
2131 * The list is sorted ascending on address.
2132 */
2133 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2134 /** Linked list of GC mappings - for R0.
2135 * The list is sorted ascending on address.
2136 */
2137 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2138
2139 /** If set no conflict checks are required. (boolean) */
2140 bool fMappingsFixed;
2141 /** If set, then no mappings are put into the shadow page table. (boolean) */
2142 bool fDisableMappings;
2143 /** Size of fixed mapping */
2144 uint32_t cbMappingFixed;
2145 /** Base address (GC) of fixed mapping */
2146 RTGCPTR GCPtrMappingFixed;
2147#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2148 uint32_t u32Padding0; /**< alignment padding. */
2149#endif
2150
2151
2152 /** @name Intermediate Context
2153 * @{ */
2154 /** Pointer to the intermediate page directory - Normal. */
2155 R3PTRTYPE(PX86PD) pInterPD;
2156 /** Pointer to the intermedate page tables - Normal.
2157 * There are two page tables, one for the identity mapping and one for
2158 * the host context mapping (of the core code). */
2159 R3PTRTYPE(PX86PT) apInterPTs[2];
2160 /** Pointer to the intermedate page tables - PAE. */
2161 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2162 /** Pointer to the intermedate page directory - PAE. */
2163 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2164 /** Pointer to the intermedate page directory - PAE. */
2165 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2166 /** Pointer to the intermedate page-map level 4 - AMD64. */
2167 R3PTRTYPE(PX86PML4) pInterPaePML4;
2168 /** Pointer to the intermedate page directory - AMD64. */
2169 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2170 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2171 RTHCPHYS HCPhysInterPD;
2172 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2173 RTHCPHYS HCPhysInterPaePDPT;
2174 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2175 RTHCPHYS HCPhysInterPaePML4;
2176 /** @} */
2177
2178 /** Base address of the dynamic page mapping area.
2179 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2180 */
2181 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2182 /** The index of the last entry used in the dynamic page mapping area. */
2183 RTUINT iDynPageMapLast;
2184 /** Cache containing the last entries in the dynamic page mapping area.
2185 * The cache size is covering half of the mapping area. */
2186 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2187
2188 /** A20 gate mask.
2189 * Our current approach to A20 emulation is to let REM do it and don't bother
2190 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2191 * But whould need arrise, we'll subject physical addresses to this mask. */
2192 RTGCPHYS GCPhysA20Mask;
2193 /** A20 gate state - boolean! */
2194 RTUINT fA20Enabled;
2195
2196 /** What needs syncing (PGM_SYNC_*).
2197 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2198 * PGMFlushTLB, and PGMR3Load. */
2199 RTUINT fSyncFlags;
2200
2201 /** PGM critical section.
2202 * This protects the physical & virtual access handlers, ram ranges,
2203 * and the page flag updating (some of it anyway).
2204 */
2205 PDMCRITSECT CritSect;
2206
2207 /** Shadow Page Pool - HC Ptr. */
2208 R3R0PTRTYPE(PPGMPOOL) pPoolHC;
2209 /** Shadow Page Pool - GC Ptr. */
2210 RCPTRTYPE(PPGMPOOL) pPoolGC;
2211
2212 /** We're not in a state which permits writes to guest memory.
2213 * (Only used in strict builds.) */
2214 bool fNoMorePhysWrites;
2215
2216 /** Flush the cache on the next access. */
2217 bool fPhysCacheFlushPending;
2218/** @todo r=bird: Fix member names!*/
2219 /** PGMPhysRead cache */
2220 PGMPHYSCACHE pgmphysreadcache;
2221 /** PGMPhysWrite cache */
2222 PGMPHYSCACHE pgmphyswritecache;
2223
2224 /**
2225 * Data associated with managing the ring-3 mappings of the allocation chunks.
2226 */
2227 struct
2228 {
2229 /** The chunk tree, ordered by chunk id. */
2230 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2231 /** The chunk mapping TLB. */
2232 PGMCHUNKR3MAPTLB Tlb;
2233 /** The number of mapped chunks. */
2234 uint32_t c;
2235 /** The maximum number of mapped chunks.
2236 * @cfgm PGM/MaxRing3Chunks */
2237 uint32_t cMax;
2238 /** The chunk age tree, ordered by ageing sequence number. */
2239 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2240 /** The current time. */
2241 uint32_t iNow;
2242 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2243 uint32_t AgeingCountdown;
2244 } ChunkR3Map;
2245
2246 /**
2247 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2248 */
2249 PGMPAGER3MAPTLB PhysTlbHC;
2250
2251 /** @name The zero page.
2252 * @{ */
2253 /** The host physical address of the zero page. */
2254 RTHCPHYS HCPhysZeroPg;
2255 /** The ring-3 mapping of the zero page. */
2256 RTR3PTR pvZeroPgR3;
2257 /** The ring-0 mapping of the zero page. */
2258 RTR0PTR pvZeroPgR0;
2259 /** The GC mapping of the zero page. */
2260 RTGCPTR pvZeroPgGC;
2261#if GC_ARCH_BITS != 32
2262 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2263#endif
2264 /** @}*/
2265
2266 /** The number of handy pages. */
2267 uint32_t cHandyPages;
2268 /**
2269 * Array of handy pages.
2270 *
2271 * This array is used in a two way communication between pgmPhysAllocPage
2272 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2273 * an intermediary.
2274 *
2275 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2276 * (The current size of 32 pages, means 128 KB of handy memory.)
2277 */
2278 GMMPAGEDESC aHandyPages[32];
2279
2280 /** @name Release Statistics
2281 * @{ */
2282 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2283 uint32_t cPrivatePages; /**< The number of private pages. */
2284 uint32_t cSharedPages; /**< The number of shared pages. */
2285 uint32_t cZeroPages; /**< The number of zero backed pages. */
2286 /** The number of times the guest has switched mode since last reset or statistics reset. */
2287 STAMCOUNTER cGuestModeChanges;
2288 /** @} */
2289
2290#ifdef VBOX_WITH_STATISTICS
2291 /** GC: Which statistic this \#PF should be attributed to. */
2292 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
2293 RTRCPTR padding0;
2294 /** HC: Which statistic this \#PF should be attributed to. */
2295 R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
2296 RTHCPTR padding1;
2297 STAMPROFILE StatGCTrap0e; /**< GC: PGMGCTrap0eHandler() profiling. */
2298 STAMPROFILE StatTrap0eCSAM; /**< Profiling of the Trap0eHandler body when the cause is CSAM. */
2299 STAMPROFILE StatTrap0eDirtyAndAccessedBits; /**< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2300 STAMPROFILE StatTrap0eGuestTrap; /**< Profiling of the Trap0eHandler body when the cause is a guest trap. */
2301 STAMPROFILE StatTrap0eHndPhys; /**< Profiling of the Trap0eHandler body when the cause is a physical handler. */
2302 STAMPROFILE StatTrap0eHndVirt; /**< Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2303 STAMPROFILE StatTrap0eHndUnhandled; /**< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2304 STAMPROFILE StatTrap0eMisc; /**< Profiling of the Trap0eHandler body when the cause is not known. */
2305 STAMPROFILE StatTrap0eOutOfSync; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2306 STAMPROFILE StatTrap0eOutOfSyncHndPhys; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2307 STAMPROFILE StatTrap0eOutOfSyncHndVirt; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2308 STAMPROFILE StatTrap0eOutOfSyncObsHnd; /**< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2309 STAMPROFILE StatTrap0eSyncPT; /**< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2310
2311 STAMCOUNTER StatTrap0eMapHandler; /**< Number of traps due to access handlers in mappings. */
2312 STAMCOUNTER StatGCTrap0eConflicts; /**< GC: The number of times \#PF was caused by an undetected conflict. */
2313
2314 STAMCOUNTER StatGCTrap0eUSNotPresentRead;
2315 STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
2316 STAMCOUNTER StatGCTrap0eUSWrite;
2317 STAMCOUNTER StatGCTrap0eUSReserved;
2318 STAMCOUNTER StatGCTrap0eUSNXE;
2319 STAMCOUNTER StatGCTrap0eUSRead;
2320
2321 STAMCOUNTER StatGCTrap0eSVNotPresentRead;
2322 STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
2323 STAMCOUNTER StatGCTrap0eSVWrite;
2324 STAMCOUNTER StatGCTrap0eSVReserved;
2325 STAMCOUNTER StatGCTrap0eSNXE;
2326
2327 STAMCOUNTER StatTrap0eWPEmulGC;
2328 STAMCOUNTER StatTrap0eWPEmulR3;
2329
2330 STAMCOUNTER StatGCTrap0eUnhandled;
2331 STAMCOUNTER StatGCTrap0eMap;
2332
2333 /** GC: PGMSyncPT() profiling. */
2334 STAMPROFILE StatGCSyncPT;
2335 /** GC: The number of times PGMSyncPT() needed to allocate page tables. */
2336 STAMCOUNTER StatGCSyncPTAlloc;
2337 /** GC: The number of times PGMSyncPT() detected conflicts. */
2338 STAMCOUNTER StatGCSyncPTConflict;
2339 /** GC: The number of times PGMSyncPT() failed. */
2340 STAMCOUNTER StatGCSyncPTFailed;
2341 /** GC: PGMGCInvalidatePage() profiling. */
2342 STAMPROFILE StatGCInvalidatePage;
2343 /** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
2344 STAMCOUNTER StatGCInvalidatePage4KBPages;
2345 /** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
2346 STAMCOUNTER StatGCInvalidatePage4MBPages;
2347 /** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
2348 STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
2349 /** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
2350 STAMCOUNTER StatGCInvalidatePagePDNAs;
2351 /** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
2352 STAMCOUNTER StatGCInvalidatePagePDNPs;
2353 /** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
2354 STAMCOUNTER StatGCInvalidatePagePDMappings;
2355 /** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2356 STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
2357 /** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2358 STAMCOUNTER StatGCInvalidatePageSkipped;
2359 /** GC: The number of times user page is out of sync was detected in GC. */
2360 STAMCOUNTER StatGCPageOutOfSyncUser;
2361 /** GC: The number of times supervisor page is out of sync was detected in GC. */
2362 STAMCOUNTER StatGCPageOutOfSyncSupervisor;
2363 /** GC: The number of dynamic page mapping cache hits */
2364 STAMCOUNTER StatDynMapCacheMisses;
2365 /** GC: The number of dynamic page mapping cache misses */
2366 STAMCOUNTER StatDynMapCacheHits;
2367 /** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
2368 STAMCOUNTER StatGCGuestCR3WriteHandled;
2369 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
2370 STAMCOUNTER StatGCGuestCR3WriteUnhandled;
2371 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
2372 STAMCOUNTER StatGCGuestCR3WriteConflict;
2373 /** GC: Number of out-of-sync handled pages. */
2374 STAMCOUNTER StatHandlersOutOfSync;
2375 /** GC: Number of traps due to physical access handlers. */
2376 STAMCOUNTER StatHandlersPhysical;
2377 /** GC: Number of traps due to virtual access handlers. */
2378 STAMCOUNTER StatHandlersVirtual;
2379 /** GC: Number of traps due to virtual access handlers found by physical address. */
2380 STAMCOUNTER StatHandlersVirtualByPhys;
2381 /** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2382 STAMCOUNTER StatHandlersVirtualUnmarked;
2383 /** GC: Number of traps due to access outside range of monitored page(s). */
2384 STAMCOUNTER StatHandlersUnhandled;
2385 /** GC: Number of traps due to access to invalid physical memory. */
2386 STAMCOUNTER StatHandlersInvalid;
2387
2388 /** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
2389 STAMCOUNTER StatGCGuestROMWriteHandled;
2390 /** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
2391 STAMCOUNTER StatGCGuestROMWriteUnhandled;
2392
2393 /** HC: PGMR3InvalidatePage() profiling. */
2394 STAMPROFILE StatHCInvalidatePage;
2395 /** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
2396 STAMCOUNTER StatHCInvalidatePage4KBPages;
2397 /** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
2398 STAMCOUNTER StatHCInvalidatePage4MBPages;
2399 /** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
2400 STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
2401 /** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
2402 STAMCOUNTER StatHCInvalidatePagePDNAs;
2403 /** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
2404 STAMCOUNTER StatHCInvalidatePagePDNPs;
2405 /** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
2406 STAMCOUNTER StatHCInvalidatePagePDMappings;
2407 /** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2408 STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
2409 /** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2410 STAMCOUNTER StatHCInvalidatePageSkipped;
2411 /** HC: PGMR3SyncPT() profiling. */
2412 STAMPROFILE StatHCSyncPT;
2413 /** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2414 STAMPROFILE StatHCResolveConflict;
2415 /** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2416 STAMCOUNTER StatHCDetectedConflicts;
2417 /** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2418 STAMCOUNTER StatHCGuestPDWrite;
2419 /** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2420 STAMCOUNTER StatHCGuestPDWriteConflict;
2421
2422 /** HC: The number of pages marked not present for accessed bit emulation. */
2423 STAMCOUNTER StatHCAccessedPage;
2424 /** HC: The number of pages marked read-only for dirty bit tracking. */
2425 STAMCOUNTER StatHCDirtyPage;
2426 /** HC: The number of pages marked read-only for dirty bit tracking. */
2427 STAMCOUNTER StatHCDirtyPageBig;
2428 /** HC: The number of traps generated for dirty bit tracking. */
2429 STAMCOUNTER StatHCDirtyPageTrap;
2430 /** HC: The number of pages already dirty or readonly. */
2431 STAMCOUNTER StatHCDirtyPageSkipped;
2432
2433 /** GC: The number of pages marked not present for accessed bit emulation. */
2434 STAMCOUNTER StatGCAccessedPage;
2435 /** GC: The number of pages marked read-only for dirty bit tracking. */
2436 STAMCOUNTER StatGCDirtyPage;
2437 /** GC: The number of pages marked read-only for dirty bit tracking. */
2438 STAMCOUNTER StatGCDirtyPageBig;
2439 /** GC: The number of traps generated for dirty bit tracking. */
2440 STAMCOUNTER StatGCDirtyPageTrap;
2441 /** GC: The number of pages already dirty or readonly. */
2442 STAMCOUNTER StatGCDirtyPageSkipped;
2443 /** GC: The number of pages marked dirty because of write accesses. */
2444 STAMCOUNTER StatGCDirtiedPage;
2445 /** GC: The number of pages already marked dirty because of write accesses. */
2446 STAMCOUNTER StatGCPageAlreadyDirty;
2447 /** GC: The number of real pages faults during dirty bit tracking. */
2448 STAMCOUNTER StatGCDirtyTrackRealPF;
2449
2450 /** GC: Profiling of the PGMTrackDirtyBit() body */
2451 STAMPROFILE StatGCDirtyBitTracking;
2452 /** HC: Profiling of the PGMTrackDirtyBit() body */
2453 STAMPROFILE StatHCDirtyBitTracking;
2454
2455 /** GC: Profiling of the PGMGstModifyPage() body */
2456 STAMPROFILE StatGCGstModifyPage;
2457 /** HC: Profiling of the PGMGstModifyPage() body */
2458 STAMPROFILE StatHCGstModifyPage;
2459
2460 /** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2461 STAMCOUNTER StatGCSyncPagePDNAs;
2462 /** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2463 STAMCOUNTER StatGCSyncPagePDOutOfSync;
2464 /** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2465 STAMCOUNTER StatHCSyncPagePDNAs;
2466 /** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2467 STAMCOUNTER StatHCSyncPagePDOutOfSync;
2468
2469 STAMCOUNTER StatSynPT4kGC;
2470 STAMCOUNTER StatSynPT4kHC;
2471 STAMCOUNTER StatSynPT4MGC;
2472 STAMCOUNTER StatSynPT4MHC;
2473
2474 /** Profiling of the PGMFlushTLB() body. */
2475 STAMPROFILE StatFlushTLB;
2476 /** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2477 STAMCOUNTER StatFlushTLBNewCR3;
2478 /** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2479 STAMCOUNTER StatFlushTLBNewCR3Global;
2480 /** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2481 STAMCOUNTER StatFlushTLBSameCR3;
2482 /** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2483 STAMCOUNTER StatFlushTLBSameCR3Global;
2484
2485 STAMPROFILE StatGCSyncCR3; /**< GC: PGMSyncCR3() profiling. */
2486 STAMPROFILE StatGCSyncCR3Handlers; /**< GC: Profiling of the PGMSyncCR3() update handler section. */
2487 STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /**< GC: Profiling of the virtual handler resets. */
2488 STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /**< GC: Profiling of the virtual handler updates. */
2489 STAMCOUNTER StatGCSyncCR3Global; /**< GC: The number of global CR3 syncs. */
2490 STAMCOUNTER StatGCSyncCR3NotGlobal; /**< GC: The number of non-global CR3 syncs. */
2491 STAMCOUNTER StatGCSyncCR3DstFreed; /**< GC: The number of times we've had to free a shadow entry. */
2492 STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /**< GC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2493 STAMCOUNTER StatGCSyncCR3DstNotPresent; /**< GC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2494 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /**< GC: The number of times a global page directory wasn't flushed. */
2495 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /**< GC: The number of times a page table with only global entries wasn't flushed. */
2496 STAMCOUNTER StatGCSyncCR3DstCacheHit; /**< GC: The number of times we got some kind of cache hit on a page table. */
2497
2498 STAMPROFILE StatHCSyncCR3; /**< HC: PGMSyncCR3() profiling. */
2499 STAMPROFILE StatHCSyncCR3Handlers; /**< HC: Profiling of the PGMSyncCR3() update handler section. */
2500 STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /**< HC: Profiling of the virtual handler resets. */
2501 STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /**< HC: Profiling of the virtual handler updates. */
2502 STAMCOUNTER StatHCSyncCR3Global; /**< HC: The number of global CR3 syncs. */
2503 STAMCOUNTER StatHCSyncCR3NotGlobal; /**< HC: The number of non-global CR3 syncs. */
2504 STAMCOUNTER StatHCSyncCR3DstFreed; /**< HC: The number of times we've had to free a shadow entry. */
2505 STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /**< HC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2506 STAMCOUNTER StatHCSyncCR3DstNotPresent; /**< HC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2507 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /**< HC: The number of times a global page directory wasn't flushed. */
2508 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /**< HC: The number of times a page table with only global entries wasn't flushed. */
2509 STAMCOUNTER StatHCSyncCR3DstCacheHit; /**< HC: The number of times we got some kind of cache hit on a page table. */
2510
2511 /** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2512 STAMPROFILE StatVirtHandleSearchByPhysGC;
2513 /** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2514 STAMPROFILE StatVirtHandleSearchByPhysHC;
2515 /** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2516 STAMCOUNTER StatHandlePhysicalReset;
2517
2518 STAMPROFILE StatCheckPageFault;
2519 STAMPROFILE StatLazySyncPT;
2520 STAMPROFILE StatMapping;
2521 STAMPROFILE StatOutOfSync;
2522 STAMPROFILE StatHandlers;
2523 STAMPROFILE StatEIPHandlers;
2524 STAMPROFILE StatHCPrefetch;
2525
2526# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2527 /** The number of first time shadowings. */
2528 STAMCOUNTER StatTrackVirgin;
2529 /** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2530 STAMCOUNTER StatTrackAliased;
2531 /** The number of times we're tracking using cRef2. */
2532 STAMCOUNTER StatTrackAliasedMany;
2533 /** The number of times we're hitting pages which has overflowed cRef2. */
2534 STAMCOUNTER StatTrackAliasedLots;
2535 /** The number of times the extent list grows to long. */
2536 STAMCOUNTER StatTrackOverflows;
2537 /** Profiling of SyncPageWorkerTrackDeref (expensive). */
2538 STAMPROFILE StatTrackDeref;
2539# endif
2540
2541 /** Ring-3/0 page mapper TLB hits. */
2542 STAMCOUNTER StatPageHCMapTlbHits;
2543 /** Ring-3/0 page mapper TLB misses. */
2544 STAMCOUNTER StatPageHCMapTlbMisses;
2545 /** Ring-3/0 chunk mapper TLB hits. */
2546 STAMCOUNTER StatChunkR3MapTlbHits;
2547 /** Ring-3/0 chunk mapper TLB misses. */
2548 STAMCOUNTER StatChunkR3MapTlbMisses;
2549 /** Times a shared page has been replaced by a private one. */
2550 STAMCOUNTER StatPageReplaceShared;
2551 /** Times the zero page has been replaced by a private one. */
2552 STAMCOUNTER StatPageReplaceZero;
2553 /** The number of times we've executed GMMR3AllocateHandyPages. */
2554 STAMCOUNTER StatPageHandyAllocs;
2555
2556 /** Allocated mbs of guest ram */
2557 STAMCOUNTER StatDynRamTotal;
2558 /** Nr of pgmr3PhysGrowRange calls. */
2559 STAMCOUNTER StatDynRamGrow;
2560
2561 STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2562 STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2563 STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2564#endif
2565} PGM, *PPGM;
2566
2567
2568/** @name PGM::fSyncFlags Flags
2569 * @{
2570 */
2571/** Updates the virtual access handler state bit in PGMPAGE. */
2572#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2573/** Always sync CR3. */
2574#define PGM_SYNC_ALWAYS RT_BIT(1)
2575/** Check monitoring on next CR3 (re)load and invalidate page. */
2576#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2577/** Clear the page pool (a light weight flush). */
2578#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2579/** @} */
2580
2581
2582__BEGIN_DECLS
2583
2584int pgmLock(PVM pVM);
2585void pgmUnlock(PVM pVM);
2586
2587PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2588PGMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2589
2590int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2591int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2592PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2593void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2594DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2595
2596void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2597int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2598DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2599#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2600void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2601#else
2602# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2603#endif
2604DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2605
2606
2607void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2608int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2609int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2610int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2611#ifdef IN_RING3
2612int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2613int pgmR3PhysRamReset(PVM pVM);
2614int pgmR3PhysRomReset(PVM pVM);
2615#ifndef VBOX_WITH_NEW_PHYS_CODE
2616int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2617#endif
2618
2619int pgmR3PoolInit(PVM pVM);
2620void pgmR3PoolRelocate(PVM pVM);
2621void pgmR3PoolReset(PVM pVM);
2622
2623#endif /* IN_RING3 */
2624#ifdef IN_GC
2625void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2626#endif
2627int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2628PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2629void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2630void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2631int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2632void pgmPoolFlushAll(PVM pVM);
2633void pgmPoolClearAll(PVM pVM);
2634void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2635void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2636int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2637PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2638void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2639void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2640uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2641void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2642#ifdef PGMPOOL_WITH_MONITORING
2643# ifdef IN_RING3
2644void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2645# else
2646void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2647# endif
2648int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2649void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2650void pgmPoolMonitorModifiedClearAll(PVM pVM);
2651int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2652int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2653#endif
2654
2655__END_DECLS
2656
2657
2658/**
2659 * Gets the PGMRAMRANGE structure for a guest page.
2660 *
2661 * @returns Pointer to the RAM range on success.
2662 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2663 *
2664 * @param pPGM PGM handle.
2665 * @param GCPhys The GC physical address.
2666 */
2667DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2668{
2669 /*
2670 * Optimize for the first range.
2671 */
2672 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2673 RTGCPHYS off = GCPhys - pRam->GCPhys;
2674 if (RT_UNLIKELY(off >= pRam->cb))
2675 {
2676 do
2677 {
2678 pRam = CTXALLSUFF(pRam->pNext);
2679 if (RT_UNLIKELY(!pRam))
2680 break;
2681 off = GCPhys - pRam->GCPhys;
2682 } while (off >= pRam->cb);
2683 }
2684 return pRam;
2685}
2686
2687
2688/**
2689 * Gets the PGMPAGE structure for a guest page.
2690 *
2691 * @returns Pointer to the page on success.
2692 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2693 *
2694 * @param pPGM PGM handle.
2695 * @param GCPhys The GC physical address.
2696 */
2697DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2698{
2699 /*
2700 * Optimize for the first range.
2701 */
2702 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2703 RTGCPHYS off = GCPhys - pRam->GCPhys;
2704 if (RT_UNLIKELY(off >= pRam->cb))
2705 {
2706 do
2707 {
2708 pRam = CTXALLSUFF(pRam->pNext);
2709 if (RT_UNLIKELY(!pRam))
2710 return NULL;
2711 off = GCPhys - pRam->GCPhys;
2712 } while (off >= pRam->cb);
2713 }
2714 return &pRam->aPages[off >> PAGE_SHIFT];
2715}
2716
2717
2718/**
2719 * Gets the PGMPAGE structure for a guest page.
2720 *
2721 * Old Phys code: Will make sure the page is present.
2722 *
2723 * @returns VBox status code.
2724 * @retval VINF_SUCCESS and a valid *ppPage on success.
2725 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2726 *
2727 * @param pPGM PGM handle.
2728 * @param GCPhys The GC physical address.
2729 * @param ppPage Where to store the page poitner on success.
2730 */
2731DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2732{
2733 /*
2734 * Optimize for the first range.
2735 */
2736 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2737 RTGCPHYS off = GCPhys - pRam->GCPhys;
2738 if (RT_UNLIKELY(off >= pRam->cb))
2739 {
2740 do
2741 {
2742 pRam = CTXALLSUFF(pRam->pNext);
2743 if (RT_UNLIKELY(!pRam))
2744 {
2745 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2746 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2747 }
2748 off = GCPhys - pRam->GCPhys;
2749 } while (off >= pRam->cb);
2750 }
2751 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2752#ifndef VBOX_WITH_NEW_PHYS_CODE
2753
2754 /*
2755 * Make sure it's present.
2756 */
2757 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2758 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2759 {
2760#ifdef IN_RING3
2761 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2762#else
2763 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2764#endif
2765 if (VBOX_FAILURE(rc))
2766 {
2767 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2768 return rc;
2769 }
2770 Assert(rc == VINF_SUCCESS);
2771 }
2772#endif
2773 return VINF_SUCCESS;
2774}
2775
2776
2777
2778
2779/**
2780 * Gets the PGMPAGE structure for a guest page.
2781 *
2782 * Old Phys code: Will make sure the page is present.
2783 *
2784 * @returns VBox status code.
2785 * @retval VINF_SUCCESS and a valid *ppPage on success.
2786 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2787 *
2788 * @param pPGM PGM handle.
2789 * @param GCPhys The GC physical address.
2790 * @param ppPage Where to store the page poitner on success.
2791 * @param ppRamHint Where to read and store the ram list hint.
2792 * The caller initializes this to NULL before the call.
2793 */
2794DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2795{
2796 RTGCPHYS off;
2797 PPGMRAMRANGE pRam = *ppRamHint;
2798 if ( !pRam
2799 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2800 {
2801 pRam = CTXALLSUFF(pPGM->pRamRanges);
2802 off = GCPhys - pRam->GCPhys;
2803 if (RT_UNLIKELY(off >= pRam->cb))
2804 {
2805 do
2806 {
2807 pRam = CTXALLSUFF(pRam->pNext);
2808 if (RT_UNLIKELY(!pRam))
2809 {
2810 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2811 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2812 }
2813 off = GCPhys - pRam->GCPhys;
2814 } while (off >= pRam->cb);
2815 }
2816 *ppRamHint = pRam;
2817 }
2818 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2819#ifndef VBOX_WITH_NEW_PHYS_CODE
2820
2821 /*
2822 * Make sure it's present.
2823 */
2824 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2825 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2826 {
2827#ifdef IN_RING3
2828 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2829#else
2830 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2831#endif
2832 if (VBOX_FAILURE(rc))
2833 {
2834 *ppPage = NULL; /* Shut up annoying smart ass. */
2835 return rc;
2836 }
2837 Assert(rc == VINF_SUCCESS);
2838 }
2839#endif
2840 return VINF_SUCCESS;
2841}
2842
2843
2844/**
2845 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2846 *
2847 * @returns Pointer to the page on success.
2848 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2849 *
2850 * @param pPGM PGM handle.
2851 * @param GCPhys The GC physical address.
2852 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
2853 */
2854DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2855{
2856 /*
2857 * Optimize for the first range.
2858 */
2859 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2860 RTGCPHYS off = GCPhys - pRam->GCPhys;
2861 if (RT_UNLIKELY(off >= pRam->cb))
2862 {
2863 do
2864 {
2865 pRam = CTXALLSUFF(pRam->pNext);
2866 if (RT_UNLIKELY(!pRam))
2867 return NULL;
2868 off = GCPhys - pRam->GCPhys;
2869 } while (off >= pRam->cb);
2870 }
2871 *ppRam = pRam;
2872 return &pRam->aPages[off >> PAGE_SHIFT];
2873}
2874
2875
2876
2877
2878/**
2879 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2880 *
2881 * @returns Pointer to the page on success.
2882 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2883 *
2884 * @param pPGM PGM handle.
2885 * @param GCPhys The GC physical address.
2886 * @param ppPage Where to store the pointer to the PGMPAGE structure.
2887 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2888 */
2889DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2890{
2891 /*
2892 * Optimize for the first range.
2893 */
2894 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2895 RTGCPHYS off = GCPhys - pRam->GCPhys;
2896 if (RT_UNLIKELY(off >= pRam->cb))
2897 {
2898 do
2899 {
2900 pRam = CTXALLSUFF(pRam->pNext);
2901 if (RT_UNLIKELY(!pRam))
2902 {
2903 *ppRam = NULL; /* Shut up silly GCC warnings. */
2904 *ppPage = NULL; /* ditto */
2905 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2906 }
2907 off = GCPhys - pRam->GCPhys;
2908 } while (off >= pRam->cb);
2909 }
2910 *ppRam = pRam;
2911 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2912#ifndef VBOX_WITH_NEW_PHYS_CODE
2913
2914 /*
2915 * Make sure it's present.
2916 */
2917 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2918 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2919 {
2920#ifdef IN_RING3
2921 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2922#else
2923 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2924#endif
2925 if (VBOX_FAILURE(rc))
2926 {
2927 *ppPage = NULL; /* Shut up silly GCC warnings. */
2928 *ppPage = NULL; /* ditto */
2929 return rc;
2930 }
2931 Assert(rc == VINF_SUCCESS);
2932
2933 }
2934#endif
2935 return VINF_SUCCESS;
2936}
2937
2938
2939/**
2940 * Convert GC Phys to HC Phys.
2941 *
2942 * @returns VBox status.
2943 * @param pPGM PGM handle.
2944 * @param GCPhys The GC physical address.
2945 * @param pHCPhys Where to store the corresponding HC physical address.
2946 *
2947 * @deprecated Doesn't deal with zero, shared or write monitored pages.
2948 * Avoid when writing new code!
2949 */
2950DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2951{
2952 PPGMPAGE pPage;
2953 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2954 if (VBOX_FAILURE(rc))
2955 return rc;
2956 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
2957 return VINF_SUCCESS;
2958}
2959
2960
2961#ifndef IN_GC
2962/**
2963 * Queries the Physical TLB entry for a physical guest page,
2964 * attemting to load the TLB entry if necessary.
2965 *
2966 * @returns VBox status code.
2967 * @retval VINF_SUCCESS on success
2968 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2969 * @param pPGM The PGM instance handle.
2970 * @param GCPhys The address of the guest page.
2971 * @param ppTlbe Where to store the pointer to the TLB entry.
2972 */
2973
2974DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
2975{
2976 int rc;
2977 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
2978 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
2979 {
2980 STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
2981 rc = VINF_SUCCESS;
2982 }
2983 else
2984 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
2985 *ppTlbe = pTlbe;
2986 return rc;
2987}
2988#endif /* !IN_GC */
2989
2990
2991#ifndef VBOX_WITH_NEW_PHYS_CODE
2992/**
2993 * Convert GC Phys to HC Virt.
2994 *
2995 * @returns VBox status.
2996 * @param pPGM PGM handle.
2997 * @param GCPhys The GC physical address.
2998 * @param pHCPtr Where to store the corresponding HC virtual address.
2999 *
3000 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
3001 */
3002DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3003{
3004 PPGMRAMRANGE pRam;
3005 PPGMPAGE pPage;
3006 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3007 if (VBOX_FAILURE(rc))
3008 {
3009 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3010 return rc;
3011 }
3012 RTGCPHYS off = GCPhys - pRam->GCPhys;
3013
3014 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3015 {
3016 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3017 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3018 return VINF_SUCCESS;
3019 }
3020 if (pRam->pvHC)
3021 {
3022 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3023 return VINF_SUCCESS;
3024 }
3025 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3026 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3027}
3028#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3029
3030
3031/**
3032 * Convert GC Phys to HC Virt.
3033 *
3034 * @returns VBox status.
3035 * @param PVM VM handle.
3036 * @param pRam Ram range
3037 * @param GCPhys The GC physical address.
3038 * @param pHCPtr Where to store the corresponding HC virtual address.
3039 *
3040 * @deprecated This will be eliminated. Don't use it.
3041 */
3042DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3043{
3044 RTGCPHYS off = GCPhys - pRam->GCPhys;
3045 Assert(off < pRam->cb);
3046
3047 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3048 {
3049 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3050 /* Physical chunk in dynamically allocated range not present? */
3051 if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
3052 {
3053#ifdef IN_RING3
3054 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3055#else
3056 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3057#endif
3058 if (rc != VINF_SUCCESS)
3059 {
3060 *pHCPtr = 0; /* GCC crap */
3061 return rc;
3062 }
3063 }
3064 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3065 return VINF_SUCCESS;
3066 }
3067 if (pRam->pvHC)
3068 {
3069 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3070 return VINF_SUCCESS;
3071 }
3072 *pHCPtr = 0; /* GCC crap */
3073 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3074}
3075
3076
3077/**
3078 * Convert GC Phys to HC Virt and HC Phys.
3079 *
3080 * @returns VBox status.
3081 * @param pPGM PGM handle.
3082 * @param GCPhys The GC physical address.
3083 * @param pHCPtr Where to store the corresponding HC virtual address.
3084 * @param pHCPhys Where to store the HC Physical address and its flags.
3085 *
3086 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3087 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3088 */
3089DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3090{
3091 PPGMRAMRANGE pRam;
3092 PPGMPAGE pPage;
3093 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3094 if (VBOX_FAILURE(rc))
3095 {
3096 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3097 *pHCPhys = 0; /* ditto */
3098 return rc;
3099 }
3100 RTGCPHYS off = GCPhys - pRam->GCPhys;
3101
3102 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3103 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3104 {
3105 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3106 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3107 return VINF_SUCCESS;
3108 }
3109 if (pRam->pvHC)
3110 {
3111 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3112 return VINF_SUCCESS;
3113 }
3114 *pHCPtr = 0;
3115 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3116}
3117
3118
3119/**
3120 * Clears flags associated with a RAM address.
3121 *
3122 * @returns VBox status code.
3123 * @param pPGM PGM handle.
3124 * @param GCPhys Guest context physical address.
3125 * @param fFlags fFlags to clear. (Bits 0-11.)
3126 */
3127DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3128{
3129 PPGMPAGE pPage;
3130 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3131 if (VBOX_FAILURE(rc))
3132 return rc;
3133
3134 fFlags &= ~X86_PTE_PAE_PG_MASK;
3135 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3136 return VINF_SUCCESS;
3137}
3138
3139
3140/**
3141 * Clears flags associated with a RAM address.
3142 *
3143 * @returns VBox status code.
3144 * @param pPGM PGM handle.
3145 * @param GCPhys Guest context physical address.
3146 * @param fFlags fFlags to clear. (Bits 0-11.)
3147 * @param ppRamHint Where to read and store the ram list hint.
3148 * The caller initializes this to NULL before the call.
3149 */
3150DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3151{
3152 PPGMPAGE pPage;
3153 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3154 if (VBOX_FAILURE(rc))
3155 return rc;
3156
3157 fFlags &= ~X86_PTE_PAE_PG_MASK;
3158 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3159 return VINF_SUCCESS;
3160}
3161
3162/**
3163 * Sets (bitwise OR) flags associated with a RAM address.
3164 *
3165 * @returns VBox status code.
3166 * @param pPGM PGM handle.
3167 * @param GCPhys Guest context physical address.
3168 * @param fFlags fFlags to set clear. (Bits 0-11.)
3169 */
3170DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3171{
3172 PPGMPAGE pPage;
3173 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3174 if (VBOX_FAILURE(rc))
3175 return rc;
3176
3177 fFlags &= ~X86_PTE_PAE_PG_MASK;
3178 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3179 return VINF_SUCCESS;
3180}
3181
3182
3183/**
3184 * Sets (bitwise OR) flags associated with a RAM address.
3185 *
3186 * @returns VBox status code.
3187 * @param pPGM PGM handle.
3188 * @param GCPhys Guest context physical address.
3189 * @param fFlags fFlags to set clear. (Bits 0-11.)
3190 * @param ppRamHint Where to read and store the ram list hint.
3191 * The caller initializes this to NULL before the call.
3192 */
3193DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3194{
3195 PPGMPAGE pPage;
3196 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3197 if (VBOX_FAILURE(rc))
3198 return rc;
3199
3200 fFlags &= ~X86_PTE_PAE_PG_MASK;
3201 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3202 return VINF_SUCCESS;
3203}
3204
3205
3206/**
3207 * Gets the page directory for the specified address.
3208 *
3209 * @returns Pointer to the page directory in question.
3210 * @returns NULL if the page directory is not present or on an invalid page.
3211 * @param pPGM Pointer to the PGM instance data.
3212 * @param GCPtr The address.
3213 */
3214DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3215{
3216 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3217 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3218 {
3219 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3220 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3221
3222 /* cache is out-of-sync. */
3223 PX86PDPAE pPD;
3224 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3225 if (VBOX_SUCCESS(rc))
3226 return pPD;
3227 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3228 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3229 }
3230 return NULL;
3231}
3232
3233
3234/**
3235 * Gets the page directory entry for the specified address.
3236 *
3237 * @returns Pointer to the page directory entry in question.
3238 * @returns NULL if the page directory is not present or on an invalid page.
3239 * @param pPGM Pointer to the PGM instance data.
3240 * @param GCPtr The address.
3241 */
3242DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3243{
3244 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3245 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3246 {
3247 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3248 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3249 return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3250
3251 /* The cache is out-of-sync. */
3252 PX86PDPAE pPD;
3253 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3254 if (VBOX_SUCCESS(rc))
3255 return &pPD->a[iPD];
3256 AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3257 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3258 }
3259 return NULL;
3260}
3261
3262
3263/**
3264 * Gets the page directory entry for the specified address.
3265 *
3266 * @returns The page directory entry in question.
3267 * @returns A non-present entry if the page directory is not present or on an invalid page.
3268 * @param pPGM Pointer to the PGM instance data.
3269 * @param GCPtr The address.
3270 */
3271DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3272{
3273 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3274 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3275 {
3276 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3277 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3278 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3279
3280 /* cache is out-of-sync. */
3281 PX86PDPAE pPD;
3282 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3283 if (VBOX_SUCCESS(rc))
3284 return pPD->a[iPD].u;
3285 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3286 }
3287 return 0ULL;
3288}
3289
3290
3291/**
3292 * Gets the page directory pointer table entry for the specified address
3293 * and returns the index into the page directory
3294 *
3295 * @returns Pointer to the page directory in question.
3296 * @returns NULL if the page directory is not present or on an invalid page.
3297 * @param pPGM Pointer to the PGM instance data.
3298 * @param GCPtr The address.
3299 * @param piPD Receives the index into the returned page directory
3300 */
3301DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3302{
3303 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3304 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3305 {
3306 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3307 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3308 {
3309 *piPD = iPD;
3310 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3311 }
3312
3313 /* cache is out-of-sync. */
3314 PX86PDPAE pPD;
3315 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3316 if (VBOX_SUCCESS(rc))
3317 {
3318 *piPD = iPD;
3319 return pPD;
3320 }
3321 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3322 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3323 }
3324 return NULL;
3325}
3326
3327#ifndef IN_GC
3328/**
3329 * Gets the page directory pointer entry for the specified address.
3330 *
3331 * @returns Pointer to the page directory pointer entry in question.
3332 * @returns NULL if the page directory is not present or on an invalid page.
3333 * @param pPGM Pointer to the PGM instance data.
3334 * @param GCPtr The address.
3335 * @param ppPml4e Page Map Level-4 Entry (out)
3336 */
3337DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e)
3338{
3339 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3340
3341 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3342 if ((*ppPml4e)->n.u1Present)
3343 {
3344 PX86PDPT pPdpt;
3345 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdpt);
3346 if (VBOX_FAILURE(rc))
3347 {
3348 AssertFailed();
3349 return NULL;
3350 }
3351 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3352 return &pPdpt->a[iPdPt];
3353 }
3354 return NULL;
3355}
3356
3357/**
3358 * Gets the page directory entry for the specified address.
3359 *
3360 * @returns The page directory entry in question.
3361 * @returns A non-present entry if the page directory is not present or on an invalid page.
3362 * @param pPGM Pointer to the PGM instance data.
3363 * @param GCPtr The address.
3364 * @param ppPml4e Page Map Level-4 Entry (out)
3365 * @param pPdpe Page directory pointer table entry (out)
3366 */
3367DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3368{
3369 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3370
3371 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3372 if ((*ppPml4e)->n.u1Present)
3373 {
3374 PX86PDPT pPdptTemp;
3375 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3376 if (VBOX_FAILURE(rc))
3377 {
3378 AssertFailed();
3379 return 0ULL;
3380 }
3381
3382 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3383 *pPdpe = pPdptTemp->a[iPdPt];
3384 if (pPdpe->n.u1Present)
3385 {
3386 PX86PDPAE pPD;
3387
3388 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3389 if (VBOX_FAILURE(rc))
3390 {
3391 AssertFailed();
3392 return 0ULL;
3393 }
3394 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3395 return pPD->a[iPD].u;
3396 }
3397 }
3398 return 0ULL;
3399}
3400
3401/**
3402 * Gets the page directory entry for the specified address.
3403 *
3404 * @returns The page directory entry in question.
3405 * @returns A non-present entry if the page directory is not present or on an invalid page.
3406 * @param pPGM Pointer to the PGM instance data.
3407 * @param GCPtr The address.
3408 */
3409DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3410{
3411 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3412
3413 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3414 {
3415 PX86PDPT pPdptTemp;
3416 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3417 if (VBOX_FAILURE(rc))
3418 {
3419 AssertFailed();
3420 return 0ULL;
3421 }
3422
3423 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3424 if (pPdptTemp->a[iPdPt].n.u1Present)
3425 {
3426 PX86PDPAE pPD;
3427
3428 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3429 if (VBOX_FAILURE(rc))
3430 {
3431 AssertFailed();
3432 return 0ULL;
3433 }
3434 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3435 return pPD->a[iPD].u;
3436 }
3437 }
3438 return 0ULL;
3439}
3440
3441/**
3442 * Gets the page directory entry for the specified address.
3443 *
3444 * @returns Pointer to the page directory entry in question.
3445 * @returns NULL if the page directory is not present or on an invalid page.
3446 * @param pPGM Pointer to the PGM instance data.
3447 * @param GCPtr The address.
3448 */
3449DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3450{
3451 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3452
3453 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3454 {
3455 PX86PDPT pPdptTemp;
3456 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3457 if (VBOX_FAILURE(rc))
3458 {
3459 AssertFailed();
3460 return NULL;
3461 }
3462
3463 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3464 if (pPdptTemp->a[iPdPt].n.u1Present)
3465 {
3466 PX86PDPAE pPD;
3467
3468 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3469 if (VBOX_FAILURE(rc))
3470 {
3471 AssertFailed();
3472 return NULL;
3473 }
3474 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3475 return &pPD->a[iPD];
3476 }
3477 }
3478 return NULL;
3479}
3480
3481
3482/**
3483 * Gets the GUEST page directory pointer for the specified address.
3484 *
3485 * @returns The page directory in question.
3486 * @returns NULL if the page directory is not present or on an invalid page.
3487 * @param pPGM Pointer to the PGM instance data.
3488 * @param GCPtr The address.
3489 * @param ppPml4e Page Map Level-4 Entry (out)
3490 * @param pPdpe Page directory pointer table entry (out)
3491 * @param piPD Receives the index into the returned page directory
3492 */
3493DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
3494{
3495 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3496
3497 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3498 if ((*ppPml4e)->n.u1Present)
3499 {
3500 PX86PDPT pPdptTemp;
3501 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3502 if (VBOX_FAILURE(rc))
3503 {
3504 AssertFailed();
3505 return 0ULL;
3506 }
3507
3508 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3509 *pPdpe = pPdptTemp->a[iPdPt];
3510 if (pPdpe->n.u1Present)
3511 {
3512 PX86PDPAE pPD;
3513
3514 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3515 if (VBOX_FAILURE(rc))
3516 {
3517 AssertFailed();
3518 return 0ULL;
3519 }
3520 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3521 return pPD;
3522 }
3523 }
3524 return 0ULL;
3525}
3526
3527/**
3528 * Gets the GUEST page directory pointer for the specified address.
3529 *
3530 * @returns The page directory in question.
3531 * @returns NULL if the page directory is not present or on an invalid page.
3532 * @param pPGM Pointer to the PGM instance data.
3533 * @param GCPtr The address.
3534 * @param piPD Receives the index into the returned page directory
3535 */
3536DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, unsigned *piPD)
3537{
3538 PX86PML4E pPml4e;
3539 PX86PDPE pPdpe;
3540 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3541
3542 pPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3543 if (pPml4e->n.u1Present)
3544 {
3545 PX86PDPT pPdptTemp;
3546 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3547 if (VBOX_FAILURE(rc))
3548 {
3549 AssertFailed();
3550 return 0ULL;
3551 }
3552
3553 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3554 pPdpe = &pPdptTemp->a[iPdPt];
3555 if (pPdpe->n.u1Present)
3556 {
3557 PX86PDPAE pPD;
3558
3559 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3560 if (VBOX_FAILURE(rc))
3561 {
3562 AssertFailed();
3563 return 0ULL;
3564 }
3565 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3566 return pPD;
3567 }
3568 }
3569 return 0ULL;
3570}
3571
3572#endif /* !IN_GC */
3573
3574/**
3575 * Checks if any of the specified page flags are set for the given page.
3576 *
3577 * @returns true if any of the flags are set.
3578 * @returns false if all the flags are clear.
3579 * @param pPGM PGM handle.
3580 * @param GCPhys The GC physical address.
3581 * @param fFlags The flags to check for.
3582 */
3583DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3584{
3585 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3586 return pPage
3587 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3588}
3589
3590
3591/**
3592 * Gets the page state for a physical handler.
3593 *
3594 * @returns The physical handler page state.
3595 * @param pCur The physical handler in question.
3596 */
3597DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3598{
3599 switch (pCur->enmType)
3600 {
3601 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3602 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3603
3604 case PGMPHYSHANDLERTYPE_MMIO:
3605 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3606 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3607
3608 default:
3609 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3610 }
3611}
3612
3613
3614/**
3615 * Gets the page state for a virtual handler.
3616 *
3617 * @returns The virtual handler page state.
3618 * @param pCur The virtual handler in question.
3619 * @remarks This should never be used on a hypervisor access handler.
3620 */
3621DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3622{
3623 switch (pCur->enmType)
3624 {
3625 case PGMVIRTHANDLERTYPE_WRITE:
3626 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3627 case PGMVIRTHANDLERTYPE_ALL:
3628 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3629 default:
3630 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3631 }
3632}
3633
3634
3635/**
3636 * Clears one physical page of a virtual handler
3637 *
3638 * @param pPGM Pointer to the PGM instance.
3639 * @param pCur Virtual handler structure
3640 * @param iPage Physical page index
3641 *
3642 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3643 * need to care about other handlers in the same page.
3644 */
3645DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3646{
3647 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3648
3649 /*
3650 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
3651 */
3652#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3653 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3654 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3655 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3656#endif
3657 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3658 {
3659 /* We're the head of the alias chain. */
3660 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3661#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3662 AssertReleaseMsg(pRemove != NULL,
3663 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3664 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3665 AssertReleaseMsg(pRemove == pPhys2Virt,
3666 ("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3667 " got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3668 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3669 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3670#endif
3671 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3672 {
3673 /* Insert the next list in the alias chain into the tree. */
3674 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3675#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3676 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3677 ("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3678 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3679#endif
3680 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
3681 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3682 AssertRelease(fRc);
3683 }
3684 }
3685 else
3686 {
3687 /* Locate the previous node in the alias chain. */
3688 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3689#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3690 AssertReleaseMsg(pPrev != pPhys2Virt,
3691 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3692 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3693#endif
3694 for (;;)
3695 {
3696 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3697 if (pNext == pPhys2Virt)
3698 {
3699 /* unlink. */
3700 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3701 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3702 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3703 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3704 else
3705 {
3706 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3707 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3708 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3709 }
3710 break;
3711 }
3712
3713 /* next */
3714 if (pNext == pPrev)
3715 {
3716#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3717 AssertReleaseMsg(pNext != pPrev,
3718 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3719 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3720#endif
3721 break;
3722 }
3723 pPrev = pNext;
3724 }
3725 }
3726 Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3727 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3728 pPhys2Virt->offNextAlias = 0;
3729 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3730
3731 /*
3732 * Clear the ram flags for this page.
3733 */
3734 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3735 AssertReturnVoid(pPage);
3736 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3737}
3738
3739
3740/**
3741 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3742 *
3743 * @returns Pointer to the shadow page structure.
3744 * @param pPool The pool.
3745 * @param HCPhys The HC physical address of the shadow page.
3746 */
3747DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3748{
3749 /*
3750 * Look up the page.
3751 */
3752 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3753 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3754 return pPage;
3755}
3756
3757
3758/**
3759 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3760 *
3761 * @returns Pointer to the shadow page structure.
3762 * @param pPool The pool.
3763 * @param idx The pool page index.
3764 */
3765DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3766{
3767 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3768 return &pPool->aPages[idx];
3769}
3770
3771
3772#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3773/**
3774 * Clear references to guest physical memory.
3775 *
3776 * @param pPool The pool.
3777 * @param pPoolPage The pool page.
3778 * @param pPhysPage The physical guest page tracking structure.
3779 */
3780DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3781{
3782 /*
3783 * Just deal with the simple case here.
3784 */
3785#ifdef LOG_ENABLED
3786 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3787#endif
3788 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3789 if (cRefs == 1)
3790 {
3791 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3792 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3793 }
3794 else
3795 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3796 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3797}
3798#endif
3799
3800
3801#ifdef PGMPOOL_WITH_CACHE
3802/**
3803 * Moves the page to the head of the age list.
3804 *
3805 * This is done when the cached page is used in one way or another.
3806 *
3807 * @param pPool The pool.
3808 * @param pPage The cached page.
3809 * @todo inline in PGMInternal.h!
3810 */
3811DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3812{
3813 /*
3814 * Move to the head of the age list.
3815 */
3816 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3817 {
3818 /* unlink */
3819 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3820 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3821 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3822 else
3823 pPool->iAgeTail = pPage->iAgePrev;
3824
3825 /* insert at head */
3826 pPage->iAgePrev = NIL_PGMPOOL_IDX;
3827 pPage->iAgeNext = pPool->iAgeHead;
3828 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3829 pPool->iAgeHead = pPage->idx;
3830 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3831 }
3832}
3833#endif /* PGMPOOL_WITH_CACHE */
3834
3835/**
3836 * Tells if mappings are to be put into the shadow page table or not
3837 *
3838 * @returns boolean result
3839 * @param pVM VM handle.
3840 */
3841
3842DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3843{
3844#ifdef IN_RING0
3845 /* There are no mappings in VT-x and AMD-V mode. */
3846 Assert(pPGM->fDisableMappings);
3847 return false;
3848#else
3849 return !pPGM->fDisableMappings;
3850#endif
3851}
3852
3853/** @} */
3854
3855#endif
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