PGMMap.cpp@ 11311

Last change on this file since 11311 was 11311, checked in by vboxsync, 16 years ago
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1	/* $Id: PGMMap.cpp 11311 2008-08-08 23:31:54Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager, Guest Context Mappings.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/dbgf.h>
28	#include <VBox/pgm.h>
29	#include "PGMInternal.h"
30	#include <VBox/vm.h>
31
32	#include <VBox/log.h>
33	#include <VBox/err.h>
34	#include <iprt/asm.h>
35	#include <iprt/assert.h>
36	#include <iprt/string.h>
37
38
39	/*******************************************************************************
40	* Internal Functions *
41	*******************************************************************************/
42	static void pgmR3MapClearPDEs(PPGM pPGM, PPGMMAPPING pMap, unsigned iOldPDE);
43	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
44	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
45	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
46
47
48
49	/**
50	* Creates a page table based mapping in GC.
51	*
52	* @returns VBox status code.
53	* @param pVM VM Handle.
54	* @param GCPtr Virtual Address. (Page table aligned!)
55	* @param cb Size of the range. Must be a 4MB aligned!
56	* @param pfnRelocate Relocation callback function.
57	* @param pvUser User argument to the callback.
58	* @param pszDesc Pointer to description string. This must not be freed.
59	*/
60	PGMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc)
61	{
62	LogFlow(("PGMR3MapPT: GCPtr=%#x cb=%d pfnRelocate=%p pvUser=%p pszDesc=%s\n", GCPtr, cb, pfnRelocate, pvUser, pszDesc));
63	AssertMsg(pVM->pgm.s.pInterPD && pVM->pgm.s.pHC32BitPD, ("Paging isn't initialized, init order problems!\n"));
64
65	/*
66	* Validate input.
67	*/
68	if (cb < _2M \|\| cb > 64 * _1M)
69	{
70	AssertMsgFailed(("Serious? cb=%d\n", cb));
71	return VERR_INVALID_PARAMETER;
72	}
73	cb = RT_ALIGN_32(cb, _4M);
74	RTGCPTR GCPtrLast = GCPtr + cb - 1;
75	if (GCPtrLast < GCPtr)
76	{
77	AssertMsgFailed(("Range wraps! GCPtr=%x GCPtrLast=%x\n", GCPtr, GCPtrLast));
78	return VERR_INVALID_PARAMETER;
79	}
80	if (pVM->pgm.s.fMappingsFixed)
81	{
82	AssertMsgFailed(("Mappings are fixed! It's not possible to add new mappings at this time!\n"));
83	return VERR_PGM_MAPPINGS_FIXED;
84	}
85	if (!pfnRelocate)
86	{
87	AssertMsgFailed(("Callback is required\n"));
88	return VERR_INVALID_PARAMETER;
89	}
90
91	/*
92	* Find list location.
93	*/
94	PPGMMAPPING pPrev = NULL;
95	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
96	while (pCur)
97	{
98	if (pCur->GCPtrLast >= GCPtr && pCur->GCPtr <= GCPtrLast)
99	{
100	AssertMsgFailed(("Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
101	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
102	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
103	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
104	return VERR_PGM_MAPPING_CONFLICT;
105	}
106	if (pCur->GCPtr > GCPtr)
107	break;
108	pPrev = pCur;
109	pCur = pCur->pNextR3;
110	}
111
112	/*
113	* Check for conflicts with intermediate mappings.
114	*/
115	const unsigned iPageDir = GCPtr >> X86_PD_SHIFT;
116	const unsigned cPTs = cb >> X86_PD_SHIFT;
117	unsigned i;
118	for (i = 0; i < cPTs; i++)
119	{
120	if (pVM->pgm.s.pInterPD->a[iPageDir + i].n.u1Present)
121	{
122	AssertMsgFailed(("Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
123	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
124	return VERR_PGM_MAPPING_CONFLICT;
125	}
126	}
127	/** @todo AMD64: add check in PAE structures too, so we can remove all the 32-Bit paging stuff there. */
128
129	/*
130	* Allocate and initialize the new list node.
131	*/
132	PPGMMAPPING pNew;
133	int rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMMAPPING, aPTs[cPTs]), 0, MM_TAG_PGM, (void **)&pNew);
134	if (VBOX_FAILURE(rc))
135	return rc;
136	pNew->GCPtr = GCPtr;
137	pNew->GCPtrLast = GCPtrLast;
138	pNew->cb = cb;
139	pNew->pszDesc = pszDesc;
140	pNew->pfnRelocate = pfnRelocate;
141	pNew->pvUser = pvUser;
142	pNew->cPTs = cPTs;
143
144	/*
145	* Allocate page tables and insert them into the page directories.
146	* (One 32-bit PT and two PAE PTs.)
147	*/
148	uint8_t *pbPTs;
149	rc = MMHyperAlloc(pVM, PAGE_SIZE * 3 * cPTs, PAGE_SIZE, MM_TAG_PGM, (void **)&pbPTs);
150	if (VBOX_FAILURE(rc))
151	{
152	MMHyperFree(pVM, pNew);
153	return VERR_NO_MEMORY;
154	}
155
156	/*
157	* Init the page tables and insert them into the page directories.
158	*/
159	Log4(("PGMR3MapPT: GCPtr=%VGv cPTs=%u pbPTs=%p\n", GCPtr, cPTs, pbPTs));
160	for (i = 0; i < cPTs; i++)
161	{
162	/*
163	* 32-bit.
164	*/
165	pNew->aPTs[i].pPTR3 = (PX86PT)pbPTs;
166	pNew->aPTs[i].pPTGC = MMHyperR3ToRC(pVM, pNew->aPTs[i].pPTR3);
167	pNew->aPTs[i].pPTR0 = MMHyperR3ToR0(pVM, pNew->aPTs[i].pPTR3);
168	pNew->aPTs[i].HCPhysPT = MMR3HyperHCVirt2HCPhys(pVM, pNew->aPTs[i].pPTR3);
169	pbPTs += PAGE_SIZE;
170	Log4(("PGMR3MapPT: i=%d: pPTHC=%p pPTGC=%p HCPhysPT=%RHp\n",
171	i, pNew->aPTs[i].pPTR3, pNew->aPTs[i].pPTGC, pNew->aPTs[i].HCPhysPT));
172
173	/*
174	* PAE.
175	*/
176	pNew->aPTs[i].HCPhysPaePT0 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs);
177	pNew->aPTs[i].HCPhysPaePT1 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs + PAGE_SIZE);
178	pNew->aPTs[i].paPaePTsR3 = (PX86PTPAE)pbPTs;
179	pNew->aPTs[i].paPaePTsGC = MMHyperR3ToRC(pVM, pbPTs);
180	pNew->aPTs[i].paPaePTsR0 = MMHyperR3ToR0(pVM, pbPTs);
181	pbPTs += PAGE_SIZE * 2;
182	Log4(("PGMR3MapPT: i=%d: paPaePTsHC=%p paPaePTsGC=%p HCPhysPaePT0=%RHp HCPhysPaePT1=%RHp\n",
183	i, pNew->aPTs[i].paPaePTsR3, pNew->aPTs[i].paPaePTsGC, pNew->aPTs[i].HCPhysPaePT0, pNew->aPTs[i].HCPhysPaePT1));
184	}
185	pgmR3MapSetPDEs(pVM, pNew, iPageDir);
186
187	/*
188	* Insert the new mapping.
189	*/
190	pNew->pNextR3 = pCur;
191	pNew->pNextGC = pCur ? MMHyperR3ToRC(pVM, pCur) : 0;
192	pNew->pNextR0 = pCur ? MMHyperR3ToR0(pVM, pCur) : 0;
193	if (pPrev)
194	{
195	pPrev->pNextR3 = pNew;
196	pPrev->pNextGC = MMHyperR3ToRC(pVM, pNew);
197	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pNew);
198	}
199	else
200	{
201	pVM->pgm.s.pMappingsR3 = pNew;
202	pVM->pgm.s.pMappingsGC = MMHyperR3ToRC(pVM, pNew);
203	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pNew);
204	}
205
206	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
207	return VINF_SUCCESS;
208	}
209
210
211	/**
212	* Removes a page table based mapping.
213	*
214	* @returns VBox status code.
215	* @param pVM VM Handle.
216	* @param GCPtr Virtual Address. (Page table aligned!)
217	*/
218	PGMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr)
219	{
220	LogFlow(("PGMR3UnmapPT: GCPtr=%#x\n", GCPtr));
221
222	/*
223	* Find it.
224	*/
225	PPGMMAPPING pPrev = NULL;
226	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
227	while (pCur)
228	{
229	if (pCur->GCPtr == GCPtr)
230	{
231	/*
232	* Unlink it.
233	*/
234	if (pPrev)
235	{
236	pPrev->pNextR3 = pCur->pNextR3;
237	pPrev->pNextGC = pCur->pNextGC;
238	pPrev->pNextR0 = pCur->pNextR0;
239	}
240	else
241	{
242	pVM->pgm.s.pMappingsR3 = pCur->pNextR3;
243	pVM->pgm.s.pMappingsGC = pCur->pNextGC;
244	pVM->pgm.s.pMappingsR0 = pCur->pNextR0;
245	}
246
247	/*
248	* Free the page table memory, clear page directory entries
249	* and free the page tables and node memory.
250	*/
251	MMHyperFree(pVM, pCur->aPTs[0].pPTR3);
252	pgmR3MapClearPDEs(&pVM->pgm.s, pCur, pCur->GCPtr >> X86_PD_SHIFT);
253	MMHyperFree(pVM, pCur);
254
255	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
256	return VINF_SUCCESS;
257	}
258
259	/* done? */
260	if (pCur->GCPtr > GCPtr)
261	break;
262
263	/* next */
264	pPrev = pCur;
265	pCur = pCur->pNextR3;
266	}
267
268	AssertMsgFailed(("No mapping for %#x found!\n", GCPtr));
269	return VERR_INVALID_PARAMETER;
270	}
271
272
273	/**
274	* Gets the size of the current guest mappings if they were to be
275	* put next to oneanother.
276	*
277	* @returns VBox status code.
278	* @param pVM The VM.
279	* @param pcb Where to store the size.
280	*/
281	PGMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb)
282	{
283	RTGCUINTPTR cb = 0;
284	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
285	cb += pCur->cb;
286
287	*pcb = cb;
288	AssertReturn(*pcb == cb, VERR_NUMBER_TOO_BIG);
289	Log(("PGMR3MappingsSize: return %d (%#x) bytes\n", cb, cb));
290	return VINF_SUCCESS;
291	}
292
293
294	/**
295	* Fixes the guest context mappings in a range reserved from the Guest OS.
296	*
297	* @returns VBox status code.
298	* @param pVM The VM.
299	* @param GCPtrBase The address of the reserved range of guest memory.
300	* @param cb The size of the range starting at GCPtrBase.
301	*/
302	PGMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb)
303	{
304	Log(("PGMR3MappingsFix: GCPtrBase=%#x cb=%#x\n", GCPtrBase, cb));
305
306	/*
307	* This is all or nothing at all. So, a tiny bit of paranoia first.
308	*/
309	if (GCPtrBase & X86_PAGE_4M_OFFSET_MASK)
310	{
311	AssertMsgFailed(("GCPtrBase (%#x) has to be aligned on a 4MB address!\n", GCPtrBase));
312	return VERR_INVALID_PARAMETER;
313	}
314	if (!cb \|\| (cb & X86_PAGE_4M_OFFSET_MASK))
315	{
316	AssertMsgFailed(("cb (%#x) is 0 or not aligned on a 4MB address!\n", cb));
317	return VERR_INVALID_PARAMETER;
318	}
319
320	/*
321	* Before we do anything we'll do a forced PD sync to try make sure any
322	* pending relocations because of these mappings have been resolved.
323	*/
324	PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), true);
325
326	/*
327	* Check that it's not conflicting with a core code mapping in the intermediate page table.
328	*/
329	unsigned iPDNew = GCPtrBase >> X86_PD_SHIFT;
330	unsigned i = cb >> X86_PD_SHIFT;
331	while (i-- > 0)
332	{
333	if (pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present)
334	{
335	/* Check that it's not one or our mappings. */
336	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
337	while (pCur)
338	{
339	if (iPDNew + i - (pCur->GCPtr >> X86_PD_SHIFT) < (pCur->cb >> X86_PD_SHIFT))
340	break;
341	pCur = pCur->pNextR3;
342	}
343	if (!pCur)
344	{
345	LogRel(("PGMR3MappingsFix: Conflicts with intermediate PDE %#x (GCPtrBase=%VGv cb=%#zx). The guest should retry.\n",
346	iPDNew + i, GCPtrBase, cb));
347	return VERR_PGM_MAPPINGS_FIX_CONFLICT;
348	}
349	}
350	}
351
352	/*
353	* Loop the mappings and check that they all agree on their new locations.
354	*/
355	RTGCPTR GCPtrCur = GCPtrBase;
356	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
357	while (pCur)
358	{
359	if (!pCur->pfnRelocate(pVM, pCur->GCPtr, GCPtrCur, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
360	{
361	AssertMsgFailed(("The suggested fixed address %#x was rejected by '%s'!\n", GCPtrCur, pCur->pszDesc));
362	return VERR_PGM_MAPPINGS_FIX_REJECTED;
363	}
364	/* next */
365	GCPtrCur += pCur->cb;
366	pCur = pCur->pNextR3;
367	}
368	if (GCPtrCur > GCPtrBase + cb)
369	{
370	AssertMsgFailed(("cb (%#x) is less than the required range %#x!\n", cb, GCPtrCur - GCPtrBase));
371	return VERR_PGM_MAPPINGS_FIX_TOO_SMALL;
372	}
373
374	/*
375	* Loop the table assigning the mappings to the passed in memory
376	* and call their relocator callback.
377	*/
378	GCPtrCur = GCPtrBase;
379	pCur = pVM->pgm.s.pMappingsR3;
380	while (pCur)
381	{
382	unsigned iPDOld = pCur->GCPtr >> X86_PD_SHIFT;
383	iPDNew = GCPtrCur >> X86_PD_SHIFT;
384
385	/*
386	* Relocate the page table(s).
387	*/
388	pgmR3MapClearPDEs(&pVM->pgm.s, pCur, iPDOld);
389	pgmR3MapSetPDEs(pVM, pCur, iPDNew);
390
391	/*
392	* Update the entry.
393	*/
394	pCur->GCPtr = GCPtrCur;
395	pCur->GCPtrLast = GCPtrCur + pCur->cb - 1;
396
397	/*
398	* Callback to execute the relocation.
399	*/
400	pCur->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pCur->pvUser);
401
402	/*
403	* Advance.
404	*/
405	GCPtrCur += pCur->cb;
406	pCur = pCur->pNextR3;
407	}
408
409	/*
410	* Turn off CR3 updating monitoring.
411	*/
412	int rc2 = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
413	AssertRC(rc2);
414
415	/*
416	* Mark the mappings as fixed and return.
417	*/
418	pVM->pgm.s.fMappingsFixed = true;
419	pVM->pgm.s.GCPtrMappingFixed = GCPtrBase;
420	pVM->pgm.s.cbMappingFixed = cb;
421	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
422	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
423	return VINF_SUCCESS;
424	}
425
426
427	/**
428	* Unfixes the mappings.
429	* After calling this function mapping conflict detection will be enabled.
430	*
431	* @returns VBox status code.
432	* @param pVM The VM.
433	*/
434	PGMR3DECL(int) PGMR3MappingsUnfix(PVM pVM)
435	{
436	Log(("PGMR3MappingsUnfix: fMappingsFixed=%d\n", pVM->pgm.s.fMappingsFixed));
437	pVM->pgm.s.fMappingsFixed = false;
438	pVM->pgm.s.GCPtrMappingFixed = 0;
439	pVM->pgm.s.cbMappingFixed = 0;
440	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
441
442	/*
443	* Re-enable the CR3 monitoring.
444	*
445	* Paranoia: We flush the page pool before doing that because Windows
446	* is using the CR3 page both as a PD and a PT, e.g. the pool may
447	* be monitoring it.
448	*/
449	#ifdef PGMPOOL_WITH_MONITORING
450	pgmPoolFlushAll(pVM);
451	#endif
452	int rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
453	AssertRC(rc);
454
455	return VINF_SUCCESS;
456	}
457
458
459	/**
460	* Map pages into the intermediate context (switcher code).
461	* These pages are mapped at both the give virtual address and at
462	* the physical address (for identity mapping).
463	*
464	* @returns VBox status code.
465	* @param pVM The virtual machine.
466	* @param Addr Intermediate context address of the mapping.
467	* @param HCPhys Start of the range of physical pages. This must be entriely below 4GB!
468	* @param cbPages Number of bytes to map.
469	*
470	* @remark This API shall not be used to anything but mapping the switcher code.
471	*/
472	PGMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages)
473	{
474	LogFlow(("PGMR3MapIntermediate: Addr=%RTptr HCPhys=%VHp cbPages=%#x\n", Addr, HCPhys, cbPages));
475
476	/*
477	* Adjust input.
478	*/
479	cbPages += (uint32_t)HCPhys & PAGE_OFFSET_MASK;
480	cbPages = RT_ALIGN(cbPages, PAGE_SIZE);
481	HCPhys &= X86_PTE_PAE_PG_MASK;
482	Addr &= PAGE_BASE_MASK;
483	/* We only care about the first 4GB, because on AMD64 we'll be repeating them all over the address space. */
484	uint32_t uAddress = (uint32_t)Addr;
485
486	/*
487	* Assert input and state.
488	*/
489	AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
490	AssertMsg(pVM->pgm.s.pInterPD, ("Bad init order, paging.\n"));
491	AssertMsg(cbPages <= (512 << PAGE_SHIFT), ("The mapping is too big %d bytes\n", cbPages));
492	AssertMsg(HCPhys < _4G && HCPhys + cbPages < _4G, ("Addr=%RTptr HCPhys=%VHp cbPages=%d\n", Addr, HCPhys, cbPages));
493
494	/*
495	* Check for internal conflicts between the virtual address and the physical address.
496	*/
497	if ( uAddress != HCPhys
498	&& ( uAddress < HCPhys
499	? HCPhys - uAddress < cbPages
500	: uAddress - HCPhys < cbPages
501	)
502	)
503	AssertLogRelMsgFailedReturn(("Addr=%RTptr HCPhys=%VHp cbPages=%d\n", Addr, HCPhys, cbPages),
504	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
505
506	/* The intermediate mapping must not conflict with our default hypervisor address. */
507	size_t cbHyper;
508	RTGCPTR pvHyperGC = MMHyperGetArea(pVM, &cbHyper);
509	if (uAddress < pvHyperGC
510	? uAddress + cbPages > pvHyperGC
511	: pvHyperGC + cbHyper > uAddress
512	)
513	AssertLogRelMsgFailedReturn(("Addr=%RTptr HyperGC=%VGv cbPages=%zu\n", Addr, pvHyperGC, cbPages),
514	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
515
516	const unsigned cPages = cbPages >> PAGE_SHIFT;
517	int rc = pgmR3MapIntermediateCheckOne(pVM, uAddress, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
518	if (VBOX_FAILURE(rc))
519	return rc;
520	rc = pgmR3MapIntermediateCheckOne(pVM, (uintptr_t)HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
521	if (VBOX_FAILURE(rc))
522	return rc;
523
524	/*
525	* Everythings fine, do the mapping.
526	*/
527	pgmR3MapIntermediateDoOne(pVM, uAddress, HCPhys, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
528	pgmR3MapIntermediateDoOne(pVM, (uintptr_t)HCPhys, HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
529
530	return VINF_SUCCESS;
531	}
532
533
534	/**
535	* Validates that there are no conflicts for this mapping into the intermediate context.
536	*
537	* @returns VBox status code.
538	* @param pVM VM handle.
539	* @param uAddress Address of the mapping.
540	* @param cPages Number of pages.
541	* @param pPTDefault Pointer to the default page table for this mapping.
542	* @param pPTPaeDefault Pointer to the default page table for this mapping.
543	*/
544	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
545	{
546	AssertMsg((uAddress >> X86_PD_SHIFT) + cPages <= 1024, ("64-bit fixme\n"));
547
548	/*
549	* Check that the ranges are available.
550	* (This codes doesn't have to be fast.)
551	*/
552	while (cPages > 0)
553	{
554	/*
555	* 32-Bit.
556	*/
557	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
558	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
559	PX86PT pPT = pPTDefault;
560	if (pVM->pgm.s.pInterPD->a[iPDE].u)
561	{
562	RTHCPHYS HCPhysPT = pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK;
563	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]))
564	pPT = pVM->pgm.s.apInterPTs[0];
565	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]))
566	pPT = pVM->pgm.s.apInterPTs[1];
567	else
568	{
569	/** @todo this must be handled with a relocation of the conflicting mapping!
570	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
571	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%VHv\n", uAddress),
572	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
573	}
574	}
575	if (pPT->a[iPTE].u)
576	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%VHv pPT->a[iPTE].u=%RX32\n", iPTE, iPDE, uAddress, pPT->a[iPTE].u),
577	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
578
579	/*
580	* PAE.
581	*/
582	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
583	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
584	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
585	Assert(iPDPE < 4);
586	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
587	PX86PTPAE pPTPae = pPTPaeDefault;
588	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
589	{
590	RTHCPHYS HCPhysPT = pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK;
591	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
592	pPTPae = pVM->pgm.s.apInterPaePTs[0];
593	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
594	pPTPae = pVM->pgm.s.apInterPaePTs[1];
595	else
596	{
597	/** @todo this must be handled with a relocation of the conflicting mapping!
598	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
599	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%VHv\n", uAddress),
600	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
601	}
602	}
603	if (pPTPae->a[iPTE].u)
604	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%VHv pPTPae->a[iPTE].u=%#RX64\n", iPTE, iPDE, uAddress, pPTPae->a[iPTE].u),
605	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
606
607	/* next */
608	uAddress += PAGE_SIZE;
609	cPages--;
610	}
611
612	return VINF_SUCCESS;
613	}
614
615
616
617	/**
618	* Sets up the intermediate page tables for a verified mapping.
619	*
620	* @param pVM VM handle.
621	* @param uAddress Address of the mapping.
622	* @param HCPhys The physical address of the page range.
623	* @param cPages Number of pages.
624	* @param pPTDefault Pointer to the default page table for this mapping.
625	* @param pPTPaeDefault Pointer to the default page table for this mapping.
626	*/
627	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
628	{
629	while (cPages > 0)
630	{
631	/*
632	* 32-Bit.
633	*/
634	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
635	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
636	PX86PT pPT;
637	if (pVM->pgm.s.pInterPD->a[iPDE].u)
638	pPT = (PX86PT)MMPagePhys2Page(pVM, pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK);
639	else
640	{
641	pVM->pgm.s.pInterPD->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
642	\| (uint32_t)MMPage2Phys(pVM, pPTDefault);
643	pPT = pPTDefault;
644	}
645	pPT->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| (uint32_t)HCPhys;
646
647	/*
648	* PAE
649	*/
650	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
651	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
652	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
653	Assert(iPDPE < 4);
654	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
655	PX86PTPAE pPTPae;
656	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
657	pPTPae = (PX86PTPAE)MMPagePhys2Page(pVM, pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK);
658	else
659	{
660	pPTPae = pPTPaeDefault;
661	pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
662	\| MMPage2Phys(pVM, pPTPaeDefault);
663	}
664	pPTPae->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| HCPhys;
665
666	/* next */
667	cPages--;
668	HCPhys += PAGE_SIZE;
669	uAddress += PAGE_SIZE;
670	}
671	}
672
673
674	/**
675	* Clears all PDEs involved with the mapping.
676	*
677	* @param pPGM Pointer to the PGM instance data.
678	* @param pMap Pointer to the mapping in question.
679	* @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
680	*/
681	static void pgmR3MapClearPDEs(PPGM pPGM, PPGMMAPPING pMap, unsigned iOldPDE)
682	{
683	unsigned i = pMap->cPTs;
684	iOldPDE += i;
685	while (i-- > 0)
686	{
687	iOldPDE--;
688
689	/*
690	* 32-bit.
691	*/
692	pPGM->pInterPD->a[iOldPDE].u = 0;
693	pPGM->pHC32BitPD->a[iOldPDE].u = 0;
694
695	/*
696	* PAE.
697	*/
698	const unsigned iPD = iOldPDE / 256;
699	unsigned iPDE = iOldPDE * 2 % 512;
700	pPGM->apInterPaePDs[iPD]->a[iPDE].u = 0;
701	pPGM->apHCPaePDs[iPD]->a[iPDE].u = 0;
702	iPDE++;
703	pPGM->apInterPaePDs[iPD]->a[iPDE].u = 0;
704	pPGM->apHCPaePDs[iPD]->a[iPDE].u = 0;
705
706	/* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode) */
707	pPGM->pHCPaePDPT->a[iPD].u &= ~PGM_PLXFLAGS_MAPPING;
708	}
709	}
710
711
712	/**
713	* Sets all PDEs involved with the mapping.
714	*
715	* @param pVM The VM handle.
716	* @param pMap Pointer to the mapping in question.
717	* @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
718	*/
719	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
720	{
721	PPGM pPGM = &pVM->pgm.s;
722
723	/* If mappings are not supposed to be put in the shadow page table, then this function is a nop. */
724	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
725	return;
726
727	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
728
729	/*
730	* Init the page tables and insert them into the page directories.
731	*/
732	unsigned i = pMap->cPTs;
733	iNewPDE += i;
734	while (i-- > 0)
735	{
736	iNewPDE--;
737
738	/*
739	* 32-bit.
740	*/
741	if (pPGM->pHC32BitPD->a[iNewPDE].n.u1Present)
742	pgmPoolFree(pVM, pPGM->pHC32BitPD->a[iNewPDE].u & X86_PDE_PG_MASK, PGMPOOL_IDX_PD, iNewPDE);
743	X86PDE Pde;
744	/* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
745	Pde.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT;
746	pPGM->pInterPD->a[iNewPDE] = Pde;
747	pPGM->pHC32BitPD->a[iNewPDE] = Pde;
748
749	/*
750	* PAE.
751	*/
752	const unsigned iPD = iNewPDE / 256;
753	unsigned iPDE = iNewPDE * 2 % 512;
754	if (pPGM->apHCPaePDs[iPD]->a[iPDE].n.u1Present)
755	pgmPoolFree(pVM, pPGM->apHCPaePDs[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2);
756	X86PDEPAE PdePae0;
757	PdePae0.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0;
758	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae0;
759	pPGM->apHCPaePDs[iPD]->a[iPDE] = PdePae0;
760
761	iPDE++;
762	if (pPGM->apHCPaePDs[iPD]->a[iPDE].n.u1Present)
763	pgmPoolFree(pVM, pPGM->apHCPaePDs[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2 + 1);
764	X86PDEPAE PdePae1;
765	PdePae1.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1;
766	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae1;
767	pPGM->apHCPaePDs[iPD]->a[iPDE] = PdePae1;
768
769	/* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode) */
770	pPGM->pHCPaePDPT->a[iPD].u \|= PGM_PLXFLAGS_MAPPING;
771	}
772	}
773
774	/**
775	* Relocates a mapping to a new address.
776	*
777	* @param pVM VM handle.
778	* @param pMapping The mapping to relocate.
779	* @param GCPtrOldMapping The address of the start of the old mapping.
780	* @param GCPtrNewMapping The address of the start of the new mapping.
781	*/
782	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping)
783	{
784	unsigned iPDOld = GCPtrOldMapping >> X86_PD_SHIFT;
785	unsigned iPDNew = GCPtrNewMapping >> X86_PD_SHIFT;
786
787	Log(("PGM: Relocating %s from %VGv to %VGv\n", pMapping->pszDesc, GCPtrOldMapping, GCPtrNewMapping));
788	Assert(((unsigned)iPDOld << X86_PD_SHIFT) == pMapping->GCPtr);
789
790	/*
791	* Relocate the page table(s).
792	*/
793	pgmR3MapClearPDEs(&pVM->pgm.s, pMapping, iPDOld);
794	pgmR3MapSetPDEs(pVM, pMapping, iPDNew);
795
796	/*
797	* Update and resort the mapping list.
798	*/
799
800	/* Find previous mapping for pMapping, put result into pPrevMap. */
801	PPGMMAPPING pPrevMap = NULL;
802	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
803	while (pCur && pCur != pMapping)
804	{
805	/* next */
806	pPrevMap = pCur;
807	pCur = pCur->pNextR3;
808	}
809	Assert(pCur);
810
811	/* Find mapping which >= than pMapping. */
812	RTGCPTR GCPtrNew = iPDNew << X86_PD_SHIFT;
813	PPGMMAPPING pPrev = NULL;
814	pCur = pVM->pgm.s.pMappingsR3;
815	while (pCur && pCur->GCPtr < GCPtrNew)
816	{
817	/* next */
818	pPrev = pCur;
819	pCur = pCur->pNextR3;
820	}
821
822	if (pCur != pMapping && pPrev != pMapping)
823	{
824	/*
825	* Unlink.
826	*/
827	if (pPrevMap)
828	{
829	pPrevMap->pNextR3 = pMapping->pNextR3;
830	pPrevMap->pNextGC = pMapping->pNextGC;
831	pPrevMap->pNextR0 = pMapping->pNextR0;
832	}
833	else
834	{
835	pVM->pgm.s.pMappingsR3 = pMapping->pNextR3;
836	pVM->pgm.s.pMappingsGC = pMapping->pNextGC;
837	pVM->pgm.s.pMappingsR0 = pMapping->pNextR0;
838	}
839
840	/*
841	* Link
842	*/
843	pMapping->pNextR3 = pCur;
844	if (pPrev)
845	{
846	pMapping->pNextGC = pPrev->pNextGC;
847	pMapping->pNextR0 = pPrev->pNextR0;
848	pPrev->pNextR3 = pMapping;
849	pPrev->pNextGC = MMHyperR3ToRC(pVM, pMapping);
850	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pMapping);
851	}
852	else
853	{
854	pMapping->pNextGC = pVM->pgm.s.pMappingsGC;
855	pMapping->pNextR0 = pVM->pgm.s.pMappingsR0;
856	pVM->pgm.s.pMappingsR3 = pMapping;
857	pVM->pgm.s.pMappingsGC = MMHyperR3ToRC(pVM, pMapping);
858	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pMapping);
859	}
860	}
861
862	/*
863	* Update the entry.
864	*/
865	pMapping->GCPtr = GCPtrNew;
866	pMapping->GCPtrLast = GCPtrNew + pMapping->cb - 1;
867
868	/*
869	* Callback to execute the relocation.
870	*/
871	pMapping->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pMapping->pvUser);
872	}
873
874
875	/**
876	* Resolves a conflict between a page table based GC mapping and
877	* the Guest OS page tables. (32 bits version)
878	*
879	* @returns VBox status code.
880	* @param pVM VM Handle.
881	* @param pMapping The mapping which conflicts.
882	* @param pPDSrc The page directory of the guest OS.
883	* @param GCPtrOldMapping The address of the start of the current mapping.
884	*/
885	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping)
886	{
887	STAM_PROFILE_START(&pVM->pgm.s.StatHCResolveConflict, a);
888
889	/*
890	* Scan for free page directory entries.
891	*
892	* Note that we do not support mappings at the very end of the
893	* address space since that will break our GCPtrEnd assumptions.
894	*/
895	const unsigned cPTs = pMapping->cPTs;
896	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
897	while (iPDNew-- > 0)
898	{
899	if (pPDSrc->a[iPDNew].n.u1Present)
900	continue;
901	if (cPTs > 1)
902	{
903	bool fOk = true;
904	for (unsigned i = 1; fOk && i < cPTs; i++)
905	if (pPDSrc->a[iPDNew + i].n.u1Present)
906	fOk = false;
907	if (!fOk)
908	continue;
909	}
910
911	/*
912	* Check that it's not conflicting with an intermediate page table mapping.
913	*/
914	bool fOk = true;
915	unsigned i = cPTs;
916	while (fOk && i-- > 0)
917	fOk = !pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present;
918	if (!fOk)
919	continue;
920	/** @todo AMD64 should check the PAE directories and skip the 32bit stuff. */
921
922	/*
923	* Ask for the mapping.
924	*/
925	RTGCPTR GCPtrNewMapping = iPDNew << X86_PD_SHIFT;
926
927	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
928	{
929	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
930	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCResolveConflict, a);
931	return VINF_SUCCESS;
932	}
933	}
934
935	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCResolveConflict, a);
936	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, cPTs));
937	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
938	}
939
940	/**
941	* Resolves a conflict between a page table based GC mapping and
942	* the Guest OS page tables. (PAE bits version)
943	*
944	* @returns VBox status code.
945	* @param pVM VM Handle.
946	* @param pMapping The mapping which conflicts.
947	* @param GCPtrOldMapping The address of the start of the current mapping.
948	*/
949	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping)
950	{
951	STAM_PROFILE_START(&pVM->pgm.s.StatHCResolveConflict, a);
952
953	for (unsigned iPDPTE = X86_PG_PAE_PDPE_ENTRIES - 1; iPDPTE >= 0; iPDPTE--)
954	{
955	unsigned iPDSrc;
956	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPDPTE << X86_PDPT_SHIFT, &iPDSrc);
957
958	/*
959	* Scan for free page directory entries.
960	*
961	* Note that we do not support mappings at the very end of the
962	* address space since that will break our GCPtrEnd assumptions.
963	*/
964	const unsigned cPTs = pMapping->cb >> X86_PD_PAE_SHIFT;
965	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
966
967	while (iPDNew-- > 0)
968	{
969	/* Ugly assumption that mappings start on a 4 MB boundary. */
970	if (iPDNew & 1)
971	continue;
972
973	if (pPDSrc)
974	{
975	if (pPDSrc->a[iPDNew].n.u1Present)
976	continue;
977	if (cPTs > 1)
978	{
979	bool fOk = true;
980	for (unsigned i = 1; fOk && i < cPTs; i++)
981	if (pPDSrc->a[iPDNew + i].n.u1Present)
982	fOk = false;
983	if (!fOk)
984	continue;
985	}
986	}
987	/*
988	* Check that it's not conflicting with an intermediate page table mapping.
989	*/
990	bool fOk = true;
991	unsigned i = cPTs;
992	while (fOk && i-- > 0)
993	fOk = !pVM->pgm.s.apInterPaePDs[iPDPTE]->a[iPDNew + i].n.u1Present;
994	if (!fOk)
995	continue;
996
997	/*
998	* Ask for the mapping.
999	*/
1000	RTGCPTR GCPtrNewMapping = (iPDPTE << X86_PDPT_SHIFT) + (iPDNew << X86_PD_PAE_SHIFT);
1001
1002	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
1003	{
1004	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
1005	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCResolveConflict, a);
1006	return VINF_SUCCESS;
1007	}
1008	}
1009	}
1010	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCResolveConflict, a);
1011	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, pMapping->cb >> X86_PD_PAE_SHIFT));
1012	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
1013	}
1014
1015	/**
1016	* Checks guest PD for conflicts with VMM GC mappings.
1017	*
1018	* @returns true if conflict detected.
1019	* @returns false if not.
1020	* @param pVM The virtual machine.
1021	* @param cr3 Guest context CR3 register.
1022	* @param fRawR0 Whether RawR0 is enabled or not.
1023	*/
1024	PGMR3DECL(bool) PGMR3MapHasConflicts(PVM pVM, uint64_t cr3, bool fRawR0) /** @todo how many HasConflict constructs do we really need? */
1025	{
1026	/*
1027	* Can skip this if mappings are safely fixed.
1028	*/
1029	if (pVM->pgm.s.fMappingsFixed)
1030	return false;
1031
1032	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1033
1034	/*
1035	* Iterate mappings.
1036	*/
1037	if (PGMGetGuestMode(pVM) == PGMMODE_32_BIT)
1038	{
1039	/*
1040	* Resolve the page directory.
1041	*/
1042	PX86PD pPD = pVM->pgm.s.pGuestPDHC;
1043	Assert(pPD);
1044	Assert(pPD == (PX86PD)MMPhysGCPhys2HCVirt(pVM, cr3 & X86_CR3_PAGE_MASK, sizeof(*pPD)));
1045
1046	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1047	{
1048	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
1049	unsigned iPT = pCur->cPTs;
1050	while (iPT-- > 0)
1051	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
1052	&& (fRawR0 \|\| pPD->a[iPDE + iPT].n.u1User))
1053	{
1054	STAM_COUNTER_INC(&pVM->pgm.s.StatHCDetectedConflicts);
1055	Log(("PGMR3HasMappingConflicts: Conflict was detected at %VGv for mapping %s (32 bits)\n"
1056	" iPDE=%#x iPT=%#x PDE=%VGp.\n",
1057	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
1058	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
1059	return true;
1060	}
1061	}
1062	}
1063	else
1064	if (PGMGetGuestMode(pVM) == PGMMODE_PAE)
1065	{
1066	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1067	{
1068	X86PDEPAE Pde;
1069	RTGCPTR GCPtr = pCur->GCPtr;
1070
1071	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
1072	while (iPT-- > 0)
1073	{
1074	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
1075
1076	if ( Pde.n.u1Present
1077	&& (fRawR0 \|\| Pde.n.u1User))
1078	{
1079	STAM_COUNTER_INC(&pVM->pgm.s.StatHCDetectedConflicts);
1080	Log(("PGMR3HasMappingConflicts: Conflict was detected at %VGv for mapping %s (PAE)\n"
1081	" PDE=%VGp.\n",
1082	GCPtr, pCur->pszDesc, Pde.u));
1083	return true;
1084	}
1085	GCPtr += (1 << X86_PD_PAE_SHIFT);
1086	}
1087	}
1088	}
1089	else
1090	AssertFailed();
1091
1092	return false;
1093	}
1094
1095
1096	/**
1097	* Read memory from the guest mappings.
1098	*
1099	* This will use the page tables associated with the mappings to
1100	* read the memory. This means that not all kind of memory is readable
1101	* since we don't necessarily know how to convert that physical address
1102	* to a HC virtual one.
1103	*
1104	* @returns VBox status.
1105	* @param pVM VM handle.
1106	* @param pvDst The destination address (HC of course).
1107	* @param GCPtrSrc The source address (GC virtual address).
1108	* @param cb Number of bytes to read.
1109	*/
1110	PGMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
1111	{
1112	/** @todo remove this simplicity hack */
1113	/*
1114	* Simplicity over speed... Chop the request up into chunks
1115	* which don't cross pages.
1116	*/
1117	if (cb + (GCPtrSrc & PAGE_OFFSET_MASK) > PAGE_SIZE)
1118	{
1119	for (;;)
1120	{
1121	unsigned cbRead = RT_MIN(cb, PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK));
1122	int rc = PGMR3MapRead(pVM, pvDst, GCPtrSrc, cbRead);
1123	if (VBOX_FAILURE(rc))
1124	return rc;
1125	cb -= cbRead;
1126	if (!cb)
1127	break;
1128	pvDst = (char *)pvDst + cbRead;
1129	GCPtrSrc += cbRead;
1130	}
1131	return VINF_SUCCESS;
1132	}
1133
1134	/*
1135	* Find the mapping.
1136	*/
1137	PPGMMAPPING pCur = CTXALLSUFF(pVM->pgm.s.pMappings);
1138	while (pCur)
1139	{
1140	RTGCUINTPTR off = (RTGCUINTPTR)GCPtrSrc - (RTGCUINTPTR)pCur->GCPtr;
1141	if (off < pCur->cb)
1142	{
1143	if (off + cb > pCur->cb)
1144	{
1145	AssertMsgFailed(("Invalid page range %VGv LB%#x. mapping '%s' %VGv to %VGv\n",
1146	GCPtrSrc, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast));
1147	return VERR_INVALID_PARAMETER;
1148	}
1149
1150	unsigned iPT = off >> X86_PD_SHIFT;
1151	unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
1152	while (cb > 0 && iPTE < RT_ELEMENTS(CTXALLSUFF(pCur->aPTs[iPT].pPT)->a))
1153	{
1154	if (!CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].n.u1Present)
1155	return VERR_PAGE_NOT_PRESENT;
1156	RTHCPHYS HCPhys = CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].u & X86_PTE_PAE_PG_MASK;
1157
1158	/*
1159	* Get the virtual page from the physical one.
1160	*/
1161	void *pvPage;
1162	int rc = MMR3HCPhys2HCVirt(pVM, HCPhys, &pvPage);
1163	if (VBOX_FAILURE(rc))
1164	return rc;
1165
1166	memcpy(pvDst, (char *)pvPage + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
1167	return VINF_SUCCESS;
1168	}
1169	}
1170
1171	/* next */
1172	pCur = CTXALLSUFF(pCur->pNext);
1173	}
1174
1175	return VERR_INVALID_POINTER;
1176	}
1177
1178
1179	/**
1180	* Info callback for 'pgmhandlers'.
1181	*
1182	* @param pHlp The output helpers.
1183	* @param pszArgs The arguments. phys or virt.
1184	*/
1185	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1186	{
1187	pHlp->pfnPrintf(pHlp, pVM->pgm.s.fMappingsFixed
1188	? "\nThe mappings are FIXED.\n"
1189	: "\nThe mappings are FLOATING.\n");
1190	PPGMMAPPING pCur;
1191	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1192	pHlp->pfnPrintf(pHlp, "%VGv - %VGv %s\n", pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
1193	}
1194

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source: vbox/trunk/src/VBox/VMM/PGMMap.cpp@ 11311

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