PGMMap.cpp@ 14257

Last change on this file since 14257 was 14154, checked in by vboxsync, 16 years ago
PGM: pGuestPD* -> pGst32BitPd*
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 42.6 KB

Line
1	/* $Id: PGMMap.cpp 14154 2008-11-12 23:34:50Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager, Guest Context Mappings.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/dbgf.h>
28	#include <VBox/pgm.h>
29	#include "PGMInternal.h"
30	#include <VBox/vm.h>
31
32	#include <VBox/log.h>
33	#include <VBox/err.h>
34	#include <iprt/asm.h>
35	#include <iprt/assert.h>
36	#include <iprt/string.h>
37
38
39	/*******************************************************************************
40	* Internal Functions *
41	*******************************************************************************/
42	static void pgmR3MapClearPDEs(PPGM pPGM, PPGMMAPPING pMap, unsigned iOldPDE);
43	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
44	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
45	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
46
47
48
49	/**
50	* Creates a page table based mapping in GC.
51	*
52	* @returns VBox status code.
53	* @param pVM VM Handle.
54	* @param GCPtr Virtual Address. (Page table aligned!)
55	* @param cb Size of the range. Must be a 4MB aligned!
56	* @param pfnRelocate Relocation callback function.
57	* @param pvUser User argument to the callback.
58	* @param pszDesc Pointer to description string. This must not be freed.
59	*/
60	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc)
61	{
62	LogFlow(("PGMR3MapPT: GCPtr=%#x cb=%d pfnRelocate=%p pvUser=%p pszDesc=%s\n", GCPtr, cb, pfnRelocate, pvUser, pszDesc));
63	AssertMsg(pVM->pgm.s.pInterPD && pVM->pgm.s.pShw32BitPdR3, ("Paging isn't initialized, init order problems!\n"));
64
65	/*
66	* Validate input.
67	*/
68	if (cb < _2M \|\| cb > 64 * _1M)
69	{
70	AssertMsgFailed(("Serious? cb=%d\n", cb));
71	return VERR_INVALID_PARAMETER;
72	}
73	cb = RT_ALIGN_32(cb, _4M);
74	RTGCPTR GCPtrLast = GCPtr + cb - 1;
75	if (GCPtrLast < GCPtr)
76	{
77	AssertMsgFailed(("Range wraps! GCPtr=%x GCPtrLast=%x\n", GCPtr, GCPtrLast));
78	return VERR_INVALID_PARAMETER;
79	}
80	if (pVM->pgm.s.fMappingsFixed)
81	{
82	AssertMsgFailed(("Mappings are fixed! It's not possible to add new mappings at this time!\n"));
83	return VERR_PGM_MAPPINGS_FIXED;
84	}
85	if (!pfnRelocate)
86	{
87	AssertMsgFailed(("Callback is required\n"));
88	return VERR_INVALID_PARAMETER;
89	}
90
91	/*
92	* Find list location.
93	*/
94	PPGMMAPPING pPrev = NULL;
95	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
96	while (pCur)
97	{
98	if (pCur->GCPtrLast >= GCPtr && pCur->GCPtr <= GCPtrLast)
99	{
100	AssertMsgFailed(("Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
101	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
102	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
103	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
104	return VERR_PGM_MAPPING_CONFLICT;
105	}
106	if (pCur->GCPtr > GCPtr)
107	break;
108	pPrev = pCur;
109	pCur = pCur->pNextR3;
110	}
111
112	/*
113	* Check for conflicts with intermediate mappings.
114	*/
115	const unsigned iPageDir = GCPtr >> X86_PD_SHIFT;
116	const unsigned cPTs = cb >> X86_PD_SHIFT;
117	unsigned i;
118	for (i = 0; i < cPTs; i++)
119	{
120	if (pVM->pgm.s.pInterPD->a[iPageDir + i].n.u1Present)
121	{
122	AssertMsgFailed(("Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
123	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
124	return VERR_PGM_MAPPING_CONFLICT;
125	}
126	}
127	/** @todo AMD64: add check in PAE structures too, so we can remove all the 32-Bit paging stuff there. */
128
129	/*
130	* Allocate and initialize the new list node.
131	*/
132	PPGMMAPPING pNew;
133	int rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMMAPPING, aPTs[cPTs]), 0, MM_TAG_PGM, (void **)&pNew);
134	if (RT_FAILURE(rc))
135	return rc;
136	pNew->GCPtr = GCPtr;
137	pNew->GCPtrLast = GCPtrLast;
138	pNew->cb = cb;
139	pNew->pszDesc = pszDesc;
140	pNew->pfnRelocate = pfnRelocate;
141	pNew->pvUser = pvUser;
142	pNew->cPTs = cPTs;
143
144	/*
145	* Allocate page tables and insert them into the page directories.
146	* (One 32-bit PT and two PAE PTs.)
147	*/
148	uint8_t *pbPTs;
149	rc = MMHyperAlloc(pVM, PAGE_SIZE * 3 * cPTs, PAGE_SIZE, MM_TAG_PGM, (void **)&pbPTs);
150	if (RT_FAILURE(rc))
151	{
152	MMHyperFree(pVM, pNew);
153	return VERR_NO_MEMORY;
154	}
155
156	/*
157	* Init the page tables and insert them into the page directories.
158	*/
159	Log4(("PGMR3MapPT: GCPtr=%RGv cPTs=%u pbPTs=%p\n", GCPtr, cPTs, pbPTs));
160	for (i = 0; i < cPTs; i++)
161	{
162	/*
163	* 32-bit.
164	*/
165	pNew->aPTs[i].pPTR3 = (PX86PT)pbPTs;
166	pNew->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pNew->aPTs[i].pPTR3);
167	pNew->aPTs[i].pPTR0 = MMHyperR3ToR0(pVM, pNew->aPTs[i].pPTR3);
168	pNew->aPTs[i].HCPhysPT = MMR3HyperHCVirt2HCPhys(pVM, pNew->aPTs[i].pPTR3);
169	pbPTs += PAGE_SIZE;
170	Log4(("PGMR3MapPT: i=%d: pPTR3=%RHv pPTRC=%RRv pPRTR0=%RHv HCPhysPT=%RHp\n",
171	i, pNew->aPTs[i].pPTR3, pNew->aPTs[i].pPTRC, pNew->aPTs[i].pPTR0, pNew->aPTs[i].HCPhysPT));
172
173	/*
174	* PAE.
175	*/
176	pNew->aPTs[i].HCPhysPaePT0 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs);
177	pNew->aPTs[i].HCPhysPaePT1 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs + PAGE_SIZE);
178	pNew->aPTs[i].paPaePTsR3 = (PX86PTPAE)pbPTs;
179	pNew->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pbPTs);
180	pNew->aPTs[i].paPaePTsR0 = MMHyperR3ToR0(pVM, pbPTs);
181	pbPTs += PAGE_SIZE * 2;
182	Log4(("PGMR3MapPT: i=%d: paPaePTsR#=%RHv paPaePTsRC=%RRv paPaePTsR#=%RHv HCPhysPaePT0=%RHp HCPhysPaePT1=%RHp\n",
183	i, pNew->aPTs[i].paPaePTsR3, pNew->aPTs[i].paPaePTsRC, pNew->aPTs[i].paPaePTsR0, pNew->aPTs[i].HCPhysPaePT0, pNew->aPTs[i].HCPhysPaePT1));
184	}
185	pgmR3MapSetPDEs(pVM, pNew, iPageDir);
186
187	/*
188	* Insert the new mapping.
189	*/
190	pNew->pNextR3 = pCur;
191	pNew->pNextRC = pCur ? MMHyperR3ToRC(pVM, pCur) : NIL_RTRCPTR;
192	pNew->pNextR0 = pCur ? MMHyperR3ToR0(pVM, pCur) : NIL_RTR0PTR;
193	if (pPrev)
194	{
195	pPrev->pNextR3 = pNew;
196	pPrev->pNextRC = MMHyperR3ToRC(pVM, pNew);
197	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pNew);
198	}
199	else
200	{
201	pVM->pgm.s.pMappingsR3 = pNew;
202	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pNew);
203	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pNew);
204	}
205
206	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
207	return VINF_SUCCESS;
208	}
209
210
211	/**
212	* Removes a page table based mapping.
213	*
214	* @returns VBox status code.
215	* @param pVM VM Handle.
216	* @param GCPtr Virtual Address. (Page table aligned!)
217	*/
218	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr)
219	{
220	LogFlow(("PGMR3UnmapPT: GCPtr=%#x\n", GCPtr));
221
222	/*
223	* Find it.
224	*/
225	PPGMMAPPING pPrev = NULL;
226	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
227	while (pCur)
228	{
229	if (pCur->GCPtr == GCPtr)
230	{
231	/*
232	* Unlink it.
233	*/
234	if (pPrev)
235	{
236	pPrev->pNextR3 = pCur->pNextR3;
237	pPrev->pNextRC = pCur->pNextRC;
238	pPrev->pNextR0 = pCur->pNextR0;
239	}
240	else
241	{
242	pVM->pgm.s.pMappingsR3 = pCur->pNextR3;
243	pVM->pgm.s.pMappingsRC = pCur->pNextRC;
244	pVM->pgm.s.pMappingsR0 = pCur->pNextR0;
245	}
246
247	/*
248	* Free the page table memory, clear page directory entries
249	* and free the page tables and node memory.
250	*/
251	MMHyperFree(pVM, pCur->aPTs[0].pPTR3);
252	pgmR3MapClearPDEs(&pVM->pgm.s, pCur, pCur->GCPtr >> X86_PD_SHIFT);
253	MMHyperFree(pVM, pCur);
254
255	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
256	return VINF_SUCCESS;
257	}
258
259	/* done? */
260	if (pCur->GCPtr > GCPtr)
261	break;
262
263	/* next */
264	pPrev = pCur;
265	pCur = pCur->pNextR3;
266	}
267
268	AssertMsgFailed(("No mapping for %#x found!\n", GCPtr));
269	return VERR_INVALID_PARAMETER;
270	}
271
272
273	/**
274	* Gets the size of the current guest mappings if they were to be
275	* put next to oneanother.
276	*
277	* @returns VBox status code.
278	* @param pVM The VM.
279	* @param pcb Where to store the size.
280	*/
281	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb)
282	{
283	RTGCPTR cb = 0;
284	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
285	cb += pCur->cb;
286
287	*pcb = cb;
288	AssertReturn(*pcb == cb, VERR_NUMBER_TOO_BIG);
289	Log(("PGMR3MappingsSize: return %d (%#x) bytes\n", cb, cb));
290	return VINF_SUCCESS;
291	}
292
293
294	/**
295	* Fixes the guest context mappings in a range reserved from the Guest OS.
296	*
297	* @returns VBox status code.
298	* @param pVM The VM.
299	* @param GCPtrBase The address of the reserved range of guest memory.
300	* @param cb The size of the range starting at GCPtrBase.
301	*/
302	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb)
303	{
304	Log(("PGMR3MappingsFix: GCPtrBase=%#x cb=%#x\n", GCPtrBase, cb));
305
306	/* Ignore the additions mapping fix call in VT-x/AMD-V. */
307	if ( pVM->pgm.s.fMappingsFixed
308	&& HWACCMR3IsActive(pVM))
309	return VINF_SUCCESS;
310
311	/*
312	* This is all or nothing at all. So, a tiny bit of paranoia first.
313	*/
314	if (GCPtrBase & X86_PAGE_4M_OFFSET_MASK)
315	{
316	AssertMsgFailed(("GCPtrBase (%#x) has to be aligned on a 4MB address!\n", GCPtrBase));
317	return VERR_INVALID_PARAMETER;
318	}
319	if (!cb \|\| (cb & X86_PAGE_4M_OFFSET_MASK))
320	{
321	AssertMsgFailed(("cb (%#x) is 0 or not aligned on a 4MB address!\n", cb));
322	return VERR_INVALID_PARAMETER;
323	}
324
325	/*
326	* Before we do anything we'll do a forced PD sync to try make sure any
327	* pending relocations because of these mappings have been resolved.
328	*/
329	PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), true);
330
331	/*
332	* Check that it's not conflicting with a core code mapping in the intermediate page table.
333	*/
334	unsigned iPDNew = GCPtrBase >> X86_PD_SHIFT;
335	unsigned i = cb >> X86_PD_SHIFT;
336	while (i-- > 0)
337	{
338	if (pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present)
339	{
340	/* Check that it's not one or our mappings. */
341	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
342	while (pCur)
343	{
344	if (iPDNew + i - (pCur->GCPtr >> X86_PD_SHIFT) < (pCur->cb >> X86_PD_SHIFT))
345	break;
346	pCur = pCur->pNextR3;
347	}
348	if (!pCur)
349	{
350	LogRel(("PGMR3MappingsFix: Conflicts with intermediate PDE %#x (GCPtrBase=%RGv cb=%#zx). The guest should retry.\n",
351	iPDNew + i, GCPtrBase, cb));
352	return VERR_PGM_MAPPINGS_FIX_CONFLICT;
353	}
354	}
355	}
356
357	/*
358	* In PAE / PAE mode, make sure we don't cross page directories.
359	*/
360	if ( ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
361	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX)
362	&& ( pVM->pgm.s.enmShadowMode == PGMMODE_PAE
363	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX))
364	{
365	unsigned iPdptBase = GCPtrBase >> X86_PDPT_SHIFT;
366	unsigned iPdptLast = (GCPtrBase + cb - 1) >> X86_PDPT_SHIFT;
367	if (iPdptBase != iPdptLast)
368	{
369	LogRel(("PGMR3MappingsFix: Crosses PD boundrary; iPdptBase=%#x iPdptLast=%#x (GCPtrBase=%RGv cb=%#zx). The guest should retry.\n",
370	iPdptBase, iPdptLast, GCPtrBase, cb));
371	return VERR_PGM_MAPPINGS_FIX_CONFLICT;
372	}
373	}
374
375	/*
376	* Loop the mappings and check that they all agree on their new locations.
377	*/
378	RTGCPTR GCPtrCur = GCPtrBase;
379	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
380	while (pCur)
381	{
382	if (!pCur->pfnRelocate(pVM, pCur->GCPtr, GCPtrCur, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
383	{
384	AssertMsgFailed(("The suggested fixed address %#x was rejected by '%s'!\n", GCPtrCur, pCur->pszDesc));
385	return VERR_PGM_MAPPINGS_FIX_REJECTED;
386	}
387	/* next */
388	GCPtrCur += pCur->cb;
389	pCur = pCur->pNextR3;
390	}
391	if (GCPtrCur > GCPtrBase + cb)
392	{
393	AssertMsgFailed(("cb (%#x) is less than the required range %#x!\n", cb, GCPtrCur - GCPtrBase));
394	return VERR_PGM_MAPPINGS_FIX_TOO_SMALL;
395	}
396
397	/*
398	* Loop the table assigning the mappings to the passed in memory
399	* and call their relocator callback.
400	*/
401	GCPtrCur = GCPtrBase;
402	pCur = pVM->pgm.s.pMappingsR3;
403	while (pCur)
404	{
405	unsigned iPDOld = pCur->GCPtr >> X86_PD_SHIFT;
406	iPDNew = GCPtrCur >> X86_PD_SHIFT;
407
408	/*
409	* Relocate the page table(s).
410	*/
411	pgmR3MapClearPDEs(&pVM->pgm.s, pCur, iPDOld);
412	pgmR3MapSetPDEs(pVM, pCur, iPDNew);
413
414	/*
415	* Update the entry.
416	*/
417	pCur->GCPtr = GCPtrCur;
418	pCur->GCPtrLast = GCPtrCur + pCur->cb - 1;
419
420	/*
421	* Callback to execute the relocation.
422	*/
423	pCur->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pCur->pvUser);
424
425	/*
426	* Advance.
427	*/
428	GCPtrCur += pCur->cb;
429	pCur = pCur->pNextR3;
430	}
431
432	/*
433	* Turn off CR3 updating monitoring.
434	*/
435	int rc2 = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
436	AssertRC(rc2);
437
438	/*
439	* Mark the mappings as fixed and return.
440	*/
441	pVM->pgm.s.fMappingsFixed = true;
442	pVM->pgm.s.GCPtrMappingFixed = GCPtrBase;
443	pVM->pgm.s.cbMappingFixed = cb;
444	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
445	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
446	return VINF_SUCCESS;
447	}
448
449
450	/**
451	* Unfixes the mappings.
452	* After calling this function mapping conflict detection will be enabled.
453	*
454	* @returns VBox status code.
455	* @param pVM The VM.
456	*/
457	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM)
458	{
459	Log(("PGMR3MappingsUnfix: fMappingsFixed=%d\n", pVM->pgm.s.fMappingsFixed));
460
461	/* Refuse in VT-x/AMD-V mode. */
462	if (HWACCMR3IsActive(pVM))
463	return VINF_SUCCESS;
464
465	pVM->pgm.s.fMappingsFixed = false;
466	pVM->pgm.s.GCPtrMappingFixed = 0;
467	pVM->pgm.s.cbMappingFixed = 0;
468	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
469
470	/*
471	* Re-enable the CR3 monitoring.
472	*
473	* Paranoia: We flush the page pool before doing that because Windows
474	* is using the CR3 page both as a PD and a PT, e.g. the pool may
475	* be monitoring it.
476	*/
477	#ifdef PGMPOOL_WITH_MONITORING
478	pgmPoolFlushAll(pVM);
479	#endif
480	/* Remap CR3 as we have just flushed the CR3 shadow PML4 in case we're in long mode. */
481	int rc = PGM_GST_PFN(MapCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
482	AssertRC(rc);
483
484	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
485	AssertRC(rc);
486
487	return VINF_SUCCESS;
488	}
489
490
491	/**
492	* Map pages into the intermediate context (switcher code).
493	* These pages are mapped at both the give virtual address and at
494	* the physical address (for identity mapping).
495	*
496	* @returns VBox status code.
497	* @param pVM The virtual machine.
498	* @param Addr Intermediate context address of the mapping.
499	* @param HCPhys Start of the range of physical pages. This must be entriely below 4GB!
500	* @param cbPages Number of bytes to map.
501	*
502	* @remark This API shall not be used to anything but mapping the switcher code.
503	*/
504	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages)
505	{
506	LogFlow(("PGMR3MapIntermediate: Addr=%RTptr HCPhys=%RHp cbPages=%#x\n", Addr, HCPhys, cbPages));
507
508	/*
509	* Adjust input.
510	*/
511	cbPages += (uint32_t)HCPhys & PAGE_OFFSET_MASK;
512	cbPages = RT_ALIGN(cbPages, PAGE_SIZE);
513	HCPhys &= X86_PTE_PAE_PG_MASK;
514	Addr &= PAGE_BASE_MASK;
515	/* We only care about the first 4GB, because on AMD64 we'll be repeating them all over the address space. */
516	uint32_t uAddress = (uint32_t)Addr;
517
518	/*
519	* Assert input and state.
520	*/
521	AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
522	AssertMsg(pVM->pgm.s.pInterPD, ("Bad init order, paging.\n"));
523	AssertMsg(cbPages <= (512 << PAGE_SHIFT), ("The mapping is too big %d bytes\n", cbPages));
524	AssertMsg(HCPhys < _4G && HCPhys + cbPages < _4G, ("Addr=%RTptr HCPhys=%RHp cbPages=%d\n", Addr, HCPhys, cbPages));
525
526	/*
527	* Check for internal conflicts between the virtual address and the physical address.
528	*/
529	if ( uAddress != HCPhys
530	&& ( uAddress < HCPhys
531	? HCPhys - uAddress < cbPages
532	: uAddress - HCPhys < cbPages
533	)
534	)
535	AssertLogRelMsgFailedReturn(("Addr=%RTptr HCPhys=%RHp cbPages=%d\n", Addr, HCPhys, cbPages),
536	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
537
538	/* The intermediate mapping must not conflict with our default hypervisor address. */
539	size_t cbHyper;
540	RTGCPTR pvHyperGC = MMHyperGetArea(pVM, &cbHyper);
541	if (uAddress < pvHyperGC
542	? uAddress + cbPages > pvHyperGC
543	: pvHyperGC + cbHyper > uAddress
544	)
545	AssertLogRelMsgFailedReturn(("Addr=%RTptr HyperGC=%RGv cbPages=%zu\n", Addr, pvHyperGC, cbPages),
546	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
547
548	const unsigned cPages = cbPages >> PAGE_SHIFT;
549	int rc = pgmR3MapIntermediateCheckOne(pVM, uAddress, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
550	if (RT_FAILURE(rc))
551	return rc;
552	rc = pgmR3MapIntermediateCheckOne(pVM, (uintptr_t)HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
553	if (RT_FAILURE(rc))
554	return rc;
555
556	/*
557	* Everythings fine, do the mapping.
558	*/
559	pgmR3MapIntermediateDoOne(pVM, uAddress, HCPhys, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
560	pgmR3MapIntermediateDoOne(pVM, (uintptr_t)HCPhys, HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
561
562	return VINF_SUCCESS;
563	}
564
565
566	/**
567	* Validates that there are no conflicts for this mapping into the intermediate context.
568	*
569	* @returns VBox status code.
570	* @param pVM VM handle.
571	* @param uAddress Address of the mapping.
572	* @param cPages Number of pages.
573	* @param pPTDefault Pointer to the default page table for this mapping.
574	* @param pPTPaeDefault Pointer to the default page table for this mapping.
575	*/
576	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
577	{
578	AssertMsg((uAddress >> X86_PD_SHIFT) + cPages <= 1024, ("64-bit fixme\n"));
579
580	/*
581	* Check that the ranges are available.
582	* (This codes doesn't have to be fast.)
583	*/
584	while (cPages > 0)
585	{
586	/*
587	* 32-Bit.
588	*/
589	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
590	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
591	PX86PT pPT = pPTDefault;
592	if (pVM->pgm.s.pInterPD->a[iPDE].u)
593	{
594	RTHCPHYS HCPhysPT = pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK;
595	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]))
596	pPT = pVM->pgm.s.apInterPTs[0];
597	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]))
598	pPT = pVM->pgm.s.apInterPTs[1];
599	else
600	{
601	/** @todo this must be handled with a relocation of the conflicting mapping!
602	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
603	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%RHv\n", uAddress),
604	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
605	}
606	}
607	if (pPT->a[iPTE].u)
608	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%RHv pPT->a[iPTE].u=%RX32\n", iPTE, iPDE, uAddress, pPT->a[iPTE].u),
609	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
610
611	/*
612	* PAE.
613	*/
614	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
615	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
616	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
617	Assert(iPDPE < 4);
618	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
619	PX86PTPAE pPTPae = pPTPaeDefault;
620	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
621	{
622	RTHCPHYS HCPhysPT = pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK;
623	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
624	pPTPae = pVM->pgm.s.apInterPaePTs[0];
625	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
626	pPTPae = pVM->pgm.s.apInterPaePTs[1];
627	else
628	{
629	/** @todo this must be handled with a relocation of the conflicting mapping!
630	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
631	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%RHv\n", uAddress),
632	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
633	}
634	}
635	if (pPTPae->a[iPTE].u)
636	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%RHv pPTPae->a[iPTE].u=%#RX64\n", iPTE, iPDE, uAddress, pPTPae->a[iPTE].u),
637	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
638
639	/* next */
640	uAddress += PAGE_SIZE;
641	cPages--;
642	}
643
644	return VINF_SUCCESS;
645	}
646
647
648
649	/**
650	* Sets up the intermediate page tables for a verified mapping.
651	*
652	* @param pVM VM handle.
653	* @param uAddress Address of the mapping.
654	* @param HCPhys The physical address of the page range.
655	* @param cPages Number of pages.
656	* @param pPTDefault Pointer to the default page table for this mapping.
657	* @param pPTPaeDefault Pointer to the default page table for this mapping.
658	*/
659	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
660	{
661	while (cPages > 0)
662	{
663	/*
664	* 32-Bit.
665	*/
666	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
667	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
668	PX86PT pPT;
669	if (pVM->pgm.s.pInterPD->a[iPDE].u)
670	pPT = (PX86PT)MMPagePhys2Page(pVM, pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK);
671	else
672	{
673	pVM->pgm.s.pInterPD->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
674	\| (uint32_t)MMPage2Phys(pVM, pPTDefault);
675	pPT = pPTDefault;
676	}
677	pPT->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| (uint32_t)HCPhys;
678
679	/*
680	* PAE
681	*/
682	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
683	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
684	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
685	Assert(iPDPE < 4);
686	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
687	PX86PTPAE pPTPae;
688	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
689	pPTPae = (PX86PTPAE)MMPagePhys2Page(pVM, pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK);
690	else
691	{
692	pPTPae = pPTPaeDefault;
693	pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
694	\| MMPage2Phys(pVM, pPTPaeDefault);
695	}
696	pPTPae->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| HCPhys;
697
698	/* next */
699	cPages--;
700	HCPhys += PAGE_SIZE;
701	uAddress += PAGE_SIZE;
702	}
703	}
704
705
706	/**
707	* Clears all PDEs involved with the mapping.
708	*
709	* @param pPGM Pointer to the PGM instance data.
710	* @param pMap Pointer to the mapping in question.
711	* @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
712	*/
713	static void pgmR3MapClearPDEs(PPGM pPGM, PPGMMAPPING pMap, unsigned iOldPDE)
714	{
715	unsigned i = pMap->cPTs;
716	iOldPDE += i;
717	while (i-- > 0)
718	{
719	iOldPDE--;
720
721	/*
722	* 32-bit.
723	*/
724	pPGM->pInterPD->a[iOldPDE].u = 0;
725	pPGM->pShw32BitPdR3->a[iOldPDE].u = 0;
726
727	/*
728	* PAE.
729	*/
730	const unsigned iPD = iOldPDE / 256;
731	unsigned iPDE = iOldPDE * 2 % 512;
732	pPGM->apInterPaePDs[iPD]->a[iPDE].u = 0;
733	pPGM->apShwPaePDsR3[iPD]->a[iPDE].u = 0;
734	iPDE++;
735	pPGM->apInterPaePDs[iPD]->a[iPDE].u = 0;
736	pPGM->apShwPaePDsR3[iPD]->a[iPDE].u = 0;
737
738	/* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode) */
739	pPGM->pShwPaePdptR3->a[iPD].u &= ~PGM_PLXFLAGS_MAPPING;
740	}
741	}
742
743
744	/**
745	* Sets all PDEs involved with the mapping.
746	*
747	* @param pVM The VM handle.
748	* @param pMap Pointer to the mapping in question.
749	* @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
750	*/
751	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
752	{
753	PPGM pPGM = &pVM->pgm.s;
754
755	/* If mappings are not supposed to be put in the shadow page table, then this function is a nop. */
756	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
757	return;
758
759	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE_NX);
760
761	/*
762	* Init the page tables and insert them into the page directories.
763	*/
764	unsigned i = pMap->cPTs;
765	iNewPDE += i;
766	while (i-- > 0)
767	{
768	iNewPDE--;
769
770	/*
771	* 32-bit.
772	*/
773	if (pPGM->pShw32BitPdR3->a[iNewPDE].n.u1Present)
774	pgmPoolFree(pVM, pPGM->pShw32BitPdR3->a[iNewPDE].u & X86_PDE_PG_MASK, PGMPOOL_IDX_PD, iNewPDE);
775	X86PDE Pde;
776	/* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
777	Pde.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT;
778	pPGM->pInterPD->a[iNewPDE] = Pde;
779	pPGM->pShw32BitPdR3->a[iNewPDE] = Pde;
780
781	/*
782	* PAE.
783	*/
784	const unsigned iPD = iNewPDE / 256;
785	unsigned iPDE = iNewPDE * 2 % 512;
786	if (pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present)
787	pgmPoolFree(pVM, pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2);
788	X86PDEPAE PdePae0;
789	PdePae0.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0;
790	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae0;
791	pPGM->apShwPaePDsR3[iPD]->a[iPDE] = PdePae0;
792
793	iPDE++;
794	if (pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present)
795	pgmPoolFree(pVM, pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2 + 1);
796	X86PDEPAE PdePae1;
797	PdePae1.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1;
798	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae1;
799	pPGM->apShwPaePDsR3[iPD]->a[iPDE] = PdePae1;
800
801	/* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode) */
802	pPGM->pShwPaePdptR3->a[iPD].u \|= PGM_PLXFLAGS_MAPPING;
803	}
804	}
805
806
807	/**
808	* Relocates a mapping to a new address.
809	*
810	* @param pVM VM handle.
811	* @param pMapping The mapping to relocate.
812	* @param GCPtrOldMapping The address of the start of the old mapping.
813	* @param GCPtrNewMapping The address of the start of the new mapping.
814	*/
815	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping)
816	{
817	unsigned iPDOld = GCPtrOldMapping >> X86_PD_SHIFT;
818	unsigned iPDNew = GCPtrNewMapping >> X86_PD_SHIFT;
819
820	Log(("PGM: Relocating %s from %RGv to %RGv\n", pMapping->pszDesc, GCPtrOldMapping, GCPtrNewMapping));
821	Assert(((unsigned)iPDOld << X86_PD_SHIFT) == pMapping->GCPtr);
822
823	/*
824	* Relocate the page table(s).
825	*/
826	pgmR3MapClearPDEs(&pVM->pgm.s, pMapping, iPDOld);
827	pgmR3MapSetPDEs(pVM, pMapping, iPDNew);
828
829	/*
830	* Update and resort the mapping list.
831	*/
832
833	/* Find previous mapping for pMapping, put result into pPrevMap. */
834	PPGMMAPPING pPrevMap = NULL;
835	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
836	while (pCur && pCur != pMapping)
837	{
838	/* next */
839	pPrevMap = pCur;
840	pCur = pCur->pNextR3;
841	}
842	Assert(pCur);
843
844	/* Find mapping which >= than pMapping. */
845	RTGCPTR GCPtrNew = iPDNew << X86_PD_SHIFT;
846	PPGMMAPPING pPrev = NULL;
847	pCur = pVM->pgm.s.pMappingsR3;
848	while (pCur && pCur->GCPtr < GCPtrNew)
849	{
850	/* next */
851	pPrev = pCur;
852	pCur = pCur->pNextR3;
853	}
854
855	if (pCur != pMapping && pPrev != pMapping)
856	{
857	/*
858	* Unlink.
859	*/
860	if (pPrevMap)
861	{
862	pPrevMap->pNextR3 = pMapping->pNextR3;
863	pPrevMap->pNextRC = pMapping->pNextRC;
864	pPrevMap->pNextR0 = pMapping->pNextR0;
865	}
866	else
867	{
868	pVM->pgm.s.pMappingsR3 = pMapping->pNextR3;
869	pVM->pgm.s.pMappingsRC = pMapping->pNextRC;
870	pVM->pgm.s.pMappingsR0 = pMapping->pNextR0;
871	}
872
873	/*
874	* Link
875	*/
876	pMapping->pNextR3 = pCur;
877	if (pPrev)
878	{
879	pMapping->pNextRC = pPrev->pNextRC;
880	pMapping->pNextR0 = pPrev->pNextR0;
881	pPrev->pNextR3 = pMapping;
882	pPrev->pNextRC = MMHyperR3ToRC(pVM, pMapping);
883	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pMapping);
884	}
885	else
886	{
887	pMapping->pNextRC = pVM->pgm.s.pMappingsRC;
888	pMapping->pNextR0 = pVM->pgm.s.pMappingsR0;
889	pVM->pgm.s.pMappingsR3 = pMapping;
890	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pMapping);
891	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pMapping);
892	}
893	}
894
895	/*
896	* Update the entry.
897	*/
898	pMapping->GCPtr = GCPtrNew;
899	pMapping->GCPtrLast = GCPtrNew + pMapping->cb - 1;
900
901	/*
902	* Callback to execute the relocation.
903	*/
904	pMapping->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pMapping->pvUser);
905	}
906
907
908	/**
909	* Resolves a conflict between a page table based GC mapping and
910	* the Guest OS page tables. (32 bits version)
911	*
912	* @returns VBox status code.
913	* @param pVM VM Handle.
914	* @param pMapping The mapping which conflicts.
915	* @param pPDSrc The page directory of the guest OS.
916	* @param GCPtrOldMapping The address of the start of the current mapping.
917	*/
918	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping)
919	{
920	STAM_PROFILE_START(&pVM->pgm.s.StatR3ResolveConflict, a);
921
922	/*
923	* Scan for free page directory entries.
924	*
925	* Note that we do not support mappings at the very end of the
926	* address space since that will break our GCPtrEnd assumptions.
927	*/
928	const unsigned cPTs = pMapping->cPTs;
929	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
930	while (iPDNew-- > 0)
931	{
932	if (pPDSrc->a[iPDNew].n.u1Present)
933	continue;
934	if (cPTs > 1)
935	{
936	bool fOk = true;
937	for (unsigned i = 1; fOk && i < cPTs; i++)
938	if (pPDSrc->a[iPDNew + i].n.u1Present)
939	fOk = false;
940	if (!fOk)
941	continue;
942	}
943
944	/*
945	* Check that it's not conflicting with an intermediate page table mapping.
946	*/
947	bool fOk = true;
948	unsigned i = cPTs;
949	while (fOk && i-- > 0)
950	fOk = !pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present;
951	if (!fOk)
952	continue;
953	/** @todo AMD64 should check the PAE directories and skip the 32bit stuff. */
954
955	/*
956	* Ask for the mapping.
957	*/
958	RTGCPTR GCPtrNewMapping = iPDNew << X86_PD_SHIFT;
959
960	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
961	{
962	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
963	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
964	return VINF_SUCCESS;
965	}
966	}
967
968	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
969	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, cPTs));
970	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
971	}
972
973
974	/**
975	* Resolves a conflict between a page table based GC mapping and
976	* the Guest OS page tables. (PAE bits version)
977	*
978	* @returns VBox status code.
979	* @param pVM VM Handle.
980	* @param pMapping The mapping which conflicts.
981	* @param GCPtrOldMapping The address of the start of the current mapping.
982	*/
983	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping)
984	{
985	STAM_PROFILE_START(&pVM->pgm.s.StatR3ResolveConflict, a);
986
987	for (int iPDPTE = X86_PG_PAE_PDPE_ENTRIES - 1; iPDPTE >= 0; iPDPTE--)
988	{
989	unsigned iPDSrc;
990	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCPTR32)iPDPTE << X86_PDPT_SHIFT, &iPDSrc, NULL);
991
992	/*
993	* Scan for free page directory entries.
994	*
995	* Note that we do not support mappings at the very end of the
996	* address space since that will break our GCPtrEnd assumptions.
997	* Nor do we support mappings crossing page directories.
998	*/
999	const unsigned cPTs = pMapping->cb >> X86_PD_PAE_SHIFT;
1000	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
1001
1002	while (iPDNew-- > 0)
1003	{
1004	/* Ugly assumption that mappings start on a 4 MB boundary. */
1005	if (iPDNew & 1)
1006	continue;
1007
1008	if (pPDSrc)
1009	{
1010	if (pPDSrc->a[iPDNew].n.u1Present)
1011	continue;
1012	if (cPTs > 1)
1013	{
1014	bool fOk = true;
1015	for (unsigned i = 1; fOk && i < cPTs; i++)
1016	if (pPDSrc->a[iPDNew + i].n.u1Present)
1017	fOk = false;
1018	if (!fOk)
1019	continue;
1020	}
1021	}
1022	/*
1023	* Check that it's not conflicting with an intermediate page table mapping.
1024	*/
1025	bool fOk = true;
1026	unsigned i = cPTs;
1027	while (fOk && i-- > 0)
1028	fOk = !pVM->pgm.s.apInterPaePDs[iPDPTE]->a[iPDNew + i].n.u1Present;
1029	if (!fOk)
1030	continue;
1031
1032	/*
1033	* Ask for the mapping.
1034	*/
1035	RTGCPTR GCPtrNewMapping = ((RTGCPTR32)iPDPTE << X86_PDPT_SHIFT) + (iPDNew << X86_PD_PAE_SHIFT);
1036
1037	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
1038	{
1039	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
1040	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1041	return VINF_SUCCESS;
1042	}
1043	}
1044	}
1045	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1046	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, pMapping->cb >> X86_PD_PAE_SHIFT));
1047	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
1048	}
1049
1050
1051	/**
1052	* Checks guest PD for conflicts with VMM GC mappings.
1053	*
1054	* @returns true if conflict detected.
1055	* @returns false if not.
1056	* @param pVM The virtual machine.
1057	* @param cr3 Guest context CR3 register.
1058	* @param fRawR0 Whether RawR0 is enabled or not.
1059	*/
1060	VMMR3DECL(bool) PGMR3MapHasConflicts(PVM pVM, uint64_t cr3, bool fRawR0) /** @todo how many HasConflict constructs do we really need? */
1061	{
1062	/*
1063	* Can skip this if mappings are safely fixed.
1064	*/
1065	if (pVM->pgm.s.fMappingsFixed)
1066	return false;
1067
1068	PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
1069	Assert(enmGuestMode <= PGMMODE_PAE_NX);
1070
1071	/*
1072	* Iterate mappings.
1073	*/
1074	if (enmGuestMode == PGMMODE_32_BIT)
1075	{
1076	/*
1077	* Resolve the page directory.
1078	*/
1079	PX86PD pPD = pVM->pgm.s.pGst32BitPdR3;
1080	Assert(pPD);
1081	Assert(pPD == (PX86PD)PGMPhysGCPhys2HCPtrAssert(pVM, cr3 & X86_CR3_PAGE_MASK, sizeof(*pPD)));
1082
1083	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1084	{
1085	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
1086	unsigned iPT = pCur->cPTs;
1087	while (iPT-- > 0)
1088	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
1089	&& (fRawR0 \|\| pPD->a[iPDE + iPT].n.u1User))
1090	{
1091	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
1092	Log(("PGMR3HasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
1093	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
1094	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
1095	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
1096	return true;
1097	}
1098	}
1099	}
1100	else if ( enmGuestMode == PGMMODE_PAE
1101	\|\| enmGuestMode == PGMMODE_PAE_NX)
1102	{
1103	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1104	{
1105	RTGCPTR GCPtr = pCur->GCPtr;
1106
1107	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
1108	while (iPT-- > 0)
1109	{
1110	X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
1111
1112	if ( Pde.n.u1Present
1113	&& (fRawR0 \|\| Pde.n.u1User))
1114	{
1115	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
1116	Log(("PGMR3HasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
1117	" PDE=%016RX64.\n",
1118	GCPtr, pCur->pszDesc, Pde.u));
1119	return true;
1120	}
1121	GCPtr += (1 << X86_PD_PAE_SHIFT);
1122	}
1123	}
1124	}
1125	else
1126	AssertFailed();
1127
1128	return false;
1129	}
1130
1131
1132	/**
1133	* Read memory from the guest mappings.
1134	*
1135	* This will use the page tables associated with the mappings to
1136	* read the memory. This means that not all kind of memory is readable
1137	* since we don't necessarily know how to convert that physical address
1138	* to a HC virtual one.
1139	*
1140	* @returns VBox status.
1141	* @param pVM VM handle.
1142	* @param pvDst The destination address (HC of course).
1143	* @param GCPtrSrc The source address (GC virtual address).
1144	* @param cb Number of bytes to read.
1145	*
1146	* @remarks The is indirectly for DBGF only.
1147	* @todo Consider renaming it to indicate it's special usage, or just
1148	* reimplement it in MMR3HyperReadGCVirt.
1149	*/
1150	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
1151	{
1152	/*
1153	* Simplicity over speed... Chop the request up into chunks
1154	* which don't cross pages.
1155	*/
1156	if (cb + (GCPtrSrc & PAGE_OFFSET_MASK) > PAGE_SIZE)
1157	{
1158	for (;;)
1159	{
1160	size_t cbRead = RT_MIN(cb, PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK));
1161	int rc = PGMR3MapRead(pVM, pvDst, GCPtrSrc, cbRead);
1162	if (RT_FAILURE(rc))
1163	return rc;
1164	cb -= cbRead;
1165	if (!cb)
1166	break;
1167	pvDst = (char *)pvDst + cbRead;
1168	GCPtrSrc += cbRead;
1169	}
1170	return VINF_SUCCESS;
1171	}
1172
1173	/*
1174	* Find the mapping.
1175	*/
1176	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
1177	while (pCur)
1178	{
1179	RTGCPTR off = GCPtrSrc - pCur->GCPtr;
1180	if (off < pCur->cb)
1181	{
1182	if (off + cb > pCur->cb)
1183	{
1184	AssertMsgFailed(("Invalid page range %RGv LB%#x. mapping '%s' %RGv to %RGv\n",
1185	GCPtrSrc, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast));
1186	return VERR_INVALID_PARAMETER;
1187	}
1188
1189	unsigned iPT = off >> X86_PD_SHIFT;
1190	unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
1191	while (cb > 0 && iPTE < RT_ELEMENTS(CTXALLSUFF(pCur->aPTs[iPT].pPT)->a))
1192	{
1193	if (!CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].n.u1Present)
1194	return VERR_PAGE_NOT_PRESENT;
1195	RTHCPHYS HCPhys = CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].u & X86_PTE_PAE_PG_MASK;
1196
1197	/*
1198	* Get the virtual page from the physical one.
1199	*/
1200	void *pvPage;
1201	int rc = MMR3HCPhys2HCVirt(pVM, HCPhys, &pvPage);
1202	if (RT_FAILURE(rc))
1203	return rc;
1204
1205	memcpy(pvDst, (char *)pvPage + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
1206	return VINF_SUCCESS;
1207	}
1208	}
1209
1210	/* next */
1211	pCur = CTXALLSUFF(pCur->pNext);
1212	}
1213
1214	return VERR_INVALID_POINTER;
1215	}
1216
1217
1218	/**
1219	* Info callback for 'pgmhandlers'.
1220	*
1221	* @param pHlp The output helpers.
1222	* @param pszArgs The arguments. phys or virt.
1223	*/
1224	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1225	{
1226	pHlp->pfnPrintf(pHlp, pVM->pgm.s.fMappingsFixed
1227	? "\nThe mappings are FIXED.\n"
1228	: "\nThe mappings are FLOATING.\n");
1229	PPGMMAPPING pCur;
1230	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1231	pHlp->pfnPrintf(pHlp, "%RGv - %RGv %s\n", pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
1232	}
1233

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/PGMMap.cpp@ 14257

Download in other formats: