PGMMap.cpp@ 14740

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1	/* $Id: PGMMap.cpp 14716 2008-11-27 15:51:16Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager, Guest Context Mappings.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/dbgf.h>
28	#include <VBox/pgm.h>
29	#include "PGMInternal.h"
30	#include <VBox/vm.h>
31
32	#include <VBox/log.h>
33	#include <VBox/err.h>
34	#include <iprt/asm.h>
35	#include <iprt/assert.h>
36	#include <iprt/string.h>
37
38
39	/*******************************************************************************
40	* Internal Functions *
41	*******************************************************************************/
42	static void pgmR3MapClearPDEs(PPGM pPGM, PPGMMAPPING pMap, unsigned iOldPDE);
43	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
44	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
45	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
46
47
48
49	/**
50	* Creates a page table based mapping in GC.
51	*
52	* @returns VBox status code.
53	* @param pVM VM Handle.
54	* @param GCPtr Virtual Address. (Page table aligned!)
55	* @param cb Size of the range. Must be a 4MB aligned!
56	* @param pfnRelocate Relocation callback function.
57	* @param pvUser User argument to the callback.
58	* @param pszDesc Pointer to description string. This must not be freed.
59	*/
60	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc)
61	{
62	LogFlow(("PGMR3MapPT: GCPtr=%#x cb=%d pfnRelocate=%p pvUser=%p pszDesc=%s\n", GCPtr, cb, pfnRelocate, pvUser, pszDesc));
63	AssertMsg(pVM->pgm.s.pInterPD && pVM->pgm.s.pShw32BitPdR3, ("Paging isn't initialized, init order problems!\n"));
64
65	/*
66	* Validate input.
67	*/
68	if (cb < _2M \|\| cb > 64 * _1M)
69	{
70	AssertMsgFailed(("Serious? cb=%d\n", cb));
71	return VERR_INVALID_PARAMETER;
72	}
73	cb = RT_ALIGN_32(cb, _4M);
74	RTGCPTR GCPtrLast = GCPtr + cb - 1;
75	if (GCPtrLast < GCPtr)
76	{
77	AssertMsgFailed(("Range wraps! GCPtr=%x GCPtrLast=%x\n", GCPtr, GCPtrLast));
78	return VERR_INVALID_PARAMETER;
79	}
80	if (pVM->pgm.s.fMappingsFixed)
81	{
82	AssertMsgFailed(("Mappings are fixed! It's not possible to add new mappings at this time!\n"));
83	return VERR_PGM_MAPPINGS_FIXED;
84	}
85	if (!pfnRelocate)
86	{
87	AssertMsgFailed(("Callback is required\n"));
88	return VERR_INVALID_PARAMETER;
89	}
90
91	/*
92	* Find list location.
93	*/
94	PPGMMAPPING pPrev = NULL;
95	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
96	while (pCur)
97	{
98	if (pCur->GCPtrLast >= GCPtr && pCur->GCPtr <= GCPtrLast)
99	{
100	AssertMsgFailed(("Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
101	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
102	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
103	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
104	return VERR_PGM_MAPPING_CONFLICT;
105	}
106	if (pCur->GCPtr > GCPtr)
107	break;
108	pPrev = pCur;
109	pCur = pCur->pNextR3;
110	}
111
112	/*
113	* Check for conflicts with intermediate mappings.
114	*/
115	const unsigned iPageDir = GCPtr >> X86_PD_SHIFT;
116	const unsigned cPTs = cb >> X86_PD_SHIFT;
117	unsigned i;
118	for (i = 0; i < cPTs; i++)
119	{
120	if (pVM->pgm.s.pInterPD->a[iPageDir + i].n.u1Present)
121	{
122	AssertMsgFailed(("Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
123	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
124	return VERR_PGM_MAPPING_CONFLICT;
125	}
126	}
127	/** @todo AMD64: add check in PAE structures too, so we can remove all the 32-Bit paging stuff there. */
128
129	/*
130	* Allocate and initialize the new list node.
131	*/
132	PPGMMAPPING pNew;
133	int rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMMAPPING, aPTs[cPTs]), 0, MM_TAG_PGM, (void **)&pNew);
134	if (RT_FAILURE(rc))
135	return rc;
136	pNew->GCPtr = GCPtr;
137	pNew->GCPtrLast = GCPtrLast;
138	pNew->cb = cb;
139	pNew->pszDesc = pszDesc;
140	pNew->pfnRelocate = pfnRelocate;
141	pNew->pvUser = pvUser;
142	pNew->cPTs = cPTs;
143
144	/*
145	* Allocate page tables and insert them into the page directories.
146	* (One 32-bit PT and two PAE PTs.)
147	*/
148	uint8_t *pbPTs;
149	rc = MMHyperAlloc(pVM, PAGE_SIZE * 3 * cPTs, PAGE_SIZE, MM_TAG_PGM, (void **)&pbPTs);
150	if (RT_FAILURE(rc))
151	{
152	MMHyperFree(pVM, pNew);
153	return VERR_NO_MEMORY;
154	}
155
156	/*
157	* Init the page tables and insert them into the page directories.
158	*/
159	Log4(("PGMR3MapPT: GCPtr=%RGv cPTs=%u pbPTs=%p\n", GCPtr, cPTs, pbPTs));
160	for (i = 0; i < cPTs; i++)
161	{
162	/*
163	* 32-bit.
164	*/
165	pNew->aPTs[i].pPTR3 = (PX86PT)pbPTs;
166	pNew->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pNew->aPTs[i].pPTR3);
167	pNew->aPTs[i].pPTR0 = MMHyperR3ToR0(pVM, pNew->aPTs[i].pPTR3);
168	pNew->aPTs[i].HCPhysPT = MMR3HyperHCVirt2HCPhys(pVM, pNew->aPTs[i].pPTR3);
169	pbPTs += PAGE_SIZE;
170	Log4(("PGMR3MapPT: i=%d: pPTR3=%RHv pPTRC=%RRv pPRTR0=%RHv HCPhysPT=%RHp\n",
171	i, pNew->aPTs[i].pPTR3, pNew->aPTs[i].pPTRC, pNew->aPTs[i].pPTR0, pNew->aPTs[i].HCPhysPT));
172
173	/*
174	* PAE.
175	*/
176	pNew->aPTs[i].HCPhysPaePT0 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs);
177	pNew->aPTs[i].HCPhysPaePT1 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs + PAGE_SIZE);
178	pNew->aPTs[i].paPaePTsR3 = (PX86PTPAE)pbPTs;
179	pNew->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pbPTs);
180	pNew->aPTs[i].paPaePTsR0 = MMHyperR3ToR0(pVM, pbPTs);
181	pbPTs += PAGE_SIZE * 2;
182	Log4(("PGMR3MapPT: i=%d: paPaePTsR#=%RHv paPaePTsRC=%RRv paPaePTsR#=%RHv HCPhysPaePT0=%RHp HCPhysPaePT1=%RHp\n",
183	i, pNew->aPTs[i].paPaePTsR3, pNew->aPTs[i].paPaePTsRC, pNew->aPTs[i].paPaePTsR0, pNew->aPTs[i].HCPhysPaePT0, pNew->aPTs[i].HCPhysPaePT1));
184	}
185	pgmR3MapSetPDEs(pVM, pNew, iPageDir);
186
187	/*
188	* Insert the new mapping.
189	*/
190	pNew->pNextR3 = pCur;
191	pNew->pNextRC = pCur ? MMHyperR3ToRC(pVM, pCur) : NIL_RTRCPTR;
192	pNew->pNextR0 = pCur ? MMHyperR3ToR0(pVM, pCur) : NIL_RTR0PTR;
193	if (pPrev)
194	{
195	pPrev->pNextR3 = pNew;
196	pPrev->pNextRC = MMHyperR3ToRC(pVM, pNew);
197	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pNew);
198	}
199	else
200	{
201	pVM->pgm.s.pMappingsR3 = pNew;
202	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pNew);
203	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pNew);
204	}
205
206	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
207	return VINF_SUCCESS;
208	}
209
210
211	/**
212	* Removes a page table based mapping.
213	*
214	* @returns VBox status code.
215	* @param pVM VM Handle.
216	* @param GCPtr Virtual Address. (Page table aligned!)
217	*/
218	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr)
219	{
220	LogFlow(("PGMR3UnmapPT: GCPtr=%#x\n", GCPtr));
221
222	/*
223	* Find it.
224	*/
225	PPGMMAPPING pPrev = NULL;
226	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
227	while (pCur)
228	{
229	if (pCur->GCPtr == GCPtr)
230	{
231	/*
232	* Unlink it.
233	*/
234	if (pPrev)
235	{
236	pPrev->pNextR3 = pCur->pNextR3;
237	pPrev->pNextRC = pCur->pNextRC;
238	pPrev->pNextR0 = pCur->pNextR0;
239	}
240	else
241	{
242	pVM->pgm.s.pMappingsR3 = pCur->pNextR3;
243	pVM->pgm.s.pMappingsRC = pCur->pNextRC;
244	pVM->pgm.s.pMappingsR0 = pCur->pNextR0;
245	}
246
247	/*
248	* Free the page table memory, clear page directory entries
249	* and free the page tables and node memory.
250	*/
251	MMHyperFree(pVM, pCur->aPTs[0].pPTR3);
252	pgmR3MapClearPDEs(&pVM->pgm.s, pCur, pCur->GCPtr >> X86_PD_SHIFT);
253	MMHyperFree(pVM, pCur);
254
255	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
256	return VINF_SUCCESS;
257	}
258
259	/* done? */
260	if (pCur->GCPtr > GCPtr)
261	break;
262
263	/* next */
264	pPrev = pCur;
265	pCur = pCur->pNextR3;
266	}
267
268	AssertMsgFailed(("No mapping for %#x found!\n", GCPtr));
269	return VERR_INVALID_PARAMETER;
270	}
271
272
273	/**
274	* Gets the size of the current guest mappings if they were to be
275	* put next to oneanother.
276	*
277	* @returns VBox status code.
278	* @param pVM The VM.
279	* @param pcb Where to store the size.
280	*/
281	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb)
282	{
283	RTGCPTR cb = 0;
284	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
285	cb += pCur->cb;
286
287	*pcb = cb;
288	AssertReturn(*pcb == cb, VERR_NUMBER_TOO_BIG);
289	Log(("PGMR3MappingsSize: return %d (%#x) bytes\n", cb, cb));
290	return VINF_SUCCESS;
291	}
292
293
294	/**
295	* Fixes the guest context mappings in a range reserved from the Guest OS.
296	*
297	* @returns VBox status code.
298	* @param pVM The VM.
299	* @param GCPtrBase The address of the reserved range of guest memory.
300	* @param cb The size of the range starting at GCPtrBase.
301	*/
302	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb)
303	{
304	Log(("PGMR3MappingsFix: GCPtrBase=%#x cb=%#x\n", GCPtrBase, cb));
305
306	/* Ignore the additions mapping fix call in VT-x/AMD-V. */
307	if ( pVM->pgm.s.fMappingsFixed
308	&& HWACCMR3IsActive(pVM))
309	return VINF_SUCCESS;
310
311	/*
312	* This is all or nothing at all. So, a tiny bit of paranoia first.
313	*/
314	if (GCPtrBase & X86_PAGE_4M_OFFSET_MASK)
315	{
316	AssertMsgFailed(("GCPtrBase (%#x) has to be aligned on a 4MB address!\n", GCPtrBase));
317	return VERR_INVALID_PARAMETER;
318	}
319	if (!cb \|\| (cb & X86_PAGE_4M_OFFSET_MASK))
320	{
321	AssertMsgFailed(("cb (%#x) is 0 or not aligned on a 4MB address!\n", cb));
322	return VERR_INVALID_PARAMETER;
323	}
324
325	/*
326	* Before we do anything we'll do a forced PD sync to try make sure any
327	* pending relocations because of these mappings have been resolved.
328	*/
329	PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), true);
330
331	/*
332	* Check that it's not conflicting with a core code mapping in the intermediate page table.
333	*/
334	unsigned iPDNew = GCPtrBase >> X86_PD_SHIFT;
335	unsigned i = cb >> X86_PD_SHIFT;
336	while (i-- > 0)
337	{
338	if (pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present)
339	{
340	/* Check that it's not one or our mappings. */
341	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
342	while (pCur)
343	{
344	if (iPDNew + i - (pCur->GCPtr >> X86_PD_SHIFT) < (pCur->cb >> X86_PD_SHIFT))
345	break;
346	pCur = pCur->pNextR3;
347	}
348	if (!pCur)
349	{
350	LogRel(("PGMR3MappingsFix: Conflicts with intermediate PDE %#x (GCPtrBase=%RGv cb=%#zx). The guest should retry.\n",
351	iPDNew + i, GCPtrBase, cb));
352	return VERR_PGM_MAPPINGS_FIX_CONFLICT;
353	}
354	}
355	}
356
357	/*
358	* In PAE / PAE mode, make sure we don't cross page directories.
359	*/
360	if ( ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
361	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX)
362	&& ( pVM->pgm.s.enmShadowMode == PGMMODE_PAE
363	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX))
364	{
365	unsigned iPdptBase = GCPtrBase >> X86_PDPT_SHIFT;
366	unsigned iPdptLast = (GCPtrBase + cb - 1) >> X86_PDPT_SHIFT;
367	if (iPdptBase != iPdptLast)
368	{
369	LogRel(("PGMR3MappingsFix: Crosses PD boundrary; iPdptBase=%#x iPdptLast=%#x (GCPtrBase=%RGv cb=%#zx). The guest should retry.\n",
370	iPdptBase, iPdptLast, GCPtrBase, cb));
371	return VERR_PGM_MAPPINGS_FIX_CONFLICT;
372	}
373	}
374
375	/*
376	* Loop the mappings and check that they all agree on their new locations.
377	*/
378	RTGCPTR GCPtrCur = GCPtrBase;
379	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
380	while (pCur)
381	{
382	if (!pCur->pfnRelocate(pVM, pCur->GCPtr, GCPtrCur, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
383	{
384	AssertMsgFailed(("The suggested fixed address %#x was rejected by '%s'!\n", GCPtrCur, pCur->pszDesc));
385	return VERR_PGM_MAPPINGS_FIX_REJECTED;
386	}
387	/* next */
388	GCPtrCur += pCur->cb;
389	pCur = pCur->pNextR3;
390	}
391	if (GCPtrCur > GCPtrBase + cb)
392	{
393	AssertMsgFailed(("cb (%#x) is less than the required range %#x!\n", cb, GCPtrCur - GCPtrBase));
394	return VERR_PGM_MAPPINGS_FIX_TOO_SMALL;
395	}
396
397	/*
398	* Loop the table assigning the mappings to the passed in memory
399	* and call their relocator callback.
400	*/
401	GCPtrCur = GCPtrBase;
402	pCur = pVM->pgm.s.pMappingsR3;
403	while (pCur)
404	{
405	unsigned iPDOld = pCur->GCPtr >> X86_PD_SHIFT;
406	iPDNew = GCPtrCur >> X86_PD_SHIFT;
407
408	/*
409	* Relocate the page table(s).
410	*/
411	pgmR3MapClearPDEs(&pVM->pgm.s, pCur, iPDOld);
412	pgmR3MapSetPDEs(pVM, pCur, iPDNew);
413
414	/*
415	* Update the entry.
416	*/
417	pCur->GCPtr = GCPtrCur;
418	pCur->GCPtrLast = GCPtrCur + pCur->cb - 1;
419
420	/*
421	* Callback to execute the relocation.
422	*/
423	pCur->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pCur->pvUser);
424
425	/*
426	* Advance.
427	*/
428	GCPtrCur += pCur->cb;
429	pCur = pCur->pNextR3;
430	}
431
432	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
433	/*
434	* Turn off CR3 updating monitoring.
435	*/
436	int rc2 = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
437	AssertRC(rc2);
438	#endif
439
440	/*
441	* Mark the mappings as fixed and return.
442	*/
443	pVM->pgm.s.fMappingsFixed = true;
444	pVM->pgm.s.GCPtrMappingFixed = GCPtrBase;
445	pVM->pgm.s.cbMappingFixed = cb;
446	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
447	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
448	return VINF_SUCCESS;
449	}
450
451
452	/**
453	* Unfixes the mappings.
454	* After calling this function mapping conflict detection will be enabled.
455	*
456	* @returns VBox status code.
457	* @param pVM The VM.
458	*/
459	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM)
460	{
461	Log(("PGMR3MappingsUnfix: fMappingsFixed=%d\n", pVM->pgm.s.fMappingsFixed));
462
463	/* Refuse in VT-x/AMD-V mode. */
464	if (HWACCMR3IsActive(pVM))
465	return VINF_SUCCESS;
466
467	pVM->pgm.s.fMappingsFixed = false;
468	pVM->pgm.s.GCPtrMappingFixed = 0;
469	pVM->pgm.s.cbMappingFixed = 0;
470	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
471
472	/*
473	* Re-enable the CR3 monitoring.
474	*
475	* Paranoia: We flush the page pool before doing that because Windows
476	* is using the CR3 page both as a PD and a PT, e.g. the pool may
477	* be monitoring it.
478	*/
479	#ifdef PGMPOOL_WITH_MONITORING
480	pgmPoolFlushAll(pVM);
481	#endif
482	/* Remap CR3 as we have just flushed the CR3 shadow PML4 in case we're in long mode. */
483	int rc = PGM_GST_PFN(MapCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
484	AssertRC(rc);
485
486	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
487	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
488	AssertRC(rc);
489	#endif
490	return VINF_SUCCESS;
491	}
492
493
494	/**
495	* Map pages into the intermediate context (switcher code).
496	* These pages are mapped at both the give virtual address and at
497	* the physical address (for identity mapping).
498	*
499	* @returns VBox status code.
500	* @param pVM The virtual machine.
501	* @param Addr Intermediate context address of the mapping.
502	* @param HCPhys Start of the range of physical pages. This must be entriely below 4GB!
503	* @param cbPages Number of bytes to map.
504	*
505	* @remark This API shall not be used to anything but mapping the switcher code.
506	*/
507	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages)
508	{
509	LogFlow(("PGMR3MapIntermediate: Addr=%RTptr HCPhys=%RHp cbPages=%#x\n", Addr, HCPhys, cbPages));
510
511	/*
512	* Adjust input.
513	*/
514	cbPages += (uint32_t)HCPhys & PAGE_OFFSET_MASK;
515	cbPages = RT_ALIGN(cbPages, PAGE_SIZE);
516	HCPhys &= X86_PTE_PAE_PG_MASK;
517	Addr &= PAGE_BASE_MASK;
518	/* We only care about the first 4GB, because on AMD64 we'll be repeating them all over the address space. */
519	uint32_t uAddress = (uint32_t)Addr;
520
521	/*
522	* Assert input and state.
523	*/
524	AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
525	AssertMsg(pVM->pgm.s.pInterPD, ("Bad init order, paging.\n"));
526	AssertMsg(cbPages <= (512 << PAGE_SHIFT), ("The mapping is too big %d bytes\n", cbPages));
527	AssertMsg(HCPhys < _4G && HCPhys + cbPages < _4G, ("Addr=%RTptr HCPhys=%RHp cbPages=%d\n", Addr, HCPhys, cbPages));
528
529	/*
530	* Check for internal conflicts between the virtual address and the physical address.
531	*/
532	if ( uAddress != HCPhys
533	&& ( uAddress < HCPhys
534	? HCPhys - uAddress < cbPages
535	: uAddress - HCPhys < cbPages
536	)
537	)
538	AssertLogRelMsgFailedReturn(("Addr=%RTptr HCPhys=%RHp cbPages=%d\n", Addr, HCPhys, cbPages),
539	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
540
541	/* The intermediate mapping must not conflict with our default hypervisor address. */
542	size_t cbHyper;
543	RTGCPTR pvHyperGC = MMHyperGetArea(pVM, &cbHyper);
544	if (uAddress < pvHyperGC
545	? uAddress + cbPages > pvHyperGC
546	: pvHyperGC + cbHyper > uAddress
547	)
548	AssertLogRelMsgFailedReturn(("Addr=%RTptr HyperGC=%RGv cbPages=%zu\n", Addr, pvHyperGC, cbPages),
549	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
550
551	const unsigned cPages = cbPages >> PAGE_SHIFT;
552	int rc = pgmR3MapIntermediateCheckOne(pVM, uAddress, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
553	if (RT_FAILURE(rc))
554	return rc;
555	rc = pgmR3MapIntermediateCheckOne(pVM, (uintptr_t)HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
556	if (RT_FAILURE(rc))
557	return rc;
558
559	/*
560	* Everythings fine, do the mapping.
561	*/
562	pgmR3MapIntermediateDoOne(pVM, uAddress, HCPhys, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
563	pgmR3MapIntermediateDoOne(pVM, (uintptr_t)HCPhys, HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
564
565	return VINF_SUCCESS;
566	}
567
568
569	/**
570	* Validates that there are no conflicts for this mapping into the intermediate context.
571	*
572	* @returns VBox status code.
573	* @param pVM VM handle.
574	* @param uAddress Address of the mapping.
575	* @param cPages Number of pages.
576	* @param pPTDefault Pointer to the default page table for this mapping.
577	* @param pPTPaeDefault Pointer to the default page table for this mapping.
578	*/
579	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
580	{
581	AssertMsg((uAddress >> X86_PD_SHIFT) + cPages <= 1024, ("64-bit fixme\n"));
582
583	/*
584	* Check that the ranges are available.
585	* (This code doesn't have to be fast.)
586	*/
587	while (cPages > 0)
588	{
589	/*
590	* 32-Bit.
591	*/
592	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
593	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
594	PX86PT pPT = pPTDefault;
595	if (pVM->pgm.s.pInterPD->a[iPDE].u)
596	{
597	RTHCPHYS HCPhysPT = pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK;
598	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]))
599	pPT = pVM->pgm.s.apInterPTs[0];
600	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]))
601	pPT = pVM->pgm.s.apInterPTs[1];
602	else
603	{
604	/** @todo this must be handled with a relocation of the conflicting mapping!
605	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
606	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%RHv\n", uAddress),
607	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
608	}
609	}
610	if (pPT->a[iPTE].u)
611	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%RHv pPT->a[iPTE].u=%RX32\n", iPTE, iPDE, uAddress, pPT->a[iPTE].u),
612	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
613
614	/*
615	* PAE.
616	*/
617	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
618	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
619	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
620	Assert(iPDPE < 4);
621	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
622	PX86PTPAE pPTPae = pPTPaeDefault;
623	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
624	{
625	RTHCPHYS HCPhysPT = pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK;
626	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
627	pPTPae = pVM->pgm.s.apInterPaePTs[0];
628	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
629	pPTPae = pVM->pgm.s.apInterPaePTs[1];
630	else
631	{
632	/** @todo this must be handled with a relocation of the conflicting mapping!
633	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
634	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%RHv\n", uAddress),
635	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
636	}
637	}
638	if (pPTPae->a[iPTE].u)
639	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%RHv pPTPae->a[iPTE].u=%#RX64\n", iPTE, iPDE, uAddress, pPTPae->a[iPTE].u),
640	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
641
642	/* next */
643	uAddress += PAGE_SIZE;
644	cPages--;
645	}
646
647	return VINF_SUCCESS;
648	}
649
650
651
652	/**
653	* Sets up the intermediate page tables for a verified mapping.
654	*
655	* @param pVM VM handle.
656	* @param uAddress Address of the mapping.
657	* @param HCPhys The physical address of the page range.
658	* @param cPages Number of pages.
659	* @param pPTDefault Pointer to the default page table for this mapping.
660	* @param pPTPaeDefault Pointer to the default page table for this mapping.
661	*/
662	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
663	{
664	while (cPages > 0)
665	{
666	/*
667	* 32-Bit.
668	*/
669	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
670	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
671	PX86PT pPT;
672	if (pVM->pgm.s.pInterPD->a[iPDE].u)
673	pPT = (PX86PT)MMPagePhys2Page(pVM, pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK);
674	else
675	{
676	pVM->pgm.s.pInterPD->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
677	\| (uint32_t)MMPage2Phys(pVM, pPTDefault);
678	pPT = pPTDefault;
679	}
680	pPT->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| (uint32_t)HCPhys;
681
682	/*
683	* PAE
684	*/
685	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
686	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
687	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
688	Assert(iPDPE < 4);
689	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
690	PX86PTPAE pPTPae;
691	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
692	pPTPae = (PX86PTPAE)MMPagePhys2Page(pVM, pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK);
693	else
694	{
695	pPTPae = pPTPaeDefault;
696	pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
697	\| MMPage2Phys(pVM, pPTPaeDefault);
698	}
699	pPTPae->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| HCPhys;
700
701	/* next */
702	cPages--;
703	HCPhys += PAGE_SIZE;
704	uAddress += PAGE_SIZE;
705	}
706	}
707
708
709	/**
710	* Clears all PDEs involved with the mapping.
711	*
712	* @param pPGM Pointer to the PGM instance data.
713	* @param pMap Pointer to the mapping in question.
714	* @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
715	*/
716	static void pgmR3MapClearPDEs(PPGM pPGM, PPGMMAPPING pMap, unsigned iOldPDE)
717	{
718	unsigned i = pMap->cPTs;
719	iOldPDE += i;
720	while (i-- > 0)
721	{
722	iOldPDE--;
723
724	/*
725	* 32-bit.
726	*/
727	pPGM->pInterPD->a[iOldPDE].u = 0;
728	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
729	pPGM->pShw32BitPdR3->a[iOldPDE].u = 0;
730	#endif
731	/*
732	* PAE.
733	*/
734	const unsigned iPD = iOldPDE / 256;
735	unsigned iPDE = iOldPDE * 2 % 512;
736	pPGM->apInterPaePDs[iPD]->a[iPDE].u = 0;
737	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
738	pPGM->apShwPaePDsR3[iPD]->a[iPDE].u = 0;
739	#endif
740	iPDE++;
741	pPGM->apInterPaePDs[iPD]->a[iPDE].u = 0;
742	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
743	pPGM->apShwPaePDsR3[iPD]->a[iPDE].u = 0;
744
745	/* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode) */
746	pPGM->pShwPaePdptR3->a[iPD].u &= ~PGM_PLXFLAGS_MAPPING;
747	#endif
748	}
749	}
750
751
752	/**
753	* Sets all PDEs involved with the mapping.
754	*
755	* @param pVM The VM handle.
756	* @param pMap Pointer to the mapping in question.
757	* @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
758	*/
759	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
760	{
761	PPGM pPGM = &pVM->pgm.s;
762
763	/* If mappings are not supposed to be put in the shadow page table, then this function is a nop. */
764	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
765	return;
766
767	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE_NX);
768
769	/*
770	* Init the page tables and insert them into the page directories.
771	*/
772	unsigned i = pMap->cPTs;
773	iNewPDE += i;
774	while (i-- > 0)
775	{
776	iNewPDE--;
777
778	/*
779	* 32-bit.
780	*/
781	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
782	if (pPGM->pShw32BitPdR3->a[iNewPDE].n.u1Present)
783	pgmPoolFree(pVM, pPGM->pShw32BitPdR3->a[iNewPDE].u & X86_PDE_PG_MASK, PGMPOOL_IDX_PD, iNewPDE);
784	#endif
785	X86PDE Pde;
786	/* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
787	Pde.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT;
788	pPGM->pInterPD->a[iNewPDE] = Pde;
789	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
790	pPGM->pShw32BitPdR3->a[iNewPDE] = Pde;
791	#endif
792	/*
793	* PAE.
794	*/
795	const unsigned iPD = iNewPDE / 256;
796	unsigned iPDE = iNewPDE * 2 % 512;
797	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
798	if (pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present)
799	pgmPoolFree(pVM, pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2);
800	#endif
801	X86PDEPAE PdePae0;
802	PdePae0.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0;
803	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae0;
804	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
805	pPGM->apShwPaePDsR3[iPD]->a[iPDE] = PdePae0;
806	#endif
807	iPDE++;
808	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
809	if (pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present)
810	pgmPoolFree(pVM, pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2 + 1);
811	#endif
812	X86PDEPAE PdePae1;
813	PdePae1.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1;
814	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae1;
815	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
816	pPGM->apShwPaePDsR3[iPD]->a[iPDE] = PdePae1;
817
818	/* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode) */
819	pPGM->pShwPaePdptR3->a[iPD].u \|= PGM_PLXFLAGS_MAPPING;
820	#endif
821	}
822	}
823
824
825	/**
826	* Relocates a mapping to a new address.
827	*
828	* @param pVM VM handle.
829	* @param pMapping The mapping to relocate.
830	* @param GCPtrOldMapping The address of the start of the old mapping.
831	* @param GCPtrNewMapping The address of the start of the new mapping.
832	*/
833	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping)
834	{
835	unsigned iPDOld = GCPtrOldMapping >> X86_PD_SHIFT;
836	unsigned iPDNew = GCPtrNewMapping >> X86_PD_SHIFT;
837
838	Log(("PGM: Relocating %s from %RGv to %RGv\n", pMapping->pszDesc, GCPtrOldMapping, GCPtrNewMapping));
839	Assert(((unsigned)iPDOld << X86_PD_SHIFT) == pMapping->GCPtr);
840
841	/*
842	* Relocate the page table(s).
843	*/
844	pgmR3MapClearPDEs(&pVM->pgm.s, pMapping, iPDOld);
845	pgmR3MapSetPDEs(pVM, pMapping, iPDNew);
846
847	/*
848	* Update and resort the mapping list.
849	*/
850
851	/* Find previous mapping for pMapping, put result into pPrevMap. */
852	PPGMMAPPING pPrevMap = NULL;
853	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
854	while (pCur && pCur != pMapping)
855	{
856	/* next */
857	pPrevMap = pCur;
858	pCur = pCur->pNextR3;
859	}
860	Assert(pCur);
861
862	/* Find mapping which >= than pMapping. */
863	RTGCPTR GCPtrNew = iPDNew << X86_PD_SHIFT;
864	PPGMMAPPING pPrev = NULL;
865	pCur = pVM->pgm.s.pMappingsR3;
866	while (pCur && pCur->GCPtr < GCPtrNew)
867	{
868	/* next */
869	pPrev = pCur;
870	pCur = pCur->pNextR3;
871	}
872
873	if (pCur != pMapping && pPrev != pMapping)
874	{
875	/*
876	* Unlink.
877	*/
878	if (pPrevMap)
879	{
880	pPrevMap->pNextR3 = pMapping->pNextR3;
881	pPrevMap->pNextRC = pMapping->pNextRC;
882	pPrevMap->pNextR0 = pMapping->pNextR0;
883	}
884	else
885	{
886	pVM->pgm.s.pMappingsR3 = pMapping->pNextR3;
887	pVM->pgm.s.pMappingsRC = pMapping->pNextRC;
888	pVM->pgm.s.pMappingsR0 = pMapping->pNextR0;
889	}
890
891	/*
892	* Link
893	*/
894	pMapping->pNextR3 = pCur;
895	if (pPrev)
896	{
897	pMapping->pNextRC = pPrev->pNextRC;
898	pMapping->pNextR0 = pPrev->pNextR0;
899	pPrev->pNextR3 = pMapping;
900	pPrev->pNextRC = MMHyperR3ToRC(pVM, pMapping);
901	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pMapping);
902	}
903	else
904	{
905	pMapping->pNextRC = pVM->pgm.s.pMappingsRC;
906	pMapping->pNextR0 = pVM->pgm.s.pMappingsR0;
907	pVM->pgm.s.pMappingsR3 = pMapping;
908	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pMapping);
909	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pMapping);
910	}
911	}
912
913	/*
914	* Update the entry.
915	*/
916	pMapping->GCPtr = GCPtrNew;
917	pMapping->GCPtrLast = GCPtrNew + pMapping->cb - 1;
918
919	/*
920	* Callback to execute the relocation.
921	*/
922	pMapping->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pMapping->pvUser);
923	}
924
925
926	/**
927	* Resolves a conflict between a page table based GC mapping and
928	* the Guest OS page tables. (32 bits version)
929	*
930	* @returns VBox status code.
931	* @param pVM VM Handle.
932	* @param pMapping The mapping which conflicts.
933	* @param pPDSrc The page directory of the guest OS.
934	* @param GCPtrOldMapping The address of the start of the current mapping.
935	*/
936	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping)
937	{
938	STAM_PROFILE_START(&pVM->pgm.s.StatR3ResolveConflict, a);
939
940	/*
941	* Scan for free page directory entries.
942	*
943	* Note that we do not support mappings at the very end of the
944	* address space since that will break our GCPtrEnd assumptions.
945	*/
946	const unsigned cPTs = pMapping->cPTs;
947	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
948	while (iPDNew-- > 0)
949	{
950	if (pPDSrc->a[iPDNew].n.u1Present)
951	continue;
952	if (cPTs > 1)
953	{
954	bool fOk = true;
955	for (unsigned i = 1; fOk && i < cPTs; i++)
956	if (pPDSrc->a[iPDNew + i].n.u1Present)
957	fOk = false;
958	if (!fOk)
959	continue;
960	}
961
962	/*
963	* Check that it's not conflicting with an intermediate page table mapping.
964	*/
965	bool fOk = true;
966	unsigned i = cPTs;
967	while (fOk && i-- > 0)
968	fOk = !pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present;
969	if (!fOk)
970	continue;
971	/** @todo AMD64 should check the PAE directories and skip the 32bit stuff. */
972
973	/*
974	* Ask for the mapping.
975	*/
976	RTGCPTR GCPtrNewMapping = iPDNew << X86_PD_SHIFT;
977
978	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
979	{
980	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
981	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
982	return VINF_SUCCESS;
983	}
984	}
985
986	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
987	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, cPTs));
988	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
989	}
990
991
992	/**
993	* Resolves a conflict between a page table based GC mapping and
994	* the Guest OS page tables. (PAE bits version)
995	*
996	* @returns VBox status code.
997	* @param pVM VM Handle.
998	* @param pMapping The mapping which conflicts.
999	* @param GCPtrOldMapping The address of the start of the current mapping.
1000	*/
1001	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping)
1002	{
1003	STAM_PROFILE_START(&pVM->pgm.s.StatR3ResolveConflict, a);
1004
1005	for (int iPDPTE = X86_PG_PAE_PDPE_ENTRIES - 1; iPDPTE >= 0; iPDPTE--)
1006	{
1007	unsigned iPDSrc;
1008	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCPTR32)iPDPTE << X86_PDPT_SHIFT, &iPDSrc, NULL);
1009
1010	/*
1011	* Scan for free page directory entries.
1012	*
1013	* Note that we do not support mappings at the very end of the
1014	* address space since that will break our GCPtrEnd assumptions.
1015	* Nor do we support mappings crossing page directories.
1016	*/
1017	const unsigned cPTs = pMapping->cb >> X86_PD_PAE_SHIFT;
1018	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
1019
1020	while (iPDNew-- > 0)
1021	{
1022	/* Ugly assumption that mappings start on a 4 MB boundary. */
1023	if (iPDNew & 1)
1024	continue;
1025
1026	if (pPDSrc)
1027	{
1028	if (pPDSrc->a[iPDNew].n.u1Present)
1029	continue;
1030	if (cPTs > 1)
1031	{
1032	bool fOk = true;
1033	for (unsigned i = 1; fOk && i < cPTs; i++)
1034	if (pPDSrc->a[iPDNew + i].n.u1Present)
1035	fOk = false;
1036	if (!fOk)
1037	continue;
1038	}
1039	}
1040	/*
1041	* Check that it's not conflicting with an intermediate page table mapping.
1042	*/
1043	bool fOk = true;
1044	unsigned i = cPTs;
1045	while (fOk && i-- > 0)
1046	fOk = !pVM->pgm.s.apInterPaePDs[iPDPTE]->a[iPDNew + i].n.u1Present;
1047	if (!fOk)
1048	continue;
1049
1050	/*
1051	* Ask for the mapping.
1052	*/
1053	RTGCPTR GCPtrNewMapping = ((RTGCPTR32)iPDPTE << X86_PDPT_SHIFT) + (iPDNew << X86_PD_PAE_SHIFT);
1054
1055	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
1056	{
1057	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
1058	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1059	return VINF_SUCCESS;
1060	}
1061	}
1062	}
1063	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1064	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, pMapping->cb >> X86_PD_PAE_SHIFT));
1065	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
1066	}
1067
1068
1069	/**
1070	* Checks guest PD for conflicts with VMM GC mappings.
1071	*
1072	* @returns true if conflict detected.
1073	* @returns false if not.
1074	* @param pVM The virtual machine.
1075	* @param cr3 Guest context CR3 register.
1076	* @param fRawR0 Whether RawR0 is enabled or not.
1077	*/
1078	VMMR3DECL(bool) PGMR3MapHasConflicts(PVM pVM, uint64_t cr3, bool fRawR0) /** @todo how many HasConflict constructs do we really need? */
1079	{
1080	/*
1081	* Can skip this if mappings are safely fixed.
1082	*/
1083	if (pVM->pgm.s.fMappingsFixed)
1084	return false;
1085
1086	PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
1087	Assert(enmGuestMode <= PGMMODE_PAE_NX);
1088
1089	/*
1090	* Iterate mappings.
1091	*/
1092	if (enmGuestMode == PGMMODE_32_BIT)
1093	{
1094	/*
1095	* Resolve the page directory.
1096	*/
1097	PX86PD pPD = pVM->pgm.s.pGst32BitPdR3;
1098	Assert(pPD);
1099	Assert(pPD == (PX86PD)PGMPhysGCPhys2HCPtrAssert(pVM, cr3 & X86_CR3_PAGE_MASK, sizeof(*pPD)));
1100
1101	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1102	{
1103	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
1104	unsigned iPT = pCur->cPTs;
1105	while (iPT-- > 0)
1106	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
1107	&& (fRawR0 \|\| pPD->a[iPDE + iPT].n.u1User))
1108	{
1109	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
1110	Log(("PGMR3HasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
1111	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
1112	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
1113	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
1114	return true;
1115	}
1116	}
1117	}
1118	else if ( enmGuestMode == PGMMODE_PAE
1119	\|\| enmGuestMode == PGMMODE_PAE_NX)
1120	{
1121	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1122	{
1123	RTGCPTR GCPtr = pCur->GCPtr;
1124
1125	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
1126	while (iPT-- > 0)
1127	{
1128	X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
1129
1130	if ( Pde.n.u1Present
1131	&& (fRawR0 \|\| Pde.n.u1User))
1132	{
1133	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
1134	Log(("PGMR3HasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
1135	" PDE=%016RX64.\n",
1136	GCPtr, pCur->pszDesc, Pde.u));
1137	return true;
1138	}
1139	GCPtr += (1 << X86_PD_PAE_SHIFT);
1140	}
1141	}
1142	}
1143	else
1144	AssertFailed();
1145
1146	return false;
1147	}
1148
1149	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1150	/**
1151	* Apply the hypervisor mappings to the active CR3.
1152	*
1153	* @returns VBox status.
1154	* @param pVM The virtual machine.
1155	*/
1156	VMMR3DECL(int) PGMR3MapActivate(PVM pVM)
1157	{
1158	/*
1159	* Can skip this if mappings are safely fixed.
1160	*/
1161	if (pVM->pgm.s.fMappingsFixed)
1162	return VINF_SUCCESS;
1163
1164	PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
1165	Assert(enmGuestMode <= PGMMODE_PAE_NX);
1166
1167	/*
1168	* Iterate mappings.
1169	*/
1170	if (enmGuestMode == PGMMODE_32_BIT)
1171	{
1172	/*
1173	* Resolve the page directory.
1174	*/
1175	PX86PD pPD = (PX86PD)pVM->pgm.s.pShwPageCR3R3;
1176	Assert(pPD);
1177
1178	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1179	{
1180	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
1181	unsigned iPT = pCur->cPTs;
1182	while (iPT-- > 0)
1183	pPD->a[iPDE + iPT].u = 0;
1184	}
1185	}
1186	else if ( enmGuestMode == PGMMODE_PAE
1187	\|\| enmGuestMode == PGMMODE_PAE_NX)
1188	{
1189	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1190	{
1191	RTGCPTR GCPtr = pCur->GCPtr;
1192	unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1193
1194	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
1195	while (iPT-- > 0)
1196	{
1197	PX86PDEPAE pPDE = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtr);
1198	pPDE->u = 0;
1199
1200	GCPtr += (1 << X86_PD_PAE_SHIFT);
1201	}
1202	}
1203	}
1204	else
1205	AssertFailed();
1206
1207	return VINF_SUCCESS;
1208	}
1209
1210	/**
1211	* Remove the hypervisor mappings from the active CR3
1212	*
1213	* @returns VBox status.
1214	* @param pVM The virtual machine.
1215	*/
1216	VMMR3DECL(int) PGMR3MapDeactivate(PVM pVM)
1217	{
1218	/*
1219	* Can skip this if mappings are safely fixed.
1220	*/
1221	if (pVM->pgm.s.fMappingsFixed)
1222	return VINF_SUCCESS;
1223
1224	PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
1225	Assert(enmGuestMode <= PGMMODE_PAE_NX);
1226
1227	/*
1228	* Iterate mappings.
1229	*/
1230	if (enmGuestMode == PGMMODE_32_BIT)
1231	{
1232	/*
1233	* Resolve the page directory.
1234	*/
1235	PX86PD pPD = (PX86PD)pVM->pgm.s.pShwPageCR3R3;
1236	Assert(pPD);
1237
1238	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1239	{
1240	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
1241	unsigned iPT = pCur->cPTs;
1242	while (iPT-- > 0)
1243	pPD->a[iPDE + iPT].u = 0;
1244	}
1245	}
1246	else if ( enmGuestMode == PGMMODE_PAE
1247	\|\| enmGuestMode == PGMMODE_PAE_NX)
1248	{
1249	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1250	{
1251	RTGCPTR GCPtr = pCur->GCPtr;
1252
1253	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
1254	while (iPT-- > 0)
1255	{
1256	PX86PDEPAE pPDE = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtr);
1257	pPDE->u = 0;
1258
1259	GCPtr += (1 << X86_PD_PAE_SHIFT);
1260	}
1261	}
1262
1263	/* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entries. (legacy PAE guest mode) */
1264	PX86PDPT pPdpt = (PX86PDPT)pVM->pgm.s.pShwPageCR3R3;
1265	for (unsigned i=0;i<X86_PG_PAE_PDPE_ENTRIES;i++)
1266	pPdpt->a[i].u &= ~PGM_PLXFLAGS_MAPPING;
1267	}
1268	else
1269	AssertFailed();
1270
1271	return VINF_SUCCESS;
1272	}
1273	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
1274
1275	/**
1276	* Read memory from the guest mappings.
1277	*
1278	* This will use the page tables associated with the mappings to
1279	* read the memory. This means that not all kind of memory is readable
1280	* since we don't necessarily know how to convert that physical address
1281	* to a HC virtual one.
1282	*
1283	* @returns VBox status.
1284	* @param pVM VM handle.
1285	* @param pvDst The destination address (HC of course).
1286	* @param GCPtrSrc The source address (GC virtual address).
1287	* @param cb Number of bytes to read.
1288	*
1289	* @remarks The is indirectly for DBGF only.
1290	* @todo Consider renaming it to indicate it's special usage, or just
1291	* reimplement it in MMR3HyperReadGCVirt.
1292	*/
1293	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
1294	{
1295	/*
1296	* Simplicity over speed... Chop the request up into chunks
1297	* which don't cross pages.
1298	*/
1299	if (cb + (GCPtrSrc & PAGE_OFFSET_MASK) > PAGE_SIZE)
1300	{
1301	for (;;)
1302	{
1303	size_t cbRead = RT_MIN(cb, PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK));
1304	int rc = PGMR3MapRead(pVM, pvDst, GCPtrSrc, cbRead);
1305	if (RT_FAILURE(rc))
1306	return rc;
1307	cb -= cbRead;
1308	if (!cb)
1309	break;
1310	pvDst = (char *)pvDst + cbRead;
1311	GCPtrSrc += cbRead;
1312	}
1313	return VINF_SUCCESS;
1314	}
1315
1316	/*
1317	* Find the mapping.
1318	*/
1319	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
1320	while (pCur)
1321	{
1322	RTGCPTR off = GCPtrSrc - pCur->GCPtr;
1323	if (off < pCur->cb)
1324	{
1325	if (off + cb > pCur->cb)
1326	{
1327	AssertMsgFailed(("Invalid page range %RGv LB%#x. mapping '%s' %RGv to %RGv\n",
1328	GCPtrSrc, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast));
1329	return VERR_INVALID_PARAMETER;
1330	}
1331
1332	unsigned iPT = off >> X86_PD_SHIFT;
1333	unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
1334	while (cb > 0 && iPTE < RT_ELEMENTS(CTXALLSUFF(pCur->aPTs[iPT].pPT)->a))
1335	{
1336	if (!CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].n.u1Present)
1337	return VERR_PAGE_NOT_PRESENT;
1338	RTHCPHYS HCPhys = CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].u & X86_PTE_PAE_PG_MASK;
1339
1340	/*
1341	* Get the virtual page from the physical one.
1342	*/
1343	void *pvPage;
1344	int rc = MMR3HCPhys2HCVirt(pVM, HCPhys, &pvPage);
1345	if (RT_FAILURE(rc))
1346	return rc;
1347
1348	memcpy(pvDst, (char *)pvPage + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
1349	return VINF_SUCCESS;
1350	}
1351	}
1352
1353	/* next */
1354	pCur = CTXALLSUFF(pCur->pNext);
1355	}
1356
1357	return VERR_INVALID_POINTER;
1358	}
1359
1360
1361	/**
1362	* Info callback for 'pgmhandlers'.
1363	*
1364	* @param pHlp The output helpers.
1365	* @param pszArgs The arguments. phys or virt.
1366	*/
1367	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1368	{
1369	pHlp->pfnPrintf(pHlp, pVM->pgm.s.fMappingsFixed
1370	? "\nThe mappings are FIXED.\n"
1371	: "\nThe mappings are FLOATING.\n");
1372	PPGMMAPPING pCur;
1373	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1374	pHlp->pfnPrintf(pHlp, "%RGv - %RGv %s\n", pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
1375	}
1376

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source: vbox/trunk/src/VBox/VMM/PGMMap.cpp@ 14740

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