PGMMap.cpp@ 16524

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1	/* $Id: PGMMap.cpp 16413 2009-01-30 13:29:42Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager, Guest Context Mappings.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/dbgf.h>
28	#include <VBox/pgm.h>
29	#include "PGMInternal.h"
30	#include <VBox/vm.h>
31
32	#include <VBox/log.h>
33	#include <VBox/err.h>
34	#include <iprt/asm.h>
35	#include <iprt/assert.h>
36	#include <iprt/string.h>
37
38
39	/*******************************************************************************
40	* Internal Functions *
41	*******************************************************************************/
42	static void pgmR3MapClearPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iOldPDE);
43	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
44	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
45	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
46
47
48	/**
49	* Creates a page table based mapping in GC.
50	*
51	* @returns VBox status code.
52	* @param pVM VM Handle.
53	* @param GCPtr Virtual Address. (Page table aligned!)
54	* @param cb Size of the range. Must be a 4MB aligned!
55	* @param pfnRelocate Relocation callback function.
56	* @param pvUser User argument to the callback.
57	* @param pszDesc Pointer to description string. This must not be freed.
58	*/
59	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc)
60	{
61	LogFlow(("PGMR3MapPT: GCPtr=%#x cb=%d pfnRelocate=%p pvUser=%p pszDesc=%s\n", GCPtr, cb, pfnRelocate, pvUser, pszDesc));
62	AssertMsg(pVM->pgm.s.pInterPD && pVM->pgm.s.pShwNestedRootR3, ("Paging isn't initialized, init order problems!\n"));
63
64	/*
65	* Validate input.
66	*/
67	if (cb < _2M \|\| cb > 64 * _1M)
68	{
69	AssertMsgFailed(("Serious? cb=%d\n", cb));
70	return VERR_INVALID_PARAMETER;
71	}
72	cb = RT_ALIGN_32(cb, _4M);
73	RTGCPTR GCPtrLast = GCPtr + cb - 1;
74	if (GCPtrLast < GCPtr)
75	{
76	AssertMsgFailed(("Range wraps! GCPtr=%x GCPtrLast=%x\n", GCPtr, GCPtrLast));
77	return VERR_INVALID_PARAMETER;
78	}
79	if (pVM->pgm.s.fMappingsFixed)
80	{
81	AssertMsgFailed(("Mappings are fixed! It's not possible to add new mappings at this time!\n"));
82	return VERR_PGM_MAPPINGS_FIXED;
83	}
84	if (!pfnRelocate)
85	{
86	AssertMsgFailed(("Callback is required\n"));
87	return VERR_INVALID_PARAMETER;
88	}
89
90	/*
91	* Find list location.
92	*/
93	PPGMMAPPING pPrev = NULL;
94	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
95	while (pCur)
96	{
97	if (pCur->GCPtrLast >= GCPtr && pCur->GCPtr <= GCPtrLast)
98	{
99	AssertMsgFailed(("Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
100	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
101	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
102	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
103	return VERR_PGM_MAPPING_CONFLICT;
104	}
105	if (pCur->GCPtr > GCPtr)
106	break;
107	pPrev = pCur;
108	pCur = pCur->pNextR3;
109	}
110
111	/*
112	* Check for conflicts with intermediate mappings.
113	*/
114	const unsigned iPageDir = GCPtr >> X86_PD_SHIFT;
115	const unsigned cPTs = cb >> X86_PD_SHIFT;
116	if (pVM->pgm.s.fFinalizedMappings)
117	{
118	for (unsigned i = 0; i < cPTs; i++)
119	if (pVM->pgm.s.pInterPD->a[iPageDir + i].n.u1Present)
120	{
121	AssertMsgFailed(("Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
122	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
123	return VERR_PGM_MAPPING_CONFLICT;
124	}
125	/** @todo AMD64: add check in PAE structures too, so we can remove all the 32-Bit paging stuff there. */
126	}
127
128	/*
129	* Allocate and initialize the new list node.
130	*/
131	PPGMMAPPING pNew;
132	int rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMMAPPING, aPTs[cPTs]), 0, MM_TAG_PGM, (void **)&pNew);
133	if (RT_FAILURE(rc))
134	return rc;
135	pNew->GCPtr = GCPtr;
136	pNew->GCPtrLast = GCPtrLast;
137	pNew->cb = cb;
138	pNew->pszDesc = pszDesc;
139	pNew->pfnRelocate = pfnRelocate;
140	pNew->pvUser = pvUser;
141	pNew->cPTs = cPTs;
142
143	/*
144	* Allocate page tables and insert them into the page directories.
145	* (One 32-bit PT and two PAE PTs.)
146	*/
147	uint8_t *pbPTs;
148	rc = MMHyperAlloc(pVM, PAGE_SIZE * 3 * cPTs, PAGE_SIZE, MM_TAG_PGM, (void **)&pbPTs);
149	if (RT_FAILURE(rc))
150	{
151	MMHyperFree(pVM, pNew);
152	return VERR_NO_MEMORY;
153	}
154
155	/*
156	* Init the page tables and insert them into the page directories.
157	*/
158	Log4(("PGMR3MapPT: GCPtr=%RGv cPTs=%u pbPTs=%p\n", GCPtr, cPTs, pbPTs));
159	for (unsigned i = 0; i < cPTs; i++)
160	{
161	/*
162	* 32-bit.
163	*/
164	pNew->aPTs[i].pPTR3 = (PX86PT)pbPTs;
165	pNew->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pNew->aPTs[i].pPTR3);
166	pNew->aPTs[i].pPTR0 = MMHyperR3ToR0(pVM, pNew->aPTs[i].pPTR3);
167	pNew->aPTs[i].HCPhysPT = MMR3HyperHCVirt2HCPhys(pVM, pNew->aPTs[i].pPTR3);
168	pbPTs += PAGE_SIZE;
169	Log4(("PGMR3MapPT: i=%d: pPTR3=%RHv pPTRC=%RRv pPRTR0=%RHv HCPhysPT=%RHp\n",
170	i, pNew->aPTs[i].pPTR3, pNew->aPTs[i].pPTRC, pNew->aPTs[i].pPTR0, pNew->aPTs[i].HCPhysPT));
171
172	/*
173	* PAE.
174	*/
175	pNew->aPTs[i].HCPhysPaePT0 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs);
176	pNew->aPTs[i].HCPhysPaePT1 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs + PAGE_SIZE);
177	pNew->aPTs[i].paPaePTsR3 = (PX86PTPAE)pbPTs;
178	pNew->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pbPTs);
179	pNew->aPTs[i].paPaePTsR0 = MMHyperR3ToR0(pVM, pbPTs);
180	pbPTs += PAGE_SIZE * 2;
181	Log4(("PGMR3MapPT: i=%d: paPaePTsR#=%RHv paPaePTsRC=%RRv paPaePTsR#=%RHv HCPhysPaePT0=%RHp HCPhysPaePT1=%RHp\n",
182	i, pNew->aPTs[i].paPaePTsR3, pNew->aPTs[i].paPaePTsRC, pNew->aPTs[i].paPaePTsR0, pNew->aPTs[i].HCPhysPaePT0, pNew->aPTs[i].HCPhysPaePT1));
183	}
184	if (pVM->pgm.s.fFinalizedMappings)
185	pgmR3MapSetPDEs(pVM, pNew, iPageDir);
186	/* else PGMR3FinalizeMappings() */
187
188	/*
189	* Insert the new mapping.
190	*/
191	pNew->pNextR3 = pCur;
192	pNew->pNextRC = pCur ? MMHyperR3ToRC(pVM, pCur) : NIL_RTRCPTR;
193	pNew->pNextR0 = pCur ? MMHyperR3ToR0(pVM, pCur) : NIL_RTR0PTR;
194	if (pPrev)
195	{
196	pPrev->pNextR3 = pNew;
197	pPrev->pNextRC = MMHyperR3ToRC(pVM, pNew);
198	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pNew);
199	}
200	else
201	{
202	pVM->pgm.s.pMappingsR3 = pNew;
203	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pNew);
204	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pNew);
205	}
206
207	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
208	return VINF_SUCCESS;
209	}
210
211
212	/**
213	* Removes a page table based mapping.
214	*
215	* @returns VBox status code.
216	* @param pVM VM Handle.
217	* @param GCPtr Virtual Address. (Page table aligned!)
218	*/
219	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr)
220	{
221	LogFlow(("PGMR3UnmapPT: GCPtr=%#x\n", GCPtr));
222	AssertReturn(pVM->pgm.s.fFinalizedMappings, VERR_WRONG_ORDER);
223
224	/*
225	* Find it.
226	*/
227	PPGMMAPPING pPrev = NULL;
228	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
229	while (pCur)
230	{
231	if (pCur->GCPtr == GCPtr)
232	{
233	/*
234	* Unlink it.
235	*/
236	if (pPrev)
237	{
238	pPrev->pNextR3 = pCur->pNextR3;
239	pPrev->pNextRC = pCur->pNextRC;
240	pPrev->pNextR0 = pCur->pNextR0;
241	}
242	else
243	{
244	pVM->pgm.s.pMappingsR3 = pCur->pNextR3;
245	pVM->pgm.s.pMappingsRC = pCur->pNextRC;
246	pVM->pgm.s.pMappingsR0 = pCur->pNextR0;
247	}
248
249	/*
250	* Free the page table memory, clear page directory entries
251	* and free the page tables and node memory.
252	*/
253	MMHyperFree(pVM, pCur->aPTs[0].pPTR3);
254	pgmR3MapClearPDEs(pVM, pCur, pCur->GCPtr >> X86_PD_SHIFT);
255	MMHyperFree(pVM, pCur);
256
257	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
258	return VINF_SUCCESS;
259	}
260
261	/* done? */
262	if (pCur->GCPtr > GCPtr)
263	break;
264
265	/* next */
266	pPrev = pCur;
267	pCur = pCur->pNextR3;
268	}
269
270	AssertMsgFailed(("No mapping for %#x found!\n", GCPtr));
271	return VERR_INVALID_PARAMETER;
272	}
273
274
275	/**
276	* Checks whether a range of PDEs in the intermediate
277	* memory context are unused.
278	*
279	* We're talking 32-bit PDEs here.
280	*
281	* @returns true/false.
282	* @param pVM Pointer to the shared VM structure.
283	* @param iPD The first PDE in the range.
284	* @param cPTs The number of PDEs in the range.
285	*/
286	DECLINLINE(bool) pgmR3AreIntermediatePDEsUnused(PVM pVM, unsigned iPD, unsigned cPTs)
287	{
288	if (pVM->pgm.s.pInterPD->a[iPD].n.u1Present)
289	return false;
290	while (cPTs > 1)
291	{
292	iPD++;
293	if (pVM->pgm.s.pInterPD->a[iPD].n.u1Present)
294	return false;
295	cPTs--;
296	}
297	return true;
298	}
299
300
301	/**
302	* Unlinks the mapping.
303	*
304	* The mapping must be in the list.
305	*
306	* @param pVM Pointer to the shared VM structure.
307	* @param pMapping The mapping to unlink.
308	*/
309	static void pgmR3MapUnlink(PVM pVM, PPGMMAPPING pMapping)
310	{
311	PPGMMAPPING pAfterThis = pVM->pgm.s.pMappingsR3;
312	if (pAfterThis == pMapping)
313	{
314	/* head */
315	pVM->pgm.s.pMappingsR3 = pMapping->pNextR3;
316	pVM->pgm.s.pMappingsRC = pMapping->pNextRC;
317	pVM->pgm.s.pMappingsR0 = pMapping->pNextR0;
318	}
319	else
320	{
321	/* in the list */
322	while (pAfterThis->pNextR3 != pMapping)
323	{
324	pAfterThis = pAfterThis->pNextR3;
325	AssertReleaseReturnVoid(pAfterThis);
326	}
327
328	pAfterThis->pNextR3 = pMapping->pNextR3;
329	pAfterThis->pNextRC = pMapping->pNextRC;
330	pAfterThis->pNextR0 = pMapping->pNextR0;
331	}
332	}
333
334
335	/**
336	* Links the mapping.
337	*
338	* @param pVM Pointer to the shared VM structure.
339	* @param pMapping The mapping to linked.
340	*/
341	static void pgmR3MapLink(PVM pVM, PPGMMAPPING pMapping)
342	{
343	/*
344	* Find the list location (it's sorted by GCPhys) and link it in.
345	*/
346	if ( !pVM->pgm.s.pMappingsR3
347	\|\| pVM->pgm.s.pMappingsR3->GCPtr > pMapping->GCPtr)
348	{
349	/* head */
350	pMapping->pNextR3 = pVM->pgm.s.pMappingsR3;
351	pMapping->pNextRC = pVM->pgm.s.pMappingsRC;
352	pMapping->pNextR0 = pVM->pgm.s.pMappingsR0;
353	pVM->pgm.s.pMappingsR3 = pMapping;
354	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pMapping);
355	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pMapping);
356	}
357	else
358	{
359	/* in the list */
360	PPGMMAPPING pAfterThis = pVM->pgm.s.pMappingsR3;
361	PPGMMAPPING pBeforeThis = pAfterThis->pNextR3;
362	while (pBeforeThis && pBeforeThis->GCPtr <= pMapping->GCPtr)
363	{
364	pAfterThis = pBeforeThis;
365	pBeforeThis = pBeforeThis->pNextR3;
366	}
367
368	pMapping->pNextR3 = pAfterThis->pNextR3;
369	pMapping->pNextRC = pAfterThis->pNextRC;
370	pMapping->pNextR0 = pAfterThis->pNextR0;
371	pAfterThis->pNextR3 = pMapping;
372	pAfterThis->pNextRC = MMHyperR3ToRC(pVM, pMapping);
373	pAfterThis->pNextR0 = MMHyperR3ToR0(pVM, pMapping);
374	}
375	}
376
377
378	/**
379	* Finalizes the intermediate context.
380	*
381	* This is called at the end of the ring-3 init and will construct the
382	* intermediate paging structures, relocating all the mappings in the process.
383	*
384	* @returns VBox status code.
385	* @param pVM Pointer to the shared VM structure.
386	* @thread EMT(0)
387	*/
388	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM)
389	{
390	AssertReturn(!pVM->pgm.s.fFinalizedMappings, VERR_WRONG_ORDER);
391	pVM->pgm.s.fFinalizedMappings = true;
392
393	/*
394	* Loop until all mappings have been finalized.
395	*/
396	/unsigned iPDNext = UINT32_C(0xc0000000) >> X86_PD_SHIFT;/ /* makes CSAM/PATM freak out booting linux. :-/ */
397	#if 0
398	unsigned iPDNext = MM_HYPER_AREA_ADDRESS >> X86_PD_SHIFT;
399	#else
400	unsigned iPDNext = 1 << X86_PD_SHIFT; /* no hint, map them from the top. */
401	#endif
402	PPGMMAPPING pCur;
403	do
404	{
405	pCur = pVM->pgm.s.pMappingsR3;
406	while (pCur)
407	{
408	if (!pCur->fFinalized)
409	{
410	/*
411	* Find a suitable location.
412	*/
413	RTGCPTR const GCPtrOld = pCur->GCPtr;
414	const unsigned cPTs = pCur->cPTs;
415	unsigned iPDNew = iPDNext;
416	if ( iPDNew + cPTs >= X86_PG_ENTRIES /* exclude the last PD */
417	\|\| !pgmR3AreIntermediatePDEsUnused(pVM, iPDNew, cPTs)
418	\|\| !pCur->pfnRelocate(pVM, GCPtrOld, (RTGCPTR)iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
419	{
420	/* No luck, just scan down from 4GB-4MB, giving up at 4MB. */
421	iPDNew = X86_PG_ENTRIES - cPTs - 1;
422	while ( iPDNew > 0
423	&& ( !pgmR3AreIntermediatePDEsUnused(pVM, iPDNew, cPTs)
424	\|\| !pCur->pfnRelocate(pVM, GCPtrOld, (RTGCPTR)iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
425	)
426	iPDNew--;
427	AssertLogRelReturn(iPDNew != 0, VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
428	}
429
430	/*
431	* Relocate it (something akin to pgmR3MapRelocate).
432	*/
433	pgmR3MapSetPDEs(pVM, pCur, iPDNew);
434
435	/* unlink the mapping, update the entry and relink it. */
436	pgmR3MapUnlink(pVM, pCur);
437
438	RTGCPTR const GCPtrNew = (RTGCPTR)iPDNew << X86_PD_SHIFT;
439	pCur->GCPtr = GCPtrNew;
440	pCur->GCPtrLast = GCPtrNew + pCur->cb - 1;
441	pCur->fFinalized = true;
442
443	pgmR3MapLink(pVM, pCur);
444
445	/* Finally work the callback. */
446	pCur->pfnRelocate(pVM, GCPtrOld, GCPtrNew, PGMRELOCATECALL_RELOCATE, pCur->pvUser);
447
448	/*
449	* The list order might have changed, start from the beginning again.
450	*/
451	iPDNext = iPDNew + cPTs;
452	break;
453	}
454
455	/* next */
456	pCur = pCur->pNextR3;
457	}
458	} while (pCur);
459
460	return VINF_SUCCESS;
461	}
462
463
464	/**
465	* Gets the size of the current guest mappings if they were to be
466	* put next to oneanother.
467	*
468	* @returns VBox status code.
469	* @param pVM The VM.
470	* @param pcb Where to store the size.
471	*/
472	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb)
473	{
474	RTGCPTR cb = 0;
475	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
476	cb += pCur->cb;
477
478	*pcb = cb;
479	AssertReturn(*pcb == cb, VERR_NUMBER_TOO_BIG);
480	Log(("PGMR3MappingsSize: return %d (%#x) bytes\n", cb, cb));
481	return VINF_SUCCESS;
482	}
483
484
485	/**
486	* Fixes the guest context mappings in a range reserved from the Guest OS.
487	*
488	* @returns VBox status code.
489	* @param pVM The VM.
490	* @param GCPtrBase The address of the reserved range of guest memory.
491	* @param cb The size of the range starting at GCPtrBase.
492	*/
493	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb)
494	{
495	Log(("PGMR3MappingsFix: GCPtrBase=%#x cb=%#x\n", GCPtrBase, cb));
496
497	/* Ignore the additions mapping fix call in VT-x/AMD-V. */
498	if ( pVM->pgm.s.fMappingsFixed
499	&& HWACCMR3IsActive(pVM))
500	return VINF_SUCCESS;
501
502	/*
503	* This is all or nothing at all. So, a tiny bit of paranoia first.
504	*/
505	if (GCPtrBase & X86_PAGE_4M_OFFSET_MASK)
506	{
507	AssertMsgFailed(("GCPtrBase (%#x) has to be aligned on a 4MB address!\n", GCPtrBase));
508	return VERR_INVALID_PARAMETER;
509	}
510	if (!cb \|\| (cb & X86_PAGE_4M_OFFSET_MASK))
511	{
512	AssertMsgFailed(("cb (%#x) is 0 or not aligned on a 4MB address!\n", cb));
513	return VERR_INVALID_PARAMETER;
514	}
515
516	/*
517	* Before we do anything we'll do a forced PD sync to try make sure any
518	* pending relocations because of these mappings have been resolved.
519	*/
520	PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), true);
521
522	/*
523	* Check that it's not conflicting with a core code mapping in the intermediate page table.
524	*/
525	unsigned iPDNew = GCPtrBase >> X86_PD_SHIFT;
526	unsigned i = cb >> X86_PD_SHIFT;
527	while (i-- > 0)
528	{
529	if (pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present)
530	{
531	/* Check that it's not one or our mappings. */
532	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
533	while (pCur)
534	{
535	if (iPDNew + i - (pCur->GCPtr >> X86_PD_SHIFT) < (pCur->cb >> X86_PD_SHIFT))
536	break;
537	pCur = pCur->pNextR3;
538	}
539	if (!pCur)
540	{
541	LogRel(("PGMR3MappingsFix: Conflicts with intermediate PDE %#x (GCPtrBase=%RGv cb=%#zx). The guest should retry.\n",
542	iPDNew + i, GCPtrBase, cb));
543	return VERR_PGM_MAPPINGS_FIX_CONFLICT;
544	}
545	}
546	}
547
548	/*
549	* In PAE / PAE mode, make sure we don't cross page directories.
550	*/
551	if ( ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
552	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX)
553	&& ( pVM->pgm.s.enmShadowMode == PGMMODE_PAE
554	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX))
555	{
556	unsigned iPdptBase = GCPtrBase >> X86_PDPT_SHIFT;
557	unsigned iPdptLast = (GCPtrBase + cb - 1) >> X86_PDPT_SHIFT;
558	if (iPdptBase != iPdptLast)
559	{
560	LogRel(("PGMR3MappingsFix: Crosses PD boundrary; iPdptBase=%#x iPdptLast=%#x (GCPtrBase=%RGv cb=%#zx). The guest should retry.\n",
561	iPdptBase, iPdptLast, GCPtrBase, cb));
562	return VERR_PGM_MAPPINGS_FIX_CONFLICT;
563	}
564	}
565
566	/*
567	* Loop the mappings and check that they all agree on their new locations.
568	*/
569	RTGCPTR GCPtrCur = GCPtrBase;
570	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
571	while (pCur)
572	{
573	if (!pCur->pfnRelocate(pVM, pCur->GCPtr, GCPtrCur, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
574	{
575	AssertMsgFailed(("The suggested fixed address %#x was rejected by '%s'!\n", GCPtrCur, pCur->pszDesc));
576	return VERR_PGM_MAPPINGS_FIX_REJECTED;
577	}
578	/* next */
579	GCPtrCur += pCur->cb;
580	pCur = pCur->pNextR3;
581	}
582	if (GCPtrCur > GCPtrBase + cb)
583	{
584	AssertMsgFailed(("cb (%#x) is less than the required range %#x!\n", cb, GCPtrCur - GCPtrBase));
585	return VERR_PGM_MAPPINGS_FIX_TOO_SMALL;
586	}
587
588	/*
589	* Loop the table assigning the mappings to the passed in memory
590	* and call their relocator callback.
591	*/
592	GCPtrCur = GCPtrBase;
593	pCur = pVM->pgm.s.pMappingsR3;
594	while (pCur)
595	{
596	unsigned iPDOld = pCur->GCPtr >> X86_PD_SHIFT;
597	iPDNew = GCPtrCur >> X86_PD_SHIFT;
598
599	/*
600	* Relocate the page table(s).
601	*/
602	pgmR3MapClearPDEs(pVM, pCur, iPDOld);
603	pgmR3MapSetPDEs(pVM, pCur, iPDNew);
604
605	/*
606	* Update the entry.
607	*/
608	pCur->GCPtr = GCPtrCur;
609	pCur->GCPtrLast = GCPtrCur + pCur->cb - 1;
610
611	/*
612	* Callback to execute the relocation.
613	*/
614	pCur->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pCur->pvUser);
615
616	/*
617	* Advance.
618	*/
619	GCPtrCur += pCur->cb;
620	pCur = pCur->pNextR3;
621	}
622
623	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
624	/*
625	* Turn off CR3 updating monitoring.
626	*/
627	int rc2 = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
628	AssertRC(rc2);
629	#endif
630
631	/*
632	* Mark the mappings as fixed and return.
633	*/
634	pVM->pgm.s.fMappingsFixed = true;
635	pVM->pgm.s.GCPtrMappingFixed = GCPtrBase;
636	pVM->pgm.s.cbMappingFixed = cb;
637	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
638	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
639	return VINF_SUCCESS;
640	}
641
642	/**
643	* Disable the hypervisor mappings in the shadow page tables (doesn't touch the intermediate table!)
644	*
645	* @returns VBox status code.
646	* @param pVM The VM.
647	*/
648	VMMR3DECL(int) PGMR3MappingsDisable(PVM pVM)
649	{
650	uint32_t cb;
651	int rc = PGMR3MappingsSize(pVM, &cb);
652	AssertRCReturn(rc, rc);
653
654	rc = PGMMapDeactivateAll(pVM);
655	AssertRCReturn(rc, rc);
656
657	/*
658	* Mark the mappings as fixed (using fake values) and disabled.
659	*/
660	pVM->pgm.s.fDisableMappings = true;
661	pVM->pgm.s.fMappingsFixed = true;
662	pVM->pgm.s.GCPtrMappingFixed = MM_HYPER_AREA_ADDRESS;
663	pVM->pgm.s.cbMappingFixed = cb;
664	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
665	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
666	return VINF_SUCCESS;
667	}
668
669
670	/**
671	* Unfixes the mappings.
672	* After calling this function mapping conflict detection will be enabled.
673	*
674	* @returns VBox status code.
675	* @param pVM The VM.
676	*/
677	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM)
678	{
679	Log(("PGMR3MappingsUnfix: fMappingsFixed=%d\n", pVM->pgm.s.fMappingsFixed));
680
681	/* Ignore in VT-x/AMD-V mode. */
682	if (HWACCMR3IsActive(pVM))
683	return VINF_SUCCESS;
684
685	pVM->pgm.s.fMappingsFixed = false;
686	pVM->pgm.s.GCPtrMappingFixed = 0;
687	pVM->pgm.s.cbMappingFixed = 0;
688	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
689
690	/*
691	* Re-enable the CR3 monitoring.
692	*
693	* Paranoia: We flush the page pool before doing that because Windows
694	* is using the CR3 page both as a PD and a PT, e.g. the pool may
695	* be monitoring it.
696	*/
697	#ifdef PGMPOOL_WITH_MONITORING
698	pgmPoolFlushAll(pVM);
699	#endif
700	/* Remap CR3 as we have just flushed the CR3 shadow PML4 in case we're in long mode. */
701	int rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
702	AssertRCSuccess(rc);
703
704	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
705	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
706	AssertRCSuccess(rc);
707	#endif
708	return VINF_SUCCESS;
709	}
710
711
712	/**
713	* Map pages into the intermediate context (switcher code).
714	* These pages are mapped at both the give virtual address and at
715	* the physical address (for identity mapping).
716	*
717	* @returns VBox status code.
718	* @param pVM The virtual machine.
719	* @param Addr Intermediate context address of the mapping.
720	* @param HCPhys Start of the range of physical pages. This must be entriely below 4GB!
721	* @param cbPages Number of bytes to map.
722	*
723	* @remark This API shall not be used to anything but mapping the switcher code.
724	*/
725	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages)
726	{
727	LogFlow(("PGMR3MapIntermediate: Addr=%RTptr HCPhys=%RHp cbPages=%#x\n", Addr, HCPhys, cbPages));
728
729	/*
730	* Adjust input.
731	*/
732	cbPages += (uint32_t)HCPhys & PAGE_OFFSET_MASK;
733	cbPages = RT_ALIGN(cbPages, PAGE_SIZE);
734	HCPhys &= X86_PTE_PAE_PG_MASK;
735	Addr &= PAGE_BASE_MASK;
736	/* We only care about the first 4GB, because on AMD64 we'll be repeating them all over the address space. */
737	uint32_t uAddress = (uint32_t)Addr;
738
739	/*
740	* Assert input and state.
741	*/
742	AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
743	AssertMsg(pVM->pgm.s.pInterPD, ("Bad init order, paging.\n"));
744	AssertMsg(cbPages <= (512 << PAGE_SHIFT), ("The mapping is too big %d bytes\n", cbPages));
745	AssertMsg(HCPhys < _4G && HCPhys + cbPages < _4G, ("Addr=%RTptr HCPhys=%RHp cbPages=%d\n", Addr, HCPhys, cbPages));
746	AssertReturn(!pVM->pgm.s.fFinalizedMappings, VERR_WRONG_ORDER);
747
748	/*
749	* Check for internal conflicts between the virtual address and the physical address.
750	* A 1:1 mapping is fine, but partial overlapping is a no-no.
751	*/
752	if ( uAddress != HCPhys
753	&& ( uAddress < HCPhys
754	? HCPhys - uAddress < cbPages
755	: uAddress - HCPhys < cbPages
756	)
757	)
758	AssertLogRelMsgFailedReturn(("Addr=%RTptr HCPhys=%RHp cbPages=%d\n", Addr, HCPhys, cbPages),
759	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
760
761	const unsigned cPages = cbPages >> PAGE_SHIFT;
762	int rc = pgmR3MapIntermediateCheckOne(pVM, uAddress, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
763	if (RT_FAILURE(rc))
764	return rc;
765	rc = pgmR3MapIntermediateCheckOne(pVM, (uintptr_t)HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
766	if (RT_FAILURE(rc))
767	return rc;
768
769	/*
770	* Everythings fine, do the mapping.
771	*/
772	pgmR3MapIntermediateDoOne(pVM, uAddress, HCPhys, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
773	pgmR3MapIntermediateDoOne(pVM, (uintptr_t)HCPhys, HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
774
775	return VINF_SUCCESS;
776	}
777
778
779	/**
780	* Validates that there are no conflicts for this mapping into the intermediate context.
781	*
782	* @returns VBox status code.
783	* @param pVM VM handle.
784	* @param uAddress Address of the mapping.
785	* @param cPages Number of pages.
786	* @param pPTDefault Pointer to the default page table for this mapping.
787	* @param pPTPaeDefault Pointer to the default page table for this mapping.
788	*/
789	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
790	{
791	AssertMsg((uAddress >> X86_PD_SHIFT) + cPages <= 1024, ("64-bit fixme\n"));
792
793	/*
794	* Check that the ranges are available.
795	* (This code doesn't have to be fast.)
796	*/
797	while (cPages > 0)
798	{
799	/*
800	* 32-Bit.
801	*/
802	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
803	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
804	PX86PT pPT = pPTDefault;
805	if (pVM->pgm.s.pInterPD->a[iPDE].u)
806	{
807	RTHCPHYS HCPhysPT = pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK;
808	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]))
809	pPT = pVM->pgm.s.apInterPTs[0];
810	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]))
811	pPT = pVM->pgm.s.apInterPTs[1];
812	else
813	{
814	/** @todo this must be handled with a relocation of the conflicting mapping!
815	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
816	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%RHv\n", uAddress),
817	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
818	}
819	}
820	if (pPT->a[iPTE].u)
821	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%RHv pPT->a[iPTE].u=%RX32\n", iPTE, iPDE, uAddress, pPT->a[iPTE].u),
822	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
823
824	/*
825	* PAE.
826	*/
827	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
828	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
829	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
830	Assert(iPDPE < 4);
831	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
832	PX86PTPAE pPTPae = pPTPaeDefault;
833	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
834	{
835	RTHCPHYS HCPhysPT = pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK;
836	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
837	pPTPae = pVM->pgm.s.apInterPaePTs[0];
838	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
839	pPTPae = pVM->pgm.s.apInterPaePTs[1];
840	else
841	{
842	/** @todo this must be handled with a relocation of the conflicting mapping!
843	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
844	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%RHv\n", uAddress),
845	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
846	}
847	}
848	if (pPTPae->a[iPTE].u)
849	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%RHv pPTPae->a[iPTE].u=%#RX64\n", iPTE, iPDE, uAddress, pPTPae->a[iPTE].u),
850	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
851
852	/* next */
853	uAddress += PAGE_SIZE;
854	cPages--;
855	}
856
857	return VINF_SUCCESS;
858	}
859
860
861
862	/**
863	* Sets up the intermediate page tables for a verified mapping.
864	*
865	* @param pVM VM handle.
866	* @param uAddress Address of the mapping.
867	* @param HCPhys The physical address of the page range.
868	* @param cPages Number of pages.
869	* @param pPTDefault Pointer to the default page table for this mapping.
870	* @param pPTPaeDefault Pointer to the default page table for this mapping.
871	*/
872	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
873	{
874	while (cPages > 0)
875	{
876	/*
877	* 32-Bit.
878	*/
879	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
880	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
881	PX86PT pPT;
882	if (pVM->pgm.s.pInterPD->a[iPDE].u)
883	pPT = (PX86PT)MMPagePhys2Page(pVM, pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK);
884	else
885	{
886	pVM->pgm.s.pInterPD->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
887	\| (uint32_t)MMPage2Phys(pVM, pPTDefault);
888	pPT = pPTDefault;
889	}
890	pPT->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| (uint32_t)HCPhys;
891
892	/*
893	* PAE
894	*/
895	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
896	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
897	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
898	Assert(iPDPE < 4);
899	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
900	PX86PTPAE pPTPae;
901	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
902	pPTPae = (PX86PTPAE)MMPagePhys2Page(pVM, pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK);
903	else
904	{
905	pPTPae = pPTPaeDefault;
906	pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
907	\| MMPage2Phys(pVM, pPTPaeDefault);
908	}
909	pPTPae->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| HCPhys;
910
911	/* next */
912	cPages--;
913	HCPhys += PAGE_SIZE;
914	uAddress += PAGE_SIZE;
915	}
916	}
917
918
919	/**
920	* Clears all PDEs involved with the mapping in the shadow and intermediate page tables.
921	*
922	* @param pVM The VM handle.
923	* @param pMap Pointer to the mapping in question.
924	* @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
925	*/
926	static void pgmR3MapClearPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iOldPDE)
927	{
928	unsigned i = pMap->cPTs;
929
930	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
931	pgmMapClearShadowPDEs(pVM, pMap, iOldPDE);
932	#endif
933
934	iOldPDE += i;
935	while (i-- > 0)
936	{
937	iOldPDE--;
938
939	/*
940	* 32-bit.
941	*/
942	pVM->pgm.s.pInterPD->a[iOldPDE].u = 0;
943	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
944	pVM->pgm.s.pShw32BitPdR3->a[iOldPDE].u = 0;
945	#endif
946	/*
947	* PAE.
948	*/
949	const unsigned iPD = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
950	unsigned iPDE = iOldPDE * 2 % 512;
951	pVM->pgm.s.apInterPaePDs[iPD]->a[iPDE].u = 0;
952	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
953	pVM->pgm.s.apShwPaePDsR3[iPD]->a[iPDE].u = 0;
954	#endif
955	iPDE++;
956	AssertFatal(iPDE < 512);
957	pVM->pgm.s.apInterPaePDs[iPD]->a[iPDE].u = 0;
958	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
959	pVM->pgm.s.apShwPaePDsR3[iPD]->a[iPDE].u = 0;
960
961	/* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode) */
962	pVM->pgm.s.pShwPaePdptR3->a[iPD].u &= ~PGM_PLXFLAGS_MAPPING;
963	#endif
964	}
965	}
966
967	/**
968	* Sets all PDEs involved with the mapping in the shadow and intermediate page tables.
969	*
970	* @param pVM The VM handle.
971	* @param pMap Pointer to the mapping in question.
972	* @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
973	*/
974	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
975	{
976	PPGM pPGM = &pVM->pgm.s;
977
978	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s) \|\| PGMGetGuestMode(pVM) <= PGMMODE_PAE_NX);
979
980	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
981	pgmMapSetShadowPDEs(pVM, pMap, iNewPDE);
982	#endif
983
984	/*
985	* Init the page tables and insert them into the page directories.
986	*/
987	unsigned i = pMap->cPTs;
988	iNewPDE += i;
989	while (i-- > 0)
990	{
991	iNewPDE--;
992
993	/*
994	* 32-bit.
995	*/
996	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
997	Assert(!pPGM->pShw32BitPdR3->a[iNewPDE].n.u1Present \|\| pgmMapAreMappingsEnabled(&pVM->pgm.s));
998	if ( pgmMapAreMappingsEnabled(&pVM->pgm.s)
999	&& pPGM->pShw32BitPdR3->a[iNewPDE].n.u1Present)
1000	{
1001	Assert(!(pPGM->pShw32BitPdR3->a[iNewPDE].u & PGM_PDFLAGS_MAPPING));
1002	pgmPoolFree(pVM, pPGM->pShw32BitPdR3->a[iNewPDE].u & X86_PDE_PG_MASK, PGMPOOL_IDX_PD, iNewPDE);
1003	}
1004	#endif
1005	X86PDE Pde;
1006	/* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
1007	Pde.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT;
1008	pPGM->pInterPD->a[iNewPDE] = Pde;
1009	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1010	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
1011	pPGM->pShw32BitPdR3->a[iNewPDE] = Pde;
1012	#endif
1013	/*
1014	* PAE.
1015	*/
1016	const unsigned iPD = iNewPDE / 256;
1017	unsigned iPDE = iNewPDE * 2 % 512;
1018	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1019	Assert(!pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present \|\| pgmMapAreMappingsEnabled(&pVM->pgm.s));
1020	if ( pgmMapAreMappingsEnabled(&pVM->pgm.s)
1021	&& pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present)
1022	{
1023	Assert(!(pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & PGM_PDFLAGS_MAPPING));
1024	pgmPoolFree(pVM, pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2);
1025	}
1026	#endif
1027	X86PDEPAE PdePae0;
1028	PdePae0.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0;
1029	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae0;
1030	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1031	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
1032	pPGM->apShwPaePDsR3[iPD]->a[iPDE] = PdePae0;
1033	#endif
1034	iPDE++;
1035	AssertFatal(iPDE < 512);
1036	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1037	Assert(!pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present \|\| pgmMapAreMappingsEnabled(&pVM->pgm.s));
1038	if ( pgmMapAreMappingsEnabled(&pVM->pgm.s)
1039	&& pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present)
1040	{
1041	Assert(!(pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & PGM_PDFLAGS_MAPPING));
1042	pgmPoolFree(pVM, pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2 + 1);
1043	}
1044	#endif
1045	X86PDEPAE PdePae1;
1046	PdePae1.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1;
1047	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae1;
1048	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1049	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
1050	{
1051	pPGM->apShwPaePDsR3[iPD]->a[iPDE] = PdePae1;
1052
1053	/* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode) */
1054	pPGM->pShwPaePdptR3->a[iPD].u \|= PGM_PLXFLAGS_MAPPING;
1055	}
1056	#endif
1057	}
1058	}
1059
1060	/**
1061	* Relocates a mapping to a new address.
1062	*
1063	* @param pVM VM handle.
1064	* @param pMapping The mapping to relocate.
1065	* @param GCPtrOldMapping The address of the start of the old mapping.
1066	* @param GCPtrNewMapping The address of the start of the new mapping.
1067	*/
1068	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping)
1069	{
1070	unsigned iPDOld = GCPtrOldMapping >> X86_PD_SHIFT;
1071	unsigned iPDNew = GCPtrNewMapping >> X86_PD_SHIFT;
1072
1073	Log(("PGM: Relocating %s from %RGv to %RGv\n", pMapping->pszDesc, GCPtrOldMapping, GCPtrNewMapping));
1074	Assert(((unsigned)iPDOld << X86_PD_SHIFT) == pMapping->GCPtr);
1075
1076	/*
1077	* Relocate the page table(s).
1078	*/
1079	pgmR3MapClearPDEs(pVM, pMapping, iPDOld);
1080	pgmR3MapSetPDEs(pVM, pMapping, iPDNew);
1081
1082	/*
1083	* Update and resort the mapping list.
1084	*/
1085
1086	/* Find previous mapping for pMapping, put result into pPrevMap. */
1087	PPGMMAPPING pPrevMap = NULL;
1088	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
1089	while (pCur && pCur != pMapping)
1090	{
1091	/* next */
1092	pPrevMap = pCur;
1093	pCur = pCur->pNextR3;
1094	}
1095	Assert(pCur);
1096
1097	/* Find mapping which >= than pMapping. */
1098	RTGCPTR GCPtrNew = iPDNew << X86_PD_SHIFT;
1099	PPGMMAPPING pPrev = NULL;
1100	pCur = pVM->pgm.s.pMappingsR3;
1101	while (pCur && pCur->GCPtr < GCPtrNew)
1102	{
1103	/* next */
1104	pPrev = pCur;
1105	pCur = pCur->pNextR3;
1106	}
1107
1108	if (pCur != pMapping && pPrev != pMapping)
1109	{
1110	/*
1111	* Unlink.
1112	*/
1113	if (pPrevMap)
1114	{
1115	pPrevMap->pNextR3 = pMapping->pNextR3;
1116	pPrevMap->pNextRC = pMapping->pNextRC;
1117	pPrevMap->pNextR0 = pMapping->pNextR0;
1118	}
1119	else
1120	{
1121	pVM->pgm.s.pMappingsR3 = pMapping->pNextR3;
1122	pVM->pgm.s.pMappingsRC = pMapping->pNextRC;
1123	pVM->pgm.s.pMappingsR0 = pMapping->pNextR0;
1124	}
1125
1126	/*
1127	* Link
1128	*/
1129	pMapping->pNextR3 = pCur;
1130	if (pPrev)
1131	{
1132	pMapping->pNextRC = pPrev->pNextRC;
1133	pMapping->pNextR0 = pPrev->pNextR0;
1134	pPrev->pNextR3 = pMapping;
1135	pPrev->pNextRC = MMHyperR3ToRC(pVM, pMapping);
1136	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pMapping);
1137	}
1138	else
1139	{
1140	pMapping->pNextRC = pVM->pgm.s.pMappingsRC;
1141	pMapping->pNextR0 = pVM->pgm.s.pMappingsR0;
1142	pVM->pgm.s.pMappingsR3 = pMapping;
1143	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pMapping);
1144	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pMapping);
1145	}
1146	}
1147
1148	/*
1149	* Update the entry.
1150	*/
1151	pMapping->GCPtr = GCPtrNew;
1152	pMapping->GCPtrLast = GCPtrNew + pMapping->cb - 1;
1153
1154	/*
1155	* Callback to execute the relocation.
1156	*/
1157	pMapping->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pMapping->pvUser);
1158	}
1159
1160
1161	/**
1162	* Resolves a conflict between a page table based GC mapping and
1163	* the Guest OS page tables. (32 bits version)
1164	*
1165	* @returns VBox status code.
1166	* @param pVM VM Handle.
1167	* @param pMapping The mapping which conflicts.
1168	* @param pPDSrc The page directory of the guest OS.
1169	* @param GCPtrOldMapping The address of the start of the current mapping.
1170	*/
1171	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping)
1172	{
1173	STAM_REL_COUNTER_INC(&pVM->pgm.s.cRelocations);
1174	STAM_PROFILE_START(&pVM->pgm.s.StatR3ResolveConflict, a);
1175
1176	/*
1177	* Scan for free page directory entries.
1178	*
1179	* Note that we do not support mappings at the very end of the
1180	* address space since that will break our GCPtrEnd assumptions.
1181	*/
1182	const unsigned cPTs = pMapping->cPTs;
1183	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
1184	while (iPDNew-- > 0)
1185	{
1186	if (pPDSrc->a[iPDNew].n.u1Present)
1187	continue;
1188	if (cPTs > 1)
1189	{
1190	bool fOk = true;
1191	for (unsigned i = 1; fOk && i < cPTs; i++)
1192	if (pPDSrc->a[iPDNew + i].n.u1Present)
1193	fOk = false;
1194	if (!fOk)
1195	continue;
1196	}
1197
1198	/*
1199	* Check that it's not conflicting with an intermediate page table mapping.
1200	*/
1201	bool fOk = true;
1202	unsigned i = cPTs;
1203	while (fOk && i-- > 0)
1204	fOk = !pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present;
1205	if (!fOk)
1206	continue;
1207	/** @todo AMD64 should check the PAE directories and skip the 32bit stuff. */
1208
1209	/*
1210	* Ask for the mapping.
1211	*/
1212	RTGCPTR GCPtrNewMapping = iPDNew << X86_PD_SHIFT;
1213
1214	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
1215	{
1216	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
1217	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1218	return VINF_SUCCESS;
1219	}
1220	}
1221
1222	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1223	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, cPTs));
1224	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
1225	}
1226
1227
1228	/**
1229	* Resolves a conflict between a page table based GC mapping and
1230	* the Guest OS page tables. (PAE bits version)
1231	*
1232	* @returns VBox status code.
1233	* @param pVM VM Handle.
1234	* @param pMapping The mapping which conflicts.
1235	* @param GCPtrOldMapping The address of the start of the current mapping.
1236	*/
1237	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping)
1238	{
1239	STAM_REL_COUNTER_INC(&pVM->pgm.s.cRelocations);
1240	STAM_PROFILE_START(&pVM->pgm.s.StatR3ResolveConflict, a);
1241
1242	for (int iPDPTE = X86_PG_PAE_PDPE_ENTRIES - 1; iPDPTE >= 0; iPDPTE--)
1243	{
1244	unsigned iPDSrc;
1245	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCPTR32)iPDPTE << X86_PDPT_SHIFT, &iPDSrc, NULL);
1246
1247	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1248	/* It would be annoying to have to deal with a PD that isn't (yet) present in the guest PDPT. */
1249	if (!pPDSrc)
1250	continue;
1251	#endif
1252
1253	/*
1254	* Scan for free page directory entries.
1255	*
1256	* Note that we do not support mappings at the very end of the
1257	* address space since that will break our GCPtrEnd assumptions.
1258	* Nor do we support mappings crossing page directories.
1259	*/
1260	const unsigned cPTs = pMapping->cb >> X86_PD_PAE_SHIFT;
1261	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
1262
1263	while (iPDNew-- > 0)
1264	{
1265	/* Ugly assumption that mappings start on a 4 MB boundary. */
1266	if (iPDNew & 1)
1267	continue;
1268
1269	if (pPDSrc)
1270	{
1271	if (pPDSrc->a[iPDNew].n.u1Present)
1272	continue;
1273	if (cPTs > 1)
1274	{
1275	bool fOk = true;
1276	for (unsigned i = 1; fOk && i < cPTs; i++)
1277	if (pPDSrc->a[iPDNew + i].n.u1Present)
1278	fOk = false;
1279	if (!fOk)
1280	continue;
1281	}
1282	}
1283	/*
1284	* Check that it's not conflicting with an intermediate page table mapping.
1285	*/
1286	bool fOk = true;
1287	unsigned i = cPTs;
1288	while (fOk && i-- > 0)
1289	fOk = !pVM->pgm.s.apInterPaePDs[iPDPTE]->a[iPDNew + i].n.u1Present;
1290	if (!fOk)
1291	continue;
1292
1293	/*
1294	* Ask for the mapping.
1295	*/
1296	RTGCPTR GCPtrNewMapping = ((RTGCPTR32)iPDPTE << X86_PDPT_SHIFT) + (iPDNew << X86_PD_PAE_SHIFT);
1297
1298	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
1299	{
1300	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
1301	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1302	return VINF_SUCCESS;
1303	}
1304	}
1305	}
1306	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1307	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, pMapping->cb >> X86_PD_PAE_SHIFT));
1308	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
1309	}
1310
1311
1312	/**
1313	* Checks guest PD for conflicts with VMM GC mappings.
1314	*
1315	* @returns true if conflict detected.
1316	* @returns false if not.
1317	* @param pVM The virtual machine.
1318	* @param cr3 Guest context CR3 register.
1319	* @param fRawR0 Whether RawR0 is enabled or not.
1320	*/
1321	VMMR3DECL(bool) PGMR3MapHasConflicts(PVM pVM, uint64_t cr3, bool fRawR0) /** @todo how many HasConflict constructs do we really need? */
1322	{
1323	/*
1324	* Can skip this if mappings are safely fixed.
1325	*/
1326	if (pVM->pgm.s.fMappingsFixed)
1327	return false;
1328
1329	PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
1330	Assert(enmGuestMode <= PGMMODE_PAE_NX);
1331
1332	/*
1333	* Iterate mappings.
1334	*/
1335	if (enmGuestMode == PGMMODE_32_BIT)
1336	{
1337	/*
1338	* Resolve the page directory.
1339	*/
1340	PX86PD pPD = pVM->pgm.s.pGst32BitPdR3;
1341	Assert(pPD);
1342	Assert(pPD == (PX86PD)PGMPhysGCPhys2R3PtrAssert(pVM, cr3 & X86_CR3_PAGE_MASK, sizeof(*pPD)));
1343
1344	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1345	{
1346	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
1347	unsigned iPT = pCur->cPTs;
1348	while (iPT-- > 0)
1349	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
1350	&& (fRawR0 \|\| pPD->a[iPDE + iPT].n.u1User))
1351	{
1352	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
1353	Log(("PGMR3HasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
1354	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
1355	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
1356	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
1357	return true;
1358	}
1359	}
1360	}
1361	else if ( enmGuestMode == PGMMODE_PAE
1362	\|\| enmGuestMode == PGMMODE_PAE_NX)
1363	{
1364	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1365	{
1366	RTGCPTR GCPtr = pCur->GCPtr;
1367
1368	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
1369	while (iPT-- > 0)
1370	{
1371	X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
1372
1373	if ( Pde.n.u1Present
1374	&& (fRawR0 \|\| Pde.n.u1User))
1375	{
1376	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
1377	Log(("PGMR3HasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
1378	" PDE=%016RX64.\n",
1379	GCPtr, pCur->pszDesc, Pde.u));
1380	return true;
1381	}
1382	GCPtr += (1 << X86_PD_PAE_SHIFT);
1383	}
1384	}
1385	}
1386	else
1387	AssertFailed();
1388
1389	return false;
1390	}
1391
1392	/**
1393	* Read memory from the guest mappings.
1394	*
1395	* This will use the page tables associated with the mappings to
1396	* read the memory. This means that not all kind of memory is readable
1397	* since we don't necessarily know how to convert that physical address
1398	* to a HC virtual one.
1399	*
1400	* @returns VBox status.
1401	* @param pVM VM handle.
1402	* @param pvDst The destination address (HC of course).
1403	* @param GCPtrSrc The source address (GC virtual address).
1404	* @param cb Number of bytes to read.
1405	*
1406	* @remarks The is indirectly for DBGF only.
1407	* @todo Consider renaming it to indicate it's special usage, or just
1408	* reimplement it in MMR3HyperReadGCVirt.
1409	*/
1410	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
1411	{
1412	/*
1413	* Simplicity over speed... Chop the request up into chunks
1414	* which don't cross pages.
1415	*/
1416	if (cb + (GCPtrSrc & PAGE_OFFSET_MASK) > PAGE_SIZE)
1417	{
1418	for (;;)
1419	{
1420	size_t cbRead = RT_MIN(cb, PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK));
1421	int rc = PGMR3MapRead(pVM, pvDst, GCPtrSrc, cbRead);
1422	if (RT_FAILURE(rc))
1423	return rc;
1424	cb -= cbRead;
1425	if (!cb)
1426	break;
1427	pvDst = (char *)pvDst + cbRead;
1428	GCPtrSrc += cbRead;
1429	}
1430	return VINF_SUCCESS;
1431	}
1432
1433	/*
1434	* Find the mapping.
1435	*/
1436	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
1437	while (pCur)
1438	{
1439	RTGCPTR off = GCPtrSrc - pCur->GCPtr;
1440	if (off < pCur->cb)
1441	{
1442	if (off + cb > pCur->cb)
1443	{
1444	AssertMsgFailed(("Invalid page range %RGv LB%#x. mapping '%s' %RGv to %RGv\n",
1445	GCPtrSrc, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast));
1446	return VERR_INVALID_PARAMETER;
1447	}
1448
1449	unsigned iPT = off >> X86_PD_SHIFT;
1450	unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
1451	while (cb > 0 && iPTE < RT_ELEMENTS(CTXALLSUFF(pCur->aPTs[iPT].pPT)->a))
1452	{
1453	if (!CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].n.u1Present)
1454	return VERR_PAGE_NOT_PRESENT;
1455	RTHCPHYS HCPhys = CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].u & X86_PTE_PAE_PG_MASK;
1456
1457	/*
1458	* Get the virtual page from the physical one.
1459	*/
1460	void *pvPage;
1461	int rc = MMR3HCPhys2HCVirt(pVM, HCPhys, &pvPage);
1462	if (RT_FAILURE(rc))
1463	return rc;
1464
1465	memcpy(pvDst, (char *)pvPage + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
1466	return VINF_SUCCESS;
1467	}
1468	}
1469
1470	/* next */
1471	pCur = CTXALLSUFF(pCur->pNext);
1472	}
1473
1474	return VERR_INVALID_POINTER;
1475	}
1476
1477
1478	/**
1479	* Info callback for 'pgmhandlers'.
1480	*
1481	* @param pHlp The output helpers.
1482	* @param pszArgs The arguments. phys or virt.
1483	*/
1484	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1485	{
1486	pHlp->pfnPrintf(pHlp, pVM->pgm.s.fMappingsFixed
1487	? "\nThe mappings are FIXED.\n"
1488	: "\nThe mappings are FLOATING.\n");
1489	PPGMMAPPING pCur;
1490	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1491	pHlp->pfnPrintf(pHlp, "%RGv - %RGv %s\n", pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
1492	}
1493

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source: vbox/trunk/src/VBox/VMM/PGMMap.cpp@ 16524

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