PGMMap.cpp@ 18291

Last change on this file since 18291 was 18291, checked in by vboxsync, 16 years ago
PGM: Map PGMRAMRANGES above 4GB outside HMA (see defect). Changed PGMR3MapPT to take a flag indicating whether PGMR3UnmapPT will be used; this way we can select a more optimal allocation function for the ram ranges. PGMMapResolveConflicts: Walk the list correctly after reloc. pgmMapClearShadowPDEs: Don't clear PGM_PLXFLAGS_MAPPING when we shouldn't (odd PAE cases).
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1	/* $Id: PGMMap.cpp 18291 2009-03-26 05:11:07Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager, Guest Context Mappings.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/dbgf.h>
28	#include <VBox/pgm.h>
29	#include "PGMInternal.h"
30	#include <VBox/vm.h>
31
32	#include <VBox/log.h>
33	#include <VBox/err.h>
34	#include <iprt/asm.h>
35	#include <iprt/assert.h>
36	#include <iprt/string.h>
37
38
39	/*******************************************************************************
40	* Internal Functions *
41	*******************************************************************************/
42	static void pgmR3MapClearPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iOldPDE);
43	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
44	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
45	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
46
47
48	/**
49	* Creates a page table based mapping in GC.
50	*
51	* @returns VBox status code.
52	* @param pVM VM Handle.
53	* @param GCPtr Virtual Address. (Page table aligned!)
54	* @param cb Size of the range. Must be a 4MB aligned!
55	* @param fFlags PGMR3MAPPT_FLAGS_UNMAPPABLE or 0.
56	* @param pfnRelocate Relocation callback function.
57	* @param pvUser User argument to the callback.
58	* @param pszDesc Pointer to description string. This must not be freed.
59	*/
60	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc)
61	{
62	LogFlow(("PGMR3MapPT: GCPtr=%#x cb=%d fFlags=%#x pfnRelocate=%p pvUser=%p pszDesc=%s\n", GCPtr, cb, fFlags, pfnRelocate, pvUser, pszDesc));
63	AssertMsg(pVM->pgm.s.pInterPD, ("Paging isn't initialized, init order problems!\n"));
64
65	/*
66	* Validate input.
67	*/
68	Assert(!fFlags \|\| fFlags == PGMR3MAPPT_FLAGS_UNMAPPABLE);
69	if (cb < _2M \|\| cb > 64 * _1M)
70	{
71	AssertMsgFailed(("Serious? cb=%d\n", cb));
72	return VERR_INVALID_PARAMETER;
73	}
74	cb = RT_ALIGN_32(cb, _4M);
75	RTGCPTR GCPtrLast = GCPtr + cb - 1;
76	if (GCPtrLast < GCPtr)
77	{
78	AssertMsgFailed(("Range wraps! GCPtr=%x GCPtrLast=%x\n", GCPtr, GCPtrLast));
79	return VERR_INVALID_PARAMETER;
80	}
81	if (pVM->pgm.s.fMappingsFixed)
82	{
83	AssertMsgFailed(("Mappings are fixed! It's not possible to add new mappings at this time!\n"));
84	return VERR_PGM_MAPPINGS_FIXED;
85	}
86	if (!pfnRelocate)
87	{
88	AssertMsgFailed(("Callback is required\n"));
89	return VERR_INVALID_PARAMETER;
90	}
91
92	/*
93	* Find list location.
94	*/
95	PPGMMAPPING pPrev = NULL;
96	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
97	while (pCur)
98	{
99	if (pCur->GCPtrLast >= GCPtr && pCur->GCPtr <= GCPtrLast)
100	{
101	AssertMsgFailed(("Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
102	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
103	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
104	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
105	return VERR_PGM_MAPPING_CONFLICT;
106	}
107	if (pCur->GCPtr > GCPtr)
108	break;
109	pPrev = pCur;
110	pCur = pCur->pNextR3;
111	}
112
113	/*
114	* Check for conflicts with intermediate mappings.
115	*/
116	const unsigned iPageDir = GCPtr >> X86_PD_SHIFT;
117	const unsigned cPTs = cb >> X86_PD_SHIFT;
118	if (pVM->pgm.s.fFinalizedMappings)
119	{
120	for (unsigned i = 0; i < cPTs; i++)
121	if (pVM->pgm.s.pInterPD->a[iPageDir + i].n.u1Present)
122	{
123	AssertMsgFailed(("Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
124	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
125	return VERR_PGM_MAPPING_CONFLICT;
126	}
127	/** @todo AMD64: add check in PAE structures too, so we can remove all the 32-Bit paging stuff there. */
128	}
129
130	/*
131	* Allocate and initialize the new list node.
132	*/
133	PPGMMAPPING pNew;
134	int rc;
135	if (fFlags & PGMR3MAPPT_FLAGS_UNMAPPABLE)
136	rc = MMHyperAlloc( pVM, RT_OFFSETOF(PGMMAPPING, aPTs[cPTs]), 0, MM_TAG_PGM_MAPPINGS, (void **)&pNew);
137	else
138	rc = MMR3HyperAllocOnceNoRel(pVM, RT_OFFSETOF(PGMMAPPING, aPTs[cPTs]), 0, MM_TAG_PGM_MAPPINGS, (void **)&pNew);
139	if (RT_FAILURE(rc))
140	return rc;
141	pNew->GCPtr = GCPtr;
142	pNew->GCPtrLast = GCPtrLast;
143	pNew->cb = cb;
144	pNew->pszDesc = pszDesc;
145	pNew->pfnRelocate = pfnRelocate;
146	pNew->pvUser = pvUser;
147	pNew->cPTs = cPTs;
148
149	/*
150	* Allocate page tables and insert them into the page directories.
151	* (One 32-bit PT and two PAE PTs.)
152	*/
153	uint8_t *pbPTs;
154	if (fFlags & PGMR3MAPPT_FLAGS_UNMAPPABLE)
155	rc = MMHyperAlloc( pVM, PAGE_SIZE * 3 * cPTs, PAGE_SIZE, MM_TAG_PGM_MAPPINGS, (void **)&pbPTs);
156	else
157	rc = MMR3HyperAllocOnceNoRel(pVM, PAGE_SIZE * 3 * cPTs, PAGE_SIZE, MM_TAG_PGM_MAPPINGS, (void **)&pbPTs);
158	if (RT_FAILURE(rc))
159	{
160	MMHyperFree(pVM, pNew);
161	return VERR_NO_MEMORY;
162	}
163
164	/*
165	* Init the page tables and insert them into the page directories.
166	*/
167	Log4(("PGMR3MapPT: GCPtr=%RGv cPTs=%u pbPTs=%p\n", GCPtr, cPTs, pbPTs));
168	for (unsigned i = 0; i < cPTs; i++)
169	{
170	/*
171	* 32-bit.
172	*/
173	pNew->aPTs[i].pPTR3 = (PX86PT)pbPTs;
174	pNew->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pNew->aPTs[i].pPTR3);
175	pNew->aPTs[i].pPTR0 = MMHyperR3ToR0(pVM, pNew->aPTs[i].pPTR3);
176	pNew->aPTs[i].HCPhysPT = MMR3HyperHCVirt2HCPhys(pVM, pNew->aPTs[i].pPTR3);
177	pbPTs += PAGE_SIZE;
178	Log4(("PGMR3MapPT: i=%d: pPTR3=%RHv pPTRC=%RRv pPRTR0=%RHv HCPhysPT=%RHp\n",
179	i, pNew->aPTs[i].pPTR3, pNew->aPTs[i].pPTRC, pNew->aPTs[i].pPTR0, pNew->aPTs[i].HCPhysPT));
180
181	/*
182	* PAE.
183	*/
184	pNew->aPTs[i].HCPhysPaePT0 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs);
185	pNew->aPTs[i].HCPhysPaePT1 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs + PAGE_SIZE);
186	pNew->aPTs[i].paPaePTsR3 = (PX86PTPAE)pbPTs;
187	pNew->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pbPTs);
188	pNew->aPTs[i].paPaePTsR0 = MMHyperR3ToR0(pVM, pbPTs);
189	pbPTs += PAGE_SIZE * 2;
190	Log4(("PGMR3MapPT: i=%d: paPaePTsR#=%RHv paPaePTsRC=%RRv paPaePTsR#=%RHv HCPhysPaePT0=%RHp HCPhysPaePT1=%RHp\n",
191	i, pNew->aPTs[i].paPaePTsR3, pNew->aPTs[i].paPaePTsRC, pNew->aPTs[i].paPaePTsR0, pNew->aPTs[i].HCPhysPaePT0, pNew->aPTs[i].HCPhysPaePT1));
192	}
193	if (pVM->pgm.s.fFinalizedMappings)
194	pgmR3MapSetPDEs(pVM, pNew, iPageDir);
195	/* else PGMR3FinalizeMappings() */
196
197	/*
198	* Insert the new mapping.
199	*/
200	pNew->pNextR3 = pCur;
201	pNew->pNextRC = pCur ? MMHyperR3ToRC(pVM, pCur) : NIL_RTRCPTR;
202	pNew->pNextR0 = pCur ? MMHyperR3ToR0(pVM, pCur) : NIL_RTR0PTR;
203	if (pPrev)
204	{
205	pPrev->pNextR3 = pNew;
206	pPrev->pNextRC = MMHyperR3ToRC(pVM, pNew);
207	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pNew);
208	}
209	else
210	{
211	pVM->pgm.s.pMappingsR3 = pNew;
212	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pNew);
213	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pNew);
214	}
215
216	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
217	return VINF_SUCCESS;
218	}
219
220
221	/**
222	* Removes a page table based mapping.
223	*
224	* @returns VBox status code.
225	* @param pVM VM Handle.
226	* @param GCPtr Virtual Address. (Page table aligned!)
227	*
228	* @remarks Don't call this without passing PGMR3MAPPT_FLAGS_UNMAPPABLE to
229	* PGMR3MapPT or you'll burn in the heap.
230	*/
231	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr)
232	{
233	LogFlow(("PGMR3UnmapPT: GCPtr=%#x\n", GCPtr));
234	AssertReturn(pVM->pgm.s.fFinalizedMappings, VERR_WRONG_ORDER);
235
236	/*
237	* Find it.
238	*/
239	PPGMMAPPING pPrev = NULL;
240	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
241	while (pCur)
242	{
243	if (pCur->GCPtr == GCPtr)
244	{
245	/*
246	* Unlink it.
247	*/
248	if (pPrev)
249	{
250	pPrev->pNextR3 = pCur->pNextR3;
251	pPrev->pNextRC = pCur->pNextRC;
252	pPrev->pNextR0 = pCur->pNextR0;
253	}
254	else
255	{
256	pVM->pgm.s.pMappingsR3 = pCur->pNextR3;
257	pVM->pgm.s.pMappingsRC = pCur->pNextRC;
258	pVM->pgm.s.pMappingsR0 = pCur->pNextR0;
259	}
260
261	/*
262	* Free the page table memory, clear page directory entries
263	* and free the page tables and node memory.
264	*/
265	MMHyperFree(pVM, pCur->aPTs[0].pPTR3);
266	pgmR3MapClearPDEs(pVM, pCur, pCur->GCPtr >> X86_PD_SHIFT);
267	MMHyperFree(pVM, pCur);
268
269	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
270	return VINF_SUCCESS;
271	}
272
273	/* done? */
274	if (pCur->GCPtr > GCPtr)
275	break;
276
277	/* next */
278	pPrev = pCur;
279	pCur = pCur->pNextR3;
280	}
281
282	AssertMsgFailed(("No mapping for %#x found!\n", GCPtr));
283	return VERR_INVALID_PARAMETER;
284	}
285
286
287	/**
288	* Checks whether a range of PDEs in the intermediate
289	* memory context are unused.
290	*
291	* We're talking 32-bit PDEs here.
292	*
293	* @returns true/false.
294	* @param pVM Pointer to the shared VM structure.
295	* @param iPD The first PDE in the range.
296	* @param cPTs The number of PDEs in the range.
297	*/
298	DECLINLINE(bool) pgmR3AreIntermediatePDEsUnused(PVM pVM, unsigned iPD, unsigned cPTs)
299	{
300	if (pVM->pgm.s.pInterPD->a[iPD].n.u1Present)
301	return false;
302	while (cPTs > 1)
303	{
304	iPD++;
305	if (pVM->pgm.s.pInterPD->a[iPD].n.u1Present)
306	return false;
307	cPTs--;
308	}
309	return true;
310	}
311
312
313	/**
314	* Unlinks the mapping.
315	*
316	* The mapping must be in the list.
317	*
318	* @param pVM Pointer to the shared VM structure.
319	* @param pMapping The mapping to unlink.
320	*/
321	static void pgmR3MapUnlink(PVM pVM, PPGMMAPPING pMapping)
322	{
323	PPGMMAPPING pAfterThis = pVM->pgm.s.pMappingsR3;
324	if (pAfterThis == pMapping)
325	{
326	/* head */
327	pVM->pgm.s.pMappingsR3 = pMapping->pNextR3;
328	pVM->pgm.s.pMappingsRC = pMapping->pNextRC;
329	pVM->pgm.s.pMappingsR0 = pMapping->pNextR0;
330	}
331	else
332	{
333	/* in the list */
334	while (pAfterThis->pNextR3 != pMapping)
335	{
336	pAfterThis = pAfterThis->pNextR3;
337	AssertReleaseReturnVoid(pAfterThis);
338	}
339
340	pAfterThis->pNextR3 = pMapping->pNextR3;
341	pAfterThis->pNextRC = pMapping->pNextRC;
342	pAfterThis->pNextR0 = pMapping->pNextR0;
343	}
344	}
345
346
347	/**
348	* Links the mapping.
349	*
350	* @param pVM Pointer to the shared VM structure.
351	* @param pMapping The mapping to linked.
352	*/
353	static void pgmR3MapLink(PVM pVM, PPGMMAPPING pMapping)
354	{
355	/*
356	* Find the list location (it's sorted by GCPhys) and link it in.
357	*/
358	if ( !pVM->pgm.s.pMappingsR3
359	\|\| pVM->pgm.s.pMappingsR3->GCPtr > pMapping->GCPtr)
360	{
361	/* head */
362	pMapping->pNextR3 = pVM->pgm.s.pMappingsR3;
363	pMapping->pNextRC = pVM->pgm.s.pMappingsRC;
364	pMapping->pNextR0 = pVM->pgm.s.pMappingsR0;
365	pVM->pgm.s.pMappingsR3 = pMapping;
366	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pMapping);
367	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pMapping);
368	}
369	else
370	{
371	/* in the list */
372	PPGMMAPPING pAfterThis = pVM->pgm.s.pMappingsR3;
373	PPGMMAPPING pBeforeThis = pAfterThis->pNextR3;
374	while (pBeforeThis && pBeforeThis->GCPtr <= pMapping->GCPtr)
375	{
376	pAfterThis = pBeforeThis;
377	pBeforeThis = pBeforeThis->pNextR3;
378	}
379
380	pMapping->pNextR3 = pAfterThis->pNextR3;
381	pMapping->pNextRC = pAfterThis->pNextRC;
382	pMapping->pNextR0 = pAfterThis->pNextR0;
383	pAfterThis->pNextR3 = pMapping;
384	pAfterThis->pNextRC = MMHyperR3ToRC(pVM, pMapping);
385	pAfterThis->pNextR0 = MMHyperR3ToR0(pVM, pMapping);
386	}
387	}
388
389
390	/**
391	* Finalizes the intermediate context.
392	*
393	* This is called at the end of the ring-3 init and will construct the
394	* intermediate paging structures, relocating all the mappings in the process.
395	*
396	* @returns VBox status code.
397	* @param pVM Pointer to the shared VM structure.
398	* @thread EMT(0)
399	*/
400	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM)
401	{
402	AssertReturn(!pVM->pgm.s.fFinalizedMappings, VERR_WRONG_ORDER);
403	pVM->pgm.s.fFinalizedMappings = true;
404
405	/*
406	* Loop until all mappings have been finalized.
407	*/
408	/unsigned iPDNext = UINT32_C(0xc0000000) >> X86_PD_SHIFT;/ /* makes CSAM/PATM freak out booting linux. :-/ */
409	#if 0
410	unsigned iPDNext = MM_HYPER_AREA_ADDRESS >> X86_PD_SHIFT;
411	#else
412	unsigned iPDNext = 1 << X86_PD_SHIFT; /* no hint, map them from the top. */
413	#endif
414	PPGMMAPPING pCur;
415	do
416	{
417	pCur = pVM->pgm.s.pMappingsR3;
418	while (pCur)
419	{
420	if (!pCur->fFinalized)
421	{
422	/*
423	* Find a suitable location.
424	*/
425	RTGCPTR const GCPtrOld = pCur->GCPtr;
426	const unsigned cPTs = pCur->cPTs;
427	unsigned iPDNew = iPDNext;
428	if ( iPDNew + cPTs >= X86_PG_ENTRIES /* exclude the last PD */
429	\|\| !pgmR3AreIntermediatePDEsUnused(pVM, iPDNew, cPTs)
430	\|\| !pCur->pfnRelocate(pVM, GCPtrOld, (RTGCPTR)iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
431	{
432	/* No luck, just scan down from 4GB-4MB, giving up at 4MB. */
433	iPDNew = X86_PG_ENTRIES - cPTs - 1;
434	while ( iPDNew > 0
435	&& ( !pgmR3AreIntermediatePDEsUnused(pVM, iPDNew, cPTs)
436	\|\| !pCur->pfnRelocate(pVM, GCPtrOld, (RTGCPTR)iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
437	)
438	iPDNew--;
439	AssertLogRelReturn(iPDNew != 0, VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
440	}
441
442	/*
443	* Relocate it (something akin to pgmR3MapRelocate).
444	*/
445	pgmR3MapSetPDEs(pVM, pCur, iPDNew);
446
447	/* unlink the mapping, update the entry and relink it. */
448	pgmR3MapUnlink(pVM, pCur);
449
450	RTGCPTR const GCPtrNew = (RTGCPTR)iPDNew << X86_PD_SHIFT;
451	pCur->GCPtr = GCPtrNew;
452	pCur->GCPtrLast = GCPtrNew + pCur->cb - 1;
453	pCur->fFinalized = true;
454
455	pgmR3MapLink(pVM, pCur);
456
457	/* Finally work the callback. */
458	pCur->pfnRelocate(pVM, GCPtrOld, GCPtrNew, PGMRELOCATECALL_RELOCATE, pCur->pvUser);
459
460	/*
461	* The list order might have changed, start from the beginning again.
462	*/
463	iPDNext = iPDNew + cPTs;
464	break;
465	}
466
467	/* next */
468	pCur = pCur->pNextR3;
469	}
470	} while (pCur);
471
472	return VINF_SUCCESS;
473	}
474
475
476	/**
477	* Gets the size of the current guest mappings if they were to be
478	* put next to oneanother.
479	*
480	* @returns VBox status code.
481	* @param pVM The VM.
482	* @param pcb Where to store the size.
483	*/
484	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb)
485	{
486	RTGCPTR cb = 0;
487	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
488	cb += pCur->cb;
489
490	*pcb = cb;
491	AssertReturn(*pcb == cb, VERR_NUMBER_TOO_BIG);
492	Log(("PGMR3MappingsSize: return %d (%#x) bytes\n", cb, cb));
493	return VINF_SUCCESS;
494	}
495
496
497	/**
498	* Fixes the guest context mappings in a range reserved from the Guest OS.
499	*
500	* @returns VBox status code.
501	* @param pVM The VM.
502	* @param GCPtrBase The address of the reserved range of guest memory.
503	* @param cb The size of the range starting at GCPtrBase.
504	*/
505	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb)
506	{
507	Log(("PGMR3MappingsFix: GCPtrBase=%#x cb=%#x\n", GCPtrBase, cb));
508
509	/* Ignore the additions mapping fix call in VT-x/AMD-V. */
510	if ( pVM->pgm.s.fMappingsFixed
511	&& HWACCMR3IsActive(pVM))
512	return VINF_SUCCESS;
513
514	/*
515	* This is all or nothing at all. So, a tiny bit of paranoia first.
516	*/
517	if (GCPtrBase & X86_PAGE_4M_OFFSET_MASK)
518	{
519	AssertMsgFailed(("GCPtrBase (%#x) has to be aligned on a 4MB address!\n", GCPtrBase));
520	return VERR_INVALID_PARAMETER;
521	}
522	if (!cb \|\| (cb & X86_PAGE_4M_OFFSET_MASK))
523	{
524	AssertMsgFailed(("cb (%#x) is 0 or not aligned on a 4MB address!\n", cb));
525	return VERR_INVALID_PARAMETER;
526	}
527
528	/*
529	* Before we do anything we'll do a forced PD sync to try make sure any
530	* pending relocations because of these mappings have been resolved.
531	*/
532	PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), true);
533
534	/*
535	* Check that it's not conflicting with a core code mapping in the intermediate page table.
536	*/
537	unsigned iPDNew = GCPtrBase >> X86_PD_SHIFT;
538	unsigned i = cb >> X86_PD_SHIFT;
539	while (i-- > 0)
540	{
541	if (pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present)
542	{
543	/* Check that it's not one or our mappings. */
544	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
545	while (pCur)
546	{
547	if (iPDNew + i - (pCur->GCPtr >> X86_PD_SHIFT) < (pCur->cb >> X86_PD_SHIFT))
548	break;
549	pCur = pCur->pNextR3;
550	}
551	if (!pCur)
552	{
553	LogRel(("PGMR3MappingsFix: Conflicts with intermediate PDE %#x (GCPtrBase=%RGv cb=%#zx). The guest should retry.\n",
554	iPDNew + i, GCPtrBase, cb));
555	return VERR_PGM_MAPPINGS_FIX_CONFLICT;
556	}
557	}
558	}
559
560	/*
561	* In PAE / PAE mode, make sure we don't cross page directories.
562	*/
563	if ( ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
564	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX)
565	&& ( pVM->pgm.s.enmShadowMode == PGMMODE_PAE
566	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX))
567	{
568	unsigned iPdptBase = GCPtrBase >> X86_PDPT_SHIFT;
569	unsigned iPdptLast = (GCPtrBase + cb - 1) >> X86_PDPT_SHIFT;
570	if (iPdptBase != iPdptLast)
571	{
572	LogRel(("PGMR3MappingsFix: Crosses PD boundrary; iPdptBase=%#x iPdptLast=%#x (GCPtrBase=%RGv cb=%#zx). The guest should retry.\n",
573	iPdptBase, iPdptLast, GCPtrBase, cb));
574	return VERR_PGM_MAPPINGS_FIX_CONFLICT;
575	}
576	}
577
578	/*
579	* Loop the mappings and check that they all agree on their new locations.
580	*/
581	RTGCPTR GCPtrCur = GCPtrBase;
582	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
583	while (pCur)
584	{
585	if (!pCur->pfnRelocate(pVM, pCur->GCPtr, GCPtrCur, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
586	{
587	AssertMsgFailed(("The suggested fixed address %#x was rejected by '%s'!\n", GCPtrCur, pCur->pszDesc));
588	return VERR_PGM_MAPPINGS_FIX_REJECTED;
589	}
590	/* next */
591	GCPtrCur += pCur->cb;
592	pCur = pCur->pNextR3;
593	}
594	if (GCPtrCur > GCPtrBase + cb)
595	{
596	AssertMsgFailed(("cb (%#x) is less than the required range %#x!\n", cb, GCPtrCur - GCPtrBase));
597	return VERR_PGM_MAPPINGS_FIX_TOO_SMALL;
598	}
599
600	/*
601	* Loop the table assigning the mappings to the passed in memory
602	* and call their relocator callback.
603	*/
604	GCPtrCur = GCPtrBase;
605	pCur = pVM->pgm.s.pMappingsR3;
606	while (pCur)
607	{
608	unsigned iPDOld = pCur->GCPtr >> X86_PD_SHIFT;
609	iPDNew = GCPtrCur >> X86_PD_SHIFT;
610
611	/*
612	* Relocate the page table(s).
613	*/
614	pgmR3MapClearPDEs(pVM, pCur, iPDOld);
615	pgmR3MapSetPDEs(pVM, pCur, iPDNew);
616
617	/*
618	* Update the entry.
619	*/
620	pCur->GCPtr = GCPtrCur;
621	pCur->GCPtrLast = GCPtrCur + pCur->cb - 1;
622
623	/*
624	* Callback to execute the relocation.
625	*/
626	pCur->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pCur->pvUser);
627
628	/*
629	* Advance.
630	*/
631	GCPtrCur += pCur->cb;
632	pCur = pCur->pNextR3;
633	}
634
635	/*
636	* Mark the mappings as fixed and return.
637	*/
638	pVM->pgm.s.fMappingsFixed = true;
639	pVM->pgm.s.GCPtrMappingFixed = GCPtrBase;
640	pVM->pgm.s.cbMappingFixed = cb;
641	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
642	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
643	return VINF_SUCCESS;
644	}
645
646	/**
647	* Disable the hypervisor mappings in the shadow page tables (doesn't touch the intermediate table!)
648	*
649	* @returns VBox status code.
650	* @param pVM The VM.
651	*/
652	VMMR3DECL(int) PGMR3MappingsDisable(PVM pVM)
653	{
654	uint32_t cb;
655	int rc = PGMR3MappingsSize(pVM, &cb);
656	AssertRCReturn(rc, rc);
657
658	rc = pgmMapDeactivateCR3(pVM, pVM->pgm.s.pShwPageCR3R3);
659	AssertRCReturn(rc, rc);
660
661	/*
662	* Mark the mappings as fixed (using fake values) and disabled.
663	*/
664	pVM->pgm.s.fDisableMappings = true;
665	pVM->pgm.s.fMappingsFixed = true;
666	pVM->pgm.s.GCPtrMappingFixed = MM_HYPER_AREA_ADDRESS;
667	pVM->pgm.s.cbMappingFixed = cb;
668	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
669	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
670	return VINF_SUCCESS;
671	}
672
673
674	/**
675	* Unfixes the mappings.
676	* After calling this function mapping conflict detection will be enabled.
677	*
678	* @returns VBox status code.
679	* @param pVM The VM.
680	*/
681	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM)
682	{
683	Log(("PGMR3MappingsUnfix: fMappingsFixed=%d\n", pVM->pgm.s.fMappingsFixed));
684
685	/* Ignore in VT-x/AMD-V mode. */
686	if (HWACCMR3IsActive(pVM))
687	return VINF_SUCCESS;
688
689	pVM->pgm.s.fMappingsFixed = false;
690	pVM->pgm.s.GCPtrMappingFixed = 0;
691	pVM->pgm.s.cbMappingFixed = 0;
692	return VINF_SUCCESS;
693	}
694
695
696	/**
697	* Map pages into the intermediate context (switcher code).
698	* These pages are mapped at both the give virtual address and at
699	* the physical address (for identity mapping).
700	*
701	* @returns VBox status code.
702	* @param pVM The virtual machine.
703	* @param Addr Intermediate context address of the mapping.
704	* @param HCPhys Start of the range of physical pages. This must be entriely below 4GB!
705	* @param cbPages Number of bytes to map.
706	*
707	* @remark This API shall not be used to anything but mapping the switcher code.
708	*/
709	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages)
710	{
711	LogFlow(("PGMR3MapIntermediate: Addr=%RTptr HCPhys=%RHp cbPages=%#x\n", Addr, HCPhys, cbPages));
712
713	/*
714	* Adjust input.
715	*/
716	cbPages += (uint32_t)HCPhys & PAGE_OFFSET_MASK;
717	cbPages = RT_ALIGN(cbPages, PAGE_SIZE);
718	HCPhys &= X86_PTE_PAE_PG_MASK;
719	Addr &= PAGE_BASE_MASK;
720	/* We only care about the first 4GB, because on AMD64 we'll be repeating them all over the address space. */
721	uint32_t uAddress = (uint32_t)Addr;
722
723	/*
724	* Assert input and state.
725	*/
726	AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
727	AssertMsg(pVM->pgm.s.pInterPD, ("Bad init order, paging.\n"));
728	AssertMsg(cbPages <= (512 << PAGE_SHIFT), ("The mapping is too big %d bytes\n", cbPages));
729	AssertMsg(HCPhys < _4G && HCPhys + cbPages < _4G, ("Addr=%RTptr HCPhys=%RHp cbPages=%d\n", Addr, HCPhys, cbPages));
730	AssertReturn(!pVM->pgm.s.fFinalizedMappings, VERR_WRONG_ORDER);
731
732	/*
733	* Check for internal conflicts between the virtual address and the physical address.
734	* A 1:1 mapping is fine, but partial overlapping is a no-no.
735	*/
736	if ( uAddress != HCPhys
737	&& ( uAddress < HCPhys
738	? HCPhys - uAddress < cbPages
739	: uAddress - HCPhys < cbPages
740	)
741	)
742	AssertLogRelMsgFailedReturn(("Addr=%RTptr HCPhys=%RHp cbPages=%d\n", Addr, HCPhys, cbPages),
743	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
744
745	const unsigned cPages = cbPages >> PAGE_SHIFT;
746	int rc = pgmR3MapIntermediateCheckOne(pVM, uAddress, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
747	if (RT_FAILURE(rc))
748	return rc;
749	rc = pgmR3MapIntermediateCheckOne(pVM, (uintptr_t)HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
750	if (RT_FAILURE(rc))
751	return rc;
752
753	/*
754	* Everythings fine, do the mapping.
755	*/
756	pgmR3MapIntermediateDoOne(pVM, uAddress, HCPhys, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
757	pgmR3MapIntermediateDoOne(pVM, (uintptr_t)HCPhys, HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
758
759	return VINF_SUCCESS;
760	}
761
762
763	/**
764	* Validates that there are no conflicts for this mapping into the intermediate context.
765	*
766	* @returns VBox status code.
767	* @param pVM VM handle.
768	* @param uAddress Address of the mapping.
769	* @param cPages Number of pages.
770	* @param pPTDefault Pointer to the default page table for this mapping.
771	* @param pPTPaeDefault Pointer to the default page table for this mapping.
772	*/
773	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
774	{
775	AssertMsg((uAddress >> X86_PD_SHIFT) + cPages <= 1024, ("64-bit fixme\n"));
776
777	/*
778	* Check that the ranges are available.
779	* (This code doesn't have to be fast.)
780	*/
781	while (cPages > 0)
782	{
783	/*
784	* 32-Bit.
785	*/
786	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
787	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
788	PX86PT pPT = pPTDefault;
789	if (pVM->pgm.s.pInterPD->a[iPDE].u)
790	{
791	RTHCPHYS HCPhysPT = pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK;
792	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]))
793	pPT = pVM->pgm.s.apInterPTs[0];
794	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]))
795	pPT = pVM->pgm.s.apInterPTs[1];
796	else
797	{
798	/** @todo this must be handled with a relocation of the conflicting mapping!
799	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
800	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%RHv\n", uAddress),
801	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
802	}
803	}
804	if (pPT->a[iPTE].u)
805	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%RHv pPT->a[iPTE].u=%RX32\n", iPTE, iPDE, uAddress, pPT->a[iPTE].u),
806	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
807
808	/*
809	* PAE.
810	*/
811	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
812	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
813	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
814	Assert(iPDPE < 4);
815	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
816	PX86PTPAE pPTPae = pPTPaeDefault;
817	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
818	{
819	RTHCPHYS HCPhysPT = pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK;
820	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
821	pPTPae = pVM->pgm.s.apInterPaePTs[0];
822	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
823	pPTPae = pVM->pgm.s.apInterPaePTs[1];
824	else
825	{
826	/** @todo this must be handled with a relocation of the conflicting mapping!
827	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
828	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%RHv\n", uAddress),
829	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
830	}
831	}
832	if (pPTPae->a[iPTE].u)
833	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%RHv pPTPae->a[iPTE].u=%#RX64\n", iPTE, iPDE, uAddress, pPTPae->a[iPTE].u),
834	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
835
836	/* next */
837	uAddress += PAGE_SIZE;
838	cPages--;
839	}
840
841	return VINF_SUCCESS;
842	}
843
844
845
846	/**
847	* Sets up the intermediate page tables for a verified mapping.
848	*
849	* @param pVM VM handle.
850	* @param uAddress Address of the mapping.
851	* @param HCPhys The physical address of the page range.
852	* @param cPages Number of pages.
853	* @param pPTDefault Pointer to the default page table for this mapping.
854	* @param pPTPaeDefault Pointer to the default page table for this mapping.
855	*/
856	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
857	{
858	while (cPages > 0)
859	{
860	/*
861	* 32-Bit.
862	*/
863	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
864	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
865	PX86PT pPT;
866	if (pVM->pgm.s.pInterPD->a[iPDE].u)
867	pPT = (PX86PT)MMPagePhys2Page(pVM, pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK);
868	else
869	{
870	pVM->pgm.s.pInterPD->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
871	\| (uint32_t)MMPage2Phys(pVM, pPTDefault);
872	pPT = pPTDefault;
873	}
874	pPT->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| (uint32_t)HCPhys;
875
876	/*
877	* PAE
878	*/
879	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
880	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
881	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
882	Assert(iPDPE < 4);
883	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
884	PX86PTPAE pPTPae;
885	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
886	pPTPae = (PX86PTPAE)MMPagePhys2Page(pVM, pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK);
887	else
888	{
889	pPTPae = pPTPaeDefault;
890	pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
891	\| MMPage2Phys(pVM, pPTPaeDefault);
892	}
893	pPTPae->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| HCPhys;
894
895	/* next */
896	cPages--;
897	HCPhys += PAGE_SIZE;
898	uAddress += PAGE_SIZE;
899	}
900	}
901
902
903	/**
904	* Clears all PDEs involved with the mapping in the shadow and intermediate page tables.
905	*
906	* @param pVM The VM handle.
907	* @param pMap Pointer to the mapping in question.
908	* @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
909	*/
910	static void pgmR3MapClearPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iOldPDE)
911	{
912	unsigned i = pMap->cPTs;
913
914	pgmMapClearShadowPDEs(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pMap, iOldPDE, false /fDeactivateCR3/);
915
916	iOldPDE += i;
917	while (i-- > 0)
918	{
919	iOldPDE--;
920
921	/*
922	* 32-bit.
923	*/
924	pVM->pgm.s.pInterPD->a[iOldPDE].u = 0;
925	/*
926	* PAE.
927	*/
928	const unsigned iPD = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
929	unsigned iPDE = iOldPDE * 2 % 512;
930	pVM->pgm.s.apInterPaePDs[iPD]->a[iPDE].u = 0;
931	iPDE++;
932	AssertFatal(iPDE < 512);
933	pVM->pgm.s.apInterPaePDs[iPD]->a[iPDE].u = 0;
934	}
935	}
936
937	/**
938	* Sets all PDEs involved with the mapping in the shadow and intermediate page tables.
939	*
940	* @param pVM The VM handle.
941	* @param pMap Pointer to the mapping in question.
942	* @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
943	*/
944	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
945	{
946	PPGM pPGM = &pVM->pgm.s;
947
948	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s) \|\| PGMGetGuestMode(pVM) <= PGMMODE_PAE_NX);
949
950	pgmMapSetShadowPDEs(pVM, pMap, iNewPDE);
951
952	/*
953	* Init the page tables and insert them into the page directories.
954	*/
955	unsigned i = pMap->cPTs;
956	iNewPDE += i;
957	while (i-- > 0)
958	{
959	iNewPDE--;
960
961	/*
962	* 32-bit.
963	*/
964	X86PDE Pde;
965	/* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
966	Pde.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT;
967	pPGM->pInterPD->a[iNewPDE] = Pde;
968	/*
969	* PAE.
970	*/
971	const unsigned iPD = iNewPDE / 256;
972	unsigned iPDE = iNewPDE * 2 % 512;
973	X86PDEPAE PdePae0;
974	PdePae0.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0;
975	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae0;
976	iPDE++;
977	AssertFatal(iPDE < 512);
978	X86PDEPAE PdePae1;
979	PdePae1.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1;
980	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae1;
981	}
982	}
983
984	/**
985	* Relocates a mapping to a new address.
986	*
987	* @param pVM VM handle.
988	* @param pMapping The mapping to relocate.
989	* @param GCPtrOldMapping The address of the start of the old mapping.
990	* @param GCPtrNewMapping The address of the start of the new mapping.
991	*/
992	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping)
993	{
994	unsigned iPDOld = GCPtrOldMapping >> X86_PD_SHIFT;
995	unsigned iPDNew = GCPtrNewMapping >> X86_PD_SHIFT;
996
997	Log(("PGM: Relocating %s from %RGv to %RGv\n", pMapping->pszDesc, GCPtrOldMapping, GCPtrNewMapping));
998	AssertMsg(((unsigned)iPDOld << X86_PD_SHIFT) == pMapping->GCPtr, ("%RGv vs %RGv\n", (RTGCPTR)((unsigned)iPDOld << X86_PD_SHIFT), pMapping->GCPtr));
999
1000	/*
1001	* Relocate the page table(s).
1002	*/
1003	pgmR3MapClearPDEs(pVM, pMapping, iPDOld);
1004	pgmR3MapSetPDEs(pVM, pMapping, iPDNew);
1005
1006	/*
1007	* Update and resort the mapping list.
1008	*/
1009
1010	/* Find previous mapping for pMapping, put result into pPrevMap. */
1011	PPGMMAPPING pPrevMap = NULL;
1012	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
1013	while (pCur && pCur != pMapping)
1014	{
1015	/* next */
1016	pPrevMap = pCur;
1017	pCur = pCur->pNextR3;
1018	}
1019	Assert(pCur);
1020
1021	/* Find mapping which >= than pMapping. */
1022	RTGCPTR GCPtrNew = iPDNew << X86_PD_SHIFT;
1023	PPGMMAPPING pPrev = NULL;
1024	pCur = pVM->pgm.s.pMappingsR3;
1025	while (pCur && pCur->GCPtr < GCPtrNew)
1026	{
1027	/* next */
1028	pPrev = pCur;
1029	pCur = pCur->pNextR3;
1030	}
1031
1032	if (pCur != pMapping && pPrev != pMapping)
1033	{
1034	/*
1035	* Unlink.
1036	*/
1037	if (pPrevMap)
1038	{
1039	pPrevMap->pNextR3 = pMapping->pNextR3;
1040	pPrevMap->pNextRC = pMapping->pNextRC;
1041	pPrevMap->pNextR0 = pMapping->pNextR0;
1042	}
1043	else
1044	{
1045	pVM->pgm.s.pMappingsR3 = pMapping->pNextR3;
1046	pVM->pgm.s.pMappingsRC = pMapping->pNextRC;
1047	pVM->pgm.s.pMappingsR0 = pMapping->pNextR0;
1048	}
1049
1050	/*
1051	* Link
1052	*/
1053	pMapping->pNextR3 = pCur;
1054	if (pPrev)
1055	{
1056	pMapping->pNextRC = pPrev->pNextRC;
1057	pMapping->pNextR0 = pPrev->pNextR0;
1058	pPrev->pNextR3 = pMapping;
1059	pPrev->pNextRC = MMHyperR3ToRC(pVM, pMapping);
1060	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pMapping);
1061	}
1062	else
1063	{
1064	pMapping->pNextRC = pVM->pgm.s.pMappingsRC;
1065	pMapping->pNextR0 = pVM->pgm.s.pMappingsR0;
1066	pVM->pgm.s.pMappingsR3 = pMapping;
1067	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pMapping);
1068	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pMapping);
1069	}
1070	}
1071
1072	/*
1073	* Update the entry.
1074	*/
1075	pMapping->GCPtr = GCPtrNew;
1076	pMapping->GCPtrLast = GCPtrNew + pMapping->cb - 1;
1077
1078	/*
1079	* Callback to execute the relocation.
1080	*/
1081	pMapping->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pMapping->pvUser);
1082	}
1083
1084
1085	/**
1086	* Checks if a new mapping address wasn't previously used and caused a clash with guest mappings.
1087	*
1088	* @returns VBox status code.
1089	* @param pMapping The mapping which conflicts.
1090	* @param GCPtr New mapping address to try
1091	*/
1092	bool pgmR3MapIsKnownConflictAddress(PPGMMAPPING pMapping, RTGCPTR GCPtr)
1093	{
1094	for (unsigned i = 0; i < RT_ELEMENTS(pMapping->aGCPtrConflicts); i++)
1095	{
1096	if (GCPtr == pMapping->aGCPtrConflicts[i])
1097	return true;
1098	}
1099	return false;
1100	}
1101
1102
1103	/**
1104	* Resolves a conflict between a page table based GC mapping and
1105	* the Guest OS page tables. (32 bits version)
1106	*
1107	* @returns VBox status code.
1108	* @param pVM VM Handle.
1109	* @param pMapping The mapping which conflicts.
1110	* @param pPDSrc The page directory of the guest OS.
1111	* @param GCPtrOldMapping The address of the start of the current mapping.
1112	*/
1113	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping)
1114	{
1115	STAM_REL_COUNTER_INC(&pVM->pgm.s.cRelocations);
1116	STAM_PROFILE_START(&pVM->pgm.s.StatR3ResolveConflict, a);
1117
1118	pMapping->aGCPtrConflicts[pMapping->cConflicts & (PGMMAPPING_CONFLICT_MAX-1)] = GCPtrOldMapping;
1119	pMapping->cConflicts++;
1120
1121	/*
1122	* Scan for free page directory entries.
1123	*
1124	* Note that we do not support mappings at the very end of the
1125	* address space since that will break our GCPtrEnd assumptions.
1126	*/
1127	const unsigned cPTs = pMapping->cPTs;
1128	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
1129	while (iPDNew-- > 0)
1130	{
1131	if (pPDSrc->a[iPDNew].n.u1Present)
1132	continue;
1133
1134	if (pgmR3MapIsKnownConflictAddress(pMapping, iPDNew << X86_PD_SHIFT))
1135	continue;
1136
1137	if (cPTs > 1)
1138	{
1139	bool fOk = true;
1140	for (unsigned i = 1; fOk && i < cPTs; i++)
1141	if (pPDSrc->a[iPDNew + i].n.u1Present)
1142	fOk = false;
1143	if (!fOk)
1144	continue;
1145	}
1146
1147	/*
1148	* Check that it's not conflicting with an intermediate page table mapping.
1149	*/
1150	bool fOk = true;
1151	unsigned i = cPTs;
1152	while (fOk && i-- > 0)
1153	fOk = !pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present;
1154	if (!fOk)
1155	continue;
1156	/** @todo AMD64 should check the PAE directories and skip the 32bit stuff. */
1157
1158	/*
1159	* Ask for the mapping.
1160	*/
1161	RTGCPTR GCPtrNewMapping = iPDNew << X86_PD_SHIFT;
1162
1163	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
1164	{
1165	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
1166	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1167	return VINF_SUCCESS;
1168	}
1169	}
1170
1171	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1172	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, cPTs));
1173	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
1174	}
1175
1176
1177	/**
1178	* Resolves a conflict between a page table based GC mapping and
1179	* the Guest OS page tables. (PAE bits version)
1180	*
1181	* @returns VBox status code.
1182	* @param pVM VM Handle.
1183	* @param pMapping The mapping which conflicts.
1184	* @param GCPtrOldMapping The address of the start of the current mapping.
1185	*/
1186	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping)
1187	{
1188	STAM_REL_COUNTER_INC(&pVM->pgm.s.cRelocations);
1189	STAM_PROFILE_START(&pVM->pgm.s.StatR3ResolveConflict, a);
1190
1191	pMapping->aGCPtrConflicts[pMapping->cConflicts & (PGMMAPPING_CONFLICT_MAX-1)] = GCPtrOldMapping;
1192	pMapping->cConflicts++;
1193
1194	for (int iPDPTE = X86_PG_PAE_PDPE_ENTRIES - 1; iPDPTE >= 0; iPDPTE--)
1195	{
1196	unsigned iPDSrc;
1197	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCPTR32)iPDPTE << X86_PDPT_SHIFT, &iPDSrc, NULL);
1198
1199	/*
1200	* Scan for free page directory entries.
1201	*
1202	* Note that we do not support mappings at the very end of the
1203	* address space since that will break our GCPtrEnd assumptions.
1204	* Nor do we support mappings crossing page directories.
1205	*/
1206	const unsigned cPTs = pMapping->cb >> X86_PD_PAE_SHIFT;
1207	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
1208
1209	while (iPDNew-- > 0)
1210	{
1211	/* Ugly assumption that mappings start on a 4 MB boundary. */
1212	if (iPDNew & 1)
1213	continue;
1214
1215	if (pgmR3MapIsKnownConflictAddress(pMapping, ((RTGCPTR32)iPDPTE << X86_PDPT_SHIFT) + (iPDNew << X86_PD_PAE_SHIFT)))
1216	continue;
1217
1218	if (pPDSrc)
1219	{
1220	if (pPDSrc->a[iPDNew].n.u1Present)
1221	continue;
1222	if (cPTs > 1)
1223	{
1224	bool fOk = true;
1225	for (unsigned i = 1; fOk && i < cPTs; i++)
1226	if (pPDSrc->a[iPDNew + i].n.u1Present)
1227	fOk = false;
1228	if (!fOk)
1229	continue;
1230	}
1231	}
1232	/*
1233	* Check that it's not conflicting with an intermediate page table mapping.
1234	*/
1235	bool fOk = true;
1236	unsigned i = cPTs;
1237	while (fOk && i-- > 0)
1238	fOk = !pVM->pgm.s.apInterPaePDs[iPDPTE]->a[iPDNew + i].n.u1Present;
1239	if (!fOk)
1240	continue;
1241
1242	/*
1243	* Ask for the mapping.
1244	*/
1245	RTGCPTR GCPtrNewMapping = ((RTGCPTR32)iPDPTE << X86_PDPT_SHIFT) + (iPDNew << X86_PD_PAE_SHIFT);
1246
1247	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
1248	{
1249	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
1250	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1251	return VINF_SUCCESS;
1252	}
1253	}
1254	}
1255	STAM_PROFILE_STOP(&pVM->pgm.s.StatR3ResolveConflict, a);
1256	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, pMapping->cb >> X86_PD_PAE_SHIFT));
1257	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
1258	}
1259
1260
1261	/**
1262	* Read memory from the guest mappings.
1263	*
1264	* This will use the page tables associated with the mappings to
1265	* read the memory. This means that not all kind of memory is readable
1266	* since we don't necessarily know how to convert that physical address
1267	* to a HC virtual one.
1268	*
1269	* @returns VBox status.
1270	* @param pVM VM handle.
1271	* @param pvDst The destination address (HC of course).
1272	* @param GCPtrSrc The source address (GC virtual address).
1273	* @param cb Number of bytes to read.
1274	*
1275	* @remarks The is indirectly for DBGF only.
1276	* @todo Consider renaming it to indicate it's special usage, or just
1277	* reimplement it in MMR3HyperReadGCVirt.
1278	*/
1279	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
1280	{
1281	/*
1282	* Simplicity over speed... Chop the request up into chunks
1283	* which don't cross pages.
1284	*/
1285	if (cb + (GCPtrSrc & PAGE_OFFSET_MASK) > PAGE_SIZE)
1286	{
1287	for (;;)
1288	{
1289	size_t cbRead = RT_MIN(cb, PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK));
1290	int rc = PGMR3MapRead(pVM, pvDst, GCPtrSrc, cbRead);
1291	if (RT_FAILURE(rc))
1292	return rc;
1293	cb -= cbRead;
1294	if (!cb)
1295	break;
1296	pvDst = (char *)pvDst + cbRead;
1297	GCPtrSrc += cbRead;
1298	}
1299	return VINF_SUCCESS;
1300	}
1301
1302	/*
1303	* Find the mapping.
1304	*/
1305	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
1306	while (pCur)
1307	{
1308	RTGCPTR off = GCPtrSrc - pCur->GCPtr;
1309	if (off < pCur->cb)
1310	{
1311	if (off + cb > pCur->cb)
1312	{
1313	AssertMsgFailed(("Invalid page range %RGv LB%#x. mapping '%s' %RGv to %RGv\n",
1314	GCPtrSrc, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast));
1315	return VERR_INVALID_PARAMETER;
1316	}
1317
1318	unsigned iPT = off >> X86_PD_SHIFT;
1319	unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
1320	while (cb > 0 && iPTE < RT_ELEMENTS(CTXALLSUFF(pCur->aPTs[iPT].pPT)->a))
1321	{
1322	if (!CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].n.u1Present)
1323	return VERR_PAGE_NOT_PRESENT;
1324	RTHCPHYS HCPhys = CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].u & X86_PTE_PAE_PG_MASK;
1325
1326	/*
1327	* Get the virtual page from the physical one.
1328	*/
1329	void *pvPage;
1330	int rc = MMR3HCPhys2HCVirt(pVM, HCPhys, &pvPage);
1331	if (RT_FAILURE(rc))
1332	return rc;
1333
1334	memcpy(pvDst, (char *)pvPage + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
1335	return VINF_SUCCESS;
1336	}
1337	}
1338
1339	/* next */
1340	pCur = CTXALLSUFF(pCur->pNext);
1341	}
1342
1343	return VERR_INVALID_POINTER;
1344	}
1345
1346
1347	/**
1348	* Info callback for 'pgmhandlers'.
1349	*
1350	* @param pHlp The output helpers.
1351	* @param pszArgs The arguments. phys or virt.
1352	*/
1353	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1354	{
1355	pHlp->pfnPrintf(pHlp, pVM->pgm.s.fMappingsFixed
1356	? "\nThe mappings are FIXED.\n"
1357	: "\nThe mappings are FLOATING.\n");
1358	PPGMMAPPING pCur;
1359	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1360	pHlp->pfnPrintf(pHlp, "%RGv - %RGv %s\n", pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
1361	}
1362

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source: vbox/trunk/src/VBox/VMM/PGMMap.cpp@ 18291

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