VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 17288

Last change on this file since 17288 was 17251, checked in by vboxsync, 16 years ago

VMM,REM,DevPcArch: VBOX_WITH_NEW_PHYS_CODE changes.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 88.6 KB
Line 
1/* $Id: PGMPhys.cpp 17251 2009-03-02 13:55:31Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM
27#include <VBox/pgm.h>
28#include <VBox/cpum.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/rem.h>
34#include <VBox/csam.h>
35#include "PGMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/dbg.h>
38#include <VBox/param.h>
39#include <VBox/err.h>
40#include <iprt/assert.h>
41#include <iprt/alloc.h>
42#include <iprt/asm.h>
43#include <VBox/log.h>
44#include <iprt/thread.h>
45#include <iprt/string.h>
46
47
48/*******************************************************************************
49* Internal Functions *
50*******************************************************************************/
51/*static - shut up warning */
52DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
53
54
55
56/*
57 * PGMR3PhysReadU8-64
58 * PGMR3PhysWriteU8-64
59 */
60#define PGMPHYSFN_READNAME PGMR3PhysReadU8
61#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
62#define PGMPHYS_DATASIZE 1
63#define PGMPHYS_DATATYPE uint8_t
64#include "PGMPhysRWTmpl.h"
65
66#define PGMPHYSFN_READNAME PGMR3PhysReadU16
67#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
68#define PGMPHYS_DATASIZE 2
69#define PGMPHYS_DATATYPE uint16_t
70#include "PGMPhysRWTmpl.h"
71
72#define PGMPHYSFN_READNAME PGMR3PhysReadU32
73#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
74#define PGMPHYS_DATASIZE 4
75#define PGMPHYS_DATATYPE uint32_t
76#include "PGMPhysRWTmpl.h"
77
78#define PGMPHYSFN_READNAME PGMR3PhysReadU64
79#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
80#define PGMPHYS_DATASIZE 8
81#define PGMPHYS_DATATYPE uint64_t
82#include "PGMPhysRWTmpl.h"
83
84
85
86/**
87 * Links a new RAM range into the list.
88 *
89 * @param pVM Pointer to the shared VM structure.
90 * @param pNew Pointer to the new list entry.
91 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
92 */
93static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
94{
95 pgmLock(pVM);
96
97 PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
98 pNew->pNextR3 = pRam;
99 pNew->pNextR0 = pRam ? MMHyperCCToR0(pVM, pRam) : NIL_RTR0PTR;
100 pNew->pNextRC = pRam ? MMHyperCCToRC(pVM, pRam) : NIL_RTRCPTR;
101
102 if (pPrev)
103 {
104 pPrev->pNextR3 = pNew;
105 pPrev->pNextR0 = MMHyperCCToR0(pVM, pNew);
106 pPrev->pNextRC = MMHyperCCToRC(pVM, pNew);
107 }
108 else
109 {
110 pVM->pgm.s.pRamRangesR3 = pNew;
111 pVM->pgm.s.pRamRangesR0 = MMHyperCCToR0(pVM, pNew);
112 pVM->pgm.s.pRamRangesRC = MMHyperCCToRC(pVM, pNew);
113 }
114
115 pgmUnlock(pVM);
116}
117
118
119/**
120 * Unlink an existing RAM range from the list.
121 *
122 * @param pVM Pointer to the shared VM structure.
123 * @param pRam Pointer to the new list entry.
124 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
125 */
126static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
127{
128 Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
129
130 pgmLock(pVM);
131
132 PPGMRAMRANGE pNext = pRam->pNextR3;
133 if (pPrev)
134 {
135 pPrev->pNextR3 = pNext;
136 pPrev->pNextR0 = pNext ? MMHyperCCToR0(pVM, pNext) : NIL_RTR0PTR;
137 pPrev->pNextRC = pNext ? MMHyperCCToRC(pVM, pNext) : NIL_RTRCPTR;
138 }
139 else
140 {
141 Assert(pVM->pgm.s.pRamRangesR3 == pRam);
142 pVM->pgm.s.pRamRangesR3 = pNext;
143 pVM->pgm.s.pRamRangesR0 = pNext ? MMHyperCCToR0(pVM, pNext) : NIL_RTR0PTR;
144 pVM->pgm.s.pRamRangesRC = pNext ? MMHyperCCToRC(pVM, pNext) : NIL_RTRCPTR;
145 }
146
147 pgmUnlock(pVM);
148}
149
150
151/**
152 * Unlink an existing RAM range from the list.
153 *
154 * @param pVM Pointer to the shared VM structure.
155 * @param pRam Pointer to the new list entry.
156 */
157static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
158{
159 /* find prev. */
160 PPGMRAMRANGE pPrev = NULL;
161 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
162 while (pCur != pRam)
163 {
164 pPrev = pCur;
165 pCur = pCur->pNextR3;
166 }
167 AssertFatal(pCur);
168
169 pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
170}
171
172
173/**
174 * Sets up a range RAM.
175 *
176 * This will check for conflicting registrations, make a resource
177 * reservation for the memory (with GMM), and setup the per-page
178 * tracking structures (PGMPAGE).
179 *
180 * @returns VBox stutus code.
181 * @param pVM Pointer to the shared VM structure.
182 * @param GCPhys The physical address of the RAM.
183 * @param cb The size of the RAM.
184 * @param pszDesc The description - not copied, so, don't free or change it.
185 */
186VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
187{
188 /*
189 * Validate input.
190 */
191 Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
192 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
193 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
194 AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
195 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
196 AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
197 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
198 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
199
200 /*
201 * Find range location and check for conflicts.
202 * (We don't lock here because the locking by EMT is only required on update.)
203 */
204 PPGMRAMRANGE pPrev = NULL;
205 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
206 while (pRam && GCPhysLast >= pRam->GCPhys)
207 {
208 if ( GCPhysLast >= pRam->GCPhys
209 && GCPhys <= pRam->GCPhysLast)
210 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
211 GCPhys, GCPhysLast, pszDesc,
212 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
213 VERR_PGM_RAM_CONFLICT);
214
215 /* next */
216 pPrev = pRam;
217 pRam = pRam->pNextR3;
218 }
219
220 /*
221 * Register it with GMM (the API bitches).
222 */
223 const RTGCPHYS cPages = cb >> PAGE_SHIFT;
224 int rc = MMR3IncreaseBaseReservation(pVM, cPages);
225 if (RT_FAILURE(rc))
226 return rc;
227
228 /*
229 * Allocate RAM range.
230 */
231 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
232 PPGMRAMRANGE pNew;
233 rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
234 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
235
236 /*
237 * Initialize the range.
238 */
239 pNew->GCPhys = GCPhys;
240 pNew->GCPhysLast = GCPhysLast;
241 pNew->pszDesc = pszDesc;
242 pNew->cb = cb;
243 pNew->fFlags = 0;
244
245 pNew->pvR3 = NULL;
246#ifndef VBOX_WITH_NEW_PHYS_CODE
247 pNew->paChunkR3Ptrs = NULL;
248
249 /* Allocate memory for chunk to HC ptr lookup array. */
250 rc = MMHyperAlloc(pVM, (cb >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(void *), 16, MM_TAG_PGM, (void **)&pNew->paChunkR3Ptrs);
251 AssertRCReturn(rc, rc);
252 pNew->fFlags |= MM_RAM_FLAGS_DYNAMIC_ALLOC;
253
254#endif
255 RTGCPHYS iPage = cPages;
256 while (iPage-- > 0)
257 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
258
259 /*
260 * Insert the new RAM range.
261 */
262 pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
263
264 /*
265 * Notify REM.
266 */
267#ifdef VBOX_WITH_NEW_PHYS_CODE
268 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, 0);
269#else
270 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, MM_RAM_FLAGS_DYNAMIC_ALLOC);
271#endif
272
273 return VINF_SUCCESS;
274}
275
276
277/**
278 * Resets (zeros) the RAM.
279 *
280 * ASSUMES that the caller owns the PGM lock.
281 *
282 * @returns VBox status code.
283 * @param pVM Pointer to the shared VM structure.
284 */
285int pgmR3PhysRamReset(PVM pVM)
286{
287 /*
288 * Walk the ram ranges.
289 */
290 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
291 {
292 uint32_t iPage = pRam->cb >> PAGE_SHIFT; Assert((RTGCPHYS)iPage << PAGE_SHIFT == pRam->cb);
293#ifdef VBOX_WITH_NEW_PHYS_CODE
294 if (!pVM->pgm.f.fRamPreAlloc)
295 {
296 /* Replace all RAM pages by ZERO pages. */
297 while (iPage-- > 0)
298 {
299 PPGMPAGE pPage = &pRam->aPages[iPage];
300 switch (PGM_PAGE_GET_TYPE(pPage))
301 {
302 case PGMPAGETYPE_RAM:
303 if (!PGM_PAGE_IS_ZERO(pPage))
304 pgmPhysFreePage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
305 break;
306
307 case PGMPAGETYPE_MMIO2:
308 case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
309 case PGMPAGETYPE_ROM:
310 case PGMPAGETYPE_MMIO:
311 break;
312 default:
313 AssertFailed();
314 }
315 } /* for each page */
316 }
317 else
318#endif
319 {
320 /* Zero the memory. */
321 while (iPage-- > 0)
322 {
323 PPGMPAGE pPage = &pRam->aPages[iPage];
324 switch (PGM_PAGE_GET_TYPE(pPage))
325 {
326#ifndef VBOX_WITH_NEW_PHYS_CODE
327 case PGMPAGETYPE_INVALID:
328 case PGMPAGETYPE_RAM:
329 if (pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2)) /** @todo PAGE FLAGS */
330 {
331 /* shadow ram is reloaded elsewhere. */
332 Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO))); /** @todo PAGE FLAGS */
333 continue;
334 }
335 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
336 {
337 unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
338 if (pRam->paChunkR3Ptrs[iChunk])
339 ASMMemZero32((char *)pRam->paChunkR3Ptrs[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
340 }
341 else
342 ASMMemZero32((char *)pRam->pvR3 + (iPage << PAGE_SHIFT), PAGE_SIZE);
343 break;
344#else /* VBOX_WITH_NEW_PHYS_CODE */
345 case PGMPAGETYPE_RAM:
346 switch (PGM_PAGE_GET_STATE(pPage))
347 {
348 case PGM_PAGE_STATE_ZERO:
349 break;
350 case PGM_PAGE_STATE_SHARED:
351 case PGM_PAGE_STATE_WRITE_MONITORED:
352 rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
353 AssertLogRelRCReturn(rc, rc);
354 case PGM_PAGE_STATE_ALLOCATED:
355 {
356 void *pvPage;
357 PPGMPAGEMAP pMapIgnored;
358 rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pMapIgnored, &pvPage);
359 AssertLogRelRCReturn(rc, rc);
360 ASMMemZeroPage(pvPage);
361 break;
362 }
363 }
364 break;
365#endif /* VBOX_WITH_NEW_PHYS_CODE */
366
367 case PGMPAGETYPE_MMIO2:
368 case PGMPAGETYPE_ROM_SHADOW:
369 case PGMPAGETYPE_ROM:
370 case PGMPAGETYPE_MMIO:
371 break;
372 default:
373 AssertFailed();
374
375 }
376 } /* for each page */
377 }
378
379 }
380
381 return VINF_SUCCESS;
382}
383
384
385/**
386 * This is the interface IOM is using to register an MMIO region.
387 *
388 * It will check for conflicts and ensure that a RAM range structure
389 * is present before calling the PGMR3HandlerPhysicalRegister API to
390 * register the callbacks.
391 *
392 * @returns VBox status code.
393 *
394 * @param pVM Pointer to the shared VM structure.
395 * @param GCPhys The start of the MMIO region.
396 * @param cb The size of the MMIO region.
397 * @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
398 * @param pvUserR3 The user argument for R3.
399 * @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
400 * @param pvUserR0 The user argument for R0.
401 * @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
402 * @param pvUserRC The user argument for RC.
403 * @param pszDesc The description of the MMIO region.
404 */
405VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
406 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
407 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
408 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
409 R3PTRTYPE(const char *) pszDesc)
410{
411 /*
412 * Assert on some assumption.
413 */
414 VM_ASSERT_EMT(pVM);
415 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
416 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
417 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
418 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
419
420 /*
421 * Make sure there's a RAM range structure for the region.
422 */
423 int rc;
424 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
425 bool fRamExists = false;
426 PPGMRAMRANGE pRamPrev = NULL;
427 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
428 while (pRam && GCPhysLast >= pRam->GCPhys)
429 {
430 if ( GCPhysLast >= pRam->GCPhys
431 && GCPhys <= pRam->GCPhysLast)
432 {
433 /* Simplification: all within the same range. */
434 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
435 && GCPhysLast <= pRam->GCPhysLast,
436 ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
437 GCPhys, GCPhysLast, pszDesc,
438 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
439 VERR_PGM_RAM_CONFLICT);
440
441 /* Check that it's all RAM or MMIO pages. */
442 PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
443 uint32_t cLeft = cb >> PAGE_SHIFT;
444 while (cLeft-- > 0)
445 {
446 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
447 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
448 ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
449 GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
450 VERR_PGM_RAM_CONFLICT);
451 pPage++;
452 }
453
454 /* Looks good. */
455 fRamExists = true;
456 break;
457 }
458
459 /* next */
460 pRamPrev = pRam;
461 pRam = pRam->pNextR3;
462 }
463 PPGMRAMRANGE pNew;
464 if (fRamExists)
465 pNew = NULL;
466 else
467 {
468 /*
469 * No RAM range, insert an ad-hoc one.
470 *
471 * Note that we don't have to tell REM about this range because
472 * PGMHandlerPhysicalRegisterEx will do that for us.
473 */
474 Log(("PGMR3PhysMMIORegister: Adding ad-hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
475
476 const uint32_t cPages = cb >> PAGE_SHIFT;
477 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
478 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
479 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
480
481 /* Initialize the range. */
482 pNew->GCPhys = GCPhys;
483 pNew->GCPhysLast = GCPhysLast;
484 pNew->pszDesc = pszDesc;
485 pNew->cb = cb;
486 pNew->fFlags = 0; /* Some MMIO flag here? */
487
488 pNew->pvR3 = NULL;
489#ifndef VBOX_WITH_NEW_PHYS_CODE
490 pNew->paChunkR3Ptrs = NULL;
491#endif
492
493 uint32_t iPage = cPages;
494 while (iPage-- > 0)
495 PGM_PAGE_INIT_ZERO_REAL(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
496 Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
497
498 /* link it */
499 pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
500 }
501
502 /*
503 * Register the access handler.
504 */
505 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
506 pfnHandlerR3, pvUserR3,
507 pfnHandlerR0, pvUserR0,
508 pfnHandlerRC, pvUserRC, pszDesc);
509 if ( RT_FAILURE(rc)
510 && !fRamExists)
511 {
512 /* remove the ad-hoc range. */
513 pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
514 pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
515 MMHyperFree(pVM, pRam);
516 }
517
518 return rc;
519}
520
521
522/**
523 * This is the interface IOM is using to register an MMIO region.
524 *
525 * It will take care of calling PGMHandlerPhysicalDeregister and clean up
526 * any ad-hoc PGMRAMRANGE left behind.
527 *
528 * @returns VBox status code.
529 * @param pVM Pointer to the shared VM structure.
530 * @param GCPhys The start of the MMIO region.
531 * @param cb The size of the MMIO region.
532 */
533VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
534{
535 VM_ASSERT_EMT(pVM);
536
537 /*
538 * First deregister the handler, then check if we should remove the ram range.
539 */
540 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
541 if (RT_SUCCESS(rc))
542 {
543 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
544 PPGMRAMRANGE pRamPrev = NULL;
545 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
546 while (pRam && GCPhysLast >= pRam->GCPhys)
547 {
548 /*if ( GCPhysLast >= pRam->GCPhys
549 && GCPhys <= pRam->GCPhysLast) - later */
550 if ( GCPhysLast == pRam->GCPhysLast
551 && GCPhys == pRam->GCPhys)
552 {
553 Assert(pRam->cb == cb);
554
555 /*
556 * See if all the pages are dead MMIO pages.
557 */
558 bool fAllMMIO = true;
559 PPGMPAGE pPage = &pRam->aPages[0];
560 uint32_t cLeft = cb >> PAGE_SHIFT;
561 while (cLeft-- > 0)
562 {
563 if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
564 /*|| not-out-of-action later */)
565 {
566 fAllMMIO = false;
567 break;
568 }
569 pPage++;
570 }
571
572 /*
573 * Unlink it and free if it's all MMIO.
574 */
575 if (fAllMMIO)
576 {
577 Log(("PGMR3PhysMMIODeregister: Freeing ad-hoc MMIO range for %RGp-%RGp %s\n",
578 GCPhys, GCPhysLast, pRam->pszDesc));
579
580 pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
581 pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
582 MMHyperFree(pVM, pRam);
583 }
584 break;
585 }
586
587 /* next */
588 pRamPrev = pRam;
589 pRam = pRam->pNextR3;
590 }
591 }
592
593 return rc;
594}
595
596
597/**
598 * Locate a MMIO2 range.
599 *
600 * @returns Pointer to the MMIO2 range.
601 * @param pVM Pointer to the shared VM structure.
602 * @param pDevIns The device instance owning the region.
603 * @param iRegion The region.
604 */
605DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
606{
607 /*
608 * Search the list.
609 */
610 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
611 if ( pCur->pDevInsR3 == pDevIns
612 && pCur->iRegion == iRegion)
613 return pCur;
614 return NULL;
615}
616
617
618/**
619 * Allocate and register an MMIO2 region.
620 *
621 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
622 * RAM associated with a device. It is also non-shared memory with a
623 * permanent ring-3 mapping and page backing (presently).
624 *
625 * A MMIO2 range may overlap with base memory if a lot of RAM
626 * is configured for the VM, in which case we'll drop the base
627 * memory pages. Presently we will make no attempt to preserve
628 * anything that happens to be present in the base memory that
629 * is replaced, this is of course incorrectly but it's too much
630 * effort.
631 *
632 * @returns VBox status code.
633 * @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
634 * @retval VERR_ALREADY_EXISTS if the region already exists.
635 *
636 * @param pVM Pointer to the shared VM structure.
637 * @param pDevIns The device instance owning the region.
638 * @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
639 * this number has to be the number of that region. Otherwise
640 * it can be any number safe UINT8_MAX.
641 * @param cb The size of the region. Must be page aligned.
642 * @param fFlags Reserved for future use, must be zero.
643 * @param ppv Where to store the pointer to the ring-3 mapping of the memory.
644 * @param pszDesc The description.
645 */
646VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)
647{
648 /*
649 * Validate input.
650 */
651 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
652 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
653 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
654 AssertPtrReturn(ppv, VERR_INVALID_POINTER);
655 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
656 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
657 AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
658 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
659 AssertReturn(cb, VERR_INVALID_PARAMETER);
660 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
661
662 const uint32_t cPages = cb >> PAGE_SHIFT;
663 AssertLogRelReturn((RTGCPHYS)cPages << PAGE_SHIFT == cb, VERR_INVALID_PARAMETER);
664 AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
665
666 /*
667 * Try reserve and allocate the backing memory first as this is what is
668 * most likely to fail.
669 */
670 int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
671 if (RT_FAILURE(rc))
672 return rc;
673
674 void *pvPages;
675 PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
676 if (RT_SUCCESS(rc))
677 rc = SUPR3PageAllocEx(cPages, 0 /*fFlags*/, &pvPages, NULL /*pR0Ptr*/, paPages);
678 if (RT_SUCCESS(rc))
679 {
680 memset(pvPages, 0, cPages * PAGE_SIZE);
681
682 /*
683 * Create the MMIO2 range record for it.
684 */
685 const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
686 PPGMMMIO2RANGE pNew;
687 rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
688 AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
689 if (RT_SUCCESS(rc))
690 {
691 pNew->pDevInsR3 = pDevIns;
692 pNew->pvR3 = pvPages;
693 //pNew->pNext = NULL;
694 //pNew->fMapped = false;
695 //pNew->fOverlapping = false;
696 pNew->iRegion = iRegion;
697 pNew->RamRange.GCPhys = NIL_RTGCPHYS;
698 pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
699 pNew->RamRange.pszDesc = pszDesc;
700 pNew->RamRange.cb = cb;
701 //pNew->RamRange.fFlags = 0;
702
703 pNew->RamRange.pvR3 = pvPages; ///@todo remove this [new phys code]
704#ifndef VBOX_WITH_NEW_PHYS_CODE
705 pNew->RamRange.paChunkR3Ptrs = NULL; ///@todo remove this [new phys code]
706#endif
707
708 uint32_t iPage = cPages;
709 while (iPage-- > 0)
710 {
711 PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
712 paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
713 PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
714 }
715
716 /*
717 * Link it into the list.
718 * Since there is no particular order, just push it.
719 */
720 pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
721 pVM->pgm.s.pMmio2RangesR3 = pNew;
722
723 *ppv = pvPages;
724 RTMemTmpFree(paPages);
725 return VINF_SUCCESS;
726 }
727
728 SUPR3PageFreeEx(pvPages, cPages);
729 }
730 RTMemTmpFree(paPages);
731 MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
732 return rc;
733}
734
735
736/**
737 * Deregisters and frees an MMIO2 region.
738 *
739 * Any physical (and virtual) access handlers registered for the region must
740 * be deregistered before calling this function.
741 *
742 * @returns VBox status code.
743 * @param pVM Pointer to the shared VM structure.
744 * @param pDevIns The device instance owning the region.
745 * @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
746 */
747VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
748{
749 /*
750 * Validate input.
751 */
752 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
753 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
754 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
755
756 int rc = VINF_SUCCESS;
757 unsigned cFound = 0;
758 PPGMMMIO2RANGE pPrev = NULL;
759 PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
760 while (pCur)
761 {
762 if ( pCur->pDevInsR3 == pDevIns
763 && ( iRegion == UINT32_MAX
764 || pCur->iRegion == iRegion))
765 {
766 cFound++;
767
768 /*
769 * Unmap it if it's mapped.
770 */
771 if (pCur->fMapped)
772 {
773 int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
774 AssertRC(rc2);
775 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
776 rc = rc2;
777 }
778
779 /*
780 * Unlink it
781 */
782 PPGMMMIO2RANGE pNext = pCur->pNextR3;
783 if (pPrev)
784 pPrev->pNextR3 = pNext;
785 else
786 pVM->pgm.s.pMmio2RangesR3 = pNext;
787 pCur->pNextR3 = NULL;
788
789 /*
790 * Free the memory.
791 */
792 int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
793 AssertRC(rc2);
794 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
795 rc = rc2;
796
797 rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)(pCur->RamRange.cb >> PAGE_SHIFT), pCur->RamRange.pszDesc);
798 AssertRC(rc2);
799 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
800 rc = rc2;
801
802 /* we're leaking hyper memory here if done at runtime. */
803 Assert( VMR3GetState(pVM) == VMSTATE_OFF
804 || VMR3GetState(pVM) == VMSTATE_DESTROYING
805 || VMR3GetState(pVM) == VMSTATE_TERMINATED
806 || VMR3GetState(pVM) == VMSTATE_CREATING);
807 /*rc = MMHyperFree(pVM, pCur);
808 AssertRCReturn(rc, rc); - not safe, see the alloc call. */
809
810 /* next */
811 pCur = pNext;
812 }
813 else
814 {
815 pPrev = pCur;
816 pCur = pCur->pNextR3;
817 }
818 }
819
820 return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
821}
822
823
824/**
825 * Maps a MMIO2 region.
826 *
827 * This is done when a guest / the bios / state loading changes the
828 * PCI config. The replacing of base memory has the same restrictions
829 * as during registration, of course.
830 *
831 * @returns VBox status code.
832 *
833 * @param pVM Pointer to the shared VM structure.
834 * @param pDevIns The
835 */
836VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
837{
838 /*
839 * Validate input
840 */
841 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
842 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
843 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
844 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
845 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
846 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
847
848 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
849 AssertReturn(pCur, VERR_NOT_FOUND);
850 AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
851 Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
852 Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
853
854 const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
855 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
856
857 /*
858 * Find our location in the ram range list, checking for
859 * restriction we don't bother implementing yet (partially overlapping).
860 */
861 bool fRamExists = false;
862 PPGMRAMRANGE pRamPrev = NULL;
863 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
864 while (pRam && GCPhysLast >= pRam->GCPhys)
865 {
866 if ( GCPhys <= pRam->GCPhysLast
867 && GCPhysLast >= pRam->GCPhys)
868 {
869 /* completely within? */
870 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
871 && GCPhysLast <= pRam->GCPhysLast,
872 ("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
873 GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
874 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
875 VERR_PGM_RAM_CONFLICT);
876 fRamExists = true;
877 break;
878 }
879
880 /* next */
881 pRamPrev = pRam;
882 pRam = pRam->pNextR3;
883 }
884 if (fRamExists)
885 {
886 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
887 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
888 while (cPagesLeft-- > 0)
889 {
890 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
891 ("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
892 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
893 VERR_PGM_RAM_CONFLICT);
894 pPage++;
895 }
896 }
897 Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
898 GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
899
900 /*
901 * Make the changes.
902 */
903 pgmLock(pVM);
904
905 pCur->RamRange.GCPhys = GCPhys;
906 pCur->RamRange.GCPhysLast = GCPhysLast;
907 pCur->fMapped = true;
908 pCur->fOverlapping = fRamExists;
909
910 if (fRamExists)
911 {
912 /* replace the pages, freeing all present RAM pages. */
913 PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
914 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
915 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
916 while (cPagesLeft-- > 0)
917 {
918 pgmPhysFreePage(pVM, pPageDst, GCPhys);
919
920 RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
921 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
922 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
923 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
924
925 GCPhys += PAGE_SIZE;
926 pPageSrc++;
927 pPageDst++;
928 }
929 }
930 else
931 {
932 /* link in the ram range */
933 pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
934 REMR3NotifyPhysRamRegister(pVM, GCPhys, pCur->RamRange.cb, 0);
935 }
936
937 pgmUnlock(pVM);
938
939 return VINF_SUCCESS;
940}
941
942
943/**
944 * Unmaps a MMIO2 region.
945 *
946 * This is done when a guest / the bios / state loading changes the
947 * PCI config. The replacing of base memory has the same restrictions
948 * as during registration, of course.
949 */
950VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
951{
952 /*
953 * Validate input
954 */
955 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
956 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
957 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
958 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
959 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
960 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
961
962 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
963 AssertReturn(pCur, VERR_NOT_FOUND);
964 AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
965 AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
966 Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
967
968 Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
969 pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
970
971 /*
972 * Unmap it.
973 */
974 pgmLock(pVM);
975
976 if (pCur->fOverlapping)
977 {
978 /* Restore the RAM pages we've replaced. */
979 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
980 while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
981 pRam = pRam->pNextR3;
982
983#ifdef RT_STRICT
984 RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
985#endif
986 Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
987 PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
988 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
989 while (cPagesLeft-- > 0)
990 {
991 PGM_PAGE_SET_HCPHYS(pPageDst, pVM->pgm.s.HCPhysZeroPg);
992 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
993 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
994
995 pPageDst++;
996 }
997 }
998 else
999 {
1000 REMR3NotifyPhysRamDeregister(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb);
1001 pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
1002 }
1003
1004 pCur->RamRange.GCPhys = NIL_RTGCPHYS;
1005 pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
1006 pCur->fOverlapping = false;
1007 pCur->fMapped = false;
1008
1009 pgmUnlock(pVM);
1010
1011 return VINF_SUCCESS;
1012}
1013
1014
1015/**
1016 * Checks if the given address is an MMIO2 base address or not.
1017 *
1018 * @returns true/false accordingly.
1019 * @param pVM Pointer to the shared VM structure.
1020 * @param pDevIns The owner of the memory, optional.
1021 * @param GCPhys The address to check.
1022 */
1023VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
1024{
1025 /*
1026 * Validate input
1027 */
1028 VM_ASSERT_EMT_RETURN(pVM, false);
1029 AssertPtrReturn(pDevIns, false);
1030 AssertReturn(GCPhys != NIL_RTGCPHYS, false);
1031 AssertReturn(GCPhys != 0, false);
1032 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
1033
1034 /*
1035 * Search the list.
1036 */
1037 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1038 if (pCur->RamRange.GCPhys == GCPhys)
1039 {
1040 Assert(pCur->fMapped);
1041 return true;
1042 }
1043 return false;
1044}
1045
1046
1047/**
1048 * Gets the HC physical address of a page in the MMIO2 region.
1049 *
1050 * This is API is intended for MMHyper and shouldn't be called
1051 * by anyone else...
1052 *
1053 * @returns VBox status code.
1054 * @param pVM Pointer to the shared VM structure.
1055 * @param pDevIns The owner of the memory, optional.
1056 * @param iRegion The region.
1057 * @param off The page expressed an offset into the MMIO2 region.
1058 * @param pHCPhys Where to store the result.
1059 */
1060VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
1061{
1062 /*
1063 * Validate input
1064 */
1065 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1066 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1067 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1068
1069 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1070 AssertReturn(pCur, VERR_NOT_FOUND);
1071 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1072
1073 PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
1074 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
1075 return VINF_SUCCESS;
1076}
1077
1078
1079/**
1080 * Maps a portion of an MMIO2 region into kernel space (host).
1081 *
1082 * The kernel mapping will become invalid when the MMIO2 memory is deregistered
1083 * or the VM is terminated.
1084 *
1085 * @return VBox status code.
1086 *
1087 * @param pVM Pointer to the shared VM structure.
1088 * @param pDevIns The device owning the MMIO2 memory.
1089 * @param iRegion The region.
1090 * @param off The offset into the region. Must be page aligned.
1091 * @param cb The number of bytes to map. Must be page aligned.
1092 * @param pszDesc Mapping description.
1093 * @param pR0Ptr Where to store the R0 address.
1094 */
1095VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
1096 const char *pszDesc, PRTR0PTR pR0Ptr)
1097{
1098 /*
1099 * Validate input.
1100 */
1101 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1102 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1103 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1104
1105 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1106 AssertReturn(pCur, VERR_NOT_FOUND);
1107 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1108 AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1109 AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1110
1111 /*
1112 * Pass the request on to the support library/driver.
1113 */
1114 int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
1115
1116 return rc;
1117}
1118
1119
1120/**
1121 * Registers a ROM image.
1122 *
1123 * Shadowed ROM images requires double the amount of backing memory, so,
1124 * don't use that unless you have to. Shadowing of ROM images is process
1125 * where we can select where the reads go and where the writes go. On real
1126 * hardware the chipset provides means to configure this. We provide
1127 * PGMR3PhysProtectROM() for this purpose.
1128 *
1129 * A read-only copy of the ROM image will always be kept around while we
1130 * will allocate RAM pages for the changes on demand (unless all memory
1131 * is configured to be preallocated).
1132 *
1133 * @returns VBox status.
1134 * @param pVM VM Handle.
1135 * @param pDevIns The device instance owning the ROM.
1136 * @param GCPhys First physical address in the range.
1137 * Must be page aligned!
1138 * @param cbRange The size of the range (in bytes).
1139 * Must be page aligned!
1140 * @param pvBinary Pointer to the binary data backing the ROM image.
1141 * This must be exactly \a cbRange in size.
1142 * @param fFlags Mask of flags. PGMPHYS_ROM_FLAG_SHADOWED
1143 * and/or PGMPHYS_ROM_FLAG_PERMANENT_BINARY.
1144 * @param pszDesc Pointer to description string. This must not be freed.
1145 *
1146 * @remark There is no way to remove the rom, automatically on device cleanup or
1147 * manually from the device yet. This isn't difficult in any way, it's
1148 * just not something we expect to be necessary for a while.
1149 */
1150VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
1151 const void *pvBinary, uint32_t fFlags, const char *pszDesc)
1152{
1153 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
1154 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
1155
1156 /*
1157 * Validate input.
1158 */
1159 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1160 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1161 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1162 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1163 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1164 AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
1165 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1166 AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAG_SHADOWED | PGMPHYS_ROM_FLAG_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
1167 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
1168
1169 const uint32_t cPages = cb >> PAGE_SHIFT;
1170
1171 /*
1172 * Find the ROM location in the ROM list first.
1173 */
1174 PPGMROMRANGE pRomPrev = NULL;
1175 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
1176 while (pRom && GCPhysLast >= pRom->GCPhys)
1177 {
1178 if ( GCPhys <= pRom->GCPhysLast
1179 && GCPhysLast >= pRom->GCPhys)
1180 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1181 GCPhys, GCPhysLast, pszDesc,
1182 pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
1183 VERR_PGM_RAM_CONFLICT);
1184 /* next */
1185 pRomPrev = pRom;
1186 pRom = pRom->pNextR3;
1187 }
1188
1189 /*
1190 * Find the RAM location and check for conflicts.
1191 *
1192 * Conflict detection is a bit different than for RAM
1193 * registration since a ROM can be located within a RAM
1194 * range. So, what we have to check for is other memory
1195 * types (other than RAM that is) and that we don't span
1196 * more than one RAM range (layz).
1197 */
1198 bool fRamExists = false;
1199 PPGMRAMRANGE pRamPrev = NULL;
1200 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1201 while (pRam && GCPhysLast >= pRam->GCPhys)
1202 {
1203 if ( GCPhys <= pRam->GCPhysLast
1204 && GCPhysLast >= pRam->GCPhys)
1205 {
1206 /* completely within? */
1207 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1208 && GCPhysLast <= pRam->GCPhysLast,
1209 ("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
1210 GCPhys, GCPhysLast, pszDesc,
1211 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1212 VERR_PGM_RAM_CONFLICT);
1213 fRamExists = true;
1214 break;
1215 }
1216
1217 /* next */
1218 pRamPrev = pRam;
1219 pRam = pRam->pNextR3;
1220 }
1221 if (fRamExists)
1222 {
1223 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1224 uint32_t cPagesLeft = cPages;
1225 while (cPagesLeft-- > 0)
1226 {
1227 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1228 ("%RGp isn't a RAM page (%d) - registering %RGp-%RGp (%s).\n",
1229 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pszDesc),
1230 VERR_PGM_RAM_CONFLICT);
1231 Assert(PGM_PAGE_IS_ZERO(pPage));
1232 pPage++;
1233 }
1234 }
1235
1236 /*
1237 * Update the base memory reservation if necessary.
1238 */
1239 uint32_t cExtraBaseCost = fRamExists ? cPages : 0;
1240 if (fFlags & PGMPHYS_ROM_FLAG_SHADOWED)
1241 cExtraBaseCost += cPages;
1242 if (cExtraBaseCost)
1243 {
1244 int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
1245 if (RT_FAILURE(rc))
1246 return rc;
1247 }
1248
1249 /*
1250 * Allocate memory for the virgin copy of the RAM.
1251 */
1252 PGMMALLOCATEPAGESREQ pReq;
1253 int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
1254 AssertRCReturn(rc, rc);
1255
1256 for (uint32_t iPage = 0; iPage < cPages; iPage++)
1257 {
1258 pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
1259 pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
1260 pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
1261 }
1262
1263 pgmLock(pVM);
1264 rc = GMMR3AllocatePagesPerform(pVM, pReq);
1265 pgmUnlock(pVM);
1266 if (RT_FAILURE(rc))
1267 {
1268 GMMR3AllocatePagesCleanup(pReq);
1269 return rc;
1270 }
1271
1272 /*
1273 * Allocate the new ROM range and RAM range (if necessary).
1274 */
1275 PPGMROMRANGE pRomNew;
1276 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
1277 if (RT_SUCCESS(rc))
1278 {
1279 PPGMRAMRANGE pRamNew = NULL;
1280 if (!fRamExists)
1281 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
1282 if (RT_SUCCESS(rc))
1283 {
1284 pgmLock(pVM);
1285
1286 /*
1287 * Initialize and insert the RAM range (if required).
1288 */
1289 PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
1290 if (!fRamExists)
1291 {
1292 pRamNew->GCPhys = GCPhys;
1293 pRamNew->GCPhysLast = GCPhysLast;
1294 pRamNew->pszDesc = pszDesc;
1295 pRamNew->cb = cb;
1296 pRamNew->fFlags = 0;
1297 pRamNew->pvR3 = NULL;
1298
1299 PPGMPAGE pPage = &pRamNew->aPages[0];
1300 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
1301 {
1302 PGM_PAGE_INIT(pPage,
1303 pReq->aPages[iPage].HCPhysGCPhys,
1304 pReq->aPages[iPage].idPage,
1305 PGMPAGETYPE_ROM,
1306 PGM_PAGE_STATE_ALLOCATED);
1307
1308 pRomPage->Virgin = *pPage;
1309 }
1310
1311 pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
1312 }
1313 else
1314 {
1315 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1316 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
1317 {
1318 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
1319 PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
1320 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1321 PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
1322
1323 pRomPage->Virgin = *pPage;
1324 }
1325
1326 pRamNew = pRam;
1327 }
1328 pgmUnlock(pVM);
1329
1330
1331 /*
1332 * Register the write access handler for the range (PGMROMPROT_READ_ROM_WRITE_IGNORE).
1333 */
1334 rc = PGMR3HandlerPhysicalRegister(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhys, GCPhysLast,
1335#if 0 /** @todo we actually need a ring-3 write handler here for shadowed ROMs, so hack REM! */
1336 pgmR3PhysRomWriteHandler, pRomNew,
1337#else
1338 NULL, NULL,
1339#endif
1340 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
1341 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
1342 if (RT_SUCCESS(rc))
1343 {
1344 pgmLock(pVM);
1345
1346 /*
1347 * Copy the image over to the virgin pages.
1348 * This must be done after linking in the RAM range.
1349 */
1350 PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
1351 for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
1352 {
1353 void *pvDstPage;
1354 PPGMPAGEMAP pMapIgnored;
1355 rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pMapIgnored, &pvDstPage);
1356 if (RT_FAILURE(rc))
1357 {
1358 VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
1359 break;
1360 }
1361 memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
1362 }
1363 if (RT_SUCCESS(rc))
1364 {
1365 /*
1366 * Initialize the ROM range.
1367 * Note that the Virgin member of the pages has already been initialized above.
1368 */
1369 pRomNew->GCPhys = GCPhys;
1370 pRomNew->GCPhysLast = GCPhysLast;
1371 pRomNew->cb = cb;
1372 pRomNew->fFlags = fFlags;
1373 pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAG_PERMANENT_BINARY ? pvBinary : NULL;
1374 pRomNew->pszDesc = pszDesc;
1375
1376 for (unsigned iPage = 0; iPage < cPages; iPage++)
1377 {
1378 PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
1379 pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
1380 PGM_PAGE_INIT_ZERO_REAL(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
1381 }
1382
1383 /*
1384 * Insert the ROM range, tell REM and return successfully.
1385 */
1386 pRomNew->pNextR3 = pRom;
1387 pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
1388 pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
1389
1390 if (pRomPrev)
1391 {
1392 pRomPrev->pNextR3 = pRomNew;
1393 pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
1394 pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
1395 }
1396 else
1397 {
1398 pVM->pgm.s.pRomRangesR3 = pRomNew;
1399 pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
1400 pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
1401 }
1402
1403 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false); /** @todo fix shadowing and REM. */
1404
1405 GMMR3AllocatePagesCleanup(pReq);
1406 pgmUnlock(pVM);
1407 return VINF_SUCCESS;
1408 }
1409
1410 /* bail out */
1411
1412 pgmUnlock(pVM);
1413 int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1414 AssertRC(rc2);
1415 pgmLock(pVM);
1416 }
1417
1418 pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
1419 if (pRamNew)
1420 MMHyperFree(pVM, pRamNew);
1421 }
1422 MMHyperFree(pVM, pRomNew);
1423 }
1424
1425 /** @todo Purge the mapping cache or something... */
1426 GMMR3FreeAllocatedPages(pVM, pReq);
1427 GMMR3AllocatePagesCleanup(pReq);
1428 pgmUnlock(pVM);
1429 return rc;
1430}
1431
1432
1433/**
1434 * \#PF Handler callback for ROM write accesses.
1435 *
1436 * @returns VINF_SUCCESS if the handler have carried out the operation.
1437 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1438 * @param pVM VM Handle.
1439 * @param GCPhys The physical address the guest is writing to.
1440 * @param pvPhys The HC mapping of that address.
1441 * @param pvBuf What the guest is reading/writing.
1442 * @param cbBuf How much it's reading/writing.
1443 * @param enmAccessType The access type.
1444 * @param pvUser User argument.
1445 */
1446/*static - shut up warning */
1447 DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1448{
1449 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
1450 const uint32_t iPage = GCPhys - pRom->GCPhys;
1451 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
1452 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
1453 switch (pRomPage->enmProt)
1454 {
1455 /*
1456 * Ignore.
1457 */
1458 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
1459 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
1460 return VINF_SUCCESS;
1461
1462 /*
1463 * Write to the ram page.
1464 */
1465 case PGMROMPROT_READ_ROM_WRITE_RAM:
1466 case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
1467 {
1468 /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
1469 Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
1470
1471 /*
1472 * Take the lock, do lazy allocation, map the page and copy the data.
1473 *
1474 * Note that we have to bypass the mapping TLB since it works on
1475 * guest physical addresses and entering the shadow page would
1476 * kind of screw things up...
1477 */
1478 int rc = pgmLock(pVM);
1479 AssertRC(rc);
1480
1481 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pRomPage->Shadow) != PGM_PAGE_STATE_ALLOCATED))
1482 {
1483 rc = pgmPhysPageMakeWritable(pVM, &pRomPage->Shadow, GCPhys);
1484 if (RT_FAILURE(rc))
1485 {
1486 pgmUnlock(pVM);
1487 return rc;
1488 }
1489 }
1490
1491 void *pvDstPage;
1492 PPGMPAGEMAP pMapIgnored;
1493 rc = pgmPhysPageMap(pVM, &pRomPage->Shadow, GCPhys & X86_PTE_PG_MASK, &pMapIgnored, &pvDstPage);
1494 if (RT_SUCCESS(rc))
1495 memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
1496
1497 pgmUnlock(pVM);
1498 return rc;
1499 }
1500
1501 default:
1502 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
1503 pRom->aPages[iPage].enmProt, iPage, GCPhys),
1504 VERR_INTERNAL_ERROR);
1505 }
1506}
1507
1508
1509/**
1510 * Called by PGMR3Reset to reset the shadow, switch to the virgin,
1511 * and verify that the virgin part is untouched.
1512 *
1513 * This is done after the normal memory has been cleared.
1514 *
1515 * ASSUMES that the caller owns the PGM lock.
1516 *
1517 * @param pVM The VM handle.
1518 */
1519int pgmR3PhysRomReset(PVM pVM)
1520{
1521 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
1522 {
1523 const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
1524
1525 if (pRom->fFlags & PGMPHYS_ROM_FLAG_SHADOWED)
1526 {
1527 /*
1528 * Reset the physical handler.
1529 */
1530 int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
1531 AssertRCReturn(rc, rc);
1532
1533 /*
1534 * What we do with the shadow pages depends on the memory
1535 * preallocation option. If not enabled, we'll just throw
1536 * out all the dirty pages and replace them by the zero page.
1537 */
1538 if (1)///@todo !pVM->pgm.f.fRamPreAlloc)
1539 {
1540 /* Count dirty shadow pages. */
1541 uint32_t cDirty = 0;
1542 uint32_t iPage = cPages;
1543 while (iPage-- > 0)
1544 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1545 cDirty++;
1546 if (cDirty)
1547 {
1548 /* Free the dirty pages. */
1549 PGMMFREEPAGESREQ pReq;
1550 rc = GMMR3FreePagesPrepare(pVM, &pReq, cDirty, GMMACCOUNT_BASE);
1551 AssertRCReturn(rc, rc);
1552
1553 uint32_t iReqPage = 0;
1554 for (iPage = 0; iPage < cPages; iPage++)
1555 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1556 {
1557 pReq->aPages[iReqPage].idPage = PGM_PAGE_GET_PAGEID(&pRom->aPages[iPage].Shadow);
1558 iReqPage++;
1559 }
1560
1561 rc = GMMR3FreePagesPerform(pVM, pReq);
1562 GMMR3FreePagesCleanup(pReq);
1563 AssertRCReturn(rc, rc);
1564
1565 /* setup the zero page. */
1566 for (iPage = 0; iPage < cPages; iPage++)
1567 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1568 PGM_PAGE_INIT_ZERO_REAL(&pRom->aPages[iPage].Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
1569 }
1570 }
1571 else
1572 {
1573 /* clear all the pages. */
1574 for (uint32_t iPage = 0; iPage < cPages; iPage++)
1575 {
1576 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
1577 rc = pgmPhysPageMakeWritable(pVM, &pRom->aPages[iPage].Shadow, GCPhys);
1578 if (RT_FAILURE(rc))
1579 break;
1580
1581 void *pvDstPage;
1582 PPGMPAGEMAP pMapIgnored;
1583 rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pMapIgnored, &pvDstPage);
1584 if (RT_FAILURE(rc))
1585 break;
1586 ASMMemZeroPage(pvDstPage);
1587 }
1588 AssertRCReturn(rc, rc);
1589 }
1590 }
1591
1592#ifdef VBOX_STRICT
1593 /*
1594 * Verify that the virgin page is unchanged if possible.
1595 */
1596 if (pRom->pvOriginal)
1597 {
1598 uint8_t const *pbSrcPage = (uint8_t const *)pRom->pvOriginal;
1599 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
1600 {
1601 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
1602 PPGMPAGEMAP pMapIgnored;
1603 void *pvDstPage;
1604 int rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pMapIgnored, &pvDstPage);
1605 if (RT_FAILURE(rc))
1606 break;
1607 if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
1608 LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
1609 GCPhys, pRom->pszDesc));
1610 }
1611 }
1612#endif
1613 }
1614
1615 return VINF_SUCCESS;
1616}
1617
1618
1619/**
1620 * Change the shadowing of a range of ROM pages.
1621 *
1622 * This is intended for implementing chipset specific memory registers
1623 * and will not be very strict about the input. It will silently ignore
1624 * any pages that are not the part of a shadowed ROM.
1625 *
1626 * @returns VBox status code.
1627 * @param pVM Pointer to the shared VM structure.
1628 * @param GCPhys Where to start. Page aligned.
1629 * @param cb How much to change. Page aligned.
1630 * @param enmProt The new ROM protection.
1631 */
1632VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
1633{
1634 /*
1635 * Check input
1636 */
1637 if (!cb)
1638 return VINF_SUCCESS;
1639 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1640 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1641 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1642 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1643 AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
1644
1645 /*
1646 * Process the request.
1647 */
1648 bool fFlushedPool = false;
1649 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
1650 if ( GCPhys <= pRom->GCPhysLast
1651 && GCPhysLast >= pRom->GCPhys)
1652 {
1653 /*
1654 * Iterate the relevant pages and the ncessary make changes.
1655 */
1656 bool fChanges = false;
1657 uint32_t const cPages = pRom->GCPhysLast > GCPhysLast
1658 ? pRom->cb >> PAGE_SHIFT
1659 : (GCPhysLast - pRom->GCPhys) >> PAGE_SHIFT;
1660 for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
1661 iPage < cPages;
1662 iPage++)
1663 {
1664 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
1665 if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
1666 {
1667 fChanges = true;
1668
1669 /* flush the page pool first so we don't leave any usage references dangling. */
1670 if (!fFlushedPool)
1671 {
1672 pgmPoolFlushAll(pVM);
1673 fFlushedPool = true;
1674 }
1675
1676 PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
1677 PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
1678 PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
1679
1680 *pOld = *pRamPage;
1681 *pRamPage = *pNew;
1682 /** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
1683 }
1684 }
1685
1686 /*
1687 * Reset the access handler if we made changes, no need
1688 * to optimize this.
1689 */
1690 if (fChanges)
1691 {
1692 int rc = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
1693 AssertRCReturn(rc, rc);
1694 }
1695
1696 /* Advance - cb isn't updated. */
1697 GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
1698 }
1699
1700 return VINF_SUCCESS;
1701}
1702
1703#ifndef VBOX_WITH_NEW_PHYS_CODE
1704
1705/**
1706 * Interface that the MMR3RamRegister(), MMR3RomRegister() and MMIO handler
1707 * registration APIs calls to inform PGM about memory registrations.
1708 *
1709 * It registers the physical memory range with PGM. MM is responsible
1710 * for the toplevel things - allocation and locking - while PGM is taking
1711 * care of all the details and implements the physical address space virtualization.
1712 *
1713 * @returns VBox status.
1714 * @param pVM The VM handle.
1715 * @param pvRam HC virtual address of the RAM range. (page aligned)
1716 * @param GCPhys GC physical address of the RAM range. (page aligned)
1717 * @param cb Size of the RAM range. (page aligned)
1718 * @param fFlags Flags, MM_RAM_*.
1719 * @param paPages Pointer an array of physical page descriptors.
1720 * @param pszDesc Description string.
1721 */
1722VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc)
1723{
1724 /*
1725 * Validate input.
1726 * (Not so important because callers are only MMR3PhysRegister()
1727 * and PGMR3HandlerPhysicalRegisterEx(), but anyway...)
1728 */
1729 Log(("PGMR3PhysRegister %08X %x bytes flags %x %s\n", GCPhys, cb, fFlags, pszDesc));
1730
1731 Assert((fFlags & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_DYNAMIC_ALLOC)) || paPages);
1732 /*Assert(!(fFlags & MM_RAM_FLAGS_RESERVED) || !paPages);*/
1733 Assert((fFlags == (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO)) || (fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) || pvRam);
1734 /*Assert(!(fFlags & MM_RAM_FLAGS_RESERVED) || !pvRam);*/
1735 Assert(!(fFlags & ~0xfff));
1736 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
1737 Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
1738 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2 | MM_RAM_FLAGS_DYNAMIC_ALLOC)));
1739 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
1740 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1741 if (GCPhysLast < GCPhys)
1742 {
1743 AssertMsgFailed(("The range wraps! GCPhys=%RGp cb=%#x\n", GCPhys, cb));
1744 return VERR_INVALID_PARAMETER;
1745 }
1746
1747 /*
1748 * Find range location and check for conflicts.
1749 */
1750 PPGMRAMRANGE pPrev = NULL;
1751 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
1752 while (pCur)
1753 {
1754 if (GCPhys <= pCur->GCPhysLast && GCPhysLast >= pCur->GCPhys)
1755 {
1756 AssertMsgFailed(("Conflict! This cannot happen!\n"));
1757 return VERR_PGM_RAM_CONFLICT;
1758 }
1759 if (GCPhysLast < pCur->GCPhys)
1760 break;
1761
1762 /* next */
1763 pPrev = pCur;
1764 pCur = pCur->pNextR3;
1765 }
1766
1767 /*
1768 * Allocate RAM range.
1769 * Small ranges are allocated from the heap, big ones have separate mappings.
1770 */
1771 size_t cbRam = RT_OFFSETOF(PGMRAMRANGE, aPages[cb >> PAGE_SHIFT]);
1772 PPGMRAMRANGE pNew;
1773 int rc = VERR_NO_MEMORY;
1774 if (cbRam > PAGE_SIZE / 2)
1775 { /* large */
1776 cbRam = RT_ALIGN_Z(cbRam, PAGE_SIZE);
1777 rc = MMR3HyperAllocOnceNoRel(pVM, cbRam, PAGE_SIZE, MM_TAG_PGM_PHYS, (void **)&pNew);
1778 AssertMsgRC(rc, ("MMR3HyperAllocOnceNoRel(,%#x,,) -> %Rrc\n", cbRam, rc));
1779 }
1780 else
1781 { /* small */
1782 rc = MMHyperAlloc(pVM, cbRam, 16, MM_TAG_PGM, (void **)&pNew);
1783 AssertMsgRC(rc, ("MMHyperAlloc(,%#x,,,) -> %Rrc\n", cbRam, rc));
1784 }
1785 if (RT_SUCCESS(rc))
1786 {
1787 /*
1788 * Initialize the range.
1789 */
1790 pNew->pvR3 = pvRam;
1791 pNew->GCPhys = GCPhys;
1792 pNew->GCPhysLast = GCPhysLast;
1793 pNew->cb = cb;
1794 pNew->fFlags = fFlags;
1795 pNew->paChunkR3Ptrs = NULL;
1796
1797 unsigned iPage = (unsigned)(cb >> PAGE_SHIFT);
1798 if (paPages)
1799 {
1800 while (iPage-- > 0)
1801 {
1802 PGM_PAGE_INIT(&pNew->aPages[iPage], paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
1803 fFlags & MM_RAM_FLAGS_MMIO2 ? PGMPAGETYPE_MMIO2 : PGMPAGETYPE_RAM,
1804 PGM_PAGE_STATE_ALLOCATED);
1805 pNew->aPages[iPage].HCPhys |= fFlags; /** @todo PAGE FLAGS*/
1806 }
1807 }
1808 else if (fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1809 {
1810 /* Allocate memory for chunk to HC ptr lookup array. */
1811 rc = MMHyperAlloc(pVM, (cb >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(void *), 16, MM_TAG_PGM, (void **)&pNew->paChunkR3Ptrs);
1812 AssertMsgReturn(rc == VINF_SUCCESS, ("MMHyperAlloc(,%#x,,,) -> %Rrc\n", cbRam, cb), rc);
1813
1814 /* Physical memory will be allocated on demand. */
1815 while (iPage-- > 0)
1816 {
1817 PGM_PAGE_INIT(&pNew->aPages[iPage], 0, NIL_GMM_PAGEID, PGMPAGETYPE_RAM, PGM_PAGE_STATE_ZERO);
1818 pNew->aPages[iPage].HCPhys = fFlags; /** @todo PAGE FLAGS */
1819 }
1820 }
1821 else
1822 {
1823 Assert(fFlags == (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO));
1824 RTHCPHYS HCPhysDummyPage = MMR3PageDummyHCPhys(pVM);
1825 while (iPage-- > 0)
1826 {
1827 PGM_PAGE_INIT(&pNew->aPages[iPage], HCPhysDummyPage, NIL_GMM_PAGEID, PGMPAGETYPE_MMIO, PGM_PAGE_STATE_ZERO);
1828 pNew->aPages[iPage].HCPhys |= fFlags; /** @todo PAGE FLAGS*/
1829 }
1830 }
1831
1832 /*
1833 * Insert the new RAM range.
1834 */
1835 pgmLock(pVM);
1836 pNew->pNextR3 = pCur;
1837 pNew->pNextR0 = pCur ? MMHyperCCToR0(pVM, pCur) : NIL_RTR0PTR;
1838 pNew->pNextRC = pCur ? MMHyperCCToRC(pVM, pCur) : NIL_RTRCPTR;
1839 if (pPrev)
1840 {
1841 pPrev->pNextR3 = pNew;
1842 pPrev->pNextR0 = MMHyperCCToR0(pVM, pNew);
1843 pPrev->pNextRC = MMHyperCCToRC(pVM, pNew);
1844 }
1845 else
1846 {
1847 pVM->pgm.s.pRamRangesR3 = pNew;
1848 pVM->pgm.s.pRamRangesR0 = MMHyperCCToR0(pVM, pNew);
1849 pVM->pgm.s.pRamRangesRC = MMHyperCCToRC(pVM, pNew);
1850 }
1851 pgmUnlock(pVM);
1852 }
1853 return rc;
1854}
1855
1856
1857/**
1858 * Register a chunk of a the physical memory range with PGM. MM is responsible
1859 * for the toplevel things - allocation and locking - while PGM is taking
1860 * care of all the details and implements the physical address space virtualization.
1861 *
1862 *
1863 * @returns VBox status.
1864 * @param pVM The VM handle.
1865 * @param pvRam HC virtual address of the RAM range. (page aligned)
1866 * @param GCPhys GC physical address of the RAM range. (page aligned)
1867 * @param cb Size of the RAM range. (page aligned)
1868 * @param fFlags Flags, MM_RAM_*.
1869 * @param paPages Pointer an array of physical page descriptors.
1870 * @param pszDesc Description string.
1871 */
1872VMMR3DECL(int) PGMR3PhysRegisterChunk(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc)
1873{
1874 NOREF(pszDesc);
1875
1876 /*
1877 * Validate input.
1878 * (Not so important because callers are only MMR3PhysRegister()
1879 * and PGMR3HandlerPhysicalRegisterEx(), but anyway...)
1880 */
1881 Log(("PGMR3PhysRegisterChunk %08X %x bytes flags %x %s\n", GCPhys, cb, fFlags, pszDesc));
1882
1883 Assert(paPages);
1884 Assert(pvRam);
1885 Assert(!(fFlags & ~0xfff));
1886 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
1887 Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
1888 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2 | MM_RAM_FLAGS_DYNAMIC_ALLOC)));
1889 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
1890 Assert(VM_IS_EMT(pVM));
1891 Assert(!(GCPhys & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
1892 Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
1893
1894 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1895 if (GCPhysLast < GCPhys)
1896 {
1897 AssertMsgFailed(("The range wraps! GCPhys=%RGp cb=%#x\n", GCPhys, cb));
1898 return VERR_INVALID_PARAMETER;
1899 }
1900
1901 /*
1902 * Find existing range location.
1903 */
1904 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1905 while (pRam)
1906 {
1907 RTGCPHYS off = GCPhys - pRam->GCPhys;
1908 if ( off < pRam->cb
1909 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
1910 break;
1911
1912 pRam = pRam->CTX_SUFF(pNext);
1913 }
1914 AssertReturn(pRam, VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS);
1915
1916 unsigned off = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1917 unsigned iPage = (unsigned)(cb >> PAGE_SHIFT);
1918 if (paPages)
1919 {
1920 while (iPage-- > 0)
1921 pRam->aPages[off + iPage].HCPhys = (paPages[iPage].Phys & X86_PTE_PAE_PG_MASK) | fFlags; /** @todo PAGE FLAGS */
1922 }
1923 off >>= (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1924 pRam->paChunkR3Ptrs[off] = (uintptr_t)pvRam;
1925
1926 /* Notify the recompiler. */
1927 REMR3NotifyPhysRamChunkRegister(pVM, GCPhys, PGM_DYNAMIC_CHUNK_SIZE, (RTHCUINTPTR)pvRam, fFlags);
1928
1929 return VINF_SUCCESS;
1930}
1931
1932
1933/**
1934 * Allocate missing physical pages for an existing guest RAM range.
1935 *
1936 * @returns VBox status.
1937 * @param pVM The VM handle.
1938 * @param GCPhys GC physical address of the RAM range. (page aligned)
1939 */
1940VMMR3DECL(int) PGM3PhysGrowRange(PVM pVM, PCRTGCPHYS pGCPhys)
1941{
1942 RTGCPHYS GCPhys = *pGCPhys;
1943
1944 /*
1945 * Walk range list.
1946 */
1947 pgmLock(pVM);
1948
1949 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1950 while (pRam)
1951 {
1952 RTGCPHYS off = GCPhys - pRam->GCPhys;
1953 if ( off < pRam->cb
1954 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
1955 {
1956 bool fRangeExists = false;
1957 unsigned off = (GCPhys - pRam->GCPhys) >> PGM_DYNAMIC_CHUNK_SHIFT;
1958
1959 /* Note: A request made from another thread may end up in EMT after somebody else has already allocated the range. */
1960 if (pRam->paChunkR3Ptrs[off])
1961 fRangeExists = true;
1962
1963 pgmUnlock(pVM);
1964 if (fRangeExists)
1965 return VINF_SUCCESS;
1966 return pgmr3PhysGrowRange(pVM, GCPhys);
1967 }
1968
1969 pRam = pRam->CTX_SUFF(pNext);
1970 }
1971 pgmUnlock(pVM);
1972 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
1973}
1974
1975
1976/**
1977 * Allocate missing physical pages for an existing guest RAM range.
1978 *
1979 * @returns VBox status.
1980 * @param pVM The VM handle.
1981 * @param pRamRange RAM range
1982 * @param GCPhys GC physical address of the RAM range. (page aligned)
1983 */
1984int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys)
1985{
1986 void *pvRam;
1987 int rc;
1988
1989 /* We must execute this function in the EMT thread, otherwise we'll run into problems. */
1990 if (!VM_IS_EMT(pVM))
1991 {
1992 PVMREQ pReq;
1993 const RTGCPHYS GCPhysParam = GCPhys;
1994
1995 AssertMsg(!PDMCritSectIsOwner(&pVM->pgm.s.CritSect), ("We own the PGM lock -> deadlock danger!!\n"));
1996
1997 rc = VMR3ReqCall(pVM, VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT, (PFNRT)PGM3PhysGrowRange, 2, pVM, &GCPhysParam);
1998 if (RT_SUCCESS(rc))
1999 {
2000 rc = pReq->iStatus;
2001 VMR3ReqFree(pReq);
2002 }
2003 return rc;
2004 }
2005
2006 /* Round down to chunk boundary */
2007 GCPhys = GCPhys & PGM_DYNAMIC_CHUNK_BASE_MASK;
2008
2009 STAM_COUNTER_INC(&pVM->pgm.s.StatR3DynRamGrow);
2010 STAM_COUNTER_ADD(&pVM->pgm.s.StatR3DynRamTotal, PGM_DYNAMIC_CHUNK_SIZE/(1024*1024));
2011
2012 Log(("pgmr3PhysGrowRange: allocate chunk of size 0x%X at %RGp\n", PGM_DYNAMIC_CHUNK_SIZE, GCPhys));
2013
2014 unsigned cPages = PGM_DYNAMIC_CHUNK_SIZE >> PAGE_SHIFT;
2015
2016 for (;;)
2017 {
2018 rc = SUPPageAlloc(cPages, &pvRam);
2019 if (RT_SUCCESS(rc))
2020 {
2021
2022 rc = MMR3PhysRegisterEx(pVM, pvRam, GCPhys, PGM_DYNAMIC_CHUNK_SIZE, 0, MM_PHYS_TYPE_DYNALLOC_CHUNK, "Main Memory");
2023 if (RT_SUCCESS(rc))
2024 return rc;
2025
2026 SUPPageFree(pvRam, cPages);
2027 }
2028
2029 VMSTATE enmVMState = VMR3GetState(pVM);
2030 if (enmVMState != VMSTATE_RUNNING)
2031 {
2032 AssertMsgFailed(("Out of memory while trying to allocate a guest RAM chunk at %RGp!\n", GCPhys));
2033 LogRel(("PGM: Out of memory while trying to allocate a guest RAM chunk at %RGp (VMstate=%s)!\n", GCPhys, VMR3GetStateName(enmVMState)));
2034 return rc;
2035 }
2036
2037 LogRel(("pgmr3PhysGrowRange: out of memory. pause until the user resumes execution.\n"));
2038
2039 /* Pause first, then inform Main. */
2040 rc = VMR3SuspendNoSave(pVM);
2041 AssertRC(rc);
2042
2043 VMSetRuntimeError(pVM, false, "HostMemoryLow", "Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM");
2044
2045 /* Wait for resume event; will only return in that case. If the VM is stopped, the EMT thread will be destroyed. */
2046 rc = VMR3WaitForResume(pVM);
2047
2048 /* Retry */
2049 LogRel(("pgmr3PhysGrowRange: VM execution resumed -> retry.\n"));
2050 }
2051}
2052
2053#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2054
2055/**
2056 * Interface MMR3RomRegister() and MMR3PhysReserve calls to update the
2057 * flags of existing RAM ranges.
2058 *
2059 * @returns VBox status.
2060 * @param pVM The VM handle.
2061 * @param GCPhys GC physical address of the RAM range. (page aligned)
2062 * @param cb Size of the RAM range. (page aligned)
2063 * @param fFlags The Or flags, MM_RAM_* \#defines.
2064 * @param fMask The and mask for the flags.
2065 */
2066VMMR3DECL(int) PGMR3PhysSetFlags(PVM pVM, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, unsigned fMask)
2067{
2068 Log(("PGMR3PhysSetFlags %08X %x %x %x\n", GCPhys, cb, fFlags, fMask));
2069
2070 /*
2071 * Validate input.
2072 * (Not so important because caller is always MMR3RomRegister() and MMR3PhysReserve(), but anyway...)
2073 */
2074 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2)));
2075 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
2076 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2077 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2078 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2079
2080 /*
2081 * Lookup the range.
2082 */
2083 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2084 while (pRam && GCPhys > pRam->GCPhysLast)
2085 pRam = pRam->CTX_SUFF(pNext);
2086 if ( !pRam
2087 || GCPhys > pRam->GCPhysLast
2088 || GCPhysLast < pRam->GCPhys)
2089 {
2090 AssertMsgFailed(("No RAM range for %RGp-%RGp\n", GCPhys, GCPhysLast));
2091 return VERR_INVALID_PARAMETER;
2092 }
2093
2094 /*
2095 * Update the requested flags.
2096 */
2097 RTHCPHYS fFullMask = ~(RTHCPHYS)(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2)
2098 | fMask;
2099 unsigned iPageEnd = (GCPhysLast - pRam->GCPhys + 1) >> PAGE_SHIFT;
2100 unsigned iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2101 for ( ; iPage < iPageEnd; iPage++)
2102 pRam->aPages[iPage].HCPhys = (pRam->aPages[iPage].HCPhys & fFullMask) | fFlags; /** @todo PAGE FLAGS */
2103
2104 return VINF_SUCCESS;
2105}
2106
2107
2108/**
2109 * Sets the Address Gate 20 state.
2110 *
2111 * @param pVM VM handle.
2112 * @param fEnable True if the gate should be enabled.
2113 * False if the gate should be disabled.
2114 */
2115VMMDECL(void) PGMR3PhysSetA20(PVM pVM, bool fEnable)
2116{
2117 LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVM->pgm.s.fA20Enabled));
2118 if (pVM->pgm.s.fA20Enabled != (RTUINT)fEnable)
2119 {
2120 pVM->pgm.s.fA20Enabled = fEnable;
2121 pVM->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2122 REMR3A20Set(pVM, fEnable);
2123 /** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2124 }
2125}
2126
2127
2128/**
2129 * Tree enumeration callback for dealing with age rollover.
2130 * It will perform a simple compression of the current age.
2131 */
2132static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2133{
2134 /* Age compression - ASSUMES iNow == 4. */
2135 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2136 if (pChunk->iAge >= UINT32_C(0xffffff00))
2137 pChunk->iAge = 3;
2138 else if (pChunk->iAge >= UINT32_C(0xfffff000))
2139 pChunk->iAge = 2;
2140 else if (pChunk->iAge)
2141 pChunk->iAge = 1;
2142 else /* iAge = 0 */
2143 pChunk->iAge = 4;
2144
2145 /* reinsert */
2146 PVM pVM = (PVM)pvUser;
2147 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2148 pChunk->AgeCore.Key = pChunk->iAge;
2149 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2150 return 0;
2151}
2152
2153
2154/**
2155 * Tree enumeration callback that updates the chunks that have
2156 * been used since the last
2157 */
2158static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
2159{
2160 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2161 if (!pChunk->iAge)
2162 {
2163 PVM pVM = (PVM)pvUser;
2164 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2165 pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
2166 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2167 }
2168
2169 return 0;
2170}
2171
2172
2173/**
2174 * Performs ageing of the ring-3 chunk mappings.
2175 *
2176 * @param pVM The VM handle.
2177 */
2178VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
2179{
2180 pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
2181 pVM->pgm.s.ChunkR3Map.iNow++;
2182 if (pVM->pgm.s.ChunkR3Map.iNow == 0)
2183 {
2184 pVM->pgm.s.ChunkR3Map.iNow = 4;
2185 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
2186 }
2187 else
2188 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingCallback, pVM);
2189}
2190
2191
2192/**
2193 * The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
2194 */
2195typedef struct PGMR3PHYSCHUNKUNMAPCB
2196{
2197 PVM pVM; /**< The VM handle. */
2198 PPGMCHUNKR3MAP pChunk; /**< The chunk to unmap. */
2199} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
2200
2201
2202/**
2203 * Callback used to find the mapping that's been unused for
2204 * the longest time.
2205 */
2206static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
2207{
2208 do
2209 {
2210 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
2211 if ( pChunk->iAge
2212 && !pChunk->cRefs)
2213 {
2214 /*
2215 * Check that it's not in any of the TLBs.
2216 */
2217 PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
2218 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2219 if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
2220 {
2221 pChunk = NULL;
2222 break;
2223 }
2224 if (pChunk)
2225 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
2226 if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
2227 {
2228 pChunk = NULL;
2229 break;
2230 }
2231 if (pChunk)
2232 {
2233 ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
2234 return 1; /* done */
2235 }
2236 }
2237
2238 /* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
2239 pNode = pNode->pList;
2240 } while (pNode);
2241 return 0;
2242}
2243
2244
2245/**
2246 * Finds a good candidate for unmapping when the ring-3 mapping cache is full.
2247 *
2248 * The candidate will not be part of any TLBs, so no need to flush
2249 * anything afterwards.
2250 *
2251 * @returns Chunk id.
2252 * @param pVM The VM handle.
2253 */
2254static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
2255{
2256 /*
2257 * Do tree ageing first?
2258 */
2259 if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
2260 PGMR3PhysChunkAgeing(pVM);
2261
2262 /*
2263 * Enumerate the age tree starting with the left most node.
2264 */
2265 PGMR3PHYSCHUNKUNMAPCB Args;
2266 Args.pVM = pVM;
2267 Args.pChunk = NULL;
2268 if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /*fFromLeft*/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
2269 return Args.pChunk->Core.Key;
2270 return INT32_MAX;
2271}
2272
2273
2274/**
2275 * Maps the given chunk into the ring-3 mapping cache.
2276 *
2277 * This will call ring-0.
2278 *
2279 * @returns VBox status code.
2280 * @param pVM The VM handle.
2281 * @param idChunk The chunk in question.
2282 * @param ppChunk Where to store the chunk tracking structure.
2283 *
2284 * @remarks Called from within the PGM critical section.
2285 */
2286int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
2287{
2288 int rc;
2289 /*
2290 * Allocate a new tracking structure first.
2291 */
2292#if 0 /* for later when we've got a separate mapping method for ring-0. */
2293 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
2294 AssertReturn(pChunk, VERR_NO_MEMORY);
2295#else
2296 PPGMCHUNKR3MAP pChunk;
2297 rc = MMHyperAlloc(pVM, sizeof(*pChunk), 0, MM_TAG_PGM_CHUNK_MAPPING, (void **)&pChunk);
2298 AssertRCReturn(rc, rc);
2299#endif
2300 pChunk->Core.Key = idChunk;
2301 pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
2302 pChunk->iAge = 0;
2303 pChunk->cRefs = 0;
2304 pChunk->cPermRefs = 0;
2305 pChunk->pv = NULL;
2306
2307 /*
2308 * Request the ring-0 part to map the chunk in question and if
2309 * necessary unmap another one to make space in the mapping cache.
2310 */
2311 GMMMAPUNMAPCHUNKREQ Req;
2312 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2313 Req.Hdr.cbReq = sizeof(Req);
2314 Req.pvR3 = NULL;
2315 Req.idChunkMap = idChunk;
2316 Req.idChunkUnmap = INT32_MAX;
2317 if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
2318 Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
2319 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
2320 if (RT_SUCCESS(rc))
2321 {
2322 /*
2323 * Update the tree.
2324 */
2325 /* insert the new one. */
2326 AssertPtr(Req.pvR3);
2327 pChunk->pv = Req.pvR3;
2328 bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
2329 AssertRelease(fRc);
2330 pVM->pgm.s.ChunkR3Map.c++;
2331
2332 fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2333 AssertRelease(fRc);
2334
2335 /* remove the unmapped one. */
2336 if (Req.idChunkUnmap != INT32_MAX)
2337 {
2338 PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
2339 AssertRelease(pUnmappedChunk);
2340 pUnmappedChunk->pv = NULL;
2341 pUnmappedChunk->Core.Key = UINT32_MAX;
2342#if 0 /* for later when we've got a separate mapping method for ring-0. */
2343 MMR3HeapFree(pUnmappedChunk);
2344#else
2345 MMHyperFree(pVM, pUnmappedChunk);
2346#endif
2347 pVM->pgm.s.ChunkR3Map.c--;
2348 }
2349 }
2350 else
2351 {
2352 AssertRC(rc);
2353#if 0 /* for later when we've got a separate mapping method for ring-0. */
2354 MMR3HeapFree(pChunk);
2355#else
2356 MMHyperFree(pVM, pChunk);
2357#endif
2358 pChunk = NULL;
2359 }
2360
2361 *ppChunk = pChunk;
2362 return rc;
2363}
2364
2365
2366/**
2367 * For VMMCALLHOST_PGM_MAP_CHUNK, considered internal.
2368 *
2369 * @returns see pgmR3PhysChunkMap.
2370 * @param pVM The VM handle.
2371 * @param idChunk The chunk to map.
2372 */
2373VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
2374{
2375 PPGMCHUNKR3MAP pChunk;
2376 return pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
2377}
2378
2379
2380/**
2381 * Invalidates the TLB for the ring-3 mapping cache.
2382 *
2383 * @param pVM The VM handle.
2384 */
2385VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
2386{
2387 pgmLock(pVM);
2388 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2389 {
2390 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
2391 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
2392 }
2393 pgmUnlock(pVM);
2394}
2395
2396
2397/**
2398 * Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES.
2399 *
2400 * @returns The following VBox status codes.
2401 * @retval VINF_SUCCESS on success. FF cleared.
2402 * @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in this case.
2403 *
2404 * @param pVM The VM handle.
2405 */
2406VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
2407{
2408 pgmLock(pVM);
2409 int rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
2410 if (rc == VERR_GMM_SEED_ME)
2411 {
2412 void *pvChunk;
2413 rc = SUPPageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
2414 if (RT_SUCCESS(rc))
2415 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
2416 if (RT_FAILURE(rc))
2417 {
2418 LogRel(("PGM: GMM Seeding failed, rc=%Rrc\n", rc));
2419 rc = VINF_EM_NO_MEMORY;
2420 }
2421 }
2422 pgmUnlock(pVM);
2423 Assert(rc == VINF_SUCCESS || rc == VINF_EM_NO_MEMORY);
2424 return rc;
2425}
2426
2427
2428/**
2429 * Converts a GC physical address to a HC ring-3 pointer, with some
2430 * additional checks.
2431 *
2432 * @returns VBox status code.
2433 * @retval VINF_SUCCESS on success.
2434 * @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *pvPtr set if the page has a write
2435 * access handler of some kind.
2436 * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
2437 * accesses or is odd in any way.
2438 * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
2439 *
2440 * @param pVM The VM handle.
2441 * @param GCPhys The GC physical address to convert.
2442 * @param fWritable Whether write access is required.
2443 * @param pR3Ptr Where to store the R3 pointer on success.
2444 */
2445VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **pvPtr)
2446{
2447 pgmLock(pVM);
2448
2449 PPGMRAMRANGE pRam;
2450 PPGMPAGE pPage;
2451 int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
2452 if (RT_SUCCESS(rc))
2453 {
2454#if 0 /** @todo ifndef PGM_IGNORE_RAM_FLAGS_RESERVED */
2455 if (RT_UNLIKELY(PGM_PAGE_IS_RESERVED(pPage)))
2456 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
2457#endif
2458 {
2459#if 0 /** @todo looks like the system ROM is registered incorrectly, 0xfe000 claims to be a zero page. */
2460 if (fWritable && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2461 rc = VERR_PGM_PHYS_TLB_UNASSIGNED; /** @todo VBOX_WITH_NEW_PHYS_CODE: remap it to a writeable page. */
2462#else
2463 if (0)
2464 /* nothing */;
2465#endif
2466 else if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
2467 {
2468 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
2469 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
2470 else if (fWritable && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2471 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
2472 else
2473 {
2474 /* Temporariliy disabled phycial handler(s), since the recompiler
2475 doesn't get notified when it's reset we'll have to pretend its
2476 operating normally. */
2477 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
2478 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
2479 else
2480 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
2481 }
2482 }
2483 else
2484 rc = VINF_SUCCESS;
2485 if (RT_SUCCESS(rc))
2486 {
2487 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2488 {
2489 AssertMsg(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM, ("GCPhys=%RGp type=%d\n", GCPhys, PGM_PAGE_GET_TYPE(pPage)));
2490 RTGCPHYS off = GCPhys - pRam->GCPhys;
2491 unsigned iChunk = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
2492 *pvPtr = (void *)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2493 }
2494 else if (RT_LIKELY(pRam->pvR3))
2495 {
2496 AssertMsg(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2, ("GCPhys=%RGp type=%d\n", GCPhys, PGM_PAGE_GET_TYPE(pPage)));
2497 RTGCPHYS off = GCPhys - pRam->GCPhys;
2498 *pvPtr = (uint8_t *)pRam->pvR3 + off;
2499 }
2500 else
2501 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
2502 }
2503 }
2504 }
2505 else
2506 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
2507
2508 pgmUnlock(pVM);
2509 return rc;
2510}
2511
2512
2513
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette