VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 17510

Last change on this file since 17510 was 17510, checked in by vboxsync, 16 years ago

PGM,EM,PDMDevHlp: Added PGMPhysInterpretedReadNoHandlers and PGMPhysInterpretedWriteNoHandlers for EM, and PGMR3PhysReadExternal and PGMR3PhysWriteExternal for PDMDevHlp. The former because PGMPhysRead/Write aren't the right APIs there (enforced now), and the latter because we have to make sure non-EMTs doesn't execute handlers or allocate pages.
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File size: 105.6 KB
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1/* $Id: PGMPhys.cpp 17510 2009-03-07 03:54:02Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM
27#include <VBox/pgm.h>
28#include <VBox/cpum.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/rem.h>
34#include <VBox/csam.h>
35#include "PGMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/dbg.h>
38#include <VBox/param.h>
39#include <VBox/err.h>
40#include <iprt/assert.h>
41#include <iprt/alloc.h>
42#include <iprt/asm.h>
43#include <VBox/log.h>
44#include <iprt/thread.h>
45#include <iprt/string.h>
46
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51/** The number of pages to free in one batch. */
52#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
53
54
55/*******************************************************************************
56* Internal Functions *
57*******************************************************************************/
58static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
59static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
60
61
62/*
63 * PGMR3PhysReadU8-64
64 * PGMR3PhysWriteU8-64
65 */
66#define PGMPHYSFN_READNAME PGMR3PhysReadU8
67#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
68#define PGMPHYS_DATASIZE 1
69#define PGMPHYS_DATATYPE uint8_t
70#include "PGMPhysRWTmpl.h"
71
72#define PGMPHYSFN_READNAME PGMR3PhysReadU16
73#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
74#define PGMPHYS_DATASIZE 2
75#define PGMPHYS_DATATYPE uint16_t
76#include "PGMPhysRWTmpl.h"
77
78#define PGMPHYSFN_READNAME PGMR3PhysReadU32
79#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
80#define PGMPHYS_DATASIZE 4
81#define PGMPHYS_DATATYPE uint32_t
82#include "PGMPhysRWTmpl.h"
83
84#define PGMPHYSFN_READNAME PGMR3PhysReadU64
85#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
86#define PGMPHYS_DATASIZE 8
87#define PGMPHYS_DATATYPE uint64_t
88#include "PGMPhysRWTmpl.h"
89
90
91/**
92 * EMT worker for PGMR3PhysReadExternal.
93 */
94static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
95{
96 PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
97 return VINF_SUCCESS;
98}
99
100
101/**
102 * Write to physical memory, external users.
103 *
104 * @returns VBox status code.
105 * @retval VINF_SUCCESS.
106 *
107 * @param pVM VM Handle.
108 * @param GCPhys Physical address to write to.
109 * @param pvBuf What to write.
110 * @param cbWrite How many bytes to write.
111 *
112 * @thread Any but EMTs.
113 */
114VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
115{
116 VM_ASSERT_OTHER_THREAD(pVM);
117
118 AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
119 LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
120
121 pgmLock(pVM);
122
123 /*
124 * Copy loop on ram ranges.
125 */
126 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
127 for (;;)
128 {
129 /* Find range. */
130 while (pRam && GCPhys > pRam->GCPhysLast)
131 pRam = pRam->CTX_SUFF(pNext);
132 /* Inside range or not? */
133 if (pRam && GCPhys >= pRam->GCPhys)
134 {
135 /*
136 * Must work our way thru this page by page.
137 */
138 RTGCPHYS off = GCPhys - pRam->GCPhys;
139 while (off < pRam->cb)
140 {
141 unsigned iPage = off >> PAGE_SHIFT;
142 PPGMPAGE pPage = &pRam->aPages[iPage];
143
144 /*
145 * If the page has an ALL access handler, we'll have to
146 * delegate the job to EMT.
147 */
148 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
149 {
150 pgmUnlock(pVM);
151
152 PVMREQ pReq = NULL;
153 int rc = VMR3ReqCall(pVM, VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT,
154 (PFNRT)pgmR3PhysReadExternalEMT, 4, pVM, &GCPhys, pvBuf, cbRead);
155 if (RT_SUCCESS(rc))
156 {
157 rc = pReq->iStatus;
158 VMR3ReqFree(pReq);
159 }
160 return rc;
161 }
162 Assert(!PGM_PAGE_IS_MMIO(pPage));
163
164 /*
165 * Simple stuff, go ahead.
166 */
167 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
168 if (cb > cbRead)
169 cb = cbRead;
170 const void *pvSrc;
171 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
172 if (RT_SUCCESS(rc))
173 memcpy(pvBuf, pvSrc, cb);
174 else
175 {
176 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
177 pRam->GCPhys + off, pPage, rc));
178 memset(pvBuf, 0xff, cb);
179 }
180
181 /* next page */
182 if (cb >= cbRead)
183 {
184 pgmUnlock(pVM);
185 return VINF_SUCCESS;
186 }
187 cbRead -= cb;
188 off += cb;
189 GCPhys += cb;
190 pvBuf = (char *)pvBuf + cb;
191 } /* walk pages in ram range. */
192 }
193 else
194 {
195 LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
196
197 /*
198 * Unassigned address space.
199 */
200 if (!pRam)
201 break;
202 size_t cb = pRam->GCPhys - GCPhys;
203 if (cb >= cbRead)
204 {
205 memset(pvBuf, 0xff, cbRead);
206 break;
207 }
208 memset(pvBuf, 0xff, cb);
209
210 cbRead -= cb;
211 pvBuf = (char *)pvBuf + cb;
212 GCPhys += cb;
213 }
214 } /* Ram range walk */
215
216 pgmUnlock(pVM);
217
218 return VINF_SUCCESS;
219}
220
221
222/**
223 * EMT worker for PGMR3PhysWriteExternal.
224 */
225static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
226{
227 /** @todo VERR_EM_NO_MEMORY */
228 PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
229 return VINF_SUCCESS;
230}
231
232
233/**
234 * Write to physical memory, external users.
235 *
236 * @returns VBox status code.
237 * @retval VINF_SUCCESS.
238 * @retval VERR_EM_NO_MEMORY.
239 *
240 * @param pVM VM Handle.
241 * @param GCPhys Physical address to write to.
242 * @param pvBuf What to write.
243 * @param cbWrite How many bytes to write.
244 *
245 * @thread Any but EMTs.
246 */
247VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
248{
249 VM_ASSERT_OTHER_THREAD(pVM);
250
251 AssertMsg(!pVM->pgm.s.fNoMorePhysWrites, ("Calling PGMR3PhysWriteExternal after pgmR3Save()!\n"));
252 AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
253 LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
254
255 pgmLock(pVM);
256
257 /*
258 * Copy loop on ram ranges, stop when we hit something difficult.
259 */
260 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
261 for (;;)
262 {
263 /* Find range. */
264 while (pRam && GCPhys > pRam->GCPhysLast)
265 pRam = pRam->CTX_SUFF(pNext);
266 /* Inside range or not? */
267 if (pRam && GCPhys >= pRam->GCPhys)
268 {
269 /*
270 * Must work our way thru this page by page.
271 */
272 RTGCPTR off = GCPhys - pRam->GCPhys;
273 while (off < pRam->cb)
274 {
275 RTGCPTR iPage = off >> PAGE_SHIFT;
276 PPGMPAGE pPage = &pRam->aPages[iPage];
277
278 /*
279 * It the page is in any way problematic, we have to
280 * do the work on the EMT. Anything that needs to be made
281 * writable or involves access handlers is problematic.
282 */
283 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
284 || PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
285 {
286 pgmUnlock(pVM);
287
288 PVMREQ pReq = NULL;
289 int rc = VMR3ReqCall(pVM, VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT,
290 (PFNRT)pgmR3PhysWriteExternalEMT, 4, pVM, &GCPhys, pvBuf, cbWrite);
291 if (RT_SUCCESS(rc))
292 {
293 rc = pReq->iStatus;
294 VMR3ReqFree(pReq);
295 }
296 return rc;
297 }
298 Assert(!PGM_PAGE_IS_MMIO(pPage));
299
300 /*
301 * Simple stuff, go ahead.
302 */
303 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
304 if (cb > cbWrite)
305 cb = cbWrite;
306 void *pvDst;
307 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
308 if (RT_SUCCESS(rc))
309 memcpy(pvDst, pvBuf, cb);
310 else
311 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
312 pRam->GCPhys + off, pPage, rc));
313
314 /* next page */
315 if (cb >= cbWrite)
316 {
317 pgmUnlock(pVM);
318 return VINF_SUCCESS;
319 }
320
321 cbWrite -= cb;
322 off += cb;
323 GCPhys += cb;
324 pvBuf = (const char *)pvBuf + cb;
325 } /* walk pages in ram range */
326 }
327 else
328 {
329 /*
330 * Unassigned address space, skip it.
331 */
332 if (!pRam)
333 break;
334 size_t cb = pRam->GCPhys - GCPhys;
335 if (cb >= cbWrite)
336 break;
337 cbWrite -= cb;
338 pvBuf = (const char *)pvBuf + cb;
339 GCPhys += cb;
340 }
341 } /* Ram range walk */
342
343 pgmUnlock(pVM);
344 return VINF_SUCCESS;
345}
346
347
348
349/**
350 * Links a new RAM range into the list.
351 *
352 * @param pVM Pointer to the shared VM structure.
353 * @param pNew Pointer to the new list entry.
354 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
355 */
356static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
357{
358 pgmLock(pVM);
359
360 PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
361 pNew->pNextR3 = pRam;
362 pNew->pNextR0 = pRam ? MMHyperCCToR0(pVM, pRam) : NIL_RTR0PTR;
363 pNew->pNextRC = pRam ? MMHyperCCToRC(pVM, pRam) : NIL_RTRCPTR;
364
365 if (pPrev)
366 {
367 pPrev->pNextR3 = pNew;
368 pPrev->pNextR0 = MMHyperCCToR0(pVM, pNew);
369 pPrev->pNextRC = MMHyperCCToRC(pVM, pNew);
370 }
371 else
372 {
373 pVM->pgm.s.pRamRangesR3 = pNew;
374 pVM->pgm.s.pRamRangesR0 = MMHyperCCToR0(pVM, pNew);
375 pVM->pgm.s.pRamRangesRC = MMHyperCCToRC(pVM, pNew);
376 }
377
378 pgmUnlock(pVM);
379}
380
381
382/**
383 * Unlink an existing RAM range from the list.
384 *
385 * @param pVM Pointer to the shared VM structure.
386 * @param pRam Pointer to the new list entry.
387 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
388 */
389static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
390{
391 Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
392
393 pgmLock(pVM);
394
395 PPGMRAMRANGE pNext = pRam->pNextR3;
396 if (pPrev)
397 {
398 pPrev->pNextR3 = pNext;
399 pPrev->pNextR0 = pNext ? MMHyperCCToR0(pVM, pNext) : NIL_RTR0PTR;
400 pPrev->pNextRC = pNext ? MMHyperCCToRC(pVM, pNext) : NIL_RTRCPTR;
401 }
402 else
403 {
404 Assert(pVM->pgm.s.pRamRangesR3 == pRam);
405 pVM->pgm.s.pRamRangesR3 = pNext;
406 pVM->pgm.s.pRamRangesR0 = pNext ? MMHyperCCToR0(pVM, pNext) : NIL_RTR0PTR;
407 pVM->pgm.s.pRamRangesRC = pNext ? MMHyperCCToRC(pVM, pNext) : NIL_RTRCPTR;
408 }
409
410 pgmUnlock(pVM);
411}
412
413
414/**
415 * Unlink an existing RAM range from the list.
416 *
417 * @param pVM Pointer to the shared VM structure.
418 * @param pRam Pointer to the new list entry.
419 */
420static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
421{
422 /* find prev. */
423 PPGMRAMRANGE pPrev = NULL;
424 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
425 while (pCur != pRam)
426 {
427 pPrev = pCur;
428 pCur = pCur->pNextR3;
429 }
430 AssertFatal(pCur);
431
432 pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
433}
434
435
436/**
437 * Sets up a range RAM.
438 *
439 * This will check for conflicting registrations, make a resource
440 * reservation for the memory (with GMM), and setup the per-page
441 * tracking structures (PGMPAGE).
442 *
443 * @returns VBox stutus code.
444 * @param pVM Pointer to the shared VM structure.
445 * @param GCPhys The physical address of the RAM.
446 * @param cb The size of the RAM.
447 * @param pszDesc The description - not copied, so, don't free or change it.
448 */
449VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
450{
451 /*
452 * Validate input.
453 */
454 Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
455 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
456 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
457 AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
458 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
459 AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
460 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
461 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
462
463 /*
464 * Find range location and check for conflicts.
465 * (We don't lock here because the locking by EMT is only required on update.)
466 */
467 PPGMRAMRANGE pPrev = NULL;
468 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
469 while (pRam && GCPhysLast >= pRam->GCPhys)
470 {
471 if ( GCPhysLast >= pRam->GCPhys
472 && GCPhys <= pRam->GCPhysLast)
473 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
474 GCPhys, GCPhysLast, pszDesc,
475 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
476 VERR_PGM_RAM_CONFLICT);
477
478 /* next */
479 pPrev = pRam;
480 pRam = pRam->pNextR3;
481 }
482
483 /*
484 * Register it with GMM (the API bitches).
485 */
486 const RTGCPHYS cPages = cb >> PAGE_SHIFT;
487 int rc = MMR3IncreaseBaseReservation(pVM, cPages);
488 if (RT_FAILURE(rc))
489 return rc;
490
491 /*
492 * Allocate RAM range.
493 */
494 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
495 PPGMRAMRANGE pNew;
496 rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
497 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
498
499 /*
500 * Initialize the range.
501 */
502 pNew->GCPhys = GCPhys;
503 pNew->GCPhysLast = GCPhysLast;
504 pNew->pszDesc = pszDesc;
505 pNew->cb = cb;
506 pNew->fFlags = 0;
507
508 pNew->pvR3 = NULL;
509#ifndef VBOX_WITH_NEW_PHYS_CODE
510 pNew->paChunkR3Ptrs = NULL;
511
512 /* Allocate memory for chunk to HC ptr lookup array. */
513 rc = MMHyperAlloc(pVM, (cb >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(void *), 16, MM_TAG_PGM, (void **)&pNew->paChunkR3Ptrs);
514 AssertRCReturn(rc, rc);
515 pNew->fFlags |= MM_RAM_FLAGS_DYNAMIC_ALLOC;
516
517#endif
518 RTGCPHYS iPage = cPages;
519 while (iPage-- > 0)
520 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
521
522 /*
523 * Insert the new RAM range.
524 */
525 pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
526
527 /*
528 * Notify REM.
529 */
530#ifdef VBOX_WITH_NEW_PHYS_CODE
531 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, 0);
532#else
533 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, MM_RAM_FLAGS_DYNAMIC_ALLOC);
534#endif
535
536 return VINF_SUCCESS;
537}
538
539
540/**
541 * Resets (zeros) the RAM.
542 *
543 * ASSUMES that the caller owns the PGM lock.
544 *
545 * @returns VBox status code.
546 * @param pVM Pointer to the shared VM structure.
547 */
548int pgmR3PhysRamReset(PVM pVM)
549{
550#ifdef VBOX_WITH_NEW_PHYS_CODE
551 /*
552 * We batch up pages before freeing them.
553 */
554 uint32_t cPendingPages = 0;
555 PGMMFREEPAGESREQ pReq;
556 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
557 AssertLogRelRCReturn(rc, rc);
558#endif
559
560 /*
561 * Walk the ram ranges.
562 */
563 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
564 {
565 uint32_t iPage = pRam->cb >> PAGE_SHIFT; Assert((RTGCPHYS)iPage << PAGE_SHIFT == pRam->cb);
566#ifdef VBOX_WITH_NEW_PHYS_CODE
567 if (!pVM->pgm.s.fRamPreAlloc)
568 {
569 /* Replace all RAM pages by ZERO pages. */
570 while (iPage-- > 0)
571 {
572 PPGMPAGE pPage = &pRam->aPages[iPage];
573 switch (PGM_PAGE_GET_TYPE(pPage))
574 {
575 case PGMPAGETYPE_RAM:
576 if (!PGM_PAGE_IS_ZERO(pPage))
577 {
578 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
579 AssertLogRelRCReturn(rc, rc);
580 }
581 break;
582
583 case PGMPAGETYPE_MMIO2:
584 case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
585 case PGMPAGETYPE_ROM:
586 case PGMPAGETYPE_MMIO:
587 break;
588 default:
589 AssertFailed();
590 }
591 } /* for each page */
592 }
593 else
594#endif
595 {
596 /* Zero the memory. */
597 while (iPage-- > 0)
598 {
599 PPGMPAGE pPage = &pRam->aPages[iPage];
600 switch (PGM_PAGE_GET_TYPE(pPage))
601 {
602#ifndef VBOX_WITH_NEW_PHYS_CODE
603 case PGMPAGETYPE_INVALID:
604 case PGMPAGETYPE_RAM:
605 if (pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2)) /** @todo PAGE FLAGS */
606 {
607 /* shadow ram is reloaded elsewhere. */
608 Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO))); /** @todo PAGE FLAGS */
609 continue;
610 }
611 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
612 {
613 unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
614 if (pRam->paChunkR3Ptrs[iChunk])
615 ASMMemZero32((char *)pRam->paChunkR3Ptrs[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
616 }
617 else
618 ASMMemZero32((char *)pRam->pvR3 + (iPage << PAGE_SHIFT), PAGE_SIZE);
619 break;
620#else /* VBOX_WITH_NEW_PHYS_CODE */
621 case PGMPAGETYPE_RAM:
622 switch (PGM_PAGE_GET_STATE(pPage))
623 {
624 case PGM_PAGE_STATE_ZERO:
625 break;
626 case PGM_PAGE_STATE_SHARED:
627 case PGM_PAGE_STATE_WRITE_MONITORED:
628 rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
629 AssertLogRelRCReturn(rc, rc);
630 case PGM_PAGE_STATE_ALLOCATED:
631 {
632 void *pvPage;
633 PPGMPAGEMAP pMapIgnored;
634 rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pMapIgnored, &pvPage);
635 AssertLogRelRCReturn(rc, rc);
636 ASMMemZeroPage(pvPage);
637 break;
638 }
639 }
640 break;
641#endif /* VBOX_WITH_NEW_PHYS_CODE */
642
643 case PGMPAGETYPE_MMIO2:
644 case PGMPAGETYPE_ROM_SHADOW:
645 case PGMPAGETYPE_ROM:
646 case PGMPAGETYPE_MMIO:
647 break;
648 default:
649 AssertFailed();
650
651 }
652 } /* for each page */
653 }
654
655 }
656
657#ifdef VBOX_WITH_NEW_PHYS_CODE
658 /*
659 * Finish off any pages pending freeing.
660 */
661 if (cPendingPages)
662 {
663 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
664 AssertLogRelRCReturn(rc, rc);
665 }
666 GMMR3FreePagesCleanup(pReq);
667#endif
668
669
670 return VINF_SUCCESS;
671}
672
673
674/**
675 * This is the interface IOM is using to register an MMIO region.
676 *
677 * It will check for conflicts and ensure that a RAM range structure
678 * is present before calling the PGMR3HandlerPhysicalRegister API to
679 * register the callbacks.
680 *
681 * @returns VBox status code.
682 *
683 * @param pVM Pointer to the shared VM structure.
684 * @param GCPhys The start of the MMIO region.
685 * @param cb The size of the MMIO region.
686 * @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
687 * @param pvUserR3 The user argument for R3.
688 * @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
689 * @param pvUserR0 The user argument for R0.
690 * @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
691 * @param pvUserRC The user argument for RC.
692 * @param pszDesc The description of the MMIO region.
693 */
694VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
695 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
696 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
697 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
698 R3PTRTYPE(const char *) pszDesc)
699{
700 /*
701 * Assert on some assumption.
702 */
703 VM_ASSERT_EMT(pVM);
704 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
705 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
706 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
707 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
708
709 /*
710 * Make sure there's a RAM range structure for the region.
711 */
712 int rc;
713 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
714 bool fRamExists = false;
715 PPGMRAMRANGE pRamPrev = NULL;
716 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
717 while (pRam && GCPhysLast >= pRam->GCPhys)
718 {
719 if ( GCPhysLast >= pRam->GCPhys
720 && GCPhys <= pRam->GCPhysLast)
721 {
722 /* Simplification: all within the same range. */
723 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
724 && GCPhysLast <= pRam->GCPhysLast,
725 ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
726 GCPhys, GCPhysLast, pszDesc,
727 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
728 VERR_PGM_RAM_CONFLICT);
729
730 /* Check that it's all RAM or MMIO pages. */
731 PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
732 uint32_t cLeft = cb >> PAGE_SHIFT;
733 while (cLeft-- > 0)
734 {
735 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
736 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
737 ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
738 GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
739 VERR_PGM_RAM_CONFLICT);
740 pPage++;
741 }
742
743 /* Looks good. */
744 fRamExists = true;
745 break;
746 }
747
748 /* next */
749 pRamPrev = pRam;
750 pRam = pRam->pNextR3;
751 }
752 PPGMRAMRANGE pNew;
753 if (fRamExists)
754 pNew = NULL;
755 else
756 {
757 /*
758 * No RAM range, insert an ad-hoc one.
759 *
760 * Note that we don't have to tell REM about this range because
761 * PGMHandlerPhysicalRegisterEx will do that for us.
762 */
763 Log(("PGMR3PhysMMIORegister: Adding ad-hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
764
765 const uint32_t cPages = cb >> PAGE_SHIFT;
766 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
767 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
768 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
769
770 /* Initialize the range. */
771 pNew->GCPhys = GCPhys;
772 pNew->GCPhysLast = GCPhysLast;
773 pNew->pszDesc = pszDesc;
774 pNew->cb = cb;
775 pNew->fFlags = 0; /* Some MMIO flag here? */
776
777 pNew->pvR3 = NULL;
778#ifndef VBOX_WITH_NEW_PHYS_CODE
779 pNew->paChunkR3Ptrs = NULL;
780#endif
781
782 uint32_t iPage = cPages;
783 while (iPage-- > 0)
784 PGM_PAGE_INIT_ZERO_REAL(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
785 Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
786
787 /* link it */
788 pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
789 }
790
791 /*
792 * Register the access handler.
793 */
794 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
795 pfnHandlerR3, pvUserR3,
796 pfnHandlerR0, pvUserR0,
797 pfnHandlerRC, pvUserRC, pszDesc);
798 if ( RT_FAILURE(rc)
799 && !fRamExists)
800 {
801 /* remove the ad-hoc range. */
802 pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
803 pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
804 MMHyperFree(pVM, pRam);
805 }
806
807 return rc;
808}
809
810
811/**
812 * This is the interface IOM is using to register an MMIO region.
813 *
814 * It will take care of calling PGMHandlerPhysicalDeregister and clean up
815 * any ad-hoc PGMRAMRANGE left behind.
816 *
817 * @returns VBox status code.
818 * @param pVM Pointer to the shared VM structure.
819 * @param GCPhys The start of the MMIO region.
820 * @param cb The size of the MMIO region.
821 */
822VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
823{
824 VM_ASSERT_EMT(pVM);
825
826 /*
827 * First deregister the handler, then check if we should remove the ram range.
828 */
829 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
830 if (RT_SUCCESS(rc))
831 {
832 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
833 PPGMRAMRANGE pRamPrev = NULL;
834 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
835 while (pRam && GCPhysLast >= pRam->GCPhys)
836 {
837 /*if ( GCPhysLast >= pRam->GCPhys
838 && GCPhys <= pRam->GCPhysLast) - later */
839 if ( GCPhysLast == pRam->GCPhysLast
840 && GCPhys == pRam->GCPhys)
841 {
842 Assert(pRam->cb == cb);
843
844 /*
845 * See if all the pages are dead MMIO pages.
846 */
847 bool fAllMMIO = true;
848 PPGMPAGE pPage = &pRam->aPages[0];
849 uint32_t cLeft = cb >> PAGE_SHIFT;
850 while (cLeft-- > 0)
851 {
852 if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
853 /*|| not-out-of-action later */)
854 {
855 fAllMMIO = false;
856 break;
857 }
858 pPage++;
859 }
860
861 /*
862 * Unlink it and free if it's all MMIO.
863 */
864 if (fAllMMIO)
865 {
866 Log(("PGMR3PhysMMIODeregister: Freeing ad-hoc MMIO range for %RGp-%RGp %s\n",
867 GCPhys, GCPhysLast, pRam->pszDesc));
868
869 pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
870 pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
871 MMHyperFree(pVM, pRam);
872 }
873 break;
874 }
875
876 /* next */
877 pRamPrev = pRam;
878 pRam = pRam->pNextR3;
879 }
880 }
881
882 return rc;
883}
884
885
886/**
887 * Locate a MMIO2 range.
888 *
889 * @returns Pointer to the MMIO2 range.
890 * @param pVM Pointer to the shared VM structure.
891 * @param pDevIns The device instance owning the region.
892 * @param iRegion The region.
893 */
894DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
895{
896 /*
897 * Search the list.
898 */
899 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
900 if ( pCur->pDevInsR3 == pDevIns
901 && pCur->iRegion == iRegion)
902 return pCur;
903 return NULL;
904}
905
906
907/**
908 * Allocate and register an MMIO2 region.
909 *
910 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
911 * RAM associated with a device. It is also non-shared memory with a
912 * permanent ring-3 mapping and page backing (presently).
913 *
914 * A MMIO2 range may overlap with base memory if a lot of RAM
915 * is configured for the VM, in which case we'll drop the base
916 * memory pages. Presently we will make no attempt to preserve
917 * anything that happens to be present in the base memory that
918 * is replaced, this is of course incorrectly but it's too much
919 * effort.
920 *
921 * @returns VBox status code.
922 * @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
923 * @retval VERR_ALREADY_EXISTS if the region already exists.
924 *
925 * @param pVM Pointer to the shared VM structure.
926 * @param pDevIns The device instance owning the region.
927 * @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
928 * this number has to be the number of that region. Otherwise
929 * it can be any number safe UINT8_MAX.
930 * @param cb The size of the region. Must be page aligned.
931 * @param fFlags Reserved for future use, must be zero.
932 * @param ppv Where to store the pointer to the ring-3 mapping of the memory.
933 * @param pszDesc The description.
934 */
935VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)
936{
937 /*
938 * Validate input.
939 */
940 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
941 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
942 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
943 AssertPtrReturn(ppv, VERR_INVALID_POINTER);
944 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
945 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
946 AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
947 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
948 AssertReturn(cb, VERR_INVALID_PARAMETER);
949 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
950
951 const uint32_t cPages = cb >> PAGE_SHIFT;
952 AssertLogRelReturn((RTGCPHYS)cPages << PAGE_SHIFT == cb, VERR_INVALID_PARAMETER);
953 AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
954
955 /*
956 * Try reserve and allocate the backing memory first as this is what is
957 * most likely to fail.
958 */
959 int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
960 if (RT_FAILURE(rc))
961 return rc;
962
963 void *pvPages;
964 PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
965 if (RT_SUCCESS(rc))
966 rc = SUPR3PageAllocEx(cPages, 0 /*fFlags*/, &pvPages, NULL /*pR0Ptr*/, paPages);
967 if (RT_SUCCESS(rc))
968 {
969 memset(pvPages, 0, cPages * PAGE_SIZE);
970
971 /*
972 * Create the MMIO2 range record for it.
973 */
974 const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
975 PPGMMMIO2RANGE pNew;
976 rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
977 AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
978 if (RT_SUCCESS(rc))
979 {
980 pNew->pDevInsR3 = pDevIns;
981 pNew->pvR3 = pvPages;
982 //pNew->pNext = NULL;
983 //pNew->fMapped = false;
984 //pNew->fOverlapping = false;
985 pNew->iRegion = iRegion;
986 pNew->RamRange.GCPhys = NIL_RTGCPHYS;
987 pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
988 pNew->RamRange.pszDesc = pszDesc;
989 pNew->RamRange.cb = cb;
990 //pNew->RamRange.fFlags = 0;
991
992 pNew->RamRange.pvR3 = pvPages; ///@todo remove this [new phys code]
993#ifndef VBOX_WITH_NEW_PHYS_CODE
994 pNew->RamRange.paChunkR3Ptrs = NULL; ///@todo remove this [new phys code]
995#endif
996
997 uint32_t iPage = cPages;
998 while (iPage-- > 0)
999 {
1000 PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1001 paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
1002 PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1003 }
1004
1005 /*
1006 * Link it into the list.
1007 * Since there is no particular order, just push it.
1008 */
1009 pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1010 pVM->pgm.s.pMmio2RangesR3 = pNew;
1011
1012 *ppv = pvPages;
1013 RTMemTmpFree(paPages);
1014 return VINF_SUCCESS;
1015 }
1016
1017 SUPR3PageFreeEx(pvPages, cPages);
1018 }
1019 RTMemTmpFree(paPages);
1020 MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1021 return rc;
1022}
1023
1024
1025/**
1026 * Deregisters and frees an MMIO2 region.
1027 *
1028 * Any physical (and virtual) access handlers registered for the region must
1029 * be deregistered before calling this function.
1030 *
1031 * @returns VBox status code.
1032 * @param pVM Pointer to the shared VM structure.
1033 * @param pDevIns The device instance owning the region.
1034 * @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1035 */
1036VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1037{
1038 /*
1039 * Validate input.
1040 */
1041 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1042 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1043 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1044
1045 int rc = VINF_SUCCESS;
1046 unsigned cFound = 0;
1047 PPGMMMIO2RANGE pPrev = NULL;
1048 PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1049 while (pCur)
1050 {
1051 if ( pCur->pDevInsR3 == pDevIns
1052 && ( iRegion == UINT32_MAX
1053 || pCur->iRegion == iRegion))
1054 {
1055 cFound++;
1056
1057 /*
1058 * Unmap it if it's mapped.
1059 */
1060 if (pCur->fMapped)
1061 {
1062 int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1063 AssertRC(rc2);
1064 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1065 rc = rc2;
1066 }
1067
1068 /*
1069 * Unlink it
1070 */
1071 PPGMMMIO2RANGE pNext = pCur->pNextR3;
1072 if (pPrev)
1073 pPrev->pNextR3 = pNext;
1074 else
1075 pVM->pgm.s.pMmio2RangesR3 = pNext;
1076 pCur->pNextR3 = NULL;
1077
1078 /*
1079 * Free the memory.
1080 */
1081 int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1082 AssertRC(rc2);
1083 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1084 rc = rc2;
1085
1086 rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)(pCur->RamRange.cb >> PAGE_SHIFT), pCur->RamRange.pszDesc);
1087 AssertRC(rc2);
1088 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1089 rc = rc2;
1090
1091 /* we're leaking hyper memory here if done at runtime. */
1092 Assert( VMR3GetState(pVM) == VMSTATE_OFF
1093 || VMR3GetState(pVM) == VMSTATE_DESTROYING
1094 || VMR3GetState(pVM) == VMSTATE_TERMINATED
1095 || VMR3GetState(pVM) == VMSTATE_CREATING);
1096 /*rc = MMHyperFree(pVM, pCur);
1097 AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1098
1099 /* next */
1100 pCur = pNext;
1101 }
1102 else
1103 {
1104 pPrev = pCur;
1105 pCur = pCur->pNextR3;
1106 }
1107 }
1108
1109 return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1110}
1111
1112
1113/**
1114 * Maps a MMIO2 region.
1115 *
1116 * This is done when a guest / the bios / state loading changes the
1117 * PCI config. The replacing of base memory has the same restrictions
1118 * as during registration, of course.
1119 *
1120 * @returns VBox status code.
1121 *
1122 * @param pVM Pointer to the shared VM structure.
1123 * @param pDevIns The
1124 */
1125VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1126{
1127 /*
1128 * Validate input
1129 */
1130 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1131 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1132 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1133 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1134 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1135 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1136
1137 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1138 AssertReturn(pCur, VERR_NOT_FOUND);
1139 AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
1140 Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
1141 Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
1142
1143 const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
1144 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1145
1146 /*
1147 * Find our location in the ram range list, checking for
1148 * restriction we don't bother implementing yet (partially overlapping).
1149 */
1150 bool fRamExists = false;
1151 PPGMRAMRANGE pRamPrev = NULL;
1152 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1153 while (pRam && GCPhysLast >= pRam->GCPhys)
1154 {
1155 if ( GCPhys <= pRam->GCPhysLast
1156 && GCPhysLast >= pRam->GCPhys)
1157 {
1158 /* completely within? */
1159 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1160 && GCPhysLast <= pRam->GCPhysLast,
1161 ("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
1162 GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
1163 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1164 VERR_PGM_RAM_CONFLICT);
1165 fRamExists = true;
1166 break;
1167 }
1168
1169 /* next */
1170 pRamPrev = pRam;
1171 pRam = pRam->pNextR3;
1172 }
1173 if (fRamExists)
1174 {
1175 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1176 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1177 while (cPagesLeft-- > 0)
1178 {
1179 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1180 ("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
1181 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
1182 VERR_PGM_RAM_CONFLICT);
1183 pPage++;
1184 }
1185 }
1186 Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
1187 GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
1188
1189 /*
1190 * Make the changes.
1191 */
1192 pgmLock(pVM);
1193
1194 pCur->RamRange.GCPhys = GCPhys;
1195 pCur->RamRange.GCPhysLast = GCPhysLast;
1196 pCur->fMapped = true;
1197 pCur->fOverlapping = fRamExists;
1198
1199 if (fRamExists)
1200 {
1201 uint32_t cPendingPages = 0;
1202 PGMMFREEPAGESREQ pReq;
1203 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1204 AssertLogRelRCReturn(rc, rc);
1205
1206 /* replace the pages, freeing all present RAM pages. */
1207 PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
1208 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1209 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1210 while (cPagesLeft-- > 0)
1211 {
1212 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
1213 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1214
1215 RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
1216 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
1217 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
1218 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
1219
1220 GCPhys += PAGE_SIZE;
1221 pPageSrc++;
1222 pPageDst++;
1223 }
1224
1225 if (cPendingPages)
1226 {
1227 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1228 AssertLogRelRCReturn(rc, rc);
1229 }
1230 GMMR3FreePagesCleanup(pReq);
1231 }
1232 else
1233 {
1234 /* link in the ram range */
1235 pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
1236 REMR3NotifyPhysRamRegister(pVM, GCPhys, pCur->RamRange.cb, 0);
1237 }
1238
1239 pgmUnlock(pVM);
1240
1241 return VINF_SUCCESS;
1242}
1243
1244
1245/**
1246 * Unmaps a MMIO2 region.
1247 *
1248 * This is done when a guest / the bios / state loading changes the
1249 * PCI config. The replacing of base memory has the same restrictions
1250 * as during registration, of course.
1251 */
1252VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1253{
1254 /*
1255 * Validate input
1256 */
1257 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1258 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1259 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1260 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1261 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1262 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1263
1264 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1265 AssertReturn(pCur, VERR_NOT_FOUND);
1266 AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
1267 AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
1268 Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
1269
1270 Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
1271 pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
1272
1273 /*
1274 * Unmap it.
1275 */
1276 pgmLock(pVM);
1277
1278 if (pCur->fOverlapping)
1279 {
1280 /* Restore the RAM pages we've replaced. */
1281 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1282 while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
1283 pRam = pRam->pNextR3;
1284
1285 RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
1286 Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
1287 PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1288 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1289 while (cPagesLeft-- > 0)
1290 {
1291 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
1292 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
1293 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
1294 PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
1295
1296 pPageDst++;
1297 }
1298 }
1299 else
1300 {
1301 REMR3NotifyPhysRamDeregister(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb);
1302 pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
1303 }
1304
1305 pCur->RamRange.GCPhys = NIL_RTGCPHYS;
1306 pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
1307 pCur->fOverlapping = false;
1308 pCur->fMapped = false;
1309
1310 pgmUnlock(pVM);
1311
1312 return VINF_SUCCESS;
1313}
1314
1315
1316/**
1317 * Checks if the given address is an MMIO2 base address or not.
1318 *
1319 * @returns true/false accordingly.
1320 * @param pVM Pointer to the shared VM structure.
1321 * @param pDevIns The owner of the memory, optional.
1322 * @param GCPhys The address to check.
1323 */
1324VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
1325{
1326 /*
1327 * Validate input
1328 */
1329 VM_ASSERT_EMT_RETURN(pVM, false);
1330 AssertPtrReturn(pDevIns, false);
1331 AssertReturn(GCPhys != NIL_RTGCPHYS, false);
1332 AssertReturn(GCPhys != 0, false);
1333 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
1334
1335 /*
1336 * Search the list.
1337 */
1338 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1339 if (pCur->RamRange.GCPhys == GCPhys)
1340 {
1341 Assert(pCur->fMapped);
1342 return true;
1343 }
1344 return false;
1345}
1346
1347
1348/**
1349 * Gets the HC physical address of a page in the MMIO2 region.
1350 *
1351 * This is API is intended for MMHyper and shouldn't be called
1352 * by anyone else...
1353 *
1354 * @returns VBox status code.
1355 * @param pVM Pointer to the shared VM structure.
1356 * @param pDevIns The owner of the memory, optional.
1357 * @param iRegion The region.
1358 * @param off The page expressed an offset into the MMIO2 region.
1359 * @param pHCPhys Where to store the result.
1360 */
1361VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
1362{
1363 /*
1364 * Validate input
1365 */
1366 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1367 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1368 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1369
1370 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1371 AssertReturn(pCur, VERR_NOT_FOUND);
1372 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1373
1374 PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
1375 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
1376 return VINF_SUCCESS;
1377}
1378
1379
1380/**
1381 * Maps a portion of an MMIO2 region into kernel space (host).
1382 *
1383 * The kernel mapping will become invalid when the MMIO2 memory is deregistered
1384 * or the VM is terminated.
1385 *
1386 * @return VBox status code.
1387 *
1388 * @param pVM Pointer to the shared VM structure.
1389 * @param pDevIns The device owning the MMIO2 memory.
1390 * @param iRegion The region.
1391 * @param off The offset into the region. Must be page aligned.
1392 * @param cb The number of bytes to map. Must be page aligned.
1393 * @param pszDesc Mapping description.
1394 * @param pR0Ptr Where to store the R0 address.
1395 */
1396VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
1397 const char *pszDesc, PRTR0PTR pR0Ptr)
1398{
1399 /*
1400 * Validate input.
1401 */
1402 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1403 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1404 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1405
1406 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1407 AssertReturn(pCur, VERR_NOT_FOUND);
1408 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1409 AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1410 AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1411
1412 /*
1413 * Pass the request on to the support library/driver.
1414 */
1415 int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
1416
1417 return rc;
1418}
1419
1420
1421/**
1422 * Registers a ROM image.
1423 *
1424 * Shadowed ROM images requires double the amount of backing memory, so,
1425 * don't use that unless you have to. Shadowing of ROM images is process
1426 * where we can select where the reads go and where the writes go. On real
1427 * hardware the chipset provides means to configure this. We provide
1428 * PGMR3PhysProtectROM() for this purpose.
1429 *
1430 * A read-only copy of the ROM image will always be kept around while we
1431 * will allocate RAM pages for the changes on demand (unless all memory
1432 * is configured to be preallocated).
1433 *
1434 * @returns VBox status.
1435 * @param pVM VM Handle.
1436 * @param pDevIns The device instance owning the ROM.
1437 * @param GCPhys First physical address in the range.
1438 * Must be page aligned!
1439 * @param cbRange The size of the range (in bytes).
1440 * Must be page aligned!
1441 * @param pvBinary Pointer to the binary data backing the ROM image.
1442 * This must be exactly \a cbRange in size.
1443 * @param fFlags Mask of flags. PGMPHYS_ROM_FLAG_SHADOWED
1444 * and/or PGMPHYS_ROM_FLAG_PERMANENT_BINARY.
1445 * @param pszDesc Pointer to description string. This must not be freed.
1446 *
1447 * @remark There is no way to remove the rom, automatically on device cleanup or
1448 * manually from the device yet. This isn't difficult in any way, it's
1449 * just not something we expect to be necessary for a while.
1450 */
1451VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
1452 const void *pvBinary, uint32_t fFlags, const char *pszDesc)
1453{
1454 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
1455 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
1456
1457 /*
1458 * Validate input.
1459 */
1460 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1461 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1462 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1463 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1464 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1465 AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
1466 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1467 AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAG_SHADOWED | PGMPHYS_ROM_FLAG_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
1468 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
1469
1470 const uint32_t cPages = cb >> PAGE_SHIFT;
1471
1472 /*
1473 * Find the ROM location in the ROM list first.
1474 */
1475 PPGMROMRANGE pRomPrev = NULL;
1476 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
1477 while (pRom && GCPhysLast >= pRom->GCPhys)
1478 {
1479 if ( GCPhys <= pRom->GCPhysLast
1480 && GCPhysLast >= pRom->GCPhys)
1481 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1482 GCPhys, GCPhysLast, pszDesc,
1483 pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
1484 VERR_PGM_RAM_CONFLICT);
1485 /* next */
1486 pRomPrev = pRom;
1487 pRom = pRom->pNextR3;
1488 }
1489
1490 /*
1491 * Find the RAM location and check for conflicts.
1492 *
1493 * Conflict detection is a bit different than for RAM
1494 * registration since a ROM can be located within a RAM
1495 * range. So, what we have to check for is other memory
1496 * types (other than RAM that is) and that we don't span
1497 * more than one RAM range (layz).
1498 */
1499 bool fRamExists = false;
1500 PPGMRAMRANGE pRamPrev = NULL;
1501 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1502 while (pRam && GCPhysLast >= pRam->GCPhys)
1503 {
1504 if ( GCPhys <= pRam->GCPhysLast
1505 && GCPhysLast >= pRam->GCPhys)
1506 {
1507 /* completely within? */
1508 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1509 && GCPhysLast <= pRam->GCPhysLast,
1510 ("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
1511 GCPhys, GCPhysLast, pszDesc,
1512 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1513 VERR_PGM_RAM_CONFLICT);
1514 fRamExists = true;
1515 break;
1516 }
1517
1518 /* next */
1519 pRamPrev = pRam;
1520 pRam = pRam->pNextR3;
1521 }
1522 if (fRamExists)
1523 {
1524 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1525 uint32_t cPagesLeft = cPages;
1526 while (cPagesLeft-- > 0)
1527 {
1528 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1529 ("%RGp isn't a RAM page (%d) - registering %RGp-%RGp (%s).\n",
1530 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pszDesc),
1531 VERR_PGM_RAM_CONFLICT);
1532 Assert(PGM_PAGE_IS_ZERO(pPage));
1533 pPage++;
1534 }
1535 }
1536
1537 /*
1538 * Update the base memory reservation if necessary.
1539 */
1540 uint32_t cExtraBaseCost = fRamExists ? cPages : 0;
1541 if (fFlags & PGMPHYS_ROM_FLAG_SHADOWED)
1542 cExtraBaseCost += cPages;
1543 if (cExtraBaseCost)
1544 {
1545 int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
1546 if (RT_FAILURE(rc))
1547 return rc;
1548 }
1549
1550 /*
1551 * Allocate memory for the virgin copy of the RAM.
1552 */
1553 PGMMALLOCATEPAGESREQ pReq;
1554 int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
1555 AssertRCReturn(rc, rc);
1556
1557 for (uint32_t iPage = 0; iPage < cPages; iPage++)
1558 {
1559 pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
1560 pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
1561 pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
1562 }
1563
1564 pgmLock(pVM);
1565 rc = GMMR3AllocatePagesPerform(pVM, pReq);
1566 pgmUnlock(pVM);
1567 if (RT_FAILURE(rc))
1568 {
1569 GMMR3AllocatePagesCleanup(pReq);
1570 return rc;
1571 }
1572
1573 /*
1574 * Allocate the new ROM range and RAM range (if necessary).
1575 */
1576 PPGMROMRANGE pRomNew;
1577 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
1578 if (RT_SUCCESS(rc))
1579 {
1580 PPGMRAMRANGE pRamNew = NULL;
1581 if (!fRamExists)
1582 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
1583 if (RT_SUCCESS(rc))
1584 {
1585 pgmLock(pVM);
1586
1587 /*
1588 * Initialize and insert the RAM range (if required).
1589 */
1590 PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
1591 if (!fRamExists)
1592 {
1593 pRamNew->GCPhys = GCPhys;
1594 pRamNew->GCPhysLast = GCPhysLast;
1595 pRamNew->pszDesc = pszDesc;
1596 pRamNew->cb = cb;
1597 pRamNew->fFlags = 0;
1598 pRamNew->pvR3 = NULL;
1599
1600 PPGMPAGE pPage = &pRamNew->aPages[0];
1601 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
1602 {
1603 PGM_PAGE_INIT(pPage,
1604 pReq->aPages[iPage].HCPhysGCPhys,
1605 pReq->aPages[iPage].idPage,
1606 PGMPAGETYPE_ROM,
1607 PGM_PAGE_STATE_ALLOCATED);
1608
1609 pRomPage->Virgin = *pPage;
1610 }
1611
1612 pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
1613 }
1614 else
1615 {
1616 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1617 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
1618 {
1619 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
1620 PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
1621 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1622 PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
1623
1624 pRomPage->Virgin = *pPage;
1625 }
1626
1627 pRamNew = pRam;
1628 }
1629 pgmUnlock(pVM);
1630
1631
1632 /*
1633 * !HACK ALERT! REM + (Shadowed) ROM ==> mess.
1634 *
1635 * If it's shadowed we'll register the handler after the ROM notification
1636 * so we get the access handler callbacks that we should. If it isn't
1637 * shadowed we'll do it the other way around to make REM use the built-in
1638 * ROM behavior and not the handler behavior (which is to route all access
1639 * to PGM atm).
1640 */
1641 if (fFlags & PGMPHYS_ROM_FLAG_SHADOWED)
1642 {
1643 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
1644 rc = PGMR3HandlerPhysicalRegister(pVM,
1645 fFlags & PGMPHYS_ROM_FLAG_SHADOWED
1646 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
1647 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1648 GCPhys, GCPhysLast,
1649 pgmR3PhysRomWriteHandler, pRomNew,
1650 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
1651 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
1652 }
1653 else
1654 {
1655 rc = PGMR3HandlerPhysicalRegister(pVM,
1656 fFlags & PGMPHYS_ROM_FLAG_SHADOWED
1657 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
1658 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1659 GCPhys, GCPhysLast,
1660 pgmR3PhysRomWriteHandler, pRomNew,
1661 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
1662 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
1663 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
1664 }
1665 if (RT_SUCCESS(rc))
1666 {
1667 pgmLock(pVM);
1668
1669 /*
1670 * Copy the image over to the virgin pages.
1671 * This must be done after linking in the RAM range.
1672 */
1673 PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
1674 for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
1675 {
1676 void *pvDstPage;
1677 PPGMPAGEMAP pMapIgnored;
1678 rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pMapIgnored, &pvDstPage);
1679 if (RT_FAILURE(rc))
1680 {
1681 VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
1682 break;
1683 }
1684 memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
1685 }
1686 if (RT_SUCCESS(rc))
1687 {
1688 /*
1689 * Initialize the ROM range.
1690 * Note that the Virgin member of the pages has already been initialized above.
1691 */
1692 pRomNew->GCPhys = GCPhys;
1693 pRomNew->GCPhysLast = GCPhysLast;
1694 pRomNew->cb = cb;
1695 pRomNew->fFlags = fFlags;
1696 pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAG_PERMANENT_BINARY ? pvBinary : NULL;
1697 pRomNew->pszDesc = pszDesc;
1698
1699 for (unsigned iPage = 0; iPage < cPages; iPage++)
1700 {
1701 PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
1702 pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
1703 PGM_PAGE_INIT_ZERO_REAL(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
1704 }
1705
1706 /*
1707 * Insert the ROM range, tell REM and return successfully.
1708 */
1709 pRomNew->pNextR3 = pRom;
1710 pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
1711 pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
1712
1713 if (pRomPrev)
1714 {
1715 pRomPrev->pNextR3 = pRomNew;
1716 pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
1717 pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
1718 }
1719 else
1720 {
1721 pVM->pgm.s.pRomRangesR3 = pRomNew;
1722 pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
1723 pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
1724 }
1725
1726 GMMR3AllocatePagesCleanup(pReq);
1727 pgmUnlock(pVM);
1728 return VINF_SUCCESS;
1729 }
1730
1731 /* bail out */
1732
1733 pgmUnlock(pVM);
1734 int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1735 AssertRC(rc2);
1736 pgmLock(pVM);
1737 }
1738
1739 if (!fRamExists)
1740 {
1741 pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
1742 MMHyperFree(pVM, pRamNew);
1743 }
1744 }
1745 MMHyperFree(pVM, pRomNew);
1746 }
1747
1748 /** @todo Purge the mapping cache or something... */
1749 GMMR3FreeAllocatedPages(pVM, pReq);
1750 GMMR3AllocatePagesCleanup(pReq);
1751 pgmUnlock(pVM);
1752 return rc;
1753}
1754
1755
1756/**
1757 * \#PF Handler callback for ROM write accesses.
1758 *
1759 * @returns VINF_SUCCESS if the handler have carried out the operation.
1760 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1761 * @param pVM VM Handle.
1762 * @param GCPhys The physical address the guest is writing to.
1763 * @param pvPhys The HC mapping of that address.
1764 * @param pvBuf What the guest is reading/writing.
1765 * @param cbBuf How much it's reading/writing.
1766 * @param enmAccessType The access type.
1767 * @param pvUser User argument.
1768 */
1769static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1770{
1771 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
1772 const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
1773 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
1774 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
1775 switch (pRomPage->enmProt)
1776 {
1777 /*
1778 * Ignore.
1779 */
1780 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
1781 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
1782 return VINF_SUCCESS;
1783
1784 /*
1785 * Write to the ram page.
1786 */
1787 case PGMROMPROT_READ_ROM_WRITE_RAM:
1788 case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
1789 {
1790 /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
1791 Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
1792
1793 /*
1794 * Take the lock, do lazy allocation, map the page and copy the data.
1795 *
1796 * Note that we have to bypass the mapping TLB since it works on
1797 * guest physical addresses and entering the shadow page would
1798 * kind of screw things up...
1799 */
1800 int rc = pgmLock(pVM);
1801 AssertRC(rc);
1802
1803 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pRomPage->Shadow) != PGM_PAGE_STATE_ALLOCATED))
1804 {
1805 rc = pgmPhysPageMakeWritable(pVM, &pRomPage->Shadow, GCPhys);
1806 if (RT_FAILURE(rc))
1807 {
1808 pgmUnlock(pVM);
1809 return rc;
1810 }
1811 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* returned */, ("%Rrc\n", rc));
1812 }
1813
1814 void *pvDstPage;
1815 PPGMPAGEMAP pMapIgnored;
1816 int rc2 = pgmPhysPageMap(pVM, &pRomPage->Shadow, GCPhys & X86_PTE_PG_MASK, &pMapIgnored, &pvDstPage);
1817 if (RT_SUCCESS(rc2))
1818 memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
1819 else
1820 rc = rc2;
1821
1822 pgmUnlock(pVM);
1823 return rc;
1824 }
1825
1826 default:
1827 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
1828 pRom->aPages[iPage].enmProt, iPage, GCPhys),
1829 VERR_INTERNAL_ERROR);
1830 }
1831}
1832
1833
1834/**
1835 * Called by PGMR3Reset to reset the shadow, switch to the virgin,
1836 * and verify that the virgin part is untouched.
1837 *
1838 * This is done after the normal memory has been cleared.
1839 *
1840 * ASSUMES that the caller owns the PGM lock.
1841 *
1842 * @param pVM The VM handle.
1843 */
1844int pgmR3PhysRomReset(PVM pVM)
1845{
1846 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
1847 {
1848 const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
1849
1850 if (pRom->fFlags & PGMPHYS_ROM_FLAG_SHADOWED)
1851 {
1852 /*
1853 * Reset the physical handler.
1854 */
1855 int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
1856 AssertRCReturn(rc, rc);
1857
1858 /*
1859 * What we do with the shadow pages depends on the memory
1860 * preallocation option. If not enabled, we'll just throw
1861 * out all the dirty pages and replace them by the zero page.
1862 */
1863 if (1)///@todo !pVM->pgm.f.fRamPreAlloc)
1864 {
1865 /* Count dirty shadow pages. */
1866 uint32_t cDirty = 0;
1867 uint32_t iPage = cPages;
1868 while (iPage-- > 0)
1869 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1870 cDirty++;
1871 if (cDirty)
1872 {
1873 /* Free the dirty pages. */
1874 PGMMFREEPAGESREQ pReq;
1875 rc = GMMR3FreePagesPrepare(pVM, &pReq, cDirty, GMMACCOUNT_BASE);
1876 AssertRCReturn(rc, rc);
1877
1878 uint32_t iReqPage = 0;
1879 for (iPage = 0; iPage < cPages; iPage++)
1880 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1881 {
1882 pReq->aPages[iReqPage].idPage = PGM_PAGE_GET_PAGEID(&pRom->aPages[iPage].Shadow);
1883 iReqPage++;
1884 }
1885
1886 rc = GMMR3FreePagesPerform(pVM, pReq, cDirty);
1887 GMMR3FreePagesCleanup(pReq);
1888 AssertRCReturn(rc, rc);
1889
1890 /* setup the zero page. */
1891 for (iPage = 0; iPage < cPages; iPage++)
1892 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1893 PGM_PAGE_INIT_ZERO_REAL(&pRom->aPages[iPage].Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
1894 }
1895 }
1896 else
1897 {
1898 /* clear all the pages. */
1899 for (uint32_t iPage = 0; iPage < cPages; iPage++)
1900 {
1901 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
1902 rc = pgmPhysPageMakeWritable(pVM, &pRom->aPages[iPage].Shadow, GCPhys);
1903 if (RT_FAILURE(rc))
1904 break;
1905
1906 void *pvDstPage;
1907 PPGMPAGEMAP pMapIgnored;
1908 rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pMapIgnored, &pvDstPage);
1909 if (RT_FAILURE(rc))
1910 break;
1911 ASMMemZeroPage(pvDstPage);
1912 }
1913 AssertRCReturn(rc, rc);
1914 }
1915 }
1916
1917#ifdef VBOX_STRICT
1918 /*
1919 * Verify that the virgin page is unchanged if possible.
1920 */
1921 if (pRom->pvOriginal)
1922 {
1923 uint8_t const *pbSrcPage = (uint8_t const *)pRom->pvOriginal;
1924 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
1925 {
1926 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
1927 PPGMPAGEMAP pMapIgnored;
1928 void *pvDstPage;
1929 int rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pMapIgnored, &pvDstPage);
1930 if (RT_FAILURE(rc))
1931 break;
1932 if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
1933 LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
1934 GCPhys, pRom->pszDesc));
1935 }
1936 }
1937#endif
1938 }
1939
1940 return VINF_SUCCESS;
1941}
1942
1943
1944/**
1945 * Change the shadowing of a range of ROM pages.
1946 *
1947 * This is intended for implementing chipset specific memory registers
1948 * and will not be very strict about the input. It will silently ignore
1949 * any pages that are not the part of a shadowed ROM.
1950 *
1951 * @returns VBox status code.
1952 * @param pVM Pointer to the shared VM structure.
1953 * @param GCPhys Where to start. Page aligned.
1954 * @param cb How much to change. Page aligned.
1955 * @param enmProt The new ROM protection.
1956 */
1957VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
1958{
1959 /*
1960 * Check input
1961 */
1962 if (!cb)
1963 return VINF_SUCCESS;
1964 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1965 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1966 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1967 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1968 AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
1969
1970 /*
1971 * Process the request.
1972 */
1973 bool fFlushedPool = false;
1974 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
1975 if ( GCPhys <= pRom->GCPhysLast
1976 && GCPhysLast >= pRom->GCPhys)
1977 {
1978 /*
1979 * Iterate the relevant pages and the ncessary make changes.
1980 */
1981 bool fChanges = false;
1982 uint32_t const cPages = pRom->GCPhysLast > GCPhysLast
1983 ? pRom->cb >> PAGE_SHIFT
1984 : (GCPhysLast - pRom->GCPhys) >> PAGE_SHIFT;
1985 for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
1986 iPage < cPages;
1987 iPage++)
1988 {
1989 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
1990 if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
1991 {
1992 fChanges = true;
1993
1994 /* flush the page pool first so we don't leave any usage references dangling. */
1995 if (!fFlushedPool)
1996 {
1997 pgmPoolFlushAll(pVM);
1998 fFlushedPool = true;
1999 }
2000
2001 PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2002 PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2003 PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2004
2005 *pOld = *pRamPage;
2006 *pRamPage = *pNew;
2007 /** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2008 }
2009 }
2010
2011 /*
2012 * Reset the access handler if we made changes, no need
2013 * to optimize this.
2014 */
2015 if (fChanges)
2016 {
2017 int rc = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2018 AssertRCReturn(rc, rc);
2019 }
2020
2021 /* Advance - cb isn't updated. */
2022 GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2023 }
2024
2025 return VINF_SUCCESS;
2026}
2027
2028#ifndef VBOX_WITH_NEW_PHYS_CODE
2029
2030/**
2031 * Interface that the MMR3RamRegister(), MMR3RomRegister() and MMIO handler
2032 * registration APIs calls to inform PGM about memory registrations.
2033 *
2034 * It registers the physical memory range with PGM. MM is responsible
2035 * for the toplevel things - allocation and locking - while PGM is taking
2036 * care of all the details and implements the physical address space virtualization.
2037 *
2038 * @returns VBox status.
2039 * @param pVM The VM handle.
2040 * @param pvRam HC virtual address of the RAM range. (page aligned)
2041 * @param GCPhys GC physical address of the RAM range. (page aligned)
2042 * @param cb Size of the RAM range. (page aligned)
2043 * @param fFlags Flags, MM_RAM_*.
2044 * @param paPages Pointer an array of physical page descriptors.
2045 * @param pszDesc Description string.
2046 */
2047VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc)
2048{
2049 /*
2050 * Validate input.
2051 * (Not so important because callers are only MMR3PhysRegister()
2052 * and PGMR3HandlerPhysicalRegisterEx(), but anyway...)
2053 */
2054 Log(("PGMR3PhysRegister %08X %x bytes flags %x %s\n", GCPhys, cb, fFlags, pszDesc));
2055
2056 Assert((fFlags & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_DYNAMIC_ALLOC)) || paPages);
2057 /*Assert(!(fFlags & MM_RAM_FLAGS_RESERVED) || !paPages);*/
2058 Assert((fFlags == (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO)) || (fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) || pvRam);
2059 /*Assert(!(fFlags & MM_RAM_FLAGS_RESERVED) || !pvRam);*/
2060 Assert(!(fFlags & ~0xfff));
2061 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
2062 Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
2063 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2 | MM_RAM_FLAGS_DYNAMIC_ALLOC)));
2064 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2065 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2066 if (GCPhysLast < GCPhys)
2067 {
2068 AssertMsgFailed(("The range wraps! GCPhys=%RGp cb=%#x\n", GCPhys, cb));
2069 return VERR_INVALID_PARAMETER;
2070 }
2071
2072 /*
2073 * Find range location and check for conflicts.
2074 */
2075 PPGMRAMRANGE pPrev = NULL;
2076 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
2077 while (pCur)
2078 {
2079 if (GCPhys <= pCur->GCPhysLast && GCPhysLast >= pCur->GCPhys)
2080 {
2081 AssertMsgFailed(("Conflict! This cannot happen!\n"));
2082 return VERR_PGM_RAM_CONFLICT;
2083 }
2084 if (GCPhysLast < pCur->GCPhys)
2085 break;
2086
2087 /* next */
2088 pPrev = pCur;
2089 pCur = pCur->pNextR3;
2090 }
2091
2092 /*
2093 * Allocate RAM range.
2094 * Small ranges are allocated from the heap, big ones have separate mappings.
2095 */
2096 size_t cbRam = RT_OFFSETOF(PGMRAMRANGE, aPages[cb >> PAGE_SHIFT]);
2097 PPGMRAMRANGE pNew;
2098 int rc = VERR_NO_MEMORY;
2099 if (cbRam > PAGE_SIZE / 2)
2100 { /* large */
2101 cbRam = RT_ALIGN_Z(cbRam, PAGE_SIZE);
2102 rc = MMR3HyperAllocOnceNoRel(pVM, cbRam, PAGE_SIZE, MM_TAG_PGM_PHYS, (void **)&pNew);
2103 AssertMsgRC(rc, ("MMR3HyperAllocOnceNoRel(,%#x,,) -> %Rrc\n", cbRam, rc));
2104 }
2105 else
2106 { /* small */
2107 rc = MMHyperAlloc(pVM, cbRam, 16, MM_TAG_PGM, (void **)&pNew);
2108 AssertMsgRC(rc, ("MMHyperAlloc(,%#x,,,) -> %Rrc\n", cbRam, rc));
2109 }
2110 if (RT_SUCCESS(rc))
2111 {
2112 /*
2113 * Initialize the range.
2114 */
2115 pNew->pvR3 = pvRam;
2116 pNew->GCPhys = GCPhys;
2117 pNew->GCPhysLast = GCPhysLast;
2118 pNew->cb = cb;
2119 pNew->fFlags = fFlags;
2120 pNew->paChunkR3Ptrs = NULL;
2121
2122 unsigned iPage = (unsigned)(cb >> PAGE_SHIFT);
2123 if (paPages)
2124 {
2125 while (iPage-- > 0)
2126 {
2127 PGM_PAGE_INIT(&pNew->aPages[iPage], paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
2128 fFlags & MM_RAM_FLAGS_MMIO2 ? PGMPAGETYPE_MMIO2 : PGMPAGETYPE_RAM,
2129 PGM_PAGE_STATE_ALLOCATED);
2130 pNew->aPages[iPage].HCPhys |= fFlags; /** @todo PAGE FLAGS*/
2131 }
2132 }
2133 else if (fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2134 {
2135 /* Allocate memory for chunk to HC ptr lookup array. */
2136 rc = MMHyperAlloc(pVM, (cb >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(void *), 16, MM_TAG_PGM, (void **)&pNew->paChunkR3Ptrs);
2137 AssertMsgReturn(rc == VINF_SUCCESS, ("MMHyperAlloc(,%#x,,,) -> %Rrc\n", cbRam, cb), rc);
2138
2139 /* Physical memory will be allocated on demand. */
2140 while (iPage-- > 0)
2141 {
2142 PGM_PAGE_INIT(&pNew->aPages[iPage], 0, NIL_GMM_PAGEID, PGMPAGETYPE_RAM, PGM_PAGE_STATE_ZERO);
2143 pNew->aPages[iPage].HCPhys = fFlags; /** @todo PAGE FLAGS */
2144 }
2145 }
2146 else
2147 {
2148 Assert(fFlags == (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO));
2149 RTHCPHYS HCPhysDummyPage = MMR3PageDummyHCPhys(pVM);
2150 while (iPage-- > 0)
2151 {
2152 PGM_PAGE_INIT(&pNew->aPages[iPage], HCPhysDummyPage, NIL_GMM_PAGEID, PGMPAGETYPE_MMIO, PGM_PAGE_STATE_ZERO);
2153 pNew->aPages[iPage].HCPhys |= fFlags; /** @todo PAGE FLAGS*/
2154 }
2155 }
2156
2157 /*
2158 * Insert the new RAM range.
2159 */
2160 pgmLock(pVM);
2161 pNew->pNextR3 = pCur;
2162 pNew->pNextR0 = pCur ? MMHyperCCToR0(pVM, pCur) : NIL_RTR0PTR;
2163 pNew->pNextRC = pCur ? MMHyperCCToRC(pVM, pCur) : NIL_RTRCPTR;
2164 if (pPrev)
2165 {
2166 pPrev->pNextR3 = pNew;
2167 pPrev->pNextR0 = MMHyperCCToR0(pVM, pNew);
2168 pPrev->pNextRC = MMHyperCCToRC(pVM, pNew);
2169 }
2170 else
2171 {
2172 pVM->pgm.s.pRamRangesR3 = pNew;
2173 pVM->pgm.s.pRamRangesR0 = MMHyperCCToR0(pVM, pNew);
2174 pVM->pgm.s.pRamRangesRC = MMHyperCCToRC(pVM, pNew);
2175 }
2176 pgmUnlock(pVM);
2177 }
2178 return rc;
2179}
2180
2181
2182/**
2183 * Register a chunk of a the physical memory range with PGM. MM is responsible
2184 * for the toplevel things - allocation and locking - while PGM is taking
2185 * care of all the details and implements the physical address space virtualization.
2186 *
2187 *
2188 * @returns VBox status.
2189 * @param pVM The VM handle.
2190 * @param pvRam HC virtual address of the RAM range. (page aligned)
2191 * @param GCPhys GC physical address of the RAM range. (page aligned)
2192 * @param cb Size of the RAM range. (page aligned)
2193 * @param fFlags Flags, MM_RAM_*.
2194 * @param paPages Pointer an array of physical page descriptors.
2195 * @param pszDesc Description string.
2196 */
2197VMMR3DECL(int) PGMR3PhysRegisterChunk(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc)
2198{
2199 NOREF(pszDesc);
2200
2201 /*
2202 * Validate input.
2203 * (Not so important because callers are only MMR3PhysRegister()
2204 * and PGMR3HandlerPhysicalRegisterEx(), but anyway...)
2205 */
2206 Log(("PGMR3PhysRegisterChunk %08X %x bytes flags %x %s\n", GCPhys, cb, fFlags, pszDesc));
2207
2208 Assert(paPages);
2209 Assert(pvRam);
2210 Assert(!(fFlags & ~0xfff));
2211 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
2212 Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
2213 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2 | MM_RAM_FLAGS_DYNAMIC_ALLOC)));
2214 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2215 Assert(VM_IS_EMT(pVM));
2216 Assert(!(GCPhys & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2217 Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
2218
2219 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2220 if (GCPhysLast < GCPhys)
2221 {
2222 AssertMsgFailed(("The range wraps! GCPhys=%RGp cb=%#x\n", GCPhys, cb));
2223 return VERR_INVALID_PARAMETER;
2224 }
2225
2226 /*
2227 * Find existing range location.
2228 */
2229 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2230 while (pRam)
2231 {
2232 RTGCPHYS off = GCPhys - pRam->GCPhys;
2233 if ( off < pRam->cb
2234 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
2235 break;
2236
2237 pRam = pRam->CTX_SUFF(pNext);
2238 }
2239 AssertReturn(pRam, VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS);
2240
2241 unsigned off = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2242 unsigned iPage = (unsigned)(cb >> PAGE_SHIFT);
2243 if (paPages)
2244 {
2245 while (iPage-- > 0)
2246 pRam->aPages[off + iPage].HCPhys = (paPages[iPage].Phys & X86_PTE_PAE_PG_MASK) | fFlags; /** @todo PAGE FLAGS */
2247 }
2248 off >>= (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
2249 pRam->paChunkR3Ptrs[off] = (uintptr_t)pvRam;
2250
2251 /* Notify the recompiler. */
2252 REMR3NotifyPhysRamChunkRegister(pVM, GCPhys, PGM_DYNAMIC_CHUNK_SIZE, (RTHCUINTPTR)pvRam, fFlags);
2253
2254 return VINF_SUCCESS;
2255}
2256
2257
2258/**
2259 * Allocate missing physical pages for an existing guest RAM range.
2260 *
2261 * @returns VBox status.
2262 * @param pVM The VM handle.
2263 * @param GCPhys GC physical address of the RAM range. (page aligned)
2264 */
2265VMMR3DECL(int) PGM3PhysGrowRange(PVM pVM, PCRTGCPHYS pGCPhys)
2266{
2267 RTGCPHYS GCPhys = *pGCPhys;
2268
2269 /*
2270 * Walk range list.
2271 */
2272 pgmLock(pVM);
2273
2274 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2275 while (pRam)
2276 {
2277 RTGCPHYS off = GCPhys - pRam->GCPhys;
2278 if ( off < pRam->cb
2279 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
2280 {
2281 bool fRangeExists = false;
2282 unsigned off = (GCPhys - pRam->GCPhys) >> PGM_DYNAMIC_CHUNK_SHIFT;
2283
2284 /* Note: A request made from another thread may end up in EMT after somebody else has already allocated the range. */
2285 if (pRam->paChunkR3Ptrs[off])
2286 fRangeExists = true;
2287
2288 pgmUnlock(pVM);
2289 if (fRangeExists)
2290 return VINF_SUCCESS;
2291 return pgmr3PhysGrowRange(pVM, GCPhys);
2292 }
2293
2294 pRam = pRam->CTX_SUFF(pNext);
2295 }
2296 pgmUnlock(pVM);
2297 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2298}
2299
2300
2301/**
2302 * Allocate missing physical pages for an existing guest RAM range.
2303 *
2304 * @returns VBox status.
2305 * @param pVM The VM handle.
2306 * @param pRamRange RAM range
2307 * @param GCPhys GC physical address of the RAM range. (page aligned)
2308 */
2309int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys)
2310{
2311 void *pvRam;
2312 int rc;
2313
2314 /* We must execute this function in the EMT thread, otherwise we'll run into problems. */
2315 if (!VM_IS_EMT(pVM))
2316 {
2317 PVMREQ pReq;
2318 const RTGCPHYS GCPhysParam = GCPhys;
2319
2320 AssertMsg(!PDMCritSectIsOwner(&pVM->pgm.s.CritSect), ("We own the PGM lock -> deadlock danger!!\n"));
2321
2322 rc = VMR3ReqCall(pVM, VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT, (PFNRT)PGM3PhysGrowRange, 2, pVM, &GCPhysParam);
2323 if (RT_SUCCESS(rc))
2324 {
2325 rc = pReq->iStatus;
2326 VMR3ReqFree(pReq);
2327 }
2328 return rc;
2329 }
2330
2331 /* Round down to chunk boundary */
2332 GCPhys = GCPhys & PGM_DYNAMIC_CHUNK_BASE_MASK;
2333
2334 STAM_COUNTER_INC(&pVM->pgm.s.StatR3DynRamGrow);
2335 STAM_COUNTER_ADD(&pVM->pgm.s.StatR3DynRamTotal, PGM_DYNAMIC_CHUNK_SIZE/(1024*1024));
2336
2337 Log(("pgmr3PhysGrowRange: allocate chunk of size 0x%X at %RGp\n", PGM_DYNAMIC_CHUNK_SIZE, GCPhys));
2338
2339 unsigned cPages = PGM_DYNAMIC_CHUNK_SIZE >> PAGE_SHIFT;
2340
2341 for (;;)
2342 {
2343 rc = SUPPageAlloc(cPages, &pvRam);
2344 if (RT_SUCCESS(rc))
2345 {
2346 rc = MMR3PhysRegisterEx(pVM, pvRam, GCPhys, PGM_DYNAMIC_CHUNK_SIZE, 0, MM_PHYS_TYPE_DYNALLOC_CHUNK, "Main Memory");
2347 if (RT_SUCCESS(rc))
2348 return rc;
2349
2350 SUPPageFree(pvRam, cPages);
2351 }
2352
2353 VMSTATE enmVMState = VMR3GetState(pVM);
2354 if (enmVMState != VMSTATE_RUNNING)
2355 {
2356 AssertMsgFailed(("Out of memory while trying to allocate a guest RAM chunk at %RGp!\n", GCPhys));
2357 LogRel(("PGM: Out of memory while trying to allocate a guest RAM chunk at %RGp (VMstate=%s)!\n", GCPhys, VMR3GetStateName(enmVMState)));
2358 return rc;
2359 }
2360
2361 LogRel(("pgmr3PhysGrowRange: out of memory. pause until the user resumes execution.\n"));
2362
2363 /* Pause first, then inform Main. */
2364 rc = VMR3SuspendNoSave(pVM);
2365 AssertRC(rc);
2366
2367 VMSetRuntimeError(pVM, false, "HostMemoryLow", "Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM");
2368
2369 /* Wait for resume event; will only return in that case. If the VM is stopped, the EMT thread will be destroyed. */
2370 rc = VMR3WaitForResume(pVM);
2371
2372 /* Retry */
2373 LogRel(("pgmr3PhysGrowRange: VM execution resumed -> retry.\n"));
2374 }
2375}
2376
2377
2378/**
2379 * Interface MMR3RomRegister() and MMR3PhysReserve calls to update the
2380 * flags of existing RAM ranges.
2381 *
2382 * @returns VBox status.
2383 * @param pVM The VM handle.
2384 * @param GCPhys GC physical address of the RAM range. (page aligned)
2385 * @param cb Size of the RAM range. (page aligned)
2386 * @param fFlags The Or flags, MM_RAM_* \#defines.
2387 * @param fMask The and mask for the flags.
2388 */
2389VMMR3DECL(int) PGMR3PhysSetFlags(PVM pVM, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, unsigned fMask)
2390{
2391 Log(("PGMR3PhysSetFlags %08X %x %x %x\n", GCPhys, cb, fFlags, fMask));
2392
2393 /*
2394 * Validate input.
2395 * (Not so important because caller is always MMR3RomRegister() and MMR3PhysReserve(), but anyway...)
2396 */
2397 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2)));
2398 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
2399 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2400 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2401 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2402
2403 /*
2404 * Lookup the range.
2405 */
2406 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2407 while (pRam && GCPhys > pRam->GCPhysLast)
2408 pRam = pRam->CTX_SUFF(pNext);
2409 if ( !pRam
2410 || GCPhys > pRam->GCPhysLast
2411 || GCPhysLast < pRam->GCPhys)
2412 {
2413 AssertMsgFailed(("No RAM range for %RGp-%RGp\n", GCPhys, GCPhysLast));
2414 return VERR_INVALID_PARAMETER;
2415 }
2416
2417 /*
2418 * Update the requested flags.
2419 */
2420 RTHCPHYS fFullMask = ~(RTHCPHYS)(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2)
2421 | fMask;
2422 unsigned iPageEnd = (GCPhysLast - pRam->GCPhys + 1) >> PAGE_SHIFT;
2423 unsigned iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2424 for ( ; iPage < iPageEnd; iPage++)
2425 pRam->aPages[iPage].HCPhys = (pRam->aPages[iPage].HCPhys & fFullMask) | fFlags; /** @todo PAGE FLAGS */
2426
2427 return VINF_SUCCESS;
2428}
2429
2430#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2431
2432/**
2433 * Sets the Address Gate 20 state.
2434 *
2435 * @param pVM VM handle.
2436 * @param fEnable True if the gate should be enabled.
2437 * False if the gate should be disabled.
2438 */
2439VMMDECL(void) PGMR3PhysSetA20(PVM pVM, bool fEnable)
2440{
2441 LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVM->pgm.s.fA20Enabled));
2442 if (pVM->pgm.s.fA20Enabled != (RTUINT)fEnable)
2443 {
2444 pVM->pgm.s.fA20Enabled = fEnable;
2445 pVM->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2446 REMR3A20Set(pVM, fEnable);
2447 /** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2448 }
2449}
2450
2451
2452/**
2453 * Tree enumeration callback for dealing with age rollover.
2454 * It will perform a simple compression of the current age.
2455 */
2456static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2457{
2458 /* Age compression - ASSUMES iNow == 4. */
2459 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2460 if (pChunk->iAge >= UINT32_C(0xffffff00))
2461 pChunk->iAge = 3;
2462 else if (pChunk->iAge >= UINT32_C(0xfffff000))
2463 pChunk->iAge = 2;
2464 else if (pChunk->iAge)
2465 pChunk->iAge = 1;
2466 else /* iAge = 0 */
2467 pChunk->iAge = 4;
2468
2469 /* reinsert */
2470 PVM pVM = (PVM)pvUser;
2471 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2472 pChunk->AgeCore.Key = pChunk->iAge;
2473 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2474 return 0;
2475}
2476
2477
2478/**
2479 * Tree enumeration callback that updates the chunks that have
2480 * been used since the last
2481 */
2482static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
2483{
2484 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2485 if (!pChunk->iAge)
2486 {
2487 PVM pVM = (PVM)pvUser;
2488 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2489 pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
2490 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2491 }
2492
2493 return 0;
2494}
2495
2496
2497/**
2498 * Performs ageing of the ring-3 chunk mappings.
2499 *
2500 * @param pVM The VM handle.
2501 */
2502VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
2503{
2504 pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
2505 pVM->pgm.s.ChunkR3Map.iNow++;
2506 if (pVM->pgm.s.ChunkR3Map.iNow == 0)
2507 {
2508 pVM->pgm.s.ChunkR3Map.iNow = 4;
2509 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
2510 }
2511 else
2512 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingCallback, pVM);
2513}
2514
2515
2516/**
2517 * The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
2518 */
2519typedef struct PGMR3PHYSCHUNKUNMAPCB
2520{
2521 PVM pVM; /**< The VM handle. */
2522 PPGMCHUNKR3MAP pChunk; /**< The chunk to unmap. */
2523} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
2524
2525
2526/**
2527 * Callback used to find the mapping that's been unused for
2528 * the longest time.
2529 */
2530static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
2531{
2532 do
2533 {
2534 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
2535 if ( pChunk->iAge
2536 && !pChunk->cRefs)
2537 {
2538 /*
2539 * Check that it's not in any of the TLBs.
2540 */
2541 PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
2542 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2543 if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
2544 {
2545 pChunk = NULL;
2546 break;
2547 }
2548 if (pChunk)
2549 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
2550 if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
2551 {
2552 pChunk = NULL;
2553 break;
2554 }
2555 if (pChunk)
2556 {
2557 ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
2558 return 1; /* done */
2559 }
2560 }
2561
2562 /* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
2563 pNode = pNode->pList;
2564 } while (pNode);
2565 return 0;
2566}
2567
2568
2569/**
2570 * Finds a good candidate for unmapping when the ring-3 mapping cache is full.
2571 *
2572 * The candidate will not be part of any TLBs, so no need to flush
2573 * anything afterwards.
2574 *
2575 * @returns Chunk id.
2576 * @param pVM The VM handle.
2577 */
2578static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
2579{
2580 /*
2581 * Do tree ageing first?
2582 */
2583 if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
2584 PGMR3PhysChunkAgeing(pVM);
2585
2586 /*
2587 * Enumerate the age tree starting with the left most node.
2588 */
2589 PGMR3PHYSCHUNKUNMAPCB Args;
2590 Args.pVM = pVM;
2591 Args.pChunk = NULL;
2592 if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /*fFromLeft*/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
2593 return Args.pChunk->Core.Key;
2594 return INT32_MAX;
2595}
2596
2597
2598/**
2599 * Maps the given chunk into the ring-3 mapping cache.
2600 *
2601 * This will call ring-0.
2602 *
2603 * @returns VBox status code.
2604 * @param pVM The VM handle.
2605 * @param idChunk The chunk in question.
2606 * @param ppChunk Where to store the chunk tracking structure.
2607 *
2608 * @remarks Called from within the PGM critical section.
2609 */
2610int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
2611{
2612 int rc;
2613 /*
2614 * Allocate a new tracking structure first.
2615 */
2616#if 0 /* for later when we've got a separate mapping method for ring-0. */
2617 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
2618 AssertReturn(pChunk, VERR_NO_MEMORY);
2619#else
2620 PPGMCHUNKR3MAP pChunk;
2621 rc = MMHyperAlloc(pVM, sizeof(*pChunk), 0, MM_TAG_PGM_CHUNK_MAPPING, (void **)&pChunk);
2622 AssertRCReturn(rc, rc);
2623#endif
2624 pChunk->Core.Key = idChunk;
2625 pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
2626 pChunk->iAge = 0;
2627 pChunk->cRefs = 0;
2628 pChunk->cPermRefs = 0;
2629 pChunk->pv = NULL;
2630
2631 /*
2632 * Request the ring-0 part to map the chunk in question and if
2633 * necessary unmap another one to make space in the mapping cache.
2634 */
2635 GMMMAPUNMAPCHUNKREQ Req;
2636 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2637 Req.Hdr.cbReq = sizeof(Req);
2638 Req.pvR3 = NULL;
2639 Req.idChunkMap = idChunk;
2640 Req.idChunkUnmap = NIL_GMM_CHUNKID;
2641 if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
2642 Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
2643 rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
2644 if (RT_SUCCESS(rc))
2645 {
2646 /*
2647 * Update the tree.
2648 */
2649 /* insert the new one. */
2650 AssertPtr(Req.pvR3);
2651 pChunk->pv = Req.pvR3;
2652 bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
2653 AssertRelease(fRc);
2654 pVM->pgm.s.ChunkR3Map.c++;
2655
2656 fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2657 AssertRelease(fRc);
2658
2659 /* remove the unmapped one. */
2660 if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
2661 {
2662 PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
2663 AssertRelease(pUnmappedChunk);
2664 pUnmappedChunk->pv = NULL;
2665 pUnmappedChunk->Core.Key = UINT32_MAX;
2666#if 0 /* for later when we've got a separate mapping method for ring-0. */
2667 MMR3HeapFree(pUnmappedChunk);
2668#else
2669 MMHyperFree(pVM, pUnmappedChunk);
2670#endif
2671 pVM->pgm.s.ChunkR3Map.c--;
2672 }
2673 }
2674 else
2675 {
2676 AssertRC(rc);
2677#if 0 /* for later when we've got a separate mapping method for ring-0. */
2678 MMR3HeapFree(pChunk);
2679#else
2680 MMHyperFree(pVM, pChunk);
2681#endif
2682 pChunk = NULL;
2683 }
2684
2685 *ppChunk = pChunk;
2686 return rc;
2687}
2688
2689
2690/**
2691 * For VMMCALLHOST_PGM_MAP_CHUNK, considered internal.
2692 *
2693 * @returns see pgmR3PhysChunkMap.
2694 * @param pVM The VM handle.
2695 * @param idChunk The chunk to map.
2696 */
2697VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
2698{
2699 PPGMCHUNKR3MAP pChunk;
2700 return pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
2701}
2702
2703
2704/**
2705 * Invalidates the TLB for the ring-3 mapping cache.
2706 *
2707 * @param pVM The VM handle.
2708 */
2709VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
2710{
2711 pgmLock(pVM);
2712 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2713 {
2714 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
2715 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
2716 }
2717 pgmUnlock(pVM);
2718}
2719
2720
2721/**
2722 * Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES.
2723 *
2724 * @returns The following VBox status codes.
2725 * @retval VINF_SUCCESS on success. FF cleared.
2726 * @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in this case.
2727 *
2728 * @param pVM The VM handle.
2729 */
2730VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
2731{
2732 pgmLock(pVM);
2733
2734 /*
2735 * Allocate more pages, noting down the index of the first new page.
2736 */
2737 uint32_t iClear = pVM->pgm.s.cHandyPages;
2738 AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
2739 Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
2740 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
2741 if (rc == VERR_GMM_SEED_ME)
2742 {
2743 void *pvChunk;
2744 rc = SUPPageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
2745 if (RT_SUCCESS(rc))
2746 rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
2747 if (RT_SUCCESS(rc))
2748 rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
2749 }
2750
2751 /*
2752 * Clear the pages.
2753 */
2754 if (RT_SUCCESS(rc))
2755 {
2756 while (iClear < pVM->pgm.s.cHandyPages)
2757 {
2758 PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
2759 void *pv;
2760 rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
2761 AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
2762 ASMMemZeroPage(pv);
2763 iClear++;
2764 }
2765
2766 VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
2767 }
2768 else
2769 {
2770 LogRel(("PGM: Failed to procure handy pages, rc=%Rrc cHandyPages=%u\n",
2771 rc, pVM->pgm.s.cHandyPages));
2772 rc = VERR_EM_NO_MEMORY;
2773 //rc = VINF_EM_NO_MEMORY;
2774 //VM_FF_SET(pVM, VM_FF_PGM_WE_ARE_SCREWED?);
2775 }
2776
2777/** @todo Do proper VERR_EM_NO_MEMORY reporting. */
2778 AssertMsg( pVM->pgm.s.cHandyPages == RT_ELEMENTS(pVM->pgm.s.aHandyPages)
2779 || rc != VINF_SUCCESS, ("%d rc=%Rrc\n", pVM->pgm.s.cHandyPages, rc));
2780 pgmUnlock(pVM);
2781 Assert(rc == VINF_SUCCESS || rc == VINF_EM_NO_MEMORY || rc == VERR_EM_NO_MEMORY);
2782 return rc;
2783}
2784
2785
2786/**
2787 * Frees the specified RAM page and replaces it with the ZERO page.
2788 *
2789 * This is used by ballooning, remapping MMIO2 and RAM reset.
2790 *
2791 * @param pVM Pointer to the shared VM structure.
2792 * @param pReq Pointer to the request.
2793 * @param pPage Pointer to the page structure.
2794 * @param GCPhys The guest physical address of the page, if applicable.
2795 *
2796 * @remarks The caller must own the PGM lock.
2797 */
2798static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
2799{
2800 /*
2801 * Assert sanity.
2802 */
2803 Assert(PDMCritSectIsOwner(&pVM->pgm.s.CritSect));
2804 if (RT_UNLIKELY(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM))
2805 {
2806 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
2807 return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
2808 }
2809
2810 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO)
2811 return VINF_SUCCESS;
2812
2813 const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
2814 if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
2815 || idPage > GMM_PAGEID_LAST
2816 || PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
2817 {
2818 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
2819 return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
2820 }
2821
2822 /*
2823 * pPage = ZERO page.
2824 */
2825 PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
2826 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
2827 PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
2828
2829 /*
2830 * Make sure it's not in the handy page array.
2831 */
2832 uint32_t i = pVM->pgm.s.cHandyPages;
2833 while (i < RT_ELEMENTS(pVM->pgm.s.aHandyPages))
2834 {
2835 if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
2836 {
2837 pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
2838 break;
2839 }
2840 if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
2841 {
2842 pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
2843 break;
2844 }
2845 i++;
2846 }
2847
2848 /*
2849 * Push it onto the page array.
2850 */
2851 uint32_t iPage = *pcPendingPages;
2852 Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
2853 *pcPendingPages += 1;
2854
2855 pReq->aPages[iPage].idPage = idPage;
2856
2857 if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
2858 return VINF_SUCCESS;
2859
2860 /*
2861 * Flush the pages.
2862 */
2863 int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
2864 if (RT_SUCCESS(rc))
2865 {
2866 GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2867 *pcPendingPages = 0;
2868 }
2869 return rc;
2870}
2871
2872
2873/**
2874 * Converts a GC physical address to a HC ring-3 pointer, with some
2875 * additional checks.
2876 *
2877 * @returns VBox status code.
2878 * @retval VINF_SUCCESS on success.
2879 * @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
2880 * access handler of some kind.
2881 * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
2882 * accesses or is odd in any way.
2883 * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
2884 *
2885 * @param pVM The VM handle.
2886 * @param GCPhys The GC physical address to convert.
2887 * @param fWritable Whether write access is required.
2888 * @param ppv Where to store the pointer corresponding to GCPhys on
2889 * success.
2890 */
2891VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
2892{
2893 pgmLock(pVM);
2894
2895 PPGMRAMRANGE pRam;
2896 PPGMPAGE pPage;
2897 int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
2898 if (RT_SUCCESS(rc))
2899 {
2900#ifdef VBOX_WITH_NEW_PHYS_CODE
2901 if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
2902 rc = VINF_SUCCESS;
2903 else
2904 {
2905 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
2906 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
2907 else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2908 {
2909 /** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
2910 * in -norawr0 mode. */
2911 if (fWritable)
2912 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
2913 }
2914 else
2915 {
2916 /* Temporariliy disabled phycial handler(s), since the recompiler
2917 doesn't get notified when it's reset we'll have to pretend its
2918 operating normally. */
2919 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
2920 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
2921 else
2922 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
2923 }
2924 }
2925 if (RT_SUCCESS(rc))
2926 {
2927 int rc2;
2928
2929 /* Make sure what we return is writable. */
2930 if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
2931 switch (PGM_PAGE_GET_STATE(pPage))
2932 {
2933 case PGM_PAGE_STATE_ALLOCATED:
2934 break;
2935 case PGM_PAGE_STATE_ZERO:
2936 case PGM_PAGE_STATE_SHARED:
2937 case PGM_PAGE_STATE_WRITE_MONITORED:
2938 rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
2939 AssertLogRelRCReturn(rc2, rc2);
2940 break;
2941 }
2942
2943 /* Get a ring-3 mapping of the address. */
2944 PPGMPAGER3MAPTLBE pTlbe;
2945 rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
2946 AssertLogRelRCReturn(rc2, rc2);
2947 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
2948 /** @todo mapping/locking hell; this isn't horribly efficient since
2949 * pgmPhysPageLoadIntoTlb will repeate the lookup we've done here. */
2950
2951 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] *ppv=%p\n", GCPhys, rc, pPage, *ppv));
2952 }
2953 else
2954 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
2955
2956 /* else: handler catching all access, no pointer returned. */
2957
2958#else
2959 if (0)
2960 /* nothing */;
2961 else if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
2962 {
2963 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
2964 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
2965 else if (fWritable && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2966 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
2967 else
2968 {
2969 /* Temporariliy disabled phycial handler(s), since the recompiler
2970 doesn't get notified when it's reset we'll have to pretend its
2971 operating normally. */
2972 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
2973 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
2974 else
2975 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
2976 }
2977 }
2978 else
2979 rc = VINF_SUCCESS;
2980 if (RT_SUCCESS(rc))
2981 {
2982 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2983 {
2984 AssertMsg(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM, ("GCPhys=%RGp type=%d\n", GCPhys, PGM_PAGE_GET_TYPE(pPage)));
2985 RTGCPHYS off = GCPhys - pRam->GCPhys;
2986 unsigned iChunk = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
2987 *ppv = (void *)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2988 }
2989 else if (RT_LIKELY(pRam->pvR3))
2990 {
2991 AssertMsg(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2, ("GCPhys=%RGp type=%d\n", GCPhys, PGM_PAGE_GET_TYPE(pPage)));
2992 RTGCPHYS off = GCPhys - pRam->GCPhys;
2993 *ppv = (uint8_t *)pRam->pvR3 + off;
2994 }
2995 else
2996 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
2997 }
2998#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2999 }
3000 else
3001 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3002
3003 pgmUnlock(pVM);
3004 return rc;
3005}
3006
3007
3008
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