VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 19300

Last change on this file since 19300 was 19300, checked in by vboxsync, 16 years ago

VMReq,*: Replaced VMREQDEST with VMCPUID because it's a pain to have to cast CPU IDs all the time.
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File size: 115.8 KB
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1/* $Id: PGMPhys.cpp 19300 2009-05-01 18:06:59Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM_PHYS
27#include <VBox/pgm.h>
28#include <VBox/iom.h>
29#include <VBox/mm.h>
30#include <VBox/stam.h>
31#include <VBox/rem.h>
32#include <VBox/pdmdev.h>
33#include "PGMInternal.h"
34#include <VBox/vm.h>
35#include <VBox/sup.h>
36#include <VBox/param.h>
37#include <VBox/err.h>
38#include <VBox/log.h>
39#include <iprt/assert.h>
40#include <iprt/alloc.h>
41#include <iprt/asm.h>
42#include <iprt/thread.h>
43#include <iprt/string.h>
44
45
46/*******************************************************************************
47* Defined Constants And Macros *
48*******************************************************************************/
49/** The number of pages to free in one batch. */
50#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
51
52
53/*******************************************************************************
54* Internal Functions *
55*******************************************************************************/
56static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
57static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
58
59
60/*
61 * PGMR3PhysReadU8-64
62 * PGMR3PhysWriteU8-64
63 */
64#define PGMPHYSFN_READNAME PGMR3PhysReadU8
65#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
66#define PGMPHYS_DATASIZE 1
67#define PGMPHYS_DATATYPE uint8_t
68#include "PGMPhysRWTmpl.h"
69
70#define PGMPHYSFN_READNAME PGMR3PhysReadU16
71#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
72#define PGMPHYS_DATASIZE 2
73#define PGMPHYS_DATATYPE uint16_t
74#include "PGMPhysRWTmpl.h"
75
76#define PGMPHYSFN_READNAME PGMR3PhysReadU32
77#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
78#define PGMPHYS_DATASIZE 4
79#define PGMPHYS_DATATYPE uint32_t
80#include "PGMPhysRWTmpl.h"
81
82#define PGMPHYSFN_READNAME PGMR3PhysReadU64
83#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
84#define PGMPHYS_DATASIZE 8
85#define PGMPHYS_DATATYPE uint64_t
86#include "PGMPhysRWTmpl.h"
87
88
89/**
90 * EMT worker for PGMR3PhysReadExternal.
91 */
92static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
93{
94 PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
95 return VINF_SUCCESS;
96}
97
98
99/**
100 * Write to physical memory, external users.
101 *
102 * @returns VBox status code.
103 * @retval VINF_SUCCESS.
104 *
105 * @param pVM VM Handle.
106 * @param GCPhys Physical address to write to.
107 * @param pvBuf What to write.
108 * @param cbWrite How many bytes to write.
109 *
110 * @thread Any but EMTs.
111 */
112VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
113{
114 VM_ASSERT_OTHER_THREAD(pVM);
115
116 AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
117 LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
118
119 pgmLock(pVM);
120
121 /*
122 * Copy loop on ram ranges.
123 */
124 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
125 for (;;)
126 {
127 /* Find range. */
128 while (pRam && GCPhys > pRam->GCPhysLast)
129 pRam = pRam->CTX_SUFF(pNext);
130 /* Inside range or not? */
131 if (pRam && GCPhys >= pRam->GCPhys)
132 {
133 /*
134 * Must work our way thru this page by page.
135 */
136 RTGCPHYS off = GCPhys - pRam->GCPhys;
137 while (off < pRam->cb)
138 {
139 unsigned iPage = off >> PAGE_SHIFT;
140 PPGMPAGE pPage = &pRam->aPages[iPage];
141
142 /*
143 * If the page has an ALL access handler, we'll have to
144 * delegate the job to EMT.
145 */
146 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
147 {
148 pgmUnlock(pVM);
149
150 PVMREQ pReq = NULL;
151 int rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
152 (PFNRT)pgmR3PhysReadExternalEMT, 4, pVM, &GCPhys, pvBuf, cbRead);
153 if (RT_SUCCESS(rc))
154 {
155 rc = pReq->iStatus;
156 VMR3ReqFree(pReq);
157 }
158 return rc;
159 }
160 Assert(!PGM_PAGE_IS_MMIO(pPage));
161
162 /*
163 * Simple stuff, go ahead.
164 */
165 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
166 if (cb > cbRead)
167 cb = cbRead;
168 const void *pvSrc;
169 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
170 if (RT_SUCCESS(rc))
171 memcpy(pvBuf, pvSrc, cb);
172 else
173 {
174 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
175 pRam->GCPhys + off, pPage, rc));
176 memset(pvBuf, 0xff, cb);
177 }
178
179 /* next page */
180 if (cb >= cbRead)
181 {
182 pgmUnlock(pVM);
183 return VINF_SUCCESS;
184 }
185 cbRead -= cb;
186 off += cb;
187 GCPhys += cb;
188 pvBuf = (char *)pvBuf + cb;
189 } /* walk pages in ram range. */
190 }
191 else
192 {
193 LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
194
195 /*
196 * Unassigned address space.
197 */
198 if (!pRam)
199 break;
200 size_t cb = pRam->GCPhys - GCPhys;
201 if (cb >= cbRead)
202 {
203 memset(pvBuf, 0xff, cbRead);
204 break;
205 }
206 memset(pvBuf, 0xff, cb);
207
208 cbRead -= cb;
209 pvBuf = (char *)pvBuf + cb;
210 GCPhys += cb;
211 }
212 } /* Ram range walk */
213
214 pgmUnlock(pVM);
215
216 return VINF_SUCCESS;
217}
218
219
220/**
221 * EMT worker for PGMR3PhysWriteExternal.
222 */
223static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
224{
225 /** @todo VERR_EM_NO_MEMORY */
226 PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
227 return VINF_SUCCESS;
228}
229
230
231/**
232 * Write to physical memory, external users.
233 *
234 * @returns VBox status code.
235 * @retval VINF_SUCCESS.
236 * @retval VERR_EM_NO_MEMORY.
237 *
238 * @param pVM VM Handle.
239 * @param GCPhys Physical address to write to.
240 * @param pvBuf What to write.
241 * @param cbWrite How many bytes to write.
242 *
243 * @thread Any but EMTs.
244 */
245VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
246{
247 VM_ASSERT_OTHER_THREAD(pVM);
248
249 AssertMsg(!pVM->pgm.s.fNoMorePhysWrites, ("Calling PGMR3PhysWriteExternal after pgmR3Save()!\n"));
250 AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
251 LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
252
253 pgmLock(pVM);
254
255 /*
256 * Copy loop on ram ranges, stop when we hit something difficult.
257 */
258 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
259 for (;;)
260 {
261 /* Find range. */
262 while (pRam && GCPhys > pRam->GCPhysLast)
263 pRam = pRam->CTX_SUFF(pNext);
264 /* Inside range or not? */
265 if (pRam && GCPhys >= pRam->GCPhys)
266 {
267 /*
268 * Must work our way thru this page by page.
269 */
270 RTGCPTR off = GCPhys - pRam->GCPhys;
271 while (off < pRam->cb)
272 {
273 RTGCPTR iPage = off >> PAGE_SHIFT;
274 PPGMPAGE pPage = &pRam->aPages[iPage];
275
276 /*
277 * It the page is in any way problematic, we have to
278 * do the work on the EMT. Anything that needs to be made
279 * writable or involves access handlers is problematic.
280 */
281 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
282 || PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
283 {
284 pgmUnlock(pVM);
285
286 PVMREQ pReq = NULL;
287 int rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
288 (PFNRT)pgmR3PhysWriteExternalEMT, 4, pVM, &GCPhys, pvBuf, cbWrite);
289 if (RT_SUCCESS(rc))
290 {
291 rc = pReq->iStatus;
292 VMR3ReqFree(pReq);
293 }
294 return rc;
295 }
296 Assert(!PGM_PAGE_IS_MMIO(pPage));
297
298 /*
299 * Simple stuff, go ahead.
300 */
301 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
302 if (cb > cbWrite)
303 cb = cbWrite;
304 void *pvDst;
305 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
306 if (RT_SUCCESS(rc))
307 memcpy(pvDst, pvBuf, cb);
308 else
309 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
310 pRam->GCPhys + off, pPage, rc));
311
312 /* next page */
313 if (cb >= cbWrite)
314 {
315 pgmUnlock(pVM);
316 return VINF_SUCCESS;
317 }
318
319 cbWrite -= cb;
320 off += cb;
321 GCPhys += cb;
322 pvBuf = (const char *)pvBuf + cb;
323 } /* walk pages in ram range */
324 }
325 else
326 {
327 /*
328 * Unassigned address space, skip it.
329 */
330 if (!pRam)
331 break;
332 size_t cb = pRam->GCPhys - GCPhys;
333 if (cb >= cbWrite)
334 break;
335 cbWrite -= cb;
336 pvBuf = (const char *)pvBuf + cb;
337 GCPhys += cb;
338 }
339 } /* Ram range walk */
340
341 pgmUnlock(pVM);
342 return VINF_SUCCESS;
343}
344
345
346/**
347 * VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
348 *
349 * @returns see PGMR3PhysGCPhys2CCPtrExternal
350 * @param pVM The VM handle.
351 * @param pGCPhys Pointer to the guest physical address.
352 * @param ppv Where to store the mapping address.
353 * @param pLock Where to store the lock.
354 */
355static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
356{
357 /*
358 * Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
359 * an access handler after it succeeds.
360 */
361 int rc = pgmLock(pVM);
362 AssertRCReturn(rc, rc);
363
364 rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
365 if (RT_SUCCESS(rc))
366 {
367 PPGMPAGEMAPTLBE pTlbe;
368 int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
369 AssertFatalRC(rc2);
370 PPGMPAGE pPage = pTlbe->pPage;
371#if 1
372 if (PGM_PAGE_IS_MMIO(pPage))
373#else
374 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
375#endif
376 {
377 PGMPhysReleasePageMappingLock(pVM, pLock);
378 rc = VERR_PGM_PHYS_PAGE_RESERVED;
379 }
380 }
381
382 pgmUnlock(pVM);
383 return rc;
384}
385
386
387/**
388 * Requests the mapping of a guest page into ring-3, external threads.
389 *
390 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
391 * release it.
392 *
393 * This API will assume your intention is to write to the page, and will
394 * therefore replace shared and zero pages. If you do not intend to modify the
395 * page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
396 *
397 * @returns VBox status code.
398 * @retval VINF_SUCCESS on success.
399 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
400 * backing or if the page has any active access handlers. The caller
401 * must fall back on using PGMR3PhysWriteExternal.
402 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
403 *
404 * @param pVM The VM handle.
405 * @param GCPhys The guest physical address of the page that should be mapped.
406 * @param ppv Where to store the address corresponding to GCPhys.
407 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
408 *
409 * @remark Avoid calling this API from within critical sections (other than the
410 * PGM one) because of the deadlock risk when we have to delegating the
411 * task to an EMT.
412 * @thread Any.
413 */
414VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
415{
416 AssertPtr(ppv);
417 AssertPtr(pLock);
418
419 int rc = pgmLock(pVM);
420 AssertRCReturn(rc, rc);
421
422 /*
423 * Query the Physical TLB entry for the page (may fail).
424 */
425 PPGMPAGEMAPTLBE pTlbe;
426 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
427 if (RT_SUCCESS(rc))
428 {
429 PPGMPAGE pPage = pTlbe->pPage;
430#if 1
431 if (PGM_PAGE_IS_MMIO(pPage))
432 rc = VERR_PGM_PHYS_PAGE_RESERVED;
433#else
434 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
435 rc = VERR_PGM_PHYS_PAGE_RESERVED;
436#endif
437 else
438 {
439 /*
440 * If the page is shared, the zero page, or being write monitored
441 * it must be converted to an page that's writable if possible.
442 * This has to be done on an EMT.
443 */
444 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
445 {
446 pgmUnlock(pVM);
447
448 PVMREQ pReq = NULL;
449 rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
450 (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4, pVM, &GCPhys, ppv, pLock);
451 if (RT_SUCCESS(rc))
452 {
453 rc = pReq->iStatus;
454 VMR3ReqFree(pReq);
455 }
456 return rc;
457 }
458
459 /*
460 * Now, just perform the locking and calculate the return address.
461 */
462 PPGMPAGEMAP pMap = pTlbe->pMap;
463 pMap->cRefs++;
464#if 0 /** @todo implement locking properly */
465 if (RT_LIKELY(pPage->cLocks != PGM_PAGE_MAX_LOCKS))
466 if (RT_UNLIKELY(++pPage->cLocks == PGM_PAGE_MAX_LOCKS))
467 {
468 AssertMsgFailed(("%RGp is entering permanent locked state!\n", GCPhys));
469 pMap->cRefs++; /* Extra ref to prevent it from going away. */
470 }
471#endif
472 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
473 pLock->pvPage = pPage;
474 pLock->pvMap = pMap;
475 }
476 }
477
478 pgmUnlock(pVM);
479 return rc;
480}
481
482
483/**
484 * Requests the mapping of a guest page into ring-3, external threads.
485 *
486 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
487 * release it.
488 *
489 * @returns VBox status code.
490 * @retval VINF_SUCCESS on success.
491 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
492 * backing or if the page as an active ALL access handler. The caller
493 * must fall back on using PGMPhysRead.
494 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
495 *
496 * @param pVM The VM handle.
497 * @param GCPhys The guest physical address of the page that should be mapped.
498 * @param ppv Where to store the address corresponding to GCPhys.
499 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
500 *
501 * @remark Avoid calling this API from within critical sections (other than
502 * the PGM one) because of the deadlock risk.
503 * @thread Any.
504 */
505VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
506{
507 int rc = pgmLock(pVM);
508 AssertRCReturn(rc, rc);
509
510 /*
511 * Query the Physical TLB entry for the page (may fail).
512 */
513 PPGMPAGEMAPTLBE pTlbe;
514 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
515 if (RT_SUCCESS(rc))
516 {
517 PPGMPAGE pPage = pTlbe->pPage;
518#if 1
519 /* MMIO pages doesn't have any readable backing. */
520 if (PGM_PAGE_IS_MMIO(pPage))
521 rc = VERR_PGM_PHYS_PAGE_RESERVED;
522#else
523 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
524 rc = VERR_PGM_PHYS_PAGE_RESERVED;
525#endif
526 else
527 {
528 /*
529 * Now, just perform the locking and calculate the return address.
530 */
531 PPGMPAGEMAP pMap = pTlbe->pMap;
532 pMap->cRefs++;
533#if 0 /** @todo implement locking properly */
534 if (RT_LIKELY(pPage->cLocks != PGM_PAGE_MAX_LOCKS))
535 if (RT_UNLIKELY(++pPage->cLocks == PGM_PAGE_MAX_LOCKS))
536 {
537 AssertMsgFailed(("%RGp is entering permanent locked state!\n", GCPhys));
538 pMap->cRefs++; /* Extra ref to prevent it from going away. */
539 }
540#endif
541 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
542 pLock->pvPage = pPage;
543 pLock->pvMap = pMap;
544 }
545 }
546
547 pgmUnlock(pVM);
548 return rc;
549}
550
551
552/**
553 * Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
554 *
555 * Called when anything was relocated.
556 *
557 * @param pVM Pointer to the shared VM structure.
558 */
559void pgmR3PhysRelinkRamRanges(PVM pVM)
560{
561 PPGMRAMRANGE pCur;
562
563#ifdef VBOX_STRICT
564 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
565 {
566 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
567 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
568 Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
569 Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
570 Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
571 Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
572 for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
573 Assert( pCur2 == pCur
574 || strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
575 }
576#endif
577
578 pCur = pVM->pgm.s.pRamRangesR3;
579 if (pCur)
580 {
581 pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
582 pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
583
584 for (; pCur->pNextR3; pCur = pCur->pNextR3)
585 {
586 pCur->pNextR0 = pCur->pNextR3->pSelfR0;
587 pCur->pNextRC = pCur->pNextR3->pSelfRC;
588 }
589
590 Assert(pCur->pNextR0 == NIL_RTR0PTR);
591 Assert(pCur->pNextRC == NIL_RTRCPTR);
592 }
593 else
594 {
595 Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
596 Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
597 }
598}
599
600
601/**
602 * Links a new RAM range into the list.
603 *
604 * @param pVM Pointer to the shared VM structure.
605 * @param pNew Pointer to the new list entry.
606 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
607 */
608static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
609{
610 AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
611 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
612 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
613
614 pgmLock(pVM);
615
616 PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
617 pNew->pNextR3 = pRam;
618 pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
619 pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
620
621 if (pPrev)
622 {
623 pPrev->pNextR3 = pNew;
624 pPrev->pNextR0 = pNew->pSelfR0;
625 pPrev->pNextRC = pNew->pSelfRC;
626 }
627 else
628 {
629 pVM->pgm.s.pRamRangesR3 = pNew;
630 pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
631 pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
632 }
633
634 pgmUnlock(pVM);
635}
636
637
638/**
639 * Unlink an existing RAM range from the list.
640 *
641 * @param pVM Pointer to the shared VM structure.
642 * @param pRam Pointer to the new list entry.
643 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
644 */
645static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
646{
647 Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
648 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
649 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
650
651 pgmLock(pVM);
652
653 PPGMRAMRANGE pNext = pRam->pNextR3;
654 if (pPrev)
655 {
656 pPrev->pNextR3 = pNext;
657 pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
658 pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
659 }
660 else
661 {
662 Assert(pVM->pgm.s.pRamRangesR3 == pRam);
663 pVM->pgm.s.pRamRangesR3 = pNext;
664 pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
665 pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
666 }
667
668 pgmUnlock(pVM);
669}
670
671
672/**
673 * Unlink an existing RAM range from the list.
674 *
675 * @param pVM Pointer to the shared VM structure.
676 * @param pRam Pointer to the new list entry.
677 */
678static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
679{
680 pgmLock(pVM);
681
682 /* find prev. */
683 PPGMRAMRANGE pPrev = NULL;
684 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
685 while (pCur != pRam)
686 {
687 pPrev = pCur;
688 pCur = pCur->pNextR3;
689 }
690 AssertFatal(pCur);
691
692 pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
693
694 pgmUnlock(pVM);
695}
696
697
698/**
699 * Frees a range of pages, replacing them with ZERO pages of the specified type.
700 *
701 * @returns VBox status code.
702 * @param pVM The VM handle.
703 * @param pRam The RAM range in which the pages resides.
704 * @param GCPhys The address of the first page.
705 * @param GCPhysLast The address of the last page.
706 * @param uType The page type to replace then with.
707 */
708static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
709{
710 uint32_t cPendingPages = 0;
711 PGMMFREEPAGESREQ pReq;
712 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
713 AssertLogRelRCReturn(rc, rc);
714
715 /* Itegerate the pages. */
716 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
717 uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
718 while (cPagesLeft-- > 0)
719 {
720 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
721 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
722
723 PGM_PAGE_SET_TYPE(pPageDst, uType);
724
725 GCPhys += PAGE_SIZE;
726 pPageDst++;
727 }
728
729 if (cPendingPages)
730 {
731 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
732 AssertLogRelRCReturn(rc, rc);
733 }
734 GMMR3FreePagesCleanup(pReq);
735
736 return rc;
737}
738
739
740/**
741 * PGMR3PhysRegisterRam worker that initializes and links a RAM range.
742 *
743 * @param pVM The VM handle.
744 * @param pNew The new RAM range.
745 * @param GCPhys The address of the RAM range.
746 * @param GCPhysLast The last address of the RAM range.
747 * @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
748 * if in HMA.
749 * @param R0PtrNew Ditto for R0.
750 * @param pszDesc The description.
751 * @param pPrev The previous RAM range (for linking).
752 */
753static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
754 RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
755{
756 /*
757 * Initialize the range.
758 */
759 pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
760 pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
761 pNew->GCPhys = GCPhys;
762 pNew->GCPhysLast = GCPhysLast;
763 pNew->cb = GCPhysLast - GCPhys + 1;
764 pNew->pszDesc = pszDesc;
765 pNew->fFlags = RCPtrNew != NIL_RTR0PTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
766 pNew->pvR3 = NULL;
767
768 uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
769 RTGCPHYS iPage = cPages;
770 while (iPage-- > 0)
771 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
772
773 /* Update the page count stats. */
774 pVM->pgm.s.cZeroPages += cPages;
775 pVM->pgm.s.cAllPages += cPages;
776
777 /*
778 * Link it.
779 */
780 pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
781}
782
783
784/**
785 * Relocate a floating RAM range.
786 *
787 * @copydoc FNPGMRELOCATE.
788 */
789static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
790{
791 PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
792 Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
793 Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
794
795 switch (enmMode)
796 {
797 case PGMRELOCATECALL_SUGGEST:
798 return true;
799 case PGMRELOCATECALL_RELOCATE:
800 {
801 /* Update myself and then relink all the ranges. */
802 pgmLock(pVM);
803 pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
804 pgmR3PhysRelinkRamRanges(pVM);
805 pgmUnlock(pVM);
806 return true;
807 }
808
809 default:
810 AssertFailedReturn(false);
811 }
812}
813
814
815/**
816 * PGMR3PhysRegisterRam worker that registers a high chunk.
817 *
818 * @returns VBox status code.
819 * @param pVM The VM handle.
820 * @param GCPhys The address of the RAM.
821 * @param cRamPages The number of RAM pages to register.
822 * @param cbChunk The size of the PGMRAMRANGE guest mapping.
823 * @param iChunk The chunk number.
824 * @param pszDesc The RAM range description.
825 * @param ppPrev Previous RAM range pointer. In/Out.
826 */
827static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
828 uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
829 PPGMRAMRANGE *ppPrev)
830{
831 const char *pszDescChunk = iChunk == 0
832 ? pszDesc
833 : MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
834 AssertReturn(pszDescChunk, VERR_NO_MEMORY);
835
836 /*
837 * Allocate memory for the new chunk.
838 */
839 size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
840 PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
841 AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
842 RTR0PTR R0PtrChunk = NIL_RTR0PTR;
843 void *pvChunk = NULL;
844 int rc = SUPR3PageAllocEx(cChunkPages, 0 /*fFlags*/, &pvChunk,
845#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
846 VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
847#else
848 NULL,
849#endif
850 paChunkPages);
851 if (RT_SUCCESS(rc))
852 {
853#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
854 if (!VMMIsHwVirtExtForced(pVM))
855 R0PtrChunk = NIL_RTR0PTR;
856#else
857 R0PtrChunk = (uintptr_t)pvChunk;
858#endif
859 memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
860
861 PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
862
863 /*
864 * Create a mapping and map the pages into it.
865 * We push these in below the HMA.
866 */
867 RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
868 rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /*fFlags*/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
869 if (RT_SUCCESS(rc))
870 {
871 pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
872
873 RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
874 RTGCPTR GCPtrPage = GCPtrChunk;
875 for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
876 rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
877 if (RT_SUCCESS(rc))
878 {
879 /*
880 * Ok, init and link the range.
881 */
882 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
883 (RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
884 *ppPrev = pNew;
885 }
886 }
887
888 if (RT_FAILURE(rc))
889 SUPR3PageFreeEx(pvChunk, cChunkPages);
890 }
891
892 RTMemTmpFree(paChunkPages);
893 return rc;
894}
895
896
897/**
898 * Sets up a range RAM.
899 *
900 * This will check for conflicting registrations, make a resource
901 * reservation for the memory (with GMM), and setup the per-page
902 * tracking structures (PGMPAGE).
903 *
904 * @returns VBox stutus code.
905 * @param pVM Pointer to the shared VM structure.
906 * @param GCPhys The physical address of the RAM.
907 * @param cb The size of the RAM.
908 * @param pszDesc The description - not copied, so, don't free or change it.
909 */
910VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
911{
912 /*
913 * Validate input.
914 */
915 Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
916 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
917 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
918 AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
919 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
920 AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
921 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
922 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
923
924 /*
925 * Find range location and check for conflicts.
926 * (We don't lock here because the locking by EMT is only required on update.)
927 */
928 PPGMRAMRANGE pPrev = NULL;
929 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
930 while (pRam && GCPhysLast >= pRam->GCPhys)
931 {
932 if ( GCPhysLast >= pRam->GCPhys
933 && GCPhys <= pRam->GCPhysLast)
934 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
935 GCPhys, GCPhysLast, pszDesc,
936 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
937 VERR_PGM_RAM_CONFLICT);
938
939 /* next */
940 pPrev = pRam;
941 pRam = pRam->pNextR3;
942 }
943
944 /*
945 * Register it with GMM (the API bitches).
946 */
947 const RTGCPHYS cPages = cb >> PAGE_SHIFT;
948 int rc = MMR3IncreaseBaseReservation(pVM, cPages);
949 if (RT_FAILURE(rc))
950 return rc;
951
952 if ( GCPhys >= _4G
953 && cPages > 256)
954 {
955 /*
956 * The PGMRAMRANGE structures for the high memory can get very big.
957 * In order to avoid SUPR3PageAllocEx allocation failures due to the
958 * allocation size limit there and also to avoid being unable to find
959 * guest mapping space for them, we split this memory up into 4MB in
960 * (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
961 * mode.
962 *
963 * The first and last page of each mapping are guard pages and marked
964 * not-present. So, we've got 4186112 and 16769024 bytes available for
965 * the PGMRAMRANGE structure.
966 *
967 * Note! The sizes used here will influence the saved state.
968 */
969 uint32_t cbChunk;
970 uint32_t cPagesPerChunk;
971 if (VMMIsHwVirtExtForced(pVM))
972 {
973 cbChunk = 16U*_1M;
974 cPagesPerChunk = 1048048; /* max ~1048059 */
975 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U*_1M - PAGE_SIZE * 2);
976 }
977 else
978 {
979 cbChunk = 4U*_1M;
980 cPagesPerChunk = 261616; /* max ~261627 */
981 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U*_1M - PAGE_SIZE * 2);
982 }
983 AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
984
985 RTGCPHYS cPagesLeft = cPages;
986 RTGCPHYS GCPhysChunk = GCPhys;
987 uint32_t iChunk = 0;
988 while (cPagesLeft > 0)
989 {
990 uint32_t cPagesInChunk = cPagesLeft;
991 if (cPagesInChunk > cPagesPerChunk)
992 cPagesInChunk = cPagesPerChunk;
993
994 rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
995 AssertRCReturn(rc, rc);
996
997 /* advance */
998 GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
999 cPagesLeft -= cPagesInChunk;
1000 iChunk++;
1001 }
1002 }
1003 else
1004 {
1005 /*
1006 * Allocate, initialize and link the new RAM range.
1007 */
1008 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1009 PPGMRAMRANGE pNew;
1010 rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1011 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1012
1013 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1014 }
1015
1016 /*
1017 * Notify REM.
1018 */
1019 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1020
1021 return VINF_SUCCESS;
1022}
1023
1024
1025/**
1026 * Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1027 *
1028 * We do this late in the init process so that all the ROM and MMIO ranges have
1029 * been registered already and we don't go wasting memory on them.
1030 *
1031 * @returns VBox status code.
1032 *
1033 * @param pVM Pointer to the shared VM structure.
1034 */
1035int pgmR3PhysRamPreAllocate(PVM pVM)
1036{
1037 Assert(pVM->pgm.s.fRamPreAlloc);
1038 Log(("pgmR3PhysRamPreAllocate: enter\n"));
1039
1040 /*
1041 * Walk the RAM ranges and allocate all RAM pages, halt at
1042 * the first allocation error.
1043 */
1044 uint64_t cPages = 0;
1045 uint64_t NanoTS = RTTimeNanoTS();
1046 pgmLock(pVM);
1047 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1048 {
1049 PPGMPAGE pPage = &pRam->aPages[0];
1050 RTGCPHYS GCPhys = pRam->GCPhys;
1051 uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1052 while (cLeft-- > 0)
1053 {
1054 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1055 {
1056 switch (PGM_PAGE_GET_STATE(pPage))
1057 {
1058 case PGM_PAGE_STATE_ZERO:
1059 {
1060 int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1061 if (RT_FAILURE(rc))
1062 {
1063 LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1064 pgmUnlock(pVM);
1065 return rc;
1066 }
1067 cPages++;
1068 break;
1069 }
1070
1071 case PGM_PAGE_STATE_ALLOCATED:
1072 case PGM_PAGE_STATE_WRITE_MONITORED:
1073 case PGM_PAGE_STATE_SHARED:
1074 /* nothing to do here. */
1075 break;
1076 }
1077 }
1078
1079 /* next */
1080 pPage++;
1081 GCPhys += PAGE_SIZE;
1082 }
1083 }
1084 pgmUnlock(pVM);
1085 NanoTS = RTTimeNanoTS() - NanoTS;
1086
1087 LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1088 Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1089 return VINF_SUCCESS;
1090}
1091
1092
1093/**
1094 * Resets (zeros) the RAM.
1095 *
1096 * ASSUMES that the caller owns the PGM lock.
1097 *
1098 * @returns VBox status code.
1099 * @param pVM Pointer to the shared VM structure.
1100 */
1101int pgmR3PhysRamReset(PVM pVM)
1102{
1103 /*
1104 * We batch up pages before freeing them.
1105 */
1106 uint32_t cPendingPages = 0;
1107 PGMMFREEPAGESREQ pReq;
1108 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1109 AssertLogRelRCReturn(rc, rc);
1110
1111 /*
1112 * Walk the ram ranges.
1113 */
1114 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1115 {
1116 uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1117 AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1118
1119 if (!pVM->pgm.s.fRamPreAlloc)
1120 {
1121 /* Replace all RAM pages by ZERO pages. */
1122 while (iPage-- > 0)
1123 {
1124 PPGMPAGE pPage = &pRam->aPages[iPage];
1125 switch (PGM_PAGE_GET_TYPE(pPage))
1126 {
1127 case PGMPAGETYPE_RAM:
1128 if (!PGM_PAGE_IS_ZERO(pPage))
1129 {
1130 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1131 AssertLogRelRCReturn(rc, rc);
1132 }
1133 break;
1134
1135 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1136 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1137 break;
1138
1139 case PGMPAGETYPE_MMIO2:
1140 case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1141 case PGMPAGETYPE_ROM:
1142 case PGMPAGETYPE_MMIO:
1143 break;
1144 default:
1145 AssertFailed();
1146 }
1147 } /* for each page */
1148 }
1149 else
1150 {
1151 /* Zero the memory. */
1152 while (iPage-- > 0)
1153 {
1154 PPGMPAGE pPage = &pRam->aPages[iPage];
1155 switch (PGM_PAGE_GET_TYPE(pPage))
1156 {
1157 case PGMPAGETYPE_RAM:
1158 switch (PGM_PAGE_GET_STATE(pPage))
1159 {
1160 case PGM_PAGE_STATE_ZERO:
1161 break;
1162 case PGM_PAGE_STATE_SHARED:
1163 case PGM_PAGE_STATE_WRITE_MONITORED:
1164 rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1165 AssertLogRelRCReturn(rc, rc);
1166 case PGM_PAGE_STATE_ALLOCATED:
1167 {
1168 void *pvPage;
1169 PPGMPAGEMAP pMapIgnored;
1170 rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pMapIgnored, &pvPage);
1171 AssertLogRelRCReturn(rc, rc);
1172 ASMMemZeroPage(pvPage);
1173 break;
1174 }
1175 }
1176 break;
1177
1178 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1179 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1180 break;
1181
1182 case PGMPAGETYPE_MMIO2:
1183 case PGMPAGETYPE_ROM_SHADOW:
1184 case PGMPAGETYPE_ROM:
1185 case PGMPAGETYPE_MMIO:
1186 break;
1187 default:
1188 AssertFailed();
1189
1190 }
1191 } /* for each page */
1192 }
1193
1194 }
1195
1196 /*
1197 * Finish off any pages pending freeing.
1198 */
1199 if (cPendingPages)
1200 {
1201 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1202 AssertLogRelRCReturn(rc, rc);
1203 }
1204 GMMR3FreePagesCleanup(pReq);
1205
1206 return VINF_SUCCESS;
1207}
1208
1209
1210/**
1211 * This is the interface IOM is using to register an MMIO region.
1212 *
1213 * It will check for conflicts and ensure that a RAM range structure
1214 * is present before calling the PGMR3HandlerPhysicalRegister API to
1215 * register the callbacks.
1216 *
1217 * @returns VBox status code.
1218 *
1219 * @param pVM Pointer to the shared VM structure.
1220 * @param GCPhys The start of the MMIO region.
1221 * @param cb The size of the MMIO region.
1222 * @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1223 * @param pvUserR3 The user argument for R3.
1224 * @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1225 * @param pvUserR0 The user argument for R0.
1226 * @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1227 * @param pvUserRC The user argument for RC.
1228 * @param pszDesc The description of the MMIO region.
1229 */
1230VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1231 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1232 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1233 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1234 R3PTRTYPE(const char *) pszDesc)
1235{
1236 /*
1237 * Assert on some assumption.
1238 */
1239 VM_ASSERT_EMT(pVM);
1240 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1241 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1242 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1243 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1244
1245 /*
1246 * Make sure there's a RAM range structure for the region.
1247 */
1248 int rc;
1249 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1250 bool fRamExists = false;
1251 PPGMRAMRANGE pRamPrev = NULL;
1252 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1253 while (pRam && GCPhysLast >= pRam->GCPhys)
1254 {
1255 if ( GCPhysLast >= pRam->GCPhys
1256 && GCPhys <= pRam->GCPhysLast)
1257 {
1258 /* Simplification: all within the same range. */
1259 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1260 && GCPhysLast <= pRam->GCPhysLast,
1261 ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1262 GCPhys, GCPhysLast, pszDesc,
1263 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1264 VERR_PGM_RAM_CONFLICT);
1265
1266 /* Check that it's all RAM or MMIO pages. */
1267 PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1268 uint32_t cLeft = cb >> PAGE_SHIFT;
1269 while (cLeft-- > 0)
1270 {
1271 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1272 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1273 ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1274 GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1275 VERR_PGM_RAM_CONFLICT);
1276 pPage++;
1277 }
1278
1279 /* Looks good. */
1280 fRamExists = true;
1281 break;
1282 }
1283
1284 /* next */
1285 pRamPrev = pRam;
1286 pRam = pRam->pNextR3;
1287 }
1288 PPGMRAMRANGE pNew;
1289 if (fRamExists)
1290 {
1291 pNew = NULL;
1292
1293 /*
1294 * Make all the pages in the range MMIO/ZERO pages, freeing any
1295 * RAM pages currently mapped here. This might not be 100% correct
1296 * for PCI memory, but we're doing the same thing for MMIO2 pages.
1297 */
1298 rc = pgmLock(pVM);
1299 if (RT_SUCCESS(rc))
1300 {
1301 rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1302 pgmUnlock(pVM);
1303 }
1304 AssertRCReturn(rc, rc);
1305 }
1306 else
1307 {
1308 /*
1309 * No RAM range, insert an ad-hoc one.
1310 *
1311 * Note that we don't have to tell REM about this range because
1312 * PGMHandlerPhysicalRegisterEx will do that for us.
1313 */
1314 Log(("PGMR3PhysMMIORegister: Adding ad-hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1315
1316 const uint32_t cPages = cb >> PAGE_SHIFT;
1317 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1318 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1319 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1320
1321 /* Initialize the range. */
1322 pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1323 pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1324 pNew->GCPhys = GCPhys;
1325 pNew->GCPhysLast = GCPhysLast;
1326 pNew->cb = cb;
1327 pNew->pszDesc = pszDesc;
1328 pNew->fFlags = 0; /** @todo add some kind of ad-hoc flag? */
1329
1330 pNew->pvR3 = NULL;
1331
1332 uint32_t iPage = cPages;
1333 while (iPage-- > 0)
1334 PGM_PAGE_INIT_ZERO_REAL(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1335 Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1336
1337 /* update the page count stats. */
1338 pVM->pgm.s.cZeroPages += cPages;
1339 pVM->pgm.s.cAllPages += cPages;
1340
1341 /* link it */
1342 pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1343 }
1344
1345 /*
1346 * Register the access handler.
1347 */
1348 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1349 pfnHandlerR3, pvUserR3,
1350 pfnHandlerR0, pvUserR0,
1351 pfnHandlerRC, pvUserRC, pszDesc);
1352 if ( RT_FAILURE(rc)
1353 && !fRamExists)
1354 {
1355 pVM->pgm.s.cZeroPages -= cb >> PAGE_SHIFT;
1356 pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1357
1358 /* remove the ad-hoc range. */
1359 pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1360 pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1361 MMHyperFree(pVM, pRam);
1362 }
1363
1364 return rc;
1365}
1366
1367
1368/**
1369 * This is the interface IOM is using to register an MMIO region.
1370 *
1371 * It will take care of calling PGMHandlerPhysicalDeregister and clean up
1372 * any ad-hoc PGMRAMRANGE left behind.
1373 *
1374 * @returns VBox status code.
1375 * @param pVM Pointer to the shared VM structure.
1376 * @param GCPhys The start of the MMIO region.
1377 * @param cb The size of the MMIO region.
1378 */
1379VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1380{
1381 VM_ASSERT_EMT(pVM);
1382
1383 /*
1384 * First deregister the handler, then check if we should remove the ram range.
1385 */
1386 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1387 if (RT_SUCCESS(rc))
1388 {
1389 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1390 PPGMRAMRANGE pRamPrev = NULL;
1391 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1392 while (pRam && GCPhysLast >= pRam->GCPhys)
1393 {
1394 /** @todo We're being a bit too careful here. rewrite. */
1395 if ( GCPhysLast == pRam->GCPhysLast
1396 && GCPhys == pRam->GCPhys)
1397 {
1398 Assert(pRam->cb == cb);
1399
1400 /*
1401 * See if all the pages are dead MMIO pages.
1402 */
1403 uint32_t const cPages = cb >> PAGE_SHIFT;
1404 bool fAllMMIO = true;
1405 uint32_t iPage = 0;
1406 uint32_t cLeft = cPages;
1407 while (cLeft-- > 0)
1408 {
1409 PPGMPAGE pPage = &pRam->aPages[iPage];
1410 if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1411 /*|| not-out-of-action later */)
1412 {
1413 fAllMMIO = false;
1414 Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1415 AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1416 break;
1417 }
1418 Assert(PGM_PAGE_IS_ZERO(pPage));
1419 pPage++;
1420 }
1421 if (fAllMMIO)
1422 {
1423 /*
1424 * Ad-hoc range, unlink and free it.
1425 */
1426 Log(("PGMR3PhysMMIODeregister: Freeing ad-hoc MMIO range for %RGp-%RGp %s\n",
1427 GCPhys, GCPhysLast, pRam->pszDesc));
1428
1429 pVM->pgm.s.cAllPages -= cPages;
1430 pVM->pgm.s.cZeroPages -= cPages;
1431
1432 pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1433 pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1434 MMHyperFree(pVM, pRam);
1435 break;
1436 }
1437 }
1438
1439 /*
1440 * Range match? It will all be within one range (see PGMAllHandler.cpp).
1441 */
1442 if ( GCPhysLast >= pRam->GCPhys
1443 && GCPhys <= pRam->GCPhysLast)
1444 {
1445 Assert(GCPhys >= pRam->GCPhys);
1446 Assert(GCPhysLast <= pRam->GCPhysLast);
1447
1448 /*
1449 * Turn the pages back into RAM pages.
1450 */
1451 uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1452 uint32_t cLeft = cb >> PAGE_SHIFT;
1453 while (cLeft--)
1454 {
1455 PPGMPAGE pPage = &pRam->aPages[iPage];
1456 AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1457 AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1458 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1459 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1460 }
1461 break;
1462 }
1463
1464 /* next */
1465 pRamPrev = pRam;
1466 pRam = pRam->pNextR3;
1467 }
1468 }
1469
1470 return rc;
1471}
1472
1473
1474/**
1475 * Locate a MMIO2 range.
1476 *
1477 * @returns Pointer to the MMIO2 range.
1478 * @param pVM Pointer to the shared VM structure.
1479 * @param pDevIns The device instance owning the region.
1480 * @param iRegion The region.
1481 */
1482DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1483{
1484 /*
1485 * Search the list.
1486 */
1487 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1488 if ( pCur->pDevInsR3 == pDevIns
1489 && pCur->iRegion == iRegion)
1490 return pCur;
1491 return NULL;
1492}
1493
1494
1495/**
1496 * Allocate and register an MMIO2 region.
1497 *
1498 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1499 * RAM associated with a device. It is also non-shared memory with a
1500 * permanent ring-3 mapping and page backing (presently).
1501 *
1502 * A MMIO2 range may overlap with base memory if a lot of RAM
1503 * is configured for the VM, in which case we'll drop the base
1504 * memory pages. Presently we will make no attempt to preserve
1505 * anything that happens to be present in the base memory that
1506 * is replaced, this is of course incorrectly but it's too much
1507 * effort.
1508 *
1509 * @returns VBox status code.
1510 * @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1511 * @retval VERR_ALREADY_EXISTS if the region already exists.
1512 *
1513 * @param pVM Pointer to the shared VM structure.
1514 * @param pDevIns The device instance owning the region.
1515 * @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1516 * this number has to be the number of that region. Otherwise
1517 * it can be any number safe UINT8_MAX.
1518 * @param cb The size of the region. Must be page aligned.
1519 * @param fFlags Reserved for future use, must be zero.
1520 * @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1521 * @param pszDesc The description.
1522 */
1523VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)
1524{
1525 /*
1526 * Validate input.
1527 */
1528 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1529 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1530 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1531 AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1532 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1533 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1534 AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1535 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1536 AssertReturn(cb, VERR_INVALID_PARAMETER);
1537 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1538
1539 const uint32_t cPages = cb >> PAGE_SHIFT;
1540 AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1541 AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1542
1543 /*
1544 * For the 2nd+ instance, mangle the description string so it's unique.
1545 */
1546 if (pDevIns->iInstance > 0)
1547 {
1548 pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1549 if (!pszDesc)
1550 return VERR_NO_MEMORY;
1551 }
1552
1553 /*
1554 * Try reserve and allocate the backing memory first as this is what is
1555 * most likely to fail.
1556 */
1557 int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1558 if (RT_SUCCESS(rc))
1559 {
1560 void *pvPages;
1561 PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1562 if (RT_SUCCESS(rc))
1563 rc = SUPR3PageAllocEx(cPages, 0 /*fFlags*/, &pvPages, NULL /*pR0Ptr*/, paPages);
1564 if (RT_SUCCESS(rc))
1565 {
1566 memset(pvPages, 0, cPages * PAGE_SIZE);
1567
1568 /*
1569 * Create the MMIO2 range record for it.
1570 */
1571 const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1572 PPGMMMIO2RANGE pNew;
1573 rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1574 AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1575 if (RT_SUCCESS(rc))
1576 {
1577 pNew->pDevInsR3 = pDevIns;
1578 pNew->pvR3 = pvPages;
1579 //pNew->pNext = NULL;
1580 //pNew->fMapped = false;
1581 //pNew->fOverlapping = false;
1582 pNew->iRegion = iRegion;
1583 pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1584 pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1585 pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1586 pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1587 pNew->RamRange.pszDesc = pszDesc;
1588 pNew->RamRange.cb = cb;
1589 //pNew->RamRange.fFlags = 0; /// @todo MMIO2 flag?
1590
1591 pNew->RamRange.pvR3 = pvPages;
1592
1593 uint32_t iPage = cPages;
1594 while (iPage-- > 0)
1595 {
1596 PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1597 paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
1598 PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1599 }
1600
1601 /* update page count stats */
1602 pVM->pgm.s.cAllPages += cPages;
1603 pVM->pgm.s.cPrivatePages += cPages;
1604
1605 /*
1606 * Link it into the list.
1607 * Since there is no particular order, just push it.
1608 */
1609 pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1610 pVM->pgm.s.pMmio2RangesR3 = pNew;
1611
1612 *ppv = pvPages;
1613 RTMemTmpFree(paPages);
1614 return VINF_SUCCESS;
1615 }
1616
1617 SUPR3PageFreeEx(pvPages, cPages);
1618 }
1619 RTMemTmpFree(paPages);
1620 MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1621 }
1622 if (pDevIns->iInstance > 0)
1623 MMR3HeapFree((void *)pszDesc);
1624 return rc;
1625}
1626
1627
1628/**
1629 * Deregisters and frees an MMIO2 region.
1630 *
1631 * Any physical (and virtual) access handlers registered for the region must
1632 * be deregistered before calling this function.
1633 *
1634 * @returns VBox status code.
1635 * @param pVM Pointer to the shared VM structure.
1636 * @param pDevIns The device instance owning the region.
1637 * @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1638 */
1639VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1640{
1641 /*
1642 * Validate input.
1643 */
1644 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1645 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1646 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1647
1648 int rc = VINF_SUCCESS;
1649 unsigned cFound = 0;
1650 PPGMMMIO2RANGE pPrev = NULL;
1651 PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1652 while (pCur)
1653 {
1654 if ( pCur->pDevInsR3 == pDevIns
1655 && ( iRegion == UINT32_MAX
1656 || pCur->iRegion == iRegion))
1657 {
1658 cFound++;
1659
1660 /*
1661 * Unmap it if it's mapped.
1662 */
1663 if (pCur->fMapped)
1664 {
1665 int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1666 AssertRC(rc2);
1667 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1668 rc = rc2;
1669 }
1670
1671 /*
1672 * Unlink it
1673 */
1674 PPGMMMIO2RANGE pNext = pCur->pNextR3;
1675 if (pPrev)
1676 pPrev->pNextR3 = pNext;
1677 else
1678 pVM->pgm.s.pMmio2RangesR3 = pNext;
1679 pCur->pNextR3 = NULL;
1680
1681 /*
1682 * Free the memory.
1683 */
1684 int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1685 AssertRC(rc2);
1686 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1687 rc = rc2;
1688
1689 uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1690 rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1691 AssertRC(rc2);
1692 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1693 rc = rc2;
1694
1695 /* we're leaking hyper memory here if done at runtime. */
1696 Assert( VMR3GetState(pVM) == VMSTATE_OFF
1697 || VMR3GetState(pVM) == VMSTATE_DESTROYING
1698 || VMR3GetState(pVM) == VMSTATE_TERMINATED
1699 || VMR3GetState(pVM) == VMSTATE_CREATING);
1700 /*rc = MMHyperFree(pVM, pCur);
1701 AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1702
1703
1704 /* update page count stats */
1705 pVM->pgm.s.cAllPages -= cPages;
1706 pVM->pgm.s.cPrivatePages -= cPages;
1707
1708 /* next */
1709 pCur = pNext;
1710 }
1711 else
1712 {
1713 pPrev = pCur;
1714 pCur = pCur->pNextR3;
1715 }
1716 }
1717
1718 return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1719}
1720
1721
1722/**
1723 * Maps a MMIO2 region.
1724 *
1725 * This is done when a guest / the bios / state loading changes the
1726 * PCI config. The replacing of base memory has the same restrictions
1727 * as during registration, of course.
1728 *
1729 * @returns VBox status code.
1730 *
1731 * @param pVM Pointer to the shared VM structure.
1732 * @param pDevIns The
1733 */
1734VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1735{
1736 /*
1737 * Validate input
1738 */
1739 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1740 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1741 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1742 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1743 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1744 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1745
1746 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1747 AssertReturn(pCur, VERR_NOT_FOUND);
1748 AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
1749 Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
1750 Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
1751
1752 const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
1753 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1754
1755 /*
1756 * Find our location in the ram range list, checking for
1757 * restriction we don't bother implementing yet (partially overlapping).
1758 */
1759 bool fRamExists = false;
1760 PPGMRAMRANGE pRamPrev = NULL;
1761 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1762 while (pRam && GCPhysLast >= pRam->GCPhys)
1763 {
1764 if ( GCPhys <= pRam->GCPhysLast
1765 && GCPhysLast >= pRam->GCPhys)
1766 {
1767 /* completely within? */
1768 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1769 && GCPhysLast <= pRam->GCPhysLast,
1770 ("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
1771 GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
1772 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1773 VERR_PGM_RAM_CONFLICT);
1774 fRamExists = true;
1775 break;
1776 }
1777
1778 /* next */
1779 pRamPrev = pRam;
1780 pRam = pRam->pNextR3;
1781 }
1782 if (fRamExists)
1783 {
1784 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1785 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1786 while (cPagesLeft-- > 0)
1787 {
1788 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1789 ("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
1790 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
1791 VERR_PGM_RAM_CONFLICT);
1792 pPage++;
1793 }
1794 }
1795 Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
1796 GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
1797
1798 /*
1799 * Make the changes.
1800 */
1801 pgmLock(pVM);
1802
1803 pCur->RamRange.GCPhys = GCPhys;
1804 pCur->RamRange.GCPhysLast = GCPhysLast;
1805 pCur->fMapped = true;
1806 pCur->fOverlapping = fRamExists;
1807
1808 if (fRamExists)
1809 {
1810/** @todo use pgmR3PhysFreePageRange here. */
1811 uint32_t cPendingPages = 0;
1812 PGMMFREEPAGESREQ pReq;
1813 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1814 AssertLogRelRCReturn(rc, rc);
1815
1816 /* replace the pages, freeing all present RAM pages. */
1817 PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
1818 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1819 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1820 while (cPagesLeft-- > 0)
1821 {
1822 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
1823 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1824
1825 RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
1826 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
1827 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
1828 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
1829
1830 pVM->pgm.s.cZeroPages--;
1831 GCPhys += PAGE_SIZE;
1832 pPageSrc++;
1833 pPageDst++;
1834 }
1835
1836 if (cPendingPages)
1837 {
1838 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1839 AssertLogRelRCReturn(rc, rc);
1840 }
1841 GMMR3FreePagesCleanup(pReq);
1842 }
1843 else
1844 {
1845 /* link in the ram range */
1846 pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
1847 REMR3NotifyPhysRamRegister(pVM, GCPhys, pCur->RamRange.cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
1848 }
1849
1850 pgmUnlock(pVM);
1851
1852 return VINF_SUCCESS;
1853}
1854
1855
1856/**
1857 * Unmaps a MMIO2 region.
1858 *
1859 * This is done when a guest / the bios / state loading changes the
1860 * PCI config. The replacing of base memory has the same restrictions
1861 * as during registration, of course.
1862 */
1863VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1864{
1865 /*
1866 * Validate input
1867 */
1868 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1869 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1870 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1871 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1872 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1873 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1874
1875 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1876 AssertReturn(pCur, VERR_NOT_FOUND);
1877 AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
1878 AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
1879 Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
1880
1881 Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
1882 pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
1883
1884 /*
1885 * Unmap it.
1886 */
1887 pgmLock(pVM);
1888
1889 if (pCur->fOverlapping)
1890 {
1891 /* Restore the RAM pages we've replaced. */
1892 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1893 while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
1894 pRam = pRam->pNextR3;
1895
1896 RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
1897 Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
1898 PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1899 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1900 while (cPagesLeft-- > 0)
1901 {
1902 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
1903 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
1904 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
1905 PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
1906
1907 pVM->pgm.s.cZeroPages++;
1908 pPageDst++;
1909 }
1910 }
1911 else
1912 {
1913 REMR3NotifyPhysRamDeregister(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb);
1914 pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
1915 }
1916
1917 pCur->RamRange.GCPhys = NIL_RTGCPHYS;
1918 pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
1919 pCur->fOverlapping = false;
1920 pCur->fMapped = false;
1921
1922 pgmUnlock(pVM);
1923
1924 return VINF_SUCCESS;
1925}
1926
1927
1928/**
1929 * Checks if the given address is an MMIO2 base address or not.
1930 *
1931 * @returns true/false accordingly.
1932 * @param pVM Pointer to the shared VM structure.
1933 * @param pDevIns The owner of the memory, optional.
1934 * @param GCPhys The address to check.
1935 */
1936VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
1937{
1938 /*
1939 * Validate input
1940 */
1941 VM_ASSERT_EMT_RETURN(pVM, false);
1942 AssertPtrReturn(pDevIns, false);
1943 AssertReturn(GCPhys != NIL_RTGCPHYS, false);
1944 AssertReturn(GCPhys != 0, false);
1945 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
1946
1947 /*
1948 * Search the list.
1949 */
1950 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1951 if (pCur->RamRange.GCPhys == GCPhys)
1952 {
1953 Assert(pCur->fMapped);
1954 return true;
1955 }
1956 return false;
1957}
1958
1959
1960/**
1961 * Gets the HC physical address of a page in the MMIO2 region.
1962 *
1963 * This is API is intended for MMHyper and shouldn't be called
1964 * by anyone else...
1965 *
1966 * @returns VBox status code.
1967 * @param pVM Pointer to the shared VM structure.
1968 * @param pDevIns The owner of the memory, optional.
1969 * @param iRegion The region.
1970 * @param off The page expressed an offset into the MMIO2 region.
1971 * @param pHCPhys Where to store the result.
1972 */
1973VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
1974{
1975 /*
1976 * Validate input
1977 */
1978 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1979 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1980 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1981
1982 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1983 AssertReturn(pCur, VERR_NOT_FOUND);
1984 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1985
1986 PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
1987 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
1988 return VINF_SUCCESS;
1989}
1990
1991
1992/**
1993 * Maps a portion of an MMIO2 region into kernel space (host).
1994 *
1995 * The kernel mapping will become invalid when the MMIO2 memory is deregistered
1996 * or the VM is terminated.
1997 *
1998 * @return VBox status code.
1999 *
2000 * @param pVM Pointer to the shared VM structure.
2001 * @param pDevIns The device owning the MMIO2 memory.
2002 * @param iRegion The region.
2003 * @param off The offset into the region. Must be page aligned.
2004 * @param cb The number of bytes to map. Must be page aligned.
2005 * @param pszDesc Mapping description.
2006 * @param pR0Ptr Where to store the R0 address.
2007 */
2008VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2009 const char *pszDesc, PRTR0PTR pR0Ptr)
2010{
2011 /*
2012 * Validate input.
2013 */
2014 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2015 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2016 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2017
2018 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2019 AssertReturn(pCur, VERR_NOT_FOUND);
2020 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2021 AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2022 AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2023
2024 /*
2025 * Pass the request on to the support library/driver.
2026 */
2027 int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2028
2029 return rc;
2030}
2031
2032
2033/**
2034 * Registers a ROM image.
2035 *
2036 * Shadowed ROM images requires double the amount of backing memory, so,
2037 * don't use that unless you have to. Shadowing of ROM images is process
2038 * where we can select where the reads go and where the writes go. On real
2039 * hardware the chipset provides means to configure this. We provide
2040 * PGMR3PhysProtectROM() for this purpose.
2041 *
2042 * A read-only copy of the ROM image will always be kept around while we
2043 * will allocate RAM pages for the changes on demand (unless all memory
2044 * is configured to be preallocated).
2045 *
2046 * @returns VBox status.
2047 * @param pVM VM Handle.
2048 * @param pDevIns The device instance owning the ROM.
2049 * @param GCPhys First physical address in the range.
2050 * Must be page aligned!
2051 * @param cbRange The size of the range (in bytes).
2052 * Must be page aligned!
2053 * @param pvBinary Pointer to the binary data backing the ROM image.
2054 * This must be exactly \a cbRange in size.
2055 * @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2056 * and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2057 * @param pszDesc Pointer to description string. This must not be freed.
2058 *
2059 * @remark There is no way to remove the rom, automatically on device cleanup or
2060 * manually from the device yet. This isn't difficult in any way, it's
2061 * just not something we expect to be necessary for a while.
2062 */
2063VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2064 const void *pvBinary, uint32_t fFlags, const char *pszDesc)
2065{
2066 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2067 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2068
2069 /*
2070 * Validate input.
2071 */
2072 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2073 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2074 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2075 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2076 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2077 AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2078 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2079 AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED | PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2080 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2081
2082 const uint32_t cPages = cb >> PAGE_SHIFT;
2083
2084 /*
2085 * Find the ROM location in the ROM list first.
2086 */
2087 PPGMROMRANGE pRomPrev = NULL;
2088 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2089 while (pRom && GCPhysLast >= pRom->GCPhys)
2090 {
2091 if ( GCPhys <= pRom->GCPhysLast
2092 && GCPhysLast >= pRom->GCPhys)
2093 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2094 GCPhys, GCPhysLast, pszDesc,
2095 pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2096 VERR_PGM_RAM_CONFLICT);
2097 /* next */
2098 pRomPrev = pRom;
2099 pRom = pRom->pNextR3;
2100 }
2101
2102 /*
2103 * Find the RAM location and check for conflicts.
2104 *
2105 * Conflict detection is a bit different than for RAM
2106 * registration since a ROM can be located within a RAM
2107 * range. So, what we have to check for is other memory
2108 * types (other than RAM that is) and that we don't span
2109 * more than one RAM range (layz).
2110 */
2111 bool fRamExists = false;
2112 PPGMRAMRANGE pRamPrev = NULL;
2113 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2114 while (pRam && GCPhysLast >= pRam->GCPhys)
2115 {
2116 if ( GCPhys <= pRam->GCPhysLast
2117 && GCPhysLast >= pRam->GCPhys)
2118 {
2119 /* completely within? */
2120 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2121 && GCPhysLast <= pRam->GCPhysLast,
2122 ("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2123 GCPhys, GCPhysLast, pszDesc,
2124 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2125 VERR_PGM_RAM_CONFLICT);
2126 fRamExists = true;
2127 break;
2128 }
2129
2130 /* next */
2131 pRamPrev = pRam;
2132 pRam = pRam->pNextR3;
2133 }
2134 if (fRamExists)
2135 {
2136 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2137 uint32_t cPagesLeft = cPages;
2138 while (cPagesLeft-- > 0)
2139 {
2140 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2141 ("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2142 pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2143 pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2144 Assert(PGM_PAGE_IS_ZERO(pPage));
2145 pPage++;
2146 }
2147 }
2148
2149 /*
2150 * Update the base memory reservation if necessary.
2151 */
2152 uint32_t cExtraBaseCost = fRamExists ? cPages : 0;
2153 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2154 cExtraBaseCost += cPages;
2155 if (cExtraBaseCost)
2156 {
2157 int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2158 if (RT_FAILURE(rc))
2159 return rc;
2160 }
2161
2162 /*
2163 * Allocate memory for the virgin copy of the RAM.
2164 */
2165 PGMMALLOCATEPAGESREQ pReq;
2166 int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2167 AssertRCReturn(rc, rc);
2168
2169 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2170 {
2171 pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2172 pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2173 pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2174 }
2175
2176 pgmLock(pVM);
2177 rc = GMMR3AllocatePagesPerform(pVM, pReq);
2178 pgmUnlock(pVM);
2179 if (RT_FAILURE(rc))
2180 {
2181 GMMR3AllocatePagesCleanup(pReq);
2182 return rc;
2183 }
2184
2185 /*
2186 * Allocate the new ROM range and RAM range (if necessary).
2187 */
2188 PPGMROMRANGE pRomNew;
2189 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2190 if (RT_SUCCESS(rc))
2191 {
2192 PPGMRAMRANGE pRamNew = NULL;
2193 if (!fRamExists)
2194 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2195 if (RT_SUCCESS(rc))
2196 {
2197 pgmLock(pVM);
2198
2199 /*
2200 * Initialize and insert the RAM range (if required).
2201 */
2202 PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2203 if (!fRamExists)
2204 {
2205 pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2206 pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2207 pRamNew->GCPhys = GCPhys;
2208 pRamNew->GCPhysLast = GCPhysLast;
2209 pRamNew->cb = cb;
2210 pRamNew->pszDesc = pszDesc;
2211 pRamNew->fFlags = 0;
2212 pRamNew->pvR3 = NULL;
2213
2214 PPGMPAGE pPage = &pRamNew->aPages[0];
2215 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2216 {
2217 PGM_PAGE_INIT(pPage,
2218 pReq->aPages[iPage].HCPhysGCPhys,
2219 pReq->aPages[iPage].idPage,
2220 PGMPAGETYPE_ROM,
2221 PGM_PAGE_STATE_ALLOCATED);
2222
2223 pRomPage->Virgin = *pPage;
2224 }
2225
2226 pVM->pgm.s.cAllPages += cPages;
2227 pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2228 }
2229 else
2230 {
2231 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2232 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2233 {
2234 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2235 PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2236 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2237 PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2238
2239 pRomPage->Virgin = *pPage;
2240 }
2241
2242 pRamNew = pRam;
2243
2244 pVM->pgm.s.cZeroPages -= cPages;
2245 }
2246 pVM->pgm.s.cPrivatePages += cPages;
2247
2248 pgmUnlock(pVM);
2249
2250
2251 /*
2252 * !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2253 *
2254 * If it's shadowed we'll register the handler after the ROM notification
2255 * so we get the access handler callbacks that we should. If it isn't
2256 * shadowed we'll do it the other way around to make REM use the built-in
2257 * ROM behavior and not the handler behavior (which is to route all access
2258 * to PGM atm).
2259 */
2260 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2261 {
2262 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2263 rc = PGMR3HandlerPhysicalRegister(pVM,
2264 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2265 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2266 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2267 GCPhys, GCPhysLast,
2268 pgmR3PhysRomWriteHandler, pRomNew,
2269 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2270 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2271 }
2272 else
2273 {
2274 rc = PGMR3HandlerPhysicalRegister(pVM,
2275 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2276 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2277 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2278 GCPhys, GCPhysLast,
2279 pgmR3PhysRomWriteHandler, pRomNew,
2280 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2281 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2282 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2283 }
2284 if (RT_SUCCESS(rc))
2285 {
2286 pgmLock(pVM);
2287
2288 /*
2289 * Copy the image over to the virgin pages.
2290 * This must be done after linking in the RAM range.
2291 */
2292 PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2293 for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2294 {
2295 void *pvDstPage;
2296 PPGMPAGEMAP pMapIgnored;
2297 rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pMapIgnored, &pvDstPage);
2298 if (RT_FAILURE(rc))
2299 {
2300 VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2301 break;
2302 }
2303 memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2304 }
2305 if (RT_SUCCESS(rc))
2306 {
2307 /*
2308 * Initialize the ROM range.
2309 * Note that the Virgin member of the pages has already been initialized above.
2310 */
2311 pRomNew->GCPhys = GCPhys;
2312 pRomNew->GCPhysLast = GCPhysLast;
2313 pRomNew->cb = cb;
2314 pRomNew->fFlags = fFlags;
2315 pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2316 pRomNew->pszDesc = pszDesc;
2317
2318 for (unsigned iPage = 0; iPage < cPages; iPage++)
2319 {
2320 PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2321 pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2322 PGM_PAGE_INIT_ZERO_REAL(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2323 }
2324
2325 /* update the page count stats */
2326 pVM->pgm.s.cZeroPages += cPages;
2327 pVM->pgm.s.cAllPages += cPages;
2328
2329 /*
2330 * Insert the ROM range, tell REM and return successfully.
2331 */
2332 pRomNew->pNextR3 = pRom;
2333 pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2334 pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2335
2336 if (pRomPrev)
2337 {
2338 pRomPrev->pNextR3 = pRomNew;
2339 pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2340 pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2341 }
2342 else
2343 {
2344 pVM->pgm.s.pRomRangesR3 = pRomNew;
2345 pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2346 pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2347 }
2348
2349 GMMR3AllocatePagesCleanup(pReq);
2350 pgmUnlock(pVM);
2351 return VINF_SUCCESS;
2352 }
2353
2354 /* bail out */
2355
2356 pgmUnlock(pVM);
2357 int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2358 AssertRC(rc2);
2359 pgmLock(pVM);
2360 }
2361
2362 if (!fRamExists)
2363 {
2364 pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2365 MMHyperFree(pVM, pRamNew);
2366 }
2367 }
2368 MMHyperFree(pVM, pRomNew);
2369 }
2370
2371 /** @todo Purge the mapping cache or something... */
2372 GMMR3FreeAllocatedPages(pVM, pReq);
2373 GMMR3AllocatePagesCleanup(pReq);
2374 pgmUnlock(pVM);
2375 return rc;
2376}
2377
2378
2379/**
2380 * \#PF Handler callback for ROM write accesses.
2381 *
2382 * @returns VINF_SUCCESS if the handler have carried out the operation.
2383 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2384 * @param pVM VM Handle.
2385 * @param GCPhys The physical address the guest is writing to.
2386 * @param pvPhys The HC mapping of that address.
2387 * @param pvBuf What the guest is reading/writing.
2388 * @param cbBuf How much it's reading/writing.
2389 * @param enmAccessType The access type.
2390 * @param pvUser User argument.
2391 */
2392static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2393{
2394 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2395 const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2396 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2397 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2398 Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2399
2400 if (enmAccessType == PGMACCESSTYPE_READ)
2401 {
2402 switch (pRomPage->enmProt)
2403 {
2404 /*
2405 * Take the default action.
2406 */
2407 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2408 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2409 case PGMROMPROT_READ_ROM_WRITE_RAM:
2410 case PGMROMPROT_READ_RAM_WRITE_RAM:
2411 return VINF_PGM_HANDLER_DO_DEFAULT;
2412
2413 default:
2414 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2415 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2416 VERR_INTERNAL_ERROR);
2417 }
2418 }
2419 else
2420 {
2421 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2422 switch (pRomPage->enmProt)
2423 {
2424 /*
2425 * Ignore writes.
2426 */
2427 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2428 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2429 return VINF_SUCCESS;
2430
2431 /*
2432 * Write to the ram page.
2433 */
2434 case PGMROMPROT_READ_ROM_WRITE_RAM:
2435 case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
2436 {
2437 /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2438 Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2439
2440 /*
2441 * Take the lock, do lazy allocation, map the page and copy the data.
2442 *
2443 * Note that we have to bypass the mapping TLB since it works on
2444 * guest physical addresses and entering the shadow page would
2445 * kind of screw things up...
2446 */
2447 int rc = pgmLock(pVM);
2448 AssertRC(rc);
2449 PPGMPAGE pShadowPage = &pRomPage->Shadow;
2450 if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2451 {
2452 pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2453 AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2454 }
2455
2456 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pShadowPage) != PGM_PAGE_STATE_ALLOCATED))
2457 {
2458 rc = pgmPhysPageMakeWritable(pVM, pShadowPage, GCPhys);
2459 if (RT_FAILURE(rc))
2460 {
2461 pgmUnlock(pVM);
2462 return rc;
2463 }
2464 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* returned */, ("%Rrc\n", rc));
2465 }
2466
2467 void *pvDstPage;
2468 PPGMPAGEMAP pMapIgnored;
2469 int rc2 = pgmPhysPageMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pMapIgnored, &pvDstPage);
2470 if (RT_SUCCESS(rc2))
2471 memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2472 else
2473 rc = rc2;
2474
2475 pgmUnlock(pVM);
2476 return rc;
2477 }
2478
2479 default:
2480 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2481 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2482 VERR_INTERNAL_ERROR);
2483 }
2484 }
2485}
2486
2487
2488/**
2489 * Called by PGMR3Reset to reset the shadow, switch to the virgin,
2490 * and verify that the virgin part is untouched.
2491 *
2492 * This is done after the normal memory has been cleared.
2493 *
2494 * ASSUMES that the caller owns the PGM lock.
2495 *
2496 * @param pVM The VM handle.
2497 */
2498int pgmR3PhysRomReset(PVM pVM)
2499{
2500 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2501 {
2502 const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2503
2504 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2505 {
2506 /*
2507 * Reset the physical handler.
2508 */
2509 int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2510 AssertRCReturn(rc, rc);
2511
2512 /*
2513 * What we do with the shadow pages depends on the memory
2514 * preallocation option. If not enabled, we'll just throw
2515 * out all the dirty pages and replace them by the zero page.
2516 */
2517 if (!pVM->pgm.s.fRamPreAlloc)
2518 {
2519 /* Free the dirty pages. */
2520 uint32_t cPendingPages = 0;
2521 PGMMFREEPAGESREQ pReq;
2522 rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2523 AssertRCReturn(rc, rc);
2524
2525 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2526 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
2527 {
2528 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2529 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2530 AssertLogRelRCReturn(rc, rc);
2531 }
2532
2533 if (cPendingPages)
2534 {
2535 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2536 AssertLogRelRCReturn(rc, rc);
2537 }
2538 GMMR3FreePagesCleanup(pReq);
2539 }
2540 else
2541 {
2542 /* clear all the shadow pages. */
2543 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2544 {
2545 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO);
2546
2547 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2548 rc = pgmPhysPageMakeWritable(pVM, &pRom->aPages[iPage].Shadow, GCPhys);
2549 if (RT_FAILURE(rc))
2550 break;
2551
2552 void *pvDstPage;
2553 PPGMPAGEMAP pMapIgnored;
2554 rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pMapIgnored, &pvDstPage);
2555 if (RT_FAILURE(rc))
2556 break;
2557 ASMMemZeroPage(pvDstPage);
2558 }
2559 AssertRCReturn(rc, rc);
2560 }
2561 }
2562
2563#ifdef VBOX_STRICT
2564 /*
2565 * Verify that the virgin page is unchanged if possible.
2566 */
2567 if (pRom->pvOriginal)
2568 {
2569 uint8_t const *pbSrcPage = (uint8_t const *)pRom->pvOriginal;
2570 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2571 {
2572 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2573 PPGMPAGEMAP pMapIgnored;
2574 void *pvDstPage;
2575 int rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pMapIgnored, &pvDstPage);
2576 if (RT_FAILURE(rc))
2577 break;
2578 if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2579 LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2580 GCPhys, pRom->pszDesc));
2581 }
2582 }
2583#endif
2584 }
2585
2586 return VINF_SUCCESS;
2587}
2588
2589
2590/**
2591 * Change the shadowing of a range of ROM pages.
2592 *
2593 * This is intended for implementing chipset specific memory registers
2594 * and will not be very strict about the input. It will silently ignore
2595 * any pages that are not the part of a shadowed ROM.
2596 *
2597 * @returns VBox status code.
2598 * @retval VINF_PGM_SYNC_CR3
2599 *
2600 * @param pVM Pointer to the shared VM structure.
2601 * @param GCPhys Where to start. Page aligned.
2602 * @param cb How much to change. Page aligned.
2603 * @param enmProt The new ROM protection.
2604 */
2605VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2606{
2607 /*
2608 * Check input
2609 */
2610 if (!cb)
2611 return VINF_SUCCESS;
2612 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2613 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2614 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2615 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2616 AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2617
2618 /*
2619 * Process the request.
2620 */
2621 int rc = VINF_SUCCESS;
2622 bool fFlushTLB = false;
2623 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2624 if ( GCPhys <= pRom->GCPhysLast
2625 && GCPhysLast >= pRom->GCPhys
2626 && (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2627 {
2628 /*
2629 * Iterate the relevant pages and make necessary the changes.
2630 */
2631 bool fChanges = false;
2632 uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2633 ? pRom->cb >> PAGE_SHIFT
2634 : (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2635 for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2636 iPage < cPages;
2637 iPage++)
2638 {
2639 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2640 if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2641 {
2642 fChanges = true;
2643
2644 /* flush references to the page. */
2645 PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2646 int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRamPage, &fFlushTLB);
2647 if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS || RT_FAILURE(rc2)))
2648 rc = rc2;
2649
2650 PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2651 PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2652
2653 *pOld = *pRamPage;
2654 *pRamPage = *pNew;
2655 /** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2656 }
2657 pRomPage->enmProt = enmProt;
2658 }
2659
2660 /*
2661 * Reset the access handler if we made changes, no need
2662 * to optimize this.
2663 */
2664 if (fChanges)
2665 {
2666 int rc = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2667 AssertRCReturn(rc, rc);
2668 }
2669
2670 /* Advance - cb isn't updated. */
2671 GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2672 }
2673
2674 if (fFlushTLB)
2675 PGM_INVL_GUEST_TLBS();
2676 return rc;
2677}
2678
2679
2680/**
2681 * Sets the Address Gate 20 state.
2682 *
2683 * @param pVCpu The VCPU to operate on.
2684 * @param fEnable True if the gate should be enabled.
2685 * False if the gate should be disabled.
2686 */
2687VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
2688{
2689 LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
2690 if (pVCpu->pgm.s.fA20Enabled != fEnable)
2691 {
2692 pVCpu->pgm.s.fA20Enabled = fEnable;
2693 pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2694 REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
2695 /** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2696 }
2697}
2698
2699
2700/**
2701 * Tree enumeration callback for dealing with age rollover.
2702 * It will perform a simple compression of the current age.
2703 */
2704static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2705{
2706 /* Age compression - ASSUMES iNow == 4. */
2707 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2708 if (pChunk->iAge >= UINT32_C(0xffffff00))
2709 pChunk->iAge = 3;
2710 else if (pChunk->iAge >= UINT32_C(0xfffff000))
2711 pChunk->iAge = 2;
2712 else if (pChunk->iAge)
2713 pChunk->iAge = 1;
2714 else /* iAge = 0 */
2715 pChunk->iAge = 4;
2716
2717 /* reinsert */
2718 PVM pVM = (PVM)pvUser;
2719 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2720 pChunk->AgeCore.Key = pChunk->iAge;
2721 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2722 return 0;
2723}
2724
2725
2726/**
2727 * Tree enumeration callback that updates the chunks that have
2728 * been used since the last
2729 */
2730static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
2731{
2732 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2733 if (!pChunk->iAge)
2734 {
2735 PVM pVM = (PVM)pvUser;
2736 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2737 pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
2738 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2739 }
2740
2741 return 0;
2742}
2743
2744
2745/**
2746 * Performs ageing of the ring-3 chunk mappings.
2747 *
2748 * @param pVM The VM handle.
2749 */
2750VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
2751{
2752 pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
2753 pVM->pgm.s.ChunkR3Map.iNow++;
2754 if (pVM->pgm.s.ChunkR3Map.iNow == 0)
2755 {
2756 pVM->pgm.s.ChunkR3Map.iNow = 4;
2757 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
2758 }
2759 else
2760 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingCallback, pVM);
2761}
2762
2763
2764/**
2765 * The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
2766 */
2767typedef struct PGMR3PHYSCHUNKUNMAPCB
2768{
2769 PVM pVM; /**< The VM handle. */
2770 PPGMCHUNKR3MAP pChunk; /**< The chunk to unmap. */
2771} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
2772
2773
2774/**
2775 * Callback used to find the mapping that's been unused for
2776 * the longest time.
2777 */
2778static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
2779{
2780 do
2781 {
2782 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
2783 if ( pChunk->iAge
2784 && !pChunk->cRefs)
2785 {
2786 /*
2787 * Check that it's not in any of the TLBs.
2788 */
2789 PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
2790 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2791 if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
2792 {
2793 pChunk = NULL;
2794 break;
2795 }
2796 if (pChunk)
2797 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
2798 if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
2799 {
2800 pChunk = NULL;
2801 break;
2802 }
2803 if (pChunk)
2804 {
2805 ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
2806 return 1; /* done */
2807 }
2808 }
2809
2810 /* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
2811 pNode = pNode->pList;
2812 } while (pNode);
2813 return 0;
2814}
2815
2816
2817/**
2818 * Finds a good candidate for unmapping when the ring-3 mapping cache is full.
2819 *
2820 * The candidate will not be part of any TLBs, so no need to flush
2821 * anything afterwards.
2822 *
2823 * @returns Chunk id.
2824 * @param pVM The VM handle.
2825 */
2826static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
2827{
2828 /*
2829 * Do tree ageing first?
2830 */
2831 if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
2832 PGMR3PhysChunkAgeing(pVM);
2833
2834 /*
2835 * Enumerate the age tree starting with the left most node.
2836 */
2837 PGMR3PHYSCHUNKUNMAPCB Args;
2838 Args.pVM = pVM;
2839 Args.pChunk = NULL;
2840 if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /*fFromLeft*/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
2841 return Args.pChunk->Core.Key;
2842 return INT32_MAX;
2843}
2844
2845
2846/**
2847 * Maps the given chunk into the ring-3 mapping cache.
2848 *
2849 * This will call ring-0.
2850 *
2851 * @returns VBox status code.
2852 * @param pVM The VM handle.
2853 * @param idChunk The chunk in question.
2854 * @param ppChunk Where to store the chunk tracking structure.
2855 *
2856 * @remarks Called from within the PGM critical section.
2857 */
2858int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
2859{
2860 int rc;
2861
2862 /*
2863 * Allocate a new tracking structure first.
2864 */
2865#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2866 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
2867#else
2868 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
2869#endif
2870 AssertReturn(pChunk, VERR_NO_MEMORY);
2871 pChunk->Core.Key = idChunk;
2872 pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
2873 pChunk->iAge = 0;
2874 pChunk->cRefs = 0;
2875 pChunk->cPermRefs = 0;
2876 pChunk->pv = NULL;
2877
2878 /*
2879 * Request the ring-0 part to map the chunk in question and if
2880 * necessary unmap another one to make space in the mapping cache.
2881 */
2882 GMMMAPUNMAPCHUNKREQ Req;
2883 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2884 Req.Hdr.cbReq = sizeof(Req);
2885 Req.pvR3 = NULL;
2886 Req.idChunkMap = idChunk;
2887 Req.idChunkUnmap = NIL_GMM_CHUNKID;
2888 if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
2889 Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
2890 rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
2891 if (RT_SUCCESS(rc))
2892 {
2893 /*
2894 * Update the tree.
2895 */
2896 /* insert the new one. */
2897 AssertPtr(Req.pvR3);
2898 pChunk->pv = Req.pvR3;
2899 bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
2900 AssertRelease(fRc);
2901 pVM->pgm.s.ChunkR3Map.c++;
2902
2903 fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2904 AssertRelease(fRc);
2905
2906 /* remove the unmapped one. */
2907 if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
2908 {
2909 PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
2910 AssertRelease(pUnmappedChunk);
2911 pUnmappedChunk->pv = NULL;
2912 pUnmappedChunk->Core.Key = UINT32_MAX;
2913#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2914 MMR3HeapFree(pUnmappedChunk);
2915#else
2916 MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
2917#endif
2918 pVM->pgm.s.ChunkR3Map.c--;
2919 }
2920 }
2921 else
2922 {
2923 AssertRC(rc);
2924#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2925 MMR3HeapFree(pChunk);
2926#else
2927 MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
2928#endif
2929 pChunk = NULL;
2930 }
2931
2932 *ppChunk = pChunk;
2933 return rc;
2934}
2935
2936
2937/**
2938 * For VMMCALLHOST_PGM_MAP_CHUNK, considered internal.
2939 *
2940 * @returns see pgmR3PhysChunkMap.
2941 * @param pVM The VM handle.
2942 * @param idChunk The chunk to map.
2943 */
2944VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
2945{
2946 PPGMCHUNKR3MAP pChunk;
2947 return pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
2948}
2949
2950
2951/**
2952 * Invalidates the TLB for the ring-3 mapping cache.
2953 *
2954 * @param pVM The VM handle.
2955 */
2956VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
2957{
2958 pgmLock(pVM);
2959 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2960 {
2961 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
2962 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
2963 }
2964 pgmUnlock(pVM);
2965}
2966
2967
2968/**
2969 * Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES.
2970 *
2971 * This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
2972 * signal and clear the out of memory condition. When contracted, this API is
2973 * used to try clear the condition when the user wants to resume.
2974 *
2975 * @returns The following VBox status codes.
2976 * @retval VINF_SUCCESS on success. FFs cleared.
2977 * @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
2978 * this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
2979 *
2980 * @param pVM The VM handle.
2981 *
2982 * @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
2983 * in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
2984 * pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
2985 * handler.
2986 */
2987VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
2988{
2989 pgmLock(pVM);
2990
2991 /*
2992 * Allocate more pages, noting down the index of the first new page.
2993 */
2994 uint32_t iClear = pVM->pgm.s.cHandyPages;
2995 AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
2996 Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
2997 int rcAlloc = VINF_SUCCESS;
2998 int rcSeed = VINF_SUCCESS;
2999 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3000 while (rc == VERR_GMM_SEED_ME)
3001 {
3002 void *pvChunk;
3003 rcAlloc = rc = SUPPageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3004 if (RT_SUCCESS(rc))
3005 {
3006 rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3007 if (RT_FAILURE(rc))
3008 SUPPageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3009 }
3010 if (RT_SUCCESS(rc))
3011 rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3012 }
3013
3014 if (RT_SUCCESS(rc))
3015 {
3016 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3017 Assert(pVM->pgm.s.cHandyPages > 0);
3018 VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3019 VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3020
3021 /*
3022 * Clear the pages.
3023 */
3024 while (iClear < pVM->pgm.s.cHandyPages)
3025 {
3026 PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3027 void *pv;
3028 rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3029 AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3030 ASMMemZeroPage(pv);
3031 iClear++;
3032 Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3033 }
3034 }
3035 else
3036 {
3037 /*
3038 * We should never get here unless there is a genuine shortage of
3039 * memory (or some internal error). Flag the error so the VM can be
3040 * suspended ASAP and the user informed. If we're totally out of
3041 * handy pages we will return failure.
3042 */
3043 /* Report the failure. */
3044 LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3045 " cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3046 rc, rcSeed, rcAlloc,
3047 pVM->pgm.s.cHandyPages,
3048 pVM->pgm.s.cAllPages,
3049 pVM->pgm.s.cPrivatePages,
3050 pVM->pgm.s.cSharedPages,
3051 pVM->pgm.s.cZeroPages));
3052 if ( rc != VERR_NO_MEMORY
3053 && rc != VERR_LOCK_FAILED)
3054 {
3055 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3056 {
3057 LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3058 i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3059 pVM->pgm.s.aHandyPages[i].idSharedPage));
3060 uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3061 if (idPage != NIL_GMM_PAGEID)
3062 {
3063 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3064 pRam;
3065 pRam = pRam->pNextR3)
3066 {
3067 uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3068 for (uint32_t iPage = 0; iPage < cPages; iPage++)
3069 if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3070 LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3071 pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3072 }
3073 }
3074 }
3075 }
3076
3077 /* Set the FFs and adjust rc. */
3078 VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3079 VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3080 if ( rc == VERR_NO_MEMORY
3081 || rc == VERR_LOCK_FAILED)
3082 rc = VINF_EM_NO_MEMORY;
3083 }
3084
3085 pgmUnlock(pVM);
3086 return rc;
3087}
3088
3089
3090/**
3091 * Frees the specified RAM page and replaces it with the ZERO page.
3092 *
3093 * This is used by ballooning, remapping MMIO2 and RAM reset.
3094 *
3095 * @param pVM Pointer to the shared VM structure.
3096 * @param pReq Pointer to the request.
3097 * @param pPage Pointer to the page structure.
3098 * @param GCPhys The guest physical address of the page, if applicable.
3099 *
3100 * @remarks The caller must own the PGM lock.
3101 */
3102static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3103{
3104 /*
3105 * Assert sanity.
3106 */
3107 Assert(PDMCritSectIsOwner(&pVM->pgm.s.CritSect));
3108 if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3109 && PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3110 {
3111 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3112 return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3113 }
3114
3115 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO)
3116 return VINF_SUCCESS;
3117
3118 const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3119 Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3120 if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3121 || idPage > GMM_PAGEID_LAST
3122 || PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3123 {
3124 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3125 return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3126 }
3127
3128 /* update page count stats. */
3129 if (PGM_PAGE_IS_SHARED(pPage))
3130 pVM->pgm.s.cSharedPages--;
3131 else
3132 pVM->pgm.s.cPrivatePages--;
3133 pVM->pgm.s.cZeroPages++;
3134
3135 /*
3136 * pPage = ZERO page.
3137 */
3138 PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3139 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3140 PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3141
3142 /*
3143 * Make sure it's not in the handy page array.
3144 */
3145 for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3146 {
3147 if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3148 {
3149 pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3150 break;
3151 }
3152 if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3153 {
3154 pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3155 break;
3156 }
3157 }
3158
3159 /*
3160 * Push it onto the page array.
3161 */
3162 uint32_t iPage = *pcPendingPages;
3163 Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3164 *pcPendingPages += 1;
3165
3166 pReq->aPages[iPage].idPage = idPage;
3167
3168 if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3169 return VINF_SUCCESS;
3170
3171 /*
3172 * Flush the pages.
3173 */
3174 int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3175 if (RT_SUCCESS(rc))
3176 {
3177 GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3178 *pcPendingPages = 0;
3179 }
3180 return rc;
3181}
3182
3183
3184/**
3185 * Converts a GC physical address to a HC ring-3 pointer, with some
3186 * additional checks.
3187 *
3188 * @returns VBox status code.
3189 * @retval VINF_SUCCESS on success.
3190 * @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3191 * access handler of some kind.
3192 * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3193 * accesses or is odd in any way.
3194 * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3195 *
3196 * @param pVM The VM handle.
3197 * @param GCPhys The GC physical address to convert.
3198 * @param fWritable Whether write access is required.
3199 * @param ppv Where to store the pointer corresponding to GCPhys on
3200 * success.
3201 */
3202VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3203{
3204 pgmLock(pVM);
3205
3206 PPGMRAMRANGE pRam;
3207 PPGMPAGE pPage;
3208 int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3209 if (RT_SUCCESS(rc))
3210 {
3211 if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3212 rc = VINF_SUCCESS;
3213 else
3214 {
3215 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3216 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3217 else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3218 {
3219 /** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3220 * in -norawr0 mode. */
3221 if (fWritable)
3222 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3223 }
3224 else
3225 {
3226 /* Temporariliy disabled phycial handler(s), since the recompiler
3227 doesn't get notified when it's reset we'll have to pretend its
3228 operating normally. */
3229 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3230 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3231 else
3232 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3233 }
3234 }
3235 if (RT_SUCCESS(rc))
3236 {
3237 int rc2;
3238
3239 /* Make sure what we return is writable. */
3240 if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3241 switch (PGM_PAGE_GET_STATE(pPage))
3242 {
3243 case PGM_PAGE_STATE_ALLOCATED:
3244 break;
3245 case PGM_PAGE_STATE_ZERO:
3246 case PGM_PAGE_STATE_SHARED:
3247 case PGM_PAGE_STATE_WRITE_MONITORED:
3248 rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3249 AssertLogRelRCReturn(rc2, rc2);
3250 break;
3251 }
3252
3253 /* Get a ring-3 mapping of the address. */
3254 PPGMPAGER3MAPTLBE pTlbe;
3255 rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3256 AssertLogRelRCReturn(rc2, rc2);
3257 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
3258 /** @todo mapping/locking hell; this isn't horribly efficient since
3259 * pgmPhysPageLoadIntoTlb will repeate the lookup we've done here. */
3260
3261 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] *ppv=%p\n", GCPhys, rc, pPage, *ppv));
3262 }
3263 else
3264 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3265
3266 /* else: handler catching all access, no pointer returned. */
3267 }
3268 else
3269 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3270
3271 pgmUnlock(pVM);
3272 return rc;
3273}
3274
3275
3276
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