VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 20774

Last change on this file since 20774 was 20730, checked in by vboxsync, 15 years ago

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1/* $Id: PGMPhys.cpp 20730 2009-06-19 15:10:42Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM_PHYS
27#include <VBox/pgm.h>
28#include <VBox/iom.h>
29#include <VBox/mm.h>
30#include <VBox/stam.h>
31#include <VBox/rem.h>
32#include <VBox/pdmdev.h>
33#include "PGMInternal.h"
34#include <VBox/vm.h>
35#include <VBox/sup.h>
36#include <VBox/param.h>
37#include <VBox/err.h>
38#include <VBox/log.h>
39#include <iprt/assert.h>
40#include <iprt/alloc.h>
41#include <iprt/asm.h>
42#include <iprt/thread.h>
43#include <iprt/string.h>
44
45
46/*******************************************************************************
47* Defined Constants And Macros *
48*******************************************************************************/
49/** The number of pages to free in one batch. */
50#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
51
52
53/*******************************************************************************
54* Internal Functions *
55*******************************************************************************/
56static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
57static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
58
59
60/*
61 * PGMR3PhysReadU8-64
62 * PGMR3PhysWriteU8-64
63 */
64#define PGMPHYSFN_READNAME PGMR3PhysReadU8
65#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
66#define PGMPHYS_DATASIZE 1
67#define PGMPHYS_DATATYPE uint8_t
68#include "PGMPhysRWTmpl.h"
69
70#define PGMPHYSFN_READNAME PGMR3PhysReadU16
71#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
72#define PGMPHYS_DATASIZE 2
73#define PGMPHYS_DATATYPE uint16_t
74#include "PGMPhysRWTmpl.h"
75
76#define PGMPHYSFN_READNAME PGMR3PhysReadU32
77#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
78#define PGMPHYS_DATASIZE 4
79#define PGMPHYS_DATATYPE uint32_t
80#include "PGMPhysRWTmpl.h"
81
82#define PGMPHYSFN_READNAME PGMR3PhysReadU64
83#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
84#define PGMPHYS_DATASIZE 8
85#define PGMPHYS_DATATYPE uint64_t
86#include "PGMPhysRWTmpl.h"
87
88
89/**
90 * EMT worker for PGMR3PhysReadExternal.
91 */
92static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
93{
94 PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
95 return VINF_SUCCESS;
96}
97
98
99/**
100 * Write to physical memory, external users.
101 *
102 * @returns VBox status code.
103 * @retval VINF_SUCCESS.
104 *
105 * @param pVM VM Handle.
106 * @param GCPhys Physical address to write to.
107 * @param pvBuf What to write.
108 * @param cbWrite How many bytes to write.
109 *
110 * @thread Any but EMTs.
111 */
112VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
113{
114 VM_ASSERT_OTHER_THREAD(pVM);
115
116 AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
117 LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
118
119 pgmLock(pVM);
120
121 /*
122 * Copy loop on ram ranges.
123 */
124 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
125 for (;;)
126 {
127 /* Find range. */
128 while (pRam && GCPhys > pRam->GCPhysLast)
129 pRam = pRam->CTX_SUFF(pNext);
130 /* Inside range or not? */
131 if (pRam && GCPhys >= pRam->GCPhys)
132 {
133 /*
134 * Must work our way thru this page by page.
135 */
136 RTGCPHYS off = GCPhys - pRam->GCPhys;
137 while (off < pRam->cb)
138 {
139 unsigned iPage = off >> PAGE_SHIFT;
140 PPGMPAGE pPage = &pRam->aPages[iPage];
141
142 /*
143 * If the page has an ALL access handler, we'll have to
144 * delegate the job to EMT.
145 */
146 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
147 {
148 pgmUnlock(pVM);
149
150 PVMREQ pReq = NULL;
151 int rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
152 (PFNRT)pgmR3PhysReadExternalEMT, 4, pVM, &GCPhys, pvBuf, cbRead);
153 if (RT_SUCCESS(rc))
154 {
155 rc = pReq->iStatus;
156 VMR3ReqFree(pReq);
157 }
158 return rc;
159 }
160 Assert(!PGM_PAGE_IS_MMIO(pPage));
161
162 /*
163 * Simple stuff, go ahead.
164 */
165 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
166 if (cb > cbRead)
167 cb = cbRead;
168 const void *pvSrc;
169 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
170 if (RT_SUCCESS(rc))
171 memcpy(pvBuf, pvSrc, cb);
172 else
173 {
174 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
175 pRam->GCPhys + off, pPage, rc));
176 memset(pvBuf, 0xff, cb);
177 }
178
179 /* next page */
180 if (cb >= cbRead)
181 {
182 pgmUnlock(pVM);
183 return VINF_SUCCESS;
184 }
185 cbRead -= cb;
186 off += cb;
187 GCPhys += cb;
188 pvBuf = (char *)pvBuf + cb;
189 } /* walk pages in ram range. */
190 }
191 else
192 {
193 LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
194
195 /*
196 * Unassigned address space.
197 */
198 if (!pRam)
199 break;
200 size_t cb = pRam->GCPhys - GCPhys;
201 if (cb >= cbRead)
202 {
203 memset(pvBuf, 0xff, cbRead);
204 break;
205 }
206 memset(pvBuf, 0xff, cb);
207
208 cbRead -= cb;
209 pvBuf = (char *)pvBuf + cb;
210 GCPhys += cb;
211 }
212 } /* Ram range walk */
213
214 pgmUnlock(pVM);
215
216 return VINF_SUCCESS;
217}
218
219
220/**
221 * EMT worker for PGMR3PhysWriteExternal.
222 */
223static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
224{
225 /** @todo VERR_EM_NO_MEMORY */
226 PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
227 return VINF_SUCCESS;
228}
229
230
231/**
232 * Write to physical memory, external users.
233 *
234 * @returns VBox status code.
235 * @retval VINF_SUCCESS.
236 * @retval VERR_EM_NO_MEMORY.
237 *
238 * @param pVM VM Handle.
239 * @param GCPhys Physical address to write to.
240 * @param pvBuf What to write.
241 * @param cbWrite How many bytes to write.
242 *
243 * @thread Any but EMTs.
244 */
245VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
246{
247 VM_ASSERT_OTHER_THREAD(pVM);
248
249 AssertMsg(!pVM->pgm.s.fNoMorePhysWrites, ("Calling PGMR3PhysWriteExternal after pgmR3Save()!\n"));
250 AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
251 LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
252
253 pgmLock(pVM);
254
255 /*
256 * Copy loop on ram ranges, stop when we hit something difficult.
257 */
258 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
259 for (;;)
260 {
261 /* Find range. */
262 while (pRam && GCPhys > pRam->GCPhysLast)
263 pRam = pRam->CTX_SUFF(pNext);
264 /* Inside range or not? */
265 if (pRam && GCPhys >= pRam->GCPhys)
266 {
267 /*
268 * Must work our way thru this page by page.
269 */
270 RTGCPTR off = GCPhys - pRam->GCPhys;
271 while (off < pRam->cb)
272 {
273 RTGCPTR iPage = off >> PAGE_SHIFT;
274 PPGMPAGE pPage = &pRam->aPages[iPage];
275
276 /*
277 * It the page is in any way problematic, we have to
278 * do the work on the EMT. Anything that needs to be made
279 * writable or involves access handlers is problematic.
280 */
281 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
282 || PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
283 {
284 pgmUnlock(pVM);
285
286 PVMREQ pReq = NULL;
287 int rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
288 (PFNRT)pgmR3PhysWriteExternalEMT, 4, pVM, &GCPhys, pvBuf, cbWrite);
289 if (RT_SUCCESS(rc))
290 {
291 rc = pReq->iStatus;
292 VMR3ReqFree(pReq);
293 }
294 return rc;
295 }
296 Assert(!PGM_PAGE_IS_MMIO(pPage));
297
298 /*
299 * Simple stuff, go ahead.
300 */
301 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
302 if (cb > cbWrite)
303 cb = cbWrite;
304 void *pvDst;
305 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
306 if (RT_SUCCESS(rc))
307 memcpy(pvDst, pvBuf, cb);
308 else
309 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
310 pRam->GCPhys + off, pPage, rc));
311
312 /* next page */
313 if (cb >= cbWrite)
314 {
315 pgmUnlock(pVM);
316 return VINF_SUCCESS;
317 }
318
319 cbWrite -= cb;
320 off += cb;
321 GCPhys += cb;
322 pvBuf = (const char *)pvBuf + cb;
323 } /* walk pages in ram range */
324 }
325 else
326 {
327 /*
328 * Unassigned address space, skip it.
329 */
330 if (!pRam)
331 break;
332 size_t cb = pRam->GCPhys - GCPhys;
333 if (cb >= cbWrite)
334 break;
335 cbWrite -= cb;
336 pvBuf = (const char *)pvBuf + cb;
337 GCPhys += cb;
338 }
339 } /* Ram range walk */
340
341 pgmUnlock(pVM);
342 return VINF_SUCCESS;
343}
344
345
346/**
347 * VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
348 *
349 * @returns see PGMR3PhysGCPhys2CCPtrExternal
350 * @param pVM The VM handle.
351 * @param pGCPhys Pointer to the guest physical address.
352 * @param ppv Where to store the mapping address.
353 * @param pLock Where to store the lock.
354 */
355static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
356{
357 /*
358 * Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
359 * an access handler after it succeeds.
360 */
361 int rc = pgmLock(pVM);
362 AssertRCReturn(rc, rc);
363
364 rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
365 if (RT_SUCCESS(rc))
366 {
367 PPGMPAGEMAPTLBE pTlbe;
368 int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
369 AssertFatalRC(rc2);
370 PPGMPAGE pPage = pTlbe->pPage;
371#if 1
372 if (PGM_PAGE_IS_MMIO(pPage))
373#else
374 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
375#endif
376 {
377 PGMPhysReleasePageMappingLock(pVM, pLock);
378 rc = VERR_PGM_PHYS_PAGE_RESERVED;
379 }
380 }
381
382 pgmUnlock(pVM);
383 return rc;
384}
385
386
387/**
388 * Requests the mapping of a guest page into ring-3, external threads.
389 *
390 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
391 * release it.
392 *
393 * This API will assume your intention is to write to the page, and will
394 * therefore replace shared and zero pages. If you do not intend to modify the
395 * page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
396 *
397 * @returns VBox status code.
398 * @retval VINF_SUCCESS on success.
399 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
400 * backing or if the page has any active access handlers. The caller
401 * must fall back on using PGMR3PhysWriteExternal.
402 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
403 *
404 * @param pVM The VM handle.
405 * @param GCPhys The guest physical address of the page that should be mapped.
406 * @param ppv Where to store the address corresponding to GCPhys.
407 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
408 *
409 * @remark Avoid calling this API from within critical sections (other than the
410 * PGM one) because of the deadlock risk when we have to delegating the
411 * task to an EMT.
412 * @thread Any.
413 */
414VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
415{
416 AssertPtr(ppv);
417 AssertPtr(pLock);
418
419 int rc = pgmLock(pVM);
420 AssertRCReturn(rc, rc);
421
422 /*
423 * Query the Physical TLB entry for the page (may fail).
424 */
425 PPGMPAGEMAPTLBE pTlbe;
426 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
427 if (RT_SUCCESS(rc))
428 {
429 PPGMPAGE pPage = pTlbe->pPage;
430#if 1
431 if (PGM_PAGE_IS_MMIO(pPage))
432 rc = VERR_PGM_PHYS_PAGE_RESERVED;
433#else
434 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
435 rc = VERR_PGM_PHYS_PAGE_RESERVED;
436#endif
437 else
438 {
439 /*
440 * If the page is shared, the zero page, or being write monitored
441 * it must be converted to an page that's writable if possible.
442 * This has to be done on an EMT.
443 */
444 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
445 {
446 pgmUnlock(pVM);
447
448 PVMREQ pReq = NULL;
449 rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
450 (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4, pVM, &GCPhys, ppv, pLock);
451 if (RT_SUCCESS(rc))
452 {
453 rc = pReq->iStatus;
454 VMR3ReqFree(pReq);
455 }
456 return rc;
457 }
458
459 /*
460 * Now, just perform the locking and calculate the return address.
461 */
462 PPGMPAGEMAP pMap = pTlbe->pMap;
463 pMap->cRefs++;
464#if 0 /** @todo implement locking properly */
465 if (RT_LIKELY(pPage->cLocks != PGM_PAGE_MAX_LOCKS))
466 if (RT_UNLIKELY(++pPage->cLocks == PGM_PAGE_MAX_LOCKS))
467 {
468 AssertMsgFailed(("%RGp is entering permanent locked state!\n", GCPhys));
469 pMap->cRefs++; /* Extra ref to prevent it from going away. */
470 }
471#endif
472 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
473 pLock->pvPage = pPage;
474 pLock->pvMap = pMap;
475 }
476 }
477
478 pgmUnlock(pVM);
479 return rc;
480}
481
482
483/**
484 * Requests the mapping of a guest page into ring-3, external threads.
485 *
486 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
487 * release it.
488 *
489 * @returns VBox status code.
490 * @retval VINF_SUCCESS on success.
491 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
492 * backing or if the page as an active ALL access handler. The caller
493 * must fall back on using PGMPhysRead.
494 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
495 *
496 * @param pVM The VM handle.
497 * @param GCPhys The guest physical address of the page that should be mapped.
498 * @param ppv Where to store the address corresponding to GCPhys.
499 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
500 *
501 * @remark Avoid calling this API from within critical sections (other than
502 * the PGM one) because of the deadlock risk.
503 * @thread Any.
504 */
505VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
506{
507 int rc = pgmLock(pVM);
508 AssertRCReturn(rc, rc);
509
510 /*
511 * Query the Physical TLB entry for the page (may fail).
512 */
513 PPGMPAGEMAPTLBE pTlbe;
514 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
515 if (RT_SUCCESS(rc))
516 {
517 PPGMPAGE pPage = pTlbe->pPage;
518#if 1
519 /* MMIO pages doesn't have any readable backing. */
520 if (PGM_PAGE_IS_MMIO(pPage))
521 rc = VERR_PGM_PHYS_PAGE_RESERVED;
522#else
523 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
524 rc = VERR_PGM_PHYS_PAGE_RESERVED;
525#endif
526 else
527 {
528 /*
529 * Now, just perform the locking and calculate the return address.
530 */
531 PPGMPAGEMAP pMap = pTlbe->pMap;
532 pMap->cRefs++;
533#if 0 /** @todo implement locking properly */
534 if (RT_LIKELY(pPage->cLocks != PGM_PAGE_MAX_LOCKS))
535 if (RT_UNLIKELY(++pPage->cLocks == PGM_PAGE_MAX_LOCKS))
536 {
537 AssertMsgFailed(("%RGp is entering permanent locked state!\n", GCPhys));
538 pMap->cRefs++; /* Extra ref to prevent it from going away. */
539 }
540#endif
541 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
542 pLock->pvPage = pPage;
543 pLock->pvMap = pMap;
544 }
545 }
546
547 pgmUnlock(pVM);
548 return rc;
549}
550
551
552/**
553 * Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
554 *
555 * Called when anything was relocated.
556 *
557 * @param pVM Pointer to the shared VM structure.
558 */
559void pgmR3PhysRelinkRamRanges(PVM pVM)
560{
561 PPGMRAMRANGE pCur;
562
563#ifdef VBOX_STRICT
564 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
565 {
566 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
567 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
568 Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
569 Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
570 Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
571 Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
572 for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
573 Assert( pCur2 == pCur
574 || strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
575 }
576#endif
577
578 pCur = pVM->pgm.s.pRamRangesR3;
579 if (pCur)
580 {
581 pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
582 pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
583
584 for (; pCur->pNextR3; pCur = pCur->pNextR3)
585 {
586 pCur->pNextR0 = pCur->pNextR3->pSelfR0;
587 pCur->pNextRC = pCur->pNextR3->pSelfRC;
588 }
589
590 Assert(pCur->pNextR0 == NIL_RTR0PTR);
591 Assert(pCur->pNextRC == NIL_RTRCPTR);
592 }
593 else
594 {
595 Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
596 Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
597 }
598}
599
600
601/**
602 * Links a new RAM range into the list.
603 *
604 * @param pVM Pointer to the shared VM structure.
605 * @param pNew Pointer to the new list entry.
606 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
607 */
608static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
609{
610 AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
611 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
612 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
613
614 pgmLock(pVM);
615
616 PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
617 pNew->pNextR3 = pRam;
618 pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
619 pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
620
621 if (pPrev)
622 {
623 pPrev->pNextR3 = pNew;
624 pPrev->pNextR0 = pNew->pSelfR0;
625 pPrev->pNextRC = pNew->pSelfRC;
626 }
627 else
628 {
629 pVM->pgm.s.pRamRangesR3 = pNew;
630 pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
631 pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
632 }
633
634 pgmUnlock(pVM);
635}
636
637
638/**
639 * Unlink an existing RAM range from the list.
640 *
641 * @param pVM Pointer to the shared VM structure.
642 * @param pRam Pointer to the new list entry.
643 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
644 */
645static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
646{
647 Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
648 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
649 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
650
651 pgmLock(pVM);
652
653 PPGMRAMRANGE pNext = pRam->pNextR3;
654 if (pPrev)
655 {
656 pPrev->pNextR3 = pNext;
657 pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
658 pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
659 }
660 else
661 {
662 Assert(pVM->pgm.s.pRamRangesR3 == pRam);
663 pVM->pgm.s.pRamRangesR3 = pNext;
664 pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
665 pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
666 }
667
668 pgmUnlock(pVM);
669}
670
671
672/**
673 * Unlink an existing RAM range from the list.
674 *
675 * @param pVM Pointer to the shared VM structure.
676 * @param pRam Pointer to the new list entry.
677 */
678static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
679{
680 pgmLock(pVM);
681
682 /* find prev. */
683 PPGMRAMRANGE pPrev = NULL;
684 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
685 while (pCur != pRam)
686 {
687 pPrev = pCur;
688 pCur = pCur->pNextR3;
689 }
690 AssertFatal(pCur);
691
692 pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
693
694 pgmUnlock(pVM);
695}
696
697
698/**
699 * Frees a range of pages, replacing them with ZERO pages of the specified type.
700 *
701 * @returns VBox status code.
702 * @param pVM The VM handle.
703 * @param pRam The RAM range in which the pages resides.
704 * @param GCPhys The address of the first page.
705 * @param GCPhysLast The address of the last page.
706 * @param uType The page type to replace then with.
707 */
708static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
709{
710 uint32_t cPendingPages = 0;
711 PGMMFREEPAGESREQ pReq;
712 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
713 AssertLogRelRCReturn(rc, rc);
714
715 /* Itegerate the pages. */
716 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
717 uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
718 while (cPagesLeft-- > 0)
719 {
720 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
721 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
722
723 PGM_PAGE_SET_TYPE(pPageDst, uType);
724
725 GCPhys += PAGE_SIZE;
726 pPageDst++;
727 }
728
729 if (cPendingPages)
730 {
731 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
732 AssertLogRelRCReturn(rc, rc);
733 }
734 GMMR3FreePagesCleanup(pReq);
735
736 return rc;
737}
738
739
740/**
741 * PGMR3PhysRegisterRam worker that initializes and links a RAM range.
742 *
743 * @param pVM The VM handle.
744 * @param pNew The new RAM range.
745 * @param GCPhys The address of the RAM range.
746 * @param GCPhysLast The last address of the RAM range.
747 * @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
748 * if in HMA.
749 * @param R0PtrNew Ditto for R0.
750 * @param pszDesc The description.
751 * @param pPrev The previous RAM range (for linking).
752 */
753static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
754 RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
755{
756 /*
757 * Initialize the range.
758 */
759 pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
760 pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
761 pNew->GCPhys = GCPhys;
762 pNew->GCPhysLast = GCPhysLast;
763 pNew->cb = GCPhysLast - GCPhys + 1;
764 pNew->pszDesc = pszDesc;
765 pNew->fFlags = RCPtrNew != NIL_RTR0PTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
766 pNew->pvR3 = NULL;
767
768 uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
769 RTGCPHYS iPage = cPages;
770 while (iPage-- > 0)
771 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
772
773 /* Update the page count stats. */
774 pVM->pgm.s.cZeroPages += cPages;
775 pVM->pgm.s.cAllPages += cPages;
776
777 /*
778 * Link it.
779 */
780 pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
781}
782
783
784/**
785 * Relocate a floating RAM range.
786 *
787 * @copydoc FNPGMRELOCATE.
788 */
789static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
790{
791 PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
792 Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
793 Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
794
795 switch (enmMode)
796 {
797 case PGMRELOCATECALL_SUGGEST:
798 return true;
799 case PGMRELOCATECALL_RELOCATE:
800 {
801 /* Update myself and then relink all the ranges. */
802 pgmLock(pVM);
803 pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
804 pgmR3PhysRelinkRamRanges(pVM);
805 pgmUnlock(pVM);
806 return true;
807 }
808
809 default:
810 AssertFailedReturn(false);
811 }
812}
813
814
815/**
816 * PGMR3PhysRegisterRam worker that registers a high chunk.
817 *
818 * @returns VBox status code.
819 * @param pVM The VM handle.
820 * @param GCPhys The address of the RAM.
821 * @param cRamPages The number of RAM pages to register.
822 * @param cbChunk The size of the PGMRAMRANGE guest mapping.
823 * @param iChunk The chunk number.
824 * @param pszDesc The RAM range description.
825 * @param ppPrev Previous RAM range pointer. In/Out.
826 */
827static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
828 uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
829 PPGMRAMRANGE *ppPrev)
830{
831 const char *pszDescChunk = iChunk == 0
832 ? pszDesc
833 : MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
834 AssertReturn(pszDescChunk, VERR_NO_MEMORY);
835
836 /*
837 * Allocate memory for the new chunk.
838 */
839 size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
840 PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
841 AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
842 RTR0PTR R0PtrChunk = NIL_RTR0PTR;
843 void *pvChunk = NULL;
844 int rc = SUPR3PageAllocEx(cChunkPages, 0 /*fFlags*/, &pvChunk,
845#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
846 VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
847#else
848 NULL,
849#endif
850 paChunkPages);
851 if (RT_SUCCESS(rc))
852 {
853#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
854 if (!VMMIsHwVirtExtForced(pVM))
855 R0PtrChunk = NIL_RTR0PTR;
856#else
857 R0PtrChunk = (uintptr_t)pvChunk;
858#endif
859 memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
860
861 PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
862
863 /*
864 * Create a mapping and map the pages into it.
865 * We push these in below the HMA.
866 */
867 RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
868 rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /*fFlags*/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
869 if (RT_SUCCESS(rc))
870 {
871 pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
872
873 RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
874 RTGCPTR GCPtrPage = GCPtrChunk;
875 for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
876 rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
877 if (RT_SUCCESS(rc))
878 {
879 /*
880 * Ok, init and link the range.
881 */
882 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
883 (RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
884 *ppPrev = pNew;
885 }
886 }
887
888 if (RT_FAILURE(rc))
889 SUPR3PageFreeEx(pvChunk, cChunkPages);
890 }
891
892 RTMemTmpFree(paChunkPages);
893 return rc;
894}
895
896
897/**
898 * Sets up a range RAM.
899 *
900 * This will check for conflicting registrations, make a resource
901 * reservation for the memory (with GMM), and setup the per-page
902 * tracking structures (PGMPAGE).
903 *
904 * @returns VBox stutus code.
905 * @param pVM Pointer to the shared VM structure.
906 * @param GCPhys The physical address of the RAM.
907 * @param cb The size of the RAM.
908 * @param pszDesc The description - not copied, so, don't free or change it.
909 */
910VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
911{
912 /*
913 * Validate input.
914 */
915 Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
916 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
917 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
918 AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
919 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
920 AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
921 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
922 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
923
924 pgmLock(pVM);
925
926 /*
927 * Find range location and check for conflicts.
928 * (We don't lock here because the locking by EMT is only required on update.)
929 */
930 PPGMRAMRANGE pPrev = NULL;
931 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
932 while (pRam && GCPhysLast >= pRam->GCPhys)
933 {
934 if ( GCPhysLast >= pRam->GCPhys
935 && GCPhys <= pRam->GCPhysLast)
936 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
937 GCPhys, GCPhysLast, pszDesc,
938 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
939 VERR_PGM_RAM_CONFLICT);
940
941 /* next */
942 pPrev = pRam;
943 pRam = pRam->pNextR3;
944 }
945
946 /*
947 * Register it with GMM (the API bitches).
948 */
949 const RTGCPHYS cPages = cb >> PAGE_SHIFT;
950 int rc = MMR3IncreaseBaseReservation(pVM, cPages);
951 if (RT_FAILURE(rc))
952 {
953 pgmUnlock(pVM);
954 return rc;
955 }
956
957 if ( GCPhys >= _4G
958 && cPages > 256)
959 {
960 /*
961 * The PGMRAMRANGE structures for the high memory can get very big.
962 * In order to avoid SUPR3PageAllocEx allocation failures due to the
963 * allocation size limit there and also to avoid being unable to find
964 * guest mapping space for them, we split this memory up into 4MB in
965 * (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
966 * mode.
967 *
968 * The first and last page of each mapping are guard pages and marked
969 * not-present. So, we've got 4186112 and 16769024 bytes available for
970 * the PGMRAMRANGE structure.
971 *
972 * Note! The sizes used here will influence the saved state.
973 */
974 uint32_t cbChunk;
975 uint32_t cPagesPerChunk;
976 if (VMMIsHwVirtExtForced(pVM))
977 {
978 cbChunk = 16U*_1M;
979 cPagesPerChunk = 1048048; /* max ~1048059 */
980 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U*_1M - PAGE_SIZE * 2);
981 }
982 else
983 {
984 cbChunk = 4U*_1M;
985 cPagesPerChunk = 261616; /* max ~261627 */
986 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U*_1M - PAGE_SIZE * 2);
987 }
988 AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
989
990 RTGCPHYS cPagesLeft = cPages;
991 RTGCPHYS GCPhysChunk = GCPhys;
992 uint32_t iChunk = 0;
993 while (cPagesLeft > 0)
994 {
995 uint32_t cPagesInChunk = cPagesLeft;
996 if (cPagesInChunk > cPagesPerChunk)
997 cPagesInChunk = cPagesPerChunk;
998
999 rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1000 AssertRCReturn(rc, rc);
1001
1002 /* advance */
1003 GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1004 cPagesLeft -= cPagesInChunk;
1005 iChunk++;
1006 }
1007 }
1008 else
1009 {
1010 /*
1011 * Allocate, initialize and link the new RAM range.
1012 */
1013 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1014 PPGMRAMRANGE pNew;
1015 rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1016 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1017
1018 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1019 }
1020 pgmUnlock(pVM);
1021
1022 /*
1023 * Notify REM.
1024 */
1025 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1026
1027 return VINF_SUCCESS;
1028}
1029
1030
1031/**
1032 * Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1033 *
1034 * We do this late in the init process so that all the ROM and MMIO ranges have
1035 * been registered already and we don't go wasting memory on them.
1036 *
1037 * @returns VBox status code.
1038 *
1039 * @param pVM Pointer to the shared VM structure.
1040 */
1041int pgmR3PhysRamPreAllocate(PVM pVM)
1042{
1043 Assert(pVM->pgm.s.fRamPreAlloc);
1044 Log(("pgmR3PhysRamPreAllocate: enter\n"));
1045
1046 /*
1047 * Walk the RAM ranges and allocate all RAM pages, halt at
1048 * the first allocation error.
1049 */
1050 uint64_t cPages = 0;
1051 uint64_t NanoTS = RTTimeNanoTS();
1052 pgmLock(pVM);
1053 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1054 {
1055 PPGMPAGE pPage = &pRam->aPages[0];
1056 RTGCPHYS GCPhys = pRam->GCPhys;
1057 uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1058 while (cLeft-- > 0)
1059 {
1060 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1061 {
1062 switch (PGM_PAGE_GET_STATE(pPage))
1063 {
1064 case PGM_PAGE_STATE_ZERO:
1065 {
1066 int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1067 if (RT_FAILURE(rc))
1068 {
1069 LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1070 pgmUnlock(pVM);
1071 return rc;
1072 }
1073 cPages++;
1074 break;
1075 }
1076
1077 case PGM_PAGE_STATE_ALLOCATED:
1078 case PGM_PAGE_STATE_WRITE_MONITORED:
1079 case PGM_PAGE_STATE_SHARED:
1080 /* nothing to do here. */
1081 break;
1082 }
1083 }
1084
1085 /* next */
1086 pPage++;
1087 GCPhys += PAGE_SIZE;
1088 }
1089 }
1090 pgmUnlock(pVM);
1091 NanoTS = RTTimeNanoTS() - NanoTS;
1092
1093 LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1094 Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1095 return VINF_SUCCESS;
1096}
1097
1098
1099/**
1100 * Resets (zeros) the RAM.
1101 *
1102 * ASSUMES that the caller owns the PGM lock.
1103 *
1104 * @returns VBox status code.
1105 * @param pVM Pointer to the shared VM structure.
1106 */
1107int pgmR3PhysRamReset(PVM pVM)
1108{
1109 Assert(PGMIsLockOwner(pVM));
1110 /*
1111 * We batch up pages before freeing them.
1112 */
1113 uint32_t cPendingPages = 0;
1114 PGMMFREEPAGESREQ pReq;
1115 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1116 AssertLogRelRCReturn(rc, rc);
1117
1118 /*
1119 * Walk the ram ranges.
1120 */
1121 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1122 {
1123 uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1124 AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1125
1126 if (!pVM->pgm.s.fRamPreAlloc)
1127 {
1128 /* Replace all RAM pages by ZERO pages. */
1129 while (iPage-- > 0)
1130 {
1131 PPGMPAGE pPage = &pRam->aPages[iPage];
1132 switch (PGM_PAGE_GET_TYPE(pPage))
1133 {
1134 case PGMPAGETYPE_RAM:
1135 if (!PGM_PAGE_IS_ZERO(pPage))
1136 {
1137 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1138 AssertLogRelRCReturn(rc, rc);
1139 }
1140 break;
1141
1142 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1143 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1144 break;
1145
1146 case PGMPAGETYPE_MMIO2:
1147 case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1148 case PGMPAGETYPE_ROM:
1149 case PGMPAGETYPE_MMIO:
1150 break;
1151 default:
1152 AssertFailed();
1153 }
1154 } /* for each page */
1155 }
1156 else
1157 {
1158 /* Zero the memory. */
1159 while (iPage-- > 0)
1160 {
1161 PPGMPAGE pPage = &pRam->aPages[iPage];
1162 switch (PGM_PAGE_GET_TYPE(pPage))
1163 {
1164 case PGMPAGETYPE_RAM:
1165 switch (PGM_PAGE_GET_STATE(pPage))
1166 {
1167 case PGM_PAGE_STATE_ZERO:
1168 break;
1169 case PGM_PAGE_STATE_SHARED:
1170 case PGM_PAGE_STATE_WRITE_MONITORED:
1171 rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1172 AssertLogRelRCReturn(rc, rc);
1173 case PGM_PAGE_STATE_ALLOCATED:
1174 {
1175 void *pvPage;
1176 PPGMPAGEMAP pMapIgnored;
1177 rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pMapIgnored, &pvPage);
1178 AssertLogRelRCReturn(rc, rc);
1179 ASMMemZeroPage(pvPage);
1180 break;
1181 }
1182 }
1183 break;
1184
1185 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1186 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1187 break;
1188
1189 case PGMPAGETYPE_MMIO2:
1190 case PGMPAGETYPE_ROM_SHADOW:
1191 case PGMPAGETYPE_ROM:
1192 case PGMPAGETYPE_MMIO:
1193 break;
1194 default:
1195 AssertFailed();
1196
1197 }
1198 } /* for each page */
1199 }
1200
1201 }
1202
1203 /*
1204 * Finish off any pages pending freeing.
1205 */
1206 if (cPendingPages)
1207 {
1208 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1209 AssertLogRelRCReturn(rc, rc);
1210 }
1211 GMMR3FreePagesCleanup(pReq);
1212
1213 return VINF_SUCCESS;
1214}
1215
1216
1217/**
1218 * This is the interface IOM is using to register an MMIO region.
1219 *
1220 * It will check for conflicts and ensure that a RAM range structure
1221 * is present before calling the PGMR3HandlerPhysicalRegister API to
1222 * register the callbacks.
1223 *
1224 * @returns VBox status code.
1225 *
1226 * @param pVM Pointer to the shared VM structure.
1227 * @param GCPhys The start of the MMIO region.
1228 * @param cb The size of the MMIO region.
1229 * @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1230 * @param pvUserR3 The user argument for R3.
1231 * @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1232 * @param pvUserR0 The user argument for R0.
1233 * @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1234 * @param pvUserRC The user argument for RC.
1235 * @param pszDesc The description of the MMIO region.
1236 */
1237VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1238 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1239 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1240 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1241 R3PTRTYPE(const char *) pszDesc)
1242{
1243 /*
1244 * Assert on some assumption.
1245 */
1246 VM_ASSERT_EMT(pVM);
1247 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1248 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1249 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1250 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1251
1252 /*
1253 * Make sure there's a RAM range structure for the region.
1254 */
1255 int rc;
1256 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1257 bool fRamExists = false;
1258 PPGMRAMRANGE pRamPrev = NULL;
1259 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1260 while (pRam && GCPhysLast >= pRam->GCPhys)
1261 {
1262 if ( GCPhysLast >= pRam->GCPhys
1263 && GCPhys <= pRam->GCPhysLast)
1264 {
1265 /* Simplification: all within the same range. */
1266 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1267 && GCPhysLast <= pRam->GCPhysLast,
1268 ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1269 GCPhys, GCPhysLast, pszDesc,
1270 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1271 VERR_PGM_RAM_CONFLICT);
1272
1273 /* Check that it's all RAM or MMIO pages. */
1274 PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1275 uint32_t cLeft = cb >> PAGE_SHIFT;
1276 while (cLeft-- > 0)
1277 {
1278 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1279 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1280 ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1281 GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1282 VERR_PGM_RAM_CONFLICT);
1283 pPage++;
1284 }
1285
1286 /* Looks good. */
1287 fRamExists = true;
1288 break;
1289 }
1290
1291 /* next */
1292 pRamPrev = pRam;
1293 pRam = pRam->pNextR3;
1294 }
1295 PPGMRAMRANGE pNew;
1296 if (fRamExists)
1297 {
1298 pNew = NULL;
1299
1300 /*
1301 * Make all the pages in the range MMIO/ZERO pages, freeing any
1302 * RAM pages currently mapped here. This might not be 100% correct
1303 * for PCI memory, but we're doing the same thing for MMIO2 pages.
1304 */
1305 rc = pgmLock(pVM);
1306 if (RT_SUCCESS(rc))
1307 {
1308 rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1309 pgmUnlock(pVM);
1310 }
1311 AssertRCReturn(rc, rc);
1312 }
1313 else
1314 {
1315 pgmLock(pVM);
1316
1317 /*
1318 * No RAM range, insert an ad-hoc one.
1319 *
1320 * Note that we don't have to tell REM about this range because
1321 * PGMHandlerPhysicalRegisterEx will do that for us.
1322 */
1323 Log(("PGMR3PhysMMIORegister: Adding ad-hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1324
1325 const uint32_t cPages = cb >> PAGE_SHIFT;
1326 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1327 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1328 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1329
1330 /* Initialize the range. */
1331 pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1332 pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1333 pNew->GCPhys = GCPhys;
1334 pNew->GCPhysLast = GCPhysLast;
1335 pNew->cb = cb;
1336 pNew->pszDesc = pszDesc;
1337 pNew->fFlags = 0; /** @todo add some kind of ad-hoc flag? */
1338
1339 pNew->pvR3 = NULL;
1340
1341 uint32_t iPage = cPages;
1342 while (iPage-- > 0)
1343 PGM_PAGE_INIT_ZERO_REAL(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1344 Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1345
1346 /* update the page count stats. */
1347 pVM->pgm.s.cZeroPages += cPages;
1348 pVM->pgm.s.cAllPages += cPages;
1349
1350 /* link it */
1351 pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1352
1353 pgmUnlock(pVM);
1354 }
1355
1356 /*
1357 * Register the access handler.
1358 */
1359 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1360 pfnHandlerR3, pvUserR3,
1361 pfnHandlerR0, pvUserR0,
1362 pfnHandlerRC, pvUserRC, pszDesc);
1363 if ( RT_FAILURE(rc)
1364 && !fRamExists)
1365 {
1366 pVM->pgm.s.cZeroPages -= cb >> PAGE_SHIFT;
1367 pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1368
1369 /* remove the ad-hoc range. */
1370 pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1371 pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1372 MMHyperFree(pVM, pRam);
1373 }
1374
1375 return rc;
1376}
1377
1378
1379/**
1380 * This is the interface IOM is using to register an MMIO region.
1381 *
1382 * It will take care of calling PGMHandlerPhysicalDeregister and clean up
1383 * any ad-hoc PGMRAMRANGE left behind.
1384 *
1385 * @returns VBox status code.
1386 * @param pVM Pointer to the shared VM structure.
1387 * @param GCPhys The start of the MMIO region.
1388 * @param cb The size of the MMIO region.
1389 */
1390VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1391{
1392 VM_ASSERT_EMT(pVM);
1393
1394 /*
1395 * First deregister the handler, then check if we should remove the ram range.
1396 */
1397 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1398 if (RT_SUCCESS(rc))
1399 {
1400 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1401 PPGMRAMRANGE pRamPrev = NULL;
1402 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1403 while (pRam && GCPhysLast >= pRam->GCPhys)
1404 {
1405 /** @todo We're being a bit too careful here. rewrite. */
1406 if ( GCPhysLast == pRam->GCPhysLast
1407 && GCPhys == pRam->GCPhys)
1408 {
1409 Assert(pRam->cb == cb);
1410
1411 /*
1412 * See if all the pages are dead MMIO pages.
1413 */
1414 uint32_t const cPages = cb >> PAGE_SHIFT;
1415 bool fAllMMIO = true;
1416 uint32_t iPage = 0;
1417 uint32_t cLeft = cPages;
1418 while (cLeft-- > 0)
1419 {
1420 PPGMPAGE pPage = &pRam->aPages[iPage];
1421 if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1422 /*|| not-out-of-action later */)
1423 {
1424 fAllMMIO = false;
1425 Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1426 AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1427 break;
1428 }
1429 Assert(PGM_PAGE_IS_ZERO(pPage));
1430 pPage++;
1431 }
1432 if (fAllMMIO)
1433 {
1434 /*
1435 * Ad-hoc range, unlink and free it.
1436 */
1437 Log(("PGMR3PhysMMIODeregister: Freeing ad-hoc MMIO range for %RGp-%RGp %s\n",
1438 GCPhys, GCPhysLast, pRam->pszDesc));
1439
1440 pVM->pgm.s.cAllPages -= cPages;
1441 pVM->pgm.s.cZeroPages -= cPages;
1442
1443 pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1444 pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1445 MMHyperFree(pVM, pRam);
1446 break;
1447 }
1448 }
1449
1450 /*
1451 * Range match? It will all be within one range (see PGMAllHandler.cpp).
1452 */
1453 if ( GCPhysLast >= pRam->GCPhys
1454 && GCPhys <= pRam->GCPhysLast)
1455 {
1456 Assert(GCPhys >= pRam->GCPhys);
1457 Assert(GCPhysLast <= pRam->GCPhysLast);
1458
1459 /*
1460 * Turn the pages back into RAM pages.
1461 */
1462 uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1463 uint32_t cLeft = cb >> PAGE_SHIFT;
1464 while (cLeft--)
1465 {
1466 PPGMPAGE pPage = &pRam->aPages[iPage];
1467 AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1468 AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1469 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1470 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1471 }
1472 break;
1473 }
1474
1475 /* next */
1476 pRamPrev = pRam;
1477 pRam = pRam->pNextR3;
1478 }
1479 }
1480
1481 return rc;
1482}
1483
1484
1485/**
1486 * Locate a MMIO2 range.
1487 *
1488 * @returns Pointer to the MMIO2 range.
1489 * @param pVM Pointer to the shared VM structure.
1490 * @param pDevIns The device instance owning the region.
1491 * @param iRegion The region.
1492 */
1493DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1494{
1495 /*
1496 * Search the list.
1497 */
1498 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1499 if ( pCur->pDevInsR3 == pDevIns
1500 && pCur->iRegion == iRegion)
1501 return pCur;
1502 return NULL;
1503}
1504
1505
1506/**
1507 * Allocate and register an MMIO2 region.
1508 *
1509 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1510 * RAM associated with a device. It is also non-shared memory with a
1511 * permanent ring-3 mapping and page backing (presently).
1512 *
1513 * A MMIO2 range may overlap with base memory if a lot of RAM
1514 * is configured for the VM, in which case we'll drop the base
1515 * memory pages. Presently we will make no attempt to preserve
1516 * anything that happens to be present in the base memory that
1517 * is replaced, this is of course incorrectly but it's too much
1518 * effort.
1519 *
1520 * @returns VBox status code.
1521 * @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1522 * @retval VERR_ALREADY_EXISTS if the region already exists.
1523 *
1524 * @param pVM Pointer to the shared VM structure.
1525 * @param pDevIns The device instance owning the region.
1526 * @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1527 * this number has to be the number of that region. Otherwise
1528 * it can be any number safe UINT8_MAX.
1529 * @param cb The size of the region. Must be page aligned.
1530 * @param fFlags Reserved for future use, must be zero.
1531 * @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1532 * @param pszDesc The description.
1533 */
1534VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)
1535{
1536 /*
1537 * Validate input.
1538 */
1539 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1540 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1541 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1542 AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1543 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1544 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1545 AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1546 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1547 AssertReturn(cb, VERR_INVALID_PARAMETER);
1548 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1549
1550 const uint32_t cPages = cb >> PAGE_SHIFT;
1551 AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1552 AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1553
1554 /*
1555 * For the 2nd+ instance, mangle the description string so it's unique.
1556 */
1557 if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
1558 {
1559 pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1560 if (!pszDesc)
1561 return VERR_NO_MEMORY;
1562 }
1563
1564 /*
1565 * Try reserve and allocate the backing memory first as this is what is
1566 * most likely to fail.
1567 */
1568 int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1569 if (RT_SUCCESS(rc))
1570 {
1571 void *pvPages;
1572 PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1573 if (RT_SUCCESS(rc))
1574 rc = SUPR3PageAllocEx(cPages, 0 /*fFlags*/, &pvPages, NULL /*pR0Ptr*/, paPages);
1575 if (RT_SUCCESS(rc))
1576 {
1577 memset(pvPages, 0, cPages * PAGE_SIZE);
1578
1579 /*
1580 * Create the MMIO2 range record for it.
1581 */
1582 const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1583 PPGMMMIO2RANGE pNew;
1584 rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1585 AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1586 if (RT_SUCCESS(rc))
1587 {
1588 pNew->pDevInsR3 = pDevIns;
1589 pNew->pvR3 = pvPages;
1590 //pNew->pNext = NULL;
1591 //pNew->fMapped = false;
1592 //pNew->fOverlapping = false;
1593 pNew->iRegion = iRegion;
1594 pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1595 pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1596 pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1597 pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1598 pNew->RamRange.pszDesc = pszDesc;
1599 pNew->RamRange.cb = cb;
1600 //pNew->RamRange.fFlags = 0; /// @todo MMIO2 flag?
1601
1602 pNew->RamRange.pvR3 = pvPages;
1603
1604 uint32_t iPage = cPages;
1605 while (iPage-- > 0)
1606 {
1607 PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1608 paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
1609 PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1610 }
1611
1612 /* update page count stats */
1613 pVM->pgm.s.cAllPages += cPages;
1614 pVM->pgm.s.cPrivatePages += cPages;
1615
1616 /*
1617 * Link it into the list.
1618 * Since there is no particular order, just push it.
1619 */
1620 pgmLock(pVM);
1621 pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1622 pVM->pgm.s.pMmio2RangesR3 = pNew;
1623 pgmUnlock(pVM);
1624
1625 *ppv = pvPages;
1626 RTMemTmpFree(paPages);
1627 return VINF_SUCCESS;
1628 }
1629
1630 SUPR3PageFreeEx(pvPages, cPages);
1631 }
1632 RTMemTmpFree(paPages);
1633 MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1634 }
1635 if (pDevIns->iInstance > 0)
1636 MMR3HeapFree((void *)pszDesc);
1637 return rc;
1638}
1639
1640
1641/**
1642 * Deregisters and frees an MMIO2 region.
1643 *
1644 * Any physical (and virtual) access handlers registered for the region must
1645 * be deregistered before calling this function.
1646 *
1647 * @returns VBox status code.
1648 * @param pVM Pointer to the shared VM structure.
1649 * @param pDevIns The device instance owning the region.
1650 * @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1651 */
1652VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1653{
1654 /*
1655 * Validate input.
1656 */
1657 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1658 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1659 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1660
1661 pgmLock(pVM);
1662 int rc = VINF_SUCCESS;
1663 unsigned cFound = 0;
1664 PPGMMMIO2RANGE pPrev = NULL;
1665 PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1666 while (pCur)
1667 {
1668 if ( pCur->pDevInsR3 == pDevIns
1669 && ( iRegion == UINT32_MAX
1670 || pCur->iRegion == iRegion))
1671 {
1672 cFound++;
1673
1674 /*
1675 * Unmap it if it's mapped.
1676 */
1677 if (pCur->fMapped)
1678 {
1679 int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1680 AssertRC(rc2);
1681 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1682 rc = rc2;
1683 }
1684
1685 /*
1686 * Unlink it
1687 */
1688 PPGMMMIO2RANGE pNext = pCur->pNextR3;
1689 if (pPrev)
1690 pPrev->pNextR3 = pNext;
1691 else
1692 pVM->pgm.s.pMmio2RangesR3 = pNext;
1693 pCur->pNextR3 = NULL;
1694
1695 /*
1696 * Free the memory.
1697 */
1698 int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1699 AssertRC(rc2);
1700 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1701 rc = rc2;
1702
1703 uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1704 rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1705 AssertRC(rc2);
1706 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1707 rc = rc2;
1708
1709 /* we're leaking hyper memory here if done at runtime. */
1710 Assert( VMR3GetState(pVM) == VMSTATE_OFF
1711 || VMR3GetState(pVM) == VMSTATE_DESTROYING
1712 || VMR3GetState(pVM) == VMSTATE_TERMINATED
1713 || VMR3GetState(pVM) == VMSTATE_CREATING);
1714 /*rc = MMHyperFree(pVM, pCur);
1715 AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1716
1717
1718 /* update page count stats */
1719 pVM->pgm.s.cAllPages -= cPages;
1720 pVM->pgm.s.cPrivatePages -= cPages;
1721
1722 /* next */
1723 pCur = pNext;
1724 }
1725 else
1726 {
1727 pPrev = pCur;
1728 pCur = pCur->pNextR3;
1729 }
1730 }
1731 pgmUnlock(pVM);
1732 return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1733}
1734
1735
1736/**
1737 * Maps a MMIO2 region.
1738 *
1739 * This is done when a guest / the bios / state loading changes the
1740 * PCI config. The replacing of base memory has the same restrictions
1741 * as during registration, of course.
1742 *
1743 * @returns VBox status code.
1744 *
1745 * @param pVM Pointer to the shared VM structure.
1746 * @param pDevIns The
1747 */
1748VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1749{
1750 /*
1751 * Validate input
1752 */
1753 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1754 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1755 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1756 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1757 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1758 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1759
1760 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1761 AssertReturn(pCur, VERR_NOT_FOUND);
1762 AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
1763 Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
1764 Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
1765
1766 const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
1767 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1768
1769 /*
1770 * Find our location in the ram range list, checking for
1771 * restriction we don't bother implementing yet (partially overlapping).
1772 */
1773 bool fRamExists = false;
1774 PPGMRAMRANGE pRamPrev = NULL;
1775 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1776 while (pRam && GCPhysLast >= pRam->GCPhys)
1777 {
1778 if ( GCPhys <= pRam->GCPhysLast
1779 && GCPhysLast >= pRam->GCPhys)
1780 {
1781 /* completely within? */
1782 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1783 && GCPhysLast <= pRam->GCPhysLast,
1784 ("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
1785 GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
1786 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1787 VERR_PGM_RAM_CONFLICT);
1788 fRamExists = true;
1789 break;
1790 }
1791
1792 /* next */
1793 pRamPrev = pRam;
1794 pRam = pRam->pNextR3;
1795 }
1796 if (fRamExists)
1797 {
1798 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1799 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1800 while (cPagesLeft-- > 0)
1801 {
1802 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1803 ("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
1804 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
1805 VERR_PGM_RAM_CONFLICT);
1806 pPage++;
1807 }
1808 }
1809 Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
1810 GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
1811
1812 /*
1813 * Make the changes.
1814 */
1815 pgmLock(pVM);
1816
1817 pCur->RamRange.GCPhys = GCPhys;
1818 pCur->RamRange.GCPhysLast = GCPhysLast;
1819 pCur->fMapped = true;
1820 pCur->fOverlapping = fRamExists;
1821
1822 if (fRamExists)
1823 {
1824/** @todo use pgmR3PhysFreePageRange here. */
1825 uint32_t cPendingPages = 0;
1826 PGMMFREEPAGESREQ pReq;
1827 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1828 AssertLogRelRCReturn(rc, rc);
1829
1830 /* replace the pages, freeing all present RAM pages. */
1831 PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
1832 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1833 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1834 while (cPagesLeft-- > 0)
1835 {
1836 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
1837 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1838
1839 RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
1840 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
1841 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
1842 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
1843
1844 pVM->pgm.s.cZeroPages--;
1845 GCPhys += PAGE_SIZE;
1846 pPageSrc++;
1847 pPageDst++;
1848 }
1849
1850 if (cPendingPages)
1851 {
1852 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1853 AssertLogRelRCReturn(rc, rc);
1854 }
1855 GMMR3FreePagesCleanup(pReq);
1856 pgmUnlock(pVM);
1857 }
1858 else
1859 {
1860 RTGCPHYS cb = pCur->RamRange.cb;
1861
1862 /* link in the ram range */
1863 pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
1864 pgmUnlock(pVM);
1865
1866 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
1867 }
1868
1869 return VINF_SUCCESS;
1870}
1871
1872
1873/**
1874 * Unmaps a MMIO2 region.
1875 *
1876 * This is done when a guest / the bios / state loading changes the
1877 * PCI config. The replacing of base memory has the same restrictions
1878 * as during registration, of course.
1879 */
1880VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1881{
1882 bool fInformREM = false;
1883 RTGCPHYS GCPhysRangeREM;
1884 RTGCPHYS cbRangeREM;
1885
1886 /*
1887 * Validate input
1888 */
1889 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1890 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1891 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1892 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1893 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1894 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1895
1896 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1897 AssertReturn(pCur, VERR_NOT_FOUND);
1898 AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
1899 AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
1900 Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
1901
1902 Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
1903 pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
1904
1905 /*
1906 * Unmap it.
1907 */
1908 pgmLock(pVM);
1909
1910 if (pCur->fOverlapping)
1911 {
1912 /* Restore the RAM pages we've replaced. */
1913 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1914 while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
1915 pRam = pRam->pNextR3;
1916
1917 RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
1918 Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
1919 PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1920 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1921 while (cPagesLeft-- > 0)
1922 {
1923 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
1924 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
1925 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
1926 PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
1927
1928 pVM->pgm.s.cZeroPages++;
1929 pPageDst++;
1930 }
1931 }
1932 else
1933 {
1934 GCPhysRangeREM = pCur->RamRange.GCPhys;
1935 cbRangeREM = pCur->RamRange.cb;
1936 fInformREM = true;
1937
1938 pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
1939 }
1940
1941 pCur->RamRange.GCPhys = NIL_RTGCPHYS;
1942 pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
1943 pCur->fOverlapping = false;
1944 pCur->fMapped = false;
1945
1946 pgmUnlock(pVM);
1947
1948 if (fInformREM)
1949 REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
1950
1951 return VINF_SUCCESS;
1952}
1953
1954
1955/**
1956 * Checks if the given address is an MMIO2 base address or not.
1957 *
1958 * @returns true/false accordingly.
1959 * @param pVM Pointer to the shared VM structure.
1960 * @param pDevIns The owner of the memory, optional.
1961 * @param GCPhys The address to check.
1962 */
1963VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
1964{
1965 /*
1966 * Validate input
1967 */
1968 VM_ASSERT_EMT_RETURN(pVM, false);
1969 AssertPtrReturn(pDevIns, false);
1970 AssertReturn(GCPhys != NIL_RTGCPHYS, false);
1971 AssertReturn(GCPhys != 0, false);
1972 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
1973
1974 /*
1975 * Search the list.
1976 */
1977 pgmLock(pVM);
1978 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1979 if (pCur->RamRange.GCPhys == GCPhys)
1980 {
1981 Assert(pCur->fMapped);
1982 pgmUnlock(pVM);
1983 return true;
1984 }
1985 pgmUnlock(pVM);
1986 return false;
1987}
1988
1989
1990/**
1991 * Gets the HC physical address of a page in the MMIO2 region.
1992 *
1993 * This is API is intended for MMHyper and shouldn't be called
1994 * by anyone else...
1995 *
1996 * @returns VBox status code.
1997 * @param pVM Pointer to the shared VM structure.
1998 * @param pDevIns The owner of the memory, optional.
1999 * @param iRegion The region.
2000 * @param off The page expressed an offset into the MMIO2 region.
2001 * @param pHCPhys Where to store the result.
2002 */
2003VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2004{
2005 /*
2006 * Validate input
2007 */
2008 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2009 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2010 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2011
2012 pgmLock(pVM);
2013 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2014 AssertReturn(pCur, VERR_NOT_FOUND);
2015 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2016
2017 PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2018 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2019 pgmUnlock(pVM);
2020 return VINF_SUCCESS;
2021}
2022
2023
2024/**
2025 * Maps a portion of an MMIO2 region into kernel space (host).
2026 *
2027 * The kernel mapping will become invalid when the MMIO2 memory is deregistered
2028 * or the VM is terminated.
2029 *
2030 * @return VBox status code.
2031 *
2032 * @param pVM Pointer to the shared VM structure.
2033 * @param pDevIns The device owning the MMIO2 memory.
2034 * @param iRegion The region.
2035 * @param off The offset into the region. Must be page aligned.
2036 * @param cb The number of bytes to map. Must be page aligned.
2037 * @param pszDesc Mapping description.
2038 * @param pR0Ptr Where to store the R0 address.
2039 */
2040VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2041 const char *pszDesc, PRTR0PTR pR0Ptr)
2042{
2043 /*
2044 * Validate input.
2045 */
2046 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2047 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2048 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2049
2050 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2051 AssertReturn(pCur, VERR_NOT_FOUND);
2052 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2053 AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2054 AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2055
2056 /*
2057 * Pass the request on to the support library/driver.
2058 */
2059 int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2060
2061 return rc;
2062}
2063
2064
2065/**
2066 * Registers a ROM image.
2067 *
2068 * Shadowed ROM images requires double the amount of backing memory, so,
2069 * don't use that unless you have to. Shadowing of ROM images is process
2070 * where we can select where the reads go and where the writes go. On real
2071 * hardware the chipset provides means to configure this. We provide
2072 * PGMR3PhysProtectROM() for this purpose.
2073 *
2074 * A read-only copy of the ROM image will always be kept around while we
2075 * will allocate RAM pages for the changes on demand (unless all memory
2076 * is configured to be preallocated).
2077 *
2078 * @returns VBox status.
2079 * @param pVM VM Handle.
2080 * @param pDevIns The device instance owning the ROM.
2081 * @param GCPhys First physical address in the range.
2082 * Must be page aligned!
2083 * @param cbRange The size of the range (in bytes).
2084 * Must be page aligned!
2085 * @param pvBinary Pointer to the binary data backing the ROM image.
2086 * This must be exactly \a cbRange in size.
2087 * @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2088 * and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2089 * @param pszDesc Pointer to description string. This must not be freed.
2090 *
2091 * @remark There is no way to remove the rom, automatically on device cleanup or
2092 * manually from the device yet. This isn't difficult in any way, it's
2093 * just not something we expect to be necessary for a while.
2094 */
2095VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2096 const void *pvBinary, uint32_t fFlags, const char *pszDesc)
2097{
2098 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2099 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2100
2101 /*
2102 * Validate input.
2103 */
2104 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2105 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2106 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2107 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2108 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2109 AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2110 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2111 AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED | PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2112 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2113
2114 const uint32_t cPages = cb >> PAGE_SHIFT;
2115
2116 /*
2117 * Find the ROM location in the ROM list first.
2118 */
2119 PPGMROMRANGE pRomPrev = NULL;
2120 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2121 while (pRom && GCPhysLast >= pRom->GCPhys)
2122 {
2123 if ( GCPhys <= pRom->GCPhysLast
2124 && GCPhysLast >= pRom->GCPhys)
2125 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2126 GCPhys, GCPhysLast, pszDesc,
2127 pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2128 VERR_PGM_RAM_CONFLICT);
2129 /* next */
2130 pRomPrev = pRom;
2131 pRom = pRom->pNextR3;
2132 }
2133
2134 /*
2135 * Find the RAM location and check for conflicts.
2136 *
2137 * Conflict detection is a bit different than for RAM
2138 * registration since a ROM can be located within a RAM
2139 * range. So, what we have to check for is other memory
2140 * types (other than RAM that is) and that we don't span
2141 * more than one RAM range (layz).
2142 */
2143 bool fRamExists = false;
2144 PPGMRAMRANGE pRamPrev = NULL;
2145 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2146 while (pRam && GCPhysLast >= pRam->GCPhys)
2147 {
2148 if ( GCPhys <= pRam->GCPhysLast
2149 && GCPhysLast >= pRam->GCPhys)
2150 {
2151 /* completely within? */
2152 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2153 && GCPhysLast <= pRam->GCPhysLast,
2154 ("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2155 GCPhys, GCPhysLast, pszDesc,
2156 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2157 VERR_PGM_RAM_CONFLICT);
2158 fRamExists = true;
2159 break;
2160 }
2161
2162 /* next */
2163 pRamPrev = pRam;
2164 pRam = pRam->pNextR3;
2165 }
2166 if (fRamExists)
2167 {
2168 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2169 uint32_t cPagesLeft = cPages;
2170 while (cPagesLeft-- > 0)
2171 {
2172 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2173 ("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2174 pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2175 pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2176 Assert(PGM_PAGE_IS_ZERO(pPage));
2177 pPage++;
2178 }
2179 }
2180
2181 /*
2182 * Update the base memory reservation if necessary.
2183 */
2184 uint32_t cExtraBaseCost = fRamExists ? cPages : 0;
2185 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2186 cExtraBaseCost += cPages;
2187 if (cExtraBaseCost)
2188 {
2189 int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2190 if (RT_FAILURE(rc))
2191 return rc;
2192 }
2193
2194 /*
2195 * Allocate memory for the virgin copy of the RAM.
2196 */
2197 PGMMALLOCATEPAGESREQ pReq;
2198 int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2199 AssertRCReturn(rc, rc);
2200
2201 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2202 {
2203 pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2204 pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2205 pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2206 }
2207
2208 pgmLock(pVM);
2209 rc = GMMR3AllocatePagesPerform(pVM, pReq);
2210 pgmUnlock(pVM);
2211 if (RT_FAILURE(rc))
2212 {
2213 GMMR3AllocatePagesCleanup(pReq);
2214 return rc;
2215 }
2216
2217 /*
2218 * Allocate the new ROM range and RAM range (if necessary).
2219 */
2220 PPGMROMRANGE pRomNew;
2221 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2222 if (RT_SUCCESS(rc))
2223 {
2224 PPGMRAMRANGE pRamNew = NULL;
2225 if (!fRamExists)
2226 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2227 if (RT_SUCCESS(rc))
2228 {
2229 pgmLock(pVM);
2230
2231 /*
2232 * Initialize and insert the RAM range (if required).
2233 */
2234 PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2235 if (!fRamExists)
2236 {
2237 pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2238 pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2239 pRamNew->GCPhys = GCPhys;
2240 pRamNew->GCPhysLast = GCPhysLast;
2241 pRamNew->cb = cb;
2242 pRamNew->pszDesc = pszDesc;
2243 pRamNew->fFlags = 0;
2244 pRamNew->pvR3 = NULL;
2245
2246 PPGMPAGE pPage = &pRamNew->aPages[0];
2247 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2248 {
2249 PGM_PAGE_INIT(pPage,
2250 pReq->aPages[iPage].HCPhysGCPhys,
2251 pReq->aPages[iPage].idPage,
2252 PGMPAGETYPE_ROM,
2253 PGM_PAGE_STATE_ALLOCATED);
2254
2255 pRomPage->Virgin = *pPage;
2256 }
2257
2258 pVM->pgm.s.cAllPages += cPages;
2259 pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2260 }
2261 else
2262 {
2263 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2264 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2265 {
2266 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2267 PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2268 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2269 PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2270
2271 pRomPage->Virgin = *pPage;
2272 }
2273
2274 pRamNew = pRam;
2275
2276 pVM->pgm.s.cZeroPages -= cPages;
2277 }
2278 pVM->pgm.s.cPrivatePages += cPages;
2279
2280 pgmUnlock(pVM);
2281
2282
2283 /*
2284 * !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2285 *
2286 * If it's shadowed we'll register the handler after the ROM notification
2287 * so we get the access handler callbacks that we should. If it isn't
2288 * shadowed we'll do it the other way around to make REM use the built-in
2289 * ROM behavior and not the handler behavior (which is to route all access
2290 * to PGM atm).
2291 */
2292 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2293 {
2294 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2295 rc = PGMR3HandlerPhysicalRegister(pVM,
2296 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2297 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2298 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2299 GCPhys, GCPhysLast,
2300 pgmR3PhysRomWriteHandler, pRomNew,
2301 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2302 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2303 }
2304 else
2305 {
2306 rc = PGMR3HandlerPhysicalRegister(pVM,
2307 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2308 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2309 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2310 GCPhys, GCPhysLast,
2311 pgmR3PhysRomWriteHandler, pRomNew,
2312 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2313 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2314 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2315 }
2316 if (RT_SUCCESS(rc))
2317 {
2318 pgmLock(pVM);
2319
2320 /*
2321 * Copy the image over to the virgin pages.
2322 * This must be done after linking in the RAM range.
2323 */
2324 PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2325 for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2326 {
2327 void *pvDstPage;
2328 PPGMPAGEMAP pMapIgnored;
2329 rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pMapIgnored, &pvDstPage);
2330 if (RT_FAILURE(rc))
2331 {
2332 VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2333 break;
2334 }
2335 memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2336 }
2337 if (RT_SUCCESS(rc))
2338 {
2339 /*
2340 * Initialize the ROM range.
2341 * Note that the Virgin member of the pages has already been initialized above.
2342 */
2343 pRomNew->GCPhys = GCPhys;
2344 pRomNew->GCPhysLast = GCPhysLast;
2345 pRomNew->cb = cb;
2346 pRomNew->fFlags = fFlags;
2347 pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2348 pRomNew->pszDesc = pszDesc;
2349
2350 for (unsigned iPage = 0; iPage < cPages; iPage++)
2351 {
2352 PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2353 pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2354 PGM_PAGE_INIT_ZERO_REAL(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2355 }
2356
2357 /* update the page count stats */
2358 pVM->pgm.s.cZeroPages += cPages;
2359 pVM->pgm.s.cAllPages += cPages;
2360
2361 /*
2362 * Insert the ROM range, tell REM and return successfully.
2363 */
2364 pRomNew->pNextR3 = pRom;
2365 pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2366 pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2367
2368 if (pRomPrev)
2369 {
2370 pRomPrev->pNextR3 = pRomNew;
2371 pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2372 pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2373 }
2374 else
2375 {
2376 pVM->pgm.s.pRomRangesR3 = pRomNew;
2377 pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2378 pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2379 }
2380
2381 GMMR3AllocatePagesCleanup(pReq);
2382 pgmUnlock(pVM);
2383 return VINF_SUCCESS;
2384 }
2385
2386 /* bail out */
2387
2388 pgmUnlock(pVM);
2389 int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2390 AssertRC(rc2);
2391 pgmLock(pVM);
2392 }
2393
2394 if (!fRamExists)
2395 {
2396 pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2397 MMHyperFree(pVM, pRamNew);
2398 }
2399 }
2400 MMHyperFree(pVM, pRomNew);
2401 }
2402
2403 /** @todo Purge the mapping cache or something... */
2404 GMMR3FreeAllocatedPages(pVM, pReq);
2405 GMMR3AllocatePagesCleanup(pReq);
2406 pgmUnlock(pVM);
2407 return rc;
2408}
2409
2410
2411/**
2412 * \#PF Handler callback for ROM write accesses.
2413 *
2414 * @returns VINF_SUCCESS if the handler have carried out the operation.
2415 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2416 * @param pVM VM Handle.
2417 * @param GCPhys The physical address the guest is writing to.
2418 * @param pvPhys The HC mapping of that address.
2419 * @param pvBuf What the guest is reading/writing.
2420 * @param cbBuf How much it's reading/writing.
2421 * @param enmAccessType The access type.
2422 * @param pvUser User argument.
2423 */
2424static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2425{
2426 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2427 const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2428 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2429 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2430 Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2431
2432 if (enmAccessType == PGMACCESSTYPE_READ)
2433 {
2434 switch (pRomPage->enmProt)
2435 {
2436 /*
2437 * Take the default action.
2438 */
2439 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2440 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2441 case PGMROMPROT_READ_ROM_WRITE_RAM:
2442 case PGMROMPROT_READ_RAM_WRITE_RAM:
2443 return VINF_PGM_HANDLER_DO_DEFAULT;
2444
2445 default:
2446 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2447 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2448 VERR_INTERNAL_ERROR);
2449 }
2450 }
2451 else
2452 {
2453 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2454 switch (pRomPage->enmProt)
2455 {
2456 /*
2457 * Ignore writes.
2458 */
2459 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2460 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2461 return VINF_SUCCESS;
2462
2463 /*
2464 * Write to the ram page.
2465 */
2466 case PGMROMPROT_READ_ROM_WRITE_RAM:
2467 case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
2468 {
2469 /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2470 Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2471
2472 /*
2473 * Take the lock, do lazy allocation, map the page and copy the data.
2474 *
2475 * Note that we have to bypass the mapping TLB since it works on
2476 * guest physical addresses and entering the shadow page would
2477 * kind of screw things up...
2478 */
2479 int rc = pgmLock(pVM);
2480 AssertRC(rc);
2481 PPGMPAGE pShadowPage = &pRomPage->Shadow;
2482 if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2483 {
2484 pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2485 AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2486 }
2487
2488 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pShadowPage) != PGM_PAGE_STATE_ALLOCATED))
2489 {
2490 rc = pgmPhysPageMakeWritable(pVM, pShadowPage, GCPhys);
2491 if (RT_FAILURE(rc))
2492 {
2493 pgmUnlock(pVM);
2494 return rc;
2495 }
2496 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* returned */, ("%Rrc\n", rc));
2497 }
2498
2499 void *pvDstPage;
2500 PPGMPAGEMAP pMapIgnored;
2501 int rc2 = pgmPhysPageMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pMapIgnored, &pvDstPage);
2502 if (RT_SUCCESS(rc2))
2503 memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2504 else
2505 rc = rc2;
2506
2507 pgmUnlock(pVM);
2508 return rc;
2509 }
2510
2511 default:
2512 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2513 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2514 VERR_INTERNAL_ERROR);
2515 }
2516 }
2517}
2518
2519
2520/**
2521 * Called by PGMR3Reset to reset the shadow, switch to the virgin,
2522 * and verify that the virgin part is untouched.
2523 *
2524 * This is done after the normal memory has been cleared.
2525 *
2526 * ASSUMES that the caller owns the PGM lock.
2527 *
2528 * @param pVM The VM handle.
2529 */
2530int pgmR3PhysRomReset(PVM pVM)
2531{
2532 Assert(PGMIsLockOwner(pVM));
2533 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2534 {
2535 const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2536
2537 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2538 {
2539 /*
2540 * Reset the physical handler.
2541 */
2542 int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2543 AssertRCReturn(rc, rc);
2544
2545 /*
2546 * What we do with the shadow pages depends on the memory
2547 * preallocation option. If not enabled, we'll just throw
2548 * out all the dirty pages and replace them by the zero page.
2549 */
2550 if (!pVM->pgm.s.fRamPreAlloc)
2551 {
2552 /* Free the dirty pages. */
2553 uint32_t cPendingPages = 0;
2554 PGMMFREEPAGESREQ pReq;
2555 rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2556 AssertRCReturn(rc, rc);
2557
2558 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2559 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
2560 {
2561 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2562 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2563 AssertLogRelRCReturn(rc, rc);
2564 }
2565
2566 if (cPendingPages)
2567 {
2568 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2569 AssertLogRelRCReturn(rc, rc);
2570 }
2571 GMMR3FreePagesCleanup(pReq);
2572 }
2573 else
2574 {
2575 /* clear all the shadow pages. */
2576 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2577 {
2578 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO);
2579
2580 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2581 rc = pgmPhysPageMakeWritable(pVM, &pRom->aPages[iPage].Shadow, GCPhys);
2582 if (RT_FAILURE(rc))
2583 break;
2584
2585 void *pvDstPage;
2586 PPGMPAGEMAP pMapIgnored;
2587 rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pMapIgnored, &pvDstPage);
2588 if (RT_FAILURE(rc))
2589 break;
2590 ASMMemZeroPage(pvDstPage);
2591 }
2592 AssertRCReturn(rc, rc);
2593 }
2594 }
2595
2596#ifdef VBOX_STRICT
2597 /*
2598 * Verify that the virgin page is unchanged if possible.
2599 */
2600 if (pRom->pvOriginal)
2601 {
2602 uint8_t const *pbSrcPage = (uint8_t const *)pRom->pvOriginal;
2603 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2604 {
2605 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2606 PPGMPAGEMAP pMapIgnored;
2607 void *pvDstPage;
2608 int rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pMapIgnored, &pvDstPage);
2609 if (RT_FAILURE(rc))
2610 break;
2611 if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2612 LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2613 GCPhys, pRom->pszDesc));
2614 }
2615 }
2616#endif
2617 }
2618
2619 return VINF_SUCCESS;
2620}
2621
2622
2623/**
2624 * Change the shadowing of a range of ROM pages.
2625 *
2626 * This is intended for implementing chipset specific memory registers
2627 * and will not be very strict about the input. It will silently ignore
2628 * any pages that are not the part of a shadowed ROM.
2629 *
2630 * @returns VBox status code.
2631 * @retval VINF_PGM_SYNC_CR3
2632 *
2633 * @param pVM Pointer to the shared VM structure.
2634 * @param GCPhys Where to start. Page aligned.
2635 * @param cb How much to change. Page aligned.
2636 * @param enmProt The new ROM protection.
2637 */
2638VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2639{
2640 /*
2641 * Check input
2642 */
2643 if (!cb)
2644 return VINF_SUCCESS;
2645 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2646 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2647 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2648 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2649 AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2650
2651 /*
2652 * Process the request.
2653 */
2654 pgmLock(pVM);
2655 int rc = VINF_SUCCESS;
2656 bool fFlushTLB = false;
2657 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2658 {
2659 if ( GCPhys <= pRom->GCPhysLast
2660 && GCPhysLast >= pRom->GCPhys
2661 && (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2662 {
2663 /*
2664 * Iterate the relevant pages and make necessary the changes.
2665 */
2666 bool fChanges = false;
2667 uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2668 ? pRom->cb >> PAGE_SHIFT
2669 : (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2670 for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2671 iPage < cPages;
2672 iPage++)
2673 {
2674 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2675 if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2676 {
2677 fChanges = true;
2678
2679 /* flush references to the page. */
2680 PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2681 int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRamPage, &fFlushTLB);
2682 if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS || RT_FAILURE(rc2)))
2683 rc = rc2;
2684
2685 PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2686 PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2687
2688 *pOld = *pRamPage;
2689 *pRamPage = *pNew;
2690 /** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2691 }
2692 pRomPage->enmProt = enmProt;
2693 }
2694
2695 /*
2696 * Reset the access handler if we made changes, no need
2697 * to optimize this.
2698 */
2699 if (fChanges)
2700 {
2701 int rc = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2702 if (RT_FAILURE(rc))
2703 {
2704 pgmUnlock(pVM);
2705 AssertRC(rc);
2706 return rc;
2707 }
2708 }
2709
2710 /* Advance - cb isn't updated. */
2711 GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2712 }
2713 }
2714 pgmUnlock(pVM);
2715 if (fFlushTLB)
2716 PGM_INVL_ALL_VCPU_TLBS(pVM);
2717
2718 return rc;
2719}
2720
2721
2722/**
2723 * Sets the Address Gate 20 state.
2724 *
2725 * @param pVCpu The VCPU to operate on.
2726 * @param fEnable True if the gate should be enabled.
2727 * False if the gate should be disabled.
2728 */
2729VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
2730{
2731 LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
2732 if (pVCpu->pgm.s.fA20Enabled != fEnable)
2733 {
2734 pVCpu->pgm.s.fA20Enabled = fEnable;
2735 pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2736 REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
2737 /** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2738 }
2739}
2740
2741
2742/**
2743 * Tree enumeration callback for dealing with age rollover.
2744 * It will perform a simple compression of the current age.
2745 */
2746static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2747{
2748 Assert(PGMIsLockOwner((PVM)pvUser));
2749 /* Age compression - ASSUMES iNow == 4. */
2750 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2751 if (pChunk->iAge >= UINT32_C(0xffffff00))
2752 pChunk->iAge = 3;
2753 else if (pChunk->iAge >= UINT32_C(0xfffff000))
2754 pChunk->iAge = 2;
2755 else if (pChunk->iAge)
2756 pChunk->iAge = 1;
2757 else /* iAge = 0 */
2758 pChunk->iAge = 4;
2759
2760 /* reinsert */
2761 PVM pVM = (PVM)pvUser;
2762 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2763 pChunk->AgeCore.Key = pChunk->iAge;
2764 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2765 return 0;
2766}
2767
2768
2769/**
2770 * Tree enumeration callback that updates the chunks that have
2771 * been used since the last
2772 */
2773static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
2774{
2775 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2776 if (!pChunk->iAge)
2777 {
2778 PVM pVM = (PVM)pvUser;
2779 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2780 pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
2781 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2782 }
2783
2784 return 0;
2785}
2786
2787
2788/**
2789 * Performs ageing of the ring-3 chunk mappings.
2790 *
2791 * @param pVM The VM handle.
2792 */
2793VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
2794{
2795 pgmLock(pVM);
2796 pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
2797 pVM->pgm.s.ChunkR3Map.iNow++;
2798 if (pVM->pgm.s.ChunkR3Map.iNow == 0)
2799 {
2800 pVM->pgm.s.ChunkR3Map.iNow = 4;
2801 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
2802 }
2803 else
2804 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingCallback, pVM);
2805 pgmUnlock(pVM);
2806}
2807
2808
2809/**
2810 * The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
2811 */
2812typedef struct PGMR3PHYSCHUNKUNMAPCB
2813{
2814 PVM pVM; /**< The VM handle. */
2815 PPGMCHUNKR3MAP pChunk; /**< The chunk to unmap. */
2816} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
2817
2818
2819/**
2820 * Callback used to find the mapping that's been unused for
2821 * the longest time.
2822 */
2823static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
2824{
2825 do
2826 {
2827 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
2828 if ( pChunk->iAge
2829 && !pChunk->cRefs)
2830 {
2831 /*
2832 * Check that it's not in any of the TLBs.
2833 */
2834 PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
2835 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2836 if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
2837 {
2838 pChunk = NULL;
2839 break;
2840 }
2841 if (pChunk)
2842 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
2843 if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
2844 {
2845 pChunk = NULL;
2846 break;
2847 }
2848 if (pChunk)
2849 {
2850 ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
2851 return 1; /* done */
2852 }
2853 }
2854
2855 /* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
2856 pNode = pNode->pList;
2857 } while (pNode);
2858 return 0;
2859}
2860
2861
2862/**
2863 * Finds a good candidate for unmapping when the ring-3 mapping cache is full.
2864 *
2865 * The candidate will not be part of any TLBs, so no need to flush
2866 * anything afterwards.
2867 *
2868 * @returns Chunk id.
2869 * @param pVM The VM handle.
2870 */
2871static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
2872{
2873 Assert(PGMIsLockOwner(pVM));
2874
2875 /*
2876 * Do tree ageing first?
2877 */
2878 if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
2879 PGMR3PhysChunkAgeing(pVM);
2880
2881 /*
2882 * Enumerate the age tree starting with the left most node.
2883 */
2884 PGMR3PHYSCHUNKUNMAPCB Args;
2885 Args.pVM = pVM;
2886 Args.pChunk = NULL;
2887 if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /*fFromLeft*/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
2888 return Args.pChunk->Core.Key;
2889 return INT32_MAX;
2890}
2891
2892
2893/**
2894 * Maps the given chunk into the ring-3 mapping cache.
2895 *
2896 * This will call ring-0.
2897 *
2898 * @returns VBox status code.
2899 * @param pVM The VM handle.
2900 * @param idChunk The chunk in question.
2901 * @param ppChunk Where to store the chunk tracking structure.
2902 *
2903 * @remarks Called from within the PGM critical section.
2904 */
2905int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
2906{
2907 int rc;
2908
2909 Assert(PGMIsLockOwner(pVM));
2910 /*
2911 * Allocate a new tracking structure first.
2912 */
2913#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2914 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
2915#else
2916 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
2917#endif
2918 AssertReturn(pChunk, VERR_NO_MEMORY);
2919 pChunk->Core.Key = idChunk;
2920 pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
2921 pChunk->iAge = 0;
2922 pChunk->cRefs = 0;
2923 pChunk->cPermRefs = 0;
2924 pChunk->pv = NULL;
2925
2926 /*
2927 * Request the ring-0 part to map the chunk in question and if
2928 * necessary unmap another one to make space in the mapping cache.
2929 */
2930 GMMMAPUNMAPCHUNKREQ Req;
2931 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2932 Req.Hdr.cbReq = sizeof(Req);
2933 Req.pvR3 = NULL;
2934 Req.idChunkMap = idChunk;
2935 Req.idChunkUnmap = NIL_GMM_CHUNKID;
2936 if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
2937 Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
2938 rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
2939 if (RT_SUCCESS(rc))
2940 {
2941 /*
2942 * Update the tree.
2943 */
2944 /* insert the new one. */
2945 AssertPtr(Req.pvR3);
2946 pChunk->pv = Req.pvR3;
2947 bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
2948 AssertRelease(fRc);
2949 pVM->pgm.s.ChunkR3Map.c++;
2950
2951 fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2952 AssertRelease(fRc);
2953
2954 /* remove the unmapped one. */
2955 if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
2956 {
2957 PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
2958 AssertRelease(pUnmappedChunk);
2959 pUnmappedChunk->pv = NULL;
2960 pUnmappedChunk->Core.Key = UINT32_MAX;
2961#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2962 MMR3HeapFree(pUnmappedChunk);
2963#else
2964 MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
2965#endif
2966 pVM->pgm.s.ChunkR3Map.c--;
2967 }
2968 }
2969 else
2970 {
2971 AssertRC(rc);
2972#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2973 MMR3HeapFree(pChunk);
2974#else
2975 MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
2976#endif
2977 pChunk = NULL;
2978 }
2979
2980 *ppChunk = pChunk;
2981 return rc;
2982}
2983
2984
2985/**
2986 * For VMMCALLHOST_PGM_MAP_CHUNK, considered internal.
2987 *
2988 * @returns see pgmR3PhysChunkMap.
2989 * @param pVM The VM handle.
2990 * @param idChunk The chunk to map.
2991 */
2992VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
2993{
2994 PPGMCHUNKR3MAP pChunk;
2995 int rc;
2996
2997 pgmLock(pVM);
2998 rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
2999 pgmUnlock(pVM);
3000 return rc;
3001}
3002
3003
3004/**
3005 * Invalidates the TLB for the ring-3 mapping cache.
3006 *
3007 * @param pVM The VM handle.
3008 */
3009VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3010{
3011 pgmLock(pVM);
3012 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3013 {
3014 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3015 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3016 }
3017 pgmUnlock(pVM);
3018}
3019
3020
3021/**
3022 * Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES.
3023 *
3024 * This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3025 * signal and clear the out of memory condition. When contracted, this API is
3026 * used to try clear the condition when the user wants to resume.
3027 *
3028 * @returns The following VBox status codes.
3029 * @retval VINF_SUCCESS on success. FFs cleared.
3030 * @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3031 * this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3032 *
3033 * @param pVM The VM handle.
3034 *
3035 * @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3036 * in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3037 * pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3038 * handler.
3039 */
3040VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3041{
3042 pgmLock(pVM);
3043
3044 /*
3045 * Allocate more pages, noting down the index of the first new page.
3046 */
3047 uint32_t iClear = pVM->pgm.s.cHandyPages;
3048 AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3049 Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3050 int rcAlloc = VINF_SUCCESS;
3051 int rcSeed = VINF_SUCCESS;
3052 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3053 while (rc == VERR_GMM_SEED_ME)
3054 {
3055 void *pvChunk;
3056 rcAlloc = rc = SUPPageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3057 if (RT_SUCCESS(rc))
3058 {
3059 rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3060 if (RT_FAILURE(rc))
3061 SUPPageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3062 }
3063 if (RT_SUCCESS(rc))
3064 rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3065 }
3066
3067 if (RT_SUCCESS(rc))
3068 {
3069 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3070 Assert(pVM->pgm.s.cHandyPages > 0);
3071 VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3072 VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3073
3074 /*
3075 * Clear the pages.
3076 */
3077 while (iClear < pVM->pgm.s.cHandyPages)
3078 {
3079 PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3080 void *pv;
3081 rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3082 AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3083 ASMMemZeroPage(pv);
3084 iClear++;
3085 Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3086 }
3087 }
3088 else
3089 {
3090 /*
3091 * We should never get here unless there is a genuine shortage of
3092 * memory (or some internal error). Flag the error so the VM can be
3093 * suspended ASAP and the user informed. If we're totally out of
3094 * handy pages we will return failure.
3095 */
3096 /* Report the failure. */
3097 LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3098 " cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3099 rc, rcSeed, rcAlloc,
3100 pVM->pgm.s.cHandyPages,
3101 pVM->pgm.s.cAllPages,
3102 pVM->pgm.s.cPrivatePages,
3103 pVM->pgm.s.cSharedPages,
3104 pVM->pgm.s.cZeroPages));
3105 if ( rc != VERR_NO_MEMORY
3106 && rc != VERR_LOCK_FAILED)
3107 {
3108 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3109 {
3110 LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3111 i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3112 pVM->pgm.s.aHandyPages[i].idSharedPage));
3113 uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3114 if (idPage != NIL_GMM_PAGEID)
3115 {
3116 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3117 pRam;
3118 pRam = pRam->pNextR3)
3119 {
3120 uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3121 for (uint32_t iPage = 0; iPage < cPages; iPage++)
3122 if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3123 LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3124 pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3125 }
3126 }
3127 }
3128 }
3129
3130 /* Set the FFs and adjust rc. */
3131 VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3132 VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3133 if ( rc == VERR_NO_MEMORY
3134 || rc == VERR_LOCK_FAILED)
3135 rc = VINF_EM_NO_MEMORY;
3136 }
3137
3138 pgmUnlock(pVM);
3139 return rc;
3140}
3141
3142
3143/**
3144 * Frees the specified RAM page and replaces it with the ZERO page.
3145 *
3146 * This is used by ballooning, remapping MMIO2 and RAM reset.
3147 *
3148 * @param pVM Pointer to the shared VM structure.
3149 * @param pReq Pointer to the request.
3150 * @param pPage Pointer to the page structure.
3151 * @param GCPhys The guest physical address of the page, if applicable.
3152 *
3153 * @remarks The caller must own the PGM lock.
3154 */
3155static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3156{
3157 /*
3158 * Assert sanity.
3159 */
3160 Assert(PGMIsLockOwner(pVM));
3161 if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3162 && PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3163 {
3164 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3165 return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3166 }
3167
3168 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO)
3169 return VINF_SUCCESS;
3170
3171 const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3172 Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3173 if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3174 || idPage > GMM_PAGEID_LAST
3175 || PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3176 {
3177 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3178 return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3179 }
3180
3181 /* update page count stats. */
3182 if (PGM_PAGE_IS_SHARED(pPage))
3183 pVM->pgm.s.cSharedPages--;
3184 else
3185 pVM->pgm.s.cPrivatePages--;
3186 pVM->pgm.s.cZeroPages++;
3187
3188 /*
3189 * pPage = ZERO page.
3190 */
3191 PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3192 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3193 PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3194
3195 /*
3196 * Make sure it's not in the handy page array.
3197 */
3198 for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3199 {
3200 if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3201 {
3202 pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3203 break;
3204 }
3205 if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3206 {
3207 pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3208 break;
3209 }
3210 }
3211
3212 /*
3213 * Push it onto the page array.
3214 */
3215 uint32_t iPage = *pcPendingPages;
3216 Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3217 *pcPendingPages += 1;
3218
3219 pReq->aPages[iPage].idPage = idPage;
3220
3221 if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3222 return VINF_SUCCESS;
3223
3224 /*
3225 * Flush the pages.
3226 */
3227 int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3228 if (RT_SUCCESS(rc))
3229 {
3230 GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3231 *pcPendingPages = 0;
3232 }
3233 return rc;
3234}
3235
3236
3237/**
3238 * Converts a GC physical address to a HC ring-3 pointer, with some
3239 * additional checks.
3240 *
3241 * @returns VBox status code.
3242 * @retval VINF_SUCCESS on success.
3243 * @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3244 * access handler of some kind.
3245 * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3246 * accesses or is odd in any way.
3247 * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3248 *
3249 * @param pVM The VM handle.
3250 * @param GCPhys The GC physical address to convert.
3251 * @param fWritable Whether write access is required.
3252 * @param ppv Where to store the pointer corresponding to GCPhys on
3253 * success.
3254 */
3255VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3256{
3257 pgmLock(pVM);
3258
3259 PPGMRAMRANGE pRam;
3260 PPGMPAGE pPage;
3261 int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3262 if (RT_SUCCESS(rc))
3263 {
3264 if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3265 rc = VINF_SUCCESS;
3266 else
3267 {
3268 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3269 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3270 else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3271 {
3272 /** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3273 * in -norawr0 mode. */
3274 if (fWritable)
3275 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3276 }
3277 else
3278 {
3279 /* Temporarily disabled physical handler(s), since the recompiler
3280 doesn't get notified when it's reset we'll have to pretend it's
3281 operating normally. */
3282 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3283 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3284 else
3285 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3286 }
3287 }
3288 if (RT_SUCCESS(rc))
3289 {
3290 int rc2;
3291
3292 /* Make sure what we return is writable. */
3293 if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3294 switch (PGM_PAGE_GET_STATE(pPage))
3295 {
3296 case PGM_PAGE_STATE_ALLOCATED:
3297 break;
3298 case PGM_PAGE_STATE_ZERO:
3299 case PGM_PAGE_STATE_SHARED:
3300 case PGM_PAGE_STATE_WRITE_MONITORED:
3301 rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3302 AssertLogRelRCReturn(rc2, rc2);
3303 break;
3304 }
3305
3306 /* Get a ring-3 mapping of the address. */
3307 PPGMPAGER3MAPTLBE pTlbe;
3308 rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3309 AssertLogRelRCReturn(rc2, rc2);
3310 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
3311 /** @todo mapping/locking hell; this isn't horribly efficient since
3312 * pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
3313
3314 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] *ppv=%p\n", GCPhys, rc, pPage, *ppv));
3315 }
3316 else
3317 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3318
3319 /* else: handler catching all access, no pointer returned. */
3320 }
3321 else
3322 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3323
3324 pgmUnlock(pVM);
3325 return rc;
3326}
3327
3328
3329
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