VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 23011

Last change on this file since 23011 was 23009, checked in by vboxsync, 15 years ago

VMM: State machine adjustments. Have only received basic testing.
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1/* $Id: PGMPhys.cpp 23009 2009-09-14 15:05:45Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM_PHYS
27#include <VBox/pgm.h>
28#include <VBox/iom.h>
29#include <VBox/mm.h>
30#include <VBox/stam.h>
31#include <VBox/rem.h>
32#include <VBox/pdmdev.h>
33#include "PGMInternal.h"
34#include <VBox/vm.h>
35#include <VBox/sup.h>
36#include <VBox/param.h>
37#include <VBox/err.h>
38#include <VBox/log.h>
39#include <iprt/assert.h>
40#include <iprt/alloc.h>
41#include <iprt/asm.h>
42#include <iprt/thread.h>
43#include <iprt/string.h>
44
45
46/*******************************************************************************
47* Defined Constants And Macros *
48*******************************************************************************/
49/** The number of pages to free in one batch. */
50#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
51
52
53/*******************************************************************************
54* Internal Functions *
55*******************************************************************************/
56static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
57static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
58
59
60/*
61 * PGMR3PhysReadU8-64
62 * PGMR3PhysWriteU8-64
63 */
64#define PGMPHYSFN_READNAME PGMR3PhysReadU8
65#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
66#define PGMPHYS_DATASIZE 1
67#define PGMPHYS_DATATYPE uint8_t
68#include "PGMPhysRWTmpl.h"
69
70#define PGMPHYSFN_READNAME PGMR3PhysReadU16
71#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
72#define PGMPHYS_DATASIZE 2
73#define PGMPHYS_DATATYPE uint16_t
74#include "PGMPhysRWTmpl.h"
75
76#define PGMPHYSFN_READNAME PGMR3PhysReadU32
77#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
78#define PGMPHYS_DATASIZE 4
79#define PGMPHYS_DATATYPE uint32_t
80#include "PGMPhysRWTmpl.h"
81
82#define PGMPHYSFN_READNAME PGMR3PhysReadU64
83#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
84#define PGMPHYS_DATASIZE 8
85#define PGMPHYS_DATATYPE uint64_t
86#include "PGMPhysRWTmpl.h"
87
88
89/**
90 * EMT worker for PGMR3PhysReadExternal.
91 */
92static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
93{
94 PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
95 return VINF_SUCCESS;
96}
97
98
99/**
100 * Write to physical memory, external users.
101 *
102 * @returns VBox status code.
103 * @retval VINF_SUCCESS.
104 *
105 * @param pVM VM Handle.
106 * @param GCPhys Physical address to write to.
107 * @param pvBuf What to write.
108 * @param cbWrite How many bytes to write.
109 *
110 * @thread Any but EMTs.
111 */
112VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
113{
114 VM_ASSERT_OTHER_THREAD(pVM);
115
116 AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
117 LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
118
119 pgmLock(pVM);
120
121 /*
122 * Copy loop on ram ranges.
123 */
124 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
125 for (;;)
126 {
127 /* Find range. */
128 while (pRam && GCPhys > pRam->GCPhysLast)
129 pRam = pRam->CTX_SUFF(pNext);
130 /* Inside range or not? */
131 if (pRam && GCPhys >= pRam->GCPhys)
132 {
133 /*
134 * Must work our way thru this page by page.
135 */
136 RTGCPHYS off = GCPhys - pRam->GCPhys;
137 while (off < pRam->cb)
138 {
139 unsigned iPage = off >> PAGE_SHIFT;
140 PPGMPAGE pPage = &pRam->aPages[iPage];
141
142 /*
143 * If the page has an ALL access handler, we'll have to
144 * delegate the job to EMT.
145 */
146 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
147 {
148 pgmUnlock(pVM);
149
150 PVMREQ pReq = NULL;
151 int rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
152 (PFNRT)pgmR3PhysReadExternalEMT, 4, pVM, &GCPhys, pvBuf, cbRead);
153 if (RT_SUCCESS(rc))
154 {
155 rc = pReq->iStatus;
156 VMR3ReqFree(pReq);
157 }
158 return rc;
159 }
160 Assert(!PGM_PAGE_IS_MMIO(pPage));
161
162 /*
163 * Simple stuff, go ahead.
164 */
165 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
166 if (cb > cbRead)
167 cb = cbRead;
168 const void *pvSrc;
169 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
170 if (RT_SUCCESS(rc))
171 memcpy(pvBuf, pvSrc, cb);
172 else
173 {
174 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
175 pRam->GCPhys + off, pPage, rc));
176 memset(pvBuf, 0xff, cb);
177 }
178
179 /* next page */
180 if (cb >= cbRead)
181 {
182 pgmUnlock(pVM);
183 return VINF_SUCCESS;
184 }
185 cbRead -= cb;
186 off += cb;
187 GCPhys += cb;
188 pvBuf = (char *)pvBuf + cb;
189 } /* walk pages in ram range. */
190 }
191 else
192 {
193 LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
194
195 /*
196 * Unassigned address space.
197 */
198 if (!pRam)
199 break;
200 size_t cb = pRam->GCPhys - GCPhys;
201 if (cb >= cbRead)
202 {
203 memset(pvBuf, 0xff, cbRead);
204 break;
205 }
206 memset(pvBuf, 0xff, cb);
207
208 cbRead -= cb;
209 pvBuf = (char *)pvBuf + cb;
210 GCPhys += cb;
211 }
212 } /* Ram range walk */
213
214 pgmUnlock(pVM);
215
216 return VINF_SUCCESS;
217}
218
219
220/**
221 * EMT worker for PGMR3PhysWriteExternal.
222 */
223static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
224{
225 /** @todo VERR_EM_NO_MEMORY */
226 PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
227 return VINF_SUCCESS;
228}
229
230
231/**
232 * Write to physical memory, external users.
233 *
234 * @returns VBox status code.
235 * @retval VINF_SUCCESS.
236 * @retval VERR_EM_NO_MEMORY.
237 *
238 * @param pVM VM Handle.
239 * @param GCPhys Physical address to write to.
240 * @param pvBuf What to write.
241 * @param cbWrite How many bytes to write.
242 *
243 * @thread Any but EMTs.
244 */
245VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
246{
247 VM_ASSERT_OTHER_THREAD(pVM);
248
249 AssertMsg(!pVM->pgm.s.fNoMorePhysWrites, ("Calling PGMR3PhysWriteExternal after pgmR3Save()!\n"));
250 AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
251 LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
252
253 pgmLock(pVM);
254
255 /*
256 * Copy loop on ram ranges, stop when we hit something difficult.
257 */
258 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
259 for (;;)
260 {
261 /* Find range. */
262 while (pRam && GCPhys > pRam->GCPhysLast)
263 pRam = pRam->CTX_SUFF(pNext);
264 /* Inside range or not? */
265 if (pRam && GCPhys >= pRam->GCPhys)
266 {
267 /*
268 * Must work our way thru this page by page.
269 */
270 RTGCPTR off = GCPhys - pRam->GCPhys;
271 while (off < pRam->cb)
272 {
273 RTGCPTR iPage = off >> PAGE_SHIFT;
274 PPGMPAGE pPage = &pRam->aPages[iPage];
275
276 /*
277 * It the page is in any way problematic, we have to
278 * do the work on the EMT. Anything that needs to be made
279 * writable or involves access handlers is problematic.
280 */
281 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
282 || PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
283 {
284 pgmUnlock(pVM);
285
286 PVMREQ pReq = NULL;
287 int rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
288 (PFNRT)pgmR3PhysWriteExternalEMT, 4, pVM, &GCPhys, pvBuf, cbWrite);
289 if (RT_SUCCESS(rc))
290 {
291 rc = pReq->iStatus;
292 VMR3ReqFree(pReq);
293 }
294 return rc;
295 }
296 Assert(!PGM_PAGE_IS_MMIO(pPage));
297
298 /*
299 * Simple stuff, go ahead.
300 */
301 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
302 if (cb > cbWrite)
303 cb = cbWrite;
304 void *pvDst;
305 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
306 if (RT_SUCCESS(rc))
307 memcpy(pvDst, pvBuf, cb);
308 else
309 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
310 pRam->GCPhys + off, pPage, rc));
311
312 /* next page */
313 if (cb >= cbWrite)
314 {
315 pgmUnlock(pVM);
316 return VINF_SUCCESS;
317 }
318
319 cbWrite -= cb;
320 off += cb;
321 GCPhys += cb;
322 pvBuf = (const char *)pvBuf + cb;
323 } /* walk pages in ram range */
324 }
325 else
326 {
327 /*
328 * Unassigned address space, skip it.
329 */
330 if (!pRam)
331 break;
332 size_t cb = pRam->GCPhys - GCPhys;
333 if (cb >= cbWrite)
334 break;
335 cbWrite -= cb;
336 pvBuf = (const char *)pvBuf + cb;
337 GCPhys += cb;
338 }
339 } /* Ram range walk */
340
341 pgmUnlock(pVM);
342 return VINF_SUCCESS;
343}
344
345
346/**
347 * VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
348 *
349 * @returns see PGMR3PhysGCPhys2CCPtrExternal
350 * @param pVM The VM handle.
351 * @param pGCPhys Pointer to the guest physical address.
352 * @param ppv Where to store the mapping address.
353 * @param pLock Where to store the lock.
354 */
355static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
356{
357 /*
358 * Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
359 * an access handler after it succeeds.
360 */
361 int rc = pgmLock(pVM);
362 AssertRCReturn(rc, rc);
363
364 rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
365 if (RT_SUCCESS(rc))
366 {
367 PPGMPAGEMAPTLBE pTlbe;
368 int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
369 AssertFatalRC(rc2);
370 PPGMPAGE pPage = pTlbe->pPage;
371 if (PGM_PAGE_IS_MMIO(pPage))
372 {
373 PGMPhysReleasePageMappingLock(pVM, pLock);
374 rc = VERR_PGM_PHYS_PAGE_RESERVED;
375 }
376 else
377 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
378#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
379 || pgmPoolIsDirtyPage(pVM, *pGCPhys)
380#endif
381 )
382 {
383 /* We *must* flush any corresponding pgm pool page here, otherwise we'll
384 * not be informed about writes and keep bogus gst->shw mappings around.
385 */
386 pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
387 Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
388 /** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
389 * active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
390 }
391 }
392
393 pgmUnlock(pVM);
394 return rc;
395}
396
397
398/**
399 * Requests the mapping of a guest page into ring-3, external threads.
400 *
401 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
402 * release it.
403 *
404 * This API will assume your intention is to write to the page, and will
405 * therefore replace shared and zero pages. If you do not intend to modify the
406 * page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
407 *
408 * @returns VBox status code.
409 * @retval VINF_SUCCESS on success.
410 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
411 * backing or if the page has any active access handlers. The caller
412 * must fall back on using PGMR3PhysWriteExternal.
413 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
414 *
415 * @param pVM The VM handle.
416 * @param GCPhys The guest physical address of the page that should be mapped.
417 * @param ppv Where to store the address corresponding to GCPhys.
418 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
419 *
420 * @remark Avoid calling this API from within critical sections (other than the
421 * PGM one) because of the deadlock risk when we have to delegating the
422 * task to an EMT.
423 * @thread Any.
424 */
425VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
426{
427 AssertPtr(ppv);
428 AssertPtr(pLock);
429
430 Assert(VM_IS_EMT(pVM) || !PGMIsLockOwner(pVM));
431
432 int rc = pgmLock(pVM);
433 AssertRCReturn(rc, rc);
434
435 /*
436 * Query the Physical TLB entry for the page (may fail).
437 */
438 PPGMPAGEMAPTLBE pTlbe;
439 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
440 if (RT_SUCCESS(rc))
441 {
442 PPGMPAGE pPage = pTlbe->pPage;
443 if (PGM_PAGE_IS_MMIO(pPage))
444 rc = VERR_PGM_PHYS_PAGE_RESERVED;
445 else
446 {
447 /*
448 * If the page is shared, the zero page, or being write monitored
449 * it must be converted to an page that's writable if possible.
450 * This has to be done on an EMT.
451 */
452 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
453#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
454 || pgmPoolIsDirtyPage(pVM, GCPhys)
455#endif
456 || RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
457 {
458 pgmUnlock(pVM);
459
460 PVMREQ pReq = NULL;
461 rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
462 (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4, pVM, &GCPhys, ppv, pLock);
463 if (RT_SUCCESS(rc))
464 {
465 rc = pReq->iStatus;
466 VMR3ReqFree(pReq);
467 }
468 return rc;
469 }
470
471 /*
472 * Now, just perform the locking and calculate the return address.
473 */
474 PPGMPAGEMAP pMap = pTlbe->pMap;
475 pMap->cRefs++;
476#if 0 /** @todo implement locking properly */
477 if (RT_LIKELY(pPage->cLocks != PGM_PAGE_MAX_LOCKS))
478 if (RT_UNLIKELY(++pPage->cLocks == PGM_PAGE_MAX_LOCKS))
479 {
480 AssertMsgFailed(("%RGp is entering permanent locked state!\n", GCPhys));
481 pMap->cRefs++; /* Extra ref to prevent it from going away. */
482 }
483#endif
484 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
485 pLock->pvPage = pPage;
486 pLock->pvMap = pMap;
487 }
488 }
489
490 pgmUnlock(pVM);
491 return rc;
492}
493
494
495/**
496 * Requests the mapping of a guest page into ring-3, external threads.
497 *
498 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
499 * release it.
500 *
501 * @returns VBox status code.
502 * @retval VINF_SUCCESS on success.
503 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
504 * backing or if the page as an active ALL access handler. The caller
505 * must fall back on using PGMPhysRead.
506 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
507 *
508 * @param pVM The VM handle.
509 * @param GCPhys The guest physical address of the page that should be mapped.
510 * @param ppv Where to store the address corresponding to GCPhys.
511 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
512 *
513 * @remark Avoid calling this API from within critical sections (other than
514 * the PGM one) because of the deadlock risk.
515 * @thread Any.
516 */
517VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
518{
519 int rc = pgmLock(pVM);
520 AssertRCReturn(rc, rc);
521
522 /*
523 * Query the Physical TLB entry for the page (may fail).
524 */
525 PPGMPAGEMAPTLBE pTlbe;
526 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
527 if (RT_SUCCESS(rc))
528 {
529 PPGMPAGE pPage = pTlbe->pPage;
530#if 1
531 /* MMIO pages doesn't have any readable backing. */
532 if (PGM_PAGE_IS_MMIO(pPage))
533 rc = VERR_PGM_PHYS_PAGE_RESERVED;
534#else
535 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
536 rc = VERR_PGM_PHYS_PAGE_RESERVED;
537#endif
538 else
539 {
540 /*
541 * Now, just perform the locking and calculate the return address.
542 */
543 PPGMPAGEMAP pMap = pTlbe->pMap;
544 pMap->cRefs++;
545#if 0 /** @todo implement locking properly */
546 if (RT_LIKELY(pPage->cLocks != PGM_PAGE_MAX_LOCKS))
547 if (RT_UNLIKELY(++pPage->cLocks == PGM_PAGE_MAX_LOCKS))
548 {
549 AssertMsgFailed(("%RGp is entering permanent locked state!\n", GCPhys));
550 pMap->cRefs++; /* Extra ref to prevent it from going away. */
551 }
552#endif
553 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
554 pLock->pvPage = pPage;
555 pLock->pvMap = pMap;
556 }
557 }
558
559 pgmUnlock(pVM);
560 return rc;
561}
562
563
564/**
565 * Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
566 *
567 * Called when anything was relocated.
568 *
569 * @param pVM Pointer to the shared VM structure.
570 */
571void pgmR3PhysRelinkRamRanges(PVM pVM)
572{
573 PPGMRAMRANGE pCur;
574
575#ifdef VBOX_STRICT
576 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
577 {
578 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
579 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
580 Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
581 Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
582 Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
583 Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
584 for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
585 Assert( pCur2 == pCur
586 || strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
587 }
588#endif
589
590 pCur = pVM->pgm.s.pRamRangesR3;
591 if (pCur)
592 {
593 pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
594 pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
595
596 for (; pCur->pNextR3; pCur = pCur->pNextR3)
597 {
598 pCur->pNextR0 = pCur->pNextR3->pSelfR0;
599 pCur->pNextRC = pCur->pNextR3->pSelfRC;
600 }
601
602 Assert(pCur->pNextR0 == NIL_RTR0PTR);
603 Assert(pCur->pNextRC == NIL_RTRCPTR);
604 }
605 else
606 {
607 Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
608 Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
609 }
610}
611
612
613/**
614 * Links a new RAM range into the list.
615 *
616 * @param pVM Pointer to the shared VM structure.
617 * @param pNew Pointer to the new list entry.
618 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
619 */
620static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
621{
622 AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
623 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
624 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
625
626 pgmLock(pVM);
627
628 PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
629 pNew->pNextR3 = pRam;
630 pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
631 pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
632
633 if (pPrev)
634 {
635 pPrev->pNextR3 = pNew;
636 pPrev->pNextR0 = pNew->pSelfR0;
637 pPrev->pNextRC = pNew->pSelfRC;
638 }
639 else
640 {
641 pVM->pgm.s.pRamRangesR3 = pNew;
642 pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
643 pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
644 }
645
646 pgmUnlock(pVM);
647}
648
649
650/**
651 * Unlink an existing RAM range from the list.
652 *
653 * @param pVM Pointer to the shared VM structure.
654 * @param pRam Pointer to the new list entry.
655 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
656 */
657static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
658{
659 Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
660 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
661 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
662
663 pgmLock(pVM);
664
665 PPGMRAMRANGE pNext = pRam->pNextR3;
666 if (pPrev)
667 {
668 pPrev->pNextR3 = pNext;
669 pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
670 pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
671 }
672 else
673 {
674 Assert(pVM->pgm.s.pRamRangesR3 == pRam);
675 pVM->pgm.s.pRamRangesR3 = pNext;
676 pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
677 pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
678 }
679
680 pgmUnlock(pVM);
681}
682
683
684/**
685 * Unlink an existing RAM range from the list.
686 *
687 * @param pVM Pointer to the shared VM structure.
688 * @param pRam Pointer to the new list entry.
689 */
690static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
691{
692 pgmLock(pVM);
693
694 /* find prev. */
695 PPGMRAMRANGE pPrev = NULL;
696 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
697 while (pCur != pRam)
698 {
699 pPrev = pCur;
700 pCur = pCur->pNextR3;
701 }
702 AssertFatal(pCur);
703
704 pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
705
706 pgmUnlock(pVM);
707}
708
709
710/**
711 * Frees a range of pages, replacing them with ZERO pages of the specified type.
712 *
713 * @returns VBox status code.
714 * @param pVM The VM handle.
715 * @param pRam The RAM range in which the pages resides.
716 * @param GCPhys The address of the first page.
717 * @param GCPhysLast The address of the last page.
718 * @param uType The page type to replace then with.
719 */
720static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
721{
722 uint32_t cPendingPages = 0;
723 PGMMFREEPAGESREQ pReq;
724 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
725 AssertLogRelRCReturn(rc, rc);
726
727 /* Itegerate the pages. */
728 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
729 uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
730 while (cPagesLeft-- > 0)
731 {
732 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
733 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
734
735 PGM_PAGE_SET_TYPE(pPageDst, uType);
736
737 GCPhys += PAGE_SIZE;
738 pPageDst++;
739 }
740
741 if (cPendingPages)
742 {
743 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
744 AssertLogRelRCReturn(rc, rc);
745 }
746 GMMR3FreePagesCleanup(pReq);
747
748 return rc;
749}
750
751
752/**
753 * PGMR3PhysRegisterRam worker that initializes and links a RAM range.
754 *
755 * @param pVM The VM handle.
756 * @param pNew The new RAM range.
757 * @param GCPhys The address of the RAM range.
758 * @param GCPhysLast The last address of the RAM range.
759 * @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
760 * if in HMA.
761 * @param R0PtrNew Ditto for R0.
762 * @param pszDesc The description.
763 * @param pPrev The previous RAM range (for linking).
764 */
765static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
766 RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
767{
768 /*
769 * Initialize the range.
770 */
771 pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
772 pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
773 pNew->GCPhys = GCPhys;
774 pNew->GCPhysLast = GCPhysLast;
775 pNew->cb = GCPhysLast - GCPhys + 1;
776 pNew->pszDesc = pszDesc;
777 pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
778 pNew->pvR3 = NULL;
779
780 uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
781 RTGCPHYS iPage = cPages;
782 while (iPage-- > 0)
783 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
784
785 /* Update the page count stats. */
786 pVM->pgm.s.cZeroPages += cPages;
787 pVM->pgm.s.cAllPages += cPages;
788
789 /*
790 * Link it.
791 */
792 pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
793}
794
795
796/**
797 * Relocate a floating RAM range.
798 *
799 * @copydoc FNPGMRELOCATE.
800 */
801static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
802{
803 PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
804 Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
805 Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
806
807 switch (enmMode)
808 {
809 case PGMRELOCATECALL_SUGGEST:
810 return true;
811 case PGMRELOCATECALL_RELOCATE:
812 {
813 /* Update myself and then relink all the ranges. */
814 pgmLock(pVM);
815 pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
816 pgmR3PhysRelinkRamRanges(pVM);
817 pgmUnlock(pVM);
818 return true;
819 }
820
821 default:
822 AssertFailedReturn(false);
823 }
824}
825
826
827/**
828 * PGMR3PhysRegisterRam worker that registers a high chunk.
829 *
830 * @returns VBox status code.
831 * @param pVM The VM handle.
832 * @param GCPhys The address of the RAM.
833 * @param cRamPages The number of RAM pages to register.
834 * @param cbChunk The size of the PGMRAMRANGE guest mapping.
835 * @param iChunk The chunk number.
836 * @param pszDesc The RAM range description.
837 * @param ppPrev Previous RAM range pointer. In/Out.
838 */
839static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
840 uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
841 PPGMRAMRANGE *ppPrev)
842{
843 const char *pszDescChunk = iChunk == 0
844 ? pszDesc
845 : MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
846 AssertReturn(pszDescChunk, VERR_NO_MEMORY);
847
848 /*
849 * Allocate memory for the new chunk.
850 */
851 size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
852 PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
853 AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
854 RTR0PTR R0PtrChunk = NIL_RTR0PTR;
855 void *pvChunk = NULL;
856 int rc = SUPR3PageAllocEx(cChunkPages, 0 /*fFlags*/, &pvChunk,
857#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
858 VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
859#else
860 NULL,
861#endif
862 paChunkPages);
863 if (RT_SUCCESS(rc))
864 {
865#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
866 if (!VMMIsHwVirtExtForced(pVM))
867 R0PtrChunk = NIL_RTR0PTR;
868#else
869 R0PtrChunk = (uintptr_t)pvChunk;
870#endif
871 memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
872
873 PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
874
875 /*
876 * Create a mapping and map the pages into it.
877 * We push these in below the HMA.
878 */
879 RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
880 rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /*fFlags*/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
881 if (RT_SUCCESS(rc))
882 {
883 pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
884
885 RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
886 RTGCPTR GCPtrPage = GCPtrChunk;
887 for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
888 rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
889 if (RT_SUCCESS(rc))
890 {
891 /*
892 * Ok, init and link the range.
893 */
894 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
895 (RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
896 *ppPrev = pNew;
897 }
898 }
899
900 if (RT_FAILURE(rc))
901 SUPR3PageFreeEx(pvChunk, cChunkPages);
902 }
903
904 RTMemTmpFree(paChunkPages);
905 return rc;
906}
907
908
909/**
910 * Sets up a range RAM.
911 *
912 * This will check for conflicting registrations, make a resource
913 * reservation for the memory (with GMM), and setup the per-page
914 * tracking structures (PGMPAGE).
915 *
916 * @returns VBox stutus code.
917 * @param pVM Pointer to the shared VM structure.
918 * @param GCPhys The physical address of the RAM.
919 * @param cb The size of the RAM.
920 * @param pszDesc The description - not copied, so, don't free or change it.
921 */
922VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
923{
924 /*
925 * Validate input.
926 */
927 Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
928 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
929 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
930 AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
931 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
932 AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
933 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
934 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
935
936 pgmLock(pVM);
937
938 /*
939 * Find range location and check for conflicts.
940 * (We don't lock here because the locking by EMT is only required on update.)
941 */
942 PPGMRAMRANGE pPrev = NULL;
943 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
944 while (pRam && GCPhysLast >= pRam->GCPhys)
945 {
946 if ( GCPhysLast >= pRam->GCPhys
947 && GCPhys <= pRam->GCPhysLast)
948 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
949 GCPhys, GCPhysLast, pszDesc,
950 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
951 VERR_PGM_RAM_CONFLICT);
952
953 /* next */
954 pPrev = pRam;
955 pRam = pRam->pNextR3;
956 }
957
958 /*
959 * Register it with GMM (the API bitches).
960 */
961 const RTGCPHYS cPages = cb >> PAGE_SHIFT;
962 int rc = MMR3IncreaseBaseReservation(pVM, cPages);
963 if (RT_FAILURE(rc))
964 {
965 pgmUnlock(pVM);
966 return rc;
967 }
968
969 if ( GCPhys >= _4G
970 && cPages > 256)
971 {
972 /*
973 * The PGMRAMRANGE structures for the high memory can get very big.
974 * In order to avoid SUPR3PageAllocEx allocation failures due to the
975 * allocation size limit there and also to avoid being unable to find
976 * guest mapping space for them, we split this memory up into 4MB in
977 * (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
978 * mode.
979 *
980 * The first and last page of each mapping are guard pages and marked
981 * not-present. So, we've got 4186112 and 16769024 bytes available for
982 * the PGMRAMRANGE structure.
983 *
984 * Note! The sizes used here will influence the saved state.
985 */
986 uint32_t cbChunk;
987 uint32_t cPagesPerChunk;
988 if (VMMIsHwVirtExtForced(pVM))
989 {
990 cbChunk = 16U*_1M;
991 cPagesPerChunk = 1048048; /* max ~1048059 */
992 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U*_1M - PAGE_SIZE * 2);
993 }
994 else
995 {
996 cbChunk = 4U*_1M;
997 cPagesPerChunk = 261616; /* max ~261627 */
998 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U*_1M - PAGE_SIZE * 2);
999 }
1000 AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1001
1002 RTGCPHYS cPagesLeft = cPages;
1003 RTGCPHYS GCPhysChunk = GCPhys;
1004 uint32_t iChunk = 0;
1005 while (cPagesLeft > 0)
1006 {
1007 uint32_t cPagesInChunk = cPagesLeft;
1008 if (cPagesInChunk > cPagesPerChunk)
1009 cPagesInChunk = cPagesPerChunk;
1010
1011 rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1012 AssertRCReturn(rc, rc);
1013
1014 /* advance */
1015 GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1016 cPagesLeft -= cPagesInChunk;
1017 iChunk++;
1018 }
1019 }
1020 else
1021 {
1022 /*
1023 * Allocate, initialize and link the new RAM range.
1024 */
1025 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1026 PPGMRAMRANGE pNew;
1027 rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1028 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1029
1030 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1031 }
1032 pgmUnlock(pVM);
1033
1034 /*
1035 * Notify REM.
1036 */
1037 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1038
1039 return VINF_SUCCESS;
1040}
1041
1042
1043/**
1044 * Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1045 *
1046 * We do this late in the init process so that all the ROM and MMIO ranges have
1047 * been registered already and we don't go wasting memory on them.
1048 *
1049 * @returns VBox status code.
1050 *
1051 * @param pVM Pointer to the shared VM structure.
1052 */
1053int pgmR3PhysRamPreAllocate(PVM pVM)
1054{
1055 Assert(pVM->pgm.s.fRamPreAlloc);
1056 Log(("pgmR3PhysRamPreAllocate: enter\n"));
1057
1058 /*
1059 * Walk the RAM ranges and allocate all RAM pages, halt at
1060 * the first allocation error.
1061 */
1062 uint64_t cPages = 0;
1063 uint64_t NanoTS = RTTimeNanoTS();
1064 pgmLock(pVM);
1065 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1066 {
1067 PPGMPAGE pPage = &pRam->aPages[0];
1068 RTGCPHYS GCPhys = pRam->GCPhys;
1069 uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1070 while (cLeft-- > 0)
1071 {
1072 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1073 {
1074 switch (PGM_PAGE_GET_STATE(pPage))
1075 {
1076 case PGM_PAGE_STATE_ZERO:
1077 {
1078 int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1079 if (RT_FAILURE(rc))
1080 {
1081 LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1082 pgmUnlock(pVM);
1083 return rc;
1084 }
1085 cPages++;
1086 break;
1087 }
1088
1089 case PGM_PAGE_STATE_ALLOCATED:
1090 case PGM_PAGE_STATE_WRITE_MONITORED:
1091 case PGM_PAGE_STATE_SHARED:
1092 /* nothing to do here. */
1093 break;
1094 }
1095 }
1096
1097 /* next */
1098 pPage++;
1099 GCPhys += PAGE_SIZE;
1100 }
1101 }
1102 pgmUnlock(pVM);
1103 NanoTS = RTTimeNanoTS() - NanoTS;
1104
1105 LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1106 Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1107 return VINF_SUCCESS;
1108}
1109
1110
1111/**
1112 * Resets (zeros) the RAM.
1113 *
1114 * ASSUMES that the caller owns the PGM lock.
1115 *
1116 * @returns VBox status code.
1117 * @param pVM Pointer to the shared VM structure.
1118 */
1119int pgmR3PhysRamReset(PVM pVM)
1120{
1121 Assert(PGMIsLockOwner(pVM));
1122 /*
1123 * We batch up pages before freeing them.
1124 */
1125 uint32_t cPendingPages = 0;
1126 PGMMFREEPAGESREQ pReq;
1127 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1128 AssertLogRelRCReturn(rc, rc);
1129
1130 /*
1131 * Walk the ram ranges.
1132 */
1133 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1134 {
1135 uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1136 AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1137
1138 if (!pVM->pgm.s.fRamPreAlloc)
1139 {
1140 /* Replace all RAM pages by ZERO pages. */
1141 while (iPage-- > 0)
1142 {
1143 PPGMPAGE pPage = &pRam->aPages[iPage];
1144 switch (PGM_PAGE_GET_TYPE(pPage))
1145 {
1146 case PGMPAGETYPE_RAM:
1147 if (!PGM_PAGE_IS_ZERO(pPage))
1148 {
1149 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1150 AssertLogRelRCReturn(rc, rc);
1151 }
1152 break;
1153
1154 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1155 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1156 break;
1157
1158 case PGMPAGETYPE_MMIO2:
1159 case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1160 case PGMPAGETYPE_ROM:
1161 case PGMPAGETYPE_MMIO:
1162 break;
1163 default:
1164 AssertFailed();
1165 }
1166 } /* for each page */
1167 }
1168 else
1169 {
1170 /* Zero the memory. */
1171 while (iPage-- > 0)
1172 {
1173 PPGMPAGE pPage = &pRam->aPages[iPage];
1174 switch (PGM_PAGE_GET_TYPE(pPage))
1175 {
1176 case PGMPAGETYPE_RAM:
1177 switch (PGM_PAGE_GET_STATE(pPage))
1178 {
1179 case PGM_PAGE_STATE_ZERO:
1180 break;
1181 case PGM_PAGE_STATE_SHARED:
1182 case PGM_PAGE_STATE_WRITE_MONITORED:
1183 rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1184 AssertLogRelRCReturn(rc, rc);
1185 case PGM_PAGE_STATE_ALLOCATED:
1186 {
1187 void *pvPage;
1188 PPGMPAGEMAP pMapIgnored;
1189 rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pMapIgnored, &pvPage);
1190 AssertLogRelRCReturn(rc, rc);
1191 ASMMemZeroPage(pvPage);
1192 break;
1193 }
1194 }
1195 break;
1196
1197 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1198 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1199 break;
1200
1201 case PGMPAGETYPE_MMIO2:
1202 case PGMPAGETYPE_ROM_SHADOW:
1203 case PGMPAGETYPE_ROM:
1204 case PGMPAGETYPE_MMIO:
1205 break;
1206 default:
1207 AssertFailed();
1208
1209 }
1210 } /* for each page */
1211 }
1212
1213 }
1214
1215 /*
1216 * Finish off any pages pending freeing.
1217 */
1218 if (cPendingPages)
1219 {
1220 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1221 AssertLogRelRCReturn(rc, rc);
1222 }
1223 GMMR3FreePagesCleanup(pReq);
1224
1225 return VINF_SUCCESS;
1226}
1227
1228
1229/**
1230 * This is the interface IOM is using to register an MMIO region.
1231 *
1232 * It will check for conflicts and ensure that a RAM range structure
1233 * is present before calling the PGMR3HandlerPhysicalRegister API to
1234 * register the callbacks.
1235 *
1236 * @returns VBox status code.
1237 *
1238 * @param pVM Pointer to the shared VM structure.
1239 * @param GCPhys The start of the MMIO region.
1240 * @param cb The size of the MMIO region.
1241 * @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1242 * @param pvUserR3 The user argument for R3.
1243 * @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1244 * @param pvUserR0 The user argument for R0.
1245 * @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1246 * @param pvUserRC The user argument for RC.
1247 * @param pszDesc The description of the MMIO region.
1248 */
1249VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1250 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1251 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1252 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1253 R3PTRTYPE(const char *) pszDesc)
1254{
1255 /*
1256 * Assert on some assumption.
1257 */
1258 VM_ASSERT_EMT(pVM);
1259 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1260 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1261 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1262 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1263
1264 /*
1265 * Make sure there's a RAM range structure for the region.
1266 */
1267 int rc;
1268 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1269 bool fRamExists = false;
1270 PPGMRAMRANGE pRamPrev = NULL;
1271 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1272 while (pRam && GCPhysLast >= pRam->GCPhys)
1273 {
1274 if ( GCPhysLast >= pRam->GCPhys
1275 && GCPhys <= pRam->GCPhysLast)
1276 {
1277 /* Simplification: all within the same range. */
1278 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1279 && GCPhysLast <= pRam->GCPhysLast,
1280 ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1281 GCPhys, GCPhysLast, pszDesc,
1282 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1283 VERR_PGM_RAM_CONFLICT);
1284
1285 /* Check that it's all RAM or MMIO pages. */
1286 PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1287 uint32_t cLeft = cb >> PAGE_SHIFT;
1288 while (cLeft-- > 0)
1289 {
1290 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1291 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1292 ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1293 GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1294 VERR_PGM_RAM_CONFLICT);
1295 pPage++;
1296 }
1297
1298 /* Looks good. */
1299 fRamExists = true;
1300 break;
1301 }
1302
1303 /* next */
1304 pRamPrev = pRam;
1305 pRam = pRam->pNextR3;
1306 }
1307 PPGMRAMRANGE pNew;
1308 if (fRamExists)
1309 {
1310 pNew = NULL;
1311
1312 /*
1313 * Make all the pages in the range MMIO/ZERO pages, freeing any
1314 * RAM pages currently mapped here. This might not be 100% correct
1315 * for PCI memory, but we're doing the same thing for MMIO2 pages.
1316 */
1317 rc = pgmLock(pVM);
1318 if (RT_SUCCESS(rc))
1319 {
1320 rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1321 pgmUnlock(pVM);
1322 }
1323 AssertRCReturn(rc, rc);
1324 }
1325 else
1326 {
1327 pgmLock(pVM);
1328
1329 /*
1330 * No RAM range, insert an ad-hoc one.
1331 *
1332 * Note that we don't have to tell REM about this range because
1333 * PGMHandlerPhysicalRegisterEx will do that for us.
1334 */
1335 Log(("PGMR3PhysMMIORegister: Adding ad-hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1336
1337 const uint32_t cPages = cb >> PAGE_SHIFT;
1338 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1339 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1340 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1341
1342 /* Initialize the range. */
1343 pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1344 pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1345 pNew->GCPhys = GCPhys;
1346 pNew->GCPhysLast = GCPhysLast;
1347 pNew->cb = cb;
1348 pNew->pszDesc = pszDesc;
1349 pNew->fFlags = 0; /** @todo add some kind of ad-hoc flag? */
1350
1351 pNew->pvR3 = NULL;
1352
1353 uint32_t iPage = cPages;
1354 while (iPage-- > 0)
1355 PGM_PAGE_INIT_ZERO_REAL(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1356 Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1357
1358 /* update the page count stats. */
1359 pVM->pgm.s.cZeroPages += cPages;
1360 pVM->pgm.s.cAllPages += cPages;
1361
1362 /* link it */
1363 pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1364
1365 pgmUnlock(pVM);
1366 }
1367
1368 /*
1369 * Register the access handler.
1370 */
1371 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1372 pfnHandlerR3, pvUserR3,
1373 pfnHandlerR0, pvUserR0,
1374 pfnHandlerRC, pvUserRC, pszDesc);
1375 if ( RT_FAILURE(rc)
1376 && !fRamExists)
1377 {
1378 pVM->pgm.s.cZeroPages -= cb >> PAGE_SHIFT;
1379 pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1380
1381 /* remove the ad-hoc range. */
1382 pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1383 pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1384 MMHyperFree(pVM, pRam);
1385 }
1386
1387 return rc;
1388}
1389
1390
1391/**
1392 * This is the interface IOM is using to register an MMIO region.
1393 *
1394 * It will take care of calling PGMHandlerPhysicalDeregister and clean up
1395 * any ad-hoc PGMRAMRANGE left behind.
1396 *
1397 * @returns VBox status code.
1398 * @param pVM Pointer to the shared VM structure.
1399 * @param GCPhys The start of the MMIO region.
1400 * @param cb The size of the MMIO region.
1401 */
1402VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1403{
1404 VM_ASSERT_EMT(pVM);
1405
1406 /*
1407 * First deregister the handler, then check if we should remove the ram range.
1408 */
1409 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1410 if (RT_SUCCESS(rc))
1411 {
1412 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1413 PPGMRAMRANGE pRamPrev = NULL;
1414 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1415 while (pRam && GCPhysLast >= pRam->GCPhys)
1416 {
1417 /** @todo We're being a bit too careful here. rewrite. */
1418 if ( GCPhysLast == pRam->GCPhysLast
1419 && GCPhys == pRam->GCPhys)
1420 {
1421 Assert(pRam->cb == cb);
1422
1423 /*
1424 * See if all the pages are dead MMIO pages.
1425 */
1426 uint32_t const cPages = cb >> PAGE_SHIFT;
1427 bool fAllMMIO = true;
1428 uint32_t iPage = 0;
1429 uint32_t cLeft = cPages;
1430 while (cLeft-- > 0)
1431 {
1432 PPGMPAGE pPage = &pRam->aPages[iPage];
1433 if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1434 /*|| not-out-of-action later */)
1435 {
1436 fAllMMIO = false;
1437 Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1438 AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1439 break;
1440 }
1441 Assert(PGM_PAGE_IS_ZERO(pPage));
1442 pPage++;
1443 }
1444 if (fAllMMIO)
1445 {
1446 /*
1447 * Ad-hoc range, unlink and free it.
1448 */
1449 Log(("PGMR3PhysMMIODeregister: Freeing ad-hoc MMIO range for %RGp-%RGp %s\n",
1450 GCPhys, GCPhysLast, pRam->pszDesc));
1451
1452 pVM->pgm.s.cAllPages -= cPages;
1453 pVM->pgm.s.cZeroPages -= cPages;
1454
1455 pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1456 pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1457 MMHyperFree(pVM, pRam);
1458 break;
1459 }
1460 }
1461
1462 /*
1463 * Range match? It will all be within one range (see PGMAllHandler.cpp).
1464 */
1465 if ( GCPhysLast >= pRam->GCPhys
1466 && GCPhys <= pRam->GCPhysLast)
1467 {
1468 Assert(GCPhys >= pRam->GCPhys);
1469 Assert(GCPhysLast <= pRam->GCPhysLast);
1470
1471 /*
1472 * Turn the pages back into RAM pages.
1473 */
1474 uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1475 uint32_t cLeft = cb >> PAGE_SHIFT;
1476 while (cLeft--)
1477 {
1478 PPGMPAGE pPage = &pRam->aPages[iPage];
1479 AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1480 AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1481 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1482 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1483 }
1484 break;
1485 }
1486
1487 /* next */
1488 pRamPrev = pRam;
1489 pRam = pRam->pNextR3;
1490 }
1491 }
1492
1493 return rc;
1494}
1495
1496
1497/**
1498 * Locate a MMIO2 range.
1499 *
1500 * @returns Pointer to the MMIO2 range.
1501 * @param pVM Pointer to the shared VM structure.
1502 * @param pDevIns The device instance owning the region.
1503 * @param iRegion The region.
1504 */
1505DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1506{
1507 /*
1508 * Search the list.
1509 */
1510 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1511 if ( pCur->pDevInsR3 == pDevIns
1512 && pCur->iRegion == iRegion)
1513 return pCur;
1514 return NULL;
1515}
1516
1517
1518/**
1519 * Allocate and register an MMIO2 region.
1520 *
1521 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1522 * RAM associated with a device. It is also non-shared memory with a
1523 * permanent ring-3 mapping and page backing (presently).
1524 *
1525 * A MMIO2 range may overlap with base memory if a lot of RAM
1526 * is configured for the VM, in which case we'll drop the base
1527 * memory pages. Presently we will make no attempt to preserve
1528 * anything that happens to be present in the base memory that
1529 * is replaced, this is of course incorrectly but it's too much
1530 * effort.
1531 *
1532 * @returns VBox status code.
1533 * @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1534 * @retval VERR_ALREADY_EXISTS if the region already exists.
1535 *
1536 * @param pVM Pointer to the shared VM structure.
1537 * @param pDevIns The device instance owning the region.
1538 * @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1539 * this number has to be the number of that region. Otherwise
1540 * it can be any number safe UINT8_MAX.
1541 * @param cb The size of the region. Must be page aligned.
1542 * @param fFlags Reserved for future use, must be zero.
1543 * @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1544 * @param pszDesc The description.
1545 */
1546VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)
1547{
1548 /*
1549 * Validate input.
1550 */
1551 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1552 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1553 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1554 AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1555 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1556 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1557 AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1558 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1559 AssertReturn(cb, VERR_INVALID_PARAMETER);
1560 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1561
1562 const uint32_t cPages = cb >> PAGE_SHIFT;
1563 AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1564 AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1565
1566 /*
1567 * For the 2nd+ instance, mangle the description string so it's unique.
1568 */
1569 if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
1570 {
1571 pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1572 if (!pszDesc)
1573 return VERR_NO_MEMORY;
1574 }
1575
1576 /*
1577 * Try reserve and allocate the backing memory first as this is what is
1578 * most likely to fail.
1579 */
1580 int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1581 if (RT_SUCCESS(rc))
1582 {
1583 void *pvPages;
1584 PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1585 if (RT_SUCCESS(rc))
1586 rc = SUPR3PageAllocEx(cPages, 0 /*fFlags*/, &pvPages, NULL /*pR0Ptr*/, paPages);
1587 if (RT_SUCCESS(rc))
1588 {
1589 memset(pvPages, 0, cPages * PAGE_SIZE);
1590
1591 /*
1592 * Create the MMIO2 range record for it.
1593 */
1594 const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1595 PPGMMMIO2RANGE pNew;
1596 rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1597 AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1598 if (RT_SUCCESS(rc))
1599 {
1600 pNew->pDevInsR3 = pDevIns;
1601 pNew->pvR3 = pvPages;
1602 //pNew->pNext = NULL;
1603 //pNew->fMapped = false;
1604 //pNew->fOverlapping = false;
1605 pNew->iRegion = iRegion;
1606 pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1607 pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1608 pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1609 pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1610 pNew->RamRange.pszDesc = pszDesc;
1611 pNew->RamRange.cb = cb;
1612 //pNew->RamRange.fFlags = 0; /// @todo MMIO2 flag?
1613
1614 pNew->RamRange.pvR3 = pvPages;
1615
1616 uint32_t iPage = cPages;
1617 while (iPage-- > 0)
1618 {
1619 PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1620 paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
1621 PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1622 }
1623
1624 /* update page count stats */
1625 pVM->pgm.s.cAllPages += cPages;
1626 pVM->pgm.s.cPrivatePages += cPages;
1627
1628 /*
1629 * Link it into the list.
1630 * Since there is no particular order, just push it.
1631 */
1632 pgmLock(pVM);
1633 pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1634 pVM->pgm.s.pMmio2RangesR3 = pNew;
1635 pgmUnlock(pVM);
1636
1637 *ppv = pvPages;
1638 RTMemTmpFree(paPages);
1639 return VINF_SUCCESS;
1640 }
1641
1642 SUPR3PageFreeEx(pvPages, cPages);
1643 }
1644 RTMemTmpFree(paPages);
1645 MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1646 }
1647 if (pDevIns->iInstance > 0)
1648 MMR3HeapFree((void *)pszDesc);
1649 return rc;
1650}
1651
1652
1653/**
1654 * Deregisters and frees an MMIO2 region.
1655 *
1656 * Any physical (and virtual) access handlers registered for the region must
1657 * be deregistered before calling this function.
1658 *
1659 * @returns VBox status code.
1660 * @param pVM Pointer to the shared VM structure.
1661 * @param pDevIns The device instance owning the region.
1662 * @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1663 */
1664VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1665{
1666 /*
1667 * Validate input.
1668 */
1669 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1670 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1671 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1672
1673 pgmLock(pVM);
1674 int rc = VINF_SUCCESS;
1675 unsigned cFound = 0;
1676 PPGMMMIO2RANGE pPrev = NULL;
1677 PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1678 while (pCur)
1679 {
1680 if ( pCur->pDevInsR3 == pDevIns
1681 && ( iRegion == UINT32_MAX
1682 || pCur->iRegion == iRegion))
1683 {
1684 cFound++;
1685
1686 /*
1687 * Unmap it if it's mapped.
1688 */
1689 if (pCur->fMapped)
1690 {
1691 int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1692 AssertRC(rc2);
1693 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1694 rc = rc2;
1695 }
1696
1697 /*
1698 * Unlink it
1699 */
1700 PPGMMMIO2RANGE pNext = pCur->pNextR3;
1701 if (pPrev)
1702 pPrev->pNextR3 = pNext;
1703 else
1704 pVM->pgm.s.pMmio2RangesR3 = pNext;
1705 pCur->pNextR3 = NULL;
1706
1707 /*
1708 * Free the memory.
1709 */
1710 int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1711 AssertRC(rc2);
1712 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1713 rc = rc2;
1714
1715 uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1716 rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1717 AssertRC(rc2);
1718 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1719 rc = rc2;
1720
1721 /* we're leaking hyper memory here if done at runtime. */
1722#ifdef VBOX_STRICT
1723 VMSTATE const enmState = VMR3GetState(pVM);
1724 AssertMsg( enmState == VMSTATE_POWERING_OFF
1725 || enmState == VMSTATE_POWERING_OFF_LS
1726 || enmState == VMSTATE_OFF
1727 || enmState == VMSTATE_OFF_LS
1728 || enmState == VMSTATE_DESTROYING
1729 || enmState == VMSTATE_TERMINATED
1730 || enmState == VMSTATE_CREATING
1731 , ("%s\n", VMR3GetStateName(enmState)));
1732#endif
1733 /*rc = MMHyperFree(pVM, pCur);
1734 AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1735
1736
1737 /* update page count stats */
1738 pVM->pgm.s.cAllPages -= cPages;
1739 pVM->pgm.s.cPrivatePages -= cPages;
1740
1741 /* next */
1742 pCur = pNext;
1743 }
1744 else
1745 {
1746 pPrev = pCur;
1747 pCur = pCur->pNextR3;
1748 }
1749 }
1750 pgmUnlock(pVM);
1751 return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1752}
1753
1754
1755/**
1756 * Maps a MMIO2 region.
1757 *
1758 * This is done when a guest / the bios / state loading changes the
1759 * PCI config. The replacing of base memory has the same restrictions
1760 * as during registration, of course.
1761 *
1762 * @returns VBox status code.
1763 *
1764 * @param pVM Pointer to the shared VM structure.
1765 * @param pDevIns The
1766 */
1767VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1768{
1769 /*
1770 * Validate input
1771 */
1772 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1773 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1774 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1775 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1776 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1777 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1778
1779 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1780 AssertReturn(pCur, VERR_NOT_FOUND);
1781 AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
1782 Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
1783 Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
1784
1785 const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
1786 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1787
1788 /*
1789 * Find our location in the ram range list, checking for
1790 * restriction we don't bother implementing yet (partially overlapping).
1791 */
1792 bool fRamExists = false;
1793 PPGMRAMRANGE pRamPrev = NULL;
1794 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1795 while (pRam && GCPhysLast >= pRam->GCPhys)
1796 {
1797 if ( GCPhys <= pRam->GCPhysLast
1798 && GCPhysLast >= pRam->GCPhys)
1799 {
1800 /* completely within? */
1801 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1802 && GCPhysLast <= pRam->GCPhysLast,
1803 ("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
1804 GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
1805 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1806 VERR_PGM_RAM_CONFLICT);
1807 fRamExists = true;
1808 break;
1809 }
1810
1811 /* next */
1812 pRamPrev = pRam;
1813 pRam = pRam->pNextR3;
1814 }
1815 if (fRamExists)
1816 {
1817 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1818 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1819 while (cPagesLeft-- > 0)
1820 {
1821 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1822 ("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
1823 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
1824 VERR_PGM_RAM_CONFLICT);
1825 pPage++;
1826 }
1827 }
1828 Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
1829 GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
1830
1831 /*
1832 * Make the changes.
1833 */
1834 pgmLock(pVM);
1835
1836 pCur->RamRange.GCPhys = GCPhys;
1837 pCur->RamRange.GCPhysLast = GCPhysLast;
1838 pCur->fMapped = true;
1839 pCur->fOverlapping = fRamExists;
1840
1841 if (fRamExists)
1842 {
1843/** @todo use pgmR3PhysFreePageRange here. */
1844 uint32_t cPendingPages = 0;
1845 PGMMFREEPAGESREQ pReq;
1846 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1847 AssertLogRelRCReturn(rc, rc);
1848
1849 /* replace the pages, freeing all present RAM pages. */
1850 PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
1851 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1852 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1853 while (cPagesLeft-- > 0)
1854 {
1855 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
1856 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1857
1858 RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
1859 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
1860 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
1861 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
1862
1863 pVM->pgm.s.cZeroPages--;
1864 GCPhys += PAGE_SIZE;
1865 pPageSrc++;
1866 pPageDst++;
1867 }
1868
1869 if (cPendingPages)
1870 {
1871 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1872 AssertLogRelRCReturn(rc, rc);
1873 }
1874 GMMR3FreePagesCleanup(pReq);
1875 pgmUnlock(pVM);
1876 }
1877 else
1878 {
1879 RTGCPHYS cb = pCur->RamRange.cb;
1880
1881 /* link in the ram range */
1882 pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
1883 pgmUnlock(pVM);
1884
1885 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
1886 }
1887
1888 return VINF_SUCCESS;
1889}
1890
1891
1892/**
1893 * Unmaps a MMIO2 region.
1894 *
1895 * This is done when a guest / the bios / state loading changes the
1896 * PCI config. The replacing of base memory has the same restrictions
1897 * as during registration, of course.
1898 */
1899VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1900{
1901 bool fInformREM = false;
1902 RTGCPHYS GCPhysRangeREM;
1903 RTGCPHYS cbRangeREM;
1904
1905 /*
1906 * Validate input
1907 */
1908 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1909 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1910 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1911 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1912 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1913 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1914
1915 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1916 AssertReturn(pCur, VERR_NOT_FOUND);
1917 AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
1918 AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
1919 Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
1920
1921 Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
1922 pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
1923
1924 /*
1925 * Unmap it.
1926 */
1927 pgmLock(pVM);
1928
1929 if (pCur->fOverlapping)
1930 {
1931 /* Restore the RAM pages we've replaced. */
1932 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1933 while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
1934 pRam = pRam->pNextR3;
1935
1936 RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
1937 Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
1938 PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1939 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1940 while (cPagesLeft-- > 0)
1941 {
1942 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
1943 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
1944 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
1945 PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
1946
1947 pVM->pgm.s.cZeroPages++;
1948 pPageDst++;
1949 }
1950 }
1951 else
1952 {
1953 GCPhysRangeREM = pCur->RamRange.GCPhys;
1954 cbRangeREM = pCur->RamRange.cb;
1955 fInformREM = true;
1956
1957 pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
1958 }
1959
1960 pCur->RamRange.GCPhys = NIL_RTGCPHYS;
1961 pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
1962 pCur->fOverlapping = false;
1963 pCur->fMapped = false;
1964
1965 pgmUnlock(pVM);
1966
1967 if (fInformREM)
1968 REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
1969
1970 return VINF_SUCCESS;
1971}
1972
1973
1974/**
1975 * Checks if the given address is an MMIO2 base address or not.
1976 *
1977 * @returns true/false accordingly.
1978 * @param pVM Pointer to the shared VM structure.
1979 * @param pDevIns The owner of the memory, optional.
1980 * @param GCPhys The address to check.
1981 */
1982VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
1983{
1984 /*
1985 * Validate input
1986 */
1987 VM_ASSERT_EMT_RETURN(pVM, false);
1988 AssertPtrReturn(pDevIns, false);
1989 AssertReturn(GCPhys != NIL_RTGCPHYS, false);
1990 AssertReturn(GCPhys != 0, false);
1991 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
1992
1993 /*
1994 * Search the list.
1995 */
1996 pgmLock(pVM);
1997 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1998 if (pCur->RamRange.GCPhys == GCPhys)
1999 {
2000 Assert(pCur->fMapped);
2001 pgmUnlock(pVM);
2002 return true;
2003 }
2004 pgmUnlock(pVM);
2005 return false;
2006}
2007
2008
2009/**
2010 * Gets the HC physical address of a page in the MMIO2 region.
2011 *
2012 * This is API is intended for MMHyper and shouldn't be called
2013 * by anyone else...
2014 *
2015 * @returns VBox status code.
2016 * @param pVM Pointer to the shared VM structure.
2017 * @param pDevIns The owner of the memory, optional.
2018 * @param iRegion The region.
2019 * @param off The page expressed an offset into the MMIO2 region.
2020 * @param pHCPhys Where to store the result.
2021 */
2022VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2023{
2024 /*
2025 * Validate input
2026 */
2027 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2028 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2029 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2030
2031 pgmLock(pVM);
2032 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2033 AssertReturn(pCur, VERR_NOT_FOUND);
2034 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2035
2036 PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2037 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2038 pgmUnlock(pVM);
2039 return VINF_SUCCESS;
2040}
2041
2042
2043/**
2044 * Maps a portion of an MMIO2 region into kernel space (host).
2045 *
2046 * The kernel mapping will become invalid when the MMIO2 memory is deregistered
2047 * or the VM is terminated.
2048 *
2049 * @return VBox status code.
2050 *
2051 * @param pVM Pointer to the shared VM structure.
2052 * @param pDevIns The device owning the MMIO2 memory.
2053 * @param iRegion The region.
2054 * @param off The offset into the region. Must be page aligned.
2055 * @param cb The number of bytes to map. Must be page aligned.
2056 * @param pszDesc Mapping description.
2057 * @param pR0Ptr Where to store the R0 address.
2058 */
2059VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2060 const char *pszDesc, PRTR0PTR pR0Ptr)
2061{
2062 /*
2063 * Validate input.
2064 */
2065 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2066 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2067 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2068
2069 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2070 AssertReturn(pCur, VERR_NOT_FOUND);
2071 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2072 AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2073 AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2074
2075 /*
2076 * Pass the request on to the support library/driver.
2077 */
2078 int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2079
2080 return rc;
2081}
2082
2083
2084/**
2085 * Registers a ROM image.
2086 *
2087 * Shadowed ROM images requires double the amount of backing memory, so,
2088 * don't use that unless you have to. Shadowing of ROM images is process
2089 * where we can select where the reads go and where the writes go. On real
2090 * hardware the chipset provides means to configure this. We provide
2091 * PGMR3PhysProtectROM() for this purpose.
2092 *
2093 * A read-only copy of the ROM image will always be kept around while we
2094 * will allocate RAM pages for the changes on demand (unless all memory
2095 * is configured to be preallocated).
2096 *
2097 * @returns VBox status.
2098 * @param pVM VM Handle.
2099 * @param pDevIns The device instance owning the ROM.
2100 * @param GCPhys First physical address in the range.
2101 * Must be page aligned!
2102 * @param cbRange The size of the range (in bytes).
2103 * Must be page aligned!
2104 * @param pvBinary Pointer to the binary data backing the ROM image.
2105 * This must be exactly \a cbRange in size.
2106 * @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2107 * and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2108 * @param pszDesc Pointer to description string. This must not be freed.
2109 *
2110 * @remark There is no way to remove the rom, automatically on device cleanup or
2111 * manually from the device yet. This isn't difficult in any way, it's
2112 * just not something we expect to be necessary for a while.
2113 */
2114VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2115 const void *pvBinary, uint32_t fFlags, const char *pszDesc)
2116{
2117 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2118 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2119
2120 /*
2121 * Validate input.
2122 */
2123 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2124 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2125 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2126 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2127 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2128 AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2129 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2130 AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED | PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2131 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2132
2133 const uint32_t cPages = cb >> PAGE_SHIFT;
2134
2135 /*
2136 * Find the ROM location in the ROM list first.
2137 */
2138 PPGMROMRANGE pRomPrev = NULL;
2139 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2140 while (pRom && GCPhysLast >= pRom->GCPhys)
2141 {
2142 if ( GCPhys <= pRom->GCPhysLast
2143 && GCPhysLast >= pRom->GCPhys)
2144 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2145 GCPhys, GCPhysLast, pszDesc,
2146 pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2147 VERR_PGM_RAM_CONFLICT);
2148 /* next */
2149 pRomPrev = pRom;
2150 pRom = pRom->pNextR3;
2151 }
2152
2153 /*
2154 * Find the RAM location and check for conflicts.
2155 *
2156 * Conflict detection is a bit different than for RAM
2157 * registration since a ROM can be located within a RAM
2158 * range. So, what we have to check for is other memory
2159 * types (other than RAM that is) and that we don't span
2160 * more than one RAM range (layz).
2161 */
2162 bool fRamExists = false;
2163 PPGMRAMRANGE pRamPrev = NULL;
2164 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2165 while (pRam && GCPhysLast >= pRam->GCPhys)
2166 {
2167 if ( GCPhys <= pRam->GCPhysLast
2168 && GCPhysLast >= pRam->GCPhys)
2169 {
2170 /* completely within? */
2171 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2172 && GCPhysLast <= pRam->GCPhysLast,
2173 ("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2174 GCPhys, GCPhysLast, pszDesc,
2175 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2176 VERR_PGM_RAM_CONFLICT);
2177 fRamExists = true;
2178 break;
2179 }
2180
2181 /* next */
2182 pRamPrev = pRam;
2183 pRam = pRam->pNextR3;
2184 }
2185 if (fRamExists)
2186 {
2187 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2188 uint32_t cPagesLeft = cPages;
2189 while (cPagesLeft-- > 0)
2190 {
2191 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2192 ("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2193 pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2194 pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2195 Assert(PGM_PAGE_IS_ZERO(pPage));
2196 pPage++;
2197 }
2198 }
2199
2200 /*
2201 * Update the base memory reservation if necessary.
2202 */
2203 uint32_t cExtraBaseCost = fRamExists ? cPages : 0;
2204 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2205 cExtraBaseCost += cPages;
2206 if (cExtraBaseCost)
2207 {
2208 int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2209 if (RT_FAILURE(rc))
2210 return rc;
2211 }
2212
2213 /*
2214 * Allocate memory for the virgin copy of the RAM.
2215 */
2216 PGMMALLOCATEPAGESREQ pReq;
2217 int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2218 AssertRCReturn(rc, rc);
2219
2220 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2221 {
2222 pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2223 pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2224 pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2225 }
2226
2227 pgmLock(pVM);
2228 rc = GMMR3AllocatePagesPerform(pVM, pReq);
2229 pgmUnlock(pVM);
2230 if (RT_FAILURE(rc))
2231 {
2232 GMMR3AllocatePagesCleanup(pReq);
2233 return rc;
2234 }
2235
2236 /*
2237 * Allocate the new ROM range and RAM range (if necessary).
2238 */
2239 PPGMROMRANGE pRomNew;
2240 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2241 if (RT_SUCCESS(rc))
2242 {
2243 PPGMRAMRANGE pRamNew = NULL;
2244 if (!fRamExists)
2245 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2246 if (RT_SUCCESS(rc))
2247 {
2248 pgmLock(pVM);
2249
2250 /*
2251 * Initialize and insert the RAM range (if required).
2252 */
2253 PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2254 if (!fRamExists)
2255 {
2256 pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2257 pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2258 pRamNew->GCPhys = GCPhys;
2259 pRamNew->GCPhysLast = GCPhysLast;
2260 pRamNew->cb = cb;
2261 pRamNew->pszDesc = pszDesc;
2262 pRamNew->fFlags = 0;
2263 pRamNew->pvR3 = NULL;
2264
2265 PPGMPAGE pPage = &pRamNew->aPages[0];
2266 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2267 {
2268 PGM_PAGE_INIT(pPage,
2269 pReq->aPages[iPage].HCPhysGCPhys,
2270 pReq->aPages[iPage].idPage,
2271 PGMPAGETYPE_ROM,
2272 PGM_PAGE_STATE_ALLOCATED);
2273
2274 pRomPage->Virgin = *pPage;
2275 }
2276
2277 pVM->pgm.s.cAllPages += cPages;
2278 pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2279 }
2280 else
2281 {
2282 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2283 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2284 {
2285 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2286 PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2287 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2288 PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2289
2290 pRomPage->Virgin = *pPage;
2291 }
2292
2293 pRamNew = pRam;
2294
2295 pVM->pgm.s.cZeroPages -= cPages;
2296 }
2297 pVM->pgm.s.cPrivatePages += cPages;
2298
2299 pgmUnlock(pVM);
2300
2301
2302 /*
2303 * !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2304 *
2305 * If it's shadowed we'll register the handler after the ROM notification
2306 * so we get the access handler callbacks that we should. If it isn't
2307 * shadowed we'll do it the other way around to make REM use the built-in
2308 * ROM behavior and not the handler behavior (which is to route all access
2309 * to PGM atm).
2310 */
2311 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2312 {
2313 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2314 rc = PGMR3HandlerPhysicalRegister(pVM,
2315 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2316 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2317 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2318 GCPhys, GCPhysLast,
2319 pgmR3PhysRomWriteHandler, pRomNew,
2320 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2321 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2322 }
2323 else
2324 {
2325 rc = PGMR3HandlerPhysicalRegister(pVM,
2326 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2327 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2328 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2329 GCPhys, GCPhysLast,
2330 pgmR3PhysRomWriteHandler, pRomNew,
2331 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2332 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2333 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2334 }
2335 if (RT_SUCCESS(rc))
2336 {
2337 pgmLock(pVM);
2338
2339 /*
2340 * Copy the image over to the virgin pages.
2341 * This must be done after linking in the RAM range.
2342 */
2343 PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2344 for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2345 {
2346 void *pvDstPage;
2347 PPGMPAGEMAP pMapIgnored;
2348 rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pMapIgnored, &pvDstPage);
2349 if (RT_FAILURE(rc))
2350 {
2351 VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2352 break;
2353 }
2354 memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2355 }
2356 if (RT_SUCCESS(rc))
2357 {
2358 /*
2359 * Initialize the ROM range.
2360 * Note that the Virgin member of the pages has already been initialized above.
2361 */
2362 pRomNew->GCPhys = GCPhys;
2363 pRomNew->GCPhysLast = GCPhysLast;
2364 pRomNew->cb = cb;
2365 pRomNew->fFlags = fFlags;
2366 pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2367 pRomNew->pszDesc = pszDesc;
2368
2369 for (unsigned iPage = 0; iPage < cPages; iPage++)
2370 {
2371 PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2372 pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2373 PGM_PAGE_INIT_ZERO_REAL(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2374 }
2375
2376 /* update the page count stats */
2377 pVM->pgm.s.cZeroPages += cPages;
2378 pVM->pgm.s.cAllPages += cPages;
2379
2380 /*
2381 * Insert the ROM range, tell REM and return successfully.
2382 */
2383 pRomNew->pNextR3 = pRom;
2384 pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2385 pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2386
2387 if (pRomPrev)
2388 {
2389 pRomPrev->pNextR3 = pRomNew;
2390 pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2391 pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2392 }
2393 else
2394 {
2395 pVM->pgm.s.pRomRangesR3 = pRomNew;
2396 pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2397 pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2398 }
2399
2400 GMMR3AllocatePagesCleanup(pReq);
2401 pgmUnlock(pVM);
2402 return VINF_SUCCESS;
2403 }
2404
2405 /* bail out */
2406
2407 pgmUnlock(pVM);
2408 int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2409 AssertRC(rc2);
2410 pgmLock(pVM);
2411 }
2412
2413 if (!fRamExists)
2414 {
2415 pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2416 MMHyperFree(pVM, pRamNew);
2417 }
2418 }
2419 MMHyperFree(pVM, pRomNew);
2420 }
2421
2422 /** @todo Purge the mapping cache or something... */
2423 GMMR3FreeAllocatedPages(pVM, pReq);
2424 GMMR3AllocatePagesCleanup(pReq);
2425 pgmUnlock(pVM);
2426 return rc;
2427}
2428
2429
2430/**
2431 * \#PF Handler callback for ROM write accesses.
2432 *
2433 * @returns VINF_SUCCESS if the handler have carried out the operation.
2434 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2435 * @param pVM VM Handle.
2436 * @param GCPhys The physical address the guest is writing to.
2437 * @param pvPhys The HC mapping of that address.
2438 * @param pvBuf What the guest is reading/writing.
2439 * @param cbBuf How much it's reading/writing.
2440 * @param enmAccessType The access type.
2441 * @param pvUser User argument.
2442 */
2443static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2444{
2445 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2446 const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2447 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2448 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2449 Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2450
2451 if (enmAccessType == PGMACCESSTYPE_READ)
2452 {
2453 switch (pRomPage->enmProt)
2454 {
2455 /*
2456 * Take the default action.
2457 */
2458 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2459 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2460 case PGMROMPROT_READ_ROM_WRITE_RAM:
2461 case PGMROMPROT_READ_RAM_WRITE_RAM:
2462 return VINF_PGM_HANDLER_DO_DEFAULT;
2463
2464 default:
2465 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2466 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2467 VERR_INTERNAL_ERROR);
2468 }
2469 }
2470 else
2471 {
2472 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2473 switch (pRomPage->enmProt)
2474 {
2475 /*
2476 * Ignore writes.
2477 */
2478 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2479 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2480 return VINF_SUCCESS;
2481
2482 /*
2483 * Write to the ram page.
2484 */
2485 case PGMROMPROT_READ_ROM_WRITE_RAM:
2486 case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
2487 {
2488 /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2489 Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2490
2491 /*
2492 * Take the lock, do lazy allocation, map the page and copy the data.
2493 *
2494 * Note that we have to bypass the mapping TLB since it works on
2495 * guest physical addresses and entering the shadow page would
2496 * kind of screw things up...
2497 */
2498 int rc = pgmLock(pVM);
2499 AssertRC(rc);
2500 PPGMPAGE pShadowPage = &pRomPage->Shadow;
2501 if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2502 {
2503 pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2504 AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2505 }
2506
2507 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pShadowPage) != PGM_PAGE_STATE_ALLOCATED))
2508 {
2509 rc = pgmPhysPageMakeWritable(pVM, pShadowPage, GCPhys);
2510 if (RT_FAILURE(rc))
2511 {
2512 pgmUnlock(pVM);
2513 return rc;
2514 }
2515 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* returned */, ("%Rrc\n", rc));
2516 }
2517
2518 void *pvDstPage;
2519 PPGMPAGEMAP pMapIgnored;
2520 int rc2 = pgmPhysPageMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pMapIgnored, &pvDstPage);
2521 if (RT_SUCCESS(rc2))
2522 memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2523 else
2524 rc = rc2;
2525
2526 pgmUnlock(pVM);
2527 return rc;
2528 }
2529
2530 default:
2531 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2532 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2533 VERR_INTERNAL_ERROR);
2534 }
2535 }
2536}
2537
2538
2539/**
2540 * Called by PGMR3Reset to reset the shadow, switch to the virgin,
2541 * and verify that the virgin part is untouched.
2542 *
2543 * This is done after the normal memory has been cleared.
2544 *
2545 * ASSUMES that the caller owns the PGM lock.
2546 *
2547 * @param pVM The VM handle.
2548 */
2549int pgmR3PhysRomReset(PVM pVM)
2550{
2551 Assert(PGMIsLockOwner(pVM));
2552 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2553 {
2554 const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2555
2556 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2557 {
2558 /*
2559 * Reset the physical handler.
2560 */
2561 int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2562 AssertRCReturn(rc, rc);
2563
2564 /*
2565 * What we do with the shadow pages depends on the memory
2566 * preallocation option. If not enabled, we'll just throw
2567 * out all the dirty pages and replace them by the zero page.
2568 */
2569 if (!pVM->pgm.s.fRamPreAlloc)
2570 {
2571 /* Free the dirty pages. */
2572 uint32_t cPendingPages = 0;
2573 PGMMFREEPAGESREQ pReq;
2574 rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2575 AssertRCReturn(rc, rc);
2576
2577 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2578 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
2579 {
2580 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2581 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2582 AssertLogRelRCReturn(rc, rc);
2583 }
2584
2585 if (cPendingPages)
2586 {
2587 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2588 AssertLogRelRCReturn(rc, rc);
2589 }
2590 GMMR3FreePagesCleanup(pReq);
2591 }
2592 else
2593 {
2594 /* clear all the shadow pages. */
2595 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2596 {
2597 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO);
2598
2599 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2600 rc = pgmPhysPageMakeWritable(pVM, &pRom->aPages[iPage].Shadow, GCPhys);
2601 if (RT_FAILURE(rc))
2602 break;
2603
2604 void *pvDstPage;
2605 PPGMPAGEMAP pMapIgnored;
2606 rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pMapIgnored, &pvDstPage);
2607 if (RT_FAILURE(rc))
2608 break;
2609 ASMMemZeroPage(pvDstPage);
2610 }
2611 AssertRCReturn(rc, rc);
2612 }
2613 }
2614
2615#ifdef VBOX_STRICT
2616 /*
2617 * Verify that the virgin page is unchanged if possible.
2618 */
2619 if (pRom->pvOriginal)
2620 {
2621 uint8_t const *pbSrcPage = (uint8_t const *)pRom->pvOriginal;
2622 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2623 {
2624 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2625 PPGMPAGEMAP pMapIgnored;
2626 void *pvDstPage;
2627 int rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pMapIgnored, &pvDstPage);
2628 if (RT_FAILURE(rc))
2629 break;
2630 if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2631 LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2632 GCPhys, pRom->pszDesc));
2633 }
2634 }
2635#endif
2636 }
2637
2638 return VINF_SUCCESS;
2639}
2640
2641
2642/**
2643 * Change the shadowing of a range of ROM pages.
2644 *
2645 * This is intended for implementing chipset specific memory registers
2646 * and will not be very strict about the input. It will silently ignore
2647 * any pages that are not the part of a shadowed ROM.
2648 *
2649 * @returns VBox status code.
2650 * @retval VINF_PGM_SYNC_CR3
2651 *
2652 * @param pVM Pointer to the shared VM structure.
2653 * @param GCPhys Where to start. Page aligned.
2654 * @param cb How much to change. Page aligned.
2655 * @param enmProt The new ROM protection.
2656 */
2657VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2658{
2659 /*
2660 * Check input
2661 */
2662 if (!cb)
2663 return VINF_SUCCESS;
2664 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2665 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2666 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2667 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2668 AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2669
2670 /*
2671 * Process the request.
2672 */
2673 pgmLock(pVM);
2674 int rc = VINF_SUCCESS;
2675 bool fFlushTLB = false;
2676 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2677 {
2678 if ( GCPhys <= pRom->GCPhysLast
2679 && GCPhysLast >= pRom->GCPhys
2680 && (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2681 {
2682 /*
2683 * Iterate the relevant pages and make necessary the changes.
2684 */
2685 bool fChanges = false;
2686 uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2687 ? pRom->cb >> PAGE_SHIFT
2688 : (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2689 for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2690 iPage < cPages;
2691 iPage++)
2692 {
2693 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2694 if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2695 {
2696 fChanges = true;
2697
2698 /* flush references to the page. */
2699 PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2700 int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRamPage, &fFlushTLB);
2701 if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS || RT_FAILURE(rc2)))
2702 rc = rc2;
2703
2704 PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2705 PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2706
2707 *pOld = *pRamPage;
2708 *pRamPage = *pNew;
2709 /** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2710 }
2711 pRomPage->enmProt = enmProt;
2712 }
2713
2714 /*
2715 * Reset the access handler if we made changes, no need
2716 * to optimize this.
2717 */
2718 if (fChanges)
2719 {
2720 int rc = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2721 if (RT_FAILURE(rc))
2722 {
2723 pgmUnlock(pVM);
2724 AssertRC(rc);
2725 return rc;
2726 }
2727 }
2728
2729 /* Advance - cb isn't updated. */
2730 GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2731 }
2732 }
2733 pgmUnlock(pVM);
2734 if (fFlushTLB)
2735 PGM_INVL_ALL_VCPU_TLBS(pVM);
2736
2737 return rc;
2738}
2739
2740
2741/**
2742 * Sets the Address Gate 20 state.
2743 *
2744 * @param pVCpu The VCPU to operate on.
2745 * @param fEnable True if the gate should be enabled.
2746 * False if the gate should be disabled.
2747 */
2748VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
2749{
2750 LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
2751 if (pVCpu->pgm.s.fA20Enabled != fEnable)
2752 {
2753 pVCpu->pgm.s.fA20Enabled = fEnable;
2754 pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2755 REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
2756 /** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2757 }
2758}
2759
2760
2761/**
2762 * Tree enumeration callback for dealing with age rollover.
2763 * It will perform a simple compression of the current age.
2764 */
2765static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2766{
2767 Assert(PGMIsLockOwner((PVM)pvUser));
2768 /* Age compression - ASSUMES iNow == 4. */
2769 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2770 if (pChunk->iAge >= UINT32_C(0xffffff00))
2771 pChunk->iAge = 3;
2772 else if (pChunk->iAge >= UINT32_C(0xfffff000))
2773 pChunk->iAge = 2;
2774 else if (pChunk->iAge)
2775 pChunk->iAge = 1;
2776 else /* iAge = 0 */
2777 pChunk->iAge = 4;
2778
2779 /* reinsert */
2780 PVM pVM = (PVM)pvUser;
2781 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2782 pChunk->AgeCore.Key = pChunk->iAge;
2783 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2784 return 0;
2785}
2786
2787
2788/**
2789 * Tree enumeration callback that updates the chunks that have
2790 * been used since the last
2791 */
2792static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
2793{
2794 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2795 if (!pChunk->iAge)
2796 {
2797 PVM pVM = (PVM)pvUser;
2798 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2799 pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
2800 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2801 }
2802
2803 return 0;
2804}
2805
2806
2807/**
2808 * Performs ageing of the ring-3 chunk mappings.
2809 *
2810 * @param pVM The VM handle.
2811 */
2812VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
2813{
2814 pgmLock(pVM);
2815 pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
2816 pVM->pgm.s.ChunkR3Map.iNow++;
2817 if (pVM->pgm.s.ChunkR3Map.iNow == 0)
2818 {
2819 pVM->pgm.s.ChunkR3Map.iNow = 4;
2820 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
2821 }
2822 else
2823 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingCallback, pVM);
2824 pgmUnlock(pVM);
2825}
2826
2827
2828/**
2829 * The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
2830 */
2831typedef struct PGMR3PHYSCHUNKUNMAPCB
2832{
2833 PVM pVM; /**< The VM handle. */
2834 PPGMCHUNKR3MAP pChunk; /**< The chunk to unmap. */
2835} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
2836
2837
2838/**
2839 * Callback used to find the mapping that's been unused for
2840 * the longest time.
2841 */
2842static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
2843{
2844 do
2845 {
2846 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
2847 if ( pChunk->iAge
2848 && !pChunk->cRefs)
2849 {
2850 /*
2851 * Check that it's not in any of the TLBs.
2852 */
2853 PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
2854 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2855 if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
2856 {
2857 pChunk = NULL;
2858 break;
2859 }
2860 if (pChunk)
2861 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
2862 if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
2863 {
2864 pChunk = NULL;
2865 break;
2866 }
2867 if (pChunk)
2868 {
2869 ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
2870 return 1; /* done */
2871 }
2872 }
2873
2874 /* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
2875 pNode = pNode->pList;
2876 } while (pNode);
2877 return 0;
2878}
2879
2880
2881/**
2882 * Finds a good candidate for unmapping when the ring-3 mapping cache is full.
2883 *
2884 * The candidate will not be part of any TLBs, so no need to flush
2885 * anything afterwards.
2886 *
2887 * @returns Chunk id.
2888 * @param pVM The VM handle.
2889 */
2890static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
2891{
2892 Assert(PGMIsLockOwner(pVM));
2893
2894 /*
2895 * Do tree ageing first?
2896 */
2897 if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
2898 PGMR3PhysChunkAgeing(pVM);
2899
2900 /*
2901 * Enumerate the age tree starting with the left most node.
2902 */
2903 PGMR3PHYSCHUNKUNMAPCB Args;
2904 Args.pVM = pVM;
2905 Args.pChunk = NULL;
2906 if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /*fFromLeft*/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
2907 return Args.pChunk->Core.Key;
2908 return INT32_MAX;
2909}
2910
2911
2912/**
2913 * Maps the given chunk into the ring-3 mapping cache.
2914 *
2915 * This will call ring-0.
2916 *
2917 * @returns VBox status code.
2918 * @param pVM The VM handle.
2919 * @param idChunk The chunk in question.
2920 * @param ppChunk Where to store the chunk tracking structure.
2921 *
2922 * @remarks Called from within the PGM critical section.
2923 */
2924int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
2925{
2926 int rc;
2927
2928 Assert(PGMIsLockOwner(pVM));
2929 /*
2930 * Allocate a new tracking structure first.
2931 */
2932#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2933 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
2934#else
2935 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
2936#endif
2937 AssertReturn(pChunk, VERR_NO_MEMORY);
2938 pChunk->Core.Key = idChunk;
2939 pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
2940 pChunk->iAge = 0;
2941 pChunk->cRefs = 0;
2942 pChunk->cPermRefs = 0;
2943 pChunk->pv = NULL;
2944
2945 /*
2946 * Request the ring-0 part to map the chunk in question and if
2947 * necessary unmap another one to make space in the mapping cache.
2948 */
2949 GMMMAPUNMAPCHUNKREQ Req;
2950 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2951 Req.Hdr.cbReq = sizeof(Req);
2952 Req.pvR3 = NULL;
2953 Req.idChunkMap = idChunk;
2954 Req.idChunkUnmap = NIL_GMM_CHUNKID;
2955 if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
2956 Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
2957/** @todo This is wrong. Any thread in the VM process should be able to do this,
2958 * there are depenenecies on this. What currently saves the day is that
2959 * we don't unmap anything and that all non-zero memory will therefore
2960 * be present when non-EMTs tries to access it. */
2961 rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
2962 if (RT_SUCCESS(rc))
2963 {
2964 /*
2965 * Update the tree.
2966 */
2967 /* insert the new one. */
2968 AssertPtr(Req.pvR3);
2969 pChunk->pv = Req.pvR3;
2970 bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
2971 AssertRelease(fRc);
2972 pVM->pgm.s.ChunkR3Map.c++;
2973
2974 fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2975 AssertRelease(fRc);
2976
2977 /* remove the unmapped one. */
2978 if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
2979 {
2980 PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
2981 AssertRelease(pUnmappedChunk);
2982 pUnmappedChunk->pv = NULL;
2983 pUnmappedChunk->Core.Key = UINT32_MAX;
2984#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2985 MMR3HeapFree(pUnmappedChunk);
2986#else
2987 MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
2988#endif
2989 pVM->pgm.s.ChunkR3Map.c--;
2990 }
2991 }
2992 else
2993 {
2994 AssertRC(rc);
2995#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2996 MMR3HeapFree(pChunk);
2997#else
2998 MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
2999#endif
3000 pChunk = NULL;
3001 }
3002
3003 *ppChunk = pChunk;
3004 return rc;
3005}
3006
3007
3008/**
3009 * For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3010 *
3011 * @returns see pgmR3PhysChunkMap.
3012 * @param pVM The VM handle.
3013 * @param idChunk The chunk to map.
3014 */
3015VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3016{
3017 PPGMCHUNKR3MAP pChunk;
3018 int rc;
3019
3020 pgmLock(pVM);
3021 rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3022 pgmUnlock(pVM);
3023 return rc;
3024}
3025
3026
3027/**
3028 * Invalidates the TLB for the ring-3 mapping cache.
3029 *
3030 * @param pVM The VM handle.
3031 */
3032VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3033{
3034 pgmLock(pVM);
3035 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3036 {
3037 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3038 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3039 }
3040 pgmUnlock(pVM);
3041}
3042
3043
3044/**
3045 * Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3046 *
3047 * This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3048 * signal and clear the out of memory condition. When contracted, this API is
3049 * used to try clear the condition when the user wants to resume.
3050 *
3051 * @returns The following VBox status codes.
3052 * @retval VINF_SUCCESS on success. FFs cleared.
3053 * @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3054 * this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3055 *
3056 * @param pVM The VM handle.
3057 *
3058 * @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3059 * in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3060 * pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3061 * handler.
3062 */
3063VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3064{
3065 pgmLock(pVM);
3066
3067 /*
3068 * Allocate more pages, noting down the index of the first new page.
3069 */
3070 uint32_t iClear = pVM->pgm.s.cHandyPages;
3071 AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3072 Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3073 int rcAlloc = VINF_SUCCESS;
3074 int rcSeed = VINF_SUCCESS;
3075 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3076 while (rc == VERR_GMM_SEED_ME)
3077 {
3078 void *pvChunk;
3079 rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3080 if (RT_SUCCESS(rc))
3081 {
3082 rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3083 if (RT_FAILURE(rc))
3084 SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3085 }
3086 if (RT_SUCCESS(rc))
3087 rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3088 }
3089
3090 if (RT_SUCCESS(rc))
3091 {
3092 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3093 Assert(pVM->pgm.s.cHandyPages > 0);
3094 VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3095 VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3096
3097 /*
3098 * Clear the pages.
3099 */
3100 while (iClear < pVM->pgm.s.cHandyPages)
3101 {
3102 PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3103 void *pv;
3104 rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3105 AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3106 ASMMemZeroPage(pv);
3107 iClear++;
3108 Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3109 }
3110 }
3111 else
3112 {
3113 /*
3114 * We should never get here unless there is a genuine shortage of
3115 * memory (or some internal error). Flag the error so the VM can be
3116 * suspended ASAP and the user informed. If we're totally out of
3117 * handy pages we will return failure.
3118 */
3119 /* Report the failure. */
3120 LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3121 " cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3122 rc, rcAlloc, rcSeed,
3123 pVM->pgm.s.cHandyPages,
3124 pVM->pgm.s.cAllPages,
3125 pVM->pgm.s.cPrivatePages,
3126 pVM->pgm.s.cSharedPages,
3127 pVM->pgm.s.cZeroPages));
3128 if ( rc != VERR_NO_MEMORY
3129 && rc != VERR_LOCK_FAILED)
3130 {
3131 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3132 {
3133 LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3134 i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3135 pVM->pgm.s.aHandyPages[i].idSharedPage));
3136 uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3137 if (idPage != NIL_GMM_PAGEID)
3138 {
3139 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3140 pRam;
3141 pRam = pRam->pNextR3)
3142 {
3143 uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3144 for (uint32_t iPage = 0; iPage < cPages; iPage++)
3145 if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3146 LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3147 pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3148 }
3149 }
3150 }
3151 }
3152
3153 /* Set the FFs and adjust rc. */
3154 VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3155 VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3156 if ( rc == VERR_NO_MEMORY
3157 || rc == VERR_LOCK_FAILED)
3158 rc = VINF_EM_NO_MEMORY;
3159 }
3160
3161 pgmUnlock(pVM);
3162 return rc;
3163}
3164
3165
3166/**
3167 * Frees the specified RAM page and replaces it with the ZERO page.
3168 *
3169 * This is used by ballooning, remapping MMIO2 and RAM reset.
3170 *
3171 * @param pVM Pointer to the shared VM structure.
3172 * @param pReq Pointer to the request.
3173 * @param pPage Pointer to the page structure.
3174 * @param GCPhys The guest physical address of the page, if applicable.
3175 *
3176 * @remarks The caller must own the PGM lock.
3177 */
3178static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3179{
3180 /*
3181 * Assert sanity.
3182 */
3183 Assert(PGMIsLockOwner(pVM));
3184 if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3185 && PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3186 {
3187 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3188 return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3189 }
3190
3191 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO)
3192 return VINF_SUCCESS;
3193
3194 const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3195 Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3196 if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3197 || idPage > GMM_PAGEID_LAST
3198 || PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3199 {
3200 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3201 return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3202 }
3203
3204 /* update page count stats. */
3205 if (PGM_PAGE_IS_SHARED(pPage))
3206 pVM->pgm.s.cSharedPages--;
3207 else
3208 pVM->pgm.s.cPrivatePages--;
3209 pVM->pgm.s.cZeroPages++;
3210
3211 /*
3212 * pPage = ZERO page.
3213 */
3214 PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3215 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3216 PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3217
3218 /*
3219 * Make sure it's not in the handy page array.
3220 */
3221 for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3222 {
3223 if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3224 {
3225 pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3226 break;
3227 }
3228 if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3229 {
3230 pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3231 break;
3232 }
3233 }
3234
3235 /*
3236 * Push it onto the page array.
3237 */
3238 uint32_t iPage = *pcPendingPages;
3239 Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3240 *pcPendingPages += 1;
3241
3242 pReq->aPages[iPage].idPage = idPage;
3243
3244 if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3245 return VINF_SUCCESS;
3246
3247 /*
3248 * Flush the pages.
3249 */
3250 int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3251 if (RT_SUCCESS(rc))
3252 {
3253 GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3254 *pcPendingPages = 0;
3255 }
3256 return rc;
3257}
3258
3259
3260/**
3261 * Converts a GC physical address to a HC ring-3 pointer, with some
3262 * additional checks.
3263 *
3264 * @returns VBox status code.
3265 * @retval VINF_SUCCESS on success.
3266 * @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3267 * access handler of some kind.
3268 * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3269 * accesses or is odd in any way.
3270 * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3271 *
3272 * @param pVM The VM handle.
3273 * @param GCPhys The GC physical address to convert.
3274 * @param fWritable Whether write access is required.
3275 * @param ppv Where to store the pointer corresponding to GCPhys on
3276 * success.
3277 */
3278VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3279{
3280 pgmLock(pVM);
3281
3282 PPGMRAMRANGE pRam;
3283 PPGMPAGE pPage;
3284 int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3285 if (RT_SUCCESS(rc))
3286 {
3287 if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3288 rc = VINF_SUCCESS;
3289 else
3290 {
3291 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3292 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3293 else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3294 {
3295 /** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3296 * in -norawr0 mode. */
3297 if (fWritable)
3298 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3299 }
3300 else
3301 {
3302 /* Temporarily disabled physical handler(s), since the recompiler
3303 doesn't get notified when it's reset we'll have to pretend it's
3304 operating normally. */
3305 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3306 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3307 else
3308 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3309 }
3310 }
3311 if (RT_SUCCESS(rc))
3312 {
3313 int rc2;
3314
3315 /* Make sure what we return is writable. */
3316 if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3317 switch (PGM_PAGE_GET_STATE(pPage))
3318 {
3319 case PGM_PAGE_STATE_ALLOCATED:
3320 break;
3321 case PGM_PAGE_STATE_ZERO:
3322 case PGM_PAGE_STATE_SHARED:
3323 case PGM_PAGE_STATE_WRITE_MONITORED:
3324 rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3325 AssertLogRelRCReturn(rc2, rc2);
3326 break;
3327 }
3328
3329 /* Get a ring-3 mapping of the address. */
3330 PPGMPAGER3MAPTLBE pTlbe;
3331 rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3332 AssertLogRelRCReturn(rc2, rc2);
3333 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
3334 /** @todo mapping/locking hell; this isn't horribly efficient since
3335 * pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
3336
3337 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] *ppv=%p\n", GCPhys, rc, pPage, *ppv));
3338 }
3339 else
3340 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3341
3342 /* else: handler catching all access, no pointer returned. */
3343 }
3344 else
3345 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3346
3347 pgmUnlock(pVM);
3348 return rc;
3349}
3350
3351
3352
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