PGMPhys.cpp@ 24911

Last change on this file since 24911 was 24767, checked in by vboxsync, 15 years ago
PGM: Deal with write monitored pages without involving EMT. This works around the pcnet/pgm deadlocks (#4464 an #3775).
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1	/* $Id: PGMPhys.cpp 24767 2009-11-18 17:15:02Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_PHYS
27	#include <VBox/pgm.h>
28	#include <VBox/iom.h>
29	#include <VBox/mm.h>
30	#include <VBox/stam.h>
31	#include <VBox/rem.h>
32	#include <VBox/pdmdev.h>
33	#include "PGMInternal.h"
34	#include <VBox/vm.h>
35	#include <VBox/sup.h>
36	#include <VBox/param.h>
37	#include <VBox/err.h>
38	#include <VBox/log.h>
39	#include <iprt/assert.h>
40	#include <iprt/alloc.h>
41	#include <iprt/asm.h>
42	#include <iprt/thread.h>
43	#include <iprt/string.h>
44
45
46	/*******************************************************************************
47	* Defined Constants And Macros *
48	*******************************************************************************/
49	/** The number of pages to free in one batch. */
50	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
51
52
53	/*******************************************************************************
54	* Internal Functions *
55	*******************************************************************************/
56	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
57	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
58
59
60	/*
61	* PGMR3PhysReadU8-64
62	* PGMR3PhysWriteU8-64
63	*/
64	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
65	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
66	#define PGMPHYS_DATASIZE 1
67	#define PGMPHYS_DATATYPE uint8_t
68	#include "PGMPhysRWTmpl.h"
69
70	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
71	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
72	#define PGMPHYS_DATASIZE 2
73	#define PGMPHYS_DATATYPE uint16_t
74	#include "PGMPhysRWTmpl.h"
75
76	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
77	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
78	#define PGMPHYS_DATASIZE 4
79	#define PGMPHYS_DATATYPE uint32_t
80	#include "PGMPhysRWTmpl.h"
81
82	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
83	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
84	#define PGMPHYS_DATASIZE 8
85	#define PGMPHYS_DATATYPE uint64_t
86	#include "PGMPhysRWTmpl.h"
87
88
89	/**
90	* EMT worker for PGMR3PhysReadExternal.
91	*/
92	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
93	{
94	PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
95	return VINF_SUCCESS;
96	}
97
98
99	/**
100	* Write to physical memory, external users.
101	*
102	* @returns VBox status code.
103	* @retval VINF_SUCCESS.
104	*
105	* @param pVM VM Handle.
106	* @param GCPhys Physical address to write to.
107	* @param pvBuf What to write.
108	* @param cbWrite How many bytes to write.
109	*
110	* @thread Any but EMTs.
111	*/
112	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
113	{
114	VM_ASSERT_OTHER_THREAD(pVM);
115
116	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
117	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
118
119	pgmLock(pVM);
120
121	/*
122	* Copy loop on ram ranges.
123	*/
124	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
125	for (;;)
126	{
127	/* Find range. */
128	while (pRam && GCPhys > pRam->GCPhysLast)
129	pRam = pRam->CTX_SUFF(pNext);
130	/* Inside range or not? */
131	if (pRam && GCPhys >= pRam->GCPhys)
132	{
133	/*
134	* Must work our way thru this page by page.
135	*/
136	RTGCPHYS off = GCPhys - pRam->GCPhys;
137	while (off < pRam->cb)
138	{
139	unsigned iPage = off >> PAGE_SHIFT;
140	PPGMPAGE pPage = &pRam->aPages[iPage];
141
142	/*
143	* If the page has an ALL access handler, we'll have to
144	* delegate the job to EMT.
145	*/
146	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
147	{
148	pgmUnlock(pVM);
149
150	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 4,
151	pVM, &GCPhys, pvBuf, cbRead);
152	}
153	Assert(!PGM_PAGE_IS_MMIO(pPage));
154
155	/*
156	* Simple stuff, go ahead.
157	*/
158	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
159	if (cb > cbRead)
160	cb = cbRead;
161	const void *pvSrc;
162	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
163	if (RT_SUCCESS(rc))
164	memcpy(pvBuf, pvSrc, cb);
165	else
166	{
167	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
168	pRam->GCPhys + off, pPage, rc));
169	memset(pvBuf, 0xff, cb);
170	}
171
172	/* next page */
173	if (cb >= cbRead)
174	{
175	pgmUnlock(pVM);
176	return VINF_SUCCESS;
177	}
178	cbRead -= cb;
179	off += cb;
180	GCPhys += cb;
181	pvBuf = (char *)pvBuf + cb;
182	} /* walk pages in ram range. */
183	}
184	else
185	{
186	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
187
188	/*
189	* Unassigned address space.
190	*/
191	if (!pRam)
192	break;
193	size_t cb = pRam->GCPhys - GCPhys;
194	if (cb >= cbRead)
195	{
196	memset(pvBuf, 0xff, cbRead);
197	break;
198	}
199	memset(pvBuf, 0xff, cb);
200
201	cbRead -= cb;
202	pvBuf = (char *)pvBuf + cb;
203	GCPhys += cb;
204	}
205	} /* Ram range walk */
206
207	pgmUnlock(pVM);
208
209	return VINF_SUCCESS;
210	}
211
212
213	/**
214	* EMT worker for PGMR3PhysWriteExternal.
215	*/
216	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
217	{
218	/** @todo VERR_EM_NO_MEMORY */
219	PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
220	return VINF_SUCCESS;
221	}
222
223
224	/**
225	* Write to physical memory, external users.
226	*
227	* @returns VBox status code.
228	* @retval VINF_SUCCESS.
229	* @retval VERR_EM_NO_MEMORY.
230	*
231	* @param pVM VM Handle.
232	* @param GCPhys Physical address to write to.
233	* @param pvBuf What to write.
234	* @param cbWrite How many bytes to write.
235	* @param pszWho Who is writing. For tracking down who is writing
236	* after we've saved the state.
237	*
238	* @thread Any but EMTs.
239	*/
240	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void pvBuf, size_t cbWrite, const char pszWho)
241	{
242	VM_ASSERT_OTHER_THREAD(pVM);
243
244	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
245	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x pszWho=%s\n",
246	GCPhys, cbWrite, pszWho));
247	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
248	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
249
250	pgmLock(pVM);
251
252	/*
253	* Copy loop on ram ranges, stop when we hit something difficult.
254	*/
255	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
256	for (;;)
257	{
258	/* Find range. */
259	while (pRam && GCPhys > pRam->GCPhysLast)
260	pRam = pRam->CTX_SUFF(pNext);
261	/* Inside range or not? */
262	if (pRam && GCPhys >= pRam->GCPhys)
263	{
264	/*
265	* Must work our way thru this page by page.
266	*/
267	RTGCPTR off = GCPhys - pRam->GCPhys;
268	while (off < pRam->cb)
269	{
270	RTGCPTR iPage = off >> PAGE_SHIFT;
271	PPGMPAGE pPage = &pRam->aPages[iPage];
272
273	/*
274	* Is the page problematic, we have to do the work on the EMT.
275	*
276	* Allocating writable pages and access handlers are
277	* problematic, write monitored pages are simple and can be
278	* dealth with here.
279	*/
280	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
281	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
282	{
283	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
284	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
285	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
286	else
287	{
288	pgmUnlock(pVM);
289
290	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 4,
291	pVM, &GCPhys, pvBuf, cbWrite);
292	}
293	}
294	Assert(!PGM_PAGE_IS_MMIO(pPage));
295
296	/*
297	* Simple stuff, go ahead.
298	*/
299	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
300	if (cb > cbWrite)
301	cb = cbWrite;
302	void *pvDst;
303	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
304	if (RT_SUCCESS(rc))
305	memcpy(pvDst, pvBuf, cb);
306	else
307	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
308	pRam->GCPhys + off, pPage, rc));
309
310	/* next page */
311	if (cb >= cbWrite)
312	{
313	pgmUnlock(pVM);
314	return VINF_SUCCESS;
315	}
316
317	cbWrite -= cb;
318	off += cb;
319	GCPhys += cb;
320	pvBuf = (const char *)pvBuf + cb;
321	} /* walk pages in ram range */
322	}
323	else
324	{
325	/*
326	* Unassigned address space, skip it.
327	*/
328	if (!pRam)
329	break;
330	size_t cb = pRam->GCPhys - GCPhys;
331	if (cb >= cbWrite)
332	break;
333	cbWrite -= cb;
334	pvBuf = (const char *)pvBuf + cb;
335	GCPhys += cb;
336	}
337	} /* Ram range walk */
338
339	pgmUnlock(pVM);
340	return VINF_SUCCESS;
341	}
342
343
344	/**
345	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
346	*
347	* @returns see PGMR3PhysGCPhys2CCPtrExternal
348	* @param pVM The VM handle.
349	* @param pGCPhys Pointer to the guest physical address.
350	* @param ppv Where to store the mapping address.
351	* @param pLock Where to store the lock.
352	*/
353	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
354	{
355	/*
356	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
357	* an access handler after it succeeds.
358	*/
359	int rc = pgmLock(pVM);
360	AssertRCReturn(rc, rc);
361
362	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
363	if (RT_SUCCESS(rc))
364	{
365	PPGMPAGEMAPTLBE pTlbe;
366	int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
367	AssertFatalRC(rc2);
368	PPGMPAGE pPage = pTlbe->pPage;
369	if (PGM_PAGE_IS_MMIO(pPage))
370	{
371	PGMPhysReleasePageMappingLock(pVM, pLock);
372	rc = VERR_PGM_PHYS_PAGE_RESERVED;
373	}
374	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
375	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
376	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
377	#endif
378	)
379	{
380	/* We must flush any corresponding pgm pool page here, otherwise we'll
381	* not be informed about writes and keep bogus gst->shw mappings around.
382	*/
383	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
384	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
385	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
386	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
387	}
388	}
389
390	pgmUnlock(pVM);
391	return rc;
392	}
393
394
395	/**
396	* Requests the mapping of a guest page into ring-3, external threads.
397	*
398	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
399	* release it.
400	*
401	* This API will assume your intention is to write to the page, and will
402	* therefore replace shared and zero pages. If you do not intend to modify the
403	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
404	*
405	* @returns VBox status code.
406	* @retval VINF_SUCCESS on success.
407	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
408	* backing or if the page has any active access handlers. The caller
409	* must fall back on using PGMR3PhysWriteExternal.
410	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
411	*
412	* @param pVM The VM handle.
413	* @param GCPhys The guest physical address of the page that should be mapped.
414	* @param ppv Where to store the address corresponding to GCPhys.
415	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
416	*
417	* @remark Avoid calling this API from within critical sections (other than the
418	* PGM one) because of the deadlock risk when we have to delegating the
419	* task to an EMT.
420	* @thread Any.
421	*/
422	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
423	{
424	AssertPtr(ppv);
425	AssertPtr(pLock);
426
427	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
428
429	int rc = pgmLock(pVM);
430	AssertRCReturn(rc, rc);
431
432	/*
433	* Query the Physical TLB entry for the page (may fail).
434	*/
435	PPGMPAGEMAPTLBE pTlbe;
436	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
437	if (RT_SUCCESS(rc))
438	{
439	PPGMPAGE pPage = pTlbe->pPage;
440	if (PGM_PAGE_IS_MMIO(pPage))
441	rc = VERR_PGM_PHYS_PAGE_RESERVED;
442	else
443	{
444	/*
445	* If the page is shared, the zero page, or being write monitored
446	* it must be converted to an page that's writable if possible.
447	* We can only deal with write monitored pages here, the rest have
448	* to be on an EMT.
449	*/
450	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
451	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
452	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
453	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
454	#endif
455	)
456	{
457	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
458	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
459	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
460	&& !pgmPoolIsDirtyPage(pVM, GCPhys)
461	#endif
462	)
463	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
464	else
465	{
466	pgmUnlock(pVM);
467
468	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
469	pVM, &GCPhys, ppv, pLock);
470	}
471	}
472
473	/*
474	* Now, just perform the locking and calculate the return address.
475	*/
476	PPGMPAGEMAP pMap = pTlbe->pMap;
477	if (pMap)
478	pMap->cRefs++;
479
480	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
481	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
482	{
483	if (cLocks == 0)
484	pVM->pgm.s.cWriteLockedPages++;
485	PGM_PAGE_INC_WRITE_LOCKS(pPage);
486	}
487	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
488	{
489	PGM_PAGE_INC_WRITE_LOCKS(pPage);
490	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
491	if (pMap)
492	pMap->cRefs++; /* Extra ref to prevent it from going away. */
493	}
494
495	ppv = (void )((uintptr_t)pTlbe->pv \| (GCPhys & PAGE_OFFSET_MASK));
496	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
497	pLock->pvMap = pMap;
498	}
499	}
500
501	pgmUnlock(pVM);
502	return rc;
503	}
504
505
506	/**
507	* Requests the mapping of a guest page into ring-3, external threads.
508	*
509	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
510	* release it.
511	*
512	* @returns VBox status code.
513	* @retval VINF_SUCCESS on success.
514	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
515	* backing or if the page as an active ALL access handler. The caller
516	* must fall back on using PGMPhysRead.
517	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
518	*
519	* @param pVM The VM handle.
520	* @param GCPhys The guest physical address of the page that should be mapped.
521	* @param ppv Where to store the address corresponding to GCPhys.
522	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
523	*
524	* @remark Avoid calling this API from within critical sections (other than
525	* the PGM one) because of the deadlock risk.
526	* @thread Any.
527	*/
528	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
529	{
530	int rc = pgmLock(pVM);
531	AssertRCReturn(rc, rc);
532
533	/*
534	* Query the Physical TLB entry for the page (may fail).
535	*/
536	PPGMPAGEMAPTLBE pTlbe;
537	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
538	if (RT_SUCCESS(rc))
539	{
540	PPGMPAGE pPage = pTlbe->pPage;
541	#if 1
542	/* MMIO pages doesn't have any readable backing. */
543	if (PGM_PAGE_IS_MMIO(pPage))
544	rc = VERR_PGM_PHYS_PAGE_RESERVED;
545	#else
546	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
547	rc = VERR_PGM_PHYS_PAGE_RESERVED;
548	#endif
549	else
550	{
551	/*
552	* Now, just perform the locking and calculate the return address.
553	*/
554	PPGMPAGEMAP pMap = pTlbe->pMap;
555	if (pMap)
556	pMap->cRefs++;
557
558	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
559	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
560	{
561	if (cLocks == 0)
562	pVM->pgm.s.cReadLockedPages++;
563	PGM_PAGE_INC_READ_LOCKS(pPage);
564	}
565	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
566	{
567	PGM_PAGE_INC_READ_LOCKS(pPage);
568	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
569	if (pMap)
570	pMap->cRefs++; /* Extra ref to prevent it from going away. */
571	}
572
573	ppv = (void )((uintptr_t)pTlbe->pv \| (GCPhys & PAGE_OFFSET_MASK));
574	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
575	pLock->pvMap = pMap;
576	}
577	}
578
579	pgmUnlock(pVM);
580	return rc;
581	}
582
583
584	/**
585	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
586	*
587	* Called when anything was relocated.
588	*
589	* @param pVM Pointer to the shared VM structure.
590	*/
591	void pgmR3PhysRelinkRamRanges(PVM pVM)
592	{
593	PPGMRAMRANGE pCur;
594
595	#ifdef VBOX_STRICT
596	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
597	{
598	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
599	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
600	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
601	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
602	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
603	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
604	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
605	Assert( pCur2 == pCur
606	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
607	}
608	#endif
609
610	pCur = pVM->pgm.s.pRamRangesR3;
611	if (pCur)
612	{
613	pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
614	pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
615
616	for (; pCur->pNextR3; pCur = pCur->pNextR3)
617	{
618	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
619	pCur->pNextRC = pCur->pNextR3->pSelfRC;
620	}
621
622	Assert(pCur->pNextR0 == NIL_RTR0PTR);
623	Assert(pCur->pNextRC == NIL_RTRCPTR);
624	}
625	else
626	{
627	Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
628	Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
629	}
630	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
631	}
632
633
634	/**
635	* Links a new RAM range into the list.
636	*
637	* @param pVM Pointer to the shared VM structure.
638	* @param pNew Pointer to the new list entry.
639	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
640	*/
641	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
642	{
643	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
644	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
645	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
646
647	pgmLock(pVM);
648
649	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
650	pNew->pNextR3 = pRam;
651	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
652	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
653
654	if (pPrev)
655	{
656	pPrev->pNextR3 = pNew;
657	pPrev->pNextR0 = pNew->pSelfR0;
658	pPrev->pNextRC = pNew->pSelfRC;
659	}
660	else
661	{
662	pVM->pgm.s.pRamRangesR3 = pNew;
663	pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
664	pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
665	}
666	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
667	pgmUnlock(pVM);
668	}
669
670
671	/**
672	* Unlink an existing RAM range from the list.
673	*
674	* @param pVM Pointer to the shared VM structure.
675	* @param pRam Pointer to the new list entry.
676	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
677	*/
678	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
679	{
680	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
681	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
682	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
683
684	pgmLock(pVM);
685
686	PPGMRAMRANGE pNext = pRam->pNextR3;
687	if (pPrev)
688	{
689	pPrev->pNextR3 = pNext;
690	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
691	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
692	}
693	else
694	{
695	Assert(pVM->pgm.s.pRamRangesR3 == pRam);
696	pVM->pgm.s.pRamRangesR3 = pNext;
697	pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
698	pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
699	}
700	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
701	pgmUnlock(pVM);
702	}
703
704
705	/**
706	* Unlink an existing RAM range from the list.
707	*
708	* @param pVM Pointer to the shared VM structure.
709	* @param pRam Pointer to the new list entry.
710	*/
711	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
712	{
713	pgmLock(pVM);
714
715	/* find prev. */
716	PPGMRAMRANGE pPrev = NULL;
717	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
718	while (pCur != pRam)
719	{
720	pPrev = pCur;
721	pCur = pCur->pNextR3;
722	}
723	AssertFatal(pCur);
724
725	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
726	pgmUnlock(pVM);
727	}
728
729
730	/**
731	* Frees a range of pages, replacing them with ZERO pages of the specified type.
732	*
733	* @returns VBox status code.
734	* @param pVM The VM handle.
735	* @param pRam The RAM range in which the pages resides.
736	* @param GCPhys The address of the first page.
737	* @param GCPhysLast The address of the last page.
738	* @param uType The page type to replace then with.
739	*/
740	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
741	{
742	uint32_t cPendingPages = 0;
743	PGMMFREEPAGESREQ pReq;
744	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
745	AssertLogRelRCReturn(rc, rc);
746
747	/* Itegerate the pages. */
748	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
749	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
750	while (cPagesLeft-- > 0)
751	{
752	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
753	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
754
755	PGM_PAGE_SET_TYPE(pPageDst, uType);
756
757	GCPhys += PAGE_SIZE;
758	pPageDst++;
759	}
760
761	if (cPendingPages)
762	{
763	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
764	AssertLogRelRCReturn(rc, rc);
765	}
766	GMMR3FreePagesCleanup(pReq);
767
768	return rc;
769	}
770
771
772	/**
773	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
774	*
775	* @param pVM The VM handle.
776	* @param pNew The new RAM range.
777	* @param GCPhys The address of the RAM range.
778	* @param GCPhysLast The last address of the RAM range.
779	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
780	* if in HMA.
781	* @param R0PtrNew Ditto for R0.
782	* @param pszDesc The description.
783	* @param pPrev The previous RAM range (for linking).
784	*/
785	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
786	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
787	{
788	/*
789	* Initialize the range.
790	*/
791	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
792	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
793	pNew->GCPhys = GCPhys;
794	pNew->GCPhysLast = GCPhysLast;
795	pNew->cb = GCPhysLast - GCPhys + 1;
796	pNew->pszDesc = pszDesc;
797	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
798	pNew->pvR3 = NULL;
799	pNew->paLSPages = NULL;
800
801	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
802	RTGCPHYS iPage = cPages;
803	while (iPage-- > 0)
804	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
805
806	/* Update the page count stats. */
807	pVM->pgm.s.cZeroPages += cPages;
808	pVM->pgm.s.cAllPages += cPages;
809
810	/*
811	* Link it.
812	*/
813	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
814	}
815
816
817	/**
818	* Relocate a floating RAM range.
819	*
820	* @copydoc FNPGMRELOCATE.
821	*/
822	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
823	{
824	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
825	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
826	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
827
828	switch (enmMode)
829	{
830	case PGMRELOCATECALL_SUGGEST:
831	return true;
832	case PGMRELOCATECALL_RELOCATE:
833	{
834	/* Update myself and then relink all the ranges. */
835	pgmLock(pVM);
836	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
837	pgmR3PhysRelinkRamRanges(pVM);
838	pgmUnlock(pVM);
839	return true;
840	}
841
842	default:
843	AssertFailedReturn(false);
844	}
845	}
846
847
848	/**
849	* PGMR3PhysRegisterRam worker that registers a high chunk.
850	*
851	* @returns VBox status code.
852	* @param pVM The VM handle.
853	* @param GCPhys The address of the RAM.
854	* @param cRamPages The number of RAM pages to register.
855	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
856	* @param iChunk The chunk number.
857	* @param pszDesc The RAM range description.
858	* @param ppPrev Previous RAM range pointer. In/Out.
859	*/
860	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
861	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
862	PPGMRAMRANGE *ppPrev)
863	{
864	const char *pszDescChunk = iChunk == 0
865	? pszDesc
866	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
867	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
868
869	/*
870	* Allocate memory for the new chunk.
871	*/
872	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
873	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
874	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
875	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
876	void *pvChunk = NULL;
877	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
878	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
879	VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
880	#else
881	NULL,
882	#endif
883	paChunkPages);
884	if (RT_SUCCESS(rc))
885	{
886	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
887	if (!VMMIsHwVirtExtForced(pVM))
888	R0PtrChunk = NIL_RTR0PTR;
889	#else
890	R0PtrChunk = (uintptr_t)pvChunk;
891	#endif
892	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
893
894	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
895
896	/*
897	* Create a mapping and map the pages into it.
898	* We push these in below the HMA.
899	*/
900	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
901	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
902	if (RT_SUCCESS(rc))
903	{
904	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
905
906	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
907	RTGCPTR GCPtrPage = GCPtrChunk;
908	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
909	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
910	if (RT_SUCCESS(rc))
911	{
912	/*
913	* Ok, init and link the range.
914	*/
915	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
916	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
917	*ppPrev = pNew;
918	}
919	}
920
921	if (RT_FAILURE(rc))
922	SUPR3PageFreeEx(pvChunk, cChunkPages);
923	}
924
925	RTMemTmpFree(paChunkPages);
926	return rc;
927	}
928
929
930	/**
931	* Sets up a range RAM.
932	*
933	* This will check for conflicting registrations, make a resource
934	* reservation for the memory (with GMM), and setup the per-page
935	* tracking structures (PGMPAGE).
936	*
937	* @returns VBox stutus code.
938	* @param pVM Pointer to the shared VM structure.
939	* @param GCPhys The physical address of the RAM.
940	* @param cb The size of the RAM.
941	* @param pszDesc The description - not copied, so, don't free or change it.
942	*/
943	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
944	{
945	/*
946	* Validate input.
947	*/
948	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
949	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
950	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
951	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
952	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
953	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
954	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
955	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
956
957	pgmLock(pVM);
958
959	/*
960	* Find range location and check for conflicts.
961	* (We don't lock here because the locking by EMT is only required on update.)
962	*/
963	PPGMRAMRANGE pPrev = NULL;
964	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
965	while (pRam && GCPhysLast >= pRam->GCPhys)
966	{
967	if ( GCPhysLast >= pRam->GCPhys
968	&& GCPhys <= pRam->GCPhysLast)
969	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
970	GCPhys, GCPhysLast, pszDesc,
971	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
972	VERR_PGM_RAM_CONFLICT);
973
974	/* next */
975	pPrev = pRam;
976	pRam = pRam->pNextR3;
977	}
978
979	/*
980	* Register it with GMM (the API bitches).
981	*/
982	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
983	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
984	if (RT_FAILURE(rc))
985	{
986	pgmUnlock(pVM);
987	return rc;
988	}
989
990	if ( GCPhys >= _4G
991	&& cPages > 256)
992	{
993	/*
994	* The PGMRAMRANGE structures for the high memory can get very big.
995	* In order to avoid SUPR3PageAllocEx allocation failures due to the
996	* allocation size limit there and also to avoid being unable to find
997	* guest mapping space for them, we split this memory up into 4MB in
998	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
999	* mode.
1000	*
1001	* The first and last page of each mapping are guard pages and marked
1002	* not-present. So, we've got 4186112 and 16769024 bytes available for
1003	* the PGMRAMRANGE structure.
1004	*
1005	* Note! The sizes used here will influence the saved state.
1006	*/
1007	uint32_t cbChunk;
1008	uint32_t cPagesPerChunk;
1009	if (VMMIsHwVirtExtForced(pVM))
1010	{
1011	cbChunk = 16U*_1M;
1012	cPagesPerChunk = 1048048; /* max ~1048059 */
1013	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1014	}
1015	else
1016	{
1017	cbChunk = 4U*_1M;
1018	cPagesPerChunk = 261616; /* max ~261627 */
1019	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1020	}
1021	AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1022
1023	RTGCPHYS cPagesLeft = cPages;
1024	RTGCPHYS GCPhysChunk = GCPhys;
1025	uint32_t iChunk = 0;
1026	while (cPagesLeft > 0)
1027	{
1028	uint32_t cPagesInChunk = cPagesLeft;
1029	if (cPagesInChunk > cPagesPerChunk)
1030	cPagesInChunk = cPagesPerChunk;
1031
1032	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1033	AssertRCReturn(rc, rc);
1034
1035	/* advance */
1036	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1037	cPagesLeft -= cPagesInChunk;
1038	iChunk++;
1039	}
1040	}
1041	else
1042	{
1043	/*
1044	* Allocate, initialize and link the new RAM range.
1045	*/
1046	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1047	PPGMRAMRANGE pNew;
1048	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1049	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1050
1051	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1052	}
1053	PGMPhysInvalidatePageMapTLB(pVM);
1054	pgmUnlock(pVM);
1055
1056	/*
1057	* Notify REM.
1058	*/
1059	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1060
1061	return VINF_SUCCESS;
1062	}
1063
1064
1065	/**
1066	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1067	*
1068	* We do this late in the init process so that all the ROM and MMIO ranges have
1069	* been registered already and we don't go wasting memory on them.
1070	*
1071	* @returns VBox status code.
1072	*
1073	* @param pVM Pointer to the shared VM structure.
1074	*/
1075	int pgmR3PhysRamPreAllocate(PVM pVM)
1076	{
1077	Assert(pVM->pgm.s.fRamPreAlloc);
1078	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1079
1080	/*
1081	* Walk the RAM ranges and allocate all RAM pages, halt at
1082	* the first allocation error.
1083	*/
1084	uint64_t cPages = 0;
1085	uint64_t NanoTS = RTTimeNanoTS();
1086	pgmLock(pVM);
1087	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1088	{
1089	PPGMPAGE pPage = &pRam->aPages[0];
1090	RTGCPHYS GCPhys = pRam->GCPhys;
1091	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1092	while (cLeft-- > 0)
1093	{
1094	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1095	{
1096	switch (PGM_PAGE_GET_STATE(pPage))
1097	{
1098	case PGM_PAGE_STATE_ZERO:
1099	{
1100	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1101	if (RT_FAILURE(rc))
1102	{
1103	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1104	pgmUnlock(pVM);
1105	return rc;
1106	}
1107	cPages++;
1108	break;
1109	}
1110
1111	case PGM_PAGE_STATE_ALLOCATED:
1112	case PGM_PAGE_STATE_WRITE_MONITORED:
1113	case PGM_PAGE_STATE_SHARED:
1114	/* nothing to do here. */
1115	break;
1116	}
1117	}
1118
1119	/* next */
1120	pPage++;
1121	GCPhys += PAGE_SIZE;
1122	}
1123	}
1124	pgmUnlock(pVM);
1125	NanoTS = RTTimeNanoTS() - NanoTS;
1126
1127	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1128	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1129	return VINF_SUCCESS;
1130	}
1131
1132
1133	/**
1134	* Resets (zeros) the RAM.
1135	*
1136	* ASSUMES that the caller owns the PGM lock.
1137	*
1138	* @returns VBox status code.
1139	* @param pVM Pointer to the shared VM structure.
1140	*/
1141	int pgmR3PhysRamReset(PVM pVM)
1142	{
1143	Assert(PGMIsLockOwner(pVM));
1144	/*
1145	* We batch up pages before freeing them.
1146	*/
1147	uint32_t cPendingPages = 0;
1148	PGMMFREEPAGESREQ pReq;
1149	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1150	AssertLogRelRCReturn(rc, rc);
1151
1152	/*
1153	* Walk the ram ranges.
1154	*/
1155	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1156	{
1157	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1158	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1159
1160	if (!pVM->pgm.s.fRamPreAlloc)
1161	{
1162	/* Replace all RAM pages by ZERO pages. */
1163	while (iPage-- > 0)
1164	{
1165	PPGMPAGE pPage = &pRam->aPages[iPage];
1166	switch (PGM_PAGE_GET_TYPE(pPage))
1167	{
1168	case PGMPAGETYPE_RAM:
1169	if (!PGM_PAGE_IS_ZERO(pPage))
1170	{
1171	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1172	AssertLogRelRCReturn(rc, rc);
1173	}
1174	break;
1175
1176	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1177	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1178	break;
1179
1180	case PGMPAGETYPE_MMIO2:
1181	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1182	case PGMPAGETYPE_ROM:
1183	case PGMPAGETYPE_MMIO:
1184	break;
1185	default:
1186	AssertFailed();
1187	}
1188	} /* for each page */
1189	}
1190	else
1191	{
1192	/* Zero the memory. */
1193	while (iPage-- > 0)
1194	{
1195	PPGMPAGE pPage = &pRam->aPages[iPage];
1196	switch (PGM_PAGE_GET_TYPE(pPage))
1197	{
1198	case PGMPAGETYPE_RAM:
1199	switch (PGM_PAGE_GET_STATE(pPage))
1200	{
1201	case PGM_PAGE_STATE_ZERO:
1202	break;
1203	case PGM_PAGE_STATE_SHARED:
1204	case PGM_PAGE_STATE_WRITE_MONITORED:
1205	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1206	AssertLogRelRCReturn(rc, rc);
1207	case PGM_PAGE_STATE_ALLOCATED:
1208	{
1209	void *pvPage;
1210	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1211	AssertLogRelRCReturn(rc, rc);
1212	ASMMemZeroPage(pvPage);
1213	break;
1214	}
1215	}
1216	break;
1217
1218	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1219	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1220	break;
1221
1222	case PGMPAGETYPE_MMIO2:
1223	case PGMPAGETYPE_ROM_SHADOW:
1224	case PGMPAGETYPE_ROM:
1225	case PGMPAGETYPE_MMIO:
1226	break;
1227	default:
1228	AssertFailed();
1229
1230	}
1231	} /* for each page */
1232	}
1233
1234	}
1235
1236	/*
1237	* Finish off any pages pending freeing.
1238	*/
1239	if (cPendingPages)
1240	{
1241	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1242	AssertLogRelRCReturn(rc, rc);
1243	}
1244	GMMR3FreePagesCleanup(pReq);
1245
1246	return VINF_SUCCESS;
1247	}
1248
1249
1250	/**
1251	* This is the interface IOM is using to register an MMIO region.
1252	*
1253	* It will check for conflicts and ensure that a RAM range structure
1254	* is present before calling the PGMR3HandlerPhysicalRegister API to
1255	* register the callbacks.
1256	*
1257	* @returns VBox status code.
1258	*
1259	* @param pVM Pointer to the shared VM structure.
1260	* @param GCPhys The start of the MMIO region.
1261	* @param cb The size of the MMIO region.
1262	* @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1263	* @param pvUserR3 The user argument for R3.
1264	* @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1265	* @param pvUserR0 The user argument for R0.
1266	* @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1267	* @param pvUserRC The user argument for RC.
1268	* @param pszDesc The description of the MMIO region.
1269	*/
1270	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1271	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1272	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1273	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1274	R3PTRTYPE(const char *) pszDesc)
1275	{
1276	/*
1277	* Assert on some assumption.
1278	*/
1279	VM_ASSERT_EMT(pVM);
1280	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1281	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1282	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1283	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1284
1285	/*
1286	* Make sure there's a RAM range structure for the region.
1287	*/
1288	int rc;
1289	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1290	bool fRamExists = false;
1291	PPGMRAMRANGE pRamPrev = NULL;
1292	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1293	while (pRam && GCPhysLast >= pRam->GCPhys)
1294	{
1295	if ( GCPhysLast >= pRam->GCPhys
1296	&& GCPhys <= pRam->GCPhysLast)
1297	{
1298	/* Simplification: all within the same range. */
1299	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1300	&& GCPhysLast <= pRam->GCPhysLast,
1301	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1302	GCPhys, GCPhysLast, pszDesc,
1303	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1304	VERR_PGM_RAM_CONFLICT);
1305
1306	/* Check that it's all RAM or MMIO pages. */
1307	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1308	uint32_t cLeft = cb >> PAGE_SHIFT;
1309	while (cLeft-- > 0)
1310	{
1311	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1312	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1313	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1314	GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1315	VERR_PGM_RAM_CONFLICT);
1316	pPage++;
1317	}
1318
1319	/* Looks good. */
1320	fRamExists = true;
1321	break;
1322	}
1323
1324	/* next */
1325	pRamPrev = pRam;
1326	pRam = pRam->pNextR3;
1327	}
1328	PPGMRAMRANGE pNew;
1329	if (fRamExists)
1330	{
1331	pNew = NULL;
1332
1333	/*
1334	* Make all the pages in the range MMIO/ZERO pages, freeing any
1335	* RAM pages currently mapped here. This might not be 100% correct
1336	* for PCI memory, but we're doing the same thing for MMIO2 pages.
1337	*/
1338	rc = pgmLock(pVM);
1339	if (RT_SUCCESS(rc))
1340	{
1341	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1342	pgmUnlock(pVM);
1343	}
1344	AssertRCReturn(rc, rc);
1345	}
1346	else
1347	{
1348	pgmLock(pVM);
1349
1350	/*
1351	* No RAM range, insert an ad hoc one.
1352	*
1353	* Note that we don't have to tell REM about this range because
1354	* PGMHandlerPhysicalRegisterEx will do that for us.
1355	*/
1356	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1357
1358	const uint32_t cPages = cb >> PAGE_SHIFT;
1359	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1360	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1361	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1362
1363	/* Initialize the range. */
1364	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1365	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1366	pNew->GCPhys = GCPhys;
1367	pNew->GCPhysLast = GCPhysLast;
1368	pNew->cb = cb;
1369	pNew->pszDesc = pszDesc;
1370	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
1371	pNew->pvR3 = NULL;
1372	pNew->paLSPages = NULL;
1373
1374	uint32_t iPage = cPages;
1375	while (iPage-- > 0)
1376	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1377	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1378
1379	/* update the page count stats. */
1380	pVM->pgm.s.cZeroPages += cPages;
1381	pVM->pgm.s.cAllPages += cPages;
1382
1383	/* link it */
1384	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1385
1386	pgmUnlock(pVM);
1387	}
1388
1389	/*
1390	* Register the access handler.
1391	*/
1392	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1393	pfnHandlerR3, pvUserR3,
1394	pfnHandlerR0, pvUserR0,
1395	pfnHandlerRC, pvUserRC, pszDesc);
1396	if ( RT_FAILURE(rc)
1397	&& !fRamExists)
1398	{
1399	pVM->pgm.s.cZeroPages -= cb >> PAGE_SHIFT;
1400	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1401
1402	/* remove the ad hoc range. */
1403	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1404	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1405	MMHyperFree(pVM, pRam);
1406	}
1407	PGMPhysInvalidatePageMapTLB(pVM);
1408
1409	return rc;
1410	}
1411
1412
1413	/**
1414	* This is the interface IOM is using to register an MMIO region.
1415	*
1416	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
1417	* any ad hoc PGMRAMRANGE left behind.
1418	*
1419	* @returns VBox status code.
1420	* @param pVM Pointer to the shared VM structure.
1421	* @param GCPhys The start of the MMIO region.
1422	* @param cb The size of the MMIO region.
1423	*/
1424	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1425	{
1426	VM_ASSERT_EMT(pVM);
1427
1428	/*
1429	* First deregister the handler, then check if we should remove the ram range.
1430	*/
1431	int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1432	if (RT_SUCCESS(rc))
1433	{
1434	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1435	PPGMRAMRANGE pRamPrev = NULL;
1436	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1437	while (pRam && GCPhysLast >= pRam->GCPhys)
1438	{
1439	/** @todo We're being a bit too careful here. rewrite. */
1440	if ( GCPhysLast == pRam->GCPhysLast
1441	&& GCPhys == pRam->GCPhys)
1442	{
1443	Assert(pRam->cb == cb);
1444
1445	/*
1446	* See if all the pages are dead MMIO pages.
1447	*/
1448	uint32_t const cPages = cb >> PAGE_SHIFT;
1449	bool fAllMMIO = true;
1450	uint32_t iPage = 0;
1451	uint32_t cLeft = cPages;
1452	while (cLeft-- > 0)
1453	{
1454	PPGMPAGE pPage = &pRam->aPages[iPage];
1455	if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1456	/\|\| not-out-of-action later /)
1457	{
1458	fAllMMIO = false;
1459	Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1460	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1461	break;
1462	}
1463	Assert(PGM_PAGE_IS_ZERO(pPage));
1464	pPage++;
1465	}
1466	if (fAllMMIO)
1467	{
1468	/*
1469	* Ad-hoc range, unlink and free it.
1470	*/
1471	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
1472	GCPhys, GCPhysLast, pRam->pszDesc));
1473
1474	pVM->pgm.s.cAllPages -= cPages;
1475	pVM->pgm.s.cZeroPages -= cPages;
1476
1477	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1478	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1479	MMHyperFree(pVM, pRam);
1480	break;
1481	}
1482	}
1483
1484	/*
1485	* Range match? It will all be within one range (see PGMAllHandler.cpp).
1486	*/
1487	if ( GCPhysLast >= pRam->GCPhys
1488	&& GCPhys <= pRam->GCPhysLast)
1489	{
1490	Assert(GCPhys >= pRam->GCPhys);
1491	Assert(GCPhysLast <= pRam->GCPhysLast);
1492
1493	/*
1494	* Turn the pages back into RAM pages.
1495	*/
1496	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1497	uint32_t cLeft = cb >> PAGE_SHIFT;
1498	while (cLeft--)
1499	{
1500	PPGMPAGE pPage = &pRam->aPages[iPage];
1501	AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1502	AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1503	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1504	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1505	}
1506	break;
1507	}
1508
1509	/* next */
1510	pRamPrev = pRam;
1511	pRam = pRam->pNextR3;
1512	}
1513	}
1514
1515	PGMPhysInvalidatePageMapTLB(pVM);
1516	return rc;
1517	}
1518
1519
1520	/**
1521	* Locate a MMIO2 range.
1522	*
1523	* @returns Pointer to the MMIO2 range.
1524	* @param pVM Pointer to the shared VM structure.
1525	* @param pDevIns The device instance owning the region.
1526	* @param iRegion The region.
1527	*/
1528	DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1529	{
1530	/*
1531	* Search the list.
1532	*/
1533	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1534	if ( pCur->pDevInsR3 == pDevIns
1535	&& pCur->iRegion == iRegion)
1536	return pCur;
1537	return NULL;
1538	}
1539
1540
1541	/**
1542	* Allocate and register an MMIO2 region.
1543	*
1544	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1545	* RAM associated with a device. It is also non-shared memory with a
1546	* permanent ring-3 mapping and page backing (presently).
1547	*
1548	* A MMIO2 range may overlap with base memory if a lot of RAM
1549	* is configured for the VM, in which case we'll drop the base
1550	* memory pages. Presently we will make no attempt to preserve
1551	* anything that happens to be present in the base memory that
1552	* is replaced, this is of course incorrectly but it's too much
1553	* effort.
1554	*
1555	* @returns VBox status code.
1556	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1557	* @retval VERR_ALREADY_EXISTS if the region already exists.
1558	*
1559	* @param pVM Pointer to the shared VM structure.
1560	* @param pDevIns The device instance owning the region.
1561	* @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1562	* this number has to be the number of that region. Otherwise
1563	* it can be any number safe UINT8_MAX.
1564	* @param cb The size of the region. Must be page aligned.
1565	* @param fFlags Reserved for future use, must be zero.
1566	* @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1567	* @param pszDesc The description.
1568	*/
1569	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc)
1570	{
1571	/*
1572	* Validate input.
1573	*/
1574	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1575	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1576	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1577	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1578	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1579	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1580	AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1581	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1582	AssertReturn(cb, VERR_INVALID_PARAMETER);
1583	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1584
1585	const uint32_t cPages = cb >> PAGE_SHIFT;
1586	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1587	AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1588
1589	/*
1590	* For the 2nd+ instance, mangle the description string so it's unique.
1591	*/
1592	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
1593	{
1594	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1595	if (!pszDesc)
1596	return VERR_NO_MEMORY;
1597	}
1598
1599	/*
1600	* Try reserve and allocate the backing memory first as this is what is
1601	* most likely to fail.
1602	*/
1603	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1604	if (RT_SUCCESS(rc))
1605	{
1606	void *pvPages;
1607	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1608	if (RT_SUCCESS(rc))
1609	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
1610	if (RT_SUCCESS(rc))
1611	{
1612	memset(pvPages, 0, cPages * PAGE_SIZE);
1613
1614	/*
1615	* Create the MMIO2 range record for it.
1616	*/
1617	const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1618	PPGMMMIO2RANGE pNew;
1619	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1620	AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1621	if (RT_SUCCESS(rc))
1622	{
1623	pNew->pDevInsR3 = pDevIns;
1624	pNew->pvR3 = pvPages;
1625	//pNew->pNext = NULL;
1626	//pNew->fMapped = false;
1627	//pNew->fOverlapping = false;
1628	pNew->iRegion = iRegion;
1629	pNew->idSavedState = UINT8_MAX;
1630	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1631	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1632	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1633	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1634	pNew->RamRange.pszDesc = pszDesc;
1635	pNew->RamRange.cb = cb;
1636	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
1637	pNew->RamRange.pvR3 = pvPages;
1638	//pNew->RamRange.paLSPages = NULL;
1639
1640	uint32_t iPage = cPages;
1641	while (iPage-- > 0)
1642	{
1643	PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1644	paPages[iPage].Phys, NIL_GMM_PAGEID,
1645	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1646	}
1647
1648	/* update page count stats */
1649	pVM->pgm.s.cAllPages += cPages;
1650	pVM->pgm.s.cPrivatePages += cPages;
1651
1652	/*
1653	* Link it into the list.
1654	* Since there is no particular order, just push it.
1655	*/
1656	pgmLock(pVM);
1657	pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1658	pVM->pgm.s.pMmio2RangesR3 = pNew;
1659	pgmUnlock(pVM);
1660
1661	*ppv = pvPages;
1662	RTMemTmpFree(paPages);
1663	PGMPhysInvalidatePageMapTLB(pVM);
1664	return VINF_SUCCESS;
1665	}
1666
1667	SUPR3PageFreeEx(pvPages, cPages);
1668	}
1669	RTMemTmpFree(paPages);
1670	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1671	}
1672	if (pDevIns->iInstance > 0)
1673	MMR3HeapFree((void *)pszDesc);
1674	return rc;
1675	}
1676
1677
1678	/**
1679	* Deregisters and frees an MMIO2 region.
1680	*
1681	* Any physical (and virtual) access handlers registered for the region must
1682	* be deregistered before calling this function.
1683	*
1684	* @returns VBox status code.
1685	* @param pVM Pointer to the shared VM structure.
1686	* @param pDevIns The device instance owning the region.
1687	* @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1688	*/
1689	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1690	{
1691	/*
1692	* Validate input.
1693	*/
1694	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1695	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1696	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1697
1698	pgmLock(pVM);
1699	int rc = VINF_SUCCESS;
1700	unsigned cFound = 0;
1701	PPGMMMIO2RANGE pPrev = NULL;
1702	PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1703	while (pCur)
1704	{
1705	if ( pCur->pDevInsR3 == pDevIns
1706	&& ( iRegion == UINT32_MAX
1707	\|\| pCur->iRegion == iRegion))
1708	{
1709	cFound++;
1710
1711	/*
1712	* Unmap it if it's mapped.
1713	*/
1714	if (pCur->fMapped)
1715	{
1716	int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1717	AssertRC(rc2);
1718	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1719	rc = rc2;
1720	}
1721
1722	/*
1723	* Unlink it
1724	*/
1725	PPGMMMIO2RANGE pNext = pCur->pNextR3;
1726	if (pPrev)
1727	pPrev->pNextR3 = pNext;
1728	else
1729	pVM->pgm.s.pMmio2RangesR3 = pNext;
1730	pCur->pNextR3 = NULL;
1731
1732	/*
1733	* Free the memory.
1734	*/
1735	int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1736	AssertRC(rc2);
1737	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1738	rc = rc2;
1739
1740	uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1741	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1742	AssertRC(rc2);
1743	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1744	rc = rc2;
1745
1746	/* we're leaking hyper memory here if done at runtime. */
1747	#ifdef VBOX_STRICT
1748	VMSTATE const enmState = VMR3GetState(pVM);
1749	AssertMsg( enmState == VMSTATE_POWERING_OFF
1750	\|\| enmState == VMSTATE_POWERING_OFF_LS
1751	\|\| enmState == VMSTATE_OFF
1752	\|\| enmState == VMSTATE_OFF_LS
1753	\|\| enmState == VMSTATE_DESTROYING
1754	\|\| enmState == VMSTATE_TERMINATED
1755	\|\| enmState == VMSTATE_CREATING
1756	, ("%s\n", VMR3GetStateName(enmState)));
1757	#endif
1758	/*rc = MMHyperFree(pVM, pCur);
1759	AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1760
1761
1762	/* update page count stats */
1763	pVM->pgm.s.cAllPages -= cPages;
1764	pVM->pgm.s.cPrivatePages -= cPages;
1765
1766	/* next */
1767	pCur = pNext;
1768	}
1769	else
1770	{
1771	pPrev = pCur;
1772	pCur = pCur->pNextR3;
1773	}
1774	}
1775	PGMPhysInvalidatePageMapTLB(pVM);
1776	pgmUnlock(pVM);
1777	return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1778	}
1779
1780
1781	/**
1782	* Maps a MMIO2 region.
1783	*
1784	* This is done when a guest / the bios / state loading changes the
1785	* PCI config. The replacing of base memory has the same restrictions
1786	* as during registration, of course.
1787	*
1788	* @returns VBox status code.
1789	*
1790	* @param pVM Pointer to the shared VM structure.
1791	* @param pDevIns The
1792	*/
1793	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1794	{
1795	/*
1796	* Validate input
1797	*/
1798	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1799	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1800	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1801	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1802	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1803	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1804
1805	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1806	AssertReturn(pCur, VERR_NOT_FOUND);
1807	AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
1808	Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
1809	Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
1810
1811	const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
1812	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1813
1814	/*
1815	* Find our location in the ram range list, checking for
1816	* restriction we don't bother implementing yet (partially overlapping).
1817	*/
1818	bool fRamExists = false;
1819	PPGMRAMRANGE pRamPrev = NULL;
1820	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1821	while (pRam && GCPhysLast >= pRam->GCPhys)
1822	{
1823	if ( GCPhys <= pRam->GCPhysLast
1824	&& GCPhysLast >= pRam->GCPhys)
1825	{
1826	/* completely within? */
1827	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1828	&& GCPhysLast <= pRam->GCPhysLast,
1829	("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
1830	GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
1831	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1832	VERR_PGM_RAM_CONFLICT);
1833	fRamExists = true;
1834	break;
1835	}
1836
1837	/* next */
1838	pRamPrev = pRam;
1839	pRam = pRam->pNextR3;
1840	}
1841	if (fRamExists)
1842	{
1843	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1844	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1845	while (cPagesLeft-- > 0)
1846	{
1847	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1848	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
1849	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
1850	VERR_PGM_RAM_CONFLICT);
1851	pPage++;
1852	}
1853	}
1854	Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
1855	GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
1856
1857	/*
1858	* Make the changes.
1859	*/
1860	pgmLock(pVM);
1861
1862	pCur->RamRange.GCPhys = GCPhys;
1863	pCur->RamRange.GCPhysLast = GCPhysLast;
1864	pCur->fMapped = true;
1865	pCur->fOverlapping = fRamExists;
1866
1867	if (fRamExists)
1868	{
1869	/** @todo use pgmR3PhysFreePageRange here. */
1870	uint32_t cPendingPages = 0;
1871	PGMMFREEPAGESREQ pReq;
1872	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1873	AssertLogRelRCReturn(rc, rc);
1874
1875	/* replace the pages, freeing all present RAM pages. */
1876	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
1877	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1878	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1879	while (cPagesLeft-- > 0)
1880	{
1881	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
1882	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1883
1884	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
1885	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
1886	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
1887	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
1888
1889	pVM->pgm.s.cZeroPages--;
1890	GCPhys += PAGE_SIZE;
1891	pPageSrc++;
1892	pPageDst++;
1893	}
1894
1895	if (cPendingPages)
1896	{
1897	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1898	AssertLogRelRCReturn(rc, rc);
1899	}
1900	GMMR3FreePagesCleanup(pReq);
1901	pgmUnlock(pVM);
1902	}
1903	else
1904	{
1905	RTGCPHYS cb = pCur->RamRange.cb;
1906
1907	/* link in the ram range */
1908	pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
1909	pgmUnlock(pVM);
1910
1911	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
1912	}
1913
1914	PGMPhysInvalidatePageMapTLB(pVM);
1915	return VINF_SUCCESS;
1916	}
1917
1918
1919	/**
1920	* Unmaps a MMIO2 region.
1921	*
1922	* This is done when a guest / the bios / state loading changes the
1923	* PCI config. The replacing of base memory has the same restrictions
1924	* as during registration, of course.
1925	*/
1926	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1927	{
1928	/*
1929	* Validate input
1930	*/
1931	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1932	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1933	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1934	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1935	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1936	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1937
1938	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1939	AssertReturn(pCur, VERR_NOT_FOUND);
1940	AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
1941	AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
1942	Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
1943
1944	Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
1945	pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
1946
1947	/*
1948	* Unmap it.
1949	*/
1950	pgmLock(pVM);
1951
1952	RTGCPHYS GCPhysRangeREM;
1953	RTGCPHYS cbRangeREM;
1954	bool fInformREM;
1955	if (pCur->fOverlapping)
1956	{
1957	/* Restore the RAM pages we've replaced. */
1958	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1959	while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
1960	pRam = pRam->pNextR3;
1961
1962	RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
1963	Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
1964	PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1965	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1966	while (cPagesLeft-- > 0)
1967	{
1968	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
1969	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
1970	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
1971	PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
1972
1973	pVM->pgm.s.cZeroPages++;
1974	pPageDst++;
1975	}
1976
1977	GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
1978	cbRangeREM = RTGCPHYS_MAX; /* ditto */
1979	fInformREM = false;
1980	}
1981	else
1982	{
1983	GCPhysRangeREM = pCur->RamRange.GCPhys;
1984	cbRangeREM = pCur->RamRange.cb;
1985	fInformREM = true;
1986
1987	pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
1988	}
1989
1990	pCur->RamRange.GCPhys = NIL_RTGCPHYS;
1991	pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
1992	pCur->fOverlapping = false;
1993	pCur->fMapped = false;
1994
1995	PGMPhysInvalidatePageMapTLB(pVM);
1996	pgmUnlock(pVM);
1997
1998	if (fInformREM)
1999	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2000
2001	return VINF_SUCCESS;
2002	}
2003
2004
2005	/**
2006	* Checks if the given address is an MMIO2 base address or not.
2007	*
2008	* @returns true/false accordingly.
2009	* @param pVM Pointer to the shared VM structure.
2010	* @param pDevIns The owner of the memory, optional.
2011	* @param GCPhys The address to check.
2012	*/
2013	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2014	{
2015	/*
2016	* Validate input
2017	*/
2018	VM_ASSERT_EMT_RETURN(pVM, false);
2019	AssertPtrReturn(pDevIns, false);
2020	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
2021	AssertReturn(GCPhys != 0, false);
2022	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
2023
2024	/*
2025	* Search the list.
2026	*/
2027	pgmLock(pVM);
2028	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2029	if (pCur->RamRange.GCPhys == GCPhys)
2030	{
2031	Assert(pCur->fMapped);
2032	pgmUnlock(pVM);
2033	return true;
2034	}
2035	pgmUnlock(pVM);
2036	return false;
2037	}
2038
2039
2040	/**
2041	* Gets the HC physical address of a page in the MMIO2 region.
2042	*
2043	* This is API is intended for MMHyper and shouldn't be called
2044	* by anyone else...
2045	*
2046	* @returns VBox status code.
2047	* @param pVM Pointer to the shared VM structure.
2048	* @param pDevIns The owner of the memory, optional.
2049	* @param iRegion The region.
2050	* @param off The page expressed an offset into the MMIO2 region.
2051	* @param pHCPhys Where to store the result.
2052	*/
2053	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2054	{
2055	/*
2056	* Validate input
2057	*/
2058	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2059	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2060	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2061
2062	pgmLock(pVM);
2063	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2064	AssertReturn(pCur, VERR_NOT_FOUND);
2065	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2066
2067	PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2068	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2069	pgmUnlock(pVM);
2070	return VINF_SUCCESS;
2071	}
2072
2073
2074	/**
2075	* Maps a portion of an MMIO2 region into kernel space (host).
2076	*
2077	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
2078	* or the VM is terminated.
2079	*
2080	* @return VBox status code.
2081	*
2082	* @param pVM Pointer to the shared VM structure.
2083	* @param pDevIns The device owning the MMIO2 memory.
2084	* @param iRegion The region.
2085	* @param off The offset into the region. Must be page aligned.
2086	* @param cb The number of bytes to map. Must be page aligned.
2087	* @param pszDesc Mapping description.
2088	* @param pR0Ptr Where to store the R0 address.
2089	*/
2090	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2091	const char *pszDesc, PRTR0PTR pR0Ptr)
2092	{
2093	/*
2094	* Validate input.
2095	*/
2096	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2097	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2098	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2099
2100	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2101	AssertReturn(pCur, VERR_NOT_FOUND);
2102	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2103	AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2104	AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2105
2106	/*
2107	* Pass the request on to the support library/driver.
2108	*/
2109	int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2110
2111	return rc;
2112	}
2113
2114
2115	/**
2116	* Registers a ROM image.
2117	*
2118	* Shadowed ROM images requires double the amount of backing memory, so,
2119	* don't use that unless you have to. Shadowing of ROM images is process
2120	* where we can select where the reads go and where the writes go. On real
2121	* hardware the chipset provides means to configure this. We provide
2122	* PGMR3PhysProtectROM() for this purpose.
2123	*
2124	* A read-only copy of the ROM image will always be kept around while we
2125	* will allocate RAM pages for the changes on demand (unless all memory
2126	* is configured to be preallocated).
2127	*
2128	* @returns VBox status.
2129	* @param pVM VM Handle.
2130	* @param pDevIns The device instance owning the ROM.
2131	* @param GCPhys First physical address in the range.
2132	* Must be page aligned!
2133	* @param cbRange The size of the range (in bytes).
2134	* Must be page aligned!
2135	* @param pvBinary Pointer to the binary data backing the ROM image.
2136	* This must be exactly \a cbRange in size.
2137	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2138	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2139	* @param pszDesc Pointer to description string. This must not be freed.
2140	*
2141	* @remark There is no way to remove the rom, automatically on device cleanup or
2142	* manually from the device yet. This isn't difficult in any way, it's
2143	* just not something we expect to be necessary for a while.
2144	*/
2145	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2146	const void pvBinary, uint32_t fFlags, const char pszDesc)
2147	{
2148	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2149	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2150
2151	/*
2152	* Validate input.
2153	*/
2154	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2155	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2156	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2157	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2158	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2159	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2160	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2161	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2162	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2163
2164	const uint32_t cPages = cb >> PAGE_SHIFT;
2165
2166	/*
2167	* Find the ROM location in the ROM list first.
2168	*/
2169	PPGMROMRANGE pRomPrev = NULL;
2170	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2171	while (pRom && GCPhysLast >= pRom->GCPhys)
2172	{
2173	if ( GCPhys <= pRom->GCPhysLast
2174	&& GCPhysLast >= pRom->GCPhys)
2175	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2176	GCPhys, GCPhysLast, pszDesc,
2177	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2178	VERR_PGM_RAM_CONFLICT);
2179	/* next */
2180	pRomPrev = pRom;
2181	pRom = pRom->pNextR3;
2182	}
2183
2184	/*
2185	* Find the RAM location and check for conflicts.
2186	*
2187	* Conflict detection is a bit different than for RAM
2188	* registration since a ROM can be located within a RAM
2189	* range. So, what we have to check for is other memory
2190	* types (other than RAM that is) and that we don't span
2191	* more than one RAM range (layz).
2192	*/
2193	bool fRamExists = false;
2194	PPGMRAMRANGE pRamPrev = NULL;
2195	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2196	while (pRam && GCPhysLast >= pRam->GCPhys)
2197	{
2198	if ( GCPhys <= pRam->GCPhysLast
2199	&& GCPhysLast >= pRam->GCPhys)
2200	{
2201	/* completely within? */
2202	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2203	&& GCPhysLast <= pRam->GCPhysLast,
2204	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2205	GCPhys, GCPhysLast, pszDesc,
2206	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2207	VERR_PGM_RAM_CONFLICT);
2208	fRamExists = true;
2209	break;
2210	}
2211
2212	/* next */
2213	pRamPrev = pRam;
2214	pRam = pRam->pNextR3;
2215	}
2216	if (fRamExists)
2217	{
2218	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2219	uint32_t cPagesLeft = cPages;
2220	while (cPagesLeft-- > 0)
2221	{
2222	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2223	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2224	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2225	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2226	Assert(PGM_PAGE_IS_ZERO(pPage));
2227	pPage++;
2228	}
2229	}
2230
2231	/*
2232	* Update the base memory reservation if necessary.
2233	*/
2234	uint32_t cExtraBaseCost = fRamExists ? cPages : 0;
2235	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2236	cExtraBaseCost += cPages;
2237	if (cExtraBaseCost)
2238	{
2239	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2240	if (RT_FAILURE(rc))
2241	return rc;
2242	}
2243
2244	/*
2245	* Allocate memory for the virgin copy of the RAM.
2246	*/
2247	PGMMALLOCATEPAGESREQ pReq;
2248	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2249	AssertRCReturn(rc, rc);
2250
2251	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2252	{
2253	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2254	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2255	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2256	}
2257
2258	pgmLock(pVM);
2259	rc = GMMR3AllocatePagesPerform(pVM, pReq);
2260	pgmUnlock(pVM);
2261	if (RT_FAILURE(rc))
2262	{
2263	GMMR3AllocatePagesCleanup(pReq);
2264	return rc;
2265	}
2266
2267	/*
2268	* Allocate the new ROM range and RAM range (if necessary).
2269	*/
2270	PPGMROMRANGE pRomNew;
2271	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2272	if (RT_SUCCESS(rc))
2273	{
2274	PPGMRAMRANGE pRamNew = NULL;
2275	if (!fRamExists)
2276	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2277	if (RT_SUCCESS(rc))
2278	{
2279	pgmLock(pVM);
2280
2281	/*
2282	* Initialize and insert the RAM range (if required).
2283	*/
2284	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2285	if (!fRamExists)
2286	{
2287	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2288	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2289	pRamNew->GCPhys = GCPhys;
2290	pRamNew->GCPhysLast = GCPhysLast;
2291	pRamNew->cb = cb;
2292	pRamNew->pszDesc = pszDesc;
2293	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
2294	pRamNew->pvR3 = NULL;
2295	pRamNew->paLSPages = NULL;
2296
2297	PPGMPAGE pPage = &pRamNew->aPages[0];
2298	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2299	{
2300	PGM_PAGE_INIT(pPage,
2301	pReq->aPages[iPage].HCPhysGCPhys,
2302	pReq->aPages[iPage].idPage,
2303	PGMPAGETYPE_ROM,
2304	PGM_PAGE_STATE_ALLOCATED);
2305
2306	pRomPage->Virgin = *pPage;
2307	}
2308
2309	pVM->pgm.s.cAllPages += cPages;
2310	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2311	}
2312	else
2313	{
2314	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2315	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2316	{
2317	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2318	PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2319	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2320	PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2321
2322	pRomPage->Virgin = *pPage;
2323	}
2324
2325	pRamNew = pRam;
2326
2327	pVM->pgm.s.cZeroPages -= cPages;
2328	}
2329	pVM->pgm.s.cPrivatePages += cPages;
2330
2331	pgmUnlock(pVM);
2332
2333
2334	/*
2335	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2336	*
2337	* If it's shadowed we'll register the handler after the ROM notification
2338	* so we get the access handler callbacks that we should. If it isn't
2339	* shadowed we'll do it the other way around to make REM use the built-in
2340	* ROM behavior and not the handler behavior (which is to route all access
2341	* to PGM atm).
2342	*/
2343	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2344	{
2345	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2346	rc = PGMR3HandlerPhysicalRegister(pVM,
2347	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2348	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2349	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2350	GCPhys, GCPhysLast,
2351	pgmR3PhysRomWriteHandler, pRomNew,
2352	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2353	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2354	}
2355	else
2356	{
2357	rc = PGMR3HandlerPhysicalRegister(pVM,
2358	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2359	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2360	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2361	GCPhys, GCPhysLast,
2362	pgmR3PhysRomWriteHandler, pRomNew,
2363	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2364	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2365	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2366	}
2367	if (RT_SUCCESS(rc))
2368	{
2369	pgmLock(pVM);
2370
2371	/*
2372	* Copy the image over to the virgin pages.
2373	* This must be done after linking in the RAM range.
2374	*/
2375	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2376	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2377	{
2378	void *pvDstPage;
2379	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
2380	if (RT_FAILURE(rc))
2381	{
2382	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2383	break;
2384	}
2385	memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2386	}
2387	if (RT_SUCCESS(rc))
2388	{
2389	/*
2390	* Initialize the ROM range.
2391	* Note that the Virgin member of the pages has already been initialized above.
2392	*/
2393	pRomNew->GCPhys = GCPhys;
2394	pRomNew->GCPhysLast = GCPhysLast;
2395	pRomNew->cb = cb;
2396	pRomNew->fFlags = fFlags;
2397	pRomNew->idSavedState = UINT8_MAX;
2398	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2399	pRomNew->pszDesc = pszDesc;
2400
2401	for (unsigned iPage = 0; iPage < cPages; iPage++)
2402	{
2403	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2404	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2405	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2406	}
2407
2408	/* update the page count stats */
2409	pVM->pgm.s.cZeroPages += cPages;
2410	pVM->pgm.s.cAllPages += cPages;
2411
2412	/*
2413	* Insert the ROM range, tell REM and return successfully.
2414	*/
2415	pRomNew->pNextR3 = pRom;
2416	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2417	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2418
2419	if (pRomPrev)
2420	{
2421	pRomPrev->pNextR3 = pRomNew;
2422	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2423	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2424	}
2425	else
2426	{
2427	pVM->pgm.s.pRomRangesR3 = pRomNew;
2428	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2429	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2430	}
2431
2432	PGMPhysInvalidatePageMapTLB(pVM);
2433	GMMR3AllocatePagesCleanup(pReq);
2434	pgmUnlock(pVM);
2435	return VINF_SUCCESS;
2436	}
2437
2438	/* bail out */
2439
2440	pgmUnlock(pVM);
2441	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2442	AssertRC(rc2);
2443	pgmLock(pVM);
2444	}
2445
2446	if (!fRamExists)
2447	{
2448	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2449	MMHyperFree(pVM, pRamNew);
2450	}
2451	}
2452	MMHyperFree(pVM, pRomNew);
2453	}
2454
2455	/** @todo Purge the mapping cache or something... */
2456	GMMR3FreeAllocatedPages(pVM, pReq);
2457	GMMR3AllocatePagesCleanup(pReq);
2458	pgmUnlock(pVM);
2459	return rc;
2460	}
2461
2462
2463	/**
2464	* \#PF Handler callback for ROM write accesses.
2465	*
2466	* @returns VINF_SUCCESS if the handler have carried out the operation.
2467	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2468	* @param pVM VM Handle.
2469	* @param GCPhys The physical address the guest is writing to.
2470	* @param pvPhys The HC mapping of that address.
2471	* @param pvBuf What the guest is reading/writing.
2472	* @param cbBuf How much it's reading/writing.
2473	* @param enmAccessType The access type.
2474	* @param pvUser User argument.
2475	*/
2476	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2477	{
2478	PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2479	const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2480	Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2481	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2482	Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2483
2484	if (enmAccessType == PGMACCESSTYPE_READ)
2485	{
2486	switch (pRomPage->enmProt)
2487	{
2488	/*
2489	* Take the default action.
2490	*/
2491	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2492	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2493	case PGMROMPROT_READ_ROM_WRITE_RAM:
2494	case PGMROMPROT_READ_RAM_WRITE_RAM:
2495	return VINF_PGM_HANDLER_DO_DEFAULT;
2496
2497	default:
2498	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2499	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2500	VERR_INTERNAL_ERROR);
2501	}
2502	}
2503	else
2504	{
2505	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2506	switch (pRomPage->enmProt)
2507	{
2508	/*
2509	* Ignore writes.
2510	*/
2511	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2512	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2513	return VINF_SUCCESS;
2514
2515	/*
2516	* Write to the ram page.
2517	*/
2518	case PGMROMPROT_READ_ROM_WRITE_RAM:
2519	case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's way simpler that way. */
2520	{
2521	/* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2522	Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2523
2524	/*
2525	* Take the lock, do lazy allocation, map the page and copy the data.
2526	*
2527	* Note that we have to bypass the mapping TLB since it works on
2528	* guest physical addresses and entering the shadow page would
2529	* kind of screw things up...
2530	*/
2531	int rc = pgmLock(pVM);
2532	AssertRC(rc);
2533
2534	PPGMPAGE pShadowPage = &pRomPage->Shadow;
2535	if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2536	{
2537	pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2538	AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2539	}
2540
2541	void *pvDstPage;
2542	rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
2543	if (RT_SUCCESS(rc))
2544	{
2545	memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2546	pRomPage->LiveSave.fWrittenTo = true;
2547	}
2548
2549	pgmUnlock(pVM);
2550	return rc;
2551	}
2552
2553	default:
2554	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2555	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2556	VERR_INTERNAL_ERROR);
2557	}
2558	}
2559	}
2560
2561
2562	/**
2563	* Called by PGMR3Reset to reset the shadow, switch to the virgin,
2564	* and verify that the virgin part is untouched.
2565	*
2566	* This is done after the normal memory has been cleared.
2567	*
2568	* ASSUMES that the caller owns the PGM lock.
2569	*
2570	* @param pVM The VM handle.
2571	*/
2572	int pgmR3PhysRomReset(PVM pVM)
2573	{
2574	Assert(PGMIsLockOwner(pVM));
2575	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2576	{
2577	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2578
2579	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2580	{
2581	/*
2582	* Reset the physical handler.
2583	*/
2584	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2585	AssertRCReturn(rc, rc);
2586
2587	/*
2588	* What we do with the shadow pages depends on the memory
2589	* preallocation option. If not enabled, we'll just throw
2590	* out all the dirty pages and replace them by the zero page.
2591	*/
2592	if (!pVM->pgm.s.fRamPreAlloc)
2593	{
2594	/* Free the dirty pages. */
2595	uint32_t cPendingPages = 0;
2596	PGMMFREEPAGESREQ pReq;
2597	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2598	AssertRCReturn(rc, rc);
2599
2600	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2601	if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
2602	{
2603	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2604	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2605	AssertLogRelRCReturn(rc, rc);
2606	}
2607
2608	if (cPendingPages)
2609	{
2610	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2611	AssertLogRelRCReturn(rc, rc);
2612	}
2613	GMMR3FreePagesCleanup(pReq);
2614	}
2615	else
2616	{
2617	/* clear all the shadow pages. */
2618	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2619	{
2620	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO);
2621	void *pvDstPage;
2622	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2623	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
2624	if (RT_FAILURE(rc))
2625	break;
2626	ASMMemZeroPage(pvDstPage);
2627	}
2628	AssertRCReturn(rc, rc);
2629	}
2630	}
2631
2632	#ifdef VBOX_STRICT
2633	/*
2634	* Verify that the virgin page is unchanged if possible.
2635	*/
2636	if (pRom->pvOriginal)
2637	{
2638	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
2639	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2640	{
2641	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2642	void const *pvDstPage;
2643	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
2644	if (RT_FAILURE(rc))
2645	break;
2646	if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2647	LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2648	GCPhys, pRom->pszDesc));
2649	}
2650	}
2651	#endif
2652	}
2653
2654	return VINF_SUCCESS;
2655	}
2656
2657
2658	/**
2659	* Change the shadowing of a range of ROM pages.
2660	*
2661	* This is intended for implementing chipset specific memory registers
2662	* and will not be very strict about the input. It will silently ignore
2663	* any pages that are not the part of a shadowed ROM.
2664	*
2665	* @returns VBox status code.
2666	* @retval VINF_PGM_SYNC_CR3
2667	*
2668	* @param pVM Pointer to the shared VM structure.
2669	* @param GCPhys Where to start. Page aligned.
2670	* @param cb How much to change. Page aligned.
2671	* @param enmProt The new ROM protection.
2672	*/
2673	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2674	{
2675	/*
2676	* Check input
2677	*/
2678	if (!cb)
2679	return VINF_SUCCESS;
2680	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2681	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2682	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2683	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2684	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2685
2686	/*
2687	* Process the request.
2688	*/
2689	pgmLock(pVM);
2690	int rc = VINF_SUCCESS;
2691	bool fFlushTLB = false;
2692	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2693	{
2694	if ( GCPhys <= pRom->GCPhysLast
2695	&& GCPhysLast >= pRom->GCPhys
2696	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2697	{
2698	/*
2699	* Iterate the relevant pages and make necessary the changes.
2700	*/
2701	bool fChanges = false;
2702	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2703	? pRom->cb >> PAGE_SHIFT
2704	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2705	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2706	iPage < cPages;
2707	iPage++)
2708	{
2709	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2710	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2711	{
2712	fChanges = true;
2713
2714	/* flush references to the page. */
2715	PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2716	int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRamPage, &fFlushTLB);
2717	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
2718	rc = rc2;
2719
2720	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2721	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2722
2723	pOld = pRamPage;
2724	pRamPage = pNew;
2725	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2726	}
2727	pRomPage->enmProt = enmProt;
2728	}
2729
2730	/*
2731	* Reset the access handler if we made changes, no need
2732	* to optimize this.
2733	*/
2734	if (fChanges)
2735	{
2736	int rc = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2737	if (RT_FAILURE(rc))
2738	{
2739	pgmUnlock(pVM);
2740	AssertRC(rc);
2741	return rc;
2742	}
2743	}
2744
2745	/* Advance - cb isn't updated. */
2746	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2747	}
2748	}
2749	pgmUnlock(pVM);
2750	if (fFlushTLB)
2751	PGM_INVL_ALL_VCPU_TLBS(pVM);
2752
2753	return rc;
2754	}
2755
2756
2757	/**
2758	* Sets the Address Gate 20 state.
2759	*
2760	* @param pVCpu The VCPU to operate on.
2761	* @param fEnable True if the gate should be enabled.
2762	* False if the gate should be disabled.
2763	*/
2764	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
2765	{
2766	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
2767	if (pVCpu->pgm.s.fA20Enabled != fEnable)
2768	{
2769	pVCpu->pgm.s.fA20Enabled = fEnable;
2770	pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2771	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
2772	/** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2773	}
2774	}
2775
2776
2777	/**
2778	* Tree enumeration callback for dealing with age rollover.
2779	* It will perform a simple compression of the current age.
2780	*/
2781	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2782	{
2783	Assert(PGMIsLockOwner((PVM)pvUser));
2784	/* Age compression - ASSUMES iNow == 4. */
2785	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2786	if (pChunk->iAge >= UINT32_C(0xffffff00))
2787	pChunk->iAge = 3;
2788	else if (pChunk->iAge >= UINT32_C(0xfffff000))
2789	pChunk->iAge = 2;
2790	else if (pChunk->iAge)
2791	pChunk->iAge = 1;
2792	else /* iAge = 0 */
2793	pChunk->iAge = 4;
2794
2795	/* reinsert */
2796	PVM pVM = (PVM)pvUser;
2797	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2798	pChunk->AgeCore.Key = pChunk->iAge;
2799	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2800	return 0;
2801	}
2802
2803
2804	/**
2805	* Tree enumeration callback that updates the chunks that have
2806	* been used since the last
2807	*/
2808	static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
2809	{
2810	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2811	if (!pChunk->iAge)
2812	{
2813	PVM pVM = (PVM)pvUser;
2814	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2815	pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
2816	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2817	}
2818
2819	return 0;
2820	}
2821
2822
2823	/**
2824	* Performs ageing of the ring-3 chunk mappings.
2825	*
2826	* @param pVM The VM handle.
2827	*/
2828	VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
2829	{
2830	pgmLock(pVM);
2831	pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
2832	pVM->pgm.s.ChunkR3Map.iNow++;
2833	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
2834	{
2835	pVM->pgm.s.ChunkR3Map.iNow = 4;
2836	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
2837	}
2838	else
2839	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingCallback, pVM);
2840	pgmUnlock(pVM);
2841	}
2842
2843
2844	/**
2845	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
2846	*/
2847	typedef struct PGMR3PHYSCHUNKUNMAPCB
2848	{
2849	PVM pVM; /*< The VM handle. /
2850	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
2851	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
2852
2853
2854	/**
2855	* Callback used to find the mapping that's been unused for
2856	* the longest time.
2857	*/
2858	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
2859	{
2860	do
2861	{
2862	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
2863	if ( pChunk->iAge
2864	&& !pChunk->cRefs)
2865	{
2866	/*
2867	* Check that it's not in any of the TLBs.
2868	*/
2869	PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
2870	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2871	if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
2872	{
2873	pChunk = NULL;
2874	break;
2875	}
2876	if (pChunk)
2877	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
2878	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
2879	{
2880	pChunk = NULL;
2881	break;
2882	}
2883	if (pChunk)
2884	{
2885	((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
2886	return 1; /* done */
2887	}
2888	}
2889
2890	/* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
2891	pNode = pNode->pList;
2892	} while (pNode);
2893	return 0;
2894	}
2895
2896
2897	/**
2898	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
2899	*
2900	* The candidate will not be part of any TLBs, so no need to flush
2901	* anything afterwards.
2902	*
2903	* @returns Chunk id.
2904	* @param pVM The VM handle.
2905	*/
2906	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
2907	{
2908	Assert(PGMIsLockOwner(pVM));
2909
2910	/*
2911	* Do tree ageing first?
2912	*/
2913	if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
2914	PGMR3PhysChunkAgeing(pVM);
2915
2916	/*
2917	* Enumerate the age tree starting with the left most node.
2918	*/
2919	PGMR3PHYSCHUNKUNMAPCB Args;
2920	Args.pVM = pVM;
2921	Args.pChunk = NULL;
2922	if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
2923	return Args.pChunk->Core.Key;
2924	return INT32_MAX;
2925	}
2926
2927
2928	/**
2929	* Maps the given chunk into the ring-3 mapping cache.
2930	*
2931	* This will call ring-0.
2932	*
2933	* @returns VBox status code.
2934	* @param pVM The VM handle.
2935	* @param idChunk The chunk in question.
2936	* @param ppChunk Where to store the chunk tracking structure.
2937	*
2938	* @remarks Called from within the PGM critical section.
2939	*/
2940	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
2941	{
2942	int rc;
2943
2944	Assert(PGMIsLockOwner(pVM));
2945	/*
2946	* Allocate a new tracking structure first.
2947	*/
2948	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2949	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
2950	#else
2951	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
2952	#endif
2953	AssertReturn(pChunk, VERR_NO_MEMORY);
2954	pChunk->Core.Key = idChunk;
2955	pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
2956	pChunk->iAge = 0;
2957	pChunk->cRefs = 0;
2958	pChunk->cPermRefs = 0;
2959	pChunk->pv = NULL;
2960
2961	/*
2962	* Request the ring-0 part to map the chunk in question and if
2963	* necessary unmap another one to make space in the mapping cache.
2964	*/
2965	GMMMAPUNMAPCHUNKREQ Req;
2966	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2967	Req.Hdr.cbReq = sizeof(Req);
2968	Req.pvR3 = NULL;
2969	Req.idChunkMap = idChunk;
2970	Req.idChunkUnmap = NIL_GMM_CHUNKID;
2971	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
2972	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
2973	/** @todo This is wrong. Any thread in the VM process should be able to do this,
2974	* there are depenenecies on this. What currently saves the day is that
2975	* we don't unmap anything and that all non-zero memory will therefore
2976	* be present when non-EMTs tries to access it. */
2977	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
2978	if (RT_SUCCESS(rc))
2979	{
2980	/*
2981	* Update the tree.
2982	*/
2983	/* insert the new one. */
2984	AssertPtr(Req.pvR3);
2985	pChunk->pv = Req.pvR3;
2986	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
2987	AssertRelease(fRc);
2988	pVM->pgm.s.ChunkR3Map.c++;
2989
2990	fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2991	AssertRelease(fRc);
2992
2993	/* remove the unmapped one. */
2994	if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
2995	{
2996	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
2997	AssertRelease(pUnmappedChunk);
2998	pUnmappedChunk->pv = NULL;
2999	pUnmappedChunk->Core.Key = UINT32_MAX;
3000	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3001	MMR3HeapFree(pUnmappedChunk);
3002	#else
3003	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3004	#endif
3005	pVM->pgm.s.ChunkR3Map.c--;
3006	}
3007	}
3008	else
3009	{
3010	AssertRC(rc);
3011	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3012	MMR3HeapFree(pChunk);
3013	#else
3014	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
3015	#endif
3016	pChunk = NULL;
3017	}
3018
3019	*ppChunk = pChunk;
3020	return rc;
3021	}
3022
3023
3024	/**
3025	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3026	*
3027	* @returns see pgmR3PhysChunkMap.
3028	* @param pVM The VM handle.
3029	* @param idChunk The chunk to map.
3030	*/
3031	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3032	{
3033	PPGMCHUNKR3MAP pChunk;
3034	int rc;
3035
3036	pgmLock(pVM);
3037	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3038	pgmUnlock(pVM);
3039	return rc;
3040	}
3041
3042
3043	/**
3044	* Invalidates the TLB for the ring-3 mapping cache.
3045	*
3046	* @param pVM The VM handle.
3047	*/
3048	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3049	{
3050	pgmLock(pVM);
3051	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3052	{
3053	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3054	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3055	}
3056	pgmUnlock(pVM);
3057	}
3058
3059
3060	/**
3061	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3062	*
3063	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3064	* signal and clear the out of memory condition. When contracted, this API is
3065	* used to try clear the condition when the user wants to resume.
3066	*
3067	* @returns The following VBox status codes.
3068	* @retval VINF_SUCCESS on success. FFs cleared.
3069	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3070	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3071	*
3072	* @param pVM The VM handle.
3073	*
3074	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3075	* in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3076	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3077	* handler.
3078	*/
3079	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3080	{
3081	pgmLock(pVM);
3082
3083	/*
3084	* Allocate more pages, noting down the index of the first new page.
3085	*/
3086	uint32_t iClear = pVM->pgm.s.cHandyPages;
3087	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3088	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3089	int rcAlloc = VINF_SUCCESS;
3090	int rcSeed = VINF_SUCCESS;
3091	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3092	while (rc == VERR_GMM_SEED_ME)
3093	{
3094	void *pvChunk;
3095	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3096	if (RT_SUCCESS(rc))
3097	{
3098	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3099	if (RT_FAILURE(rc))
3100	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3101	}
3102	if (RT_SUCCESS(rc))
3103	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3104	}
3105
3106	if (RT_SUCCESS(rc))
3107	{
3108	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3109	Assert(pVM->pgm.s.cHandyPages > 0);
3110	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3111	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3112
3113	/*
3114	* Clear the pages.
3115	*/
3116	while (iClear < pVM->pgm.s.cHandyPages)
3117	{
3118	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3119	void *pv;
3120	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3121	AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3122	ASMMemZeroPage(pv);
3123	iClear++;
3124	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3125	}
3126	}
3127	else
3128	{
3129	/*
3130	* We should never get here unless there is a genuine shortage of
3131	* memory (or some internal error). Flag the error so the VM can be
3132	* suspended ASAP and the user informed. If we're totally out of
3133	* handy pages we will return failure.
3134	*/
3135	/* Report the failure. */
3136	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3137	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3138	rc, rcAlloc, rcSeed,
3139	pVM->pgm.s.cHandyPages,
3140	pVM->pgm.s.cAllPages,
3141	pVM->pgm.s.cPrivatePages,
3142	pVM->pgm.s.cSharedPages,
3143	pVM->pgm.s.cZeroPages));
3144	if ( rc != VERR_NO_MEMORY
3145	&& rc != VERR_LOCK_FAILED)
3146	{
3147	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3148	{
3149	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3150	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3151	pVM->pgm.s.aHandyPages[i].idSharedPage));
3152	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3153	if (idPage != NIL_GMM_PAGEID)
3154	{
3155	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3156	pRam;
3157	pRam = pRam->pNextR3)
3158	{
3159	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3160	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3161	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3162	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3163	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3164	}
3165	}
3166	}
3167	}
3168
3169	/* Set the FFs and adjust rc. */
3170	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3171	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3172	if ( rc == VERR_NO_MEMORY
3173	\|\| rc == VERR_LOCK_FAILED)
3174	rc = VINF_EM_NO_MEMORY;
3175	}
3176
3177	pgmUnlock(pVM);
3178	return rc;
3179	}
3180
3181
3182	/**
3183	* Frees the specified RAM page and replaces it with the ZERO page.
3184	*
3185	* This is used by ballooning, remapping MMIO2 and RAM reset.
3186	*
3187	* @param pVM Pointer to the shared VM structure.
3188	* @param pReq Pointer to the request.
3189	* @param pPage Pointer to the page structure.
3190	* @param GCPhys The guest physical address of the page, if applicable.
3191	*
3192	* @remarks The caller must own the PGM lock.
3193	*/
3194	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3195	{
3196	/*
3197	* Assert sanity.
3198	*/
3199	Assert(PGMIsLockOwner(pVM));
3200	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3201	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3202	{
3203	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3204	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3205	}
3206
3207	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO)
3208	return VINF_SUCCESS;
3209
3210	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3211	Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3212	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3213	\|\| idPage > GMM_PAGEID_LAST
3214	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3215	{
3216	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3217	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3218	}
3219
3220	/* update page count stats. */
3221	if (PGM_PAGE_IS_SHARED(pPage))
3222	pVM->pgm.s.cSharedPages--;
3223	else
3224	pVM->pgm.s.cPrivatePages--;
3225	pVM->pgm.s.cZeroPages++;
3226
3227	/*
3228	* pPage = ZERO page.
3229	*/
3230	PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3231	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3232	PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3233
3234	/*
3235	* Make sure it's not in the handy page array.
3236	*/
3237	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3238	{
3239	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3240	{
3241	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3242	break;
3243	}
3244	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3245	{
3246	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3247	break;
3248	}
3249	}
3250
3251	/*
3252	* Push it onto the page array.
3253	*/
3254	uint32_t iPage = *pcPendingPages;
3255	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3256	*pcPendingPages += 1;
3257
3258	pReq->aPages[iPage].idPage = idPage;
3259
3260	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3261	return VINF_SUCCESS;
3262
3263	/*
3264	* Flush the pages.
3265	*/
3266	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3267	if (RT_SUCCESS(rc))
3268	{
3269	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3270	*pcPendingPages = 0;
3271	}
3272	return rc;
3273	}
3274
3275
3276	/**
3277	* Converts a GC physical address to a HC ring-3 pointer, with some
3278	* additional checks.
3279	*
3280	* @returns VBox status code.
3281	* @retval VINF_SUCCESS on success.
3282	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3283	* access handler of some kind.
3284	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3285	* accesses or is odd in any way.
3286	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3287	*
3288	* @param pVM The VM handle.
3289	* @param GCPhys The GC physical address to convert.
3290	* @param fWritable Whether write access is required.
3291	* @param ppv Where to store the pointer corresponding to GCPhys on
3292	* success.
3293	*/
3294	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3295	{
3296	pgmLock(pVM);
3297
3298	PPGMRAMRANGE pRam;
3299	PPGMPAGE pPage;
3300	int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3301	if (RT_SUCCESS(rc))
3302	{
3303	if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3304	rc = VINF_SUCCESS;
3305	else
3306	{
3307	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3308	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3309	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3310	{
3311	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3312	* in -norawr0 mode. */
3313	if (fWritable)
3314	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3315	}
3316	else
3317	{
3318	/* Temporarily disabled physical handler(s), since the recompiler
3319	doesn't get notified when it's reset we'll have to pretend it's
3320	operating normally. */
3321	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3322	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3323	else
3324	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3325	}
3326	}
3327	if (RT_SUCCESS(rc))
3328	{
3329	int rc2;
3330
3331	/* Make sure what we return is writable. */
3332	if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3333	switch (PGM_PAGE_GET_STATE(pPage))
3334	{
3335	case PGM_PAGE_STATE_ALLOCATED:
3336	break;
3337	case PGM_PAGE_STATE_ZERO:
3338	case PGM_PAGE_STATE_SHARED:
3339	case PGM_PAGE_STATE_WRITE_MONITORED:
3340	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3341	AssertLogRelRCReturn(rc2, rc2);
3342	break;
3343	}
3344
3345	/* Get a ring-3 mapping of the address. */
3346	PPGMPAGER3MAPTLBE pTlbe;
3347	rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3348	AssertLogRelRCReturn(rc2, rc2);
3349	ppv = (void )((uintptr_t)pTlbe->pv \| (GCPhys & PAGE_OFFSET_MASK));
3350	/** @todo mapping/locking hell; this isn't horribly efficient since
3351	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
3352
3353	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
3354	}
3355	else
3356	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3357
3358	/* else: handler catching all access, no pointer returned. */
3359	}
3360	else
3361	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3362
3363	pgmUnlock(pVM);
3364	return rc;
3365	}
3366

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source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 24911

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