VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 26330

Last change on this file since 26330 was 26330, checked in by vboxsync, 15 years ago

Introducing PGMR3PhysFreeRamPages
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1/* $Id: PGMPhys.cpp 26330 2010-02-08 15:07:04Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM_PHYS
27#include <VBox/pgm.h>
28#include <VBox/iom.h>
29#include <VBox/mm.h>
30#include <VBox/stam.h>
31#include <VBox/rem.h>
32#include <VBox/pdmdev.h>
33#include "PGMInternal.h"
34#include <VBox/vm.h>
35#include "PGMInline.h"
36#include <VBox/sup.h>
37#include <VBox/param.h>
38#include <VBox/err.h>
39#include <VBox/log.h>
40#include <iprt/assert.h>
41#include <iprt/alloc.h>
42#include <iprt/asm.h>
43#include <iprt/thread.h>
44#include <iprt/string.h>
45
46
47/*******************************************************************************
48* Defined Constants And Macros *
49*******************************************************************************/
50/** The number of pages to free in one batch. */
51#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
52
53
54/*******************************************************************************
55* Internal Functions *
56*******************************************************************************/
57static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
58static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
59
60
61/*
62 * PGMR3PhysReadU8-64
63 * PGMR3PhysWriteU8-64
64 */
65#define PGMPHYSFN_READNAME PGMR3PhysReadU8
66#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
67#define PGMPHYS_DATASIZE 1
68#define PGMPHYS_DATATYPE uint8_t
69#include "PGMPhysRWTmpl.h"
70
71#define PGMPHYSFN_READNAME PGMR3PhysReadU16
72#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
73#define PGMPHYS_DATASIZE 2
74#define PGMPHYS_DATATYPE uint16_t
75#include "PGMPhysRWTmpl.h"
76
77#define PGMPHYSFN_READNAME PGMR3PhysReadU32
78#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
79#define PGMPHYS_DATASIZE 4
80#define PGMPHYS_DATATYPE uint32_t
81#include "PGMPhysRWTmpl.h"
82
83#define PGMPHYSFN_READNAME PGMR3PhysReadU64
84#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
85#define PGMPHYS_DATASIZE 8
86#define PGMPHYS_DATATYPE uint64_t
87#include "PGMPhysRWTmpl.h"
88
89
90/**
91 * EMT worker for PGMR3PhysReadExternal.
92 */
93static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
94{
95 PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
96 return VINF_SUCCESS;
97}
98
99
100/**
101 * Write to physical memory, external users.
102 *
103 * @returns VBox status code.
104 * @retval VINF_SUCCESS.
105 *
106 * @param pVM VM Handle.
107 * @param GCPhys Physical address to write to.
108 * @param pvBuf What to write.
109 * @param cbWrite How many bytes to write.
110 *
111 * @thread Any but EMTs.
112 */
113VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
114{
115 VM_ASSERT_OTHER_THREAD(pVM);
116
117 AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
118 LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
119
120 pgmLock(pVM);
121
122 /*
123 * Copy loop on ram ranges.
124 */
125 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
126 for (;;)
127 {
128 /* Find range. */
129 while (pRam && GCPhys > pRam->GCPhysLast)
130 pRam = pRam->CTX_SUFF(pNext);
131 /* Inside range or not? */
132 if (pRam && GCPhys >= pRam->GCPhys)
133 {
134 /*
135 * Must work our way thru this page by page.
136 */
137 RTGCPHYS off = GCPhys - pRam->GCPhys;
138 while (off < pRam->cb)
139 {
140 unsigned iPage = off >> PAGE_SHIFT;
141 PPGMPAGE pPage = &pRam->aPages[iPage];
142
143 /*
144 * If the page has an ALL access handler, we'll have to
145 * delegate the job to EMT.
146 */
147 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
148 {
149 pgmUnlock(pVM);
150
151 return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 4,
152 pVM, &GCPhys, pvBuf, cbRead);
153 }
154 Assert(!PGM_PAGE_IS_MMIO(pPage));
155
156 /*
157 * Simple stuff, go ahead.
158 */
159 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
160 if (cb > cbRead)
161 cb = cbRead;
162 const void *pvSrc;
163 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
164 if (RT_SUCCESS(rc))
165 memcpy(pvBuf, pvSrc, cb);
166 else
167 {
168 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
169 pRam->GCPhys + off, pPage, rc));
170 memset(pvBuf, 0xff, cb);
171 }
172
173 /* next page */
174 if (cb >= cbRead)
175 {
176 pgmUnlock(pVM);
177 return VINF_SUCCESS;
178 }
179 cbRead -= cb;
180 off += cb;
181 GCPhys += cb;
182 pvBuf = (char *)pvBuf + cb;
183 } /* walk pages in ram range. */
184 }
185 else
186 {
187 LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
188
189 /*
190 * Unassigned address space.
191 */
192 if (!pRam)
193 break;
194 size_t cb = pRam->GCPhys - GCPhys;
195 if (cb >= cbRead)
196 {
197 memset(pvBuf, 0xff, cbRead);
198 break;
199 }
200 memset(pvBuf, 0xff, cb);
201
202 cbRead -= cb;
203 pvBuf = (char *)pvBuf + cb;
204 GCPhys += cb;
205 }
206 } /* Ram range walk */
207
208 pgmUnlock(pVM);
209
210 return VINF_SUCCESS;
211}
212
213
214/**
215 * EMT worker for PGMR3PhysWriteExternal.
216 */
217static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
218{
219 /** @todo VERR_EM_NO_MEMORY */
220 PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
221 return VINF_SUCCESS;
222}
223
224
225/**
226 * Write to physical memory, external users.
227 *
228 * @returns VBox status code.
229 * @retval VINF_SUCCESS.
230 * @retval VERR_EM_NO_MEMORY.
231 *
232 * @param pVM VM Handle.
233 * @param GCPhys Physical address to write to.
234 * @param pvBuf What to write.
235 * @param cbWrite How many bytes to write.
236 * @param pszWho Who is writing. For tracking down who is writing
237 * after we've saved the state.
238 *
239 * @thread Any but EMTs.
240 */
241VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, const char *pszWho)
242{
243 VM_ASSERT_OTHER_THREAD(pVM);
244
245 AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
246 ("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x pszWho=%s\n",
247 GCPhys, cbWrite, pszWho));
248 AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
249 LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
250
251 pgmLock(pVM);
252
253 /*
254 * Copy loop on ram ranges, stop when we hit something difficult.
255 */
256 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
257 for (;;)
258 {
259 /* Find range. */
260 while (pRam && GCPhys > pRam->GCPhysLast)
261 pRam = pRam->CTX_SUFF(pNext);
262 /* Inside range or not? */
263 if (pRam && GCPhys >= pRam->GCPhys)
264 {
265 /*
266 * Must work our way thru this page by page.
267 */
268 RTGCPTR off = GCPhys - pRam->GCPhys;
269 while (off < pRam->cb)
270 {
271 RTGCPTR iPage = off >> PAGE_SHIFT;
272 PPGMPAGE pPage = &pRam->aPages[iPage];
273
274 /*
275 * Is the page problematic, we have to do the work on the EMT.
276 *
277 * Allocating writable pages and access handlers are
278 * problematic, write monitored pages are simple and can be
279 * dealth with here.
280 */
281 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
282 || PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
283 {
284 if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
285 && !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
286 pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
287 else
288 {
289 pgmUnlock(pVM);
290
291 return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 4,
292 pVM, &GCPhys, pvBuf, cbWrite);
293 }
294 }
295 Assert(!PGM_PAGE_IS_MMIO(pPage));
296
297 /*
298 * Simple stuff, go ahead.
299 */
300 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
301 if (cb > cbWrite)
302 cb = cbWrite;
303 void *pvDst;
304 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
305 if (RT_SUCCESS(rc))
306 memcpy(pvDst, pvBuf, cb);
307 else
308 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
309 pRam->GCPhys + off, pPage, rc));
310
311 /* next page */
312 if (cb >= cbWrite)
313 {
314 pgmUnlock(pVM);
315 return VINF_SUCCESS;
316 }
317
318 cbWrite -= cb;
319 off += cb;
320 GCPhys += cb;
321 pvBuf = (const char *)pvBuf + cb;
322 } /* walk pages in ram range */
323 }
324 else
325 {
326 /*
327 * Unassigned address space, skip it.
328 */
329 if (!pRam)
330 break;
331 size_t cb = pRam->GCPhys - GCPhys;
332 if (cb >= cbWrite)
333 break;
334 cbWrite -= cb;
335 pvBuf = (const char *)pvBuf + cb;
336 GCPhys += cb;
337 }
338 } /* Ram range walk */
339
340 pgmUnlock(pVM);
341 return VINF_SUCCESS;
342}
343
344
345/**
346 * VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
347 *
348 * @returns see PGMR3PhysGCPhys2CCPtrExternal
349 * @param pVM The VM handle.
350 * @param pGCPhys Pointer to the guest physical address.
351 * @param ppv Where to store the mapping address.
352 * @param pLock Where to store the lock.
353 */
354static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
355{
356 /*
357 * Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
358 * an access handler after it succeeds.
359 */
360 int rc = pgmLock(pVM);
361 AssertRCReturn(rc, rc);
362
363 rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
364 if (RT_SUCCESS(rc))
365 {
366 PPGMPAGEMAPTLBE pTlbe;
367 int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
368 AssertFatalRC(rc2);
369 PPGMPAGE pPage = pTlbe->pPage;
370 if (PGM_PAGE_IS_MMIO(pPage))
371 {
372 PGMPhysReleasePageMappingLock(pVM, pLock);
373 rc = VERR_PGM_PHYS_PAGE_RESERVED;
374 }
375 else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
376#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
377 || pgmPoolIsDirtyPage(pVM, *pGCPhys)
378#endif
379 )
380 {
381 /* We *must* flush any corresponding pgm pool page here, otherwise we'll
382 * not be informed about writes and keep bogus gst->shw mappings around.
383 */
384 pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
385 Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
386 /** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
387 * active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
388 }
389 }
390
391 pgmUnlock(pVM);
392 return rc;
393}
394
395
396/**
397 * Requests the mapping of a guest page into ring-3, external threads.
398 *
399 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
400 * release it.
401 *
402 * This API will assume your intention is to write to the page, and will
403 * therefore replace shared and zero pages. If you do not intend to modify the
404 * page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
405 *
406 * @returns VBox status code.
407 * @retval VINF_SUCCESS on success.
408 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
409 * backing or if the page has any active access handlers. The caller
410 * must fall back on using PGMR3PhysWriteExternal.
411 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
412 *
413 * @param pVM The VM handle.
414 * @param GCPhys The guest physical address of the page that should be mapped.
415 * @param ppv Where to store the address corresponding to GCPhys.
416 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
417 *
418 * @remark Avoid calling this API from within critical sections (other than the
419 * PGM one) because of the deadlock risk when we have to delegating the
420 * task to an EMT.
421 * @thread Any.
422 */
423VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
424{
425 AssertPtr(ppv);
426 AssertPtr(pLock);
427
428 Assert(VM_IS_EMT(pVM) || !PGMIsLockOwner(pVM));
429
430 int rc = pgmLock(pVM);
431 AssertRCReturn(rc, rc);
432
433 /*
434 * Query the Physical TLB entry for the page (may fail).
435 */
436 PPGMPAGEMAPTLBE pTlbe;
437 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
438 if (RT_SUCCESS(rc))
439 {
440 PPGMPAGE pPage = pTlbe->pPage;
441 if (PGM_PAGE_IS_MMIO(pPage))
442 rc = VERR_PGM_PHYS_PAGE_RESERVED;
443 else
444 {
445 /*
446 * If the page is shared, the zero page, or being write monitored
447 * it must be converted to an page that's writable if possible.
448 * We can only deal with write monitored pages here, the rest have
449 * to be on an EMT.
450 */
451 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
452 || PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
453#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
454 || pgmPoolIsDirtyPage(pVM, GCPhys)
455#endif
456 )
457 {
458 if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
459 && !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
460#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
461 && !pgmPoolIsDirtyPage(pVM, GCPhys)
462#endif
463 )
464 pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
465 else
466 {
467 pgmUnlock(pVM);
468
469 return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
470 pVM, &GCPhys, ppv, pLock);
471 }
472 }
473
474 /*
475 * Now, just perform the locking and calculate the return address.
476 */
477 PPGMPAGEMAP pMap = pTlbe->pMap;
478 if (pMap)
479 pMap->cRefs++;
480
481 unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
482 if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
483 {
484 if (cLocks == 0)
485 pVM->pgm.s.cWriteLockedPages++;
486 PGM_PAGE_INC_WRITE_LOCKS(pPage);
487 }
488 else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
489 {
490 PGM_PAGE_INC_WRITE_LOCKS(pPage);
491 AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
492 if (pMap)
493 pMap->cRefs++; /* Extra ref to prevent it from going away. */
494 }
495
496 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
497 pLock->uPageAndType = (uintptr_t)pPage | PGMPAGEMAPLOCK_TYPE_WRITE;
498 pLock->pvMap = pMap;
499 }
500 }
501
502 pgmUnlock(pVM);
503 return rc;
504}
505
506
507/**
508 * Requests the mapping of a guest page into ring-3, external threads.
509 *
510 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
511 * release it.
512 *
513 * @returns VBox status code.
514 * @retval VINF_SUCCESS on success.
515 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
516 * backing or if the page as an active ALL access handler. The caller
517 * must fall back on using PGMPhysRead.
518 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
519 *
520 * @param pVM The VM handle.
521 * @param GCPhys The guest physical address of the page that should be mapped.
522 * @param ppv Where to store the address corresponding to GCPhys.
523 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
524 *
525 * @remark Avoid calling this API from within critical sections (other than
526 * the PGM one) because of the deadlock risk.
527 * @thread Any.
528 */
529VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
530{
531 int rc = pgmLock(pVM);
532 AssertRCReturn(rc, rc);
533
534 /*
535 * Query the Physical TLB entry for the page (may fail).
536 */
537 PPGMPAGEMAPTLBE pTlbe;
538 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
539 if (RT_SUCCESS(rc))
540 {
541 PPGMPAGE pPage = pTlbe->pPage;
542#if 1
543 /* MMIO pages doesn't have any readable backing. */
544 if (PGM_PAGE_IS_MMIO(pPage))
545 rc = VERR_PGM_PHYS_PAGE_RESERVED;
546#else
547 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
548 rc = VERR_PGM_PHYS_PAGE_RESERVED;
549#endif
550 else
551 {
552 /*
553 * Now, just perform the locking and calculate the return address.
554 */
555 PPGMPAGEMAP pMap = pTlbe->pMap;
556 if (pMap)
557 pMap->cRefs++;
558
559 unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
560 if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
561 {
562 if (cLocks == 0)
563 pVM->pgm.s.cReadLockedPages++;
564 PGM_PAGE_INC_READ_LOCKS(pPage);
565 }
566 else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
567 {
568 PGM_PAGE_INC_READ_LOCKS(pPage);
569 AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
570 if (pMap)
571 pMap->cRefs++; /* Extra ref to prevent it from going away. */
572 }
573
574 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
575 pLock->uPageAndType = (uintptr_t)pPage | PGMPAGEMAPLOCK_TYPE_READ;
576 pLock->pvMap = pMap;
577 }
578 }
579
580 pgmUnlock(pVM);
581 return rc;
582}
583
584
585/**
586 * Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
587 *
588 * Called when anything was relocated.
589 *
590 * @param pVM Pointer to the shared VM structure.
591 */
592void pgmR3PhysRelinkRamRanges(PVM pVM)
593{
594 PPGMRAMRANGE pCur;
595
596#ifdef VBOX_STRICT
597 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
598 {
599 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
600 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
601 Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
602 Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
603 Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
604 Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
605 for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
606 Assert( pCur2 == pCur
607 || strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
608 }
609#endif
610
611 pCur = pVM->pgm.s.pRamRangesR3;
612 if (pCur)
613 {
614 pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
615 pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
616
617 for (; pCur->pNextR3; pCur = pCur->pNextR3)
618 {
619 pCur->pNextR0 = pCur->pNextR3->pSelfR0;
620 pCur->pNextRC = pCur->pNextR3->pSelfRC;
621 }
622
623 Assert(pCur->pNextR0 == NIL_RTR0PTR);
624 Assert(pCur->pNextRC == NIL_RTRCPTR);
625 }
626 else
627 {
628 Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
629 Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
630 }
631 ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
632}
633
634
635/**
636 * Links a new RAM range into the list.
637 *
638 * @param pVM Pointer to the shared VM structure.
639 * @param pNew Pointer to the new list entry.
640 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
641 */
642static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
643{
644 AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
645 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
646 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
647
648 pgmLock(pVM);
649
650 PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
651 pNew->pNextR3 = pRam;
652 pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
653 pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
654
655 if (pPrev)
656 {
657 pPrev->pNextR3 = pNew;
658 pPrev->pNextR0 = pNew->pSelfR0;
659 pPrev->pNextRC = pNew->pSelfRC;
660 }
661 else
662 {
663 pVM->pgm.s.pRamRangesR3 = pNew;
664 pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
665 pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
666 }
667 ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
668 pgmUnlock(pVM);
669}
670
671
672/**
673 * Unlink an existing RAM range from the list.
674 *
675 * @param pVM Pointer to the shared VM structure.
676 * @param pRam Pointer to the new list entry.
677 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
678 */
679static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
680{
681 Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
682 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
683 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
684
685 pgmLock(pVM);
686
687 PPGMRAMRANGE pNext = pRam->pNextR3;
688 if (pPrev)
689 {
690 pPrev->pNextR3 = pNext;
691 pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
692 pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
693 }
694 else
695 {
696 Assert(pVM->pgm.s.pRamRangesR3 == pRam);
697 pVM->pgm.s.pRamRangesR3 = pNext;
698 pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
699 pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
700 }
701 ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
702 pgmUnlock(pVM);
703}
704
705
706/**
707 * Unlink an existing RAM range from the list.
708 *
709 * @param pVM Pointer to the shared VM structure.
710 * @param pRam Pointer to the new list entry.
711 */
712static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
713{
714 pgmLock(pVM);
715
716 /* find prev. */
717 PPGMRAMRANGE pPrev = NULL;
718 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
719 while (pCur != pRam)
720 {
721 pPrev = pCur;
722 pCur = pCur->pNextR3;
723 }
724 AssertFatal(pCur);
725
726 pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
727 pgmUnlock(pVM);
728}
729
730
731/**
732 * Frees a range of pages, replacing them with ZERO pages of the specified type.
733 *
734 * @returns VBox status code.
735 * @param pVM The VM handle.
736 * @param pRam The RAM range in which the pages resides.
737 * @param GCPhys The address of the first page.
738 * @param GCPhysLast The address of the last page.
739 * @param uType The page type to replace then with.
740 */
741static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
742{
743 uint32_t cPendingPages = 0;
744 PGMMFREEPAGESREQ pReq;
745 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
746 AssertLogRelRCReturn(rc, rc);
747
748 /* Itegerate the pages. */
749 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
750 uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
751 while (cPagesLeft-- > 0)
752 {
753 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
754 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
755
756 PGM_PAGE_SET_TYPE(pPageDst, uType);
757
758 GCPhys += PAGE_SIZE;
759 pPageDst++;
760 }
761
762 if (cPendingPages)
763 {
764 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
765 AssertLogRelRCReturn(rc, rc);
766 }
767 GMMR3FreePagesCleanup(pReq);
768
769 return rc;
770}
771
772/**
773 * Frees a range of ram pages, replacing them with ZERO pages
774 *
775 * @returns VBox status code.
776 * @param pVM The VM handle.
777 * @param cPages Number of pages to free
778 * @param paPhysPage Array of guest physical addresses
779 */
780VMMR3DECL(int) PGMR3PhysFreeRamPages(PVM pVM, unsigned cPages, RTGCPHYS *paPhysPage)
781{
782 uint32_t cPendingPages = 0;
783 PGMMFREEPAGESREQ pReq;
784 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
785 AssertLogRelRCReturn(rc, rc);
786
787 /* Itegerate the pages. */
788 for (unsigned i = 0; i < cPages; i++)
789 {
790 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
791 if ( pPage == NULL
792 || pPage->uTypeY != PGMPAGETYPE_RAM)
793 {
794 Log(("PGMR3PhysFreePageRange: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], (pPage) ? pPage->uTypeY : 0));
795 break;
796 }
797
798 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i]);
799 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
800 }
801
802 if (cPendingPages)
803 {
804 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
805 AssertLogRelRCReturn(rc, rc);
806 }
807 GMMR3FreePagesCleanup(pReq);
808
809 return rc;
810}
811
812
813/**
814 * PGMR3PhysRegisterRam worker that initializes and links a RAM range.
815 *
816 * @param pVM The VM handle.
817 * @param pNew The new RAM range.
818 * @param GCPhys The address of the RAM range.
819 * @param GCPhysLast The last address of the RAM range.
820 * @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
821 * if in HMA.
822 * @param R0PtrNew Ditto for R0.
823 * @param pszDesc The description.
824 * @param pPrev The previous RAM range (for linking).
825 */
826static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
827 RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
828{
829 /*
830 * Initialize the range.
831 */
832 pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
833 pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
834 pNew->GCPhys = GCPhys;
835 pNew->GCPhysLast = GCPhysLast;
836 pNew->cb = GCPhysLast - GCPhys + 1;
837 pNew->pszDesc = pszDesc;
838 pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
839 pNew->pvR3 = NULL;
840 pNew->paLSPages = NULL;
841
842 uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
843 RTGCPHYS iPage = cPages;
844 while (iPage-- > 0)
845 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
846
847 /* Update the page count stats. */
848 pVM->pgm.s.cZeroPages += cPages;
849 pVM->pgm.s.cAllPages += cPages;
850
851 /*
852 * Link it.
853 */
854 pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
855}
856
857
858/**
859 * Relocate a floating RAM range.
860 *
861 * @copydoc FNPGMRELOCATE.
862 */
863static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
864{
865 PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
866 Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
867 Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
868
869 switch (enmMode)
870 {
871 case PGMRELOCATECALL_SUGGEST:
872 return true;
873 case PGMRELOCATECALL_RELOCATE:
874 {
875 /* Update myself and then relink all the ranges. */
876 pgmLock(pVM);
877 pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
878 pgmR3PhysRelinkRamRanges(pVM);
879 pgmUnlock(pVM);
880 return true;
881 }
882
883 default:
884 AssertFailedReturn(false);
885 }
886}
887
888
889/**
890 * PGMR3PhysRegisterRam worker that registers a high chunk.
891 *
892 * @returns VBox status code.
893 * @param pVM The VM handle.
894 * @param GCPhys The address of the RAM.
895 * @param cRamPages The number of RAM pages to register.
896 * @param cbChunk The size of the PGMRAMRANGE guest mapping.
897 * @param iChunk The chunk number.
898 * @param pszDesc The RAM range description.
899 * @param ppPrev Previous RAM range pointer. In/Out.
900 */
901static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
902 uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
903 PPGMRAMRANGE *ppPrev)
904{
905 const char *pszDescChunk = iChunk == 0
906 ? pszDesc
907 : MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
908 AssertReturn(pszDescChunk, VERR_NO_MEMORY);
909
910 /*
911 * Allocate memory for the new chunk.
912 */
913 size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
914 PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
915 AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
916 RTR0PTR R0PtrChunk = NIL_RTR0PTR;
917 void *pvChunk = NULL;
918 int rc = SUPR3PageAllocEx(cChunkPages, 0 /*fFlags*/, &pvChunk,
919#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
920 VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
921#else
922 NULL,
923#endif
924 paChunkPages);
925 if (RT_SUCCESS(rc))
926 {
927#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
928 if (!VMMIsHwVirtExtForced(pVM))
929 R0PtrChunk = NIL_RTR0PTR;
930#else
931 R0PtrChunk = (uintptr_t)pvChunk;
932#endif
933 memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
934
935 PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
936
937 /*
938 * Create a mapping and map the pages into it.
939 * We push these in below the HMA.
940 */
941 RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
942 rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /*fFlags*/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
943 if (RT_SUCCESS(rc))
944 {
945 pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
946
947 RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
948 RTGCPTR GCPtrPage = GCPtrChunk;
949 for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
950 rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
951 if (RT_SUCCESS(rc))
952 {
953 /*
954 * Ok, init and link the range.
955 */
956 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
957 (RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
958 *ppPrev = pNew;
959 }
960 }
961
962 if (RT_FAILURE(rc))
963 SUPR3PageFreeEx(pvChunk, cChunkPages);
964 }
965
966 RTMemTmpFree(paChunkPages);
967 return rc;
968}
969
970
971/**
972 * Sets up a range RAM.
973 *
974 * This will check for conflicting registrations, make a resource
975 * reservation for the memory (with GMM), and setup the per-page
976 * tracking structures (PGMPAGE).
977 *
978 * @returns VBox stutus code.
979 * @param pVM Pointer to the shared VM structure.
980 * @param GCPhys The physical address of the RAM.
981 * @param cb The size of the RAM.
982 * @param pszDesc The description - not copied, so, don't free or change it.
983 */
984VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
985{
986 /*
987 * Validate input.
988 */
989 Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
990 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
991 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
992 AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
993 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
994 AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
995 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
996 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
997
998 pgmLock(pVM);
999
1000 /*
1001 * Find range location and check for conflicts.
1002 * (We don't lock here because the locking by EMT is only required on update.)
1003 */
1004 PPGMRAMRANGE pPrev = NULL;
1005 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1006 while (pRam && GCPhysLast >= pRam->GCPhys)
1007 {
1008 if ( GCPhysLast >= pRam->GCPhys
1009 && GCPhys <= pRam->GCPhysLast)
1010 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1011 GCPhys, GCPhysLast, pszDesc,
1012 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1013 VERR_PGM_RAM_CONFLICT);
1014
1015 /* next */
1016 pPrev = pRam;
1017 pRam = pRam->pNextR3;
1018 }
1019
1020 /*
1021 * Register it with GMM (the API bitches).
1022 */
1023 const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1024 int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1025 if (RT_FAILURE(rc))
1026 {
1027 pgmUnlock(pVM);
1028 return rc;
1029 }
1030
1031 if ( GCPhys >= _4G
1032 && cPages > 256)
1033 {
1034 /*
1035 * The PGMRAMRANGE structures for the high memory can get very big.
1036 * In order to avoid SUPR3PageAllocEx allocation failures due to the
1037 * allocation size limit there and also to avoid being unable to find
1038 * guest mapping space for them, we split this memory up into 4MB in
1039 * (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1040 * mode.
1041 *
1042 * The first and last page of each mapping are guard pages and marked
1043 * not-present. So, we've got 4186112 and 16769024 bytes available for
1044 * the PGMRAMRANGE structure.
1045 *
1046 * Note! The sizes used here will influence the saved state.
1047 */
1048 uint32_t cbChunk;
1049 uint32_t cPagesPerChunk;
1050 if (VMMIsHwVirtExtForced(pVM))
1051 {
1052 cbChunk = 16U*_1M;
1053 cPagesPerChunk = 1048048; /* max ~1048059 */
1054 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U*_1M - PAGE_SIZE * 2);
1055 }
1056 else
1057 {
1058 cbChunk = 4U*_1M;
1059 cPagesPerChunk = 261616; /* max ~261627 */
1060 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U*_1M - PAGE_SIZE * 2);
1061 }
1062 AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1063
1064 RTGCPHYS cPagesLeft = cPages;
1065 RTGCPHYS GCPhysChunk = GCPhys;
1066 uint32_t iChunk = 0;
1067 while (cPagesLeft > 0)
1068 {
1069 uint32_t cPagesInChunk = cPagesLeft;
1070 if (cPagesInChunk > cPagesPerChunk)
1071 cPagesInChunk = cPagesPerChunk;
1072
1073 rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1074 AssertRCReturn(rc, rc);
1075
1076 /* advance */
1077 GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1078 cPagesLeft -= cPagesInChunk;
1079 iChunk++;
1080 }
1081 }
1082 else
1083 {
1084 /*
1085 * Allocate, initialize and link the new RAM range.
1086 */
1087 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1088 PPGMRAMRANGE pNew;
1089 rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1090 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1091
1092 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1093 }
1094 PGMPhysInvalidatePageMapTLB(pVM);
1095 pgmUnlock(pVM);
1096
1097 /*
1098 * Notify REM.
1099 */
1100 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1101
1102 return VINF_SUCCESS;
1103}
1104
1105
1106/**
1107 * Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1108 *
1109 * We do this late in the init process so that all the ROM and MMIO ranges have
1110 * been registered already and we don't go wasting memory on them.
1111 *
1112 * @returns VBox status code.
1113 *
1114 * @param pVM Pointer to the shared VM structure.
1115 */
1116int pgmR3PhysRamPreAllocate(PVM pVM)
1117{
1118 Assert(pVM->pgm.s.fRamPreAlloc);
1119 Log(("pgmR3PhysRamPreAllocate: enter\n"));
1120
1121 /*
1122 * Walk the RAM ranges and allocate all RAM pages, halt at
1123 * the first allocation error.
1124 */
1125 uint64_t cPages = 0;
1126 uint64_t NanoTS = RTTimeNanoTS();
1127 pgmLock(pVM);
1128 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1129 {
1130 PPGMPAGE pPage = &pRam->aPages[0];
1131 RTGCPHYS GCPhys = pRam->GCPhys;
1132 uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1133 while (cLeft-- > 0)
1134 {
1135 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1136 {
1137 switch (PGM_PAGE_GET_STATE(pPage))
1138 {
1139 case PGM_PAGE_STATE_ZERO:
1140 {
1141 int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1142 if (RT_FAILURE(rc))
1143 {
1144 LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1145 pgmUnlock(pVM);
1146 return rc;
1147 }
1148 cPages++;
1149 break;
1150 }
1151
1152 case PGM_PAGE_STATE_ALLOCATED:
1153 case PGM_PAGE_STATE_WRITE_MONITORED:
1154 case PGM_PAGE_STATE_SHARED:
1155 /* nothing to do here. */
1156 break;
1157 }
1158 }
1159
1160 /* next */
1161 pPage++;
1162 GCPhys += PAGE_SIZE;
1163 }
1164 }
1165 pgmUnlock(pVM);
1166 NanoTS = RTTimeNanoTS() - NanoTS;
1167
1168 LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1169 Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1170 return VINF_SUCCESS;
1171}
1172
1173
1174/**
1175 * Resets (zeros) the RAM.
1176 *
1177 * ASSUMES that the caller owns the PGM lock.
1178 *
1179 * @returns VBox status code.
1180 * @param pVM Pointer to the shared VM structure.
1181 */
1182int pgmR3PhysRamReset(PVM pVM)
1183{
1184 Assert(PGMIsLockOwner(pVM));
1185
1186 /*
1187 * We batch up pages that should be freed instead of calling GMM for
1188 * each and every one of them.
1189 */
1190 uint32_t cPendingPages = 0;
1191 PGMMFREEPAGESREQ pReq;
1192 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1193 AssertLogRelRCReturn(rc, rc);
1194
1195 /*
1196 * Walk the ram ranges.
1197 */
1198 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1199 {
1200 uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1201 AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1202
1203 if (!pVM->pgm.s.fRamPreAlloc)
1204 {
1205 /* Replace all RAM pages by ZERO pages. */
1206 while (iPage-- > 0)
1207 {
1208 PPGMPAGE pPage = &pRam->aPages[iPage];
1209 switch (PGM_PAGE_GET_TYPE(pPage))
1210 {
1211 case PGMPAGETYPE_RAM:
1212 if (!PGM_PAGE_IS_ZERO(pPage))
1213 {
1214 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1215 AssertLogRelRCReturn(rc, rc);
1216 }
1217 break;
1218
1219 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1220 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1221 break;
1222
1223 case PGMPAGETYPE_MMIO2:
1224 case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1225 case PGMPAGETYPE_ROM:
1226 case PGMPAGETYPE_MMIO:
1227 break;
1228 default:
1229 AssertFailed();
1230 }
1231 } /* for each page */
1232 }
1233 else
1234 {
1235 /* Zero the memory. */
1236 while (iPage-- > 0)
1237 {
1238 PPGMPAGE pPage = &pRam->aPages[iPage];
1239 switch (PGM_PAGE_GET_TYPE(pPage))
1240 {
1241 case PGMPAGETYPE_RAM:
1242 switch (PGM_PAGE_GET_STATE(pPage))
1243 {
1244 case PGM_PAGE_STATE_ZERO:
1245 break;
1246 case PGM_PAGE_STATE_SHARED:
1247 case PGM_PAGE_STATE_WRITE_MONITORED:
1248 rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1249 AssertLogRelRCReturn(rc, rc);
1250 case PGM_PAGE_STATE_ALLOCATED:
1251 {
1252 void *pvPage;
1253 rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1254 AssertLogRelRCReturn(rc, rc);
1255 ASMMemZeroPage(pvPage);
1256 break;
1257 }
1258 }
1259 break;
1260
1261 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1262 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1263 break;
1264
1265 case PGMPAGETYPE_MMIO2:
1266 case PGMPAGETYPE_ROM_SHADOW:
1267 case PGMPAGETYPE_ROM:
1268 case PGMPAGETYPE_MMIO:
1269 break;
1270 default:
1271 AssertFailed();
1272
1273 }
1274 } /* for each page */
1275 }
1276
1277 }
1278
1279 /*
1280 * Finish off any pages pending freeing.
1281 */
1282 if (cPendingPages)
1283 {
1284 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1285 AssertLogRelRCReturn(rc, rc);
1286 }
1287 GMMR3FreePagesCleanup(pReq);
1288
1289 return VINF_SUCCESS;
1290}
1291
1292
1293/**
1294 * This is the interface IOM is using to register an MMIO region.
1295 *
1296 * It will check for conflicts and ensure that a RAM range structure
1297 * is present before calling the PGMR3HandlerPhysicalRegister API to
1298 * register the callbacks.
1299 *
1300 * @returns VBox status code.
1301 *
1302 * @param pVM Pointer to the shared VM structure.
1303 * @param GCPhys The start of the MMIO region.
1304 * @param cb The size of the MMIO region.
1305 * @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1306 * @param pvUserR3 The user argument for R3.
1307 * @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1308 * @param pvUserR0 The user argument for R0.
1309 * @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1310 * @param pvUserRC The user argument for RC.
1311 * @param pszDesc The description of the MMIO region.
1312 */
1313VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1314 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1315 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1316 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1317 R3PTRTYPE(const char *) pszDesc)
1318{
1319 /*
1320 * Assert on some assumption.
1321 */
1322 VM_ASSERT_EMT(pVM);
1323 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1324 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1325 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1326 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1327
1328 /*
1329 * Make sure there's a RAM range structure for the region.
1330 */
1331 int rc;
1332 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1333 bool fRamExists = false;
1334 PPGMRAMRANGE pRamPrev = NULL;
1335 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1336 while (pRam && GCPhysLast >= pRam->GCPhys)
1337 {
1338 if ( GCPhysLast >= pRam->GCPhys
1339 && GCPhys <= pRam->GCPhysLast)
1340 {
1341 /* Simplification: all within the same range. */
1342 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1343 && GCPhysLast <= pRam->GCPhysLast,
1344 ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1345 GCPhys, GCPhysLast, pszDesc,
1346 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1347 VERR_PGM_RAM_CONFLICT);
1348
1349 /* Check that it's all RAM or MMIO pages. */
1350 PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1351 uint32_t cLeft = cb >> PAGE_SHIFT;
1352 while (cLeft-- > 0)
1353 {
1354 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1355 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1356 ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1357 GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1358 VERR_PGM_RAM_CONFLICT);
1359 pPage++;
1360 }
1361
1362 /* Looks good. */
1363 fRamExists = true;
1364 break;
1365 }
1366
1367 /* next */
1368 pRamPrev = pRam;
1369 pRam = pRam->pNextR3;
1370 }
1371 PPGMRAMRANGE pNew;
1372 if (fRamExists)
1373 {
1374 pNew = NULL;
1375
1376 /*
1377 * Make all the pages in the range MMIO/ZERO pages, freeing any
1378 * RAM pages currently mapped here. This might not be 100% correct
1379 * for PCI memory, but we're doing the same thing for MMIO2 pages.
1380 */
1381 rc = pgmLock(pVM);
1382 if (RT_SUCCESS(rc))
1383 {
1384 rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1385 pgmUnlock(pVM);
1386 }
1387 AssertRCReturn(rc, rc);
1388 }
1389 else
1390 {
1391 pgmLock(pVM);
1392
1393 /*
1394 * No RAM range, insert an ad hoc one.
1395 *
1396 * Note that we don't have to tell REM about this range because
1397 * PGMHandlerPhysicalRegisterEx will do that for us.
1398 */
1399 Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1400
1401 const uint32_t cPages = cb >> PAGE_SHIFT;
1402 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1403 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1404 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1405
1406 /* Initialize the range. */
1407 pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1408 pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1409 pNew->GCPhys = GCPhys;
1410 pNew->GCPhysLast = GCPhysLast;
1411 pNew->cb = cb;
1412 pNew->pszDesc = pszDesc;
1413 pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
1414 pNew->pvR3 = NULL;
1415 pNew->paLSPages = NULL;
1416
1417 uint32_t iPage = cPages;
1418 while (iPage-- > 0)
1419 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1420 Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1421
1422 /* update the page count stats. */
1423 pVM->pgm.s.cPureMmioPages += cPages;
1424 pVM->pgm.s.cAllPages += cPages;
1425
1426 /* link it */
1427 pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1428
1429 pgmUnlock(pVM);
1430 }
1431
1432 /*
1433 * Register the access handler.
1434 */
1435 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1436 pfnHandlerR3, pvUserR3,
1437 pfnHandlerR0, pvUserR0,
1438 pfnHandlerRC, pvUserRC, pszDesc);
1439 if ( RT_FAILURE(rc)
1440 && !fRamExists)
1441 {
1442 pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
1443 pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1444
1445 /* remove the ad hoc range. */
1446 pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1447 pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1448 MMHyperFree(pVM, pRam);
1449 }
1450 PGMPhysInvalidatePageMapTLB(pVM);
1451
1452 return rc;
1453}
1454
1455
1456/**
1457 * This is the interface IOM is using to register an MMIO region.
1458 *
1459 * It will take care of calling PGMHandlerPhysicalDeregister and clean up
1460 * any ad hoc PGMRAMRANGE left behind.
1461 *
1462 * @returns VBox status code.
1463 * @param pVM Pointer to the shared VM structure.
1464 * @param GCPhys The start of the MMIO region.
1465 * @param cb The size of the MMIO region.
1466 */
1467VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1468{
1469 VM_ASSERT_EMT(pVM);
1470
1471 /*
1472 * First deregister the handler, then check if we should remove the ram range.
1473 */
1474 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1475 if (RT_SUCCESS(rc))
1476 {
1477 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1478 PPGMRAMRANGE pRamPrev = NULL;
1479 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1480 while (pRam && GCPhysLast >= pRam->GCPhys)
1481 {
1482 /** @todo We're being a bit too careful here. rewrite. */
1483 if ( GCPhysLast == pRam->GCPhysLast
1484 && GCPhys == pRam->GCPhys)
1485 {
1486 Assert(pRam->cb == cb);
1487
1488 /*
1489 * See if all the pages are dead MMIO pages.
1490 */
1491 uint32_t const cPages = cb >> PAGE_SHIFT;
1492 bool fAllMMIO = true;
1493 uint32_t iPage = 0;
1494 uint32_t cLeft = cPages;
1495 while (cLeft-- > 0)
1496 {
1497 PPGMPAGE pPage = &pRam->aPages[iPage];
1498 if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1499 /*|| not-out-of-action later */)
1500 {
1501 fAllMMIO = false;
1502 Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1503 AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1504 break;
1505 }
1506 Assert(PGM_PAGE_IS_ZERO(pPage));
1507 pPage++;
1508 }
1509 if (fAllMMIO)
1510 {
1511 /*
1512 * Ad-hoc range, unlink and free it.
1513 */
1514 Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
1515 GCPhys, GCPhysLast, pRam->pszDesc));
1516
1517 pVM->pgm.s.cAllPages -= cPages;
1518 pVM->pgm.s.cPureMmioPages -= cPages;
1519
1520 pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1521 pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1522 MMHyperFree(pVM, pRam);
1523 break;
1524 }
1525 }
1526
1527 /*
1528 * Range match? It will all be within one range (see PGMAllHandler.cpp).
1529 */
1530 if ( GCPhysLast >= pRam->GCPhys
1531 && GCPhys <= pRam->GCPhysLast)
1532 {
1533 Assert(GCPhys >= pRam->GCPhys);
1534 Assert(GCPhysLast <= pRam->GCPhysLast);
1535
1536 /*
1537 * Turn the pages back into RAM pages.
1538 */
1539 uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1540 uint32_t cLeft = cb >> PAGE_SHIFT;
1541 while (cLeft--)
1542 {
1543 PPGMPAGE pPage = &pRam->aPages[iPage];
1544 AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1545 AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1546 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1547 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1548 }
1549 break;
1550 }
1551
1552 /* next */
1553 pRamPrev = pRam;
1554 pRam = pRam->pNextR3;
1555 }
1556 }
1557
1558 PGMPhysInvalidatePageMapTLB(pVM);
1559 return rc;
1560}
1561
1562
1563/**
1564 * Locate a MMIO2 range.
1565 *
1566 * @returns Pointer to the MMIO2 range.
1567 * @param pVM Pointer to the shared VM structure.
1568 * @param pDevIns The device instance owning the region.
1569 * @param iRegion The region.
1570 */
1571DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1572{
1573 /*
1574 * Search the list.
1575 */
1576 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1577 if ( pCur->pDevInsR3 == pDevIns
1578 && pCur->iRegion == iRegion)
1579 return pCur;
1580 return NULL;
1581}
1582
1583
1584/**
1585 * Allocate and register an MMIO2 region.
1586 *
1587 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1588 * RAM associated with a device. It is also non-shared memory with a
1589 * permanent ring-3 mapping and page backing (presently).
1590 *
1591 * A MMIO2 range may overlap with base memory if a lot of RAM
1592 * is configured for the VM, in which case we'll drop the base
1593 * memory pages. Presently we will make no attempt to preserve
1594 * anything that happens to be present in the base memory that
1595 * is replaced, this is of course incorrectly but it's too much
1596 * effort.
1597 *
1598 * @returns VBox status code.
1599 * @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1600 * @retval VERR_ALREADY_EXISTS if the region already exists.
1601 *
1602 * @param pVM Pointer to the shared VM structure.
1603 * @param pDevIns The device instance owning the region.
1604 * @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1605 * this number has to be the number of that region. Otherwise
1606 * it can be any number safe UINT8_MAX.
1607 * @param cb The size of the region. Must be page aligned.
1608 * @param fFlags Reserved for future use, must be zero.
1609 * @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1610 * @param pszDesc The description.
1611 */
1612VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)
1613{
1614 /*
1615 * Validate input.
1616 */
1617 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1618 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1619 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1620 AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1621 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1622 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1623 AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1624 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1625 AssertReturn(cb, VERR_INVALID_PARAMETER);
1626 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1627
1628 const uint32_t cPages = cb >> PAGE_SHIFT;
1629 AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1630 AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1631
1632 /*
1633 * For the 2nd+ instance, mangle the description string so it's unique.
1634 */
1635 if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
1636 {
1637 pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1638 if (!pszDesc)
1639 return VERR_NO_MEMORY;
1640 }
1641
1642 /*
1643 * Try reserve and allocate the backing memory first as this is what is
1644 * most likely to fail.
1645 */
1646 int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1647 if (RT_SUCCESS(rc))
1648 {
1649 void *pvPages;
1650 PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1651 if (RT_SUCCESS(rc))
1652 rc = SUPR3PageAllocEx(cPages, 0 /*fFlags*/, &pvPages, NULL /*pR0Ptr*/, paPages);
1653 if (RT_SUCCESS(rc))
1654 {
1655 memset(pvPages, 0, cPages * PAGE_SIZE);
1656
1657 /*
1658 * Create the MMIO2 range record for it.
1659 */
1660 const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1661 PPGMMMIO2RANGE pNew;
1662 rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1663 AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1664 if (RT_SUCCESS(rc))
1665 {
1666 pNew->pDevInsR3 = pDevIns;
1667 pNew->pvR3 = pvPages;
1668 //pNew->pNext = NULL;
1669 //pNew->fMapped = false;
1670 //pNew->fOverlapping = false;
1671 pNew->iRegion = iRegion;
1672 pNew->idSavedState = UINT8_MAX;
1673 pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1674 pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1675 pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1676 pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1677 pNew->RamRange.pszDesc = pszDesc;
1678 pNew->RamRange.cb = cb;
1679 pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
1680 pNew->RamRange.pvR3 = pvPages;
1681 //pNew->RamRange.paLSPages = NULL;
1682
1683 uint32_t iPage = cPages;
1684 while (iPage-- > 0)
1685 {
1686 PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1687 paPages[iPage].Phys, NIL_GMM_PAGEID,
1688 PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1689 }
1690
1691 /* update page count stats */
1692 pVM->pgm.s.cAllPages += cPages;
1693 pVM->pgm.s.cPrivatePages += cPages;
1694
1695 /*
1696 * Link it into the list.
1697 * Since there is no particular order, just push it.
1698 */
1699 pgmLock(pVM);
1700 pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1701 pVM->pgm.s.pMmio2RangesR3 = pNew;
1702 pgmUnlock(pVM);
1703
1704 *ppv = pvPages;
1705 RTMemTmpFree(paPages);
1706 PGMPhysInvalidatePageMapTLB(pVM);
1707 return VINF_SUCCESS;
1708 }
1709
1710 SUPR3PageFreeEx(pvPages, cPages);
1711 }
1712 RTMemTmpFree(paPages);
1713 MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1714 }
1715 if (pDevIns->iInstance > 0)
1716 MMR3HeapFree((void *)pszDesc);
1717 return rc;
1718}
1719
1720
1721/**
1722 * Deregisters and frees an MMIO2 region.
1723 *
1724 * Any physical (and virtual) access handlers registered for the region must
1725 * be deregistered before calling this function.
1726 *
1727 * @returns VBox status code.
1728 * @param pVM Pointer to the shared VM structure.
1729 * @param pDevIns The device instance owning the region.
1730 * @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1731 */
1732VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1733{
1734 /*
1735 * Validate input.
1736 */
1737 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1738 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1739 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1740
1741 pgmLock(pVM);
1742 int rc = VINF_SUCCESS;
1743 unsigned cFound = 0;
1744 PPGMMMIO2RANGE pPrev = NULL;
1745 PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1746 while (pCur)
1747 {
1748 if ( pCur->pDevInsR3 == pDevIns
1749 && ( iRegion == UINT32_MAX
1750 || pCur->iRegion == iRegion))
1751 {
1752 cFound++;
1753
1754 /*
1755 * Unmap it if it's mapped.
1756 */
1757 if (pCur->fMapped)
1758 {
1759 int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1760 AssertRC(rc2);
1761 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1762 rc = rc2;
1763 }
1764
1765 /*
1766 * Unlink it
1767 */
1768 PPGMMMIO2RANGE pNext = pCur->pNextR3;
1769 if (pPrev)
1770 pPrev->pNextR3 = pNext;
1771 else
1772 pVM->pgm.s.pMmio2RangesR3 = pNext;
1773 pCur->pNextR3 = NULL;
1774
1775 /*
1776 * Free the memory.
1777 */
1778 int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1779 AssertRC(rc2);
1780 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1781 rc = rc2;
1782
1783 uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1784 rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1785 AssertRC(rc2);
1786 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1787 rc = rc2;
1788
1789 /* we're leaking hyper memory here if done at runtime. */
1790#ifdef VBOX_STRICT
1791 VMSTATE const enmState = VMR3GetState(pVM);
1792 AssertMsg( enmState == VMSTATE_POWERING_OFF
1793 || enmState == VMSTATE_POWERING_OFF_LS
1794 || enmState == VMSTATE_OFF
1795 || enmState == VMSTATE_OFF_LS
1796 || enmState == VMSTATE_DESTROYING
1797 || enmState == VMSTATE_TERMINATED
1798 || enmState == VMSTATE_CREATING
1799 , ("%s\n", VMR3GetStateName(enmState)));
1800#endif
1801 /*rc = MMHyperFree(pVM, pCur);
1802 AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1803
1804
1805 /* update page count stats */
1806 pVM->pgm.s.cAllPages -= cPages;
1807 pVM->pgm.s.cPrivatePages -= cPages;
1808
1809 /* next */
1810 pCur = pNext;
1811 }
1812 else
1813 {
1814 pPrev = pCur;
1815 pCur = pCur->pNextR3;
1816 }
1817 }
1818 PGMPhysInvalidatePageMapTLB(pVM);
1819 pgmUnlock(pVM);
1820 return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1821}
1822
1823
1824/**
1825 * Maps a MMIO2 region.
1826 *
1827 * This is done when a guest / the bios / state loading changes the
1828 * PCI config. The replacing of base memory has the same restrictions
1829 * as during registration, of course.
1830 *
1831 * @returns VBox status code.
1832 *
1833 * @param pVM Pointer to the shared VM structure.
1834 * @param pDevIns The
1835 */
1836VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1837{
1838 /*
1839 * Validate input
1840 */
1841 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1842 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1843 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1844 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1845 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1846 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1847
1848 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1849 AssertReturn(pCur, VERR_NOT_FOUND);
1850 AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
1851 Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
1852 Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
1853
1854 const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
1855 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1856
1857 /*
1858 * Find our location in the ram range list, checking for
1859 * restriction we don't bother implementing yet (partially overlapping).
1860 */
1861 bool fRamExists = false;
1862 PPGMRAMRANGE pRamPrev = NULL;
1863 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1864 while (pRam && GCPhysLast >= pRam->GCPhys)
1865 {
1866 if ( GCPhys <= pRam->GCPhysLast
1867 && GCPhysLast >= pRam->GCPhys)
1868 {
1869 /* completely within? */
1870 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1871 && GCPhysLast <= pRam->GCPhysLast,
1872 ("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
1873 GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
1874 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1875 VERR_PGM_RAM_CONFLICT);
1876 fRamExists = true;
1877 break;
1878 }
1879
1880 /* next */
1881 pRamPrev = pRam;
1882 pRam = pRam->pNextR3;
1883 }
1884 if (fRamExists)
1885 {
1886 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1887 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1888 while (cPagesLeft-- > 0)
1889 {
1890 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1891 ("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
1892 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
1893 VERR_PGM_RAM_CONFLICT);
1894 pPage++;
1895 }
1896 }
1897 Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
1898 GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
1899
1900 /*
1901 * Make the changes.
1902 */
1903 pgmLock(pVM);
1904
1905 pCur->RamRange.GCPhys = GCPhys;
1906 pCur->RamRange.GCPhysLast = GCPhysLast;
1907 pCur->fMapped = true;
1908 pCur->fOverlapping = fRamExists;
1909
1910 if (fRamExists)
1911 {
1912/** @todo use pgmR3PhysFreePageRange here. */
1913 uint32_t cPendingPages = 0;
1914 PGMMFREEPAGESREQ pReq;
1915 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1916 AssertLogRelRCReturn(rc, rc);
1917
1918 /* replace the pages, freeing all present RAM pages. */
1919 PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
1920 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1921 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1922 while (cPagesLeft-- > 0)
1923 {
1924 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
1925 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1926
1927 RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
1928 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
1929 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
1930 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
1931
1932 pVM->pgm.s.cZeroPages--;
1933 GCPhys += PAGE_SIZE;
1934 pPageSrc++;
1935 pPageDst++;
1936 }
1937
1938 /* Flush physical page map TLB. */
1939 PGMPhysInvalidatePageMapTLB(pVM);
1940
1941 if (cPendingPages)
1942 {
1943 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1944 AssertLogRelRCReturn(rc, rc);
1945 }
1946 GMMR3FreePagesCleanup(pReq);
1947 pgmUnlock(pVM);
1948 }
1949 else
1950 {
1951 RTGCPHYS cb = pCur->RamRange.cb;
1952
1953 /* link in the ram range */
1954 pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
1955 pgmUnlock(pVM);
1956
1957 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
1958 }
1959
1960 PGMPhysInvalidatePageMapTLB(pVM);
1961 return VINF_SUCCESS;
1962}
1963
1964
1965/**
1966 * Unmaps a MMIO2 region.
1967 *
1968 * This is done when a guest / the bios / state loading changes the
1969 * PCI config. The replacing of base memory has the same restrictions
1970 * as during registration, of course.
1971 */
1972VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1973{
1974 /*
1975 * Validate input
1976 */
1977 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1978 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1979 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1980 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1981 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1982 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1983
1984 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1985 AssertReturn(pCur, VERR_NOT_FOUND);
1986 AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
1987 AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
1988 Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
1989
1990 Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
1991 pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
1992
1993 /*
1994 * Unmap it.
1995 */
1996 pgmLock(pVM);
1997
1998 RTGCPHYS GCPhysRangeREM;
1999 RTGCPHYS cbRangeREM;
2000 bool fInformREM;
2001 if (pCur->fOverlapping)
2002 {
2003 /* Restore the RAM pages we've replaced. */
2004 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2005 while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
2006 pRam = pRam->pNextR3;
2007
2008 RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
2009 Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
2010 PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2011 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2012 while (cPagesLeft-- > 0)
2013 {
2014 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
2015 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
2016 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
2017 PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
2018
2019 pVM->pgm.s.cZeroPages++;
2020 pPageDst++;
2021 }
2022
2023 /* Flush physical page map TLB. */
2024 PGMPhysInvalidatePageMapTLB(pVM);
2025
2026 GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
2027 cbRangeREM = RTGCPHYS_MAX; /* ditto */
2028 fInformREM = false;
2029 }
2030 else
2031 {
2032 GCPhysRangeREM = pCur->RamRange.GCPhys;
2033 cbRangeREM = pCur->RamRange.cb;
2034 fInformREM = true;
2035
2036 pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
2037 }
2038
2039 pCur->RamRange.GCPhys = NIL_RTGCPHYS;
2040 pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
2041 pCur->fOverlapping = false;
2042 pCur->fMapped = false;
2043
2044 PGMPhysInvalidatePageMapTLB(pVM);
2045 pgmUnlock(pVM);
2046
2047 if (fInformREM)
2048 REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2049
2050 return VINF_SUCCESS;
2051}
2052
2053
2054/**
2055 * Checks if the given address is an MMIO2 base address or not.
2056 *
2057 * @returns true/false accordingly.
2058 * @param pVM Pointer to the shared VM structure.
2059 * @param pDevIns The owner of the memory, optional.
2060 * @param GCPhys The address to check.
2061 */
2062VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2063{
2064 /*
2065 * Validate input
2066 */
2067 VM_ASSERT_EMT_RETURN(pVM, false);
2068 AssertPtrReturn(pDevIns, false);
2069 AssertReturn(GCPhys != NIL_RTGCPHYS, false);
2070 AssertReturn(GCPhys != 0, false);
2071 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
2072
2073 /*
2074 * Search the list.
2075 */
2076 pgmLock(pVM);
2077 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2078 if (pCur->RamRange.GCPhys == GCPhys)
2079 {
2080 Assert(pCur->fMapped);
2081 pgmUnlock(pVM);
2082 return true;
2083 }
2084 pgmUnlock(pVM);
2085 return false;
2086}
2087
2088
2089/**
2090 * Gets the HC physical address of a page in the MMIO2 region.
2091 *
2092 * This is API is intended for MMHyper and shouldn't be called
2093 * by anyone else...
2094 *
2095 * @returns VBox status code.
2096 * @param pVM Pointer to the shared VM structure.
2097 * @param pDevIns The owner of the memory, optional.
2098 * @param iRegion The region.
2099 * @param off The page expressed an offset into the MMIO2 region.
2100 * @param pHCPhys Where to store the result.
2101 */
2102VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2103{
2104 /*
2105 * Validate input
2106 */
2107 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2108 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2109 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2110
2111 pgmLock(pVM);
2112 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2113 AssertReturn(pCur, VERR_NOT_FOUND);
2114 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2115
2116 PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2117 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2118 pgmUnlock(pVM);
2119 return VINF_SUCCESS;
2120}
2121
2122
2123/**
2124 * Maps a portion of an MMIO2 region into kernel space (host).
2125 *
2126 * The kernel mapping will become invalid when the MMIO2 memory is deregistered
2127 * or the VM is terminated.
2128 *
2129 * @return VBox status code.
2130 *
2131 * @param pVM Pointer to the shared VM structure.
2132 * @param pDevIns The device owning the MMIO2 memory.
2133 * @param iRegion The region.
2134 * @param off The offset into the region. Must be page aligned.
2135 * @param cb The number of bytes to map. Must be page aligned.
2136 * @param pszDesc Mapping description.
2137 * @param pR0Ptr Where to store the R0 address.
2138 */
2139VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2140 const char *pszDesc, PRTR0PTR pR0Ptr)
2141{
2142 /*
2143 * Validate input.
2144 */
2145 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2146 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2147 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2148
2149 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2150 AssertReturn(pCur, VERR_NOT_FOUND);
2151 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2152 AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2153 AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2154
2155 /*
2156 * Pass the request on to the support library/driver.
2157 */
2158 int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2159
2160 return rc;
2161}
2162
2163
2164/**
2165 * Registers a ROM image.
2166 *
2167 * Shadowed ROM images requires double the amount of backing memory, so,
2168 * don't use that unless you have to. Shadowing of ROM images is process
2169 * where we can select where the reads go and where the writes go. On real
2170 * hardware the chipset provides means to configure this. We provide
2171 * PGMR3PhysProtectROM() for this purpose.
2172 *
2173 * A read-only copy of the ROM image will always be kept around while we
2174 * will allocate RAM pages for the changes on demand (unless all memory
2175 * is configured to be preallocated).
2176 *
2177 * @returns VBox status.
2178 * @param pVM VM Handle.
2179 * @param pDevIns The device instance owning the ROM.
2180 * @param GCPhys First physical address in the range.
2181 * Must be page aligned!
2182 * @param cbRange The size of the range (in bytes).
2183 * Must be page aligned!
2184 * @param pvBinary Pointer to the binary data backing the ROM image.
2185 * This must be exactly \a cbRange in size.
2186 * @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2187 * and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2188 * @param pszDesc Pointer to description string. This must not be freed.
2189 *
2190 * @remark There is no way to remove the rom, automatically on device cleanup or
2191 * manually from the device yet. This isn't difficult in any way, it's
2192 * just not something we expect to be necessary for a while.
2193 */
2194VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2195 const void *pvBinary, uint32_t fFlags, const char *pszDesc)
2196{
2197 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2198 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2199
2200 /*
2201 * Validate input.
2202 */
2203 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2204 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2205 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2206 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2207 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2208 AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2209 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2210 AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED | PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2211 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2212
2213 const uint32_t cPages = cb >> PAGE_SHIFT;
2214
2215 /*
2216 * Find the ROM location in the ROM list first.
2217 */
2218 PPGMROMRANGE pRomPrev = NULL;
2219 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2220 while (pRom && GCPhysLast >= pRom->GCPhys)
2221 {
2222 if ( GCPhys <= pRom->GCPhysLast
2223 && GCPhysLast >= pRom->GCPhys)
2224 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2225 GCPhys, GCPhysLast, pszDesc,
2226 pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2227 VERR_PGM_RAM_CONFLICT);
2228 /* next */
2229 pRomPrev = pRom;
2230 pRom = pRom->pNextR3;
2231 }
2232
2233 /*
2234 * Find the RAM location and check for conflicts.
2235 *
2236 * Conflict detection is a bit different than for RAM
2237 * registration since a ROM can be located within a RAM
2238 * range. So, what we have to check for is other memory
2239 * types (other than RAM that is) and that we don't span
2240 * more than one RAM range (layz).
2241 */
2242 bool fRamExists = false;
2243 PPGMRAMRANGE pRamPrev = NULL;
2244 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2245 while (pRam && GCPhysLast >= pRam->GCPhys)
2246 {
2247 if ( GCPhys <= pRam->GCPhysLast
2248 && GCPhysLast >= pRam->GCPhys)
2249 {
2250 /* completely within? */
2251 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2252 && GCPhysLast <= pRam->GCPhysLast,
2253 ("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2254 GCPhys, GCPhysLast, pszDesc,
2255 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2256 VERR_PGM_RAM_CONFLICT);
2257 fRamExists = true;
2258 break;
2259 }
2260
2261 /* next */
2262 pRamPrev = pRam;
2263 pRam = pRam->pNextR3;
2264 }
2265 if (fRamExists)
2266 {
2267 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2268 uint32_t cPagesLeft = cPages;
2269 while (cPagesLeft-- > 0)
2270 {
2271 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2272 ("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2273 pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2274 pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2275 Assert(PGM_PAGE_IS_ZERO(pPage));
2276 pPage++;
2277 }
2278 }
2279
2280 /*
2281 * Update the base memory reservation if necessary.
2282 */
2283 uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
2284 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2285 cExtraBaseCost += cPages;
2286 if (cExtraBaseCost)
2287 {
2288 int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2289 if (RT_FAILURE(rc))
2290 return rc;
2291 }
2292
2293 /*
2294 * Allocate memory for the virgin copy of the RAM.
2295 */
2296 PGMMALLOCATEPAGESREQ pReq;
2297 int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2298 AssertRCReturn(rc, rc);
2299
2300 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2301 {
2302 pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2303 pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2304 pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2305 }
2306
2307 pgmLock(pVM);
2308 rc = GMMR3AllocatePagesPerform(pVM, pReq);
2309 pgmUnlock(pVM);
2310 if (RT_FAILURE(rc))
2311 {
2312 GMMR3AllocatePagesCleanup(pReq);
2313 return rc;
2314 }
2315
2316 /*
2317 * Allocate the new ROM range and RAM range (if necessary).
2318 */
2319 PPGMROMRANGE pRomNew;
2320 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2321 if (RT_SUCCESS(rc))
2322 {
2323 PPGMRAMRANGE pRamNew = NULL;
2324 if (!fRamExists)
2325 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2326 if (RT_SUCCESS(rc))
2327 {
2328 pgmLock(pVM);
2329
2330 /*
2331 * Initialize and insert the RAM range (if required).
2332 */
2333 PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2334 if (!fRamExists)
2335 {
2336 pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2337 pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2338 pRamNew->GCPhys = GCPhys;
2339 pRamNew->GCPhysLast = GCPhysLast;
2340 pRamNew->cb = cb;
2341 pRamNew->pszDesc = pszDesc;
2342 pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
2343 pRamNew->pvR3 = NULL;
2344 pRamNew->paLSPages = NULL;
2345
2346 PPGMPAGE pPage = &pRamNew->aPages[0];
2347 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2348 {
2349 PGM_PAGE_INIT(pPage,
2350 pReq->aPages[iPage].HCPhysGCPhys,
2351 pReq->aPages[iPage].idPage,
2352 PGMPAGETYPE_ROM,
2353 PGM_PAGE_STATE_ALLOCATED);
2354
2355 pRomPage->Virgin = *pPage;
2356 }
2357
2358 pVM->pgm.s.cAllPages += cPages;
2359 pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2360 }
2361 else
2362 {
2363 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2364 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2365 {
2366 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2367 PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2368 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2369 PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2370
2371 pRomPage->Virgin = *pPage;
2372 }
2373
2374 pRamNew = pRam;
2375
2376 pVM->pgm.s.cZeroPages -= cPages;
2377 }
2378 pVM->pgm.s.cPrivatePages += cPages;
2379
2380 /* Flush physical page map TLB. */
2381 PGMPhysInvalidatePageMapTLB(pVM);
2382
2383 pgmUnlock(pVM);
2384
2385
2386 /*
2387 * !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2388 *
2389 * If it's shadowed we'll register the handler after the ROM notification
2390 * so we get the access handler callbacks that we should. If it isn't
2391 * shadowed we'll do it the other way around to make REM use the built-in
2392 * ROM behavior and not the handler behavior (which is to route all access
2393 * to PGM atm).
2394 */
2395 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2396 {
2397 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2398 rc = PGMR3HandlerPhysicalRegister(pVM,
2399 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2400 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2401 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2402 GCPhys, GCPhysLast,
2403 pgmR3PhysRomWriteHandler, pRomNew,
2404 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2405 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2406 }
2407 else
2408 {
2409 rc = PGMR3HandlerPhysicalRegister(pVM,
2410 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2411 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2412 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2413 GCPhys, GCPhysLast,
2414 pgmR3PhysRomWriteHandler, pRomNew,
2415 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2416 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2417 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2418 }
2419 if (RT_SUCCESS(rc))
2420 {
2421 pgmLock(pVM);
2422
2423 /*
2424 * Copy the image over to the virgin pages.
2425 * This must be done after linking in the RAM range.
2426 */
2427 PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2428 for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2429 {
2430 void *pvDstPage;
2431 rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
2432 if (RT_FAILURE(rc))
2433 {
2434 VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2435 break;
2436 }
2437 memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2438 }
2439 if (RT_SUCCESS(rc))
2440 {
2441 /*
2442 * Initialize the ROM range.
2443 * Note that the Virgin member of the pages has already been initialized above.
2444 */
2445 pRomNew->GCPhys = GCPhys;
2446 pRomNew->GCPhysLast = GCPhysLast;
2447 pRomNew->cb = cb;
2448 pRomNew->fFlags = fFlags;
2449 pRomNew->idSavedState = UINT8_MAX;
2450 pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2451 pRomNew->pszDesc = pszDesc;
2452
2453 for (unsigned iPage = 0; iPage < cPages; iPage++)
2454 {
2455 PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2456 pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2457 PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2458 }
2459
2460 /* update the page count stats for the shadow pages. */
2461 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2462 {
2463 pVM->pgm.s.cZeroPages += cPages;
2464 pVM->pgm.s.cAllPages += cPages;
2465 }
2466
2467 /*
2468 * Insert the ROM range, tell REM and return successfully.
2469 */
2470 pRomNew->pNextR3 = pRom;
2471 pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2472 pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2473
2474 if (pRomPrev)
2475 {
2476 pRomPrev->pNextR3 = pRomNew;
2477 pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2478 pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2479 }
2480 else
2481 {
2482 pVM->pgm.s.pRomRangesR3 = pRomNew;
2483 pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2484 pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2485 }
2486
2487 PGMPhysInvalidatePageMapTLB(pVM);
2488 GMMR3AllocatePagesCleanup(pReq);
2489 pgmUnlock(pVM);
2490 return VINF_SUCCESS;
2491 }
2492
2493 /* bail out */
2494
2495 pgmUnlock(pVM);
2496 int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2497 AssertRC(rc2);
2498 pgmLock(pVM);
2499 }
2500
2501 if (!fRamExists)
2502 {
2503 pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2504 MMHyperFree(pVM, pRamNew);
2505 }
2506 }
2507 MMHyperFree(pVM, pRomNew);
2508 }
2509
2510 /** @todo Purge the mapping cache or something... */
2511 GMMR3FreeAllocatedPages(pVM, pReq);
2512 GMMR3AllocatePagesCleanup(pReq);
2513 pgmUnlock(pVM);
2514 return rc;
2515}
2516
2517
2518/**
2519 * \#PF Handler callback for ROM write accesses.
2520 *
2521 * @returns VINF_SUCCESS if the handler have carried out the operation.
2522 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2523 * @param pVM VM Handle.
2524 * @param GCPhys The physical address the guest is writing to.
2525 * @param pvPhys The HC mapping of that address.
2526 * @param pvBuf What the guest is reading/writing.
2527 * @param cbBuf How much it's reading/writing.
2528 * @param enmAccessType The access type.
2529 * @param pvUser User argument.
2530 */
2531static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2532{
2533 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2534 const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2535 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2536 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2537 Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2538
2539 if (enmAccessType == PGMACCESSTYPE_READ)
2540 {
2541 switch (pRomPage->enmProt)
2542 {
2543 /*
2544 * Take the default action.
2545 */
2546 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2547 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2548 case PGMROMPROT_READ_ROM_WRITE_RAM:
2549 case PGMROMPROT_READ_RAM_WRITE_RAM:
2550 return VINF_PGM_HANDLER_DO_DEFAULT;
2551
2552 default:
2553 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2554 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2555 VERR_INTERNAL_ERROR);
2556 }
2557 }
2558 else
2559 {
2560 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2561 switch (pRomPage->enmProt)
2562 {
2563 /*
2564 * Ignore writes.
2565 */
2566 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2567 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2568 return VINF_SUCCESS;
2569
2570 /*
2571 * Write to the ram page.
2572 */
2573 case PGMROMPROT_READ_ROM_WRITE_RAM:
2574 case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
2575 {
2576 /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2577 Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2578
2579 /*
2580 * Take the lock, do lazy allocation, map the page and copy the data.
2581 *
2582 * Note that we have to bypass the mapping TLB since it works on
2583 * guest physical addresses and entering the shadow page would
2584 * kind of screw things up...
2585 */
2586 int rc = pgmLock(pVM);
2587 AssertRC(rc);
2588
2589 PPGMPAGE pShadowPage = &pRomPage->Shadow;
2590 if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2591 {
2592 pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2593 AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2594 }
2595
2596 void *pvDstPage;
2597 rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
2598 if (RT_SUCCESS(rc))
2599 {
2600 memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2601 pRomPage->LiveSave.fWrittenTo = true;
2602 }
2603
2604 pgmUnlock(pVM);
2605 return rc;
2606 }
2607
2608 default:
2609 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2610 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2611 VERR_INTERNAL_ERROR);
2612 }
2613 }
2614}
2615
2616
2617/**
2618 * Called by PGMR3Reset to reset the shadow, switch to the virgin,
2619 * and verify that the virgin part is untouched.
2620 *
2621 * This is done after the normal memory has been cleared.
2622 *
2623 * ASSUMES that the caller owns the PGM lock.
2624 *
2625 * @param pVM The VM handle.
2626 */
2627int pgmR3PhysRomReset(PVM pVM)
2628{
2629 Assert(PGMIsLockOwner(pVM));
2630 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2631 {
2632 const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2633
2634 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2635 {
2636 /*
2637 * Reset the physical handler.
2638 */
2639 int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2640 AssertRCReturn(rc, rc);
2641
2642 /*
2643 * What we do with the shadow pages depends on the memory
2644 * preallocation option. If not enabled, we'll just throw
2645 * out all the dirty pages and replace them by the zero page.
2646 */
2647 if (!pVM->pgm.s.fRamPreAlloc)
2648 {
2649 /* Free the dirty pages. */
2650 uint32_t cPendingPages = 0;
2651 PGMMFREEPAGESREQ pReq;
2652 rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2653 AssertRCReturn(rc, rc);
2654
2655 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2656 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
2657 {
2658 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2659 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2660 AssertLogRelRCReturn(rc, rc);
2661 }
2662
2663 if (cPendingPages)
2664 {
2665 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2666 AssertLogRelRCReturn(rc, rc);
2667 }
2668 GMMR3FreePagesCleanup(pReq);
2669 }
2670 else
2671 {
2672 /* clear all the shadow pages. */
2673 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2674 {
2675 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO);
2676 void *pvDstPage;
2677 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2678 rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
2679 if (RT_FAILURE(rc))
2680 break;
2681 ASMMemZeroPage(pvDstPage);
2682 }
2683 AssertRCReturn(rc, rc);
2684 }
2685 }
2686
2687#ifdef VBOX_STRICT
2688 /*
2689 * Verify that the virgin page is unchanged if possible.
2690 */
2691 if (pRom->pvOriginal)
2692 {
2693 uint8_t const *pbSrcPage = (uint8_t const *)pRom->pvOriginal;
2694 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2695 {
2696 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2697 void const *pvDstPage;
2698 int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
2699 if (RT_FAILURE(rc))
2700 break;
2701 if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2702 LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2703 GCPhys, pRom->pszDesc));
2704 }
2705 }
2706#endif
2707 }
2708
2709 return VINF_SUCCESS;
2710}
2711
2712
2713/**
2714 * Change the shadowing of a range of ROM pages.
2715 *
2716 * This is intended for implementing chipset specific memory registers
2717 * and will not be very strict about the input. It will silently ignore
2718 * any pages that are not the part of a shadowed ROM.
2719 *
2720 * @returns VBox status code.
2721 * @retval VINF_PGM_SYNC_CR3
2722 *
2723 * @param pVM Pointer to the shared VM structure.
2724 * @param GCPhys Where to start. Page aligned.
2725 * @param cb How much to change. Page aligned.
2726 * @param enmProt The new ROM protection.
2727 */
2728VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2729{
2730 /*
2731 * Check input
2732 */
2733 if (!cb)
2734 return VINF_SUCCESS;
2735 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2736 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2737 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2738 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2739 AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2740
2741 /*
2742 * Process the request.
2743 */
2744 pgmLock(pVM);
2745 int rc = VINF_SUCCESS;
2746 bool fFlushTLB = false;
2747 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2748 {
2749 if ( GCPhys <= pRom->GCPhysLast
2750 && GCPhysLast >= pRom->GCPhys
2751 && (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2752 {
2753 /*
2754 * Iterate the relevant pages and make necessary the changes.
2755 */
2756 bool fChanges = false;
2757 uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2758 ? pRom->cb >> PAGE_SHIFT
2759 : (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2760 for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2761 iPage < cPages;
2762 iPage++)
2763 {
2764 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2765 if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2766 {
2767 fChanges = true;
2768
2769 /* flush references to the page. */
2770 PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2771 int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRamPage, &fFlushTLB);
2772 if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS || RT_FAILURE(rc2)))
2773 rc = rc2;
2774
2775 PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2776 PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2777
2778 *pOld = *pRamPage;
2779 *pRamPage = *pNew;
2780 /** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2781 }
2782 pRomPage->enmProt = enmProt;
2783 }
2784
2785 /*
2786 * Reset the access handler if we made changes, no need
2787 * to optimize this.
2788 */
2789 if (fChanges)
2790 {
2791 int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2792 if (RT_FAILURE(rc2))
2793 {
2794 pgmUnlock(pVM);
2795 AssertRC(rc);
2796 return rc2;
2797 }
2798 }
2799
2800 /* Advance - cb isn't updated. */
2801 GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2802 }
2803 }
2804 pgmUnlock(pVM);
2805 if (fFlushTLB)
2806 PGM_INVL_ALL_VCPU_TLBS(pVM);
2807
2808 return rc;
2809}
2810
2811
2812/**
2813 * Sets the Address Gate 20 state.
2814 *
2815 * @param pVCpu The VCPU to operate on.
2816 * @param fEnable True if the gate should be enabled.
2817 * False if the gate should be disabled.
2818 */
2819VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
2820{
2821 LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
2822 if (pVCpu->pgm.s.fA20Enabled != fEnable)
2823 {
2824 pVCpu->pgm.s.fA20Enabled = fEnable;
2825 pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2826 REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
2827 /** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2828 }
2829}
2830
2831
2832/**
2833 * Tree enumeration callback for dealing with age rollover.
2834 * It will perform a simple compression of the current age.
2835 */
2836static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2837{
2838 Assert(PGMIsLockOwner((PVM)pvUser));
2839 /* Age compression - ASSUMES iNow == 4. */
2840 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2841 if (pChunk->iAge >= UINT32_C(0xffffff00))
2842 pChunk->iAge = 3;
2843 else if (pChunk->iAge >= UINT32_C(0xfffff000))
2844 pChunk->iAge = 2;
2845 else if (pChunk->iAge)
2846 pChunk->iAge = 1;
2847 else /* iAge = 0 */
2848 pChunk->iAge = 4;
2849
2850 /* reinsert */
2851 PVM pVM = (PVM)pvUser;
2852 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2853 pChunk->AgeCore.Key = pChunk->iAge;
2854 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2855 return 0;
2856}
2857
2858
2859/**
2860 * Tree enumeration callback that updates the chunks that have
2861 * been used since the last
2862 */
2863static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
2864{
2865 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2866 if (!pChunk->iAge)
2867 {
2868 PVM pVM = (PVM)pvUser;
2869 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2870 pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
2871 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2872 }
2873
2874 return 0;
2875}
2876
2877
2878/**
2879 * Performs ageing of the ring-3 chunk mappings.
2880 *
2881 * @param pVM The VM handle.
2882 */
2883VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
2884{
2885 pgmLock(pVM);
2886 pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
2887 pVM->pgm.s.ChunkR3Map.iNow++;
2888 if (pVM->pgm.s.ChunkR3Map.iNow == 0)
2889 {
2890 pVM->pgm.s.ChunkR3Map.iNow = 4;
2891 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
2892 }
2893 else
2894 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingCallback, pVM);
2895 pgmUnlock(pVM);
2896}
2897
2898
2899/**
2900 * The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
2901 */
2902typedef struct PGMR3PHYSCHUNKUNMAPCB
2903{
2904 PVM pVM; /**< The VM handle. */
2905 PPGMCHUNKR3MAP pChunk; /**< The chunk to unmap. */
2906} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
2907
2908
2909/**
2910 * Callback used to find the mapping that's been unused for
2911 * the longest time.
2912 */
2913static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
2914{
2915 do
2916 {
2917 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
2918 if ( pChunk->iAge
2919 && !pChunk->cRefs)
2920 {
2921 /*
2922 * Check that it's not in any of the TLBs.
2923 */
2924 PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
2925 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2926 if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
2927 {
2928 pChunk = NULL;
2929 break;
2930 }
2931 if (pChunk)
2932 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
2933 if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
2934 {
2935 pChunk = NULL;
2936 break;
2937 }
2938 if (pChunk)
2939 {
2940 ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
2941 return 1; /* done */
2942 }
2943 }
2944
2945 /* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
2946 pNode = pNode->pList;
2947 } while (pNode);
2948 return 0;
2949}
2950
2951
2952/**
2953 * Finds a good candidate for unmapping when the ring-3 mapping cache is full.
2954 *
2955 * The candidate will not be part of any TLBs, so no need to flush
2956 * anything afterwards.
2957 *
2958 * @returns Chunk id.
2959 * @param pVM The VM handle.
2960 */
2961static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
2962{
2963 Assert(PGMIsLockOwner(pVM));
2964
2965 /*
2966 * Do tree ageing first?
2967 */
2968 if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
2969 PGMR3PhysChunkAgeing(pVM);
2970
2971 /*
2972 * Enumerate the age tree starting with the left most node.
2973 */
2974 PGMR3PHYSCHUNKUNMAPCB Args;
2975 Args.pVM = pVM;
2976 Args.pChunk = NULL;
2977 if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /*fFromLeft*/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
2978 return Args.pChunk->Core.Key;
2979 return INT32_MAX;
2980}
2981
2982
2983/**
2984 * Maps the given chunk into the ring-3 mapping cache.
2985 *
2986 * This will call ring-0.
2987 *
2988 * @returns VBox status code.
2989 * @param pVM The VM handle.
2990 * @param idChunk The chunk in question.
2991 * @param ppChunk Where to store the chunk tracking structure.
2992 *
2993 * @remarks Called from within the PGM critical section.
2994 */
2995int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
2996{
2997 int rc;
2998
2999 Assert(PGMIsLockOwner(pVM));
3000 /*
3001 * Allocate a new tracking structure first.
3002 */
3003#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3004 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
3005#else
3006 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
3007#endif
3008 AssertReturn(pChunk, VERR_NO_MEMORY);
3009 pChunk->Core.Key = idChunk;
3010 pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
3011 pChunk->iAge = 0;
3012 pChunk->cRefs = 0;
3013 pChunk->cPermRefs = 0;
3014 pChunk->pv = NULL;
3015
3016 /*
3017 * Request the ring-0 part to map the chunk in question and if
3018 * necessary unmap another one to make space in the mapping cache.
3019 */
3020 GMMMAPUNMAPCHUNKREQ Req;
3021 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3022 Req.Hdr.cbReq = sizeof(Req);
3023 Req.pvR3 = NULL;
3024 Req.idChunkMap = idChunk;
3025 Req.idChunkUnmap = NIL_GMM_CHUNKID;
3026 if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3027 Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
3028/** @todo This is wrong. Any thread in the VM process should be able to do this,
3029 * there are depenenecies on this. What currently saves the day is that
3030 * we don't unmap anything and that all non-zero memory will therefore
3031 * be present when non-EMTs tries to access it. */
3032 rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3033 if (RT_SUCCESS(rc))
3034 {
3035 /*
3036 * Update the tree.
3037 */
3038 /* insert the new one. */
3039 AssertPtr(Req.pvR3);
3040 pChunk->pv = Req.pvR3;
3041 bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
3042 AssertRelease(fRc);
3043 pVM->pgm.s.ChunkR3Map.c++;
3044
3045 fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3046 AssertRelease(fRc);
3047
3048 /* remove the unmapped one. */
3049 if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
3050 {
3051 PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
3052 AssertRelease(pUnmappedChunk);
3053 pUnmappedChunk->pv = NULL;
3054 pUnmappedChunk->Core.Key = UINT32_MAX;
3055#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3056 MMR3HeapFree(pUnmappedChunk);
3057#else
3058 MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3059#endif
3060 pVM->pgm.s.ChunkR3Map.c--;
3061
3062 /* Chunk removed, so clear the page map TBL as well (might still be referenced). */
3063 PGMPhysInvalidatePageMapTLB(pVM);
3064 }
3065 }
3066 else
3067 {
3068 AssertRC(rc);
3069#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3070 MMR3HeapFree(pChunk);
3071#else
3072 MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
3073#endif
3074 pChunk = NULL;
3075 }
3076
3077 *ppChunk = pChunk;
3078 return rc;
3079}
3080
3081
3082/**
3083 * For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3084 *
3085 * @returns see pgmR3PhysChunkMap.
3086 * @param pVM The VM handle.
3087 * @param idChunk The chunk to map.
3088 */
3089VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3090{
3091 PPGMCHUNKR3MAP pChunk;
3092 int rc;
3093
3094 pgmLock(pVM);
3095 rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3096 pgmUnlock(pVM);
3097 return rc;
3098}
3099
3100
3101/**
3102 * Invalidates the TLB for the ring-3 mapping cache.
3103 *
3104 * @param pVM The VM handle.
3105 */
3106VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3107{
3108 pgmLock(pVM);
3109 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3110 {
3111 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3112 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3113 }
3114 /* The page map TLB references chunks, so invalidate that one too. */
3115 PGMPhysInvalidatePageMapTLB(pVM);
3116 pgmUnlock(pVM);
3117}
3118
3119
3120/**
3121 * Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3122 *
3123 * This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3124 * signal and clear the out of memory condition. When contracted, this API is
3125 * used to try clear the condition when the user wants to resume.
3126 *
3127 * @returns The following VBox status codes.
3128 * @retval VINF_SUCCESS on success. FFs cleared.
3129 * @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3130 * this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3131 *
3132 * @param pVM The VM handle.
3133 *
3134 * @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3135 * in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3136 * pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3137 * handler.
3138 */
3139VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3140{
3141 pgmLock(pVM);
3142
3143 /*
3144 * Allocate more pages, noting down the index of the first new page.
3145 */
3146 uint32_t iClear = pVM->pgm.s.cHandyPages;
3147 AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3148 Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3149 int rcAlloc = VINF_SUCCESS;
3150 int rcSeed = VINF_SUCCESS;
3151 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3152 while (rc == VERR_GMM_SEED_ME)
3153 {
3154 void *pvChunk;
3155 rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3156 if (RT_SUCCESS(rc))
3157 {
3158 rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3159 if (RT_FAILURE(rc))
3160 SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3161 }
3162 if (RT_SUCCESS(rc))
3163 rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3164 }
3165
3166 if (RT_SUCCESS(rc))
3167 {
3168 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3169 Assert(pVM->pgm.s.cHandyPages > 0);
3170 VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3171 VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3172
3173 /*
3174 * Clear the pages.
3175 */
3176 while (iClear < pVM->pgm.s.cHandyPages)
3177 {
3178 PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3179 void *pv;
3180 rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3181 AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3182 ASMMemZeroPage(pv);
3183 iClear++;
3184 Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3185 }
3186 }
3187 else
3188 {
3189 /*
3190 * We should never get here unless there is a genuine shortage of
3191 * memory (or some internal error). Flag the error so the VM can be
3192 * suspended ASAP and the user informed. If we're totally out of
3193 * handy pages we will return failure.
3194 */
3195 /* Report the failure. */
3196 LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3197 " cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3198 rc, rcAlloc, rcSeed,
3199 pVM->pgm.s.cHandyPages,
3200 pVM->pgm.s.cAllPages,
3201 pVM->pgm.s.cPrivatePages,
3202 pVM->pgm.s.cSharedPages,
3203 pVM->pgm.s.cZeroPages));
3204 if ( rc != VERR_NO_MEMORY
3205 && rc != VERR_LOCK_FAILED)
3206 {
3207 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3208 {
3209 LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3210 i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3211 pVM->pgm.s.aHandyPages[i].idSharedPage));
3212 uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3213 if (idPage != NIL_GMM_PAGEID)
3214 {
3215 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3216 pRam;
3217 pRam = pRam->pNextR3)
3218 {
3219 uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3220 for (uint32_t iPage = 0; iPage < cPages; iPage++)
3221 if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3222 LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3223 pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3224 }
3225 }
3226 }
3227 }
3228
3229 /* Set the FFs and adjust rc. */
3230 VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3231 VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3232 if ( rc == VERR_NO_MEMORY
3233 || rc == VERR_LOCK_FAILED)
3234 rc = VINF_EM_NO_MEMORY;
3235 }
3236
3237 pgmUnlock(pVM);
3238 return rc;
3239}
3240
3241
3242/**
3243 * Frees the specified RAM page and replaces it with the ZERO page.
3244 *
3245 * This is used by ballooning, remapping MMIO2 and RAM reset.
3246 *
3247 * @param pVM Pointer to the shared VM structure.
3248 * @param pReq Pointer to the request.
3249 * @param pPage Pointer to the page structure.
3250 * @param GCPhys The guest physical address of the page, if applicable.
3251 *
3252 * @remarks The caller must own the PGM lock.
3253 */
3254static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3255{
3256 /*
3257 * Assert sanity.
3258 */
3259 Assert(PGMIsLockOwner(pVM));
3260 if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3261 && PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3262 {
3263 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3264 return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3265 }
3266
3267 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO)
3268 return VINF_SUCCESS;
3269
3270 const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3271 Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3272 if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3273 || idPage > GMM_PAGEID_LAST
3274 || PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3275 {
3276 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3277 return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3278 }
3279
3280 /* update page count stats. */
3281 if (PGM_PAGE_IS_SHARED(pPage))
3282 pVM->pgm.s.cSharedPages--;
3283 else
3284 pVM->pgm.s.cPrivatePages--;
3285 pVM->pgm.s.cZeroPages++;
3286
3287 /* Deal with write monitored pages. */
3288 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
3289 {
3290 PGM_PAGE_SET_WRITTEN_TO(pPage);
3291 pVM->pgm.s.cWrittenToPages++;
3292 }
3293
3294 /*
3295 * pPage = ZERO page.
3296 */
3297 PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3298 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3299 PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3300
3301 /* Flush physical page map TLB entry. */
3302 PGMPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
3303
3304 /*
3305 * Make sure it's not in the handy page array.
3306 */
3307 for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3308 {
3309 if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3310 {
3311 pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3312 break;
3313 }
3314 if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3315 {
3316 pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3317 break;
3318 }
3319 }
3320
3321 /*
3322 * Push it onto the page array.
3323 */
3324 uint32_t iPage = *pcPendingPages;
3325 Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3326 *pcPendingPages += 1;
3327
3328 pReq->aPages[iPage].idPage = idPage;
3329
3330 if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3331 return VINF_SUCCESS;
3332
3333 /*
3334 * Flush the pages.
3335 */
3336 int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3337 if (RT_SUCCESS(rc))
3338 {
3339 GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3340 *pcPendingPages = 0;
3341 }
3342 return rc;
3343}
3344
3345
3346/**
3347 * Converts a GC physical address to a HC ring-3 pointer, with some
3348 * additional checks.
3349 *
3350 * @returns VBox status code.
3351 * @retval VINF_SUCCESS on success.
3352 * @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3353 * access handler of some kind.
3354 * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3355 * accesses or is odd in any way.
3356 * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3357 *
3358 * @param pVM The VM handle.
3359 * @param GCPhys The GC physical address to convert.
3360 * @param fWritable Whether write access is required.
3361 * @param ppv Where to store the pointer corresponding to GCPhys on
3362 * success.
3363 */
3364VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3365{
3366 pgmLock(pVM);
3367
3368 PPGMRAMRANGE pRam;
3369 PPGMPAGE pPage;
3370 int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3371 if (RT_SUCCESS(rc))
3372 {
3373 if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3374 rc = VINF_SUCCESS;
3375 else
3376 {
3377 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3378 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3379 else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3380 {
3381 /** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3382 * in -norawr0 mode. */
3383 if (fWritable)
3384 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3385 }
3386 else
3387 {
3388 /* Temporarily disabled physical handler(s), since the recompiler
3389 doesn't get notified when it's reset we'll have to pretend it's
3390 operating normally. */
3391 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3392 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3393 else
3394 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3395 }
3396 }
3397 if (RT_SUCCESS(rc))
3398 {
3399 int rc2;
3400
3401 /* Make sure what we return is writable. */
3402 if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3403 switch (PGM_PAGE_GET_STATE(pPage))
3404 {
3405 case PGM_PAGE_STATE_ALLOCATED:
3406 break;
3407 case PGM_PAGE_STATE_ZERO:
3408 case PGM_PAGE_STATE_SHARED:
3409 case PGM_PAGE_STATE_WRITE_MONITORED:
3410 rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3411 AssertLogRelRCReturn(rc2, rc2);
3412 break;
3413 }
3414
3415 /* Get a ring-3 mapping of the address. */
3416 PPGMPAGER3MAPTLBE pTlbe;
3417 rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3418 AssertLogRelRCReturn(rc2, rc2);
3419 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
3420 /** @todo mapping/locking hell; this isn't horribly efficient since
3421 * pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
3422
3423 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] *ppv=%p\n", GCPhys, rc, pPage, *ppv));
3424 }
3425 else
3426 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3427
3428 /* else: handler catching all access, no pointer returned. */
3429 }
3430 else
3431 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3432
3433 pgmUnlock(pVM);
3434 return rc;
3435}
3436
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