VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 27053

Last change on this file since 27053 was 27042, checked in by vboxsync, 15 years ago

Do not replace pages part of a 2 MB continuous range with zero pages, but zero them instead.

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1/* $Id: PGMPhys.cpp 27042 2010-03-04 15:14:29Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM_PHYS
27#include <VBox/pgm.h>
28#include <VBox/iom.h>
29#include <VBox/mm.h>
30#include <VBox/stam.h>
31#include <VBox/rem.h>
32#include <VBox/pdmdev.h>
33#include "PGMInternal.h"
34#include <VBox/vm.h>
35#include "PGMInline.h"
36#include <VBox/sup.h>
37#include <VBox/param.h>
38#include <VBox/err.h>
39#include <VBox/log.h>
40#include <iprt/assert.h>
41#include <iprt/alloc.h>
42#include <iprt/asm.h>
43#include <iprt/thread.h>
44#include <iprt/string.h>
45
46
47/*******************************************************************************
48* Defined Constants And Macros *
49*******************************************************************************/
50/** The number of pages to free in one batch. */
51#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
52
53
54/*******************************************************************************
55* Internal Functions *
56*******************************************************************************/
57static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
58static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
59
60
61/*
62 * PGMR3PhysReadU8-64
63 * PGMR3PhysWriteU8-64
64 */
65#define PGMPHYSFN_READNAME PGMR3PhysReadU8
66#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
67#define PGMPHYS_DATASIZE 1
68#define PGMPHYS_DATATYPE uint8_t
69#include "PGMPhysRWTmpl.h"
70
71#define PGMPHYSFN_READNAME PGMR3PhysReadU16
72#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
73#define PGMPHYS_DATASIZE 2
74#define PGMPHYS_DATATYPE uint16_t
75#include "PGMPhysRWTmpl.h"
76
77#define PGMPHYSFN_READNAME PGMR3PhysReadU32
78#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
79#define PGMPHYS_DATASIZE 4
80#define PGMPHYS_DATATYPE uint32_t
81#include "PGMPhysRWTmpl.h"
82
83#define PGMPHYSFN_READNAME PGMR3PhysReadU64
84#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
85#define PGMPHYS_DATASIZE 8
86#define PGMPHYS_DATATYPE uint64_t
87#include "PGMPhysRWTmpl.h"
88
89
90/**
91 * EMT worker for PGMR3PhysReadExternal.
92 */
93static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
94{
95 PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
96 return VINF_SUCCESS;
97}
98
99
100/**
101 * Write to physical memory, external users.
102 *
103 * @returns VBox status code.
104 * @retval VINF_SUCCESS.
105 *
106 * @param pVM VM Handle.
107 * @param GCPhys Physical address to write to.
108 * @param pvBuf What to write.
109 * @param cbWrite How many bytes to write.
110 *
111 * @thread Any but EMTs.
112 */
113VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
114{
115 VM_ASSERT_OTHER_THREAD(pVM);
116
117 AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
118 LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
119
120 pgmLock(pVM);
121
122 /*
123 * Copy loop on ram ranges.
124 */
125 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
126 for (;;)
127 {
128 /* Find range. */
129 while (pRam && GCPhys > pRam->GCPhysLast)
130 pRam = pRam->CTX_SUFF(pNext);
131 /* Inside range or not? */
132 if (pRam && GCPhys >= pRam->GCPhys)
133 {
134 /*
135 * Must work our way thru this page by page.
136 */
137 RTGCPHYS off = GCPhys - pRam->GCPhys;
138 while (off < pRam->cb)
139 {
140 unsigned iPage = off >> PAGE_SHIFT;
141 PPGMPAGE pPage = &pRam->aPages[iPage];
142
143 /*
144 * If the page has an ALL access handler, we'll have to
145 * delegate the job to EMT.
146 */
147 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
148 {
149 pgmUnlock(pVM);
150
151 return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 4,
152 pVM, &GCPhys, pvBuf, cbRead);
153 }
154 Assert(!PGM_PAGE_IS_MMIO(pPage));
155
156 /*
157 * Simple stuff, go ahead.
158 */
159 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
160 if (cb > cbRead)
161 cb = cbRead;
162 const void *pvSrc;
163 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
164 if (RT_SUCCESS(rc))
165 memcpy(pvBuf, pvSrc, cb);
166 else
167 {
168 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
169 pRam->GCPhys + off, pPage, rc));
170 memset(pvBuf, 0xff, cb);
171 }
172
173 /* next page */
174 if (cb >= cbRead)
175 {
176 pgmUnlock(pVM);
177 return VINF_SUCCESS;
178 }
179 cbRead -= cb;
180 off += cb;
181 GCPhys += cb;
182 pvBuf = (char *)pvBuf + cb;
183 } /* walk pages in ram range. */
184 }
185 else
186 {
187 LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
188
189 /*
190 * Unassigned address space.
191 */
192 if (!pRam)
193 break;
194 size_t cb = pRam->GCPhys - GCPhys;
195 if (cb >= cbRead)
196 {
197 memset(pvBuf, 0xff, cbRead);
198 break;
199 }
200 memset(pvBuf, 0xff, cb);
201
202 cbRead -= cb;
203 pvBuf = (char *)pvBuf + cb;
204 GCPhys += cb;
205 }
206 } /* Ram range walk */
207
208 pgmUnlock(pVM);
209
210 return VINF_SUCCESS;
211}
212
213
214/**
215 * EMT worker for PGMR3PhysWriteExternal.
216 */
217static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
218{
219 /** @todo VERR_EM_NO_MEMORY */
220 PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
221 return VINF_SUCCESS;
222}
223
224
225/**
226 * Write to physical memory, external users.
227 *
228 * @returns VBox status code.
229 * @retval VINF_SUCCESS.
230 * @retval VERR_EM_NO_MEMORY.
231 *
232 * @param pVM VM Handle.
233 * @param GCPhys Physical address to write to.
234 * @param pvBuf What to write.
235 * @param cbWrite How many bytes to write.
236 * @param pszWho Who is writing. For tracking down who is writing
237 * after we've saved the state.
238 *
239 * @thread Any but EMTs.
240 */
241VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, const char *pszWho)
242{
243 VM_ASSERT_OTHER_THREAD(pVM);
244
245 AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
246 ("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x pszWho=%s\n",
247 GCPhys, cbWrite, pszWho));
248 AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
249 LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
250
251 pgmLock(pVM);
252
253 /*
254 * Copy loop on ram ranges, stop when we hit something difficult.
255 */
256 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
257 for (;;)
258 {
259 /* Find range. */
260 while (pRam && GCPhys > pRam->GCPhysLast)
261 pRam = pRam->CTX_SUFF(pNext);
262 /* Inside range or not? */
263 if (pRam && GCPhys >= pRam->GCPhys)
264 {
265 /*
266 * Must work our way thru this page by page.
267 */
268 RTGCPTR off = GCPhys - pRam->GCPhys;
269 while (off < pRam->cb)
270 {
271 RTGCPTR iPage = off >> PAGE_SHIFT;
272 PPGMPAGE pPage = &pRam->aPages[iPage];
273
274 /*
275 * Is the page problematic, we have to do the work on the EMT.
276 *
277 * Allocating writable pages and access handlers are
278 * problematic, write monitored pages are simple and can be
279 * dealth with here.
280 */
281 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
282 || PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
283 {
284 if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
285 && !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
286 pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
287 else
288 {
289 pgmUnlock(pVM);
290
291 return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 4,
292 pVM, &GCPhys, pvBuf, cbWrite);
293 }
294 }
295 Assert(!PGM_PAGE_IS_MMIO(pPage));
296
297 /*
298 * Simple stuff, go ahead.
299 */
300 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
301 if (cb > cbWrite)
302 cb = cbWrite;
303 void *pvDst;
304 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
305 if (RT_SUCCESS(rc))
306 memcpy(pvDst, pvBuf, cb);
307 else
308 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
309 pRam->GCPhys + off, pPage, rc));
310
311 /* next page */
312 if (cb >= cbWrite)
313 {
314 pgmUnlock(pVM);
315 return VINF_SUCCESS;
316 }
317
318 cbWrite -= cb;
319 off += cb;
320 GCPhys += cb;
321 pvBuf = (const char *)pvBuf + cb;
322 } /* walk pages in ram range */
323 }
324 else
325 {
326 /*
327 * Unassigned address space, skip it.
328 */
329 if (!pRam)
330 break;
331 size_t cb = pRam->GCPhys - GCPhys;
332 if (cb >= cbWrite)
333 break;
334 cbWrite -= cb;
335 pvBuf = (const char *)pvBuf + cb;
336 GCPhys += cb;
337 }
338 } /* Ram range walk */
339
340 pgmUnlock(pVM);
341 return VINF_SUCCESS;
342}
343
344
345/**
346 * VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
347 *
348 * @returns see PGMR3PhysGCPhys2CCPtrExternal
349 * @param pVM The VM handle.
350 * @param pGCPhys Pointer to the guest physical address.
351 * @param ppv Where to store the mapping address.
352 * @param pLock Where to store the lock.
353 */
354static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
355{
356 /*
357 * Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
358 * an access handler after it succeeds.
359 */
360 int rc = pgmLock(pVM);
361 AssertRCReturn(rc, rc);
362
363 rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
364 if (RT_SUCCESS(rc))
365 {
366 PPGMPAGEMAPTLBE pTlbe;
367 int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
368 AssertFatalRC(rc2);
369 PPGMPAGE pPage = pTlbe->pPage;
370 if (PGM_PAGE_IS_MMIO(pPage))
371 {
372 PGMPhysReleasePageMappingLock(pVM, pLock);
373 rc = VERR_PGM_PHYS_PAGE_RESERVED;
374 }
375 else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
376#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
377 || pgmPoolIsDirtyPage(pVM, *pGCPhys)
378#endif
379 )
380 {
381 /* We *must* flush any corresponding pgm pool page here, otherwise we'll
382 * not be informed about writes and keep bogus gst->shw mappings around.
383 */
384 pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
385 Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
386 /** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
387 * active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
388 }
389 }
390
391 pgmUnlock(pVM);
392 return rc;
393}
394
395
396/**
397 * Requests the mapping of a guest page into ring-3, external threads.
398 *
399 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
400 * release it.
401 *
402 * This API will assume your intention is to write to the page, and will
403 * therefore replace shared and zero pages. If you do not intend to modify the
404 * page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
405 *
406 * @returns VBox status code.
407 * @retval VINF_SUCCESS on success.
408 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
409 * backing or if the page has any active access handlers. The caller
410 * must fall back on using PGMR3PhysWriteExternal.
411 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
412 *
413 * @param pVM The VM handle.
414 * @param GCPhys The guest physical address of the page that should be mapped.
415 * @param ppv Where to store the address corresponding to GCPhys.
416 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
417 *
418 * @remark Avoid calling this API from within critical sections (other than the
419 * PGM one) because of the deadlock risk when we have to delegating the
420 * task to an EMT.
421 * @thread Any.
422 */
423VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
424{
425 AssertPtr(ppv);
426 AssertPtr(pLock);
427
428 Assert(VM_IS_EMT(pVM) || !PGMIsLockOwner(pVM));
429
430 int rc = pgmLock(pVM);
431 AssertRCReturn(rc, rc);
432
433 /*
434 * Query the Physical TLB entry for the page (may fail).
435 */
436 PPGMPAGEMAPTLBE pTlbe;
437 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
438 if (RT_SUCCESS(rc))
439 {
440 PPGMPAGE pPage = pTlbe->pPage;
441 if (PGM_PAGE_IS_MMIO(pPage))
442 rc = VERR_PGM_PHYS_PAGE_RESERVED;
443 else
444 {
445 /*
446 * If the page is shared, the zero page, or being write monitored
447 * it must be converted to an page that's writable if possible.
448 * We can only deal with write monitored pages here, the rest have
449 * to be on an EMT.
450 */
451 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
452 || PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
453#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
454 || pgmPoolIsDirtyPage(pVM, GCPhys)
455#endif
456 )
457 {
458 if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
459 && !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
460#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
461 && !pgmPoolIsDirtyPage(pVM, GCPhys)
462#endif
463 )
464 pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
465 else
466 {
467 pgmUnlock(pVM);
468
469 return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
470 pVM, &GCPhys, ppv, pLock);
471 }
472 }
473
474 /*
475 * Now, just perform the locking and calculate the return address.
476 */
477 PPGMPAGEMAP pMap = pTlbe->pMap;
478 if (pMap)
479 pMap->cRefs++;
480
481 unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
482 if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
483 {
484 if (cLocks == 0)
485 pVM->pgm.s.cWriteLockedPages++;
486 PGM_PAGE_INC_WRITE_LOCKS(pPage);
487 }
488 else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
489 {
490 PGM_PAGE_INC_WRITE_LOCKS(pPage);
491 AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
492 if (pMap)
493 pMap->cRefs++; /* Extra ref to prevent it from going away. */
494 }
495
496 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
497 pLock->uPageAndType = (uintptr_t)pPage | PGMPAGEMAPLOCK_TYPE_WRITE;
498 pLock->pvMap = pMap;
499 }
500 }
501
502 pgmUnlock(pVM);
503 return rc;
504}
505
506
507/**
508 * Requests the mapping of a guest page into ring-3, external threads.
509 *
510 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
511 * release it.
512 *
513 * @returns VBox status code.
514 * @retval VINF_SUCCESS on success.
515 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
516 * backing or if the page as an active ALL access handler. The caller
517 * must fall back on using PGMPhysRead.
518 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
519 *
520 * @param pVM The VM handle.
521 * @param GCPhys The guest physical address of the page that should be mapped.
522 * @param ppv Where to store the address corresponding to GCPhys.
523 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
524 *
525 * @remark Avoid calling this API from within critical sections (other than
526 * the PGM one) because of the deadlock risk.
527 * @thread Any.
528 */
529VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
530{
531 int rc = pgmLock(pVM);
532 AssertRCReturn(rc, rc);
533
534 /*
535 * Query the Physical TLB entry for the page (may fail).
536 */
537 PPGMPAGEMAPTLBE pTlbe;
538 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
539 if (RT_SUCCESS(rc))
540 {
541 PPGMPAGE pPage = pTlbe->pPage;
542#if 1
543 /* MMIO pages doesn't have any readable backing. */
544 if (PGM_PAGE_IS_MMIO(pPage))
545 rc = VERR_PGM_PHYS_PAGE_RESERVED;
546#else
547 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
548 rc = VERR_PGM_PHYS_PAGE_RESERVED;
549#endif
550 else
551 {
552 /*
553 * Now, just perform the locking and calculate the return address.
554 */
555 PPGMPAGEMAP pMap = pTlbe->pMap;
556 if (pMap)
557 pMap->cRefs++;
558
559 unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
560 if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
561 {
562 if (cLocks == 0)
563 pVM->pgm.s.cReadLockedPages++;
564 PGM_PAGE_INC_READ_LOCKS(pPage);
565 }
566 else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
567 {
568 PGM_PAGE_INC_READ_LOCKS(pPage);
569 AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
570 if (pMap)
571 pMap->cRefs++; /* Extra ref to prevent it from going away. */
572 }
573
574 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
575 pLock->uPageAndType = (uintptr_t)pPage | PGMPAGEMAPLOCK_TYPE_READ;
576 pLock->pvMap = pMap;
577 }
578 }
579
580 pgmUnlock(pVM);
581 return rc;
582}
583
584
585/**
586 * Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
587 *
588 * Called when anything was relocated.
589 *
590 * @param pVM Pointer to the shared VM structure.
591 */
592void pgmR3PhysRelinkRamRanges(PVM pVM)
593{
594 PPGMRAMRANGE pCur;
595
596#ifdef VBOX_STRICT
597 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
598 {
599 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
600 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
601 Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
602 Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
603 Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
604 Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
605 for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
606 Assert( pCur2 == pCur
607 || strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
608 }
609#endif
610
611 pCur = pVM->pgm.s.pRamRangesR3;
612 if (pCur)
613 {
614 pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
615 pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
616
617 for (; pCur->pNextR3; pCur = pCur->pNextR3)
618 {
619 pCur->pNextR0 = pCur->pNextR3->pSelfR0;
620 pCur->pNextRC = pCur->pNextR3->pSelfRC;
621 }
622
623 Assert(pCur->pNextR0 == NIL_RTR0PTR);
624 Assert(pCur->pNextRC == NIL_RTRCPTR);
625 }
626 else
627 {
628 Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
629 Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
630 }
631 ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
632}
633
634
635/**
636 * Links a new RAM range into the list.
637 *
638 * @param pVM Pointer to the shared VM structure.
639 * @param pNew Pointer to the new list entry.
640 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
641 */
642static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
643{
644 AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
645 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
646 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
647
648 pgmLock(pVM);
649
650 PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
651 pNew->pNextR3 = pRam;
652 pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
653 pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
654
655 if (pPrev)
656 {
657 pPrev->pNextR3 = pNew;
658 pPrev->pNextR0 = pNew->pSelfR0;
659 pPrev->pNextRC = pNew->pSelfRC;
660 }
661 else
662 {
663 pVM->pgm.s.pRamRangesR3 = pNew;
664 pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
665 pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
666 }
667 ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
668 pgmUnlock(pVM);
669}
670
671
672/**
673 * Unlink an existing RAM range from the list.
674 *
675 * @param pVM Pointer to the shared VM structure.
676 * @param pRam Pointer to the new list entry.
677 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
678 */
679static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
680{
681 Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
682 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
683 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
684
685 pgmLock(pVM);
686
687 PPGMRAMRANGE pNext = pRam->pNextR3;
688 if (pPrev)
689 {
690 pPrev->pNextR3 = pNext;
691 pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
692 pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
693 }
694 else
695 {
696 Assert(pVM->pgm.s.pRamRangesR3 == pRam);
697 pVM->pgm.s.pRamRangesR3 = pNext;
698 pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
699 pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
700 }
701 ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
702 pgmUnlock(pVM);
703}
704
705
706/**
707 * Unlink an existing RAM range from the list.
708 *
709 * @param pVM Pointer to the shared VM structure.
710 * @param pRam Pointer to the new list entry.
711 */
712static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
713{
714 pgmLock(pVM);
715
716 /* find prev. */
717 PPGMRAMRANGE pPrev = NULL;
718 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
719 while (pCur != pRam)
720 {
721 pPrev = pCur;
722 pCur = pCur->pNextR3;
723 }
724 AssertFatal(pCur);
725
726 pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
727 pgmUnlock(pVM);
728}
729
730
731/**
732 * Frees a range of pages, replacing them with ZERO pages of the specified type.
733 *
734 * @returns VBox status code.
735 * @param pVM The VM handle.
736 * @param pRam The RAM range in which the pages resides.
737 * @param GCPhys The address of the first page.
738 * @param GCPhysLast The address of the last page.
739 * @param uType The page type to replace then with.
740 */
741static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
742{
743 Assert(PGMIsLockOwner(pVM));
744 uint32_t cPendingPages = 0;
745 PGMMFREEPAGESREQ pReq;
746 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
747 AssertLogRelRCReturn(rc, rc);
748
749 /* Iterate the pages. */
750 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
751 uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
752 while (cPagesLeft-- > 0)
753 {
754 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
755 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
756
757 PGM_PAGE_SET_TYPE(pPageDst, uType);
758
759 GCPhys += PAGE_SIZE;
760 pPageDst++;
761 }
762
763 if (cPendingPages)
764 {
765 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
766 AssertLogRelRCReturn(rc, rc);
767 }
768 GMMR3FreePagesCleanup(pReq);
769
770 return rc;
771}
772
773/**
774 * Rendezvous callback used by PGMR3PhysFreeRamPages that frees a range of guest physical pages
775 *
776 * This is only called on one of the EMTs while the other ones are waiting for
777 * it to complete this function.
778 *
779 * @returns VINF_SUCCESS (VBox strict status code).
780 * @param pVM The VM handle.
781 * @param pVCpu The VMCPU for the EMT we're being called on. Unused.
782 * @param pvUser User parameter
783 */
784static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysFreeRamPagesRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
785{
786 uintptr_t *paUser = (uintptr_t *)pvUser;
787 unsigned cPages = paUser[0];
788 RTGCPHYS *paPhysPage = (RTGCPHYS *)paUser[1];
789 uint32_t cPendingPages = 0;
790 PGMMFREEPAGESREQ pReq;
791
792 pgmLock(pVM);
793 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
794 if (RT_FAILURE(rc))
795 {
796 pgmUnlock(pVM);
797 AssertLogRelRC(rc);
798 return rc;
799 }
800
801 /* Iterate the pages. */
802 for (unsigned i = 0; i < cPages; i++)
803 {
804 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
805 if ( pPage == NULL
806 || pPage->uTypeY != PGMPAGETYPE_RAM)
807 {
808 Log(("PGMR3PhysFreePageRange: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], (pPage) ? pPage->uTypeY : 0));
809 break;
810 }
811
812 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i]);
813 if (RT_FAILURE(rc))
814 {
815 pgmUnlock(pVM);
816 AssertLogRelRC(rc);
817 return rc;
818 }
819 }
820
821 if (cPendingPages)
822 {
823 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
824 if (RT_FAILURE(rc))
825 {
826 pgmUnlock(pVM);
827 AssertLogRelRC(rc);
828 return rc;
829 }
830 }
831 GMMR3FreePagesCleanup(pReq);
832
833 /* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
834 pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
835
836 pgmUnlock(pVM);
837 return rc;
838}
839
840/**
841 * Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
842 *
843 * @returns VBox status code.
844 * @param pVM The VM handle.
845 * @param cPages Number of pages to free
846 * @param paPhysPage Array of guest physical addresses
847 */
848static DECLCALLBACK(void) pgmR3PhysFreeRamPagesHelper(PVM pVM, unsigned cPages, RTGCPHYS *paPhysPage)
849{
850 uintptr_t paUser[2];
851
852 paUser[0] = cPages;
853 paUser[1] = (uintptr_t)paPhysPage;
854 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysFreeRamPagesRendezvous, (void *)paUser);
855 AssertRC(rc);
856
857 /* Made a copy in PGMR3PhysFreeRamPages; free it here. */
858 RTMemFree(paPhysPage);
859}
860
861/**
862 * Frees a range of ram pages, replacing them with ZERO pages
863 *
864 * @returns VBox status code.
865 * @param pVM The VM handle.
866 * @param cPages Number of pages to free
867 * @param paPhysPage Array of guest physical addresses
868 */
869VMMR3DECL(int) PGMR3PhysFreeRamPages(PVM pVM, unsigned cPages, RTGCPHYS *paPhysPage)
870{
871 int rc;
872
873 /* Currently only used by the VMM device in responds to a balloon request. */
874
875 /* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
876 * In the SMP case we post a request packet to postpone the job.
877 */
878 if (pVM->cCpus > 1)
879 {
880 unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
881 RTGCPHYS *paPhysPageCopy = (RTGCPHYS *)RTMemAlloc(cbPhysPage);
882 AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
883
884 memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
885
886 rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysFreeRamPagesHelper, 3, pVM, cPages, paPhysPageCopy);
887 AssertRC(rc);
888 }
889 else
890 {
891 uintptr_t paUser[2];
892
893 paUser[0] = cPages;
894 paUser[1] = (uintptr_t)paPhysPage;
895 rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysFreeRamPagesRendezvous, (void *)paUser);
896 AssertRC(rc);
897 }
898 return rc;
899}
900
901
902/**
903 * PGMR3PhysRegisterRam worker that initializes and links a RAM range.
904 *
905 * @param pVM The VM handle.
906 * @param pNew The new RAM range.
907 * @param GCPhys The address of the RAM range.
908 * @param GCPhysLast The last address of the RAM range.
909 * @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
910 * if in HMA.
911 * @param R0PtrNew Ditto for R0.
912 * @param pszDesc The description.
913 * @param pPrev The previous RAM range (for linking).
914 */
915static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
916 RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
917{
918 /*
919 * Initialize the range.
920 */
921 pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
922 pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
923 pNew->GCPhys = GCPhys;
924 pNew->GCPhysLast = GCPhysLast;
925 pNew->cb = GCPhysLast - GCPhys + 1;
926 pNew->pszDesc = pszDesc;
927 pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
928 pNew->pvR3 = NULL;
929 pNew->paLSPages = NULL;
930
931 uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
932 RTGCPHYS iPage = cPages;
933 while (iPage-- > 0)
934 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
935
936 /* Update the page count stats. */
937 pVM->pgm.s.cZeroPages += cPages;
938 pVM->pgm.s.cAllPages += cPages;
939
940 /*
941 * Link it.
942 */
943 pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
944}
945
946
947/**
948 * Relocate a floating RAM range.
949 *
950 * @copydoc FNPGMRELOCATE.
951 */
952static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
953{
954 PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
955 Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
956 Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
957
958 switch (enmMode)
959 {
960 case PGMRELOCATECALL_SUGGEST:
961 return true;
962 case PGMRELOCATECALL_RELOCATE:
963 {
964 /* Update myself and then relink all the ranges. */
965 pgmLock(pVM);
966 pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
967 pgmR3PhysRelinkRamRanges(pVM);
968 pgmUnlock(pVM);
969 return true;
970 }
971
972 default:
973 AssertFailedReturn(false);
974 }
975}
976
977
978/**
979 * PGMR3PhysRegisterRam worker that registers a high chunk.
980 *
981 * @returns VBox status code.
982 * @param pVM The VM handle.
983 * @param GCPhys The address of the RAM.
984 * @param cRamPages The number of RAM pages to register.
985 * @param cbChunk The size of the PGMRAMRANGE guest mapping.
986 * @param iChunk The chunk number.
987 * @param pszDesc The RAM range description.
988 * @param ppPrev Previous RAM range pointer. In/Out.
989 */
990static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
991 uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
992 PPGMRAMRANGE *ppPrev)
993{
994 const char *pszDescChunk = iChunk == 0
995 ? pszDesc
996 : MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
997 AssertReturn(pszDescChunk, VERR_NO_MEMORY);
998
999 /*
1000 * Allocate memory for the new chunk.
1001 */
1002 size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1003 PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1004 AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1005 RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1006 void *pvChunk = NULL;
1007 int rc = SUPR3PageAllocEx(cChunkPages, 0 /*fFlags*/, &pvChunk,
1008#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1009 VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
1010#else
1011 NULL,
1012#endif
1013 paChunkPages);
1014 if (RT_SUCCESS(rc))
1015 {
1016#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1017 if (!VMMIsHwVirtExtForced(pVM))
1018 R0PtrChunk = NIL_RTR0PTR;
1019#else
1020 R0PtrChunk = (uintptr_t)pvChunk;
1021#endif
1022 memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1023
1024 PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1025
1026 /*
1027 * Create a mapping and map the pages into it.
1028 * We push these in below the HMA.
1029 */
1030 RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1031 rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /*fFlags*/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1032 if (RT_SUCCESS(rc))
1033 {
1034 pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1035
1036 RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1037 RTGCPTR GCPtrPage = GCPtrChunk;
1038 for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1039 rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1040 if (RT_SUCCESS(rc))
1041 {
1042 /*
1043 * Ok, init and link the range.
1044 */
1045 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1046 (RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1047 *ppPrev = pNew;
1048 }
1049 }
1050
1051 if (RT_FAILURE(rc))
1052 SUPR3PageFreeEx(pvChunk, cChunkPages);
1053 }
1054
1055 RTMemTmpFree(paChunkPages);
1056 return rc;
1057}
1058
1059
1060/**
1061 * Sets up a range RAM.
1062 *
1063 * This will check for conflicting registrations, make a resource
1064 * reservation for the memory (with GMM), and setup the per-page
1065 * tracking structures (PGMPAGE).
1066 *
1067 * @returns VBox stutus code.
1068 * @param pVM Pointer to the shared VM structure.
1069 * @param GCPhys The physical address of the RAM.
1070 * @param cb The size of the RAM.
1071 * @param pszDesc The description - not copied, so, don't free or change it.
1072 */
1073VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1074{
1075 /*
1076 * Validate input.
1077 */
1078 Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1079 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1080 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1081 AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1082 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1083 AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1084 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1085 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1086
1087 pgmLock(pVM);
1088
1089 /*
1090 * Find range location and check for conflicts.
1091 * (We don't lock here because the locking by EMT is only required on update.)
1092 */
1093 PPGMRAMRANGE pPrev = NULL;
1094 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1095 while (pRam && GCPhysLast >= pRam->GCPhys)
1096 {
1097 if ( GCPhysLast >= pRam->GCPhys
1098 && GCPhys <= pRam->GCPhysLast)
1099 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1100 GCPhys, GCPhysLast, pszDesc,
1101 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1102 VERR_PGM_RAM_CONFLICT);
1103
1104 /* next */
1105 pPrev = pRam;
1106 pRam = pRam->pNextR3;
1107 }
1108
1109 /*
1110 * Register it with GMM (the API bitches).
1111 */
1112 const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1113 int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1114 if (RT_FAILURE(rc))
1115 {
1116 pgmUnlock(pVM);
1117 return rc;
1118 }
1119
1120 if ( GCPhys >= _4G
1121 && cPages > 256)
1122 {
1123 /*
1124 * The PGMRAMRANGE structures for the high memory can get very big.
1125 * In order to avoid SUPR3PageAllocEx allocation failures due to the
1126 * allocation size limit there and also to avoid being unable to find
1127 * guest mapping space for them, we split this memory up into 4MB in
1128 * (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1129 * mode.
1130 *
1131 * The first and last page of each mapping are guard pages and marked
1132 * not-present. So, we've got 4186112 and 16769024 bytes available for
1133 * the PGMRAMRANGE structure.
1134 *
1135 * Note! The sizes used here will influence the saved state.
1136 */
1137 uint32_t cbChunk;
1138 uint32_t cPagesPerChunk;
1139 if (VMMIsHwVirtExtForced(pVM))
1140 {
1141 cbChunk = 16U*_1M;
1142 cPagesPerChunk = 1048048; /* max ~1048059 */
1143 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U*_1M - PAGE_SIZE * 2);
1144 }
1145 else
1146 {
1147 cbChunk = 4U*_1M;
1148 cPagesPerChunk = 261616; /* max ~261627 */
1149 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U*_1M - PAGE_SIZE * 2);
1150 }
1151 AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1152
1153 RTGCPHYS cPagesLeft = cPages;
1154 RTGCPHYS GCPhysChunk = GCPhys;
1155 uint32_t iChunk = 0;
1156 while (cPagesLeft > 0)
1157 {
1158 uint32_t cPagesInChunk = cPagesLeft;
1159 if (cPagesInChunk > cPagesPerChunk)
1160 cPagesInChunk = cPagesPerChunk;
1161
1162 rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1163 AssertRCReturn(rc, rc);
1164
1165 /* advance */
1166 GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1167 cPagesLeft -= cPagesInChunk;
1168 iChunk++;
1169 }
1170 }
1171 else
1172 {
1173 /*
1174 * Allocate, initialize and link the new RAM range.
1175 */
1176 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1177 PPGMRAMRANGE pNew;
1178 rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1179 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1180
1181 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1182 }
1183 PGMPhysInvalidatePageMapTLB(pVM);
1184 pgmUnlock(pVM);
1185
1186 /*
1187 * Notify REM.
1188 */
1189 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1190
1191 return VINF_SUCCESS;
1192}
1193
1194
1195/**
1196 * Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1197 *
1198 * We do this late in the init process so that all the ROM and MMIO ranges have
1199 * been registered already and we don't go wasting memory on them.
1200 *
1201 * @returns VBox status code.
1202 *
1203 * @param pVM Pointer to the shared VM structure.
1204 */
1205int pgmR3PhysRamPreAllocate(PVM pVM)
1206{
1207 Assert(pVM->pgm.s.fRamPreAlloc);
1208 Log(("pgmR3PhysRamPreAllocate: enter\n"));
1209
1210 /*
1211 * Walk the RAM ranges and allocate all RAM pages, halt at
1212 * the first allocation error.
1213 */
1214 uint64_t cPages = 0;
1215 uint64_t NanoTS = RTTimeNanoTS();
1216 pgmLock(pVM);
1217 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1218 {
1219 PPGMPAGE pPage = &pRam->aPages[0];
1220 RTGCPHYS GCPhys = pRam->GCPhys;
1221 uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1222 while (cLeft-- > 0)
1223 {
1224 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1225 {
1226 switch (PGM_PAGE_GET_STATE(pPage))
1227 {
1228 case PGM_PAGE_STATE_ZERO:
1229 {
1230 int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1231 if (RT_FAILURE(rc))
1232 {
1233 LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1234 pgmUnlock(pVM);
1235 return rc;
1236 }
1237 cPages++;
1238 break;
1239 }
1240
1241 case PGM_PAGE_STATE_ALLOCATED:
1242 case PGM_PAGE_STATE_WRITE_MONITORED:
1243 case PGM_PAGE_STATE_SHARED:
1244 /* nothing to do here. */
1245 break;
1246 }
1247 }
1248
1249 /* next */
1250 pPage++;
1251 GCPhys += PAGE_SIZE;
1252 }
1253 }
1254 pgmUnlock(pVM);
1255 NanoTS = RTTimeNanoTS() - NanoTS;
1256
1257 LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1258 Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1259 return VINF_SUCCESS;
1260}
1261
1262
1263/**
1264 * Resets (zeros) the RAM.
1265 *
1266 * ASSUMES that the caller owns the PGM lock.
1267 *
1268 * @returns VBox status code.
1269 * @param pVM Pointer to the shared VM structure.
1270 */
1271int pgmR3PhysRamReset(PVM pVM)
1272{
1273 Assert(PGMIsLockOwner(pVM));
1274
1275 /*
1276 * We batch up pages that should be freed instead of calling GMM for
1277 * each and every one of them.
1278 */
1279 uint32_t cPendingPages = 0;
1280 PGMMFREEPAGESREQ pReq;
1281 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1282 AssertLogRelRCReturn(rc, rc);
1283
1284 /*
1285 * Walk the ram ranges.
1286 */
1287 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1288 {
1289 uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1290 AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1291
1292 if (!pVM->pgm.s.fRamPreAlloc)
1293 {
1294 /* Replace all RAM pages by ZERO pages. */
1295 while (iPage-- > 0)
1296 {
1297 PPGMPAGE pPage = &pRam->aPages[iPage];
1298 switch (PGM_PAGE_GET_TYPE(pPage))
1299 {
1300 case PGMPAGETYPE_RAM:
1301 /* Do not replace pages part of a 2 MB continuous range with zero pages, but zero them instead. */
1302 if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
1303 {
1304 void *pvPage;
1305 rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1306 AssertLogRelRCReturn(rc, rc);
1307 ASMMemZeroPage(pvPage);
1308 }
1309 else
1310 if (!PGM_PAGE_IS_ZERO(pPage))
1311 {
1312 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1313 AssertLogRelRCReturn(rc, rc);
1314 }
1315 break;
1316
1317 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1318 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1319 break;
1320
1321 case PGMPAGETYPE_MMIO2:
1322 case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1323 case PGMPAGETYPE_ROM:
1324 case PGMPAGETYPE_MMIO:
1325 break;
1326 default:
1327 AssertFailed();
1328 }
1329 } /* for each page */
1330 }
1331 else
1332 {
1333 /* Zero the memory. */
1334 while (iPage-- > 0)
1335 {
1336 PPGMPAGE pPage = &pRam->aPages[iPage];
1337 switch (PGM_PAGE_GET_TYPE(pPage))
1338 {
1339 case PGMPAGETYPE_RAM:
1340 switch (PGM_PAGE_GET_STATE(pPage))
1341 {
1342 case PGM_PAGE_STATE_ZERO:
1343 break;
1344 case PGM_PAGE_STATE_SHARED:
1345 case PGM_PAGE_STATE_WRITE_MONITORED:
1346 rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1347 AssertLogRelRCReturn(rc, rc);
1348 case PGM_PAGE_STATE_ALLOCATED:
1349 {
1350 void *pvPage;
1351 rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1352 AssertLogRelRCReturn(rc, rc);
1353 ASMMemZeroPage(pvPage);
1354 break;
1355 }
1356 }
1357 break;
1358
1359 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1360 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1361 break;
1362
1363 case PGMPAGETYPE_MMIO2:
1364 case PGMPAGETYPE_ROM_SHADOW:
1365 case PGMPAGETYPE_ROM:
1366 case PGMPAGETYPE_MMIO:
1367 break;
1368 default:
1369 AssertFailed();
1370
1371 }
1372 } /* for each page */
1373 }
1374
1375 }
1376
1377 /*
1378 * Finish off any pages pending freeing.
1379 */
1380 if (cPendingPages)
1381 {
1382 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1383 AssertLogRelRCReturn(rc, rc);
1384 }
1385 GMMR3FreePagesCleanup(pReq);
1386
1387 return VINF_SUCCESS;
1388}
1389
1390
1391/**
1392 * This is the interface IOM is using to register an MMIO region.
1393 *
1394 * It will check for conflicts and ensure that a RAM range structure
1395 * is present before calling the PGMR3HandlerPhysicalRegister API to
1396 * register the callbacks.
1397 *
1398 * @returns VBox status code.
1399 *
1400 * @param pVM Pointer to the shared VM structure.
1401 * @param GCPhys The start of the MMIO region.
1402 * @param cb The size of the MMIO region.
1403 * @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1404 * @param pvUserR3 The user argument for R3.
1405 * @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1406 * @param pvUserR0 The user argument for R0.
1407 * @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1408 * @param pvUserRC The user argument for RC.
1409 * @param pszDesc The description of the MMIO region.
1410 */
1411VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1412 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1413 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1414 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1415 R3PTRTYPE(const char *) pszDesc)
1416{
1417 /*
1418 * Assert on some assumption.
1419 */
1420 VM_ASSERT_EMT(pVM);
1421 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1422 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1423 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1424 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1425
1426 /*
1427 * Make sure there's a RAM range structure for the region.
1428 */
1429 int rc;
1430 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1431 bool fRamExists = false;
1432 PPGMRAMRANGE pRamPrev = NULL;
1433 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1434 while (pRam && GCPhysLast >= pRam->GCPhys)
1435 {
1436 if ( GCPhysLast >= pRam->GCPhys
1437 && GCPhys <= pRam->GCPhysLast)
1438 {
1439 /* Simplification: all within the same range. */
1440 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1441 && GCPhysLast <= pRam->GCPhysLast,
1442 ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1443 GCPhys, GCPhysLast, pszDesc,
1444 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1445 VERR_PGM_RAM_CONFLICT);
1446
1447 /* Check that it's all RAM or MMIO pages. */
1448 PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1449 uint32_t cLeft = cb >> PAGE_SHIFT;
1450 while (cLeft-- > 0)
1451 {
1452 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1453 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1454 ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1455 GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1456 VERR_PGM_RAM_CONFLICT);
1457 pPage++;
1458 }
1459
1460 /* Looks good. */
1461 fRamExists = true;
1462 break;
1463 }
1464
1465 /* next */
1466 pRamPrev = pRam;
1467 pRam = pRam->pNextR3;
1468 }
1469 PPGMRAMRANGE pNew;
1470 if (fRamExists)
1471 {
1472 pNew = NULL;
1473
1474 /*
1475 * Make all the pages in the range MMIO/ZERO pages, freeing any
1476 * RAM pages currently mapped here. This might not be 100% correct
1477 * for PCI memory, but we're doing the same thing for MMIO2 pages.
1478 */
1479 rc = pgmLock(pVM);
1480 if (RT_SUCCESS(rc))
1481 {
1482 rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1483 pgmUnlock(pVM);
1484 }
1485 AssertRCReturn(rc, rc);
1486 }
1487 else
1488 {
1489 pgmLock(pVM);
1490
1491 /*
1492 * No RAM range, insert an ad hoc one.
1493 *
1494 * Note that we don't have to tell REM about this range because
1495 * PGMHandlerPhysicalRegisterEx will do that for us.
1496 */
1497 Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1498
1499 const uint32_t cPages = cb >> PAGE_SHIFT;
1500 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1501 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1502 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1503
1504 /* Initialize the range. */
1505 pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1506 pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1507 pNew->GCPhys = GCPhys;
1508 pNew->GCPhysLast = GCPhysLast;
1509 pNew->cb = cb;
1510 pNew->pszDesc = pszDesc;
1511 pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
1512 pNew->pvR3 = NULL;
1513 pNew->paLSPages = NULL;
1514
1515 uint32_t iPage = cPages;
1516 while (iPage-- > 0)
1517 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1518 Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1519
1520 /* update the page count stats. */
1521 pVM->pgm.s.cPureMmioPages += cPages;
1522 pVM->pgm.s.cAllPages += cPages;
1523
1524 /* link it */
1525 pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1526
1527 pgmUnlock(pVM);
1528 }
1529
1530 /*
1531 * Register the access handler.
1532 */
1533 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1534 pfnHandlerR3, pvUserR3,
1535 pfnHandlerR0, pvUserR0,
1536 pfnHandlerRC, pvUserRC, pszDesc);
1537 if ( RT_FAILURE(rc)
1538 && !fRamExists)
1539 {
1540 pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
1541 pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1542
1543 /* remove the ad hoc range. */
1544 pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1545 pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1546 MMHyperFree(pVM, pRam);
1547 }
1548 PGMPhysInvalidatePageMapTLB(pVM);
1549
1550 return rc;
1551}
1552
1553
1554/**
1555 * This is the interface IOM is using to register an MMIO region.
1556 *
1557 * It will take care of calling PGMHandlerPhysicalDeregister and clean up
1558 * any ad hoc PGMRAMRANGE left behind.
1559 *
1560 * @returns VBox status code.
1561 * @param pVM Pointer to the shared VM structure.
1562 * @param GCPhys The start of the MMIO region.
1563 * @param cb The size of the MMIO region.
1564 */
1565VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1566{
1567 VM_ASSERT_EMT(pVM);
1568
1569 /*
1570 * First deregister the handler, then check if we should remove the ram range.
1571 */
1572 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1573 if (RT_SUCCESS(rc))
1574 {
1575 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1576 PPGMRAMRANGE pRamPrev = NULL;
1577 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1578 while (pRam && GCPhysLast >= pRam->GCPhys)
1579 {
1580 /** @todo We're being a bit too careful here. rewrite. */
1581 if ( GCPhysLast == pRam->GCPhysLast
1582 && GCPhys == pRam->GCPhys)
1583 {
1584 Assert(pRam->cb == cb);
1585
1586 /*
1587 * See if all the pages are dead MMIO pages.
1588 */
1589 uint32_t const cPages = cb >> PAGE_SHIFT;
1590 bool fAllMMIO = true;
1591 uint32_t iPage = 0;
1592 uint32_t cLeft = cPages;
1593 while (cLeft-- > 0)
1594 {
1595 PPGMPAGE pPage = &pRam->aPages[iPage];
1596 if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1597 /*|| not-out-of-action later */)
1598 {
1599 fAllMMIO = false;
1600 Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1601 AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1602 break;
1603 }
1604 Assert(PGM_PAGE_IS_ZERO(pPage));
1605 pPage++;
1606 }
1607 if (fAllMMIO)
1608 {
1609 /*
1610 * Ad-hoc range, unlink and free it.
1611 */
1612 Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
1613 GCPhys, GCPhysLast, pRam->pszDesc));
1614
1615 pVM->pgm.s.cAllPages -= cPages;
1616 pVM->pgm.s.cPureMmioPages -= cPages;
1617
1618 pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1619 pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1620 MMHyperFree(pVM, pRam);
1621 break;
1622 }
1623 }
1624
1625 /*
1626 * Range match? It will all be within one range (see PGMAllHandler.cpp).
1627 */
1628 if ( GCPhysLast >= pRam->GCPhys
1629 && GCPhys <= pRam->GCPhysLast)
1630 {
1631 Assert(GCPhys >= pRam->GCPhys);
1632 Assert(GCPhysLast <= pRam->GCPhysLast);
1633
1634 /*
1635 * Turn the pages back into RAM pages.
1636 */
1637 uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1638 uint32_t cLeft = cb >> PAGE_SHIFT;
1639 while (cLeft--)
1640 {
1641 PPGMPAGE pPage = &pRam->aPages[iPage];
1642 AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1643 AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1644 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1645 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1646 }
1647 break;
1648 }
1649
1650 /* next */
1651 pRamPrev = pRam;
1652 pRam = pRam->pNextR3;
1653 }
1654 }
1655
1656 PGMPhysInvalidatePageMapTLB(pVM);
1657 return rc;
1658}
1659
1660
1661/**
1662 * Locate a MMIO2 range.
1663 *
1664 * @returns Pointer to the MMIO2 range.
1665 * @param pVM Pointer to the shared VM structure.
1666 * @param pDevIns The device instance owning the region.
1667 * @param iRegion The region.
1668 */
1669DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1670{
1671 /*
1672 * Search the list.
1673 */
1674 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1675 if ( pCur->pDevInsR3 == pDevIns
1676 && pCur->iRegion == iRegion)
1677 return pCur;
1678 return NULL;
1679}
1680
1681
1682/**
1683 * Allocate and register an MMIO2 region.
1684 *
1685 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1686 * RAM associated with a device. It is also non-shared memory with a
1687 * permanent ring-3 mapping and page backing (presently).
1688 *
1689 * A MMIO2 range may overlap with base memory if a lot of RAM
1690 * is configured for the VM, in which case we'll drop the base
1691 * memory pages. Presently we will make no attempt to preserve
1692 * anything that happens to be present in the base memory that
1693 * is replaced, this is of course incorrectly but it's too much
1694 * effort.
1695 *
1696 * @returns VBox status code.
1697 * @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1698 * @retval VERR_ALREADY_EXISTS if the region already exists.
1699 *
1700 * @param pVM Pointer to the shared VM structure.
1701 * @param pDevIns The device instance owning the region.
1702 * @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1703 * this number has to be the number of that region. Otherwise
1704 * it can be any number safe UINT8_MAX.
1705 * @param cb The size of the region. Must be page aligned.
1706 * @param fFlags Reserved for future use, must be zero.
1707 * @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1708 * @param pszDesc The description.
1709 */
1710VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)
1711{
1712 /*
1713 * Validate input.
1714 */
1715 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1716 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1717 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1718 AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1719 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1720 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1721 AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1722 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1723 AssertReturn(cb, VERR_INVALID_PARAMETER);
1724 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1725
1726 const uint32_t cPages = cb >> PAGE_SHIFT;
1727 AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1728 AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1729
1730 /*
1731 * For the 2nd+ instance, mangle the description string so it's unique.
1732 */
1733 if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
1734 {
1735 pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1736 if (!pszDesc)
1737 return VERR_NO_MEMORY;
1738 }
1739
1740 /*
1741 * Try reserve and allocate the backing memory first as this is what is
1742 * most likely to fail.
1743 */
1744 int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1745 if (RT_SUCCESS(rc))
1746 {
1747 void *pvPages;
1748 PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1749 if (RT_SUCCESS(rc))
1750 rc = SUPR3PageAllocEx(cPages, 0 /*fFlags*/, &pvPages, NULL /*pR0Ptr*/, paPages);
1751 if (RT_SUCCESS(rc))
1752 {
1753 memset(pvPages, 0, cPages * PAGE_SIZE);
1754
1755 /*
1756 * Create the MMIO2 range record for it.
1757 */
1758 const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1759 PPGMMMIO2RANGE pNew;
1760 rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1761 AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1762 if (RT_SUCCESS(rc))
1763 {
1764 pNew->pDevInsR3 = pDevIns;
1765 pNew->pvR3 = pvPages;
1766 //pNew->pNext = NULL;
1767 //pNew->fMapped = false;
1768 //pNew->fOverlapping = false;
1769 pNew->iRegion = iRegion;
1770 pNew->idSavedState = UINT8_MAX;
1771 pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1772 pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1773 pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1774 pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1775 pNew->RamRange.pszDesc = pszDesc;
1776 pNew->RamRange.cb = cb;
1777 pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
1778 pNew->RamRange.pvR3 = pvPages;
1779 //pNew->RamRange.paLSPages = NULL;
1780
1781 uint32_t iPage = cPages;
1782 while (iPage-- > 0)
1783 {
1784 PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1785 paPages[iPage].Phys, NIL_GMM_PAGEID,
1786 PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1787 }
1788
1789 /* update page count stats */
1790 pVM->pgm.s.cAllPages += cPages;
1791 pVM->pgm.s.cPrivatePages += cPages;
1792
1793 /*
1794 * Link it into the list.
1795 * Since there is no particular order, just push it.
1796 */
1797 pgmLock(pVM);
1798 pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1799 pVM->pgm.s.pMmio2RangesR3 = pNew;
1800 pgmUnlock(pVM);
1801
1802 *ppv = pvPages;
1803 RTMemTmpFree(paPages);
1804 PGMPhysInvalidatePageMapTLB(pVM);
1805 return VINF_SUCCESS;
1806 }
1807
1808 SUPR3PageFreeEx(pvPages, cPages);
1809 }
1810 RTMemTmpFree(paPages);
1811 MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1812 }
1813 if (pDevIns->iInstance > 0)
1814 MMR3HeapFree((void *)pszDesc);
1815 return rc;
1816}
1817
1818
1819/**
1820 * Deregisters and frees an MMIO2 region.
1821 *
1822 * Any physical (and virtual) access handlers registered for the region must
1823 * be deregistered before calling this function.
1824 *
1825 * @returns VBox status code.
1826 * @param pVM Pointer to the shared VM structure.
1827 * @param pDevIns The device instance owning the region.
1828 * @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1829 */
1830VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1831{
1832 /*
1833 * Validate input.
1834 */
1835 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1836 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1837 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1838
1839 pgmLock(pVM);
1840 int rc = VINF_SUCCESS;
1841 unsigned cFound = 0;
1842 PPGMMMIO2RANGE pPrev = NULL;
1843 PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1844 while (pCur)
1845 {
1846 if ( pCur->pDevInsR3 == pDevIns
1847 && ( iRegion == UINT32_MAX
1848 || pCur->iRegion == iRegion))
1849 {
1850 cFound++;
1851
1852 /*
1853 * Unmap it if it's mapped.
1854 */
1855 if (pCur->fMapped)
1856 {
1857 int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1858 AssertRC(rc2);
1859 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1860 rc = rc2;
1861 }
1862
1863 /*
1864 * Unlink it
1865 */
1866 PPGMMMIO2RANGE pNext = pCur->pNextR3;
1867 if (pPrev)
1868 pPrev->pNextR3 = pNext;
1869 else
1870 pVM->pgm.s.pMmio2RangesR3 = pNext;
1871 pCur->pNextR3 = NULL;
1872
1873 /*
1874 * Free the memory.
1875 */
1876 int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1877 AssertRC(rc2);
1878 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1879 rc = rc2;
1880
1881 uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1882 rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1883 AssertRC(rc2);
1884 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1885 rc = rc2;
1886
1887 /* we're leaking hyper memory here if done at runtime. */
1888#ifdef VBOX_STRICT
1889 VMSTATE const enmState = VMR3GetState(pVM);
1890 AssertMsg( enmState == VMSTATE_POWERING_OFF
1891 || enmState == VMSTATE_POWERING_OFF_LS
1892 || enmState == VMSTATE_OFF
1893 || enmState == VMSTATE_OFF_LS
1894 || enmState == VMSTATE_DESTROYING
1895 || enmState == VMSTATE_TERMINATED
1896 || enmState == VMSTATE_CREATING
1897 , ("%s\n", VMR3GetStateName(enmState)));
1898#endif
1899 /*rc = MMHyperFree(pVM, pCur);
1900 AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1901
1902
1903 /* update page count stats */
1904 pVM->pgm.s.cAllPages -= cPages;
1905 pVM->pgm.s.cPrivatePages -= cPages;
1906
1907 /* next */
1908 pCur = pNext;
1909 }
1910 else
1911 {
1912 pPrev = pCur;
1913 pCur = pCur->pNextR3;
1914 }
1915 }
1916 PGMPhysInvalidatePageMapTLB(pVM);
1917 pgmUnlock(pVM);
1918 return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1919}
1920
1921
1922/**
1923 * Maps a MMIO2 region.
1924 *
1925 * This is done when a guest / the bios / state loading changes the
1926 * PCI config. The replacing of base memory has the same restrictions
1927 * as during registration, of course.
1928 *
1929 * @returns VBox status code.
1930 *
1931 * @param pVM Pointer to the shared VM structure.
1932 * @param pDevIns The
1933 */
1934VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1935{
1936 /*
1937 * Validate input
1938 */
1939 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1940 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1941 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1942 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1943 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1944 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1945
1946 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1947 AssertReturn(pCur, VERR_NOT_FOUND);
1948 AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
1949 Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
1950 Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
1951
1952 const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
1953 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1954
1955 /*
1956 * Find our location in the ram range list, checking for
1957 * restriction we don't bother implementing yet (partially overlapping).
1958 */
1959 bool fRamExists = false;
1960 PPGMRAMRANGE pRamPrev = NULL;
1961 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1962 while (pRam && GCPhysLast >= pRam->GCPhys)
1963 {
1964 if ( GCPhys <= pRam->GCPhysLast
1965 && GCPhysLast >= pRam->GCPhys)
1966 {
1967 /* completely within? */
1968 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1969 && GCPhysLast <= pRam->GCPhysLast,
1970 ("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
1971 GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
1972 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1973 VERR_PGM_RAM_CONFLICT);
1974 fRamExists = true;
1975 break;
1976 }
1977
1978 /* next */
1979 pRamPrev = pRam;
1980 pRam = pRam->pNextR3;
1981 }
1982 if (fRamExists)
1983 {
1984 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1985 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1986 while (cPagesLeft-- > 0)
1987 {
1988 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1989 ("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
1990 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
1991 VERR_PGM_RAM_CONFLICT);
1992 pPage++;
1993 }
1994 }
1995 Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
1996 GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
1997
1998 /*
1999 * Make the changes.
2000 */
2001 pgmLock(pVM);
2002
2003 pCur->RamRange.GCPhys = GCPhys;
2004 pCur->RamRange.GCPhysLast = GCPhysLast;
2005 pCur->fMapped = true;
2006 pCur->fOverlapping = fRamExists;
2007
2008 if (fRamExists)
2009 {
2010/** @todo use pgmR3PhysFreePageRange here. */
2011 uint32_t cPendingPages = 0;
2012 PGMMFREEPAGESREQ pReq;
2013 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2014 AssertLogRelRCReturn(rc, rc);
2015
2016 /* replace the pages, freeing all present RAM pages. */
2017 PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2018 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2019 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2020 while (cPagesLeft-- > 0)
2021 {
2022 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
2023 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
2024
2025 RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
2026 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
2027 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
2028 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
2029
2030 pVM->pgm.s.cZeroPages--;
2031 GCPhys += PAGE_SIZE;
2032 pPageSrc++;
2033 pPageDst++;
2034 }
2035
2036 /* Flush physical page map TLB. */
2037 PGMPhysInvalidatePageMapTLB(pVM);
2038
2039 if (cPendingPages)
2040 {
2041 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2042 AssertLogRelRCReturn(rc, rc);
2043 }
2044 GMMR3FreePagesCleanup(pReq);
2045 pgmUnlock(pVM);
2046 }
2047 else
2048 {
2049 RTGCPHYS cb = pCur->RamRange.cb;
2050
2051 /* link in the ram range */
2052 pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
2053 pgmUnlock(pVM);
2054
2055 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
2056 }
2057
2058 PGMPhysInvalidatePageMapTLB(pVM);
2059 return VINF_SUCCESS;
2060}
2061
2062
2063/**
2064 * Unmaps a MMIO2 region.
2065 *
2066 * This is done when a guest / the bios / state loading changes the
2067 * PCI config. The replacing of base memory has the same restrictions
2068 * as during registration, of course.
2069 */
2070VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2071{
2072 /*
2073 * Validate input
2074 */
2075 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2076 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2077 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2078 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2079 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2080 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2081
2082 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2083 AssertReturn(pCur, VERR_NOT_FOUND);
2084 AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
2085 AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
2086 Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
2087
2088 Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
2089 pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
2090
2091 /*
2092 * Unmap it.
2093 */
2094 pgmLock(pVM);
2095
2096 RTGCPHYS GCPhysRangeREM;
2097 RTGCPHYS cbRangeREM;
2098 bool fInformREM;
2099 if (pCur->fOverlapping)
2100 {
2101 /* Restore the RAM pages we've replaced. */
2102 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2103 while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
2104 pRam = pRam->pNextR3;
2105
2106 RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
2107 Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
2108 PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2109 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2110 while (cPagesLeft-- > 0)
2111 {
2112 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
2113 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
2114 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
2115 PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
2116 PGM_PAGE_SET_PDE_TYPE(pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
2117
2118 pVM->pgm.s.cZeroPages++;
2119 pPageDst++;
2120 }
2121
2122 /* Flush physical page map TLB. */
2123 PGMPhysInvalidatePageMapTLB(pVM);
2124
2125 GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
2126 cbRangeREM = RTGCPHYS_MAX; /* ditto */
2127 fInformREM = false;
2128 }
2129 else
2130 {
2131 GCPhysRangeREM = pCur->RamRange.GCPhys;
2132 cbRangeREM = pCur->RamRange.cb;
2133 fInformREM = true;
2134
2135 pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
2136 }
2137
2138 pCur->RamRange.GCPhys = NIL_RTGCPHYS;
2139 pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
2140 pCur->fOverlapping = false;
2141 pCur->fMapped = false;
2142
2143 PGMPhysInvalidatePageMapTLB(pVM);
2144 pgmUnlock(pVM);
2145
2146 if (fInformREM)
2147 REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2148
2149 return VINF_SUCCESS;
2150}
2151
2152
2153/**
2154 * Checks if the given address is an MMIO2 base address or not.
2155 *
2156 * @returns true/false accordingly.
2157 * @param pVM Pointer to the shared VM structure.
2158 * @param pDevIns The owner of the memory, optional.
2159 * @param GCPhys The address to check.
2160 */
2161VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2162{
2163 /*
2164 * Validate input
2165 */
2166 VM_ASSERT_EMT_RETURN(pVM, false);
2167 AssertPtrReturn(pDevIns, false);
2168 AssertReturn(GCPhys != NIL_RTGCPHYS, false);
2169 AssertReturn(GCPhys != 0, false);
2170 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
2171
2172 /*
2173 * Search the list.
2174 */
2175 pgmLock(pVM);
2176 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2177 if (pCur->RamRange.GCPhys == GCPhys)
2178 {
2179 Assert(pCur->fMapped);
2180 pgmUnlock(pVM);
2181 return true;
2182 }
2183 pgmUnlock(pVM);
2184 return false;
2185}
2186
2187
2188/**
2189 * Gets the HC physical address of a page in the MMIO2 region.
2190 *
2191 * This is API is intended for MMHyper and shouldn't be called
2192 * by anyone else...
2193 *
2194 * @returns VBox status code.
2195 * @param pVM Pointer to the shared VM structure.
2196 * @param pDevIns The owner of the memory, optional.
2197 * @param iRegion The region.
2198 * @param off The page expressed an offset into the MMIO2 region.
2199 * @param pHCPhys Where to store the result.
2200 */
2201VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2202{
2203 /*
2204 * Validate input
2205 */
2206 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2207 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2208 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2209
2210 pgmLock(pVM);
2211 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2212 AssertReturn(pCur, VERR_NOT_FOUND);
2213 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2214
2215 PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2216 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2217 pgmUnlock(pVM);
2218 return VINF_SUCCESS;
2219}
2220
2221
2222/**
2223 * Maps a portion of an MMIO2 region into kernel space (host).
2224 *
2225 * The kernel mapping will become invalid when the MMIO2 memory is deregistered
2226 * or the VM is terminated.
2227 *
2228 * @return VBox status code.
2229 *
2230 * @param pVM Pointer to the shared VM structure.
2231 * @param pDevIns The device owning the MMIO2 memory.
2232 * @param iRegion The region.
2233 * @param off The offset into the region. Must be page aligned.
2234 * @param cb The number of bytes to map. Must be page aligned.
2235 * @param pszDesc Mapping description.
2236 * @param pR0Ptr Where to store the R0 address.
2237 */
2238VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2239 const char *pszDesc, PRTR0PTR pR0Ptr)
2240{
2241 /*
2242 * Validate input.
2243 */
2244 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2245 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2246 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2247
2248 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2249 AssertReturn(pCur, VERR_NOT_FOUND);
2250 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2251 AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2252 AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2253
2254 /*
2255 * Pass the request on to the support library/driver.
2256 */
2257 int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2258
2259 return rc;
2260}
2261
2262
2263/**
2264 * Registers a ROM image.
2265 *
2266 * Shadowed ROM images requires double the amount of backing memory, so,
2267 * don't use that unless you have to. Shadowing of ROM images is process
2268 * where we can select where the reads go and where the writes go. On real
2269 * hardware the chipset provides means to configure this. We provide
2270 * PGMR3PhysProtectROM() for this purpose.
2271 *
2272 * A read-only copy of the ROM image will always be kept around while we
2273 * will allocate RAM pages for the changes on demand (unless all memory
2274 * is configured to be preallocated).
2275 *
2276 * @returns VBox status.
2277 * @param pVM VM Handle.
2278 * @param pDevIns The device instance owning the ROM.
2279 * @param GCPhys First physical address in the range.
2280 * Must be page aligned!
2281 * @param cbRange The size of the range (in bytes).
2282 * Must be page aligned!
2283 * @param pvBinary Pointer to the binary data backing the ROM image.
2284 * This must be exactly \a cbRange in size.
2285 * @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2286 * and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2287 * @param pszDesc Pointer to description string. This must not be freed.
2288 *
2289 * @remark There is no way to remove the rom, automatically on device cleanup or
2290 * manually from the device yet. This isn't difficult in any way, it's
2291 * just not something we expect to be necessary for a while.
2292 */
2293VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2294 const void *pvBinary, uint32_t fFlags, const char *pszDesc)
2295{
2296 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2297 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2298
2299 /*
2300 * Validate input.
2301 */
2302 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2303 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2304 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2305 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2306 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2307 AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2308 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2309 AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED | PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2310 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2311
2312 const uint32_t cPages = cb >> PAGE_SHIFT;
2313
2314 /*
2315 * Find the ROM location in the ROM list first.
2316 */
2317 PPGMROMRANGE pRomPrev = NULL;
2318 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2319 while (pRom && GCPhysLast >= pRom->GCPhys)
2320 {
2321 if ( GCPhys <= pRom->GCPhysLast
2322 && GCPhysLast >= pRom->GCPhys)
2323 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2324 GCPhys, GCPhysLast, pszDesc,
2325 pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2326 VERR_PGM_RAM_CONFLICT);
2327 /* next */
2328 pRomPrev = pRom;
2329 pRom = pRom->pNextR3;
2330 }
2331
2332 /*
2333 * Find the RAM location and check for conflicts.
2334 *
2335 * Conflict detection is a bit different than for RAM
2336 * registration since a ROM can be located within a RAM
2337 * range. So, what we have to check for is other memory
2338 * types (other than RAM that is) and that we don't span
2339 * more than one RAM range (layz).
2340 */
2341 bool fRamExists = false;
2342 PPGMRAMRANGE pRamPrev = NULL;
2343 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2344 while (pRam && GCPhysLast >= pRam->GCPhys)
2345 {
2346 if ( GCPhys <= pRam->GCPhysLast
2347 && GCPhysLast >= pRam->GCPhys)
2348 {
2349 /* completely within? */
2350 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2351 && GCPhysLast <= pRam->GCPhysLast,
2352 ("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2353 GCPhys, GCPhysLast, pszDesc,
2354 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2355 VERR_PGM_RAM_CONFLICT);
2356 fRamExists = true;
2357 break;
2358 }
2359
2360 /* next */
2361 pRamPrev = pRam;
2362 pRam = pRam->pNextR3;
2363 }
2364 if (fRamExists)
2365 {
2366 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2367 uint32_t cPagesLeft = cPages;
2368 while (cPagesLeft-- > 0)
2369 {
2370 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2371 ("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2372 pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2373 pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2374 Assert(PGM_PAGE_IS_ZERO(pPage));
2375 pPage++;
2376 }
2377 }
2378
2379 /*
2380 * Update the base memory reservation if necessary.
2381 */
2382 uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
2383 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2384 cExtraBaseCost += cPages;
2385 if (cExtraBaseCost)
2386 {
2387 int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2388 if (RT_FAILURE(rc))
2389 return rc;
2390 }
2391
2392 /*
2393 * Allocate memory for the virgin copy of the RAM.
2394 */
2395 PGMMALLOCATEPAGESREQ pReq;
2396 int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2397 AssertRCReturn(rc, rc);
2398
2399 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2400 {
2401 pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2402 pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2403 pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2404 }
2405
2406 pgmLock(pVM);
2407 rc = GMMR3AllocatePagesPerform(pVM, pReq);
2408 pgmUnlock(pVM);
2409 if (RT_FAILURE(rc))
2410 {
2411 GMMR3AllocatePagesCleanup(pReq);
2412 return rc;
2413 }
2414
2415 /*
2416 * Allocate the new ROM range and RAM range (if necessary).
2417 */
2418 PPGMROMRANGE pRomNew;
2419 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2420 if (RT_SUCCESS(rc))
2421 {
2422 PPGMRAMRANGE pRamNew = NULL;
2423 if (!fRamExists)
2424 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2425 if (RT_SUCCESS(rc))
2426 {
2427 pgmLock(pVM);
2428
2429 /*
2430 * Initialize and insert the RAM range (if required).
2431 */
2432 PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2433 if (!fRamExists)
2434 {
2435 pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2436 pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2437 pRamNew->GCPhys = GCPhys;
2438 pRamNew->GCPhysLast = GCPhysLast;
2439 pRamNew->cb = cb;
2440 pRamNew->pszDesc = pszDesc;
2441 pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
2442 pRamNew->pvR3 = NULL;
2443 pRamNew->paLSPages = NULL;
2444
2445 PPGMPAGE pPage = &pRamNew->aPages[0];
2446 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2447 {
2448 PGM_PAGE_INIT(pPage,
2449 pReq->aPages[iPage].HCPhysGCPhys,
2450 pReq->aPages[iPage].idPage,
2451 PGMPAGETYPE_ROM,
2452 PGM_PAGE_STATE_ALLOCATED);
2453
2454 pRomPage->Virgin = *pPage;
2455 }
2456
2457 pVM->pgm.s.cAllPages += cPages;
2458 pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2459 }
2460 else
2461 {
2462 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2463 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2464 {
2465 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2466 PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2467 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2468 PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2469
2470 pRomPage->Virgin = *pPage;
2471 }
2472
2473 pRamNew = pRam;
2474
2475 pVM->pgm.s.cZeroPages -= cPages;
2476 }
2477 pVM->pgm.s.cPrivatePages += cPages;
2478
2479 /* Flush physical page map TLB. */
2480 PGMPhysInvalidatePageMapTLB(pVM);
2481
2482 pgmUnlock(pVM);
2483
2484
2485 /*
2486 * !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2487 *
2488 * If it's shadowed we'll register the handler after the ROM notification
2489 * so we get the access handler callbacks that we should. If it isn't
2490 * shadowed we'll do it the other way around to make REM use the built-in
2491 * ROM behavior and not the handler behavior (which is to route all access
2492 * to PGM atm).
2493 */
2494 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2495 {
2496 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2497 rc = PGMR3HandlerPhysicalRegister(pVM,
2498 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2499 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2500 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2501 GCPhys, GCPhysLast,
2502 pgmR3PhysRomWriteHandler, pRomNew,
2503 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2504 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2505 }
2506 else
2507 {
2508 rc = PGMR3HandlerPhysicalRegister(pVM,
2509 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2510 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2511 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2512 GCPhys, GCPhysLast,
2513 pgmR3PhysRomWriteHandler, pRomNew,
2514 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2515 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2516 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2517 }
2518 if (RT_SUCCESS(rc))
2519 {
2520 pgmLock(pVM);
2521
2522 /*
2523 * Copy the image over to the virgin pages.
2524 * This must be done after linking in the RAM range.
2525 */
2526 PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2527 for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2528 {
2529 void *pvDstPage;
2530 rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
2531 if (RT_FAILURE(rc))
2532 {
2533 VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2534 break;
2535 }
2536 memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2537 }
2538 if (RT_SUCCESS(rc))
2539 {
2540 /*
2541 * Initialize the ROM range.
2542 * Note that the Virgin member of the pages has already been initialized above.
2543 */
2544 pRomNew->GCPhys = GCPhys;
2545 pRomNew->GCPhysLast = GCPhysLast;
2546 pRomNew->cb = cb;
2547 pRomNew->fFlags = fFlags;
2548 pRomNew->idSavedState = UINT8_MAX;
2549 pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2550 pRomNew->pszDesc = pszDesc;
2551
2552 for (unsigned iPage = 0; iPage < cPages; iPage++)
2553 {
2554 PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2555 pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2556 PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2557 }
2558
2559 /* update the page count stats for the shadow pages. */
2560 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2561 {
2562 pVM->pgm.s.cZeroPages += cPages;
2563 pVM->pgm.s.cAllPages += cPages;
2564 }
2565
2566 /*
2567 * Insert the ROM range, tell REM and return successfully.
2568 */
2569 pRomNew->pNextR3 = pRom;
2570 pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2571 pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2572
2573 if (pRomPrev)
2574 {
2575 pRomPrev->pNextR3 = pRomNew;
2576 pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2577 pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2578 }
2579 else
2580 {
2581 pVM->pgm.s.pRomRangesR3 = pRomNew;
2582 pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2583 pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2584 }
2585
2586 PGMPhysInvalidatePageMapTLB(pVM);
2587 GMMR3AllocatePagesCleanup(pReq);
2588 pgmUnlock(pVM);
2589 return VINF_SUCCESS;
2590 }
2591
2592 /* bail out */
2593
2594 pgmUnlock(pVM);
2595 int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2596 AssertRC(rc2);
2597 pgmLock(pVM);
2598 }
2599
2600 if (!fRamExists)
2601 {
2602 pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2603 MMHyperFree(pVM, pRamNew);
2604 }
2605 }
2606 MMHyperFree(pVM, pRomNew);
2607 }
2608
2609 /** @todo Purge the mapping cache or something... */
2610 GMMR3FreeAllocatedPages(pVM, pReq);
2611 GMMR3AllocatePagesCleanup(pReq);
2612 pgmUnlock(pVM);
2613 return rc;
2614}
2615
2616
2617/**
2618 * \#PF Handler callback for ROM write accesses.
2619 *
2620 * @returns VINF_SUCCESS if the handler have carried out the operation.
2621 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2622 * @param pVM VM Handle.
2623 * @param GCPhys The physical address the guest is writing to.
2624 * @param pvPhys The HC mapping of that address.
2625 * @param pvBuf What the guest is reading/writing.
2626 * @param cbBuf How much it's reading/writing.
2627 * @param enmAccessType The access type.
2628 * @param pvUser User argument.
2629 */
2630static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2631{
2632 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2633 const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2634 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2635 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2636 Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2637
2638 if (enmAccessType == PGMACCESSTYPE_READ)
2639 {
2640 switch (pRomPage->enmProt)
2641 {
2642 /*
2643 * Take the default action.
2644 */
2645 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2646 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2647 case PGMROMPROT_READ_ROM_WRITE_RAM:
2648 case PGMROMPROT_READ_RAM_WRITE_RAM:
2649 return VINF_PGM_HANDLER_DO_DEFAULT;
2650
2651 default:
2652 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2653 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2654 VERR_INTERNAL_ERROR);
2655 }
2656 }
2657 else
2658 {
2659 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2660 switch (pRomPage->enmProt)
2661 {
2662 /*
2663 * Ignore writes.
2664 */
2665 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2666 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2667 return VINF_SUCCESS;
2668
2669 /*
2670 * Write to the ram page.
2671 */
2672 case PGMROMPROT_READ_ROM_WRITE_RAM:
2673 case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
2674 {
2675 /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2676 Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2677
2678 /*
2679 * Take the lock, do lazy allocation, map the page and copy the data.
2680 *
2681 * Note that we have to bypass the mapping TLB since it works on
2682 * guest physical addresses and entering the shadow page would
2683 * kind of screw things up...
2684 */
2685 int rc = pgmLock(pVM);
2686 AssertRC(rc);
2687
2688 PPGMPAGE pShadowPage = &pRomPage->Shadow;
2689 if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2690 {
2691 pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2692 AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2693 }
2694
2695 void *pvDstPage;
2696 rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
2697 if (RT_SUCCESS(rc))
2698 {
2699 memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2700 pRomPage->LiveSave.fWrittenTo = true;
2701 }
2702
2703 pgmUnlock(pVM);
2704 return rc;
2705 }
2706
2707 default:
2708 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2709 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2710 VERR_INTERNAL_ERROR);
2711 }
2712 }
2713}
2714
2715
2716/**
2717 * Called by PGMR3Reset to reset the shadow, switch to the virgin,
2718 * and verify that the virgin part is untouched.
2719 *
2720 * This is done after the normal memory has been cleared.
2721 *
2722 * ASSUMES that the caller owns the PGM lock.
2723 *
2724 * @param pVM The VM handle.
2725 */
2726int pgmR3PhysRomReset(PVM pVM)
2727{
2728 Assert(PGMIsLockOwner(pVM));
2729 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2730 {
2731 const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2732
2733 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2734 {
2735 /*
2736 * Reset the physical handler.
2737 */
2738 int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2739 AssertRCReturn(rc, rc);
2740
2741 /*
2742 * What we do with the shadow pages depends on the memory
2743 * preallocation option. If not enabled, we'll just throw
2744 * out all the dirty pages and replace them by the zero page.
2745 */
2746 if (!pVM->pgm.s.fRamPreAlloc)
2747 {
2748 /* Free the dirty pages. */
2749 uint32_t cPendingPages = 0;
2750 PGMMFREEPAGESREQ pReq;
2751 rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2752 AssertRCReturn(rc, rc);
2753
2754 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2755 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
2756 {
2757 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2758 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2759 AssertLogRelRCReturn(rc, rc);
2760 }
2761
2762 if (cPendingPages)
2763 {
2764 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2765 AssertLogRelRCReturn(rc, rc);
2766 }
2767 GMMR3FreePagesCleanup(pReq);
2768 }
2769 else
2770 {
2771 /* clear all the shadow pages. */
2772 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2773 {
2774 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO);
2775 void *pvDstPage;
2776 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2777 rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
2778 if (RT_FAILURE(rc))
2779 break;
2780 ASMMemZeroPage(pvDstPage);
2781 }
2782 AssertRCReturn(rc, rc);
2783 }
2784 }
2785
2786#ifdef VBOX_STRICT
2787 /*
2788 * Verify that the virgin page is unchanged if possible.
2789 */
2790 if (pRom->pvOriginal)
2791 {
2792 uint8_t const *pbSrcPage = (uint8_t const *)pRom->pvOriginal;
2793 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2794 {
2795 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2796 void const *pvDstPage;
2797 int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
2798 if (RT_FAILURE(rc))
2799 break;
2800 if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2801 LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2802 GCPhys, pRom->pszDesc));
2803 }
2804 }
2805#endif
2806 }
2807
2808 return VINF_SUCCESS;
2809}
2810
2811
2812/**
2813 * Change the shadowing of a range of ROM pages.
2814 *
2815 * This is intended for implementing chipset specific memory registers
2816 * and will not be very strict about the input. It will silently ignore
2817 * any pages that are not the part of a shadowed ROM.
2818 *
2819 * @returns VBox status code.
2820 * @retval VINF_PGM_SYNC_CR3
2821 *
2822 * @param pVM Pointer to the shared VM structure.
2823 * @param GCPhys Where to start. Page aligned.
2824 * @param cb How much to change. Page aligned.
2825 * @param enmProt The new ROM protection.
2826 */
2827VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2828{
2829 /*
2830 * Check input
2831 */
2832 if (!cb)
2833 return VINF_SUCCESS;
2834 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2835 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2836 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2837 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2838 AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2839
2840 /*
2841 * Process the request.
2842 */
2843 pgmLock(pVM);
2844 int rc = VINF_SUCCESS;
2845 bool fFlushTLB = false;
2846 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2847 {
2848 if ( GCPhys <= pRom->GCPhysLast
2849 && GCPhysLast >= pRom->GCPhys
2850 && (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2851 {
2852 /*
2853 * Iterate the relevant pages and make necessary the changes.
2854 */
2855 bool fChanges = false;
2856 uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2857 ? pRom->cb >> PAGE_SHIFT
2858 : (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2859 for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2860 iPage < cPages;
2861 iPage++)
2862 {
2863 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2864 if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2865 {
2866 fChanges = true;
2867
2868 /* flush references to the page. */
2869 PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2870 int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage, &fFlushTLB);
2871 if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS || RT_FAILURE(rc2)))
2872 rc = rc2;
2873
2874 PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2875 PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2876
2877 *pOld = *pRamPage;
2878 *pRamPage = *pNew;
2879 /** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2880 }
2881 pRomPage->enmProt = enmProt;
2882 }
2883
2884 /*
2885 * Reset the access handler if we made changes, no need
2886 * to optimize this.
2887 */
2888 if (fChanges)
2889 {
2890 int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2891 if (RT_FAILURE(rc2))
2892 {
2893 pgmUnlock(pVM);
2894 AssertRC(rc);
2895 return rc2;
2896 }
2897 }
2898
2899 /* Advance - cb isn't updated. */
2900 GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2901 }
2902 }
2903 pgmUnlock(pVM);
2904 if (fFlushTLB)
2905 PGM_INVL_ALL_VCPU_TLBS(pVM);
2906
2907 return rc;
2908}
2909
2910
2911/**
2912 * Sets the Address Gate 20 state.
2913 *
2914 * @param pVCpu The VCPU to operate on.
2915 * @param fEnable True if the gate should be enabled.
2916 * False if the gate should be disabled.
2917 */
2918VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
2919{
2920 LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
2921 if (pVCpu->pgm.s.fA20Enabled != fEnable)
2922 {
2923 pVCpu->pgm.s.fA20Enabled = fEnable;
2924 pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2925 REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
2926 /** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2927 }
2928}
2929
2930
2931/**
2932 * Tree enumeration callback for dealing with age rollover.
2933 * It will perform a simple compression of the current age.
2934 */
2935static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2936{
2937 Assert(PGMIsLockOwner((PVM)pvUser));
2938 /* Age compression - ASSUMES iNow == 4. */
2939 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2940 if (pChunk->iAge >= UINT32_C(0xffffff00))
2941 pChunk->iAge = 3;
2942 else if (pChunk->iAge >= UINT32_C(0xfffff000))
2943 pChunk->iAge = 2;
2944 else if (pChunk->iAge)
2945 pChunk->iAge = 1;
2946 else /* iAge = 0 */
2947 pChunk->iAge = 4;
2948
2949 /* reinsert */
2950 PVM pVM = (PVM)pvUser;
2951 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2952 pChunk->AgeCore.Key = pChunk->iAge;
2953 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2954 return 0;
2955}
2956
2957
2958/**
2959 * Tree enumeration callback that updates the chunks that have
2960 * been used since the last
2961 */
2962static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
2963{
2964 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2965 if (!pChunk->iAge)
2966 {
2967 PVM pVM = (PVM)pvUser;
2968 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2969 pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
2970 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2971 }
2972
2973 return 0;
2974}
2975
2976
2977/**
2978 * Performs ageing of the ring-3 chunk mappings.
2979 *
2980 * @param pVM The VM handle.
2981 */
2982VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
2983{
2984 pgmLock(pVM);
2985 pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
2986 pVM->pgm.s.ChunkR3Map.iNow++;
2987 if (pVM->pgm.s.ChunkR3Map.iNow == 0)
2988 {
2989 pVM->pgm.s.ChunkR3Map.iNow = 4;
2990 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
2991 }
2992 else
2993 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingCallback, pVM);
2994 pgmUnlock(pVM);
2995}
2996
2997
2998/**
2999 * The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
3000 */
3001typedef struct PGMR3PHYSCHUNKUNMAPCB
3002{
3003 PVM pVM; /**< The VM handle. */
3004 PPGMCHUNKR3MAP pChunk; /**< The chunk to unmap. */
3005} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
3006
3007
3008/**
3009 * Callback used to find the mapping that's been unused for
3010 * the longest time.
3011 */
3012static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
3013{
3014 do
3015 {
3016 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
3017 if ( pChunk->iAge
3018 && !pChunk->cRefs)
3019 {
3020 /*
3021 * Check that it's not in any of the TLBs.
3022 */
3023 PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
3024 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3025 if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
3026 {
3027 pChunk = NULL;
3028 break;
3029 }
3030 if (pChunk)
3031 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
3032 if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
3033 {
3034 pChunk = NULL;
3035 break;
3036 }
3037 if (pChunk)
3038 {
3039 ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
3040 return 1; /* done */
3041 }
3042 }
3043
3044 /* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
3045 pNode = pNode->pList;
3046 } while (pNode);
3047 return 0;
3048}
3049
3050
3051/**
3052 * Finds a good candidate for unmapping when the ring-3 mapping cache is full.
3053 *
3054 * The candidate will not be part of any TLBs, so no need to flush
3055 * anything afterwards.
3056 *
3057 * @returns Chunk id.
3058 * @param pVM The VM handle.
3059 */
3060static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
3061{
3062 Assert(PGMIsLockOwner(pVM));
3063
3064 /*
3065 * Do tree ageing first?
3066 */
3067 if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
3068 PGMR3PhysChunkAgeing(pVM);
3069
3070 /*
3071 * Enumerate the age tree starting with the left most node.
3072 */
3073 PGMR3PHYSCHUNKUNMAPCB Args;
3074 Args.pVM = pVM;
3075 Args.pChunk = NULL;
3076 if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /*fFromLeft*/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
3077 return Args.pChunk->Core.Key;
3078 return INT32_MAX;
3079}
3080
3081
3082/**
3083 * Maps the given chunk into the ring-3 mapping cache.
3084 *
3085 * This will call ring-0.
3086 *
3087 * @returns VBox status code.
3088 * @param pVM The VM handle.
3089 * @param idChunk The chunk in question.
3090 * @param ppChunk Where to store the chunk tracking structure.
3091 *
3092 * @remarks Called from within the PGM critical section.
3093 */
3094int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
3095{
3096 int rc;
3097
3098 Assert(PGMIsLockOwner(pVM));
3099 /*
3100 * Allocate a new tracking structure first.
3101 */
3102#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3103 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
3104#else
3105 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
3106#endif
3107 AssertReturn(pChunk, VERR_NO_MEMORY);
3108 pChunk->Core.Key = idChunk;
3109 pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
3110 pChunk->iAge = 0;
3111 pChunk->cRefs = 0;
3112 pChunk->cPermRefs = 0;
3113 pChunk->pv = NULL;
3114
3115 /*
3116 * Request the ring-0 part to map the chunk in question and if
3117 * necessary unmap another one to make space in the mapping cache.
3118 */
3119 GMMMAPUNMAPCHUNKREQ Req;
3120 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3121 Req.Hdr.cbReq = sizeof(Req);
3122 Req.pvR3 = NULL;
3123 Req.idChunkMap = idChunk;
3124 Req.idChunkUnmap = NIL_GMM_CHUNKID;
3125 if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3126 Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
3127/** @todo This is wrong. Any thread in the VM process should be able to do this,
3128 * there are depenenecies on this. What currently saves the day is that
3129 * we don't unmap anything and that all non-zero memory will therefore
3130 * be present when non-EMTs tries to access it. */
3131 rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3132 if (RT_SUCCESS(rc))
3133 {
3134 /*
3135 * Update the tree.
3136 */
3137 /* insert the new one. */
3138 AssertPtr(Req.pvR3);
3139 pChunk->pv = Req.pvR3;
3140 bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
3141 AssertRelease(fRc);
3142 pVM->pgm.s.ChunkR3Map.c++;
3143
3144 fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3145 AssertRelease(fRc);
3146
3147 /* remove the unmapped one. */
3148 if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
3149 {
3150 PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
3151 AssertRelease(pUnmappedChunk);
3152 pUnmappedChunk->pv = NULL;
3153 pUnmappedChunk->Core.Key = UINT32_MAX;
3154#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3155 MMR3HeapFree(pUnmappedChunk);
3156#else
3157 MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3158#endif
3159 pVM->pgm.s.ChunkR3Map.c--;
3160
3161 /* Chunk removed, so clear the page map TBL as well (might still be referenced). */
3162 PGMPhysInvalidatePageMapTLB(pVM);
3163 }
3164 }
3165 else
3166 {
3167 AssertRC(rc);
3168#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3169 MMR3HeapFree(pChunk);
3170#else
3171 MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
3172#endif
3173 pChunk = NULL;
3174 }
3175
3176 *ppChunk = pChunk;
3177 return rc;
3178}
3179
3180
3181/**
3182 * For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3183 *
3184 * @returns see pgmR3PhysChunkMap.
3185 * @param pVM The VM handle.
3186 * @param idChunk The chunk to map.
3187 */
3188VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3189{
3190 PPGMCHUNKR3MAP pChunk;
3191 int rc;
3192
3193 pgmLock(pVM);
3194 rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3195 pgmUnlock(pVM);
3196 return rc;
3197}
3198
3199
3200/**
3201 * Invalidates the TLB for the ring-3 mapping cache.
3202 *
3203 * @param pVM The VM handle.
3204 */
3205VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3206{
3207 pgmLock(pVM);
3208 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3209 {
3210 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3211 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3212 }
3213 /* The page map TLB references chunks, so invalidate that one too. */
3214 PGMPhysInvalidatePageMapTLB(pVM);
3215 pgmUnlock(pVM);
3216}
3217
3218
3219/**
3220 * Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_PAGE to allocate a large (2MB) page
3221 * for use with a nested paging PDE.
3222 *
3223 * @returns The following VBox status codes.
3224 * @retval VINF_SUCCESS on success.
3225 * @retval VINF_EM_NO_MEMORY if we're out of memory.
3226 *
3227 * @param pVM The VM handle.
3228 * @param GCPhys GC physical start address of the 2 MB range
3229 */
3230VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
3231{
3232 pgmLock(pVM);
3233
3234 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
3235 if (RT_SUCCESS(rc))
3236 {
3237 Assert(pVM->pgm.s.cLargeHandyPages == 1);
3238
3239 uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
3240 RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
3241
3242 void *pv;
3243
3244 /* Map the large page into our address space.
3245 *
3246 * Note: assuming that within the 2 MB range:
3247 * - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
3248 * - user space mapping is continuous as well
3249 * - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
3250 */
3251 rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
3252 AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", idPage, HCPhys, rc));
3253
3254 if (RT_SUCCESS(rc))
3255 {
3256 /*
3257 * Clear the pages.
3258 */
3259 for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
3260 {
3261 ASMMemZeroPage(pv);
3262
3263 PPGMPAGE pPage;
3264 rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
3265 AssertRC(rc);
3266
3267 Assert(PGM_PAGE_IS_ZERO(pPage));
3268 STAM_COUNTER_INC(&pVM->pgm.s.StatRZPageReplaceZero);
3269 pVM->pgm.s.cZeroPages--;
3270
3271 /*
3272 * Do the PGMPAGE modifications.
3273 */
3274 pVM->pgm.s.cPrivatePages++;
3275 PGM_PAGE_SET_HCPHYS(pPage, HCPhys);
3276 PGM_PAGE_SET_PAGEID(pPage, idPage);
3277 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
3278 PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_PDE);
3279
3280 /* Somewhat dirty assumption that page ids are increasing. */
3281 idPage++;
3282
3283 HCPhys += PAGE_SIZE;
3284 GCPhys += PAGE_SIZE;
3285
3286 pv = (void *)((uintptr_t)pv + PAGE_SIZE);
3287
3288 Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
3289 }
3290 /* Flush all TLBs. */
3291 PGM_INVL_ALL_VCPU_TLBS(pVM);
3292 PGMPhysInvalidatePageMapTLB(pVM);
3293 }
3294 pVM->pgm.s.cLargeHandyPages = 0;
3295 }
3296
3297 pgmUnlock(pVM);
3298 return rc;
3299}
3300
3301
3302/**
3303 * Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3304 *
3305 * This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3306 * signal and clear the out of memory condition. When contracted, this API is
3307 * used to try clear the condition when the user wants to resume.
3308 *
3309 * @returns The following VBox status codes.
3310 * @retval VINF_SUCCESS on success. FFs cleared.
3311 * @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3312 * this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3313 *
3314 * @param pVM The VM handle.
3315 *
3316 * @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3317 * in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3318 * pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3319 * handler.
3320 */
3321VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3322{
3323 pgmLock(pVM);
3324
3325 /*
3326 * Allocate more pages, noting down the index of the first new page.
3327 */
3328 uint32_t iClear = pVM->pgm.s.cHandyPages;
3329 AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3330 Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3331 int rcAlloc = VINF_SUCCESS;
3332 int rcSeed = VINF_SUCCESS;
3333 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3334 while (rc == VERR_GMM_SEED_ME)
3335 {
3336 void *pvChunk;
3337 rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3338 if (RT_SUCCESS(rc))
3339 {
3340 rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3341 if (RT_FAILURE(rc))
3342 SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3343 }
3344 if (RT_SUCCESS(rc))
3345 rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3346 }
3347
3348 if (RT_SUCCESS(rc))
3349 {
3350 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3351 Assert(pVM->pgm.s.cHandyPages > 0);
3352 VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3353 VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3354
3355 /*
3356 * Clear the pages.
3357 */
3358 while (iClear < pVM->pgm.s.cHandyPages)
3359 {
3360 PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3361 void *pv;
3362 rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3363 AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3364 ASMMemZeroPage(pv);
3365 iClear++;
3366 Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3367 }
3368 }
3369 else
3370 {
3371 /*
3372 * We should never get here unless there is a genuine shortage of
3373 * memory (or some internal error). Flag the error so the VM can be
3374 * suspended ASAP and the user informed. If we're totally out of
3375 * handy pages we will return failure.
3376 */
3377 /* Report the failure. */
3378 LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3379 " cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3380 rc, rcAlloc, rcSeed,
3381 pVM->pgm.s.cHandyPages,
3382 pVM->pgm.s.cAllPages,
3383 pVM->pgm.s.cPrivatePages,
3384 pVM->pgm.s.cSharedPages,
3385 pVM->pgm.s.cZeroPages));
3386 if ( rc != VERR_NO_MEMORY
3387 && rc != VERR_LOCK_FAILED)
3388 {
3389 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3390 {
3391 LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3392 i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3393 pVM->pgm.s.aHandyPages[i].idSharedPage));
3394 uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3395 if (idPage != NIL_GMM_PAGEID)
3396 {
3397 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3398 pRam;
3399 pRam = pRam->pNextR3)
3400 {
3401 uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3402 for (uint32_t iPage = 0; iPage < cPages; iPage++)
3403 if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3404 LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3405 pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3406 }
3407 }
3408 }
3409 }
3410
3411 /* Set the FFs and adjust rc. */
3412 VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3413 VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3414 if ( rc == VERR_NO_MEMORY
3415 || rc == VERR_LOCK_FAILED)
3416 rc = VINF_EM_NO_MEMORY;
3417 }
3418
3419 pgmUnlock(pVM);
3420 return rc;
3421}
3422
3423
3424/**
3425 * Frees the specified RAM page and replaces it with the ZERO page.
3426 *
3427 * This is used by ballooning, remapping MMIO2 and RAM reset.
3428 *
3429 * @param pVM Pointer to the shared VM structure.
3430 * @param pReq Pointer to the request.
3431 * @param pPage Pointer to the page structure.
3432 * @param GCPhys The guest physical address of the page, if applicable.
3433 *
3434 * @remarks The caller must own the PGM lock.
3435 */
3436static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3437{
3438 /*
3439 * Assert sanity.
3440 */
3441 Assert(PGMIsLockOwner(pVM));
3442 if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3443 && PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3444 {
3445 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3446 return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3447 }
3448
3449 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO)
3450 return VINF_SUCCESS;
3451
3452 const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3453 Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3454 if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3455 || idPage > GMM_PAGEID_LAST
3456 || PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3457 {
3458 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3459 return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3460 }
3461
3462 /* update page count stats. */
3463 if (PGM_PAGE_IS_SHARED(pPage))
3464 pVM->pgm.s.cSharedPages--;
3465 else
3466 pVM->pgm.s.cPrivatePages--;
3467 pVM->pgm.s.cZeroPages++;
3468
3469 /* Deal with write monitored pages. */
3470 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
3471 {
3472 PGM_PAGE_SET_WRITTEN_TO(pPage);
3473 pVM->pgm.s.cWrittenToPages++;
3474 }
3475
3476 /*
3477 * pPage = ZERO page.
3478 */
3479 PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3480 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3481 PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3482 PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
3483
3484 /* Flush physical page map TLB entry. */
3485 PGMPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
3486
3487 /*
3488 * Make sure it's not in the handy page array.
3489 */
3490 for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3491 {
3492 if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3493 {
3494 pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3495 break;
3496 }
3497 if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3498 {
3499 pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3500 break;
3501 }
3502 }
3503
3504 /*
3505 * Push it onto the page array.
3506 */
3507 uint32_t iPage = *pcPendingPages;
3508 Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3509 *pcPendingPages += 1;
3510
3511 pReq->aPages[iPage].idPage = idPage;
3512
3513 if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3514 return VINF_SUCCESS;
3515
3516 /*
3517 * Flush the pages.
3518 */
3519 int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3520 if (RT_SUCCESS(rc))
3521 {
3522 GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3523 *pcPendingPages = 0;
3524 }
3525 return rc;
3526}
3527
3528
3529/**
3530 * Converts a GC physical address to a HC ring-3 pointer, with some
3531 * additional checks.
3532 *
3533 * @returns VBox status code.
3534 * @retval VINF_SUCCESS on success.
3535 * @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3536 * access handler of some kind.
3537 * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3538 * accesses or is odd in any way.
3539 * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3540 *
3541 * @param pVM The VM handle.
3542 * @param GCPhys The GC physical address to convert.
3543 * @param fWritable Whether write access is required.
3544 * @param ppv Where to store the pointer corresponding to GCPhys on
3545 * success.
3546 */
3547VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3548{
3549 pgmLock(pVM);
3550
3551 PPGMRAMRANGE pRam;
3552 PPGMPAGE pPage;
3553 int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3554 if (RT_SUCCESS(rc))
3555 {
3556 if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3557 rc = VINF_SUCCESS;
3558 else
3559 {
3560 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3561 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3562 else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3563 {
3564 /** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3565 * in -norawr0 mode. */
3566 if (fWritable)
3567 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3568 }
3569 else
3570 {
3571 /* Temporarily disabled physical handler(s), since the recompiler
3572 doesn't get notified when it's reset we'll have to pretend it's
3573 operating normally. */
3574 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3575 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3576 else
3577 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3578 }
3579 }
3580 if (RT_SUCCESS(rc))
3581 {
3582 int rc2;
3583
3584 /* Make sure what we return is writable. */
3585 if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3586 switch (PGM_PAGE_GET_STATE(pPage))
3587 {
3588 case PGM_PAGE_STATE_ALLOCATED:
3589 break;
3590 case PGM_PAGE_STATE_ZERO:
3591 case PGM_PAGE_STATE_SHARED:
3592 case PGM_PAGE_STATE_WRITE_MONITORED:
3593 rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3594 AssertLogRelRCReturn(rc2, rc2);
3595 break;
3596 }
3597
3598 /* Get a ring-3 mapping of the address. */
3599 PPGMPAGER3MAPTLBE pTlbe;
3600 rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3601 AssertLogRelRCReturn(rc2, rc2);
3602 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
3603 /** @todo mapping/locking hell; this isn't horribly efficient since
3604 * pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
3605
3606 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] *ppv=%p\n", GCPhys, rc, pPage, *ppv));
3607 }
3608 else
3609 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3610
3611 /* else: handler catching all access, no pointer returned. */
3612 }
3613 else
3614 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3615
3616 pgmUnlock(pVM);
3617 return rc;
3618}
3619
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