PGMPhys.cpp@ 27588

Last change on this file since 27588 was 27588, checked in by vboxsync, 15 years ago
Flush the recompiler's TLB as well when adjusting the balloon.
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File size: 129.9 KB

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1	/* $Id: PGMPhys.cpp 27588 2010-03-22 13:21:13Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_PHYS
27	#include <VBox/pgm.h>
28	#include <VBox/iom.h>
29	#include <VBox/mm.h>
30	#include <VBox/stam.h>
31	#include <VBox/rem.h>
32	#include <VBox/pdmdev.h>
33	#include "PGMInternal.h"
34	#include <VBox/vm.h>
35	#include "PGMInline.h"
36	#include <VBox/sup.h>
37	#include <VBox/param.h>
38	#include <VBox/err.h>
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/alloc.h>
42	#include <iprt/asm.h>
43	#include <iprt/thread.h>
44	#include <iprt/string.h>
45
46
47	/*******************************************************************************
48	* Defined Constants And Macros *
49	*******************************************************************************/
50	/** The number of pages to free in one batch. */
51	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
52
53
54	/*******************************************************************************
55	* Internal Functions *
56	*******************************************************************************/
57	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
58	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
59
60
61	/*
62	* PGMR3PhysReadU8-64
63	* PGMR3PhysWriteU8-64
64	*/
65	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
66	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
67	#define PGMPHYS_DATASIZE 1
68	#define PGMPHYS_DATATYPE uint8_t
69	#include "PGMPhysRWTmpl.h"
70
71	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
72	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
73	#define PGMPHYS_DATASIZE 2
74	#define PGMPHYS_DATATYPE uint16_t
75	#include "PGMPhysRWTmpl.h"
76
77	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
78	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
79	#define PGMPHYS_DATASIZE 4
80	#define PGMPHYS_DATATYPE uint32_t
81	#include "PGMPhysRWTmpl.h"
82
83	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
84	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
85	#define PGMPHYS_DATASIZE 8
86	#define PGMPHYS_DATATYPE uint64_t
87	#include "PGMPhysRWTmpl.h"
88
89
90	/**
91	* EMT worker for PGMR3PhysReadExternal.
92	*/
93	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
94	{
95	PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
96	return VINF_SUCCESS;
97	}
98
99
100	/**
101	* Write to physical memory, external users.
102	*
103	* @returns VBox status code.
104	* @retval VINF_SUCCESS.
105	*
106	* @param pVM VM Handle.
107	* @param GCPhys Physical address to write to.
108	* @param pvBuf What to write.
109	* @param cbWrite How many bytes to write.
110	*
111	* @thread Any but EMTs.
112	*/
113	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
114	{
115	VM_ASSERT_OTHER_THREAD(pVM);
116
117	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
118	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
119
120	pgmLock(pVM);
121
122	/*
123	* Copy loop on ram ranges.
124	*/
125	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
126	for (;;)
127	{
128	/* Find range. */
129	while (pRam && GCPhys > pRam->GCPhysLast)
130	pRam = pRam->CTX_SUFF(pNext);
131	/* Inside range or not? */
132	if (pRam && GCPhys >= pRam->GCPhys)
133	{
134	/*
135	* Must work our way thru this page by page.
136	*/
137	RTGCPHYS off = GCPhys - pRam->GCPhys;
138	while (off < pRam->cb)
139	{
140	unsigned iPage = off >> PAGE_SHIFT;
141	PPGMPAGE pPage = &pRam->aPages[iPage];
142
143	/*
144	* If the page has an ALL access handler, we'll have to
145	* delegate the job to EMT.
146	*/
147	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
148	{
149	pgmUnlock(pVM);
150
151	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 4,
152	pVM, &GCPhys, pvBuf, cbRead);
153	}
154	Assert(!PGM_PAGE_IS_MMIO(pPage));
155
156	/*
157	* Simple stuff, go ahead.
158	*/
159	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
160	if (cb > cbRead)
161	cb = cbRead;
162	const void *pvSrc;
163	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
164	if (RT_SUCCESS(rc))
165	memcpy(pvBuf, pvSrc, cb);
166	else
167	{
168	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
169	pRam->GCPhys + off, pPage, rc));
170	memset(pvBuf, 0xff, cb);
171	}
172
173	/* next page */
174	if (cb >= cbRead)
175	{
176	pgmUnlock(pVM);
177	return VINF_SUCCESS;
178	}
179	cbRead -= cb;
180	off += cb;
181	GCPhys += cb;
182	pvBuf = (char *)pvBuf + cb;
183	} /* walk pages in ram range. */
184	}
185	else
186	{
187	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
188
189	/*
190	* Unassigned address space.
191	*/
192	if (!pRam)
193	break;
194	size_t cb = pRam->GCPhys - GCPhys;
195	if (cb >= cbRead)
196	{
197	memset(pvBuf, 0xff, cbRead);
198	break;
199	}
200	memset(pvBuf, 0xff, cb);
201
202	cbRead -= cb;
203	pvBuf = (char *)pvBuf + cb;
204	GCPhys += cb;
205	}
206	} /* Ram range walk */
207
208	pgmUnlock(pVM);
209
210	return VINF_SUCCESS;
211	}
212
213
214	/**
215	* EMT worker for PGMR3PhysWriteExternal.
216	*/
217	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
218	{
219	/** @todo VERR_EM_NO_MEMORY */
220	PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
221	return VINF_SUCCESS;
222	}
223
224
225	/**
226	* Write to physical memory, external users.
227	*
228	* @returns VBox status code.
229	* @retval VINF_SUCCESS.
230	* @retval VERR_EM_NO_MEMORY.
231	*
232	* @param pVM VM Handle.
233	* @param GCPhys Physical address to write to.
234	* @param pvBuf What to write.
235	* @param cbWrite How many bytes to write.
236	* @param pszWho Who is writing. For tracking down who is writing
237	* after we've saved the state.
238	*
239	* @thread Any but EMTs.
240	*/
241	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void pvBuf, size_t cbWrite, const char pszWho)
242	{
243	VM_ASSERT_OTHER_THREAD(pVM);
244
245	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
246	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x pszWho=%s\n",
247	GCPhys, cbWrite, pszWho));
248	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
249	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
250
251	pgmLock(pVM);
252
253	/*
254	* Copy loop on ram ranges, stop when we hit something difficult.
255	*/
256	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
257	for (;;)
258	{
259	/* Find range. */
260	while (pRam && GCPhys > pRam->GCPhysLast)
261	pRam = pRam->CTX_SUFF(pNext);
262	/* Inside range or not? */
263	if (pRam && GCPhys >= pRam->GCPhys)
264	{
265	/*
266	* Must work our way thru this page by page.
267	*/
268	RTGCPTR off = GCPhys - pRam->GCPhys;
269	while (off < pRam->cb)
270	{
271	RTGCPTR iPage = off >> PAGE_SHIFT;
272	PPGMPAGE pPage = &pRam->aPages[iPage];
273
274	/*
275	* Is the page problematic, we have to do the work on the EMT.
276	*
277	* Allocating writable pages and access handlers are
278	* problematic, write monitored pages are simple and can be
279	* dealth with here.
280	*/
281	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
282	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
283	{
284	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
285	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
286	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
287	else
288	{
289	pgmUnlock(pVM);
290
291	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 4,
292	pVM, &GCPhys, pvBuf, cbWrite);
293	}
294	}
295	Assert(!PGM_PAGE_IS_MMIO(pPage));
296
297	/*
298	* Simple stuff, go ahead.
299	*/
300	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
301	if (cb > cbWrite)
302	cb = cbWrite;
303	void *pvDst;
304	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
305	if (RT_SUCCESS(rc))
306	memcpy(pvDst, pvBuf, cb);
307	else
308	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
309	pRam->GCPhys + off, pPage, rc));
310
311	/* next page */
312	if (cb >= cbWrite)
313	{
314	pgmUnlock(pVM);
315	return VINF_SUCCESS;
316	}
317
318	cbWrite -= cb;
319	off += cb;
320	GCPhys += cb;
321	pvBuf = (const char *)pvBuf + cb;
322	} /* walk pages in ram range */
323	}
324	else
325	{
326	/*
327	* Unassigned address space, skip it.
328	*/
329	if (!pRam)
330	break;
331	size_t cb = pRam->GCPhys - GCPhys;
332	if (cb >= cbWrite)
333	break;
334	cbWrite -= cb;
335	pvBuf = (const char *)pvBuf + cb;
336	GCPhys += cb;
337	}
338	} /* Ram range walk */
339
340	pgmUnlock(pVM);
341	return VINF_SUCCESS;
342	}
343
344
345	/**
346	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
347	*
348	* @returns see PGMR3PhysGCPhys2CCPtrExternal
349	* @param pVM The VM handle.
350	* @param pGCPhys Pointer to the guest physical address.
351	* @param ppv Where to store the mapping address.
352	* @param pLock Where to store the lock.
353	*/
354	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
355	{
356	/*
357	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
358	* an access handler after it succeeds.
359	*/
360	int rc = pgmLock(pVM);
361	AssertRCReturn(rc, rc);
362
363	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
364	if (RT_SUCCESS(rc))
365	{
366	PPGMPAGEMAPTLBE pTlbe;
367	int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
368	AssertFatalRC(rc2);
369	PPGMPAGE pPage = pTlbe->pPage;
370	if (PGM_PAGE_IS_MMIO(pPage))
371	{
372	PGMPhysReleasePageMappingLock(pVM, pLock);
373	rc = VERR_PGM_PHYS_PAGE_RESERVED;
374	}
375	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
376	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
377	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
378	#endif
379	)
380	{
381	/* We must flush any corresponding pgm pool page here, otherwise we'll
382	* not be informed about writes and keep bogus gst->shw mappings around.
383	*/
384	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
385	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
386	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
387	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
388	}
389	}
390
391	pgmUnlock(pVM);
392	return rc;
393	}
394
395
396	/**
397	* Requests the mapping of a guest page into ring-3, external threads.
398	*
399	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
400	* release it.
401	*
402	* This API will assume your intention is to write to the page, and will
403	* therefore replace shared and zero pages. If you do not intend to modify the
404	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
405	*
406	* @returns VBox status code.
407	* @retval VINF_SUCCESS on success.
408	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
409	* backing or if the page has any active access handlers. The caller
410	* must fall back on using PGMR3PhysWriteExternal.
411	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
412	*
413	* @param pVM The VM handle.
414	* @param GCPhys The guest physical address of the page that should be mapped.
415	* @param ppv Where to store the address corresponding to GCPhys.
416	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
417	*
418	* @remark Avoid calling this API from within critical sections (other than the
419	* PGM one) because of the deadlock risk when we have to delegating the
420	* task to an EMT.
421	* @thread Any.
422	*/
423	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
424	{
425	AssertPtr(ppv);
426	AssertPtr(pLock);
427
428	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
429
430	int rc = pgmLock(pVM);
431	AssertRCReturn(rc, rc);
432
433	/*
434	* Query the Physical TLB entry for the page (may fail).
435	*/
436	PPGMPAGEMAPTLBE pTlbe;
437	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
438	if (RT_SUCCESS(rc))
439	{
440	PPGMPAGE pPage = pTlbe->pPage;
441	if (PGM_PAGE_IS_MMIO(pPage))
442	rc = VERR_PGM_PHYS_PAGE_RESERVED;
443	else
444	{
445	/*
446	* If the page is shared, the zero page, or being write monitored
447	* it must be converted to an page that's writable if possible.
448	* We can only deal with write monitored pages here, the rest have
449	* to be on an EMT.
450	*/
451	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
452	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
453	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
454	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
455	#endif
456	)
457	{
458	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
459	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
460	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
461	&& !pgmPoolIsDirtyPage(pVM, GCPhys)
462	#endif
463	)
464	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
465	else
466	{
467	pgmUnlock(pVM);
468
469	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
470	pVM, &GCPhys, ppv, pLock);
471	}
472	}
473
474	/*
475	* Now, just perform the locking and calculate the return address.
476	*/
477	PPGMPAGEMAP pMap = pTlbe->pMap;
478	if (pMap)
479	pMap->cRefs++;
480
481	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
482	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
483	{
484	if (cLocks == 0)
485	pVM->pgm.s.cWriteLockedPages++;
486	PGM_PAGE_INC_WRITE_LOCKS(pPage);
487	}
488	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
489	{
490	PGM_PAGE_INC_WRITE_LOCKS(pPage);
491	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
492	if (pMap)
493	pMap->cRefs++; /* Extra ref to prevent it from going away. */
494	}
495
496	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
497	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
498	pLock->pvMap = pMap;
499	}
500	}
501
502	pgmUnlock(pVM);
503	return rc;
504	}
505
506
507	/**
508	* Requests the mapping of a guest page into ring-3, external threads.
509	*
510	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
511	* release it.
512	*
513	* @returns VBox status code.
514	* @retval VINF_SUCCESS on success.
515	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
516	* backing or if the page as an active ALL access handler. The caller
517	* must fall back on using PGMPhysRead.
518	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
519	*
520	* @param pVM The VM handle.
521	* @param GCPhys The guest physical address of the page that should be mapped.
522	* @param ppv Where to store the address corresponding to GCPhys.
523	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
524	*
525	* @remark Avoid calling this API from within critical sections (other than
526	* the PGM one) because of the deadlock risk.
527	* @thread Any.
528	*/
529	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
530	{
531	int rc = pgmLock(pVM);
532	AssertRCReturn(rc, rc);
533
534	/*
535	* Query the Physical TLB entry for the page (may fail).
536	*/
537	PPGMPAGEMAPTLBE pTlbe;
538	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
539	if (RT_SUCCESS(rc))
540	{
541	PPGMPAGE pPage = pTlbe->pPage;
542	#if 1
543	/* MMIO pages doesn't have any readable backing. */
544	if (PGM_PAGE_IS_MMIO(pPage))
545	rc = VERR_PGM_PHYS_PAGE_RESERVED;
546	#else
547	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
548	rc = VERR_PGM_PHYS_PAGE_RESERVED;
549	#endif
550	else
551	{
552	/*
553	* Now, just perform the locking and calculate the return address.
554	*/
555	PPGMPAGEMAP pMap = pTlbe->pMap;
556	if (pMap)
557	pMap->cRefs++;
558
559	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
560	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
561	{
562	if (cLocks == 0)
563	pVM->pgm.s.cReadLockedPages++;
564	PGM_PAGE_INC_READ_LOCKS(pPage);
565	}
566	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
567	{
568	PGM_PAGE_INC_READ_LOCKS(pPage);
569	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
570	if (pMap)
571	pMap->cRefs++; /* Extra ref to prevent it from going away. */
572	}
573
574	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
575	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
576	pLock->pvMap = pMap;
577	}
578	}
579
580	pgmUnlock(pVM);
581	return rc;
582	}
583
584
585	/**
586	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
587	*
588	* Called when anything was relocated.
589	*
590	* @param pVM Pointer to the shared VM structure.
591	*/
592	void pgmR3PhysRelinkRamRanges(PVM pVM)
593	{
594	PPGMRAMRANGE pCur;
595
596	#ifdef VBOX_STRICT
597	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
598	{
599	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
600	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
601	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
602	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
603	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
604	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
605	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
606	Assert( pCur2 == pCur
607	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
608	}
609	#endif
610
611	pCur = pVM->pgm.s.pRamRangesR3;
612	if (pCur)
613	{
614	pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
615	pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
616
617	for (; pCur->pNextR3; pCur = pCur->pNextR3)
618	{
619	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
620	pCur->pNextRC = pCur->pNextR3->pSelfRC;
621	}
622
623	Assert(pCur->pNextR0 == NIL_RTR0PTR);
624	Assert(pCur->pNextRC == NIL_RTRCPTR);
625	}
626	else
627	{
628	Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
629	Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
630	}
631	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
632	}
633
634
635	/**
636	* Links a new RAM range into the list.
637	*
638	* @param pVM Pointer to the shared VM structure.
639	* @param pNew Pointer to the new list entry.
640	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
641	*/
642	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
643	{
644	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
645	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
646	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
647
648	pgmLock(pVM);
649
650	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
651	pNew->pNextR3 = pRam;
652	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
653	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
654
655	if (pPrev)
656	{
657	pPrev->pNextR3 = pNew;
658	pPrev->pNextR0 = pNew->pSelfR0;
659	pPrev->pNextRC = pNew->pSelfRC;
660	}
661	else
662	{
663	pVM->pgm.s.pRamRangesR3 = pNew;
664	pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
665	pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
666	}
667	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
668	pgmUnlock(pVM);
669	}
670
671
672	/**
673	* Unlink an existing RAM range from the list.
674	*
675	* @param pVM Pointer to the shared VM structure.
676	* @param pRam Pointer to the new list entry.
677	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
678	*/
679	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
680	{
681	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
682	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
683	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
684
685	pgmLock(pVM);
686
687	PPGMRAMRANGE pNext = pRam->pNextR3;
688	if (pPrev)
689	{
690	pPrev->pNextR3 = pNext;
691	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
692	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
693	}
694	else
695	{
696	Assert(pVM->pgm.s.pRamRangesR3 == pRam);
697	pVM->pgm.s.pRamRangesR3 = pNext;
698	pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
699	pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
700	}
701	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
702	pgmUnlock(pVM);
703	}
704
705
706	/**
707	* Unlink an existing RAM range from the list.
708	*
709	* @param pVM Pointer to the shared VM structure.
710	* @param pRam Pointer to the new list entry.
711	*/
712	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
713	{
714	pgmLock(pVM);
715
716	/* find prev. */
717	PPGMRAMRANGE pPrev = NULL;
718	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
719	while (pCur != pRam)
720	{
721	pPrev = pCur;
722	pCur = pCur->pNextR3;
723	}
724	AssertFatal(pCur);
725
726	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
727	pgmUnlock(pVM);
728	}
729
730
731	/**
732	* Frees a range of pages, replacing them with ZERO pages of the specified type.
733	*
734	* @returns VBox status code.
735	* @param pVM The VM handle.
736	* @param pRam The RAM range in which the pages resides.
737	* @param GCPhys The address of the first page.
738	* @param GCPhysLast The address of the last page.
739	* @param uType The page type to replace then with.
740	*/
741	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
742	{
743	Assert(PGMIsLockOwner(pVM));
744	uint32_t cPendingPages = 0;
745	PGMMFREEPAGESREQ pReq;
746	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
747	AssertLogRelRCReturn(rc, rc);
748
749	/* Iterate the pages. */
750	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
751	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
752	while (cPagesLeft-- > 0)
753	{
754	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
755	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
756
757	PGM_PAGE_SET_TYPE(pPageDst, uType);
758
759	GCPhys += PAGE_SIZE;
760	pPageDst++;
761	}
762
763	if (cPendingPages)
764	{
765	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
766	AssertLogRelRCReturn(rc, rc);
767	}
768	GMMR3FreePagesCleanup(pReq);
769
770	return rc;
771	}
772
773	/**
774	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
775	*
776	* This is only called on one of the EMTs while the other ones are waiting for
777	* it to complete this function.
778	*
779	* @returns VINF_SUCCESS (VBox strict status code).
780	* @param pVM The VM handle.
781	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
782	* @param pvUser User parameter
783	*/
784	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
785	{
786	uintptr_t paUser = (uintptr_t )pvUser;
787	bool fInflate = !!paUser[0];
788	unsigned cPages = paUser[1];
789	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
790	uint32_t cPendingPages = 0;
791	PGMMFREEPAGESREQ pReq;
792	int rc;
793
794	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
795	pgmLock(pVM);
796
797	if (fInflate)
798	{
799	/* Replace pages with ZERO pages. */
800	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
801	if (RT_FAILURE(rc))
802	{
803	pgmUnlock(pVM);
804	AssertLogRelRC(rc);
805	return rc;
806	}
807
808	/* Iterate the pages. */
809	for (unsigned i = 0; i < cPages; i++)
810	{
811	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
812	if ( pPage == NULL
813	\|\| pPage->uTypeY != PGMPAGETYPE_RAM)
814	{
815	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], (pPage) ? pPage->uTypeY : 0));
816	break;
817	}
818
819	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i]);
820	if (RT_FAILURE(rc))
821	{
822	pgmUnlock(pVM);
823	AssertLogRelRC(rc);
824	return rc;
825	}
826	Assert(PGM_PAGE_IS_ZERO(pPage));
827	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_BALLOONED);
828	}
829
830	if (cPendingPages)
831	{
832	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
833	if (RT_FAILURE(rc))
834	{
835	pgmUnlock(pVM);
836	AssertLogRelRC(rc);
837	return rc;
838	}
839	}
840	GMMR3FreePagesCleanup(pReq);
841
842	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
843	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
844	}
845
846	/* Notify GMM about the balloon change. */
847	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
848	if (RT_SUCCESS(rc))
849	{
850	if (!fInflate)
851	{
852	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
853	pVM->pgm.s.cBalloonedPages -= cPages;
854	}
855	else
856	pVM->pgm.s.cBalloonedPages += cPages;
857	}
858
859	pgmUnlock(pVM);
860
861	/* Flush the recompiler's TLB as well. */
862	REMFlushTBs(pVM);
863
864	AssertLogRelRC(rc);
865	return rc;
866	}
867
868	/**
869	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
870	*
871	* @returns VBox status code.
872	* @param pVM The VM handle.
873	* @param fInflate Inflate or deflate memory balloon
874	* @param cPages Number of pages to free
875	* @param paPhysPage Array of guest physical addresses
876	*/
877	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
878	{
879	uintptr_t paUser[3];
880
881	paUser[0] = fInflate;
882	paUser[1] = cPages;
883	paUser[2] = (uintptr_t)paPhysPage;
884	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
885	AssertRC(rc);
886
887	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
888	RTMemFree(paPhysPage);
889	}
890
891	/**
892	* Inflate or deflate a memory balloon
893	*
894	* @returns VBox status code.
895	* @param pVM The VM handle.
896	* @param fInflate Inflate or deflate memory balloon
897	* @param cPages Number of pages to free
898	* @param paPhysPage Array of guest physical addresses
899	*/
900	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
901	{
902	int rc;
903
904	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
905	* In the SMP case we post a request packet to postpone the job.
906	*/
907	if (pVM->cCpus > 1)
908	{
909	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
910	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
911	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
912
913	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
914
915	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
916	AssertRC(rc);
917	}
918	else
919	{
920	uintptr_t paUser[3];
921
922	paUser[0] = fInflate;
923	paUser[1] = cPages;
924	paUser[2] = (uintptr_t)paPhysPage;
925	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
926	AssertRC(rc);
927	}
928	return rc;
929	}
930
931
932	/**
933	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
934	*
935	* @param pVM The VM handle.
936	* @param pNew The new RAM range.
937	* @param GCPhys The address of the RAM range.
938	* @param GCPhysLast The last address of the RAM range.
939	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
940	* if in HMA.
941	* @param R0PtrNew Ditto for R0.
942	* @param pszDesc The description.
943	* @param pPrev The previous RAM range (for linking).
944	*/
945	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
946	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
947	{
948	/*
949	* Initialize the range.
950	*/
951	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
952	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
953	pNew->GCPhys = GCPhys;
954	pNew->GCPhysLast = GCPhysLast;
955	pNew->cb = GCPhysLast - GCPhys + 1;
956	pNew->pszDesc = pszDesc;
957	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
958	pNew->pvR3 = NULL;
959	pNew->paLSPages = NULL;
960
961	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
962	RTGCPHYS iPage = cPages;
963	while (iPage-- > 0)
964	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
965
966	/* Update the page count stats. */
967	pVM->pgm.s.cZeroPages += cPages;
968	pVM->pgm.s.cAllPages += cPages;
969
970	/*
971	* Link it.
972	*/
973	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
974	}
975
976
977	/**
978	* Relocate a floating RAM range.
979	*
980	* @copydoc FNPGMRELOCATE.
981	*/
982	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
983	{
984	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
985	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
986	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
987
988	switch (enmMode)
989	{
990	case PGMRELOCATECALL_SUGGEST:
991	return true;
992	case PGMRELOCATECALL_RELOCATE:
993	{
994	/* Update myself and then relink all the ranges. */
995	pgmLock(pVM);
996	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
997	pgmR3PhysRelinkRamRanges(pVM);
998	pgmUnlock(pVM);
999	return true;
1000	}
1001
1002	default:
1003	AssertFailedReturn(false);
1004	}
1005	}
1006
1007
1008	/**
1009	* PGMR3PhysRegisterRam worker that registers a high chunk.
1010	*
1011	* @returns VBox status code.
1012	* @param pVM The VM handle.
1013	* @param GCPhys The address of the RAM.
1014	* @param cRamPages The number of RAM pages to register.
1015	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1016	* @param iChunk The chunk number.
1017	* @param pszDesc The RAM range description.
1018	* @param ppPrev Previous RAM range pointer. In/Out.
1019	*/
1020	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1021	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1022	PPGMRAMRANGE *ppPrev)
1023	{
1024	const char *pszDescChunk = iChunk == 0
1025	? pszDesc
1026	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1027	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1028
1029	/*
1030	* Allocate memory for the new chunk.
1031	*/
1032	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1033	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1034	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1035	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1036	void *pvChunk = NULL;
1037	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
1038	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1039	VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
1040	#else
1041	NULL,
1042	#endif
1043	paChunkPages);
1044	if (RT_SUCCESS(rc))
1045	{
1046	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1047	if (!VMMIsHwVirtExtForced(pVM))
1048	R0PtrChunk = NIL_RTR0PTR;
1049	#else
1050	R0PtrChunk = (uintptr_t)pvChunk;
1051	#endif
1052	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1053
1054	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1055
1056	/*
1057	* Create a mapping and map the pages into it.
1058	* We push these in below the HMA.
1059	*/
1060	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1061	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1062	if (RT_SUCCESS(rc))
1063	{
1064	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1065
1066	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1067	RTGCPTR GCPtrPage = GCPtrChunk;
1068	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1069	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1070	if (RT_SUCCESS(rc))
1071	{
1072	/*
1073	* Ok, init and link the range.
1074	*/
1075	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1076	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1077	*ppPrev = pNew;
1078	}
1079	}
1080
1081	if (RT_FAILURE(rc))
1082	SUPR3PageFreeEx(pvChunk, cChunkPages);
1083	}
1084
1085	RTMemTmpFree(paChunkPages);
1086	return rc;
1087	}
1088
1089
1090	/**
1091	* Sets up a range RAM.
1092	*
1093	* This will check for conflicting registrations, make a resource
1094	* reservation for the memory (with GMM), and setup the per-page
1095	* tracking structures (PGMPAGE).
1096	*
1097	* @returns VBox stutus code.
1098	* @param pVM Pointer to the shared VM structure.
1099	* @param GCPhys The physical address of the RAM.
1100	* @param cb The size of the RAM.
1101	* @param pszDesc The description - not copied, so, don't free or change it.
1102	*/
1103	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1104	{
1105	/*
1106	* Validate input.
1107	*/
1108	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1109	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1110	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1111	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1112	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1113	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1114	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1115	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1116
1117	pgmLock(pVM);
1118
1119	/*
1120	* Find range location and check for conflicts.
1121	* (We don't lock here because the locking by EMT is only required on update.)
1122	*/
1123	PPGMRAMRANGE pPrev = NULL;
1124	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1125	while (pRam && GCPhysLast >= pRam->GCPhys)
1126	{
1127	if ( GCPhysLast >= pRam->GCPhys
1128	&& GCPhys <= pRam->GCPhysLast)
1129	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1130	GCPhys, GCPhysLast, pszDesc,
1131	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1132	VERR_PGM_RAM_CONFLICT);
1133
1134	/* next */
1135	pPrev = pRam;
1136	pRam = pRam->pNextR3;
1137	}
1138
1139	/*
1140	* Register it with GMM (the API bitches).
1141	*/
1142	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1143	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1144	if (RT_FAILURE(rc))
1145	{
1146	pgmUnlock(pVM);
1147	return rc;
1148	}
1149
1150	if ( GCPhys >= _4G
1151	&& cPages > 256)
1152	{
1153	/*
1154	* The PGMRAMRANGE structures for the high memory can get very big.
1155	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1156	* allocation size limit there and also to avoid being unable to find
1157	* guest mapping space for them, we split this memory up into 4MB in
1158	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1159	* mode.
1160	*
1161	* The first and last page of each mapping are guard pages and marked
1162	* not-present. So, we've got 4186112 and 16769024 bytes available for
1163	* the PGMRAMRANGE structure.
1164	*
1165	* Note! The sizes used here will influence the saved state.
1166	*/
1167	uint32_t cbChunk;
1168	uint32_t cPagesPerChunk;
1169	if (VMMIsHwVirtExtForced(pVM))
1170	{
1171	cbChunk = 16U*_1M;
1172	cPagesPerChunk = 1048048; /* max ~1048059 */
1173	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1174	}
1175	else
1176	{
1177	cbChunk = 4U*_1M;
1178	cPagesPerChunk = 261616; /* max ~261627 */
1179	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1180	}
1181	AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1182
1183	RTGCPHYS cPagesLeft = cPages;
1184	RTGCPHYS GCPhysChunk = GCPhys;
1185	uint32_t iChunk = 0;
1186	while (cPagesLeft > 0)
1187	{
1188	uint32_t cPagesInChunk = cPagesLeft;
1189	if (cPagesInChunk > cPagesPerChunk)
1190	cPagesInChunk = cPagesPerChunk;
1191
1192	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1193	AssertRCReturn(rc, rc);
1194
1195	/* advance */
1196	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1197	cPagesLeft -= cPagesInChunk;
1198	iChunk++;
1199	}
1200	}
1201	else
1202	{
1203	/*
1204	* Allocate, initialize and link the new RAM range.
1205	*/
1206	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1207	PPGMRAMRANGE pNew;
1208	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1209	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1210
1211	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1212	}
1213	PGMPhysInvalidatePageMapTLB(pVM);
1214	pgmUnlock(pVM);
1215
1216	/*
1217	* Notify REM.
1218	*/
1219	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1220
1221	return VINF_SUCCESS;
1222	}
1223
1224
1225	/**
1226	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1227	*
1228	* We do this late in the init process so that all the ROM and MMIO ranges have
1229	* been registered already and we don't go wasting memory on them.
1230	*
1231	* @returns VBox status code.
1232	*
1233	* @param pVM Pointer to the shared VM structure.
1234	*/
1235	int pgmR3PhysRamPreAllocate(PVM pVM)
1236	{
1237	Assert(pVM->pgm.s.fRamPreAlloc);
1238	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1239
1240	/*
1241	* Walk the RAM ranges and allocate all RAM pages, halt at
1242	* the first allocation error.
1243	*/
1244	uint64_t cPages = 0;
1245	uint64_t NanoTS = RTTimeNanoTS();
1246	pgmLock(pVM);
1247	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1248	{
1249	PPGMPAGE pPage = &pRam->aPages[0];
1250	RTGCPHYS GCPhys = pRam->GCPhys;
1251	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1252	while (cLeft-- > 0)
1253	{
1254	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1255	{
1256	switch (PGM_PAGE_GET_STATE(pPage))
1257	{
1258	case PGM_PAGE_STATE_ZERO:
1259	{
1260	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1261	if (RT_FAILURE(rc))
1262	{
1263	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1264	pgmUnlock(pVM);
1265	return rc;
1266	}
1267	cPages++;
1268	break;
1269	}
1270
1271	case PGM_PAGE_STATE_BALLOONED:
1272	case PGM_PAGE_STATE_ALLOCATED:
1273	case PGM_PAGE_STATE_WRITE_MONITORED:
1274	case PGM_PAGE_STATE_SHARED:
1275	/* nothing to do here. */
1276	break;
1277	}
1278	}
1279
1280	/* next */
1281	pPage++;
1282	GCPhys += PAGE_SIZE;
1283	}
1284	}
1285	pgmUnlock(pVM);
1286	NanoTS = RTTimeNanoTS() - NanoTS;
1287
1288	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1289	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1290	return VINF_SUCCESS;
1291	}
1292
1293
1294	/**
1295	* Resets (zeros) the RAM.
1296	*
1297	* ASSUMES that the caller owns the PGM lock.
1298	*
1299	* @returns VBox status code.
1300	* @param pVM Pointer to the shared VM structure.
1301	*/
1302	int pgmR3PhysRamReset(PVM pVM)
1303	{
1304	Assert(PGMIsLockOwner(pVM));
1305
1306	/* Reset the memory balloon. */
1307	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1308	AssertRC(rc);
1309
1310	/*
1311	* We batch up pages that should be freed instead of calling GMM for
1312	* each and every one of them.
1313	*/
1314	uint32_t cPendingPages = 0;
1315	PGMMFREEPAGESREQ pReq;
1316	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1317	AssertLogRelRCReturn(rc, rc);
1318
1319	/*
1320	* Walk the ram ranges.
1321	*/
1322	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1323	{
1324	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1325	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1326
1327	if (!pVM->pgm.s.fRamPreAlloc)
1328	{
1329	/* Replace all RAM pages by ZERO pages. */
1330	while (iPage-- > 0)
1331	{
1332	PPGMPAGE pPage = &pRam->aPages[iPage];
1333	switch (PGM_PAGE_GET_TYPE(pPage))
1334	{
1335	case PGMPAGETYPE_RAM:
1336	/* Do not replace pages part of a 2 MB continuous range with zero pages, but zero them instead. */
1337	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
1338	{
1339	void *pvPage;
1340	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1341	AssertLogRelRCReturn(rc, rc);
1342	ASMMemZeroPage(pvPage);
1343	}
1344	else
1345	if ( !PGM_PAGE_IS_ZERO(pPage)
1346	&& !PGM_PAGE_IS_BALLOONED(pPage))
1347	{
1348	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1349	AssertLogRelRCReturn(rc, rc);
1350	}
1351	break;
1352
1353	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1354	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1355	break;
1356
1357	case PGMPAGETYPE_MMIO2:
1358	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1359	case PGMPAGETYPE_ROM:
1360	case PGMPAGETYPE_MMIO:
1361	break;
1362	default:
1363	AssertFailed();
1364	}
1365	} /* for each page */
1366	}
1367	else
1368	{
1369	/* Zero the memory. */
1370	while (iPage-- > 0)
1371	{
1372	PPGMPAGE pPage = &pRam->aPages[iPage];
1373	switch (PGM_PAGE_GET_TYPE(pPage))
1374	{
1375	case PGMPAGETYPE_RAM:
1376	switch (PGM_PAGE_GET_STATE(pPage))
1377	{
1378	case PGM_PAGE_STATE_ZERO:
1379	break;
1380
1381	case PGM_PAGE_STATE_BALLOONED:
1382	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1383	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
1384	break;
1385
1386	case PGM_PAGE_STATE_SHARED:
1387	case PGM_PAGE_STATE_WRITE_MONITORED:
1388	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1389	AssertLogRelRCReturn(rc, rc);
1390	/* no break */
1391
1392	case PGM_PAGE_STATE_ALLOCATED:
1393	{
1394	void *pvPage;
1395	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1396	AssertLogRelRCReturn(rc, rc);
1397	ASMMemZeroPage(pvPage);
1398	break;
1399	}
1400	}
1401	break;
1402
1403	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1404	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1405	break;
1406
1407	case PGMPAGETYPE_MMIO2:
1408	case PGMPAGETYPE_ROM_SHADOW:
1409	case PGMPAGETYPE_ROM:
1410	case PGMPAGETYPE_MMIO:
1411	break;
1412	default:
1413	AssertFailed();
1414
1415	}
1416	} /* for each page */
1417	}
1418
1419	}
1420
1421	/*
1422	* Finish off any pages pending freeing.
1423	*/
1424	if (cPendingPages)
1425	{
1426	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1427	AssertLogRelRCReturn(rc, rc);
1428	}
1429	GMMR3FreePagesCleanup(pReq);
1430
1431	return VINF_SUCCESS;
1432	}
1433
1434
1435	/**
1436	* This is the interface IOM is using to register an MMIO region.
1437	*
1438	* It will check for conflicts and ensure that a RAM range structure
1439	* is present before calling the PGMR3HandlerPhysicalRegister API to
1440	* register the callbacks.
1441	*
1442	* @returns VBox status code.
1443	*
1444	* @param pVM Pointer to the shared VM structure.
1445	* @param GCPhys The start of the MMIO region.
1446	* @param cb The size of the MMIO region.
1447	* @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1448	* @param pvUserR3 The user argument for R3.
1449	* @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1450	* @param pvUserR0 The user argument for R0.
1451	* @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1452	* @param pvUserRC The user argument for RC.
1453	* @param pszDesc The description of the MMIO region.
1454	*/
1455	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1456	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1457	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1458	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1459	R3PTRTYPE(const char *) pszDesc)
1460	{
1461	/*
1462	* Assert on some assumption.
1463	*/
1464	VM_ASSERT_EMT(pVM);
1465	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1466	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1467	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1468	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1469
1470	/*
1471	* Make sure there's a RAM range structure for the region.
1472	*/
1473	int rc;
1474	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1475	bool fRamExists = false;
1476	PPGMRAMRANGE pRamPrev = NULL;
1477	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1478	while (pRam && GCPhysLast >= pRam->GCPhys)
1479	{
1480	if ( GCPhysLast >= pRam->GCPhys
1481	&& GCPhys <= pRam->GCPhysLast)
1482	{
1483	/* Simplification: all within the same range. */
1484	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1485	&& GCPhysLast <= pRam->GCPhysLast,
1486	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1487	GCPhys, GCPhysLast, pszDesc,
1488	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1489	VERR_PGM_RAM_CONFLICT);
1490
1491	/* Check that it's all RAM or MMIO pages. */
1492	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1493	uint32_t cLeft = cb >> PAGE_SHIFT;
1494	while (cLeft-- > 0)
1495	{
1496	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1497	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1498	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1499	GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1500	VERR_PGM_RAM_CONFLICT);
1501	pPage++;
1502	}
1503
1504	/* Looks good. */
1505	fRamExists = true;
1506	break;
1507	}
1508
1509	/* next */
1510	pRamPrev = pRam;
1511	pRam = pRam->pNextR3;
1512	}
1513	PPGMRAMRANGE pNew;
1514	if (fRamExists)
1515	{
1516	pNew = NULL;
1517
1518	/*
1519	* Make all the pages in the range MMIO/ZERO pages, freeing any
1520	* RAM pages currently mapped here. This might not be 100% correct
1521	* for PCI memory, but we're doing the same thing for MMIO2 pages.
1522	*/
1523	rc = pgmLock(pVM);
1524	if (RT_SUCCESS(rc))
1525	{
1526	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1527	pgmUnlock(pVM);
1528	}
1529	AssertRCReturn(rc, rc);
1530	}
1531	else
1532	{
1533	pgmLock(pVM);
1534
1535	/*
1536	* No RAM range, insert an ad hoc one.
1537	*
1538	* Note that we don't have to tell REM about this range because
1539	* PGMHandlerPhysicalRegisterEx will do that for us.
1540	*/
1541	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1542
1543	const uint32_t cPages = cb >> PAGE_SHIFT;
1544	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1545	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1546	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1547
1548	/* Initialize the range. */
1549	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1550	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1551	pNew->GCPhys = GCPhys;
1552	pNew->GCPhysLast = GCPhysLast;
1553	pNew->cb = cb;
1554	pNew->pszDesc = pszDesc;
1555	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
1556	pNew->pvR3 = NULL;
1557	pNew->paLSPages = NULL;
1558
1559	uint32_t iPage = cPages;
1560	while (iPage-- > 0)
1561	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1562	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1563
1564	/* update the page count stats. */
1565	pVM->pgm.s.cPureMmioPages += cPages;
1566	pVM->pgm.s.cAllPages += cPages;
1567
1568	/* link it */
1569	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1570
1571	pgmUnlock(pVM);
1572	}
1573
1574	/*
1575	* Register the access handler.
1576	*/
1577	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1578	pfnHandlerR3, pvUserR3,
1579	pfnHandlerR0, pvUserR0,
1580	pfnHandlerRC, pvUserRC, pszDesc);
1581	if ( RT_FAILURE(rc)
1582	&& !fRamExists)
1583	{
1584	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
1585	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1586
1587	/* remove the ad hoc range. */
1588	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1589	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1590	MMHyperFree(pVM, pRam);
1591	}
1592	PGMPhysInvalidatePageMapTLB(pVM);
1593
1594	return rc;
1595	}
1596
1597
1598	/**
1599	* This is the interface IOM is using to register an MMIO region.
1600	*
1601	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
1602	* any ad hoc PGMRAMRANGE left behind.
1603	*
1604	* @returns VBox status code.
1605	* @param pVM Pointer to the shared VM structure.
1606	* @param GCPhys The start of the MMIO region.
1607	* @param cb The size of the MMIO region.
1608	*/
1609	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1610	{
1611	VM_ASSERT_EMT(pVM);
1612
1613	/*
1614	* First deregister the handler, then check if we should remove the ram range.
1615	*/
1616	int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1617	if (RT_SUCCESS(rc))
1618	{
1619	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1620	PPGMRAMRANGE pRamPrev = NULL;
1621	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1622	while (pRam && GCPhysLast >= pRam->GCPhys)
1623	{
1624	/** @todo We're being a bit too careful here. rewrite. */
1625	if ( GCPhysLast == pRam->GCPhysLast
1626	&& GCPhys == pRam->GCPhys)
1627	{
1628	Assert(pRam->cb == cb);
1629
1630	/*
1631	* See if all the pages are dead MMIO pages.
1632	*/
1633	uint32_t const cPages = cb >> PAGE_SHIFT;
1634	bool fAllMMIO = true;
1635	uint32_t iPage = 0;
1636	uint32_t cLeft = cPages;
1637	while (cLeft-- > 0)
1638	{
1639	PPGMPAGE pPage = &pRam->aPages[iPage];
1640	if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1641	/\|\| not-out-of-action later /)
1642	{
1643	fAllMMIO = false;
1644	Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1645	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1646	break;
1647	}
1648	Assert(PGM_PAGE_IS_ZERO(pPage));
1649	pPage++;
1650	}
1651	if (fAllMMIO)
1652	{
1653	/*
1654	* Ad-hoc range, unlink and free it.
1655	*/
1656	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
1657	GCPhys, GCPhysLast, pRam->pszDesc));
1658
1659	pVM->pgm.s.cAllPages -= cPages;
1660	pVM->pgm.s.cPureMmioPages -= cPages;
1661
1662	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1663	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1664	MMHyperFree(pVM, pRam);
1665	break;
1666	}
1667	}
1668
1669	/*
1670	* Range match? It will all be within one range (see PGMAllHandler.cpp).
1671	*/
1672	if ( GCPhysLast >= pRam->GCPhys
1673	&& GCPhys <= pRam->GCPhysLast)
1674	{
1675	Assert(GCPhys >= pRam->GCPhys);
1676	Assert(GCPhysLast <= pRam->GCPhysLast);
1677
1678	/*
1679	* Turn the pages back into RAM pages.
1680	*/
1681	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1682	uint32_t cLeft = cb >> PAGE_SHIFT;
1683	while (cLeft--)
1684	{
1685	PPGMPAGE pPage = &pRam->aPages[iPage];
1686	AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1687	AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1688	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1689	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1690	}
1691	break;
1692	}
1693
1694	/* next */
1695	pRamPrev = pRam;
1696	pRam = pRam->pNextR3;
1697	}
1698	}
1699
1700	PGMPhysInvalidatePageMapTLB(pVM);
1701	return rc;
1702	}
1703
1704
1705	/**
1706	* Locate a MMIO2 range.
1707	*
1708	* @returns Pointer to the MMIO2 range.
1709	* @param pVM Pointer to the shared VM structure.
1710	* @param pDevIns The device instance owning the region.
1711	* @param iRegion The region.
1712	*/
1713	DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1714	{
1715	/*
1716	* Search the list.
1717	*/
1718	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1719	if ( pCur->pDevInsR3 == pDevIns
1720	&& pCur->iRegion == iRegion)
1721	return pCur;
1722	return NULL;
1723	}
1724
1725
1726	/**
1727	* Allocate and register an MMIO2 region.
1728	*
1729	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1730	* RAM associated with a device. It is also non-shared memory with a
1731	* permanent ring-3 mapping and page backing (presently).
1732	*
1733	* A MMIO2 range may overlap with base memory if a lot of RAM
1734	* is configured for the VM, in which case we'll drop the base
1735	* memory pages. Presently we will make no attempt to preserve
1736	* anything that happens to be present in the base memory that
1737	* is replaced, this is of course incorrectly but it's too much
1738	* effort.
1739	*
1740	* @returns VBox status code.
1741	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1742	* @retval VERR_ALREADY_EXISTS if the region already exists.
1743	*
1744	* @param pVM Pointer to the shared VM structure.
1745	* @param pDevIns The device instance owning the region.
1746	* @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1747	* this number has to be the number of that region. Otherwise
1748	* it can be any number safe UINT8_MAX.
1749	* @param cb The size of the region. Must be page aligned.
1750	* @param fFlags Reserved for future use, must be zero.
1751	* @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1752	* @param pszDesc The description.
1753	*/
1754	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc)
1755	{
1756	/*
1757	* Validate input.
1758	*/
1759	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1760	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1761	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1762	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1763	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1764	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1765	AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1766	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1767	AssertReturn(cb, VERR_INVALID_PARAMETER);
1768	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1769
1770	const uint32_t cPages = cb >> PAGE_SHIFT;
1771	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1772	AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1773
1774	/*
1775	* For the 2nd+ instance, mangle the description string so it's unique.
1776	*/
1777	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
1778	{
1779	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1780	if (!pszDesc)
1781	return VERR_NO_MEMORY;
1782	}
1783
1784	/*
1785	* Try reserve and allocate the backing memory first as this is what is
1786	* most likely to fail.
1787	*/
1788	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1789	if (RT_SUCCESS(rc))
1790	{
1791	void *pvPages;
1792	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1793	if (RT_SUCCESS(rc))
1794	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
1795	if (RT_SUCCESS(rc))
1796	{
1797	memset(pvPages, 0, cPages * PAGE_SIZE);
1798
1799	/*
1800	* Create the MMIO2 range record for it.
1801	*/
1802	const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1803	PPGMMMIO2RANGE pNew;
1804	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1805	AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1806	if (RT_SUCCESS(rc))
1807	{
1808	pNew->pDevInsR3 = pDevIns;
1809	pNew->pvR3 = pvPages;
1810	//pNew->pNext = NULL;
1811	//pNew->fMapped = false;
1812	//pNew->fOverlapping = false;
1813	pNew->iRegion = iRegion;
1814	pNew->idSavedState = UINT8_MAX;
1815	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1816	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1817	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1818	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1819	pNew->RamRange.pszDesc = pszDesc;
1820	pNew->RamRange.cb = cb;
1821	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
1822	pNew->RamRange.pvR3 = pvPages;
1823	//pNew->RamRange.paLSPages = NULL;
1824
1825	uint32_t iPage = cPages;
1826	while (iPage-- > 0)
1827	{
1828	PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1829	paPages[iPage].Phys, NIL_GMM_PAGEID,
1830	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1831	}
1832
1833	/* update page count stats */
1834	pVM->pgm.s.cAllPages += cPages;
1835	pVM->pgm.s.cPrivatePages += cPages;
1836
1837	/*
1838	* Link it into the list.
1839	* Since there is no particular order, just push it.
1840	*/
1841	pgmLock(pVM);
1842	pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1843	pVM->pgm.s.pMmio2RangesR3 = pNew;
1844	pgmUnlock(pVM);
1845
1846	*ppv = pvPages;
1847	RTMemTmpFree(paPages);
1848	PGMPhysInvalidatePageMapTLB(pVM);
1849	return VINF_SUCCESS;
1850	}
1851
1852	SUPR3PageFreeEx(pvPages, cPages);
1853	}
1854	RTMemTmpFree(paPages);
1855	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1856	}
1857	if (pDevIns->iInstance > 0)
1858	MMR3HeapFree((void *)pszDesc);
1859	return rc;
1860	}
1861
1862
1863	/**
1864	* Deregisters and frees an MMIO2 region.
1865	*
1866	* Any physical (and virtual) access handlers registered for the region must
1867	* be deregistered before calling this function.
1868	*
1869	* @returns VBox status code.
1870	* @param pVM Pointer to the shared VM structure.
1871	* @param pDevIns The device instance owning the region.
1872	* @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1873	*/
1874	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1875	{
1876	/*
1877	* Validate input.
1878	*/
1879	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1880	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1881	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1882
1883	pgmLock(pVM);
1884	int rc = VINF_SUCCESS;
1885	unsigned cFound = 0;
1886	PPGMMMIO2RANGE pPrev = NULL;
1887	PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1888	while (pCur)
1889	{
1890	if ( pCur->pDevInsR3 == pDevIns
1891	&& ( iRegion == UINT32_MAX
1892	\|\| pCur->iRegion == iRegion))
1893	{
1894	cFound++;
1895
1896	/*
1897	* Unmap it if it's mapped.
1898	*/
1899	if (pCur->fMapped)
1900	{
1901	int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1902	AssertRC(rc2);
1903	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1904	rc = rc2;
1905	}
1906
1907	/*
1908	* Unlink it
1909	*/
1910	PPGMMMIO2RANGE pNext = pCur->pNextR3;
1911	if (pPrev)
1912	pPrev->pNextR3 = pNext;
1913	else
1914	pVM->pgm.s.pMmio2RangesR3 = pNext;
1915	pCur->pNextR3 = NULL;
1916
1917	/*
1918	* Free the memory.
1919	*/
1920	int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1921	AssertRC(rc2);
1922	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1923	rc = rc2;
1924
1925	uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1926	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1927	AssertRC(rc2);
1928	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1929	rc = rc2;
1930
1931	/* we're leaking hyper memory here if done at runtime. */
1932	#ifdef VBOX_STRICT
1933	VMSTATE const enmState = VMR3GetState(pVM);
1934	AssertMsg( enmState == VMSTATE_POWERING_OFF
1935	\|\| enmState == VMSTATE_POWERING_OFF_LS
1936	\|\| enmState == VMSTATE_OFF
1937	\|\| enmState == VMSTATE_OFF_LS
1938	\|\| enmState == VMSTATE_DESTROYING
1939	\|\| enmState == VMSTATE_TERMINATED
1940	\|\| enmState == VMSTATE_CREATING
1941	, ("%s\n", VMR3GetStateName(enmState)));
1942	#endif
1943	/*rc = MMHyperFree(pVM, pCur);
1944	AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1945
1946
1947	/* update page count stats */
1948	pVM->pgm.s.cAllPages -= cPages;
1949	pVM->pgm.s.cPrivatePages -= cPages;
1950
1951	/* next */
1952	pCur = pNext;
1953	}
1954	else
1955	{
1956	pPrev = pCur;
1957	pCur = pCur->pNextR3;
1958	}
1959	}
1960	PGMPhysInvalidatePageMapTLB(pVM);
1961	pgmUnlock(pVM);
1962	return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1963	}
1964
1965
1966	/**
1967	* Maps a MMIO2 region.
1968	*
1969	* This is done when a guest / the bios / state loading changes the
1970	* PCI config. The replacing of base memory has the same restrictions
1971	* as during registration, of course.
1972	*
1973	* @returns VBox status code.
1974	*
1975	* @param pVM Pointer to the shared VM structure.
1976	* @param pDevIns The
1977	*/
1978	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1979	{
1980	/*
1981	* Validate input
1982	*/
1983	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1984	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1985	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1986	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1987	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1988	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1989
1990	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1991	AssertReturn(pCur, VERR_NOT_FOUND);
1992	AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
1993	Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
1994	Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
1995
1996	const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
1997	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1998
1999	/*
2000	* Find our location in the ram range list, checking for
2001	* restriction we don't bother implementing yet (partially overlapping).
2002	*/
2003	bool fRamExists = false;
2004	PPGMRAMRANGE pRamPrev = NULL;
2005	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2006	while (pRam && GCPhysLast >= pRam->GCPhys)
2007	{
2008	if ( GCPhys <= pRam->GCPhysLast
2009	&& GCPhysLast >= pRam->GCPhys)
2010	{
2011	/* completely within? */
2012	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2013	&& GCPhysLast <= pRam->GCPhysLast,
2014	("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
2015	GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
2016	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2017	VERR_PGM_RAM_CONFLICT);
2018	fRamExists = true;
2019	break;
2020	}
2021
2022	/* next */
2023	pRamPrev = pRam;
2024	pRam = pRam->pNextR3;
2025	}
2026	if (fRamExists)
2027	{
2028	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2029	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2030	while (cPagesLeft-- > 0)
2031	{
2032	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2033	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
2034	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
2035	VERR_PGM_RAM_CONFLICT);
2036	pPage++;
2037	}
2038	}
2039	Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
2040	GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
2041
2042	/*
2043	* Make the changes.
2044	*/
2045	pgmLock(pVM);
2046
2047	pCur->RamRange.GCPhys = GCPhys;
2048	pCur->RamRange.GCPhysLast = GCPhysLast;
2049	pCur->fMapped = true;
2050	pCur->fOverlapping = fRamExists;
2051
2052	if (fRamExists)
2053	{
2054	/** @todo use pgmR3PhysFreePageRange here. */
2055	uint32_t cPendingPages = 0;
2056	PGMMFREEPAGESREQ pReq;
2057	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2058	AssertLogRelRCReturn(rc, rc);
2059
2060	/* replace the pages, freeing all present RAM pages. */
2061	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2062	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2063	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2064	while (cPagesLeft-- > 0)
2065	{
2066	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
2067	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
2068
2069	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
2070	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
2071	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
2072	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
2073
2074	pVM->pgm.s.cZeroPages--;
2075	GCPhys += PAGE_SIZE;
2076	pPageSrc++;
2077	pPageDst++;
2078	}
2079
2080	/* Flush physical page map TLB. */
2081	PGMPhysInvalidatePageMapTLB(pVM);
2082
2083	if (cPendingPages)
2084	{
2085	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2086	AssertLogRelRCReturn(rc, rc);
2087	}
2088	GMMR3FreePagesCleanup(pReq);
2089	pgmUnlock(pVM);
2090	}
2091	else
2092	{
2093	RTGCPHYS cb = pCur->RamRange.cb;
2094
2095	/* link in the ram range */
2096	pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
2097	pgmUnlock(pVM);
2098
2099	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
2100	}
2101
2102	PGMPhysInvalidatePageMapTLB(pVM);
2103	return VINF_SUCCESS;
2104	}
2105
2106
2107	/**
2108	* Unmaps a MMIO2 region.
2109	*
2110	* This is done when a guest / the bios / state loading changes the
2111	* PCI config. The replacing of base memory has the same restrictions
2112	* as during registration, of course.
2113	*/
2114	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2115	{
2116	/*
2117	* Validate input
2118	*/
2119	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2120	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2121	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2122	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2123	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2124	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2125
2126	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2127	AssertReturn(pCur, VERR_NOT_FOUND);
2128	AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
2129	AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
2130	Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
2131
2132	Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
2133	pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
2134
2135	/*
2136	* Unmap it.
2137	*/
2138	pgmLock(pVM);
2139
2140	RTGCPHYS GCPhysRangeREM;
2141	RTGCPHYS cbRangeREM;
2142	bool fInformREM;
2143	if (pCur->fOverlapping)
2144	{
2145	/* Restore the RAM pages we've replaced. */
2146	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2147	while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
2148	pRam = pRam->pNextR3;
2149
2150	RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
2151	Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
2152	PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2153	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2154	while (cPagesLeft-- > 0)
2155	{
2156	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
2157	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
2158	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
2159	PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
2160	PGM_PAGE_SET_PDE_TYPE(pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
2161
2162	pVM->pgm.s.cZeroPages++;
2163	pPageDst++;
2164	}
2165
2166	/* Flush physical page map TLB. */
2167	PGMPhysInvalidatePageMapTLB(pVM);
2168
2169	GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
2170	cbRangeREM = RTGCPHYS_MAX; /* ditto */
2171	fInformREM = false;
2172	}
2173	else
2174	{
2175	GCPhysRangeREM = pCur->RamRange.GCPhys;
2176	cbRangeREM = pCur->RamRange.cb;
2177	fInformREM = true;
2178
2179	pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
2180	}
2181
2182	pCur->RamRange.GCPhys = NIL_RTGCPHYS;
2183	pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
2184	pCur->fOverlapping = false;
2185	pCur->fMapped = false;
2186
2187	PGMPhysInvalidatePageMapTLB(pVM);
2188	pgmUnlock(pVM);
2189
2190	if (fInformREM)
2191	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2192
2193	return VINF_SUCCESS;
2194	}
2195
2196
2197	/**
2198	* Checks if the given address is an MMIO2 base address or not.
2199	*
2200	* @returns true/false accordingly.
2201	* @param pVM Pointer to the shared VM structure.
2202	* @param pDevIns The owner of the memory, optional.
2203	* @param GCPhys The address to check.
2204	*/
2205	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2206	{
2207	/*
2208	* Validate input
2209	*/
2210	VM_ASSERT_EMT_RETURN(pVM, false);
2211	AssertPtrReturn(pDevIns, false);
2212	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
2213	AssertReturn(GCPhys != 0, false);
2214	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
2215
2216	/*
2217	* Search the list.
2218	*/
2219	pgmLock(pVM);
2220	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2221	if (pCur->RamRange.GCPhys == GCPhys)
2222	{
2223	Assert(pCur->fMapped);
2224	pgmUnlock(pVM);
2225	return true;
2226	}
2227	pgmUnlock(pVM);
2228	return false;
2229	}
2230
2231
2232	/**
2233	* Gets the HC physical address of a page in the MMIO2 region.
2234	*
2235	* This is API is intended for MMHyper and shouldn't be called
2236	* by anyone else...
2237	*
2238	* @returns VBox status code.
2239	* @param pVM Pointer to the shared VM structure.
2240	* @param pDevIns The owner of the memory, optional.
2241	* @param iRegion The region.
2242	* @param off The page expressed an offset into the MMIO2 region.
2243	* @param pHCPhys Where to store the result.
2244	*/
2245	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2246	{
2247	/*
2248	* Validate input
2249	*/
2250	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2251	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2252	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2253
2254	pgmLock(pVM);
2255	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2256	AssertReturn(pCur, VERR_NOT_FOUND);
2257	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2258
2259	PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2260	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2261	pgmUnlock(pVM);
2262	return VINF_SUCCESS;
2263	}
2264
2265
2266	/**
2267	* Maps a portion of an MMIO2 region into kernel space (host).
2268	*
2269	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
2270	* or the VM is terminated.
2271	*
2272	* @return VBox status code.
2273	*
2274	* @param pVM Pointer to the shared VM structure.
2275	* @param pDevIns The device owning the MMIO2 memory.
2276	* @param iRegion The region.
2277	* @param off The offset into the region. Must be page aligned.
2278	* @param cb The number of bytes to map. Must be page aligned.
2279	* @param pszDesc Mapping description.
2280	* @param pR0Ptr Where to store the R0 address.
2281	*/
2282	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2283	const char *pszDesc, PRTR0PTR pR0Ptr)
2284	{
2285	/*
2286	* Validate input.
2287	*/
2288	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2289	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2290	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2291
2292	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2293	AssertReturn(pCur, VERR_NOT_FOUND);
2294	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2295	AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2296	AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2297
2298	/*
2299	* Pass the request on to the support library/driver.
2300	*/
2301	int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2302
2303	return rc;
2304	}
2305
2306
2307	/**
2308	* Registers a ROM image.
2309	*
2310	* Shadowed ROM images requires double the amount of backing memory, so,
2311	* don't use that unless you have to. Shadowing of ROM images is process
2312	* where we can select where the reads go and where the writes go. On real
2313	* hardware the chipset provides means to configure this. We provide
2314	* PGMR3PhysProtectROM() for this purpose.
2315	*
2316	* A read-only copy of the ROM image will always be kept around while we
2317	* will allocate RAM pages for the changes on demand (unless all memory
2318	* is configured to be preallocated).
2319	*
2320	* @returns VBox status.
2321	* @param pVM VM Handle.
2322	* @param pDevIns The device instance owning the ROM.
2323	* @param GCPhys First physical address in the range.
2324	* Must be page aligned!
2325	* @param cbRange The size of the range (in bytes).
2326	* Must be page aligned!
2327	* @param pvBinary Pointer to the binary data backing the ROM image.
2328	* This must be exactly \a cbRange in size.
2329	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2330	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2331	* @param pszDesc Pointer to description string. This must not be freed.
2332	*
2333	* @remark There is no way to remove the rom, automatically on device cleanup or
2334	* manually from the device yet. This isn't difficult in any way, it's
2335	* just not something we expect to be necessary for a while.
2336	*/
2337	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2338	const void pvBinary, uint32_t fFlags, const char pszDesc)
2339	{
2340	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2341	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2342
2343	/*
2344	* Validate input.
2345	*/
2346	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2347	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2348	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2349	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2350	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2351	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2352	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2353	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2354	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2355
2356	const uint32_t cPages = cb >> PAGE_SHIFT;
2357
2358	/*
2359	* Find the ROM location in the ROM list first.
2360	*/
2361	PPGMROMRANGE pRomPrev = NULL;
2362	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2363	while (pRom && GCPhysLast >= pRom->GCPhys)
2364	{
2365	if ( GCPhys <= pRom->GCPhysLast
2366	&& GCPhysLast >= pRom->GCPhys)
2367	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2368	GCPhys, GCPhysLast, pszDesc,
2369	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2370	VERR_PGM_RAM_CONFLICT);
2371	/* next */
2372	pRomPrev = pRom;
2373	pRom = pRom->pNextR3;
2374	}
2375
2376	/*
2377	* Find the RAM location and check for conflicts.
2378	*
2379	* Conflict detection is a bit different than for RAM
2380	* registration since a ROM can be located within a RAM
2381	* range. So, what we have to check for is other memory
2382	* types (other than RAM that is) and that we don't span
2383	* more than one RAM range (layz).
2384	*/
2385	bool fRamExists = false;
2386	PPGMRAMRANGE pRamPrev = NULL;
2387	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2388	while (pRam && GCPhysLast >= pRam->GCPhys)
2389	{
2390	if ( GCPhys <= pRam->GCPhysLast
2391	&& GCPhysLast >= pRam->GCPhys)
2392	{
2393	/* completely within? */
2394	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2395	&& GCPhysLast <= pRam->GCPhysLast,
2396	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2397	GCPhys, GCPhysLast, pszDesc,
2398	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2399	VERR_PGM_RAM_CONFLICT);
2400	fRamExists = true;
2401	break;
2402	}
2403
2404	/* next */
2405	pRamPrev = pRam;
2406	pRam = pRam->pNextR3;
2407	}
2408	if (fRamExists)
2409	{
2410	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2411	uint32_t cPagesLeft = cPages;
2412	while (cPagesLeft-- > 0)
2413	{
2414	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2415	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2416	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2417	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2418	Assert(PGM_PAGE_IS_ZERO(pPage));
2419	pPage++;
2420	}
2421	}
2422
2423	/*
2424	* Update the base memory reservation if necessary.
2425	*/
2426	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
2427	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2428	cExtraBaseCost += cPages;
2429	if (cExtraBaseCost)
2430	{
2431	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2432	if (RT_FAILURE(rc))
2433	return rc;
2434	}
2435
2436	/*
2437	* Allocate memory for the virgin copy of the RAM.
2438	*/
2439	PGMMALLOCATEPAGESREQ pReq;
2440	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2441	AssertRCReturn(rc, rc);
2442
2443	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2444	{
2445	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2446	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2447	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2448	}
2449
2450	pgmLock(pVM);
2451	rc = GMMR3AllocatePagesPerform(pVM, pReq);
2452	pgmUnlock(pVM);
2453	if (RT_FAILURE(rc))
2454	{
2455	GMMR3AllocatePagesCleanup(pReq);
2456	return rc;
2457	}
2458
2459	/*
2460	* Allocate the new ROM range and RAM range (if necessary).
2461	*/
2462	PPGMROMRANGE pRomNew;
2463	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2464	if (RT_SUCCESS(rc))
2465	{
2466	PPGMRAMRANGE pRamNew = NULL;
2467	if (!fRamExists)
2468	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2469	if (RT_SUCCESS(rc))
2470	{
2471	pgmLock(pVM);
2472
2473	/*
2474	* Initialize and insert the RAM range (if required).
2475	*/
2476	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2477	if (!fRamExists)
2478	{
2479	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2480	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2481	pRamNew->GCPhys = GCPhys;
2482	pRamNew->GCPhysLast = GCPhysLast;
2483	pRamNew->cb = cb;
2484	pRamNew->pszDesc = pszDesc;
2485	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
2486	pRamNew->pvR3 = NULL;
2487	pRamNew->paLSPages = NULL;
2488
2489	PPGMPAGE pPage = &pRamNew->aPages[0];
2490	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2491	{
2492	PGM_PAGE_INIT(pPage,
2493	pReq->aPages[iPage].HCPhysGCPhys,
2494	pReq->aPages[iPage].idPage,
2495	PGMPAGETYPE_ROM,
2496	PGM_PAGE_STATE_ALLOCATED);
2497
2498	pRomPage->Virgin = *pPage;
2499	}
2500
2501	pVM->pgm.s.cAllPages += cPages;
2502	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2503	}
2504	else
2505	{
2506	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2507	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2508	{
2509	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2510	PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2511	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2512	PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2513
2514	pRomPage->Virgin = *pPage;
2515	}
2516
2517	pRamNew = pRam;
2518
2519	pVM->pgm.s.cZeroPages -= cPages;
2520	}
2521	pVM->pgm.s.cPrivatePages += cPages;
2522
2523	/* Flush physical page map TLB. */
2524	PGMPhysInvalidatePageMapTLB(pVM);
2525
2526	pgmUnlock(pVM);
2527
2528
2529	/*
2530	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2531	*
2532	* If it's shadowed we'll register the handler after the ROM notification
2533	* so we get the access handler callbacks that we should. If it isn't
2534	* shadowed we'll do it the other way around to make REM use the built-in
2535	* ROM behavior and not the handler behavior (which is to route all access
2536	* to PGM atm).
2537	*/
2538	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2539	{
2540	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2541	rc = PGMR3HandlerPhysicalRegister(pVM,
2542	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2543	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2544	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2545	GCPhys, GCPhysLast,
2546	pgmR3PhysRomWriteHandler, pRomNew,
2547	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2548	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2549	}
2550	else
2551	{
2552	rc = PGMR3HandlerPhysicalRegister(pVM,
2553	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2554	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2555	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2556	GCPhys, GCPhysLast,
2557	pgmR3PhysRomWriteHandler, pRomNew,
2558	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2559	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2560	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2561	}
2562	if (RT_SUCCESS(rc))
2563	{
2564	pgmLock(pVM);
2565
2566	/*
2567	* Copy the image over to the virgin pages.
2568	* This must be done after linking in the RAM range.
2569	*/
2570	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2571	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2572	{
2573	void *pvDstPage;
2574	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
2575	if (RT_FAILURE(rc))
2576	{
2577	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2578	break;
2579	}
2580	memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2581	}
2582	if (RT_SUCCESS(rc))
2583	{
2584	/*
2585	* Initialize the ROM range.
2586	* Note that the Virgin member of the pages has already been initialized above.
2587	*/
2588	pRomNew->GCPhys = GCPhys;
2589	pRomNew->GCPhysLast = GCPhysLast;
2590	pRomNew->cb = cb;
2591	pRomNew->fFlags = fFlags;
2592	pRomNew->idSavedState = UINT8_MAX;
2593	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2594	pRomNew->pszDesc = pszDesc;
2595
2596	for (unsigned iPage = 0; iPage < cPages; iPage++)
2597	{
2598	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2599	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2600	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2601	}
2602
2603	/* update the page count stats for the shadow pages. */
2604	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2605	{
2606	pVM->pgm.s.cZeroPages += cPages;
2607	pVM->pgm.s.cAllPages += cPages;
2608	}
2609
2610	/*
2611	* Insert the ROM range, tell REM and return successfully.
2612	*/
2613	pRomNew->pNextR3 = pRom;
2614	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2615	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2616
2617	if (pRomPrev)
2618	{
2619	pRomPrev->pNextR3 = pRomNew;
2620	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2621	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2622	}
2623	else
2624	{
2625	pVM->pgm.s.pRomRangesR3 = pRomNew;
2626	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2627	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2628	}
2629
2630	PGMPhysInvalidatePageMapTLB(pVM);
2631	GMMR3AllocatePagesCleanup(pReq);
2632	pgmUnlock(pVM);
2633	return VINF_SUCCESS;
2634	}
2635
2636	/* bail out */
2637
2638	pgmUnlock(pVM);
2639	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2640	AssertRC(rc2);
2641	pgmLock(pVM);
2642	}
2643
2644	if (!fRamExists)
2645	{
2646	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2647	MMHyperFree(pVM, pRamNew);
2648	}
2649	}
2650	MMHyperFree(pVM, pRomNew);
2651	}
2652
2653	/** @todo Purge the mapping cache or something... */
2654	GMMR3FreeAllocatedPages(pVM, pReq);
2655	GMMR3AllocatePagesCleanup(pReq);
2656	pgmUnlock(pVM);
2657	return rc;
2658	}
2659
2660
2661	/**
2662	* \#PF Handler callback for ROM write accesses.
2663	*
2664	* @returns VINF_SUCCESS if the handler have carried out the operation.
2665	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2666	* @param pVM VM Handle.
2667	* @param GCPhys The physical address the guest is writing to.
2668	* @param pvPhys The HC mapping of that address.
2669	* @param pvBuf What the guest is reading/writing.
2670	* @param cbBuf How much it's reading/writing.
2671	* @param enmAccessType The access type.
2672	* @param pvUser User argument.
2673	*/
2674	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2675	{
2676	PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2677	const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2678	Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2679	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2680	Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2681
2682	if (enmAccessType == PGMACCESSTYPE_READ)
2683	{
2684	switch (pRomPage->enmProt)
2685	{
2686	/*
2687	* Take the default action.
2688	*/
2689	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2690	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2691	case PGMROMPROT_READ_ROM_WRITE_RAM:
2692	case PGMROMPROT_READ_RAM_WRITE_RAM:
2693	return VINF_PGM_HANDLER_DO_DEFAULT;
2694
2695	default:
2696	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2697	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2698	VERR_INTERNAL_ERROR);
2699	}
2700	}
2701	else
2702	{
2703	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2704	switch (pRomPage->enmProt)
2705	{
2706	/*
2707	* Ignore writes.
2708	*/
2709	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2710	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2711	return VINF_SUCCESS;
2712
2713	/*
2714	* Write to the ram page.
2715	*/
2716	case PGMROMPROT_READ_ROM_WRITE_RAM:
2717	case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's way simpler that way. */
2718	{
2719	/* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2720	Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2721
2722	/*
2723	* Take the lock, do lazy allocation, map the page and copy the data.
2724	*
2725	* Note that we have to bypass the mapping TLB since it works on
2726	* guest physical addresses and entering the shadow page would
2727	* kind of screw things up...
2728	*/
2729	int rc = pgmLock(pVM);
2730	AssertRC(rc);
2731
2732	PPGMPAGE pShadowPage = &pRomPage->Shadow;
2733	if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2734	{
2735	pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2736	AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2737	}
2738
2739	void *pvDstPage;
2740	rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
2741	if (RT_SUCCESS(rc))
2742	{
2743	memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2744	pRomPage->LiveSave.fWrittenTo = true;
2745	}
2746
2747	pgmUnlock(pVM);
2748	return rc;
2749	}
2750
2751	default:
2752	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2753	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2754	VERR_INTERNAL_ERROR);
2755	}
2756	}
2757	}
2758
2759
2760	/**
2761	* Called by PGMR3Reset to reset the shadow, switch to the virgin,
2762	* and verify that the virgin part is untouched.
2763	*
2764	* This is done after the normal memory has been cleared.
2765	*
2766	* ASSUMES that the caller owns the PGM lock.
2767	*
2768	* @param pVM The VM handle.
2769	*/
2770	int pgmR3PhysRomReset(PVM pVM)
2771	{
2772	Assert(PGMIsLockOwner(pVM));
2773	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2774	{
2775	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2776
2777	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2778	{
2779	/*
2780	* Reset the physical handler.
2781	*/
2782	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2783	AssertRCReturn(rc, rc);
2784
2785	/*
2786	* What we do with the shadow pages depends on the memory
2787	* preallocation option. If not enabled, we'll just throw
2788	* out all the dirty pages and replace them by the zero page.
2789	*/
2790	if (!pVM->pgm.s.fRamPreAlloc)
2791	{
2792	/* Free the dirty pages. */
2793	uint32_t cPendingPages = 0;
2794	PGMMFREEPAGESREQ pReq;
2795	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2796	AssertRCReturn(rc, rc);
2797
2798	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2799	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
2800	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
2801	{
2802	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2803	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2804	AssertLogRelRCReturn(rc, rc);
2805	}
2806
2807	if (cPendingPages)
2808	{
2809	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2810	AssertLogRelRCReturn(rc, rc);
2811	}
2812	GMMR3FreePagesCleanup(pReq);
2813	}
2814	else
2815	{
2816	/* clear all the shadow pages. */
2817	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2818	{
2819	Assert(!PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
2820	void *pvDstPage;
2821	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2822	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
2823	if (RT_FAILURE(rc))
2824	break;
2825	ASMMemZeroPage(pvDstPage);
2826	}
2827	AssertRCReturn(rc, rc);
2828	}
2829	}
2830
2831	#ifdef VBOX_STRICT
2832	/*
2833	* Verify that the virgin page is unchanged if possible.
2834	*/
2835	if (pRom->pvOriginal)
2836	{
2837	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
2838	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2839	{
2840	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2841	void const *pvDstPage;
2842	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
2843	if (RT_FAILURE(rc))
2844	break;
2845	if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2846	LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2847	GCPhys, pRom->pszDesc));
2848	}
2849	}
2850	#endif
2851	}
2852
2853	return VINF_SUCCESS;
2854	}
2855
2856
2857	/**
2858	* Change the shadowing of a range of ROM pages.
2859	*
2860	* This is intended for implementing chipset specific memory registers
2861	* and will not be very strict about the input. It will silently ignore
2862	* any pages that are not the part of a shadowed ROM.
2863	*
2864	* @returns VBox status code.
2865	* @retval VINF_PGM_SYNC_CR3
2866	*
2867	* @param pVM Pointer to the shared VM structure.
2868	* @param GCPhys Where to start. Page aligned.
2869	* @param cb How much to change. Page aligned.
2870	* @param enmProt The new ROM protection.
2871	*/
2872	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2873	{
2874	/*
2875	* Check input
2876	*/
2877	if (!cb)
2878	return VINF_SUCCESS;
2879	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2880	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2881	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2882	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2883	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2884
2885	/*
2886	* Process the request.
2887	*/
2888	pgmLock(pVM);
2889	int rc = VINF_SUCCESS;
2890	bool fFlushTLB = false;
2891	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2892	{
2893	if ( GCPhys <= pRom->GCPhysLast
2894	&& GCPhysLast >= pRom->GCPhys
2895	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2896	{
2897	/*
2898	* Iterate the relevant pages and make necessary the changes.
2899	*/
2900	bool fChanges = false;
2901	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2902	? pRom->cb >> PAGE_SHIFT
2903	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2904	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2905	iPage < cPages;
2906	iPage++)
2907	{
2908	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2909	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2910	{
2911	fChanges = true;
2912
2913	/* flush references to the page. */
2914	PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2915	int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage, &fFlushTLB);
2916	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
2917	rc = rc2;
2918
2919	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2920	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2921
2922	pOld = pRamPage;
2923	pRamPage = pNew;
2924	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2925	}
2926	pRomPage->enmProt = enmProt;
2927	}
2928
2929	/*
2930	* Reset the access handler if we made changes, no need
2931	* to optimize this.
2932	*/
2933	if (fChanges)
2934	{
2935	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2936	if (RT_FAILURE(rc2))
2937	{
2938	pgmUnlock(pVM);
2939	AssertRC(rc);
2940	return rc2;
2941	}
2942	}
2943
2944	/* Advance - cb isn't updated. */
2945	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2946	}
2947	}
2948	pgmUnlock(pVM);
2949	if (fFlushTLB)
2950	PGM_INVL_ALL_VCPU_TLBS(pVM);
2951
2952	return rc;
2953	}
2954
2955
2956	/**
2957	* Sets the Address Gate 20 state.
2958	*
2959	* @param pVCpu The VCPU to operate on.
2960	* @param fEnable True if the gate should be enabled.
2961	* False if the gate should be disabled.
2962	*/
2963	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
2964	{
2965	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
2966	if (pVCpu->pgm.s.fA20Enabled != fEnable)
2967	{
2968	pVCpu->pgm.s.fA20Enabled = fEnable;
2969	pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2970	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
2971	/** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2972	}
2973	}
2974
2975
2976	/**
2977	* Tree enumeration callback for dealing with age rollover.
2978	* It will perform a simple compression of the current age.
2979	*/
2980	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2981	{
2982	Assert(PGMIsLockOwner((PVM)pvUser));
2983	/* Age compression - ASSUMES iNow == 4. */
2984	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2985	if (pChunk->iAge >= UINT32_C(0xffffff00))
2986	pChunk->iAge = 3;
2987	else if (pChunk->iAge >= UINT32_C(0xfffff000))
2988	pChunk->iAge = 2;
2989	else if (pChunk->iAge)
2990	pChunk->iAge = 1;
2991	else /* iAge = 0 */
2992	pChunk->iAge = 4;
2993
2994	/* reinsert */
2995	PVM pVM = (PVM)pvUser;
2996	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2997	pChunk->AgeCore.Key = pChunk->iAge;
2998	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2999	return 0;
3000	}
3001
3002
3003	/**
3004	* Tree enumeration callback that updates the chunks that have
3005	* been used since the last
3006	*/
3007	static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
3008	{
3009	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3010	if (!pChunk->iAge)
3011	{
3012	PVM pVM = (PVM)pvUser;
3013	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
3014	pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
3015	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3016	}
3017
3018	return 0;
3019	}
3020
3021
3022	/**
3023	* Performs ageing of the ring-3 chunk mappings.
3024	*
3025	* @param pVM The VM handle.
3026	*/
3027	VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
3028	{
3029	pgmLock(pVM);
3030	pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
3031	pVM->pgm.s.ChunkR3Map.iNow++;
3032	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
3033	{
3034	pVM->pgm.s.ChunkR3Map.iNow = 4;
3035	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
3036	}
3037	else
3038	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingCallback, pVM);
3039	pgmUnlock(pVM);
3040	}
3041
3042
3043	/**
3044	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
3045	*/
3046	typedef struct PGMR3PHYSCHUNKUNMAPCB
3047	{
3048	PVM pVM; /*< The VM handle. /
3049	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
3050	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
3051
3052
3053	/**
3054	* Callback used to find the mapping that's been unused for
3055	* the longest time.
3056	*/
3057	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
3058	{
3059	do
3060	{
3061	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
3062	if ( pChunk->iAge
3063	&& !pChunk->cRefs)
3064	{
3065	/*
3066	* Check that it's not in any of the TLBs.
3067	*/
3068	PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
3069	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3070	if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
3071	{
3072	pChunk = NULL;
3073	break;
3074	}
3075	if (pChunk)
3076	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
3077	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
3078	{
3079	pChunk = NULL;
3080	break;
3081	}
3082	if (pChunk)
3083	{
3084	((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
3085	return 1; /* done */
3086	}
3087	}
3088
3089	/* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
3090	pNode = pNode->pList;
3091	} while (pNode);
3092	return 0;
3093	}
3094
3095
3096	/**
3097	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
3098	*
3099	* The candidate will not be part of any TLBs, so no need to flush
3100	* anything afterwards.
3101	*
3102	* @returns Chunk id.
3103	* @param pVM The VM handle.
3104	*/
3105	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
3106	{
3107	Assert(PGMIsLockOwner(pVM));
3108
3109	/*
3110	* Do tree ageing first?
3111	*/
3112	if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
3113	PGMR3PhysChunkAgeing(pVM);
3114
3115	/*
3116	* Enumerate the age tree starting with the left most node.
3117	*/
3118	PGMR3PHYSCHUNKUNMAPCB Args;
3119	Args.pVM = pVM;
3120	Args.pChunk = NULL;
3121	if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
3122	return Args.pChunk->Core.Key;
3123	return INT32_MAX;
3124	}
3125
3126
3127	/**
3128	* Maps the given chunk into the ring-3 mapping cache.
3129	*
3130	* This will call ring-0.
3131	*
3132	* @returns VBox status code.
3133	* @param pVM The VM handle.
3134	* @param idChunk The chunk in question.
3135	* @param ppChunk Where to store the chunk tracking structure.
3136	*
3137	* @remarks Called from within the PGM critical section.
3138	*/
3139	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
3140	{
3141	int rc;
3142
3143	Assert(PGMIsLockOwner(pVM));
3144	/*
3145	* Allocate a new tracking structure first.
3146	*/
3147	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3148	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
3149	#else
3150	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
3151	#endif
3152	AssertReturn(pChunk, VERR_NO_MEMORY);
3153	pChunk->Core.Key = idChunk;
3154	pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
3155	pChunk->iAge = 0;
3156	pChunk->cRefs = 0;
3157	pChunk->cPermRefs = 0;
3158	pChunk->pv = NULL;
3159
3160	/*
3161	* Request the ring-0 part to map the chunk in question and if
3162	* necessary unmap another one to make space in the mapping cache.
3163	*/
3164	GMMMAPUNMAPCHUNKREQ Req;
3165	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3166	Req.Hdr.cbReq = sizeof(Req);
3167	Req.pvR3 = NULL;
3168	Req.idChunkMap = idChunk;
3169	Req.idChunkUnmap = NIL_GMM_CHUNKID;
3170	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3171	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
3172	/** @todo This is wrong. Any thread in the VM process should be able to do this,
3173	* there are depenenecies on this. What currently saves the day is that
3174	* we don't unmap anything and that all non-zero memory will therefore
3175	* be present when non-EMTs tries to access it. */
3176	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3177	if (RT_SUCCESS(rc))
3178	{
3179	/*
3180	* Update the tree.
3181	*/
3182	/* insert the new one. */
3183	AssertPtr(Req.pvR3);
3184	pChunk->pv = Req.pvR3;
3185	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
3186	AssertRelease(fRc);
3187	pVM->pgm.s.ChunkR3Map.c++;
3188
3189	fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3190	AssertRelease(fRc);
3191
3192	/* remove the unmapped one. */
3193	if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
3194	{
3195	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
3196	AssertRelease(pUnmappedChunk);
3197	pUnmappedChunk->pv = NULL;
3198	pUnmappedChunk->Core.Key = UINT32_MAX;
3199	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3200	MMR3HeapFree(pUnmappedChunk);
3201	#else
3202	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3203	#endif
3204	pVM->pgm.s.ChunkR3Map.c--;
3205
3206	/* Chunk removed, so clear the page map TBL as well (might still be referenced). */
3207	PGMPhysInvalidatePageMapTLB(pVM);
3208	}
3209	}
3210	else
3211	{
3212	AssertRC(rc);
3213	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3214	MMR3HeapFree(pChunk);
3215	#else
3216	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
3217	#endif
3218	pChunk = NULL;
3219	}
3220
3221	*ppChunk = pChunk;
3222	return rc;
3223	}
3224
3225
3226	/**
3227	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3228	*
3229	* @returns see pgmR3PhysChunkMap.
3230	* @param pVM The VM handle.
3231	* @param idChunk The chunk to map.
3232	*/
3233	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3234	{
3235	PPGMCHUNKR3MAP pChunk;
3236	int rc;
3237
3238	pgmLock(pVM);
3239	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3240	pgmUnlock(pVM);
3241	return rc;
3242	}
3243
3244
3245	/**
3246	* Invalidates the TLB for the ring-3 mapping cache.
3247	*
3248	* @param pVM The VM handle.
3249	*/
3250	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3251	{
3252	pgmLock(pVM);
3253	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3254	{
3255	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3256	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3257	}
3258	/* The page map TLB references chunks, so invalidate that one too. */
3259	PGMPhysInvalidatePageMapTLB(pVM);
3260	pgmUnlock(pVM);
3261	}
3262
3263
3264	/**
3265	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_PAGE to allocate a large (2MB) page
3266	* for use with a nested paging PDE.
3267	*
3268	* @returns The following VBox status codes.
3269	* @retval VINF_SUCCESS on success.
3270	* @retval VINF_EM_NO_MEMORY if we're out of memory.
3271	*
3272	* @param pVM The VM handle.
3273	* @param GCPhys GC physical start address of the 2 MB range
3274	*/
3275	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
3276	{
3277	pgmLock(pVM);
3278
3279	STAM_PROFILE_START(&pVM->pgm.s.StatAllocLargePage, a);
3280	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
3281	STAM_PROFILE_STOP(&pVM->pgm.s.StatAllocLargePage, a);
3282	if (RT_SUCCESS(rc))
3283	{
3284	Assert(pVM->pgm.s.cLargeHandyPages == 1);
3285
3286	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
3287	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
3288
3289	void *pv;
3290
3291	/* Map the large page into our address space.
3292	*
3293	* Note: assuming that within the 2 MB range:
3294	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
3295	* - user space mapping is continuous as well
3296	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
3297	*/
3298	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
3299	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", idPage, HCPhys, rc));
3300
3301	if (RT_SUCCESS(rc))
3302	{
3303	/*
3304	* Clear the pages.
3305	*/
3306	STAM_PROFILE_START(&pVM->pgm.s.StatClearLargePage, b);
3307	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
3308	{
3309	ASMMemZeroPage(pv);
3310
3311	PPGMPAGE pPage;
3312	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
3313	AssertRC(rc);
3314
3315	Assert(PGM_PAGE_IS_ZERO(pPage));
3316	STAM_COUNTER_INC(&pVM->pgm.s.StatRZPageReplaceZero);
3317	pVM->pgm.s.cZeroPages--;
3318
3319	/*
3320	* Do the PGMPAGE modifications.
3321	*/
3322	pVM->pgm.s.cPrivatePages++;
3323	PGM_PAGE_SET_HCPHYS(pPage, HCPhys);
3324	PGM_PAGE_SET_PAGEID(pPage, idPage);
3325	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
3326	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_PDE);
3327
3328	/* Somewhat dirty assumption that page ids are increasing. */
3329	idPage++;
3330
3331	HCPhys += PAGE_SIZE;
3332	GCPhys += PAGE_SIZE;
3333
3334	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
3335
3336	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
3337	}
3338	STAM_PROFILE_STOP(&pVM->pgm.s.StatClearLargePage, b);
3339
3340	/* Flush all TLBs. */
3341	PGM_INVL_ALL_VCPU_TLBS(pVM);
3342	PGMPhysInvalidatePageMapTLB(pVM);
3343	}
3344	pVM->pgm.s.cLargeHandyPages = 0;
3345	}
3346
3347	pgmUnlock(pVM);
3348	return rc;
3349	}
3350
3351
3352	/**
3353	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3354	*
3355	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3356	* signal and clear the out of memory condition. When contracted, this API is
3357	* used to try clear the condition when the user wants to resume.
3358	*
3359	* @returns The following VBox status codes.
3360	* @retval VINF_SUCCESS on success. FFs cleared.
3361	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3362	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3363	*
3364	* @param pVM The VM handle.
3365	*
3366	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3367	* in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3368	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3369	* handler.
3370	*/
3371	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3372	{
3373	pgmLock(pVM);
3374
3375	/*
3376	* Allocate more pages, noting down the index of the first new page.
3377	*/
3378	uint32_t iClear = pVM->pgm.s.cHandyPages;
3379	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3380	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3381	int rcAlloc = VINF_SUCCESS;
3382	int rcSeed = VINF_SUCCESS;
3383	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3384	while (rc == VERR_GMM_SEED_ME)
3385	{
3386	void *pvChunk;
3387	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3388	if (RT_SUCCESS(rc))
3389	{
3390	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3391	if (RT_FAILURE(rc))
3392	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3393	}
3394	if (RT_SUCCESS(rc))
3395	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3396	}
3397
3398	if (RT_SUCCESS(rc))
3399	{
3400	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3401	Assert(pVM->pgm.s.cHandyPages > 0);
3402	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3403	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3404
3405	/*
3406	* Clear the pages.
3407	*/
3408	while (iClear < pVM->pgm.s.cHandyPages)
3409	{
3410	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3411	void *pv;
3412	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3413	AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3414	ASMMemZeroPage(pv);
3415	iClear++;
3416	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3417	}
3418	}
3419	else
3420	{
3421	/*
3422	* We should never get here unless there is a genuine shortage of
3423	* memory (or some internal error). Flag the error so the VM can be
3424	* suspended ASAP and the user informed. If we're totally out of
3425	* handy pages we will return failure.
3426	*/
3427	/* Report the failure. */
3428	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3429	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3430	rc, rcAlloc, rcSeed,
3431	pVM->pgm.s.cHandyPages,
3432	pVM->pgm.s.cAllPages,
3433	pVM->pgm.s.cPrivatePages,
3434	pVM->pgm.s.cSharedPages,
3435	pVM->pgm.s.cZeroPages));
3436	if ( rc != VERR_NO_MEMORY
3437	&& rc != VERR_LOCK_FAILED)
3438	{
3439	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3440	{
3441	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3442	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3443	pVM->pgm.s.aHandyPages[i].idSharedPage));
3444	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3445	if (idPage != NIL_GMM_PAGEID)
3446	{
3447	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3448	pRam;
3449	pRam = pRam->pNextR3)
3450	{
3451	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3452	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3453	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3454	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3455	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3456	}
3457	}
3458	}
3459	}
3460
3461	/* Set the FFs and adjust rc. */
3462	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3463	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3464	if ( rc == VERR_NO_MEMORY
3465	\|\| rc == VERR_LOCK_FAILED)
3466	rc = VINF_EM_NO_MEMORY;
3467	}
3468
3469	pgmUnlock(pVM);
3470	return rc;
3471	}
3472
3473
3474	/**
3475	* Frees the specified RAM page and replaces it with the ZERO page.
3476	*
3477	* This is used by ballooning, remapping MMIO2 and RAM reset.
3478	*
3479	* @param pVM Pointer to the shared VM structure.
3480	* @param pReq Pointer to the request.
3481	* @param pPage Pointer to the page structure.
3482	* @param GCPhys The guest physical address of the page, if applicable.
3483	*
3484	* @remarks The caller must own the PGM lock.
3485	*/
3486	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3487	{
3488	/*
3489	* Assert sanity.
3490	*/
3491	Assert(PGMIsLockOwner(pVM));
3492	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3493	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3494	{
3495	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3496	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3497	}
3498
3499	if ( PGM_PAGE_IS_ZERO(pPage)
3500	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3501	return VINF_SUCCESS;
3502
3503	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3504	Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3505	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3506	\|\| idPage > GMM_PAGEID_LAST
3507	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3508	{
3509	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3510	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3511	}
3512
3513	/* update page count stats. */
3514	if (PGM_PAGE_IS_SHARED(pPage))
3515	pVM->pgm.s.cSharedPages--;
3516	else
3517	pVM->pgm.s.cPrivatePages--;
3518	pVM->pgm.s.cZeroPages++;
3519
3520	/* Deal with write monitored pages. */
3521	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
3522	{
3523	PGM_PAGE_SET_WRITTEN_TO(pPage);
3524	pVM->pgm.s.cWrittenToPages++;
3525	}
3526
3527	/*
3528	* pPage = ZERO page.
3529	*/
3530	PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3531	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3532	PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3533	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
3534
3535	/* Flush physical page map TLB entry. */
3536	PGMPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
3537
3538	/*
3539	* Make sure it's not in the handy page array.
3540	*/
3541	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3542	{
3543	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3544	{
3545	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3546	break;
3547	}
3548	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3549	{
3550	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3551	break;
3552	}
3553	}
3554
3555	/*
3556	* Push it onto the page array.
3557	*/
3558	uint32_t iPage = *pcPendingPages;
3559	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3560	*pcPendingPages += 1;
3561
3562	pReq->aPages[iPage].idPage = idPage;
3563
3564	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3565	return VINF_SUCCESS;
3566
3567	/*
3568	* Flush the pages.
3569	*/
3570	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3571	if (RT_SUCCESS(rc))
3572	{
3573	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3574	*pcPendingPages = 0;
3575	}
3576	return rc;
3577	}
3578
3579
3580	/**
3581	* Converts a GC physical address to a HC ring-3 pointer, with some
3582	* additional checks.
3583	*
3584	* @returns VBox status code.
3585	* @retval VINF_SUCCESS on success.
3586	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3587	* access handler of some kind.
3588	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3589	* accesses or is odd in any way.
3590	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3591	*
3592	* @param pVM The VM handle.
3593	* @param GCPhys The GC physical address to convert.
3594	* @param fWritable Whether write access is required.
3595	* @param ppv Where to store the pointer corresponding to GCPhys on
3596	* success.
3597	*/
3598	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3599	{
3600	pgmLock(pVM);
3601
3602	PPGMRAMRANGE pRam;
3603	PPGMPAGE pPage;
3604	int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3605	if (RT_SUCCESS(rc))
3606	{
3607	if (PGM_PAGE_IS_BALLOONED(pPage))
3608	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3609	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3610	rc = VINF_SUCCESS;
3611	else
3612	{
3613	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3614	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3615	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3616	{
3617	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3618	* in -norawr0 mode. */
3619	if (fWritable)
3620	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3621	}
3622	else
3623	{
3624	/* Temporarily disabled physical handler(s), since the recompiler
3625	doesn't get notified when it's reset we'll have to pretend it's
3626	operating normally. */
3627	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3628	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3629	else
3630	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3631	}
3632	}
3633	if (RT_SUCCESS(rc))
3634	{
3635	int rc2;
3636
3637	/* Make sure what we return is writable. */
3638	if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3639	switch (PGM_PAGE_GET_STATE(pPage))
3640	{
3641	case PGM_PAGE_STATE_ALLOCATED:
3642	break;
3643	case PGM_PAGE_STATE_BALLOONED:
3644	AssertFailed();
3645	break;
3646	case PGM_PAGE_STATE_ZERO:
3647	case PGM_PAGE_STATE_SHARED:
3648	case PGM_PAGE_STATE_WRITE_MONITORED:
3649	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3650	AssertLogRelRCReturn(rc2, rc2);
3651	break;
3652	}
3653
3654	/* Get a ring-3 mapping of the address. */
3655	PPGMPAGER3MAPTLBE pTlbe;
3656	rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3657	AssertLogRelRCReturn(rc2, rc2);
3658	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
3659	/** @todo mapping/locking hell; this isn't horribly efficient since
3660	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
3661
3662	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
3663	}
3664	else
3665	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3666
3667	/* else: handler catching all access, no pointer returned. */
3668	}
3669	else
3670	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3671
3672	pgmUnlock(pVM);
3673	return rc;
3674	}
3675

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source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 27588

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