PGMPhys.cpp@ 27590

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1	/* $Id: PGMPhys.cpp 27590 2010-03-22 13:52:58Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_PHYS
27	#include <VBox/pgm.h>
28	#include <VBox/iom.h>
29	#include <VBox/mm.h>
30	#include <VBox/stam.h>
31	#include <VBox/rem.h>
32	#include <VBox/pdmdev.h>
33	#include "PGMInternal.h"
34	#include <VBox/vm.h>
35	#include "PGMInline.h"
36	#include <VBox/sup.h>
37	#include <VBox/param.h>
38	#include <VBox/err.h>
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/alloc.h>
42	#include <iprt/asm.h>
43	#include <iprt/thread.h>
44	#include <iprt/string.h>
45
46
47	/*******************************************************************************
48	* Defined Constants And Macros *
49	*******************************************************************************/
50	/** The number of pages to free in one batch. */
51	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
52
53
54	/*******************************************************************************
55	* Internal Functions *
56	*******************************************************************************/
57	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
58	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
59
60
61	/*
62	* PGMR3PhysReadU8-64
63	* PGMR3PhysWriteU8-64
64	*/
65	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
66	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
67	#define PGMPHYS_DATASIZE 1
68	#define PGMPHYS_DATATYPE uint8_t
69	#include "PGMPhysRWTmpl.h"
70
71	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
72	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
73	#define PGMPHYS_DATASIZE 2
74	#define PGMPHYS_DATATYPE uint16_t
75	#include "PGMPhysRWTmpl.h"
76
77	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
78	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
79	#define PGMPHYS_DATASIZE 4
80	#define PGMPHYS_DATATYPE uint32_t
81	#include "PGMPhysRWTmpl.h"
82
83	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
84	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
85	#define PGMPHYS_DATASIZE 8
86	#define PGMPHYS_DATATYPE uint64_t
87	#include "PGMPhysRWTmpl.h"
88
89
90	/**
91	* EMT worker for PGMR3PhysReadExternal.
92	*/
93	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
94	{
95	PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
96	return VINF_SUCCESS;
97	}
98
99
100	/**
101	* Write to physical memory, external users.
102	*
103	* @returns VBox status code.
104	* @retval VINF_SUCCESS.
105	*
106	* @param pVM VM Handle.
107	* @param GCPhys Physical address to write to.
108	* @param pvBuf What to write.
109	* @param cbWrite How many bytes to write.
110	*
111	* @thread Any but EMTs.
112	*/
113	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
114	{
115	VM_ASSERT_OTHER_THREAD(pVM);
116
117	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
118	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
119
120	pgmLock(pVM);
121
122	/*
123	* Copy loop on ram ranges.
124	*/
125	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
126	for (;;)
127	{
128	/* Find range. */
129	while (pRam && GCPhys > pRam->GCPhysLast)
130	pRam = pRam->CTX_SUFF(pNext);
131	/* Inside range or not? */
132	if (pRam && GCPhys >= pRam->GCPhys)
133	{
134	/*
135	* Must work our way thru this page by page.
136	*/
137	RTGCPHYS off = GCPhys - pRam->GCPhys;
138	while (off < pRam->cb)
139	{
140	unsigned iPage = off >> PAGE_SHIFT;
141	PPGMPAGE pPage = &pRam->aPages[iPage];
142
143	/*
144	* If the page has an ALL access handler, we'll have to
145	* delegate the job to EMT.
146	*/
147	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
148	{
149	pgmUnlock(pVM);
150
151	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 4,
152	pVM, &GCPhys, pvBuf, cbRead);
153	}
154	Assert(!PGM_PAGE_IS_MMIO(pPage));
155
156	/*
157	* Simple stuff, go ahead.
158	*/
159	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
160	if (cb > cbRead)
161	cb = cbRead;
162	const void *pvSrc;
163	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
164	if (RT_SUCCESS(rc))
165	memcpy(pvBuf, pvSrc, cb);
166	else
167	{
168	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
169	pRam->GCPhys + off, pPage, rc));
170	memset(pvBuf, 0xff, cb);
171	}
172
173	/* next page */
174	if (cb >= cbRead)
175	{
176	pgmUnlock(pVM);
177	return VINF_SUCCESS;
178	}
179	cbRead -= cb;
180	off += cb;
181	GCPhys += cb;
182	pvBuf = (char *)pvBuf + cb;
183	} /* walk pages in ram range. */
184	}
185	else
186	{
187	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
188
189	/*
190	* Unassigned address space.
191	*/
192	if (!pRam)
193	break;
194	size_t cb = pRam->GCPhys - GCPhys;
195	if (cb >= cbRead)
196	{
197	memset(pvBuf, 0xff, cbRead);
198	break;
199	}
200	memset(pvBuf, 0xff, cb);
201
202	cbRead -= cb;
203	pvBuf = (char *)pvBuf + cb;
204	GCPhys += cb;
205	}
206	} /* Ram range walk */
207
208	pgmUnlock(pVM);
209
210	return VINF_SUCCESS;
211	}
212
213
214	/**
215	* EMT worker for PGMR3PhysWriteExternal.
216	*/
217	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
218	{
219	/** @todo VERR_EM_NO_MEMORY */
220	PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
221	return VINF_SUCCESS;
222	}
223
224
225	/**
226	* Write to physical memory, external users.
227	*
228	* @returns VBox status code.
229	* @retval VINF_SUCCESS.
230	* @retval VERR_EM_NO_MEMORY.
231	*
232	* @param pVM VM Handle.
233	* @param GCPhys Physical address to write to.
234	* @param pvBuf What to write.
235	* @param cbWrite How many bytes to write.
236	* @param pszWho Who is writing. For tracking down who is writing
237	* after we've saved the state.
238	*
239	* @thread Any but EMTs.
240	*/
241	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void pvBuf, size_t cbWrite, const char pszWho)
242	{
243	VM_ASSERT_OTHER_THREAD(pVM);
244
245	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
246	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x pszWho=%s\n",
247	GCPhys, cbWrite, pszWho));
248	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
249	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
250
251	pgmLock(pVM);
252
253	/*
254	* Copy loop on ram ranges, stop when we hit something difficult.
255	*/
256	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
257	for (;;)
258	{
259	/* Find range. */
260	while (pRam && GCPhys > pRam->GCPhysLast)
261	pRam = pRam->CTX_SUFF(pNext);
262	/* Inside range or not? */
263	if (pRam && GCPhys >= pRam->GCPhys)
264	{
265	/*
266	* Must work our way thru this page by page.
267	*/
268	RTGCPTR off = GCPhys - pRam->GCPhys;
269	while (off < pRam->cb)
270	{
271	RTGCPTR iPage = off >> PAGE_SHIFT;
272	PPGMPAGE pPage = &pRam->aPages[iPage];
273
274	/*
275	* Is the page problematic, we have to do the work on the EMT.
276	*
277	* Allocating writable pages and access handlers are
278	* problematic, write monitored pages are simple and can be
279	* dealth with here.
280	*/
281	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
282	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
283	{
284	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
285	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
286	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
287	else
288	{
289	pgmUnlock(pVM);
290
291	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 4,
292	pVM, &GCPhys, pvBuf, cbWrite);
293	}
294	}
295	Assert(!PGM_PAGE_IS_MMIO(pPage));
296
297	/*
298	* Simple stuff, go ahead.
299	*/
300	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
301	if (cb > cbWrite)
302	cb = cbWrite;
303	void *pvDst;
304	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
305	if (RT_SUCCESS(rc))
306	memcpy(pvDst, pvBuf, cb);
307	else
308	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
309	pRam->GCPhys + off, pPage, rc));
310
311	/* next page */
312	if (cb >= cbWrite)
313	{
314	pgmUnlock(pVM);
315	return VINF_SUCCESS;
316	}
317
318	cbWrite -= cb;
319	off += cb;
320	GCPhys += cb;
321	pvBuf = (const char *)pvBuf + cb;
322	} /* walk pages in ram range */
323	}
324	else
325	{
326	/*
327	* Unassigned address space, skip it.
328	*/
329	if (!pRam)
330	break;
331	size_t cb = pRam->GCPhys - GCPhys;
332	if (cb >= cbWrite)
333	break;
334	cbWrite -= cb;
335	pvBuf = (const char *)pvBuf + cb;
336	GCPhys += cb;
337	}
338	} /* Ram range walk */
339
340	pgmUnlock(pVM);
341	return VINF_SUCCESS;
342	}
343
344
345	/**
346	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
347	*
348	* @returns see PGMR3PhysGCPhys2CCPtrExternal
349	* @param pVM The VM handle.
350	* @param pGCPhys Pointer to the guest physical address.
351	* @param ppv Where to store the mapping address.
352	* @param pLock Where to store the lock.
353	*/
354	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
355	{
356	/*
357	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
358	* an access handler after it succeeds.
359	*/
360	int rc = pgmLock(pVM);
361	AssertRCReturn(rc, rc);
362
363	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
364	if (RT_SUCCESS(rc))
365	{
366	PPGMPAGEMAPTLBE pTlbe;
367	int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
368	AssertFatalRC(rc2);
369	PPGMPAGE pPage = pTlbe->pPage;
370	if (PGM_PAGE_IS_MMIO(pPage))
371	{
372	PGMPhysReleasePageMappingLock(pVM, pLock);
373	rc = VERR_PGM_PHYS_PAGE_RESERVED;
374	}
375	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
376	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
377	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
378	#endif
379	)
380	{
381	/* We must flush any corresponding pgm pool page here, otherwise we'll
382	* not be informed about writes and keep bogus gst->shw mappings around.
383	*/
384	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
385	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
386	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
387	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
388	}
389	}
390
391	pgmUnlock(pVM);
392	return rc;
393	}
394
395
396	/**
397	* Requests the mapping of a guest page into ring-3, external threads.
398	*
399	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
400	* release it.
401	*
402	* This API will assume your intention is to write to the page, and will
403	* therefore replace shared and zero pages. If you do not intend to modify the
404	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
405	*
406	* @returns VBox status code.
407	* @retval VINF_SUCCESS on success.
408	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
409	* backing or if the page has any active access handlers. The caller
410	* must fall back on using PGMR3PhysWriteExternal.
411	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
412	*
413	* @param pVM The VM handle.
414	* @param GCPhys The guest physical address of the page that should be mapped.
415	* @param ppv Where to store the address corresponding to GCPhys.
416	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
417	*
418	* @remark Avoid calling this API from within critical sections (other than the
419	* PGM one) because of the deadlock risk when we have to delegating the
420	* task to an EMT.
421	* @thread Any.
422	*/
423	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
424	{
425	AssertPtr(ppv);
426	AssertPtr(pLock);
427
428	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
429
430	int rc = pgmLock(pVM);
431	AssertRCReturn(rc, rc);
432
433	/*
434	* Query the Physical TLB entry for the page (may fail).
435	*/
436	PPGMPAGEMAPTLBE pTlbe;
437	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
438	if (RT_SUCCESS(rc))
439	{
440	PPGMPAGE pPage = pTlbe->pPage;
441	if (PGM_PAGE_IS_MMIO(pPage))
442	rc = VERR_PGM_PHYS_PAGE_RESERVED;
443	else
444	{
445	/*
446	* If the page is shared, the zero page, or being write monitored
447	* it must be converted to an page that's writable if possible.
448	* We can only deal with write monitored pages here, the rest have
449	* to be on an EMT.
450	*/
451	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
452	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
453	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
454	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
455	#endif
456	)
457	{
458	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
459	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
460	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
461	&& !pgmPoolIsDirtyPage(pVM, GCPhys)
462	#endif
463	)
464	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
465	else
466	{
467	pgmUnlock(pVM);
468
469	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
470	pVM, &GCPhys, ppv, pLock);
471	}
472	}
473
474	/*
475	* Now, just perform the locking and calculate the return address.
476	*/
477	PPGMPAGEMAP pMap = pTlbe->pMap;
478	if (pMap)
479	pMap->cRefs++;
480
481	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
482	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
483	{
484	if (cLocks == 0)
485	pVM->pgm.s.cWriteLockedPages++;
486	PGM_PAGE_INC_WRITE_LOCKS(pPage);
487	}
488	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
489	{
490	PGM_PAGE_INC_WRITE_LOCKS(pPage);
491	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
492	if (pMap)
493	pMap->cRefs++; /* Extra ref to prevent it from going away. */
494	}
495
496	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
497	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
498	pLock->pvMap = pMap;
499	}
500	}
501
502	pgmUnlock(pVM);
503	return rc;
504	}
505
506
507	/**
508	* Requests the mapping of a guest page into ring-3, external threads.
509	*
510	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
511	* release it.
512	*
513	* @returns VBox status code.
514	* @retval VINF_SUCCESS on success.
515	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
516	* backing or if the page as an active ALL access handler. The caller
517	* must fall back on using PGMPhysRead.
518	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
519	*
520	* @param pVM The VM handle.
521	* @param GCPhys The guest physical address of the page that should be mapped.
522	* @param ppv Where to store the address corresponding to GCPhys.
523	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
524	*
525	* @remark Avoid calling this API from within critical sections (other than
526	* the PGM one) because of the deadlock risk.
527	* @thread Any.
528	*/
529	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
530	{
531	int rc = pgmLock(pVM);
532	AssertRCReturn(rc, rc);
533
534	/*
535	* Query the Physical TLB entry for the page (may fail).
536	*/
537	PPGMPAGEMAPTLBE pTlbe;
538	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
539	if (RT_SUCCESS(rc))
540	{
541	PPGMPAGE pPage = pTlbe->pPage;
542	#if 1
543	/* MMIO pages doesn't have any readable backing. */
544	if (PGM_PAGE_IS_MMIO(pPage))
545	rc = VERR_PGM_PHYS_PAGE_RESERVED;
546	#else
547	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
548	rc = VERR_PGM_PHYS_PAGE_RESERVED;
549	#endif
550	else
551	{
552	/*
553	* Now, just perform the locking and calculate the return address.
554	*/
555	PPGMPAGEMAP pMap = pTlbe->pMap;
556	if (pMap)
557	pMap->cRefs++;
558
559	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
560	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
561	{
562	if (cLocks == 0)
563	pVM->pgm.s.cReadLockedPages++;
564	PGM_PAGE_INC_READ_LOCKS(pPage);
565	}
566	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
567	{
568	PGM_PAGE_INC_READ_LOCKS(pPage);
569	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
570	if (pMap)
571	pMap->cRefs++; /* Extra ref to prevent it from going away. */
572	}
573
574	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
575	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
576	pLock->pvMap = pMap;
577	}
578	}
579
580	pgmUnlock(pVM);
581	return rc;
582	}
583
584
585	/**
586	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
587	*
588	* Called when anything was relocated.
589	*
590	* @param pVM Pointer to the shared VM structure.
591	*/
592	void pgmR3PhysRelinkRamRanges(PVM pVM)
593	{
594	PPGMRAMRANGE pCur;
595
596	#ifdef VBOX_STRICT
597	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
598	{
599	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
600	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
601	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
602	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
603	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
604	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
605	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
606	Assert( pCur2 == pCur
607	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
608	}
609	#endif
610
611	pCur = pVM->pgm.s.pRamRangesR3;
612	if (pCur)
613	{
614	pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
615	pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
616
617	for (; pCur->pNextR3; pCur = pCur->pNextR3)
618	{
619	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
620	pCur->pNextRC = pCur->pNextR3->pSelfRC;
621	}
622
623	Assert(pCur->pNextR0 == NIL_RTR0PTR);
624	Assert(pCur->pNextRC == NIL_RTRCPTR);
625	}
626	else
627	{
628	Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
629	Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
630	}
631	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
632	}
633
634
635	/**
636	* Links a new RAM range into the list.
637	*
638	* @param pVM Pointer to the shared VM structure.
639	* @param pNew Pointer to the new list entry.
640	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
641	*/
642	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
643	{
644	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
645	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
646	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
647
648	pgmLock(pVM);
649
650	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
651	pNew->pNextR3 = pRam;
652	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
653	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
654
655	if (pPrev)
656	{
657	pPrev->pNextR3 = pNew;
658	pPrev->pNextR0 = pNew->pSelfR0;
659	pPrev->pNextRC = pNew->pSelfRC;
660	}
661	else
662	{
663	pVM->pgm.s.pRamRangesR3 = pNew;
664	pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
665	pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
666	}
667	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
668	pgmUnlock(pVM);
669	}
670
671
672	/**
673	* Unlink an existing RAM range from the list.
674	*
675	* @param pVM Pointer to the shared VM structure.
676	* @param pRam Pointer to the new list entry.
677	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
678	*/
679	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
680	{
681	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
682	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
683	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
684
685	pgmLock(pVM);
686
687	PPGMRAMRANGE pNext = pRam->pNextR3;
688	if (pPrev)
689	{
690	pPrev->pNextR3 = pNext;
691	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
692	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
693	}
694	else
695	{
696	Assert(pVM->pgm.s.pRamRangesR3 == pRam);
697	pVM->pgm.s.pRamRangesR3 = pNext;
698	pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
699	pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
700	}
701	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
702	pgmUnlock(pVM);
703	}
704
705
706	/**
707	* Unlink an existing RAM range from the list.
708	*
709	* @param pVM Pointer to the shared VM structure.
710	* @param pRam Pointer to the new list entry.
711	*/
712	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
713	{
714	pgmLock(pVM);
715
716	/* find prev. */
717	PPGMRAMRANGE pPrev = NULL;
718	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
719	while (pCur != pRam)
720	{
721	pPrev = pCur;
722	pCur = pCur->pNextR3;
723	}
724	AssertFatal(pCur);
725
726	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
727	pgmUnlock(pVM);
728	}
729
730
731	/**
732	* Frees a range of pages, replacing them with ZERO pages of the specified type.
733	*
734	* @returns VBox status code.
735	* @param pVM The VM handle.
736	* @param pRam The RAM range in which the pages resides.
737	* @param GCPhys The address of the first page.
738	* @param GCPhysLast The address of the last page.
739	* @param uType The page type to replace then with.
740	*/
741	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
742	{
743	Assert(PGMIsLockOwner(pVM));
744	uint32_t cPendingPages = 0;
745	PGMMFREEPAGESREQ pReq;
746	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
747	AssertLogRelRCReturn(rc, rc);
748
749	/* Iterate the pages. */
750	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
751	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
752	while (cPagesLeft-- > 0)
753	{
754	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
755	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
756
757	PGM_PAGE_SET_TYPE(pPageDst, uType);
758
759	GCPhys += PAGE_SIZE;
760	pPageDst++;
761	}
762
763	if (cPendingPages)
764	{
765	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
766	AssertLogRelRCReturn(rc, rc);
767	}
768	GMMR3FreePagesCleanup(pReq);
769
770	return rc;
771	}
772
773	/**
774	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
775	*
776	* This is only called on one of the EMTs while the other ones are waiting for
777	* it to complete this function.
778	*
779	* @returns VINF_SUCCESS (VBox strict status code).
780	* @param pVM The VM handle.
781	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
782	* @param pvUser User parameter
783	*/
784	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
785	{
786	uintptr_t paUser = (uintptr_t )pvUser;
787	bool fInflate = !!paUser[0];
788	unsigned cPages = paUser[1];
789	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
790	uint32_t cPendingPages = 0;
791	PGMMFREEPAGESREQ pReq;
792	int rc;
793
794	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
795	pgmLock(pVM);
796
797	if (fInflate)
798	{
799	/* Replace pages with ZERO pages. */
800	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
801	if (RT_FAILURE(rc))
802	{
803	pgmUnlock(pVM);
804	AssertLogRelRC(rc);
805	return rc;
806	}
807
808	/* Iterate the pages. */
809	for (unsigned i = 0; i < cPages; i++)
810	{
811	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
812	if ( pPage == NULL
813	\|\| pPage->uTypeY != PGMPAGETYPE_RAM)
814	{
815	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], (pPage) ? pPage->uTypeY : 0));
816	break;
817	}
818
819	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i]);
820	if (RT_FAILURE(rc))
821	{
822	pgmUnlock(pVM);
823	AssertLogRelRC(rc);
824	return rc;
825	}
826	Assert(PGM_PAGE_IS_ZERO(pPage));
827	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_BALLOONED);
828	}
829
830	if (cPendingPages)
831	{
832	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
833	if (RT_FAILURE(rc))
834	{
835	pgmUnlock(pVM);
836	AssertLogRelRC(rc);
837	return rc;
838	}
839	}
840	GMMR3FreePagesCleanup(pReq);
841
842	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
843	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
844	}
845
846	/* Notify GMM about the balloon change. */
847	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
848	if (RT_SUCCESS(rc))
849	{
850	if (!fInflate)
851	{
852	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
853	pVM->pgm.s.cBalloonedPages -= cPages;
854	}
855	else
856	pVM->pgm.s.cBalloonedPages += cPages;
857	}
858
859	pgmUnlock(pVM);
860
861	/* Flush the recompiler's TLB as well. */
862	for (unsigned i = 0; i < pVM->cCpus; i++)
863	CPUMSetChangedFlags(&pVM->aCpus[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
864
865	AssertLogRelRC(rc);
866	return rc;
867	}
868
869	/**
870	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
871	*
872	* @returns VBox status code.
873	* @param pVM The VM handle.
874	* @param fInflate Inflate or deflate memory balloon
875	* @param cPages Number of pages to free
876	* @param paPhysPage Array of guest physical addresses
877	*/
878	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
879	{
880	uintptr_t paUser[3];
881
882	paUser[0] = fInflate;
883	paUser[1] = cPages;
884	paUser[2] = (uintptr_t)paPhysPage;
885	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
886	AssertRC(rc);
887
888	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
889	RTMemFree(paPhysPage);
890	}
891
892	/**
893	* Inflate or deflate a memory balloon
894	*
895	* @returns VBox status code.
896	* @param pVM The VM handle.
897	* @param fInflate Inflate or deflate memory balloon
898	* @param cPages Number of pages to free
899	* @param paPhysPage Array of guest physical addresses
900	*/
901	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
902	{
903	int rc;
904
905	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
906	* In the SMP case we post a request packet to postpone the job.
907	*/
908	if (pVM->cCpus > 1)
909	{
910	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
911	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
912	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
913
914	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
915
916	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
917	AssertRC(rc);
918	}
919	else
920	{
921	uintptr_t paUser[3];
922
923	paUser[0] = fInflate;
924	paUser[1] = cPages;
925	paUser[2] = (uintptr_t)paPhysPage;
926	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
927	AssertRC(rc);
928	}
929	return rc;
930	}
931
932
933	/**
934	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
935	*
936	* @param pVM The VM handle.
937	* @param pNew The new RAM range.
938	* @param GCPhys The address of the RAM range.
939	* @param GCPhysLast The last address of the RAM range.
940	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
941	* if in HMA.
942	* @param R0PtrNew Ditto for R0.
943	* @param pszDesc The description.
944	* @param pPrev The previous RAM range (for linking).
945	*/
946	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
947	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
948	{
949	/*
950	* Initialize the range.
951	*/
952	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
953	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
954	pNew->GCPhys = GCPhys;
955	pNew->GCPhysLast = GCPhysLast;
956	pNew->cb = GCPhysLast - GCPhys + 1;
957	pNew->pszDesc = pszDesc;
958	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
959	pNew->pvR3 = NULL;
960	pNew->paLSPages = NULL;
961
962	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
963	RTGCPHYS iPage = cPages;
964	while (iPage-- > 0)
965	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
966
967	/* Update the page count stats. */
968	pVM->pgm.s.cZeroPages += cPages;
969	pVM->pgm.s.cAllPages += cPages;
970
971	/*
972	* Link it.
973	*/
974	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
975	}
976
977
978	/**
979	* Relocate a floating RAM range.
980	*
981	* @copydoc FNPGMRELOCATE.
982	*/
983	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
984	{
985	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
986	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
987	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
988
989	switch (enmMode)
990	{
991	case PGMRELOCATECALL_SUGGEST:
992	return true;
993	case PGMRELOCATECALL_RELOCATE:
994	{
995	/* Update myself and then relink all the ranges. */
996	pgmLock(pVM);
997	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
998	pgmR3PhysRelinkRamRanges(pVM);
999	pgmUnlock(pVM);
1000	return true;
1001	}
1002
1003	default:
1004	AssertFailedReturn(false);
1005	}
1006	}
1007
1008
1009	/**
1010	* PGMR3PhysRegisterRam worker that registers a high chunk.
1011	*
1012	* @returns VBox status code.
1013	* @param pVM The VM handle.
1014	* @param GCPhys The address of the RAM.
1015	* @param cRamPages The number of RAM pages to register.
1016	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1017	* @param iChunk The chunk number.
1018	* @param pszDesc The RAM range description.
1019	* @param ppPrev Previous RAM range pointer. In/Out.
1020	*/
1021	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1022	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1023	PPGMRAMRANGE *ppPrev)
1024	{
1025	const char *pszDescChunk = iChunk == 0
1026	? pszDesc
1027	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1028	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1029
1030	/*
1031	* Allocate memory for the new chunk.
1032	*/
1033	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1034	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1035	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1036	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1037	void *pvChunk = NULL;
1038	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
1039	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1040	VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
1041	#else
1042	NULL,
1043	#endif
1044	paChunkPages);
1045	if (RT_SUCCESS(rc))
1046	{
1047	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1048	if (!VMMIsHwVirtExtForced(pVM))
1049	R0PtrChunk = NIL_RTR0PTR;
1050	#else
1051	R0PtrChunk = (uintptr_t)pvChunk;
1052	#endif
1053	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1054
1055	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1056
1057	/*
1058	* Create a mapping and map the pages into it.
1059	* We push these in below the HMA.
1060	*/
1061	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1062	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1063	if (RT_SUCCESS(rc))
1064	{
1065	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1066
1067	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1068	RTGCPTR GCPtrPage = GCPtrChunk;
1069	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1070	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1071	if (RT_SUCCESS(rc))
1072	{
1073	/*
1074	* Ok, init and link the range.
1075	*/
1076	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1077	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1078	*ppPrev = pNew;
1079	}
1080	}
1081
1082	if (RT_FAILURE(rc))
1083	SUPR3PageFreeEx(pvChunk, cChunkPages);
1084	}
1085
1086	RTMemTmpFree(paChunkPages);
1087	return rc;
1088	}
1089
1090
1091	/**
1092	* Sets up a range RAM.
1093	*
1094	* This will check for conflicting registrations, make a resource
1095	* reservation for the memory (with GMM), and setup the per-page
1096	* tracking structures (PGMPAGE).
1097	*
1098	* @returns VBox stutus code.
1099	* @param pVM Pointer to the shared VM structure.
1100	* @param GCPhys The physical address of the RAM.
1101	* @param cb The size of the RAM.
1102	* @param pszDesc The description - not copied, so, don't free or change it.
1103	*/
1104	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1105	{
1106	/*
1107	* Validate input.
1108	*/
1109	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1110	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1111	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1112	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1113	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1114	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1115	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1116	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1117
1118	pgmLock(pVM);
1119
1120	/*
1121	* Find range location and check for conflicts.
1122	* (We don't lock here because the locking by EMT is only required on update.)
1123	*/
1124	PPGMRAMRANGE pPrev = NULL;
1125	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1126	while (pRam && GCPhysLast >= pRam->GCPhys)
1127	{
1128	if ( GCPhysLast >= pRam->GCPhys
1129	&& GCPhys <= pRam->GCPhysLast)
1130	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1131	GCPhys, GCPhysLast, pszDesc,
1132	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1133	VERR_PGM_RAM_CONFLICT);
1134
1135	/* next */
1136	pPrev = pRam;
1137	pRam = pRam->pNextR3;
1138	}
1139
1140	/*
1141	* Register it with GMM (the API bitches).
1142	*/
1143	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1144	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1145	if (RT_FAILURE(rc))
1146	{
1147	pgmUnlock(pVM);
1148	return rc;
1149	}
1150
1151	if ( GCPhys >= _4G
1152	&& cPages > 256)
1153	{
1154	/*
1155	* The PGMRAMRANGE structures for the high memory can get very big.
1156	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1157	* allocation size limit there and also to avoid being unable to find
1158	* guest mapping space for them, we split this memory up into 4MB in
1159	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1160	* mode.
1161	*
1162	* The first and last page of each mapping are guard pages and marked
1163	* not-present. So, we've got 4186112 and 16769024 bytes available for
1164	* the PGMRAMRANGE structure.
1165	*
1166	* Note! The sizes used here will influence the saved state.
1167	*/
1168	uint32_t cbChunk;
1169	uint32_t cPagesPerChunk;
1170	if (VMMIsHwVirtExtForced(pVM))
1171	{
1172	cbChunk = 16U*_1M;
1173	cPagesPerChunk = 1048048; /* max ~1048059 */
1174	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1175	}
1176	else
1177	{
1178	cbChunk = 4U*_1M;
1179	cPagesPerChunk = 261616; /* max ~261627 */
1180	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1181	}
1182	AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1183
1184	RTGCPHYS cPagesLeft = cPages;
1185	RTGCPHYS GCPhysChunk = GCPhys;
1186	uint32_t iChunk = 0;
1187	while (cPagesLeft > 0)
1188	{
1189	uint32_t cPagesInChunk = cPagesLeft;
1190	if (cPagesInChunk > cPagesPerChunk)
1191	cPagesInChunk = cPagesPerChunk;
1192
1193	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1194	AssertRCReturn(rc, rc);
1195
1196	/* advance */
1197	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1198	cPagesLeft -= cPagesInChunk;
1199	iChunk++;
1200	}
1201	}
1202	else
1203	{
1204	/*
1205	* Allocate, initialize and link the new RAM range.
1206	*/
1207	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1208	PPGMRAMRANGE pNew;
1209	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1210	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1211
1212	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1213	}
1214	PGMPhysInvalidatePageMapTLB(pVM);
1215	pgmUnlock(pVM);
1216
1217	/*
1218	* Notify REM.
1219	*/
1220	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1221
1222	return VINF_SUCCESS;
1223	}
1224
1225
1226	/**
1227	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1228	*
1229	* We do this late in the init process so that all the ROM and MMIO ranges have
1230	* been registered already and we don't go wasting memory on them.
1231	*
1232	* @returns VBox status code.
1233	*
1234	* @param pVM Pointer to the shared VM structure.
1235	*/
1236	int pgmR3PhysRamPreAllocate(PVM pVM)
1237	{
1238	Assert(pVM->pgm.s.fRamPreAlloc);
1239	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1240
1241	/*
1242	* Walk the RAM ranges and allocate all RAM pages, halt at
1243	* the first allocation error.
1244	*/
1245	uint64_t cPages = 0;
1246	uint64_t NanoTS = RTTimeNanoTS();
1247	pgmLock(pVM);
1248	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1249	{
1250	PPGMPAGE pPage = &pRam->aPages[0];
1251	RTGCPHYS GCPhys = pRam->GCPhys;
1252	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1253	while (cLeft-- > 0)
1254	{
1255	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1256	{
1257	switch (PGM_PAGE_GET_STATE(pPage))
1258	{
1259	case PGM_PAGE_STATE_ZERO:
1260	{
1261	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1262	if (RT_FAILURE(rc))
1263	{
1264	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1265	pgmUnlock(pVM);
1266	return rc;
1267	}
1268	cPages++;
1269	break;
1270	}
1271
1272	case PGM_PAGE_STATE_BALLOONED:
1273	case PGM_PAGE_STATE_ALLOCATED:
1274	case PGM_PAGE_STATE_WRITE_MONITORED:
1275	case PGM_PAGE_STATE_SHARED:
1276	/* nothing to do here. */
1277	break;
1278	}
1279	}
1280
1281	/* next */
1282	pPage++;
1283	GCPhys += PAGE_SIZE;
1284	}
1285	}
1286	pgmUnlock(pVM);
1287	NanoTS = RTTimeNanoTS() - NanoTS;
1288
1289	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1290	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1291	return VINF_SUCCESS;
1292	}
1293
1294
1295	/**
1296	* Resets (zeros) the RAM.
1297	*
1298	* ASSUMES that the caller owns the PGM lock.
1299	*
1300	* @returns VBox status code.
1301	* @param pVM Pointer to the shared VM structure.
1302	*/
1303	int pgmR3PhysRamReset(PVM pVM)
1304	{
1305	Assert(PGMIsLockOwner(pVM));
1306
1307	/* Reset the memory balloon. */
1308	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1309	AssertRC(rc);
1310
1311	/*
1312	* We batch up pages that should be freed instead of calling GMM for
1313	* each and every one of them.
1314	*/
1315	uint32_t cPendingPages = 0;
1316	PGMMFREEPAGESREQ pReq;
1317	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1318	AssertLogRelRCReturn(rc, rc);
1319
1320	/*
1321	* Walk the ram ranges.
1322	*/
1323	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1324	{
1325	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1326	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1327
1328	if (!pVM->pgm.s.fRamPreAlloc)
1329	{
1330	/* Replace all RAM pages by ZERO pages. */
1331	while (iPage-- > 0)
1332	{
1333	PPGMPAGE pPage = &pRam->aPages[iPage];
1334	switch (PGM_PAGE_GET_TYPE(pPage))
1335	{
1336	case PGMPAGETYPE_RAM:
1337	/* Do not replace pages part of a 2 MB continuous range with zero pages, but zero them instead. */
1338	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
1339	{
1340	void *pvPage;
1341	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1342	AssertLogRelRCReturn(rc, rc);
1343	ASMMemZeroPage(pvPage);
1344	}
1345	else
1346	if ( !PGM_PAGE_IS_ZERO(pPage)
1347	&& !PGM_PAGE_IS_BALLOONED(pPage))
1348	{
1349	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1350	AssertLogRelRCReturn(rc, rc);
1351	}
1352	break;
1353
1354	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1355	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1356	break;
1357
1358	case PGMPAGETYPE_MMIO2:
1359	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1360	case PGMPAGETYPE_ROM:
1361	case PGMPAGETYPE_MMIO:
1362	break;
1363	default:
1364	AssertFailed();
1365	}
1366	} /* for each page */
1367	}
1368	else
1369	{
1370	/* Zero the memory. */
1371	while (iPage-- > 0)
1372	{
1373	PPGMPAGE pPage = &pRam->aPages[iPage];
1374	switch (PGM_PAGE_GET_TYPE(pPage))
1375	{
1376	case PGMPAGETYPE_RAM:
1377	switch (PGM_PAGE_GET_STATE(pPage))
1378	{
1379	case PGM_PAGE_STATE_ZERO:
1380	break;
1381
1382	case PGM_PAGE_STATE_BALLOONED:
1383	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1384	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
1385	break;
1386
1387	case PGM_PAGE_STATE_SHARED:
1388	case PGM_PAGE_STATE_WRITE_MONITORED:
1389	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1390	AssertLogRelRCReturn(rc, rc);
1391	/* no break */
1392
1393	case PGM_PAGE_STATE_ALLOCATED:
1394	{
1395	void *pvPage;
1396	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1397	AssertLogRelRCReturn(rc, rc);
1398	ASMMemZeroPage(pvPage);
1399	break;
1400	}
1401	}
1402	break;
1403
1404	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1405	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1406	break;
1407
1408	case PGMPAGETYPE_MMIO2:
1409	case PGMPAGETYPE_ROM_SHADOW:
1410	case PGMPAGETYPE_ROM:
1411	case PGMPAGETYPE_MMIO:
1412	break;
1413	default:
1414	AssertFailed();
1415
1416	}
1417	} /* for each page */
1418	}
1419
1420	}
1421
1422	/*
1423	* Finish off any pages pending freeing.
1424	*/
1425	if (cPendingPages)
1426	{
1427	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1428	AssertLogRelRCReturn(rc, rc);
1429	}
1430	GMMR3FreePagesCleanup(pReq);
1431
1432	return VINF_SUCCESS;
1433	}
1434
1435
1436	/**
1437	* This is the interface IOM is using to register an MMIO region.
1438	*
1439	* It will check for conflicts and ensure that a RAM range structure
1440	* is present before calling the PGMR3HandlerPhysicalRegister API to
1441	* register the callbacks.
1442	*
1443	* @returns VBox status code.
1444	*
1445	* @param pVM Pointer to the shared VM structure.
1446	* @param GCPhys The start of the MMIO region.
1447	* @param cb The size of the MMIO region.
1448	* @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1449	* @param pvUserR3 The user argument for R3.
1450	* @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1451	* @param pvUserR0 The user argument for R0.
1452	* @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1453	* @param pvUserRC The user argument for RC.
1454	* @param pszDesc The description of the MMIO region.
1455	*/
1456	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1457	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1458	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1459	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1460	R3PTRTYPE(const char *) pszDesc)
1461	{
1462	/*
1463	* Assert on some assumption.
1464	*/
1465	VM_ASSERT_EMT(pVM);
1466	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1467	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1468	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1469	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1470
1471	/*
1472	* Make sure there's a RAM range structure for the region.
1473	*/
1474	int rc;
1475	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1476	bool fRamExists = false;
1477	PPGMRAMRANGE pRamPrev = NULL;
1478	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1479	while (pRam && GCPhysLast >= pRam->GCPhys)
1480	{
1481	if ( GCPhysLast >= pRam->GCPhys
1482	&& GCPhys <= pRam->GCPhysLast)
1483	{
1484	/* Simplification: all within the same range. */
1485	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1486	&& GCPhysLast <= pRam->GCPhysLast,
1487	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1488	GCPhys, GCPhysLast, pszDesc,
1489	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1490	VERR_PGM_RAM_CONFLICT);
1491
1492	/* Check that it's all RAM or MMIO pages. */
1493	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1494	uint32_t cLeft = cb >> PAGE_SHIFT;
1495	while (cLeft-- > 0)
1496	{
1497	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1498	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1499	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1500	GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1501	VERR_PGM_RAM_CONFLICT);
1502	pPage++;
1503	}
1504
1505	/* Looks good. */
1506	fRamExists = true;
1507	break;
1508	}
1509
1510	/* next */
1511	pRamPrev = pRam;
1512	pRam = pRam->pNextR3;
1513	}
1514	PPGMRAMRANGE pNew;
1515	if (fRamExists)
1516	{
1517	pNew = NULL;
1518
1519	/*
1520	* Make all the pages in the range MMIO/ZERO pages, freeing any
1521	* RAM pages currently mapped here. This might not be 100% correct
1522	* for PCI memory, but we're doing the same thing for MMIO2 pages.
1523	*/
1524	rc = pgmLock(pVM);
1525	if (RT_SUCCESS(rc))
1526	{
1527	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1528	pgmUnlock(pVM);
1529	}
1530	AssertRCReturn(rc, rc);
1531	}
1532	else
1533	{
1534	pgmLock(pVM);
1535
1536	/*
1537	* No RAM range, insert an ad hoc one.
1538	*
1539	* Note that we don't have to tell REM about this range because
1540	* PGMHandlerPhysicalRegisterEx will do that for us.
1541	*/
1542	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1543
1544	const uint32_t cPages = cb >> PAGE_SHIFT;
1545	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1546	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1547	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1548
1549	/* Initialize the range. */
1550	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1551	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1552	pNew->GCPhys = GCPhys;
1553	pNew->GCPhysLast = GCPhysLast;
1554	pNew->cb = cb;
1555	pNew->pszDesc = pszDesc;
1556	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
1557	pNew->pvR3 = NULL;
1558	pNew->paLSPages = NULL;
1559
1560	uint32_t iPage = cPages;
1561	while (iPage-- > 0)
1562	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1563	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1564
1565	/* update the page count stats. */
1566	pVM->pgm.s.cPureMmioPages += cPages;
1567	pVM->pgm.s.cAllPages += cPages;
1568
1569	/* link it */
1570	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1571
1572	pgmUnlock(pVM);
1573	}
1574
1575	/*
1576	* Register the access handler.
1577	*/
1578	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1579	pfnHandlerR3, pvUserR3,
1580	pfnHandlerR0, pvUserR0,
1581	pfnHandlerRC, pvUserRC, pszDesc);
1582	if ( RT_FAILURE(rc)
1583	&& !fRamExists)
1584	{
1585	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
1586	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1587
1588	/* remove the ad hoc range. */
1589	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1590	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1591	MMHyperFree(pVM, pRam);
1592	}
1593	PGMPhysInvalidatePageMapTLB(pVM);
1594
1595	return rc;
1596	}
1597
1598
1599	/**
1600	* This is the interface IOM is using to register an MMIO region.
1601	*
1602	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
1603	* any ad hoc PGMRAMRANGE left behind.
1604	*
1605	* @returns VBox status code.
1606	* @param pVM Pointer to the shared VM structure.
1607	* @param GCPhys The start of the MMIO region.
1608	* @param cb The size of the MMIO region.
1609	*/
1610	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1611	{
1612	VM_ASSERT_EMT(pVM);
1613
1614	/*
1615	* First deregister the handler, then check if we should remove the ram range.
1616	*/
1617	int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1618	if (RT_SUCCESS(rc))
1619	{
1620	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1621	PPGMRAMRANGE pRamPrev = NULL;
1622	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1623	while (pRam && GCPhysLast >= pRam->GCPhys)
1624	{
1625	/** @todo We're being a bit too careful here. rewrite. */
1626	if ( GCPhysLast == pRam->GCPhysLast
1627	&& GCPhys == pRam->GCPhys)
1628	{
1629	Assert(pRam->cb == cb);
1630
1631	/*
1632	* See if all the pages are dead MMIO pages.
1633	*/
1634	uint32_t const cPages = cb >> PAGE_SHIFT;
1635	bool fAllMMIO = true;
1636	uint32_t iPage = 0;
1637	uint32_t cLeft = cPages;
1638	while (cLeft-- > 0)
1639	{
1640	PPGMPAGE pPage = &pRam->aPages[iPage];
1641	if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1642	/\|\| not-out-of-action later /)
1643	{
1644	fAllMMIO = false;
1645	Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1646	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1647	break;
1648	}
1649	Assert(PGM_PAGE_IS_ZERO(pPage));
1650	pPage++;
1651	}
1652	if (fAllMMIO)
1653	{
1654	/*
1655	* Ad-hoc range, unlink and free it.
1656	*/
1657	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
1658	GCPhys, GCPhysLast, pRam->pszDesc));
1659
1660	pVM->pgm.s.cAllPages -= cPages;
1661	pVM->pgm.s.cPureMmioPages -= cPages;
1662
1663	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1664	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1665	MMHyperFree(pVM, pRam);
1666	break;
1667	}
1668	}
1669
1670	/*
1671	* Range match? It will all be within one range (see PGMAllHandler.cpp).
1672	*/
1673	if ( GCPhysLast >= pRam->GCPhys
1674	&& GCPhys <= pRam->GCPhysLast)
1675	{
1676	Assert(GCPhys >= pRam->GCPhys);
1677	Assert(GCPhysLast <= pRam->GCPhysLast);
1678
1679	/*
1680	* Turn the pages back into RAM pages.
1681	*/
1682	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1683	uint32_t cLeft = cb >> PAGE_SHIFT;
1684	while (cLeft--)
1685	{
1686	PPGMPAGE pPage = &pRam->aPages[iPage];
1687	AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1688	AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1689	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1690	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1691	}
1692	break;
1693	}
1694
1695	/* next */
1696	pRamPrev = pRam;
1697	pRam = pRam->pNextR3;
1698	}
1699	}
1700
1701	PGMPhysInvalidatePageMapTLB(pVM);
1702	return rc;
1703	}
1704
1705
1706	/**
1707	* Locate a MMIO2 range.
1708	*
1709	* @returns Pointer to the MMIO2 range.
1710	* @param pVM Pointer to the shared VM structure.
1711	* @param pDevIns The device instance owning the region.
1712	* @param iRegion The region.
1713	*/
1714	DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1715	{
1716	/*
1717	* Search the list.
1718	*/
1719	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1720	if ( pCur->pDevInsR3 == pDevIns
1721	&& pCur->iRegion == iRegion)
1722	return pCur;
1723	return NULL;
1724	}
1725
1726
1727	/**
1728	* Allocate and register an MMIO2 region.
1729	*
1730	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1731	* RAM associated with a device. It is also non-shared memory with a
1732	* permanent ring-3 mapping and page backing (presently).
1733	*
1734	* A MMIO2 range may overlap with base memory if a lot of RAM
1735	* is configured for the VM, in which case we'll drop the base
1736	* memory pages. Presently we will make no attempt to preserve
1737	* anything that happens to be present in the base memory that
1738	* is replaced, this is of course incorrectly but it's too much
1739	* effort.
1740	*
1741	* @returns VBox status code.
1742	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1743	* @retval VERR_ALREADY_EXISTS if the region already exists.
1744	*
1745	* @param pVM Pointer to the shared VM structure.
1746	* @param pDevIns The device instance owning the region.
1747	* @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1748	* this number has to be the number of that region. Otherwise
1749	* it can be any number safe UINT8_MAX.
1750	* @param cb The size of the region. Must be page aligned.
1751	* @param fFlags Reserved for future use, must be zero.
1752	* @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1753	* @param pszDesc The description.
1754	*/
1755	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc)
1756	{
1757	/*
1758	* Validate input.
1759	*/
1760	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1761	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1762	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1763	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1764	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1765	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1766	AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1767	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1768	AssertReturn(cb, VERR_INVALID_PARAMETER);
1769	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1770
1771	const uint32_t cPages = cb >> PAGE_SHIFT;
1772	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1773	AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1774
1775	/*
1776	* For the 2nd+ instance, mangle the description string so it's unique.
1777	*/
1778	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
1779	{
1780	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1781	if (!pszDesc)
1782	return VERR_NO_MEMORY;
1783	}
1784
1785	/*
1786	* Try reserve and allocate the backing memory first as this is what is
1787	* most likely to fail.
1788	*/
1789	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1790	if (RT_SUCCESS(rc))
1791	{
1792	void *pvPages;
1793	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1794	if (RT_SUCCESS(rc))
1795	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
1796	if (RT_SUCCESS(rc))
1797	{
1798	memset(pvPages, 0, cPages * PAGE_SIZE);
1799
1800	/*
1801	* Create the MMIO2 range record for it.
1802	*/
1803	const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1804	PPGMMMIO2RANGE pNew;
1805	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1806	AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1807	if (RT_SUCCESS(rc))
1808	{
1809	pNew->pDevInsR3 = pDevIns;
1810	pNew->pvR3 = pvPages;
1811	//pNew->pNext = NULL;
1812	//pNew->fMapped = false;
1813	//pNew->fOverlapping = false;
1814	pNew->iRegion = iRegion;
1815	pNew->idSavedState = UINT8_MAX;
1816	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1817	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1818	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1819	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1820	pNew->RamRange.pszDesc = pszDesc;
1821	pNew->RamRange.cb = cb;
1822	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
1823	pNew->RamRange.pvR3 = pvPages;
1824	//pNew->RamRange.paLSPages = NULL;
1825
1826	uint32_t iPage = cPages;
1827	while (iPage-- > 0)
1828	{
1829	PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1830	paPages[iPage].Phys, NIL_GMM_PAGEID,
1831	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1832	}
1833
1834	/* update page count stats */
1835	pVM->pgm.s.cAllPages += cPages;
1836	pVM->pgm.s.cPrivatePages += cPages;
1837
1838	/*
1839	* Link it into the list.
1840	* Since there is no particular order, just push it.
1841	*/
1842	pgmLock(pVM);
1843	pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1844	pVM->pgm.s.pMmio2RangesR3 = pNew;
1845	pgmUnlock(pVM);
1846
1847	*ppv = pvPages;
1848	RTMemTmpFree(paPages);
1849	PGMPhysInvalidatePageMapTLB(pVM);
1850	return VINF_SUCCESS;
1851	}
1852
1853	SUPR3PageFreeEx(pvPages, cPages);
1854	}
1855	RTMemTmpFree(paPages);
1856	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1857	}
1858	if (pDevIns->iInstance > 0)
1859	MMR3HeapFree((void *)pszDesc);
1860	return rc;
1861	}
1862
1863
1864	/**
1865	* Deregisters and frees an MMIO2 region.
1866	*
1867	* Any physical (and virtual) access handlers registered for the region must
1868	* be deregistered before calling this function.
1869	*
1870	* @returns VBox status code.
1871	* @param pVM Pointer to the shared VM structure.
1872	* @param pDevIns The device instance owning the region.
1873	* @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1874	*/
1875	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1876	{
1877	/*
1878	* Validate input.
1879	*/
1880	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1881	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1882	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1883
1884	pgmLock(pVM);
1885	int rc = VINF_SUCCESS;
1886	unsigned cFound = 0;
1887	PPGMMMIO2RANGE pPrev = NULL;
1888	PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1889	while (pCur)
1890	{
1891	if ( pCur->pDevInsR3 == pDevIns
1892	&& ( iRegion == UINT32_MAX
1893	\|\| pCur->iRegion == iRegion))
1894	{
1895	cFound++;
1896
1897	/*
1898	* Unmap it if it's mapped.
1899	*/
1900	if (pCur->fMapped)
1901	{
1902	int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1903	AssertRC(rc2);
1904	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1905	rc = rc2;
1906	}
1907
1908	/*
1909	* Unlink it
1910	*/
1911	PPGMMMIO2RANGE pNext = pCur->pNextR3;
1912	if (pPrev)
1913	pPrev->pNextR3 = pNext;
1914	else
1915	pVM->pgm.s.pMmio2RangesR3 = pNext;
1916	pCur->pNextR3 = NULL;
1917
1918	/*
1919	* Free the memory.
1920	*/
1921	int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1922	AssertRC(rc2);
1923	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1924	rc = rc2;
1925
1926	uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1927	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1928	AssertRC(rc2);
1929	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1930	rc = rc2;
1931
1932	/* we're leaking hyper memory here if done at runtime. */
1933	#ifdef VBOX_STRICT
1934	VMSTATE const enmState = VMR3GetState(pVM);
1935	AssertMsg( enmState == VMSTATE_POWERING_OFF
1936	\|\| enmState == VMSTATE_POWERING_OFF_LS
1937	\|\| enmState == VMSTATE_OFF
1938	\|\| enmState == VMSTATE_OFF_LS
1939	\|\| enmState == VMSTATE_DESTROYING
1940	\|\| enmState == VMSTATE_TERMINATED
1941	\|\| enmState == VMSTATE_CREATING
1942	, ("%s\n", VMR3GetStateName(enmState)));
1943	#endif
1944	/*rc = MMHyperFree(pVM, pCur);
1945	AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1946
1947
1948	/* update page count stats */
1949	pVM->pgm.s.cAllPages -= cPages;
1950	pVM->pgm.s.cPrivatePages -= cPages;
1951
1952	/* next */
1953	pCur = pNext;
1954	}
1955	else
1956	{
1957	pPrev = pCur;
1958	pCur = pCur->pNextR3;
1959	}
1960	}
1961	PGMPhysInvalidatePageMapTLB(pVM);
1962	pgmUnlock(pVM);
1963	return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1964	}
1965
1966
1967	/**
1968	* Maps a MMIO2 region.
1969	*
1970	* This is done when a guest / the bios / state loading changes the
1971	* PCI config. The replacing of base memory has the same restrictions
1972	* as during registration, of course.
1973	*
1974	* @returns VBox status code.
1975	*
1976	* @param pVM Pointer to the shared VM structure.
1977	* @param pDevIns The
1978	*/
1979	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1980	{
1981	/*
1982	* Validate input
1983	*/
1984	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1985	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1986	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1987	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1988	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1989	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1990
1991	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1992	AssertReturn(pCur, VERR_NOT_FOUND);
1993	AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
1994	Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
1995	Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
1996
1997	const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
1998	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1999
2000	/*
2001	* Find our location in the ram range list, checking for
2002	* restriction we don't bother implementing yet (partially overlapping).
2003	*/
2004	bool fRamExists = false;
2005	PPGMRAMRANGE pRamPrev = NULL;
2006	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2007	while (pRam && GCPhysLast >= pRam->GCPhys)
2008	{
2009	if ( GCPhys <= pRam->GCPhysLast
2010	&& GCPhysLast >= pRam->GCPhys)
2011	{
2012	/* completely within? */
2013	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2014	&& GCPhysLast <= pRam->GCPhysLast,
2015	("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
2016	GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
2017	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2018	VERR_PGM_RAM_CONFLICT);
2019	fRamExists = true;
2020	break;
2021	}
2022
2023	/* next */
2024	pRamPrev = pRam;
2025	pRam = pRam->pNextR3;
2026	}
2027	if (fRamExists)
2028	{
2029	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2030	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2031	while (cPagesLeft-- > 0)
2032	{
2033	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2034	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
2035	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
2036	VERR_PGM_RAM_CONFLICT);
2037	pPage++;
2038	}
2039	}
2040	Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
2041	GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
2042
2043	/*
2044	* Make the changes.
2045	*/
2046	pgmLock(pVM);
2047
2048	pCur->RamRange.GCPhys = GCPhys;
2049	pCur->RamRange.GCPhysLast = GCPhysLast;
2050	pCur->fMapped = true;
2051	pCur->fOverlapping = fRamExists;
2052
2053	if (fRamExists)
2054	{
2055	/** @todo use pgmR3PhysFreePageRange here. */
2056	uint32_t cPendingPages = 0;
2057	PGMMFREEPAGESREQ pReq;
2058	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2059	AssertLogRelRCReturn(rc, rc);
2060
2061	/* replace the pages, freeing all present RAM pages. */
2062	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2063	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2064	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2065	while (cPagesLeft-- > 0)
2066	{
2067	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
2068	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
2069
2070	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
2071	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
2072	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
2073	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
2074
2075	pVM->pgm.s.cZeroPages--;
2076	GCPhys += PAGE_SIZE;
2077	pPageSrc++;
2078	pPageDst++;
2079	}
2080
2081	/* Flush physical page map TLB. */
2082	PGMPhysInvalidatePageMapTLB(pVM);
2083
2084	if (cPendingPages)
2085	{
2086	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2087	AssertLogRelRCReturn(rc, rc);
2088	}
2089	GMMR3FreePagesCleanup(pReq);
2090	pgmUnlock(pVM);
2091	}
2092	else
2093	{
2094	RTGCPHYS cb = pCur->RamRange.cb;
2095
2096	/* link in the ram range */
2097	pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
2098	pgmUnlock(pVM);
2099
2100	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
2101	}
2102
2103	PGMPhysInvalidatePageMapTLB(pVM);
2104	return VINF_SUCCESS;
2105	}
2106
2107
2108	/**
2109	* Unmaps a MMIO2 region.
2110	*
2111	* This is done when a guest / the bios / state loading changes the
2112	* PCI config. The replacing of base memory has the same restrictions
2113	* as during registration, of course.
2114	*/
2115	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2116	{
2117	/*
2118	* Validate input
2119	*/
2120	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2121	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2122	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2123	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2124	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2125	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2126
2127	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2128	AssertReturn(pCur, VERR_NOT_FOUND);
2129	AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
2130	AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
2131	Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
2132
2133	Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
2134	pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
2135
2136	/*
2137	* Unmap it.
2138	*/
2139	pgmLock(pVM);
2140
2141	RTGCPHYS GCPhysRangeREM;
2142	RTGCPHYS cbRangeREM;
2143	bool fInformREM;
2144	if (pCur->fOverlapping)
2145	{
2146	/* Restore the RAM pages we've replaced. */
2147	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2148	while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
2149	pRam = pRam->pNextR3;
2150
2151	RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
2152	Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
2153	PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2154	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2155	while (cPagesLeft-- > 0)
2156	{
2157	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
2158	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
2159	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
2160	PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
2161	PGM_PAGE_SET_PDE_TYPE(pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
2162
2163	pVM->pgm.s.cZeroPages++;
2164	pPageDst++;
2165	}
2166
2167	/* Flush physical page map TLB. */
2168	PGMPhysInvalidatePageMapTLB(pVM);
2169
2170	GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
2171	cbRangeREM = RTGCPHYS_MAX; /* ditto */
2172	fInformREM = false;
2173	}
2174	else
2175	{
2176	GCPhysRangeREM = pCur->RamRange.GCPhys;
2177	cbRangeREM = pCur->RamRange.cb;
2178	fInformREM = true;
2179
2180	pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
2181	}
2182
2183	pCur->RamRange.GCPhys = NIL_RTGCPHYS;
2184	pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
2185	pCur->fOverlapping = false;
2186	pCur->fMapped = false;
2187
2188	PGMPhysInvalidatePageMapTLB(pVM);
2189	pgmUnlock(pVM);
2190
2191	if (fInformREM)
2192	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2193
2194	return VINF_SUCCESS;
2195	}
2196
2197
2198	/**
2199	* Checks if the given address is an MMIO2 base address or not.
2200	*
2201	* @returns true/false accordingly.
2202	* @param pVM Pointer to the shared VM structure.
2203	* @param pDevIns The owner of the memory, optional.
2204	* @param GCPhys The address to check.
2205	*/
2206	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2207	{
2208	/*
2209	* Validate input
2210	*/
2211	VM_ASSERT_EMT_RETURN(pVM, false);
2212	AssertPtrReturn(pDevIns, false);
2213	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
2214	AssertReturn(GCPhys != 0, false);
2215	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
2216
2217	/*
2218	* Search the list.
2219	*/
2220	pgmLock(pVM);
2221	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2222	if (pCur->RamRange.GCPhys == GCPhys)
2223	{
2224	Assert(pCur->fMapped);
2225	pgmUnlock(pVM);
2226	return true;
2227	}
2228	pgmUnlock(pVM);
2229	return false;
2230	}
2231
2232
2233	/**
2234	* Gets the HC physical address of a page in the MMIO2 region.
2235	*
2236	* This is API is intended for MMHyper and shouldn't be called
2237	* by anyone else...
2238	*
2239	* @returns VBox status code.
2240	* @param pVM Pointer to the shared VM structure.
2241	* @param pDevIns The owner of the memory, optional.
2242	* @param iRegion The region.
2243	* @param off The page expressed an offset into the MMIO2 region.
2244	* @param pHCPhys Where to store the result.
2245	*/
2246	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2247	{
2248	/*
2249	* Validate input
2250	*/
2251	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2252	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2253	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2254
2255	pgmLock(pVM);
2256	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2257	AssertReturn(pCur, VERR_NOT_FOUND);
2258	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2259
2260	PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2261	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2262	pgmUnlock(pVM);
2263	return VINF_SUCCESS;
2264	}
2265
2266
2267	/**
2268	* Maps a portion of an MMIO2 region into kernel space (host).
2269	*
2270	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
2271	* or the VM is terminated.
2272	*
2273	* @return VBox status code.
2274	*
2275	* @param pVM Pointer to the shared VM structure.
2276	* @param pDevIns The device owning the MMIO2 memory.
2277	* @param iRegion The region.
2278	* @param off The offset into the region. Must be page aligned.
2279	* @param cb The number of bytes to map. Must be page aligned.
2280	* @param pszDesc Mapping description.
2281	* @param pR0Ptr Where to store the R0 address.
2282	*/
2283	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2284	const char *pszDesc, PRTR0PTR pR0Ptr)
2285	{
2286	/*
2287	* Validate input.
2288	*/
2289	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2290	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2291	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2292
2293	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2294	AssertReturn(pCur, VERR_NOT_FOUND);
2295	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2296	AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2297	AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2298
2299	/*
2300	* Pass the request on to the support library/driver.
2301	*/
2302	int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2303
2304	return rc;
2305	}
2306
2307
2308	/**
2309	* Registers a ROM image.
2310	*
2311	* Shadowed ROM images requires double the amount of backing memory, so,
2312	* don't use that unless you have to. Shadowing of ROM images is process
2313	* where we can select where the reads go and where the writes go. On real
2314	* hardware the chipset provides means to configure this. We provide
2315	* PGMR3PhysProtectROM() for this purpose.
2316	*
2317	* A read-only copy of the ROM image will always be kept around while we
2318	* will allocate RAM pages for the changes on demand (unless all memory
2319	* is configured to be preallocated).
2320	*
2321	* @returns VBox status.
2322	* @param pVM VM Handle.
2323	* @param pDevIns The device instance owning the ROM.
2324	* @param GCPhys First physical address in the range.
2325	* Must be page aligned!
2326	* @param cbRange The size of the range (in bytes).
2327	* Must be page aligned!
2328	* @param pvBinary Pointer to the binary data backing the ROM image.
2329	* This must be exactly \a cbRange in size.
2330	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2331	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2332	* @param pszDesc Pointer to description string. This must not be freed.
2333	*
2334	* @remark There is no way to remove the rom, automatically on device cleanup or
2335	* manually from the device yet. This isn't difficult in any way, it's
2336	* just not something we expect to be necessary for a while.
2337	*/
2338	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2339	const void pvBinary, uint32_t fFlags, const char pszDesc)
2340	{
2341	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2342	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2343
2344	/*
2345	* Validate input.
2346	*/
2347	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2348	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2349	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2350	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2351	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2352	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2353	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2354	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2355	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2356
2357	const uint32_t cPages = cb >> PAGE_SHIFT;
2358
2359	/*
2360	* Find the ROM location in the ROM list first.
2361	*/
2362	PPGMROMRANGE pRomPrev = NULL;
2363	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2364	while (pRom && GCPhysLast >= pRom->GCPhys)
2365	{
2366	if ( GCPhys <= pRom->GCPhysLast
2367	&& GCPhysLast >= pRom->GCPhys)
2368	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2369	GCPhys, GCPhysLast, pszDesc,
2370	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2371	VERR_PGM_RAM_CONFLICT);
2372	/* next */
2373	pRomPrev = pRom;
2374	pRom = pRom->pNextR3;
2375	}
2376
2377	/*
2378	* Find the RAM location and check for conflicts.
2379	*
2380	* Conflict detection is a bit different than for RAM
2381	* registration since a ROM can be located within a RAM
2382	* range. So, what we have to check for is other memory
2383	* types (other than RAM that is) and that we don't span
2384	* more than one RAM range (layz).
2385	*/
2386	bool fRamExists = false;
2387	PPGMRAMRANGE pRamPrev = NULL;
2388	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2389	while (pRam && GCPhysLast >= pRam->GCPhys)
2390	{
2391	if ( GCPhys <= pRam->GCPhysLast
2392	&& GCPhysLast >= pRam->GCPhys)
2393	{
2394	/* completely within? */
2395	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2396	&& GCPhysLast <= pRam->GCPhysLast,
2397	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2398	GCPhys, GCPhysLast, pszDesc,
2399	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2400	VERR_PGM_RAM_CONFLICT);
2401	fRamExists = true;
2402	break;
2403	}
2404
2405	/* next */
2406	pRamPrev = pRam;
2407	pRam = pRam->pNextR3;
2408	}
2409	if (fRamExists)
2410	{
2411	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2412	uint32_t cPagesLeft = cPages;
2413	while (cPagesLeft-- > 0)
2414	{
2415	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2416	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2417	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2418	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2419	Assert(PGM_PAGE_IS_ZERO(pPage));
2420	pPage++;
2421	}
2422	}
2423
2424	/*
2425	* Update the base memory reservation if necessary.
2426	*/
2427	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
2428	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2429	cExtraBaseCost += cPages;
2430	if (cExtraBaseCost)
2431	{
2432	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2433	if (RT_FAILURE(rc))
2434	return rc;
2435	}
2436
2437	/*
2438	* Allocate memory for the virgin copy of the RAM.
2439	*/
2440	PGMMALLOCATEPAGESREQ pReq;
2441	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2442	AssertRCReturn(rc, rc);
2443
2444	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2445	{
2446	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2447	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2448	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2449	}
2450
2451	pgmLock(pVM);
2452	rc = GMMR3AllocatePagesPerform(pVM, pReq);
2453	pgmUnlock(pVM);
2454	if (RT_FAILURE(rc))
2455	{
2456	GMMR3AllocatePagesCleanup(pReq);
2457	return rc;
2458	}
2459
2460	/*
2461	* Allocate the new ROM range and RAM range (if necessary).
2462	*/
2463	PPGMROMRANGE pRomNew;
2464	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2465	if (RT_SUCCESS(rc))
2466	{
2467	PPGMRAMRANGE pRamNew = NULL;
2468	if (!fRamExists)
2469	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2470	if (RT_SUCCESS(rc))
2471	{
2472	pgmLock(pVM);
2473
2474	/*
2475	* Initialize and insert the RAM range (if required).
2476	*/
2477	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2478	if (!fRamExists)
2479	{
2480	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2481	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2482	pRamNew->GCPhys = GCPhys;
2483	pRamNew->GCPhysLast = GCPhysLast;
2484	pRamNew->cb = cb;
2485	pRamNew->pszDesc = pszDesc;
2486	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
2487	pRamNew->pvR3 = NULL;
2488	pRamNew->paLSPages = NULL;
2489
2490	PPGMPAGE pPage = &pRamNew->aPages[0];
2491	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2492	{
2493	PGM_PAGE_INIT(pPage,
2494	pReq->aPages[iPage].HCPhysGCPhys,
2495	pReq->aPages[iPage].idPage,
2496	PGMPAGETYPE_ROM,
2497	PGM_PAGE_STATE_ALLOCATED);
2498
2499	pRomPage->Virgin = *pPage;
2500	}
2501
2502	pVM->pgm.s.cAllPages += cPages;
2503	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2504	}
2505	else
2506	{
2507	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2508	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2509	{
2510	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2511	PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2512	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2513	PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2514
2515	pRomPage->Virgin = *pPage;
2516	}
2517
2518	pRamNew = pRam;
2519
2520	pVM->pgm.s.cZeroPages -= cPages;
2521	}
2522	pVM->pgm.s.cPrivatePages += cPages;
2523
2524	/* Flush physical page map TLB. */
2525	PGMPhysInvalidatePageMapTLB(pVM);
2526
2527	pgmUnlock(pVM);
2528
2529
2530	/*
2531	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2532	*
2533	* If it's shadowed we'll register the handler after the ROM notification
2534	* so we get the access handler callbacks that we should. If it isn't
2535	* shadowed we'll do it the other way around to make REM use the built-in
2536	* ROM behavior and not the handler behavior (which is to route all access
2537	* to PGM atm).
2538	*/
2539	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2540	{
2541	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2542	rc = PGMR3HandlerPhysicalRegister(pVM,
2543	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2544	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2545	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2546	GCPhys, GCPhysLast,
2547	pgmR3PhysRomWriteHandler, pRomNew,
2548	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2549	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2550	}
2551	else
2552	{
2553	rc = PGMR3HandlerPhysicalRegister(pVM,
2554	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2555	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2556	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2557	GCPhys, GCPhysLast,
2558	pgmR3PhysRomWriteHandler, pRomNew,
2559	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2560	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2561	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2562	}
2563	if (RT_SUCCESS(rc))
2564	{
2565	pgmLock(pVM);
2566
2567	/*
2568	* Copy the image over to the virgin pages.
2569	* This must be done after linking in the RAM range.
2570	*/
2571	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2572	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2573	{
2574	void *pvDstPage;
2575	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
2576	if (RT_FAILURE(rc))
2577	{
2578	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2579	break;
2580	}
2581	memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2582	}
2583	if (RT_SUCCESS(rc))
2584	{
2585	/*
2586	* Initialize the ROM range.
2587	* Note that the Virgin member of the pages has already been initialized above.
2588	*/
2589	pRomNew->GCPhys = GCPhys;
2590	pRomNew->GCPhysLast = GCPhysLast;
2591	pRomNew->cb = cb;
2592	pRomNew->fFlags = fFlags;
2593	pRomNew->idSavedState = UINT8_MAX;
2594	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2595	pRomNew->pszDesc = pszDesc;
2596
2597	for (unsigned iPage = 0; iPage < cPages; iPage++)
2598	{
2599	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2600	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2601	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2602	}
2603
2604	/* update the page count stats for the shadow pages. */
2605	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2606	{
2607	pVM->pgm.s.cZeroPages += cPages;
2608	pVM->pgm.s.cAllPages += cPages;
2609	}
2610
2611	/*
2612	* Insert the ROM range, tell REM and return successfully.
2613	*/
2614	pRomNew->pNextR3 = pRom;
2615	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2616	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2617
2618	if (pRomPrev)
2619	{
2620	pRomPrev->pNextR3 = pRomNew;
2621	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2622	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2623	}
2624	else
2625	{
2626	pVM->pgm.s.pRomRangesR3 = pRomNew;
2627	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2628	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2629	}
2630
2631	PGMPhysInvalidatePageMapTLB(pVM);
2632	GMMR3AllocatePagesCleanup(pReq);
2633	pgmUnlock(pVM);
2634	return VINF_SUCCESS;
2635	}
2636
2637	/* bail out */
2638
2639	pgmUnlock(pVM);
2640	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2641	AssertRC(rc2);
2642	pgmLock(pVM);
2643	}
2644
2645	if (!fRamExists)
2646	{
2647	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2648	MMHyperFree(pVM, pRamNew);
2649	}
2650	}
2651	MMHyperFree(pVM, pRomNew);
2652	}
2653
2654	/** @todo Purge the mapping cache or something... */
2655	GMMR3FreeAllocatedPages(pVM, pReq);
2656	GMMR3AllocatePagesCleanup(pReq);
2657	pgmUnlock(pVM);
2658	return rc;
2659	}
2660
2661
2662	/**
2663	* \#PF Handler callback for ROM write accesses.
2664	*
2665	* @returns VINF_SUCCESS if the handler have carried out the operation.
2666	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2667	* @param pVM VM Handle.
2668	* @param GCPhys The physical address the guest is writing to.
2669	* @param pvPhys The HC mapping of that address.
2670	* @param pvBuf What the guest is reading/writing.
2671	* @param cbBuf How much it's reading/writing.
2672	* @param enmAccessType The access type.
2673	* @param pvUser User argument.
2674	*/
2675	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2676	{
2677	PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2678	const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2679	Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2680	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2681	Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2682
2683	if (enmAccessType == PGMACCESSTYPE_READ)
2684	{
2685	switch (pRomPage->enmProt)
2686	{
2687	/*
2688	* Take the default action.
2689	*/
2690	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2691	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2692	case PGMROMPROT_READ_ROM_WRITE_RAM:
2693	case PGMROMPROT_READ_RAM_WRITE_RAM:
2694	return VINF_PGM_HANDLER_DO_DEFAULT;
2695
2696	default:
2697	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2698	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2699	VERR_INTERNAL_ERROR);
2700	}
2701	}
2702	else
2703	{
2704	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2705	switch (pRomPage->enmProt)
2706	{
2707	/*
2708	* Ignore writes.
2709	*/
2710	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2711	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2712	return VINF_SUCCESS;
2713
2714	/*
2715	* Write to the ram page.
2716	*/
2717	case PGMROMPROT_READ_ROM_WRITE_RAM:
2718	case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's way simpler that way. */
2719	{
2720	/* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2721	Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2722
2723	/*
2724	* Take the lock, do lazy allocation, map the page and copy the data.
2725	*
2726	* Note that we have to bypass the mapping TLB since it works on
2727	* guest physical addresses and entering the shadow page would
2728	* kind of screw things up...
2729	*/
2730	int rc = pgmLock(pVM);
2731	AssertRC(rc);
2732
2733	PPGMPAGE pShadowPage = &pRomPage->Shadow;
2734	if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2735	{
2736	pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2737	AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2738	}
2739
2740	void *pvDstPage;
2741	rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
2742	if (RT_SUCCESS(rc))
2743	{
2744	memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2745	pRomPage->LiveSave.fWrittenTo = true;
2746	}
2747
2748	pgmUnlock(pVM);
2749	return rc;
2750	}
2751
2752	default:
2753	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2754	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2755	VERR_INTERNAL_ERROR);
2756	}
2757	}
2758	}
2759
2760
2761	/**
2762	* Called by PGMR3Reset to reset the shadow, switch to the virgin,
2763	* and verify that the virgin part is untouched.
2764	*
2765	* This is done after the normal memory has been cleared.
2766	*
2767	* ASSUMES that the caller owns the PGM lock.
2768	*
2769	* @param pVM The VM handle.
2770	*/
2771	int pgmR3PhysRomReset(PVM pVM)
2772	{
2773	Assert(PGMIsLockOwner(pVM));
2774	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2775	{
2776	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2777
2778	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2779	{
2780	/*
2781	* Reset the physical handler.
2782	*/
2783	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2784	AssertRCReturn(rc, rc);
2785
2786	/*
2787	* What we do with the shadow pages depends on the memory
2788	* preallocation option. If not enabled, we'll just throw
2789	* out all the dirty pages and replace them by the zero page.
2790	*/
2791	if (!pVM->pgm.s.fRamPreAlloc)
2792	{
2793	/* Free the dirty pages. */
2794	uint32_t cPendingPages = 0;
2795	PGMMFREEPAGESREQ pReq;
2796	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2797	AssertRCReturn(rc, rc);
2798
2799	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2800	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
2801	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
2802	{
2803	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2804	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2805	AssertLogRelRCReturn(rc, rc);
2806	}
2807
2808	if (cPendingPages)
2809	{
2810	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2811	AssertLogRelRCReturn(rc, rc);
2812	}
2813	GMMR3FreePagesCleanup(pReq);
2814	}
2815	else
2816	{
2817	/* clear all the shadow pages. */
2818	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2819	{
2820	Assert(!PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
2821	void *pvDstPage;
2822	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2823	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
2824	if (RT_FAILURE(rc))
2825	break;
2826	ASMMemZeroPage(pvDstPage);
2827	}
2828	AssertRCReturn(rc, rc);
2829	}
2830	}
2831
2832	#ifdef VBOX_STRICT
2833	/*
2834	* Verify that the virgin page is unchanged if possible.
2835	*/
2836	if (pRom->pvOriginal)
2837	{
2838	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
2839	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2840	{
2841	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2842	void const *pvDstPage;
2843	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
2844	if (RT_FAILURE(rc))
2845	break;
2846	if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2847	LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2848	GCPhys, pRom->pszDesc));
2849	}
2850	}
2851	#endif
2852	}
2853
2854	return VINF_SUCCESS;
2855	}
2856
2857
2858	/**
2859	* Change the shadowing of a range of ROM pages.
2860	*
2861	* This is intended for implementing chipset specific memory registers
2862	* and will not be very strict about the input. It will silently ignore
2863	* any pages that are not the part of a shadowed ROM.
2864	*
2865	* @returns VBox status code.
2866	* @retval VINF_PGM_SYNC_CR3
2867	*
2868	* @param pVM Pointer to the shared VM structure.
2869	* @param GCPhys Where to start. Page aligned.
2870	* @param cb How much to change. Page aligned.
2871	* @param enmProt The new ROM protection.
2872	*/
2873	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2874	{
2875	/*
2876	* Check input
2877	*/
2878	if (!cb)
2879	return VINF_SUCCESS;
2880	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2881	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2882	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2883	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2884	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2885
2886	/*
2887	* Process the request.
2888	*/
2889	pgmLock(pVM);
2890	int rc = VINF_SUCCESS;
2891	bool fFlushTLB = false;
2892	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2893	{
2894	if ( GCPhys <= pRom->GCPhysLast
2895	&& GCPhysLast >= pRom->GCPhys
2896	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2897	{
2898	/*
2899	* Iterate the relevant pages and make necessary the changes.
2900	*/
2901	bool fChanges = false;
2902	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2903	? pRom->cb >> PAGE_SHIFT
2904	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2905	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2906	iPage < cPages;
2907	iPage++)
2908	{
2909	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2910	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2911	{
2912	fChanges = true;
2913
2914	/* flush references to the page. */
2915	PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2916	int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage, &fFlushTLB);
2917	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
2918	rc = rc2;
2919
2920	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2921	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2922
2923	pOld = pRamPage;
2924	pRamPage = pNew;
2925	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2926	}
2927	pRomPage->enmProt = enmProt;
2928	}
2929
2930	/*
2931	* Reset the access handler if we made changes, no need
2932	* to optimize this.
2933	*/
2934	if (fChanges)
2935	{
2936	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2937	if (RT_FAILURE(rc2))
2938	{
2939	pgmUnlock(pVM);
2940	AssertRC(rc);
2941	return rc2;
2942	}
2943	}
2944
2945	/* Advance - cb isn't updated. */
2946	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2947	}
2948	}
2949	pgmUnlock(pVM);
2950	if (fFlushTLB)
2951	PGM_INVL_ALL_VCPU_TLBS(pVM);
2952
2953	return rc;
2954	}
2955
2956
2957	/**
2958	* Sets the Address Gate 20 state.
2959	*
2960	* @param pVCpu The VCPU to operate on.
2961	* @param fEnable True if the gate should be enabled.
2962	* False if the gate should be disabled.
2963	*/
2964	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
2965	{
2966	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
2967	if (pVCpu->pgm.s.fA20Enabled != fEnable)
2968	{
2969	pVCpu->pgm.s.fA20Enabled = fEnable;
2970	pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2971	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
2972	/** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2973	}
2974	}
2975
2976
2977	/**
2978	* Tree enumeration callback for dealing with age rollover.
2979	* It will perform a simple compression of the current age.
2980	*/
2981	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2982	{
2983	Assert(PGMIsLockOwner((PVM)pvUser));
2984	/* Age compression - ASSUMES iNow == 4. */
2985	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2986	if (pChunk->iAge >= UINT32_C(0xffffff00))
2987	pChunk->iAge = 3;
2988	else if (pChunk->iAge >= UINT32_C(0xfffff000))
2989	pChunk->iAge = 2;
2990	else if (pChunk->iAge)
2991	pChunk->iAge = 1;
2992	else /* iAge = 0 */
2993	pChunk->iAge = 4;
2994
2995	/* reinsert */
2996	PVM pVM = (PVM)pvUser;
2997	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2998	pChunk->AgeCore.Key = pChunk->iAge;
2999	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3000	return 0;
3001	}
3002
3003
3004	/**
3005	* Tree enumeration callback that updates the chunks that have
3006	* been used since the last
3007	*/
3008	static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
3009	{
3010	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3011	if (!pChunk->iAge)
3012	{
3013	PVM pVM = (PVM)pvUser;
3014	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
3015	pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
3016	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3017	}
3018
3019	return 0;
3020	}
3021
3022
3023	/**
3024	* Performs ageing of the ring-3 chunk mappings.
3025	*
3026	* @param pVM The VM handle.
3027	*/
3028	VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
3029	{
3030	pgmLock(pVM);
3031	pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
3032	pVM->pgm.s.ChunkR3Map.iNow++;
3033	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
3034	{
3035	pVM->pgm.s.ChunkR3Map.iNow = 4;
3036	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
3037	}
3038	else
3039	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingCallback, pVM);
3040	pgmUnlock(pVM);
3041	}
3042
3043
3044	/**
3045	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
3046	*/
3047	typedef struct PGMR3PHYSCHUNKUNMAPCB
3048	{
3049	PVM pVM; /*< The VM handle. /
3050	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
3051	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
3052
3053
3054	/**
3055	* Callback used to find the mapping that's been unused for
3056	* the longest time.
3057	*/
3058	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
3059	{
3060	do
3061	{
3062	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
3063	if ( pChunk->iAge
3064	&& !pChunk->cRefs)
3065	{
3066	/*
3067	* Check that it's not in any of the TLBs.
3068	*/
3069	PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
3070	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3071	if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
3072	{
3073	pChunk = NULL;
3074	break;
3075	}
3076	if (pChunk)
3077	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
3078	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
3079	{
3080	pChunk = NULL;
3081	break;
3082	}
3083	if (pChunk)
3084	{
3085	((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
3086	return 1; /* done */
3087	}
3088	}
3089
3090	/* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
3091	pNode = pNode->pList;
3092	} while (pNode);
3093	return 0;
3094	}
3095
3096
3097	/**
3098	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
3099	*
3100	* The candidate will not be part of any TLBs, so no need to flush
3101	* anything afterwards.
3102	*
3103	* @returns Chunk id.
3104	* @param pVM The VM handle.
3105	*/
3106	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
3107	{
3108	Assert(PGMIsLockOwner(pVM));
3109
3110	/*
3111	* Do tree ageing first?
3112	*/
3113	if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
3114	PGMR3PhysChunkAgeing(pVM);
3115
3116	/*
3117	* Enumerate the age tree starting with the left most node.
3118	*/
3119	PGMR3PHYSCHUNKUNMAPCB Args;
3120	Args.pVM = pVM;
3121	Args.pChunk = NULL;
3122	if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
3123	return Args.pChunk->Core.Key;
3124	return INT32_MAX;
3125	}
3126
3127
3128	/**
3129	* Maps the given chunk into the ring-3 mapping cache.
3130	*
3131	* This will call ring-0.
3132	*
3133	* @returns VBox status code.
3134	* @param pVM The VM handle.
3135	* @param idChunk The chunk in question.
3136	* @param ppChunk Where to store the chunk tracking structure.
3137	*
3138	* @remarks Called from within the PGM critical section.
3139	*/
3140	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
3141	{
3142	int rc;
3143
3144	Assert(PGMIsLockOwner(pVM));
3145	/*
3146	* Allocate a new tracking structure first.
3147	*/
3148	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3149	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
3150	#else
3151	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
3152	#endif
3153	AssertReturn(pChunk, VERR_NO_MEMORY);
3154	pChunk->Core.Key = idChunk;
3155	pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
3156	pChunk->iAge = 0;
3157	pChunk->cRefs = 0;
3158	pChunk->cPermRefs = 0;
3159	pChunk->pv = NULL;
3160
3161	/*
3162	* Request the ring-0 part to map the chunk in question and if
3163	* necessary unmap another one to make space in the mapping cache.
3164	*/
3165	GMMMAPUNMAPCHUNKREQ Req;
3166	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3167	Req.Hdr.cbReq = sizeof(Req);
3168	Req.pvR3 = NULL;
3169	Req.idChunkMap = idChunk;
3170	Req.idChunkUnmap = NIL_GMM_CHUNKID;
3171	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3172	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
3173	/** @todo This is wrong. Any thread in the VM process should be able to do this,
3174	* there are depenenecies on this. What currently saves the day is that
3175	* we don't unmap anything and that all non-zero memory will therefore
3176	* be present when non-EMTs tries to access it. */
3177	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3178	if (RT_SUCCESS(rc))
3179	{
3180	/*
3181	* Update the tree.
3182	*/
3183	/* insert the new one. */
3184	AssertPtr(Req.pvR3);
3185	pChunk->pv = Req.pvR3;
3186	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
3187	AssertRelease(fRc);
3188	pVM->pgm.s.ChunkR3Map.c++;
3189
3190	fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3191	AssertRelease(fRc);
3192
3193	/* remove the unmapped one. */
3194	if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
3195	{
3196	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
3197	AssertRelease(pUnmappedChunk);
3198	pUnmappedChunk->pv = NULL;
3199	pUnmappedChunk->Core.Key = UINT32_MAX;
3200	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3201	MMR3HeapFree(pUnmappedChunk);
3202	#else
3203	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3204	#endif
3205	pVM->pgm.s.ChunkR3Map.c--;
3206
3207	/* Chunk removed, so clear the page map TBL as well (might still be referenced). */
3208	PGMPhysInvalidatePageMapTLB(pVM);
3209	}
3210	}
3211	else
3212	{
3213	AssertRC(rc);
3214	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3215	MMR3HeapFree(pChunk);
3216	#else
3217	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
3218	#endif
3219	pChunk = NULL;
3220	}
3221
3222	*ppChunk = pChunk;
3223	return rc;
3224	}
3225
3226
3227	/**
3228	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3229	*
3230	* @returns see pgmR3PhysChunkMap.
3231	* @param pVM The VM handle.
3232	* @param idChunk The chunk to map.
3233	*/
3234	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3235	{
3236	PPGMCHUNKR3MAP pChunk;
3237	int rc;
3238
3239	pgmLock(pVM);
3240	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3241	pgmUnlock(pVM);
3242	return rc;
3243	}
3244
3245
3246	/**
3247	* Invalidates the TLB for the ring-3 mapping cache.
3248	*
3249	* @param pVM The VM handle.
3250	*/
3251	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3252	{
3253	pgmLock(pVM);
3254	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3255	{
3256	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3257	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3258	}
3259	/* The page map TLB references chunks, so invalidate that one too. */
3260	PGMPhysInvalidatePageMapTLB(pVM);
3261	pgmUnlock(pVM);
3262	}
3263
3264
3265	/**
3266	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_PAGE to allocate a large (2MB) page
3267	* for use with a nested paging PDE.
3268	*
3269	* @returns The following VBox status codes.
3270	* @retval VINF_SUCCESS on success.
3271	* @retval VINF_EM_NO_MEMORY if we're out of memory.
3272	*
3273	* @param pVM The VM handle.
3274	* @param GCPhys GC physical start address of the 2 MB range
3275	*/
3276	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
3277	{
3278	pgmLock(pVM);
3279
3280	STAM_PROFILE_START(&pVM->pgm.s.StatAllocLargePage, a);
3281	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
3282	STAM_PROFILE_STOP(&pVM->pgm.s.StatAllocLargePage, a);
3283	if (RT_SUCCESS(rc))
3284	{
3285	Assert(pVM->pgm.s.cLargeHandyPages == 1);
3286
3287	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
3288	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
3289
3290	void *pv;
3291
3292	/* Map the large page into our address space.
3293	*
3294	* Note: assuming that within the 2 MB range:
3295	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
3296	* - user space mapping is continuous as well
3297	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
3298	*/
3299	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
3300	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", idPage, HCPhys, rc));
3301
3302	if (RT_SUCCESS(rc))
3303	{
3304	/*
3305	* Clear the pages.
3306	*/
3307	STAM_PROFILE_START(&pVM->pgm.s.StatClearLargePage, b);
3308	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
3309	{
3310	ASMMemZeroPage(pv);
3311
3312	PPGMPAGE pPage;
3313	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
3314	AssertRC(rc);
3315
3316	Assert(PGM_PAGE_IS_ZERO(pPage));
3317	STAM_COUNTER_INC(&pVM->pgm.s.StatRZPageReplaceZero);
3318	pVM->pgm.s.cZeroPages--;
3319
3320	/*
3321	* Do the PGMPAGE modifications.
3322	*/
3323	pVM->pgm.s.cPrivatePages++;
3324	PGM_PAGE_SET_HCPHYS(pPage, HCPhys);
3325	PGM_PAGE_SET_PAGEID(pPage, idPage);
3326	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
3327	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_PDE);
3328
3329	/* Somewhat dirty assumption that page ids are increasing. */
3330	idPage++;
3331
3332	HCPhys += PAGE_SIZE;
3333	GCPhys += PAGE_SIZE;
3334
3335	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
3336
3337	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
3338	}
3339	STAM_PROFILE_STOP(&pVM->pgm.s.StatClearLargePage, b);
3340
3341	/* Flush all TLBs. */
3342	PGM_INVL_ALL_VCPU_TLBS(pVM);
3343	PGMPhysInvalidatePageMapTLB(pVM);
3344	}
3345	pVM->pgm.s.cLargeHandyPages = 0;
3346	}
3347
3348	pgmUnlock(pVM);
3349	return rc;
3350	}
3351
3352
3353	/**
3354	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3355	*
3356	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3357	* signal and clear the out of memory condition. When contracted, this API is
3358	* used to try clear the condition when the user wants to resume.
3359	*
3360	* @returns The following VBox status codes.
3361	* @retval VINF_SUCCESS on success. FFs cleared.
3362	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3363	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3364	*
3365	* @param pVM The VM handle.
3366	*
3367	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3368	* in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3369	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3370	* handler.
3371	*/
3372	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3373	{
3374	pgmLock(pVM);
3375
3376	/*
3377	* Allocate more pages, noting down the index of the first new page.
3378	*/
3379	uint32_t iClear = pVM->pgm.s.cHandyPages;
3380	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3381	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3382	int rcAlloc = VINF_SUCCESS;
3383	int rcSeed = VINF_SUCCESS;
3384	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3385	while (rc == VERR_GMM_SEED_ME)
3386	{
3387	void *pvChunk;
3388	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3389	if (RT_SUCCESS(rc))
3390	{
3391	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3392	if (RT_FAILURE(rc))
3393	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3394	}
3395	if (RT_SUCCESS(rc))
3396	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3397	}
3398
3399	if (RT_SUCCESS(rc))
3400	{
3401	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3402	Assert(pVM->pgm.s.cHandyPages > 0);
3403	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3404	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3405
3406	/*
3407	* Clear the pages.
3408	*/
3409	while (iClear < pVM->pgm.s.cHandyPages)
3410	{
3411	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3412	void *pv;
3413	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3414	AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3415	ASMMemZeroPage(pv);
3416	iClear++;
3417	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3418	}
3419	}
3420	else
3421	{
3422	/*
3423	* We should never get here unless there is a genuine shortage of
3424	* memory (or some internal error). Flag the error so the VM can be
3425	* suspended ASAP and the user informed. If we're totally out of
3426	* handy pages we will return failure.
3427	*/
3428	/* Report the failure. */
3429	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3430	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3431	rc, rcAlloc, rcSeed,
3432	pVM->pgm.s.cHandyPages,
3433	pVM->pgm.s.cAllPages,
3434	pVM->pgm.s.cPrivatePages,
3435	pVM->pgm.s.cSharedPages,
3436	pVM->pgm.s.cZeroPages));
3437	if ( rc != VERR_NO_MEMORY
3438	&& rc != VERR_LOCK_FAILED)
3439	{
3440	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3441	{
3442	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3443	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3444	pVM->pgm.s.aHandyPages[i].idSharedPage));
3445	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3446	if (idPage != NIL_GMM_PAGEID)
3447	{
3448	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3449	pRam;
3450	pRam = pRam->pNextR3)
3451	{
3452	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3453	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3454	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3455	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3456	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3457	}
3458	}
3459	}
3460	}
3461
3462	/* Set the FFs and adjust rc. */
3463	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3464	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3465	if ( rc == VERR_NO_MEMORY
3466	\|\| rc == VERR_LOCK_FAILED)
3467	rc = VINF_EM_NO_MEMORY;
3468	}
3469
3470	pgmUnlock(pVM);
3471	return rc;
3472	}
3473
3474
3475	/**
3476	* Frees the specified RAM page and replaces it with the ZERO page.
3477	*
3478	* This is used by ballooning, remapping MMIO2 and RAM reset.
3479	*
3480	* @param pVM Pointer to the shared VM structure.
3481	* @param pReq Pointer to the request.
3482	* @param pPage Pointer to the page structure.
3483	* @param GCPhys The guest physical address of the page, if applicable.
3484	*
3485	* @remarks The caller must own the PGM lock.
3486	*/
3487	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3488	{
3489	/*
3490	* Assert sanity.
3491	*/
3492	Assert(PGMIsLockOwner(pVM));
3493	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3494	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3495	{
3496	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3497	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3498	}
3499
3500	if ( PGM_PAGE_IS_ZERO(pPage)
3501	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3502	return VINF_SUCCESS;
3503
3504	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3505	Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3506	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3507	\|\| idPage > GMM_PAGEID_LAST
3508	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3509	{
3510	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3511	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3512	}
3513
3514	/* update page count stats. */
3515	if (PGM_PAGE_IS_SHARED(pPage))
3516	pVM->pgm.s.cSharedPages--;
3517	else
3518	pVM->pgm.s.cPrivatePages--;
3519	pVM->pgm.s.cZeroPages++;
3520
3521	/* Deal with write monitored pages. */
3522	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
3523	{
3524	PGM_PAGE_SET_WRITTEN_TO(pPage);
3525	pVM->pgm.s.cWrittenToPages++;
3526	}
3527
3528	/*
3529	* pPage = ZERO page.
3530	*/
3531	PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3532	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3533	PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3534	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
3535
3536	/* Flush physical page map TLB entry. */
3537	PGMPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
3538
3539	/*
3540	* Make sure it's not in the handy page array.
3541	*/
3542	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3543	{
3544	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3545	{
3546	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3547	break;
3548	}
3549	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3550	{
3551	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3552	break;
3553	}
3554	}
3555
3556	/*
3557	* Push it onto the page array.
3558	*/
3559	uint32_t iPage = *pcPendingPages;
3560	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3561	*pcPendingPages += 1;
3562
3563	pReq->aPages[iPage].idPage = idPage;
3564
3565	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3566	return VINF_SUCCESS;
3567
3568	/*
3569	* Flush the pages.
3570	*/
3571	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3572	if (RT_SUCCESS(rc))
3573	{
3574	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3575	*pcPendingPages = 0;
3576	}
3577	return rc;
3578	}
3579
3580
3581	/**
3582	* Converts a GC physical address to a HC ring-3 pointer, with some
3583	* additional checks.
3584	*
3585	* @returns VBox status code.
3586	* @retval VINF_SUCCESS on success.
3587	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3588	* access handler of some kind.
3589	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3590	* accesses or is odd in any way.
3591	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3592	*
3593	* @param pVM The VM handle.
3594	* @param GCPhys The GC physical address to convert.
3595	* @param fWritable Whether write access is required.
3596	* @param ppv Where to store the pointer corresponding to GCPhys on
3597	* success.
3598	*/
3599	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3600	{
3601	pgmLock(pVM);
3602
3603	PPGMRAMRANGE pRam;
3604	PPGMPAGE pPage;
3605	int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3606	if (RT_SUCCESS(rc))
3607	{
3608	if (PGM_PAGE_IS_BALLOONED(pPage))
3609	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3610	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3611	rc = VINF_SUCCESS;
3612	else
3613	{
3614	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3615	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3616	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3617	{
3618	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3619	* in -norawr0 mode. */
3620	if (fWritable)
3621	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3622	}
3623	else
3624	{
3625	/* Temporarily disabled physical handler(s), since the recompiler
3626	doesn't get notified when it's reset we'll have to pretend it's
3627	operating normally. */
3628	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3629	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3630	else
3631	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3632	}
3633	}
3634	if (RT_SUCCESS(rc))
3635	{
3636	int rc2;
3637
3638	/* Make sure what we return is writable. */
3639	if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3640	switch (PGM_PAGE_GET_STATE(pPage))
3641	{
3642	case PGM_PAGE_STATE_ALLOCATED:
3643	break;
3644	case PGM_PAGE_STATE_BALLOONED:
3645	AssertFailed();
3646	break;
3647	case PGM_PAGE_STATE_ZERO:
3648	case PGM_PAGE_STATE_SHARED:
3649	case PGM_PAGE_STATE_WRITE_MONITORED:
3650	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3651	AssertLogRelRCReturn(rc2, rc2);
3652	break;
3653	}
3654
3655	/* Get a ring-3 mapping of the address. */
3656	PPGMPAGER3MAPTLBE pTlbe;
3657	rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3658	AssertLogRelRCReturn(rc2, rc2);
3659	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
3660	/** @todo mapping/locking hell; this isn't horribly efficient since
3661	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
3662
3663	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
3664	}
3665	else
3666	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3667
3668	/* else: handler catching all access, no pointer returned. */
3669	}
3670	else
3671	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3672
3673	pgmUnlock(pVM);
3674	return rc;
3675	}
3676

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source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 27590

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