PGMPhys.cpp@ 27746

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1	/* $Id: PGMPhys.cpp 27746 2010-03-26 14:55:02Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_PHYS
27	#include <VBox/pgm.h>
28	#include <VBox/iom.h>
29	#include <VBox/mm.h>
30	#include <VBox/stam.h>
31	#include <VBox/rem.h>
32	#include <VBox/pdmdev.h>
33	#include "PGMInternal.h"
34	#include <VBox/vm.h>
35	#include "PGMInline.h"
36	#include <VBox/sup.h>
37	#include <VBox/param.h>
38	#include <VBox/err.h>
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/alloc.h>
42	#include <iprt/asm.h>
43	#include <iprt/thread.h>
44	#include <iprt/string.h>
45
46
47	/*******************************************************************************
48	* Defined Constants And Macros *
49	*******************************************************************************/
50	/** The number of pages to free in one batch. */
51	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
52
53
54	/*******************************************************************************
55	* Internal Functions *
56	*******************************************************************************/
57	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
58	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
59
60
61	/*
62	* PGMR3PhysReadU8-64
63	* PGMR3PhysWriteU8-64
64	*/
65	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
66	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
67	#define PGMPHYS_DATASIZE 1
68	#define PGMPHYS_DATATYPE uint8_t
69	#include "PGMPhysRWTmpl.h"
70
71	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
72	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
73	#define PGMPHYS_DATASIZE 2
74	#define PGMPHYS_DATATYPE uint16_t
75	#include "PGMPhysRWTmpl.h"
76
77	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
78	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
79	#define PGMPHYS_DATASIZE 4
80	#define PGMPHYS_DATATYPE uint32_t
81	#include "PGMPhysRWTmpl.h"
82
83	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
84	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
85	#define PGMPHYS_DATASIZE 8
86	#define PGMPHYS_DATATYPE uint64_t
87	#include "PGMPhysRWTmpl.h"
88
89
90	/**
91	* EMT worker for PGMR3PhysReadExternal.
92	*/
93	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
94	{
95	PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
96	return VINF_SUCCESS;
97	}
98
99
100	/**
101	* Write to physical memory, external users.
102	*
103	* @returns VBox status code.
104	* @retval VINF_SUCCESS.
105	*
106	* @param pVM VM Handle.
107	* @param GCPhys Physical address to write to.
108	* @param pvBuf What to write.
109	* @param cbWrite How many bytes to write.
110	*
111	* @thread Any but EMTs.
112	*/
113	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
114	{
115	VM_ASSERT_OTHER_THREAD(pVM);
116
117	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
118	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
119
120	pgmLock(pVM);
121
122	/*
123	* Copy loop on ram ranges.
124	*/
125	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
126	for (;;)
127	{
128	/* Find range. */
129	while (pRam && GCPhys > pRam->GCPhysLast)
130	pRam = pRam->CTX_SUFF(pNext);
131	/* Inside range or not? */
132	if (pRam && GCPhys >= pRam->GCPhys)
133	{
134	/*
135	* Must work our way thru this page by page.
136	*/
137	RTGCPHYS off = GCPhys - pRam->GCPhys;
138	while (off < pRam->cb)
139	{
140	unsigned iPage = off >> PAGE_SHIFT;
141	PPGMPAGE pPage = &pRam->aPages[iPage];
142
143	/*
144	* If the page has an ALL access handler, we'll have to
145	* delegate the job to EMT.
146	*/
147	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
148	{
149	pgmUnlock(pVM);
150
151	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 4,
152	pVM, &GCPhys, pvBuf, cbRead);
153	}
154	Assert(!PGM_PAGE_IS_MMIO(pPage));
155
156	/*
157	* Simple stuff, go ahead.
158	*/
159	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
160	if (cb > cbRead)
161	cb = cbRead;
162	const void *pvSrc;
163	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
164	if (RT_SUCCESS(rc))
165	memcpy(pvBuf, pvSrc, cb);
166	else
167	{
168	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
169	pRam->GCPhys + off, pPage, rc));
170	memset(pvBuf, 0xff, cb);
171	}
172
173	/* next page */
174	if (cb >= cbRead)
175	{
176	pgmUnlock(pVM);
177	return VINF_SUCCESS;
178	}
179	cbRead -= cb;
180	off += cb;
181	GCPhys += cb;
182	pvBuf = (char *)pvBuf + cb;
183	} /* walk pages in ram range. */
184	}
185	else
186	{
187	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
188
189	/*
190	* Unassigned address space.
191	*/
192	if (!pRam)
193	break;
194	size_t cb = pRam->GCPhys - GCPhys;
195	if (cb >= cbRead)
196	{
197	memset(pvBuf, 0xff, cbRead);
198	break;
199	}
200	memset(pvBuf, 0xff, cb);
201
202	cbRead -= cb;
203	pvBuf = (char *)pvBuf + cb;
204	GCPhys += cb;
205	}
206	} /* Ram range walk */
207
208	pgmUnlock(pVM);
209
210	return VINF_SUCCESS;
211	}
212
213
214	/**
215	* EMT worker for PGMR3PhysWriteExternal.
216	*/
217	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
218	{
219	/** @todo VERR_EM_NO_MEMORY */
220	PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
221	return VINF_SUCCESS;
222	}
223
224
225	/**
226	* Write to physical memory, external users.
227	*
228	* @returns VBox status code.
229	* @retval VINF_SUCCESS.
230	* @retval VERR_EM_NO_MEMORY.
231	*
232	* @param pVM VM Handle.
233	* @param GCPhys Physical address to write to.
234	* @param pvBuf What to write.
235	* @param cbWrite How many bytes to write.
236	* @param pszWho Who is writing. For tracking down who is writing
237	* after we've saved the state.
238	*
239	* @thread Any but EMTs.
240	*/
241	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void pvBuf, size_t cbWrite, const char pszWho)
242	{
243	VM_ASSERT_OTHER_THREAD(pVM);
244
245	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
246	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x pszWho=%s\n",
247	GCPhys, cbWrite, pszWho));
248	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
249	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
250
251	pgmLock(pVM);
252
253	/*
254	* Copy loop on ram ranges, stop when we hit something difficult.
255	*/
256	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
257	for (;;)
258	{
259	/* Find range. */
260	while (pRam && GCPhys > pRam->GCPhysLast)
261	pRam = pRam->CTX_SUFF(pNext);
262	/* Inside range or not? */
263	if (pRam && GCPhys >= pRam->GCPhys)
264	{
265	/*
266	* Must work our way thru this page by page.
267	*/
268	RTGCPTR off = GCPhys - pRam->GCPhys;
269	while (off < pRam->cb)
270	{
271	RTGCPTR iPage = off >> PAGE_SHIFT;
272	PPGMPAGE pPage = &pRam->aPages[iPage];
273
274	/*
275	* Is the page problematic, we have to do the work on the EMT.
276	*
277	* Allocating writable pages and access handlers are
278	* problematic, write monitored pages are simple and can be
279	* dealth with here.
280	*/
281	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
282	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
283	{
284	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
285	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
286	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
287	else
288	{
289	pgmUnlock(pVM);
290
291	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 4,
292	pVM, &GCPhys, pvBuf, cbWrite);
293	}
294	}
295	Assert(!PGM_PAGE_IS_MMIO(pPage));
296
297	/*
298	* Simple stuff, go ahead.
299	*/
300	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
301	if (cb > cbWrite)
302	cb = cbWrite;
303	void *pvDst;
304	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
305	if (RT_SUCCESS(rc))
306	memcpy(pvDst, pvBuf, cb);
307	else
308	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
309	pRam->GCPhys + off, pPage, rc));
310
311	/* next page */
312	if (cb >= cbWrite)
313	{
314	pgmUnlock(pVM);
315	return VINF_SUCCESS;
316	}
317
318	cbWrite -= cb;
319	off += cb;
320	GCPhys += cb;
321	pvBuf = (const char *)pvBuf + cb;
322	} /* walk pages in ram range */
323	}
324	else
325	{
326	/*
327	* Unassigned address space, skip it.
328	*/
329	if (!pRam)
330	break;
331	size_t cb = pRam->GCPhys - GCPhys;
332	if (cb >= cbWrite)
333	break;
334	cbWrite -= cb;
335	pvBuf = (const char *)pvBuf + cb;
336	GCPhys += cb;
337	}
338	} /* Ram range walk */
339
340	pgmUnlock(pVM);
341	return VINF_SUCCESS;
342	}
343
344
345	/**
346	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
347	*
348	* @returns see PGMR3PhysGCPhys2CCPtrExternal
349	* @param pVM The VM handle.
350	* @param pGCPhys Pointer to the guest physical address.
351	* @param ppv Where to store the mapping address.
352	* @param pLock Where to store the lock.
353	*/
354	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
355	{
356	/*
357	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
358	* an access handler after it succeeds.
359	*/
360	int rc = pgmLock(pVM);
361	AssertRCReturn(rc, rc);
362
363	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
364	if (RT_SUCCESS(rc))
365	{
366	PPGMPAGEMAPTLBE pTlbe;
367	int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
368	AssertFatalRC(rc2);
369	PPGMPAGE pPage = pTlbe->pPage;
370	if (PGM_PAGE_IS_MMIO(pPage))
371	{
372	PGMPhysReleasePageMappingLock(pVM, pLock);
373	rc = VERR_PGM_PHYS_PAGE_RESERVED;
374	}
375	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
376	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
377	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
378	#endif
379	)
380	{
381	/* We must flush any corresponding pgm pool page here, otherwise we'll
382	* not be informed about writes and keep bogus gst->shw mappings around.
383	*/
384	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
385	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
386	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
387	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
388	}
389	}
390
391	pgmUnlock(pVM);
392	return rc;
393	}
394
395
396	/**
397	* Requests the mapping of a guest page into ring-3, external threads.
398	*
399	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
400	* release it.
401	*
402	* This API will assume your intention is to write to the page, and will
403	* therefore replace shared and zero pages. If you do not intend to modify the
404	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
405	*
406	* @returns VBox status code.
407	* @retval VINF_SUCCESS on success.
408	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
409	* backing or if the page has any active access handlers. The caller
410	* must fall back on using PGMR3PhysWriteExternal.
411	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
412	*
413	* @param pVM The VM handle.
414	* @param GCPhys The guest physical address of the page that should be mapped.
415	* @param ppv Where to store the address corresponding to GCPhys.
416	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
417	*
418	* @remark Avoid calling this API from within critical sections (other than the
419	* PGM one) because of the deadlock risk when we have to delegating the
420	* task to an EMT.
421	* @thread Any.
422	*/
423	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
424	{
425	AssertPtr(ppv);
426	AssertPtr(pLock);
427
428	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
429
430	int rc = pgmLock(pVM);
431	AssertRCReturn(rc, rc);
432
433	/*
434	* Query the Physical TLB entry for the page (may fail).
435	*/
436	PPGMPAGEMAPTLBE pTlbe;
437	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
438	if (RT_SUCCESS(rc))
439	{
440	PPGMPAGE pPage = pTlbe->pPage;
441	if (PGM_PAGE_IS_MMIO(pPage))
442	rc = VERR_PGM_PHYS_PAGE_RESERVED;
443	else
444	{
445	/*
446	* If the page is shared, the zero page, or being write monitored
447	* it must be converted to an page that's writable if possible.
448	* We can only deal with write monitored pages here, the rest have
449	* to be on an EMT.
450	*/
451	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
452	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
453	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
454	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
455	#endif
456	)
457	{
458	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
459	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
460	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
461	&& !pgmPoolIsDirtyPage(pVM, GCPhys)
462	#endif
463	)
464	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
465	else
466	{
467	pgmUnlock(pVM);
468
469	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
470	pVM, &GCPhys, ppv, pLock);
471	}
472	}
473
474	/*
475	* Now, just perform the locking and calculate the return address.
476	*/
477	PPGMPAGEMAP pMap = pTlbe->pMap;
478	if (pMap)
479	pMap->cRefs++;
480
481	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
482	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
483	{
484	if (cLocks == 0)
485	pVM->pgm.s.cWriteLockedPages++;
486	PGM_PAGE_INC_WRITE_LOCKS(pPage);
487	}
488	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
489	{
490	PGM_PAGE_INC_WRITE_LOCKS(pPage);
491	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
492	if (pMap)
493	pMap->cRefs++; /* Extra ref to prevent it from going away. */
494	}
495
496	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
497	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
498	pLock->pvMap = pMap;
499	}
500	}
501
502	pgmUnlock(pVM);
503	return rc;
504	}
505
506
507	/**
508	* Requests the mapping of a guest page into ring-3, external threads.
509	*
510	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
511	* release it.
512	*
513	* @returns VBox status code.
514	* @retval VINF_SUCCESS on success.
515	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
516	* backing or if the page as an active ALL access handler. The caller
517	* must fall back on using PGMPhysRead.
518	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
519	*
520	* @param pVM The VM handle.
521	* @param GCPhys The guest physical address of the page that should be mapped.
522	* @param ppv Where to store the address corresponding to GCPhys.
523	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
524	*
525	* @remark Avoid calling this API from within critical sections (other than
526	* the PGM one) because of the deadlock risk.
527	* @thread Any.
528	*/
529	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
530	{
531	int rc = pgmLock(pVM);
532	AssertRCReturn(rc, rc);
533
534	/*
535	* Query the Physical TLB entry for the page (may fail).
536	*/
537	PPGMPAGEMAPTLBE pTlbe;
538	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
539	if (RT_SUCCESS(rc))
540	{
541	PPGMPAGE pPage = pTlbe->pPage;
542	#if 1
543	/* MMIO pages doesn't have any readable backing. */
544	if (PGM_PAGE_IS_MMIO(pPage))
545	rc = VERR_PGM_PHYS_PAGE_RESERVED;
546	#else
547	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
548	rc = VERR_PGM_PHYS_PAGE_RESERVED;
549	#endif
550	else
551	{
552	/*
553	* Now, just perform the locking and calculate the return address.
554	*/
555	PPGMPAGEMAP pMap = pTlbe->pMap;
556	if (pMap)
557	pMap->cRefs++;
558
559	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
560	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
561	{
562	if (cLocks == 0)
563	pVM->pgm.s.cReadLockedPages++;
564	PGM_PAGE_INC_READ_LOCKS(pPage);
565	}
566	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
567	{
568	PGM_PAGE_INC_READ_LOCKS(pPage);
569	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
570	if (pMap)
571	pMap->cRefs++; /* Extra ref to prevent it from going away. */
572	}
573
574	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
575	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
576	pLock->pvMap = pMap;
577	}
578	}
579
580	pgmUnlock(pVM);
581	return rc;
582	}
583
584
585	/**
586	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
587	*
588	* Called when anything was relocated.
589	*
590	* @param pVM Pointer to the shared VM structure.
591	*/
592	void pgmR3PhysRelinkRamRanges(PVM pVM)
593	{
594	PPGMRAMRANGE pCur;
595
596	#ifdef VBOX_STRICT
597	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
598	{
599	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
600	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
601	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
602	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
603	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
604	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
605	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
606	Assert( pCur2 == pCur
607	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
608	}
609	#endif
610
611	pCur = pVM->pgm.s.pRamRangesR3;
612	if (pCur)
613	{
614	pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
615	pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
616
617	for (; pCur->pNextR3; pCur = pCur->pNextR3)
618	{
619	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
620	pCur->pNextRC = pCur->pNextR3->pSelfRC;
621	}
622
623	Assert(pCur->pNextR0 == NIL_RTR0PTR);
624	Assert(pCur->pNextRC == NIL_RTRCPTR);
625	}
626	else
627	{
628	Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
629	Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
630	}
631	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
632	}
633
634
635	/**
636	* Links a new RAM range into the list.
637	*
638	* @param pVM Pointer to the shared VM structure.
639	* @param pNew Pointer to the new list entry.
640	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
641	*/
642	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
643	{
644	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
645	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
646	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
647
648	pgmLock(pVM);
649
650	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
651	pNew->pNextR3 = pRam;
652	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
653	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
654
655	if (pPrev)
656	{
657	pPrev->pNextR3 = pNew;
658	pPrev->pNextR0 = pNew->pSelfR0;
659	pPrev->pNextRC = pNew->pSelfRC;
660	}
661	else
662	{
663	pVM->pgm.s.pRamRangesR3 = pNew;
664	pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
665	pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
666	}
667	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
668	pgmUnlock(pVM);
669	}
670
671
672	/**
673	* Unlink an existing RAM range from the list.
674	*
675	* @param pVM Pointer to the shared VM structure.
676	* @param pRam Pointer to the new list entry.
677	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
678	*/
679	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
680	{
681	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
682	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
683	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
684
685	pgmLock(pVM);
686
687	PPGMRAMRANGE pNext = pRam->pNextR3;
688	if (pPrev)
689	{
690	pPrev->pNextR3 = pNext;
691	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
692	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
693	}
694	else
695	{
696	Assert(pVM->pgm.s.pRamRangesR3 == pRam);
697	pVM->pgm.s.pRamRangesR3 = pNext;
698	pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
699	pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
700	}
701	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
702	pgmUnlock(pVM);
703	}
704
705
706	/**
707	* Unlink an existing RAM range from the list.
708	*
709	* @param pVM Pointer to the shared VM structure.
710	* @param pRam Pointer to the new list entry.
711	*/
712	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
713	{
714	pgmLock(pVM);
715
716	/* find prev. */
717	PPGMRAMRANGE pPrev = NULL;
718	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
719	while (pCur != pRam)
720	{
721	pPrev = pCur;
722	pCur = pCur->pNextR3;
723	}
724	AssertFatal(pCur);
725
726	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
727	pgmUnlock(pVM);
728	}
729
730
731	/**
732	* Frees a range of pages, replacing them with ZERO pages of the specified type.
733	*
734	* @returns VBox status code.
735	* @param pVM The VM handle.
736	* @param pRam The RAM range in which the pages resides.
737	* @param GCPhys The address of the first page.
738	* @param GCPhysLast The address of the last page.
739	* @param uType The page type to replace then with.
740	*/
741	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
742	{
743	Assert(PGMIsLockOwner(pVM));
744	uint32_t cPendingPages = 0;
745	PGMMFREEPAGESREQ pReq;
746	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
747	AssertLogRelRCReturn(rc, rc);
748
749	/* Iterate the pages. */
750	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
751	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
752	while (cPagesLeft-- > 0)
753	{
754	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
755	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
756
757	PGM_PAGE_SET_TYPE(pPageDst, uType);
758
759	GCPhys += PAGE_SIZE;
760	pPageDst++;
761	}
762
763	if (cPendingPages)
764	{
765	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
766	AssertLogRelRCReturn(rc, rc);
767	}
768	GMMR3FreePagesCleanup(pReq);
769
770	return rc;
771	}
772
773	/**
774	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
775	*
776	* This is only called on one of the EMTs while the other ones are waiting for
777	* it to complete this function.
778	*
779	* @returns VINF_SUCCESS (VBox strict status code).
780	* @param pVM The VM handle.
781	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
782	* @param pvUser User parameter
783	*/
784	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
785	{
786	uintptr_t paUser = (uintptr_t )pvUser;
787	bool fInflate = !!paUser[0];
788	unsigned cPages = paUser[1];
789	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
790	uint32_t cPendingPages = 0;
791	PGMMFREEPAGESREQ pReq;
792	int rc;
793
794	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
795	pgmLock(pVM);
796
797	if (fInflate)
798	{
799	/* Replace pages with ZERO pages. */
800	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
801	if (RT_FAILURE(rc))
802	{
803	pgmUnlock(pVM);
804	AssertLogRelRC(rc);
805	return rc;
806	}
807
808	/* Iterate the pages. */
809	for (unsigned i = 0; i < cPages; i++)
810	{
811	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
812	if ( pPage == NULL
813	\|\| pPage->uTypeY != PGMPAGETYPE_RAM)
814	{
815	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], (pPage) ? pPage->uTypeY : 0));
816	break;
817	}
818
819	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
820
821	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i]);
822	if (RT_FAILURE(rc))
823	{
824	pgmUnlock(pVM);
825	AssertLogRelRC(rc);
826	return rc;
827	}
828	Assert(PGM_PAGE_IS_ZERO(pPage));
829	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_BALLOONED);
830
831	/* Flush the shadow PT if this page was previously used as a guest page table. */
832	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
833	}
834
835	if (cPendingPages)
836	{
837	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
838	if (RT_FAILURE(rc))
839	{
840	pgmUnlock(pVM);
841	AssertLogRelRC(rc);
842	return rc;
843	}
844	}
845	GMMR3FreePagesCleanup(pReq);
846
847	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
848	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
849	}
850	else
851	{
852	/* Iterate the pages. */
853	for (unsigned i = 0; i < cPages; i++)
854	{
855	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
856	AssertBreak(pPage && pPage->uTypeY == PGMPAGETYPE_RAM);
857
858	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
859
860	Assert(PGM_PAGE_IS_BALLOONED(pPage));
861
862	/* Change back to zero page. */
863	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
864	}
865
866	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
867	}
868
869	/* Notify GMM about the balloon change. */
870	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
871	if (RT_SUCCESS(rc))
872	{
873	if (!fInflate)
874	{
875	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
876	pVM->pgm.s.cBalloonedPages -= cPages;
877	}
878	else
879	pVM->pgm.s.cBalloonedPages += cPages;
880	}
881
882	pgmUnlock(pVM);
883
884	/* Flush the recompiler's TLB as well. */
885	for (unsigned i = 0; i < pVM->cCpus; i++)
886	CPUMSetChangedFlags(&pVM->aCpus[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
887
888	AssertLogRelRC(rc);
889	return rc;
890	}
891
892	/**
893	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
894	*
895	* @returns VBox status code.
896	* @param pVM The VM handle.
897	* @param fInflate Inflate or deflate memory balloon
898	* @param cPages Number of pages to free
899	* @param paPhysPage Array of guest physical addresses
900	*/
901	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
902	{
903	uintptr_t paUser[3];
904
905	paUser[0] = fInflate;
906	paUser[1] = cPages;
907	paUser[2] = (uintptr_t)paPhysPage;
908	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
909	AssertRC(rc);
910
911	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
912	RTMemFree(paPhysPage);
913	}
914
915	/**
916	* Inflate or deflate a memory balloon
917	*
918	* @returns VBox status code.
919	* @param pVM The VM handle.
920	* @param fInflate Inflate or deflate memory balloon
921	* @param cPages Number of pages to free
922	* @param paPhysPage Array of guest physical addresses
923	*/
924	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
925	{
926	int rc;
927
928	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
929	* In the SMP case we post a request packet to postpone the job.
930	*/
931	if (pVM->cCpus > 1)
932	{
933	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
934	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
935	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
936
937	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
938
939	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
940	AssertRC(rc);
941	}
942	else
943	{
944	uintptr_t paUser[3];
945
946	paUser[0] = fInflate;
947	paUser[1] = cPages;
948	paUser[2] = (uintptr_t)paPhysPage;
949	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
950	AssertRC(rc);
951	}
952	return rc;
953	}
954
955
956	/**
957	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
958	*
959	* @param pVM The VM handle.
960	* @param pNew The new RAM range.
961	* @param GCPhys The address of the RAM range.
962	* @param GCPhysLast The last address of the RAM range.
963	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
964	* if in HMA.
965	* @param R0PtrNew Ditto for R0.
966	* @param pszDesc The description.
967	* @param pPrev The previous RAM range (for linking).
968	*/
969	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
970	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
971	{
972	/*
973	* Initialize the range.
974	*/
975	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
976	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
977	pNew->GCPhys = GCPhys;
978	pNew->GCPhysLast = GCPhysLast;
979	pNew->cb = GCPhysLast - GCPhys + 1;
980	pNew->pszDesc = pszDesc;
981	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
982	pNew->pvR3 = NULL;
983	pNew->paLSPages = NULL;
984
985	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
986	RTGCPHYS iPage = cPages;
987	while (iPage-- > 0)
988	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
989
990	/* Update the page count stats. */
991	pVM->pgm.s.cZeroPages += cPages;
992	pVM->pgm.s.cAllPages += cPages;
993
994	/*
995	* Link it.
996	*/
997	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
998	}
999
1000
1001	/**
1002	* Relocate a floating RAM range.
1003	*
1004	* @copydoc FNPGMRELOCATE.
1005	*/
1006	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
1007	{
1008	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
1009	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
1010	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
1011
1012	switch (enmMode)
1013	{
1014	case PGMRELOCATECALL_SUGGEST:
1015	return true;
1016	case PGMRELOCATECALL_RELOCATE:
1017	{
1018	/* Update myself and then relink all the ranges. */
1019	pgmLock(pVM);
1020	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
1021	pgmR3PhysRelinkRamRanges(pVM);
1022	pgmUnlock(pVM);
1023	return true;
1024	}
1025
1026	default:
1027	AssertFailedReturn(false);
1028	}
1029	}
1030
1031
1032	/**
1033	* PGMR3PhysRegisterRam worker that registers a high chunk.
1034	*
1035	* @returns VBox status code.
1036	* @param pVM The VM handle.
1037	* @param GCPhys The address of the RAM.
1038	* @param cRamPages The number of RAM pages to register.
1039	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1040	* @param iChunk The chunk number.
1041	* @param pszDesc The RAM range description.
1042	* @param ppPrev Previous RAM range pointer. In/Out.
1043	*/
1044	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1045	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1046	PPGMRAMRANGE *ppPrev)
1047	{
1048	const char *pszDescChunk = iChunk == 0
1049	? pszDesc
1050	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1051	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1052
1053	/*
1054	* Allocate memory for the new chunk.
1055	*/
1056	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1057	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1058	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1059	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1060	void *pvChunk = NULL;
1061	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
1062	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1063	VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
1064	#else
1065	NULL,
1066	#endif
1067	paChunkPages);
1068	if (RT_SUCCESS(rc))
1069	{
1070	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1071	if (!VMMIsHwVirtExtForced(pVM))
1072	R0PtrChunk = NIL_RTR0PTR;
1073	#else
1074	R0PtrChunk = (uintptr_t)pvChunk;
1075	#endif
1076	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1077
1078	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1079
1080	/*
1081	* Create a mapping and map the pages into it.
1082	* We push these in below the HMA.
1083	*/
1084	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1085	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1086	if (RT_SUCCESS(rc))
1087	{
1088	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1089
1090	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1091	RTGCPTR GCPtrPage = GCPtrChunk;
1092	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1093	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1094	if (RT_SUCCESS(rc))
1095	{
1096	/*
1097	* Ok, init and link the range.
1098	*/
1099	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1100	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1101	*ppPrev = pNew;
1102	}
1103	}
1104
1105	if (RT_FAILURE(rc))
1106	SUPR3PageFreeEx(pvChunk, cChunkPages);
1107	}
1108
1109	RTMemTmpFree(paChunkPages);
1110	return rc;
1111	}
1112
1113
1114	/**
1115	* Sets up a range RAM.
1116	*
1117	* This will check for conflicting registrations, make a resource
1118	* reservation for the memory (with GMM), and setup the per-page
1119	* tracking structures (PGMPAGE).
1120	*
1121	* @returns VBox stutus code.
1122	* @param pVM Pointer to the shared VM structure.
1123	* @param GCPhys The physical address of the RAM.
1124	* @param cb The size of the RAM.
1125	* @param pszDesc The description - not copied, so, don't free or change it.
1126	*/
1127	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1128	{
1129	/*
1130	* Validate input.
1131	*/
1132	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1133	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1134	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1135	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1136	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1137	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1138	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1139	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1140
1141	pgmLock(pVM);
1142
1143	/*
1144	* Find range location and check for conflicts.
1145	* (We don't lock here because the locking by EMT is only required on update.)
1146	*/
1147	PPGMRAMRANGE pPrev = NULL;
1148	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1149	while (pRam && GCPhysLast >= pRam->GCPhys)
1150	{
1151	if ( GCPhysLast >= pRam->GCPhys
1152	&& GCPhys <= pRam->GCPhysLast)
1153	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1154	GCPhys, GCPhysLast, pszDesc,
1155	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1156	VERR_PGM_RAM_CONFLICT);
1157
1158	/* next */
1159	pPrev = pRam;
1160	pRam = pRam->pNextR3;
1161	}
1162
1163	/*
1164	* Register it with GMM (the API bitches).
1165	*/
1166	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1167	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1168	if (RT_FAILURE(rc))
1169	{
1170	pgmUnlock(pVM);
1171	return rc;
1172	}
1173
1174	if ( GCPhys >= _4G
1175	&& cPages > 256)
1176	{
1177	/*
1178	* The PGMRAMRANGE structures for the high memory can get very big.
1179	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1180	* allocation size limit there and also to avoid being unable to find
1181	* guest mapping space for them, we split this memory up into 4MB in
1182	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1183	* mode.
1184	*
1185	* The first and last page of each mapping are guard pages and marked
1186	* not-present. So, we've got 4186112 and 16769024 bytes available for
1187	* the PGMRAMRANGE structure.
1188	*
1189	* Note! The sizes used here will influence the saved state.
1190	*/
1191	uint32_t cbChunk;
1192	uint32_t cPagesPerChunk;
1193	if (VMMIsHwVirtExtForced(pVM))
1194	{
1195	cbChunk = 16U*_1M;
1196	cPagesPerChunk = 1048048; /* max ~1048059 */
1197	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1198	}
1199	else
1200	{
1201	cbChunk = 4U*_1M;
1202	cPagesPerChunk = 261616; /* max ~261627 */
1203	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1204	}
1205	AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1206
1207	RTGCPHYS cPagesLeft = cPages;
1208	RTGCPHYS GCPhysChunk = GCPhys;
1209	uint32_t iChunk = 0;
1210	while (cPagesLeft > 0)
1211	{
1212	uint32_t cPagesInChunk = cPagesLeft;
1213	if (cPagesInChunk > cPagesPerChunk)
1214	cPagesInChunk = cPagesPerChunk;
1215
1216	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1217	AssertRCReturn(rc, rc);
1218
1219	/* advance */
1220	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1221	cPagesLeft -= cPagesInChunk;
1222	iChunk++;
1223	}
1224	}
1225	else
1226	{
1227	/*
1228	* Allocate, initialize and link the new RAM range.
1229	*/
1230	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1231	PPGMRAMRANGE pNew;
1232	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1233	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1234
1235	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1236	}
1237	PGMPhysInvalidatePageMapTLB(pVM);
1238	pgmUnlock(pVM);
1239
1240	/*
1241	* Notify REM.
1242	*/
1243	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1244
1245	return VINF_SUCCESS;
1246	}
1247
1248
1249	/**
1250	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1251	*
1252	* We do this late in the init process so that all the ROM and MMIO ranges have
1253	* been registered already and we don't go wasting memory on them.
1254	*
1255	* @returns VBox status code.
1256	*
1257	* @param pVM Pointer to the shared VM structure.
1258	*/
1259	int pgmR3PhysRamPreAllocate(PVM pVM)
1260	{
1261	Assert(pVM->pgm.s.fRamPreAlloc);
1262	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1263
1264	/*
1265	* Walk the RAM ranges and allocate all RAM pages, halt at
1266	* the first allocation error.
1267	*/
1268	uint64_t cPages = 0;
1269	uint64_t NanoTS = RTTimeNanoTS();
1270	pgmLock(pVM);
1271	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1272	{
1273	PPGMPAGE pPage = &pRam->aPages[0];
1274	RTGCPHYS GCPhys = pRam->GCPhys;
1275	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1276	while (cLeft-- > 0)
1277	{
1278	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1279	{
1280	switch (PGM_PAGE_GET_STATE(pPage))
1281	{
1282	case PGM_PAGE_STATE_ZERO:
1283	{
1284	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1285	if (RT_FAILURE(rc))
1286	{
1287	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1288	pgmUnlock(pVM);
1289	return rc;
1290	}
1291	cPages++;
1292	break;
1293	}
1294
1295	case PGM_PAGE_STATE_BALLOONED:
1296	case PGM_PAGE_STATE_ALLOCATED:
1297	case PGM_PAGE_STATE_WRITE_MONITORED:
1298	case PGM_PAGE_STATE_SHARED:
1299	/* nothing to do here. */
1300	break;
1301	}
1302	}
1303
1304	/* next */
1305	pPage++;
1306	GCPhys += PAGE_SIZE;
1307	}
1308	}
1309	pgmUnlock(pVM);
1310	NanoTS = RTTimeNanoTS() - NanoTS;
1311
1312	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1313	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1314	return VINF_SUCCESS;
1315	}
1316
1317
1318	/**
1319	* Resets (zeros) the RAM.
1320	*
1321	* ASSUMES that the caller owns the PGM lock.
1322	*
1323	* @returns VBox status code.
1324	* @param pVM Pointer to the shared VM structure.
1325	*/
1326	int pgmR3PhysRamReset(PVM pVM)
1327	{
1328	Assert(PGMIsLockOwner(pVM));
1329
1330	/* Reset the memory balloon. */
1331	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1332	AssertRC(rc);
1333
1334	/*
1335	* We batch up pages that should be freed instead of calling GMM for
1336	* each and every one of them.
1337	*/
1338	uint32_t cPendingPages = 0;
1339	PGMMFREEPAGESREQ pReq;
1340	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1341	AssertLogRelRCReturn(rc, rc);
1342
1343	/*
1344	* Walk the ram ranges.
1345	*/
1346	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1347	{
1348	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1349	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1350
1351	if (!pVM->pgm.s.fRamPreAlloc)
1352	{
1353	/* Replace all RAM pages by ZERO pages. */
1354	while (iPage-- > 0)
1355	{
1356	PPGMPAGE pPage = &pRam->aPages[iPage];
1357	switch (PGM_PAGE_GET_TYPE(pPage))
1358	{
1359	case PGMPAGETYPE_RAM:
1360	/* Do not replace pages part of a 2 MB continuous range with zero pages, but zero them instead. */
1361	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
1362	{
1363	void *pvPage;
1364	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1365	AssertLogRelRCReturn(rc, rc);
1366	ASMMemZeroPage(pvPage);
1367	}
1368	else
1369	if ( !PGM_PAGE_IS_ZERO(pPage)
1370	&& !PGM_PAGE_IS_BALLOONED(pPage))
1371	{
1372	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1373	AssertLogRelRCReturn(rc, rc);
1374	}
1375	break;
1376
1377	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1378	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1379	break;
1380
1381	case PGMPAGETYPE_MMIO2:
1382	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1383	case PGMPAGETYPE_ROM:
1384	case PGMPAGETYPE_MMIO:
1385	break;
1386	default:
1387	AssertFailed();
1388	}
1389	} /* for each page */
1390	}
1391	else
1392	{
1393	/* Zero the memory. */
1394	while (iPage-- > 0)
1395	{
1396	PPGMPAGE pPage = &pRam->aPages[iPage];
1397	switch (PGM_PAGE_GET_TYPE(pPage))
1398	{
1399	case PGMPAGETYPE_RAM:
1400	switch (PGM_PAGE_GET_STATE(pPage))
1401	{
1402	case PGM_PAGE_STATE_ZERO:
1403	break;
1404
1405	case PGM_PAGE_STATE_BALLOONED:
1406	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1407	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
1408	break;
1409
1410	case PGM_PAGE_STATE_SHARED:
1411	case PGM_PAGE_STATE_WRITE_MONITORED:
1412	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1413	AssertLogRelRCReturn(rc, rc);
1414	/* no break */
1415
1416	case PGM_PAGE_STATE_ALLOCATED:
1417	{
1418	void *pvPage;
1419	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1420	AssertLogRelRCReturn(rc, rc);
1421	ASMMemZeroPage(pvPage);
1422	break;
1423	}
1424	}
1425	break;
1426
1427	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1428	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1429	break;
1430
1431	case PGMPAGETYPE_MMIO2:
1432	case PGMPAGETYPE_ROM_SHADOW:
1433	case PGMPAGETYPE_ROM:
1434	case PGMPAGETYPE_MMIO:
1435	break;
1436	default:
1437	AssertFailed();
1438
1439	}
1440	} /* for each page */
1441	}
1442
1443	}
1444
1445	/*
1446	* Finish off any pages pending freeing.
1447	*/
1448	if (cPendingPages)
1449	{
1450	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1451	AssertLogRelRCReturn(rc, rc);
1452	}
1453	GMMR3FreePagesCleanup(pReq);
1454
1455	return VINF_SUCCESS;
1456	}
1457
1458
1459	/**
1460	* This is the interface IOM is using to register an MMIO region.
1461	*
1462	* It will check for conflicts and ensure that a RAM range structure
1463	* is present before calling the PGMR3HandlerPhysicalRegister API to
1464	* register the callbacks.
1465	*
1466	* @returns VBox status code.
1467	*
1468	* @param pVM Pointer to the shared VM structure.
1469	* @param GCPhys The start of the MMIO region.
1470	* @param cb The size of the MMIO region.
1471	* @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1472	* @param pvUserR3 The user argument for R3.
1473	* @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1474	* @param pvUserR0 The user argument for R0.
1475	* @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1476	* @param pvUserRC The user argument for RC.
1477	* @param pszDesc The description of the MMIO region.
1478	*/
1479	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1480	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1481	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1482	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1483	R3PTRTYPE(const char *) pszDesc)
1484	{
1485	/*
1486	* Assert on some assumption.
1487	*/
1488	VM_ASSERT_EMT(pVM);
1489	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1490	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1491	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1492	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1493
1494	/*
1495	* Make sure there's a RAM range structure for the region.
1496	*/
1497	int rc;
1498	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1499	bool fRamExists = false;
1500	PPGMRAMRANGE pRamPrev = NULL;
1501	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1502	while (pRam && GCPhysLast >= pRam->GCPhys)
1503	{
1504	if ( GCPhysLast >= pRam->GCPhys
1505	&& GCPhys <= pRam->GCPhysLast)
1506	{
1507	/* Simplification: all within the same range. */
1508	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1509	&& GCPhysLast <= pRam->GCPhysLast,
1510	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1511	GCPhys, GCPhysLast, pszDesc,
1512	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1513	VERR_PGM_RAM_CONFLICT);
1514
1515	/* Check that it's all RAM or MMIO pages. */
1516	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1517	uint32_t cLeft = cb >> PAGE_SHIFT;
1518	while (cLeft-- > 0)
1519	{
1520	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1521	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1522	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1523	GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1524	VERR_PGM_RAM_CONFLICT);
1525	pPage++;
1526	}
1527
1528	/* Looks good. */
1529	fRamExists = true;
1530	break;
1531	}
1532
1533	/* next */
1534	pRamPrev = pRam;
1535	pRam = pRam->pNextR3;
1536	}
1537	PPGMRAMRANGE pNew;
1538	if (fRamExists)
1539	{
1540	pNew = NULL;
1541
1542	/*
1543	* Make all the pages in the range MMIO/ZERO pages, freeing any
1544	* RAM pages currently mapped here. This might not be 100% correct
1545	* for PCI memory, but we're doing the same thing for MMIO2 pages.
1546	*/
1547	rc = pgmLock(pVM);
1548	if (RT_SUCCESS(rc))
1549	{
1550	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1551	pgmUnlock(pVM);
1552	}
1553	AssertRCReturn(rc, rc);
1554	}
1555	else
1556	{
1557	pgmLock(pVM);
1558
1559	/*
1560	* No RAM range, insert an ad hoc one.
1561	*
1562	* Note that we don't have to tell REM about this range because
1563	* PGMHandlerPhysicalRegisterEx will do that for us.
1564	*/
1565	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1566
1567	const uint32_t cPages = cb >> PAGE_SHIFT;
1568	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1569	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1570	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1571
1572	/* Initialize the range. */
1573	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1574	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1575	pNew->GCPhys = GCPhys;
1576	pNew->GCPhysLast = GCPhysLast;
1577	pNew->cb = cb;
1578	pNew->pszDesc = pszDesc;
1579	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
1580	pNew->pvR3 = NULL;
1581	pNew->paLSPages = NULL;
1582
1583	uint32_t iPage = cPages;
1584	while (iPage-- > 0)
1585	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1586	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1587
1588	/* update the page count stats. */
1589	pVM->pgm.s.cPureMmioPages += cPages;
1590	pVM->pgm.s.cAllPages += cPages;
1591
1592	/* link it */
1593	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1594
1595	pgmUnlock(pVM);
1596	}
1597
1598	/*
1599	* Register the access handler.
1600	*/
1601	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1602	pfnHandlerR3, pvUserR3,
1603	pfnHandlerR0, pvUserR0,
1604	pfnHandlerRC, pvUserRC, pszDesc);
1605	if ( RT_FAILURE(rc)
1606	&& !fRamExists)
1607	{
1608	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
1609	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1610
1611	/* remove the ad hoc range. */
1612	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1613	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1614	MMHyperFree(pVM, pRam);
1615	}
1616	PGMPhysInvalidatePageMapTLB(pVM);
1617
1618	return rc;
1619	}
1620
1621
1622	/**
1623	* This is the interface IOM is using to register an MMIO region.
1624	*
1625	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
1626	* any ad hoc PGMRAMRANGE left behind.
1627	*
1628	* @returns VBox status code.
1629	* @param pVM Pointer to the shared VM structure.
1630	* @param GCPhys The start of the MMIO region.
1631	* @param cb The size of the MMIO region.
1632	*/
1633	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1634	{
1635	VM_ASSERT_EMT(pVM);
1636
1637	/*
1638	* First deregister the handler, then check if we should remove the ram range.
1639	*/
1640	int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1641	if (RT_SUCCESS(rc))
1642	{
1643	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1644	PPGMRAMRANGE pRamPrev = NULL;
1645	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1646	while (pRam && GCPhysLast >= pRam->GCPhys)
1647	{
1648	/** @todo We're being a bit too careful here. rewrite. */
1649	if ( GCPhysLast == pRam->GCPhysLast
1650	&& GCPhys == pRam->GCPhys)
1651	{
1652	Assert(pRam->cb == cb);
1653
1654	/*
1655	* See if all the pages are dead MMIO pages.
1656	*/
1657	uint32_t const cPages = cb >> PAGE_SHIFT;
1658	bool fAllMMIO = true;
1659	uint32_t iPage = 0;
1660	uint32_t cLeft = cPages;
1661	while (cLeft-- > 0)
1662	{
1663	PPGMPAGE pPage = &pRam->aPages[iPage];
1664	if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1665	/\|\| not-out-of-action later /)
1666	{
1667	fAllMMIO = false;
1668	Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1669	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1670	break;
1671	}
1672	Assert(PGM_PAGE_IS_ZERO(pPage));
1673	pPage++;
1674	}
1675	if (fAllMMIO)
1676	{
1677	/*
1678	* Ad-hoc range, unlink and free it.
1679	*/
1680	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
1681	GCPhys, GCPhysLast, pRam->pszDesc));
1682
1683	pVM->pgm.s.cAllPages -= cPages;
1684	pVM->pgm.s.cPureMmioPages -= cPages;
1685
1686	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1687	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1688	MMHyperFree(pVM, pRam);
1689	break;
1690	}
1691	}
1692
1693	/*
1694	* Range match? It will all be within one range (see PGMAllHandler.cpp).
1695	*/
1696	if ( GCPhysLast >= pRam->GCPhys
1697	&& GCPhys <= pRam->GCPhysLast)
1698	{
1699	Assert(GCPhys >= pRam->GCPhys);
1700	Assert(GCPhysLast <= pRam->GCPhysLast);
1701
1702	/*
1703	* Turn the pages back into RAM pages.
1704	*/
1705	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1706	uint32_t cLeft = cb >> PAGE_SHIFT;
1707	while (cLeft--)
1708	{
1709	PPGMPAGE pPage = &pRam->aPages[iPage];
1710	AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1711	AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1712	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1713	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1714	}
1715	break;
1716	}
1717
1718	/* next */
1719	pRamPrev = pRam;
1720	pRam = pRam->pNextR3;
1721	}
1722	}
1723
1724	PGMPhysInvalidatePageMapTLB(pVM);
1725	return rc;
1726	}
1727
1728
1729	/**
1730	* Locate a MMIO2 range.
1731	*
1732	* @returns Pointer to the MMIO2 range.
1733	* @param pVM Pointer to the shared VM structure.
1734	* @param pDevIns The device instance owning the region.
1735	* @param iRegion The region.
1736	*/
1737	DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1738	{
1739	/*
1740	* Search the list.
1741	*/
1742	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1743	if ( pCur->pDevInsR3 == pDevIns
1744	&& pCur->iRegion == iRegion)
1745	return pCur;
1746	return NULL;
1747	}
1748
1749
1750	/**
1751	* Allocate and register an MMIO2 region.
1752	*
1753	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1754	* RAM associated with a device. It is also non-shared memory with a
1755	* permanent ring-3 mapping and page backing (presently).
1756	*
1757	* A MMIO2 range may overlap with base memory if a lot of RAM
1758	* is configured for the VM, in which case we'll drop the base
1759	* memory pages. Presently we will make no attempt to preserve
1760	* anything that happens to be present in the base memory that
1761	* is replaced, this is of course incorrectly but it's too much
1762	* effort.
1763	*
1764	* @returns VBox status code.
1765	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1766	* @retval VERR_ALREADY_EXISTS if the region already exists.
1767	*
1768	* @param pVM Pointer to the shared VM structure.
1769	* @param pDevIns The device instance owning the region.
1770	* @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1771	* this number has to be the number of that region. Otherwise
1772	* it can be any number safe UINT8_MAX.
1773	* @param cb The size of the region. Must be page aligned.
1774	* @param fFlags Reserved for future use, must be zero.
1775	* @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1776	* @param pszDesc The description.
1777	*/
1778	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc)
1779	{
1780	/*
1781	* Validate input.
1782	*/
1783	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1784	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1785	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1786	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1787	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1788	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1789	AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1790	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1791	AssertReturn(cb, VERR_INVALID_PARAMETER);
1792	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1793
1794	const uint32_t cPages = cb >> PAGE_SHIFT;
1795	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1796	AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1797
1798	/*
1799	* For the 2nd+ instance, mangle the description string so it's unique.
1800	*/
1801	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
1802	{
1803	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1804	if (!pszDesc)
1805	return VERR_NO_MEMORY;
1806	}
1807
1808	/*
1809	* Try reserve and allocate the backing memory first as this is what is
1810	* most likely to fail.
1811	*/
1812	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1813	if (RT_SUCCESS(rc))
1814	{
1815	void *pvPages;
1816	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1817	if (RT_SUCCESS(rc))
1818	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
1819	if (RT_SUCCESS(rc))
1820	{
1821	memset(pvPages, 0, cPages * PAGE_SIZE);
1822
1823	/*
1824	* Create the MMIO2 range record for it.
1825	*/
1826	const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1827	PPGMMMIO2RANGE pNew;
1828	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1829	AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1830	if (RT_SUCCESS(rc))
1831	{
1832	pNew->pDevInsR3 = pDevIns;
1833	pNew->pvR3 = pvPages;
1834	//pNew->pNext = NULL;
1835	//pNew->fMapped = false;
1836	//pNew->fOverlapping = false;
1837	pNew->iRegion = iRegion;
1838	pNew->idSavedState = UINT8_MAX;
1839	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1840	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1841	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1842	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1843	pNew->RamRange.pszDesc = pszDesc;
1844	pNew->RamRange.cb = cb;
1845	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
1846	pNew->RamRange.pvR3 = pvPages;
1847	//pNew->RamRange.paLSPages = NULL;
1848
1849	uint32_t iPage = cPages;
1850	while (iPage-- > 0)
1851	{
1852	PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1853	paPages[iPage].Phys, NIL_GMM_PAGEID,
1854	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1855	}
1856
1857	/* update page count stats */
1858	pVM->pgm.s.cAllPages += cPages;
1859	pVM->pgm.s.cPrivatePages += cPages;
1860
1861	/*
1862	* Link it into the list.
1863	* Since there is no particular order, just push it.
1864	*/
1865	pgmLock(pVM);
1866	pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1867	pVM->pgm.s.pMmio2RangesR3 = pNew;
1868	pgmUnlock(pVM);
1869
1870	*ppv = pvPages;
1871	RTMemTmpFree(paPages);
1872	PGMPhysInvalidatePageMapTLB(pVM);
1873	return VINF_SUCCESS;
1874	}
1875
1876	SUPR3PageFreeEx(pvPages, cPages);
1877	}
1878	RTMemTmpFree(paPages);
1879	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1880	}
1881	if (pDevIns->iInstance > 0)
1882	MMR3HeapFree((void *)pszDesc);
1883	return rc;
1884	}
1885
1886
1887	/**
1888	* Deregisters and frees an MMIO2 region.
1889	*
1890	* Any physical (and virtual) access handlers registered for the region must
1891	* be deregistered before calling this function.
1892	*
1893	* @returns VBox status code.
1894	* @param pVM Pointer to the shared VM structure.
1895	* @param pDevIns The device instance owning the region.
1896	* @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1897	*/
1898	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1899	{
1900	/*
1901	* Validate input.
1902	*/
1903	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1904	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1905	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1906
1907	pgmLock(pVM);
1908	int rc = VINF_SUCCESS;
1909	unsigned cFound = 0;
1910	PPGMMMIO2RANGE pPrev = NULL;
1911	PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1912	while (pCur)
1913	{
1914	if ( pCur->pDevInsR3 == pDevIns
1915	&& ( iRegion == UINT32_MAX
1916	\|\| pCur->iRegion == iRegion))
1917	{
1918	cFound++;
1919
1920	/*
1921	* Unmap it if it's mapped.
1922	*/
1923	if (pCur->fMapped)
1924	{
1925	int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1926	AssertRC(rc2);
1927	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1928	rc = rc2;
1929	}
1930
1931	/*
1932	* Unlink it
1933	*/
1934	PPGMMMIO2RANGE pNext = pCur->pNextR3;
1935	if (pPrev)
1936	pPrev->pNextR3 = pNext;
1937	else
1938	pVM->pgm.s.pMmio2RangesR3 = pNext;
1939	pCur->pNextR3 = NULL;
1940
1941	/*
1942	* Free the memory.
1943	*/
1944	int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1945	AssertRC(rc2);
1946	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1947	rc = rc2;
1948
1949	uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1950	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1951	AssertRC(rc2);
1952	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1953	rc = rc2;
1954
1955	/* we're leaking hyper memory here if done at runtime. */
1956	#ifdef VBOX_STRICT
1957	VMSTATE const enmState = VMR3GetState(pVM);
1958	AssertMsg( enmState == VMSTATE_POWERING_OFF
1959	\|\| enmState == VMSTATE_POWERING_OFF_LS
1960	\|\| enmState == VMSTATE_OFF
1961	\|\| enmState == VMSTATE_OFF_LS
1962	\|\| enmState == VMSTATE_DESTROYING
1963	\|\| enmState == VMSTATE_TERMINATED
1964	\|\| enmState == VMSTATE_CREATING
1965	, ("%s\n", VMR3GetStateName(enmState)));
1966	#endif
1967	/*rc = MMHyperFree(pVM, pCur);
1968	AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1969
1970
1971	/* update page count stats */
1972	pVM->pgm.s.cAllPages -= cPages;
1973	pVM->pgm.s.cPrivatePages -= cPages;
1974
1975	/* next */
1976	pCur = pNext;
1977	}
1978	else
1979	{
1980	pPrev = pCur;
1981	pCur = pCur->pNextR3;
1982	}
1983	}
1984	PGMPhysInvalidatePageMapTLB(pVM);
1985	pgmUnlock(pVM);
1986	return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1987	}
1988
1989
1990	/**
1991	* Maps a MMIO2 region.
1992	*
1993	* This is done when a guest / the bios / state loading changes the
1994	* PCI config. The replacing of base memory has the same restrictions
1995	* as during registration, of course.
1996	*
1997	* @returns VBox status code.
1998	*
1999	* @param pVM Pointer to the shared VM structure.
2000	* @param pDevIns The
2001	*/
2002	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2003	{
2004	/*
2005	* Validate input
2006	*/
2007	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2008	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2009	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2010	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2011	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2012	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2013
2014	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2015	AssertReturn(pCur, VERR_NOT_FOUND);
2016	AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
2017	Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
2018	Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
2019
2020	const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
2021	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2022
2023	/*
2024	* Find our location in the ram range list, checking for
2025	* restriction we don't bother implementing yet (partially overlapping).
2026	*/
2027	bool fRamExists = false;
2028	PPGMRAMRANGE pRamPrev = NULL;
2029	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2030	while (pRam && GCPhysLast >= pRam->GCPhys)
2031	{
2032	if ( GCPhys <= pRam->GCPhysLast
2033	&& GCPhysLast >= pRam->GCPhys)
2034	{
2035	/* completely within? */
2036	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2037	&& GCPhysLast <= pRam->GCPhysLast,
2038	("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
2039	GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
2040	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2041	VERR_PGM_RAM_CONFLICT);
2042	fRamExists = true;
2043	break;
2044	}
2045
2046	/* next */
2047	pRamPrev = pRam;
2048	pRam = pRam->pNextR3;
2049	}
2050	if (fRamExists)
2051	{
2052	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2053	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2054	while (cPagesLeft-- > 0)
2055	{
2056	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2057	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
2058	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
2059	VERR_PGM_RAM_CONFLICT);
2060	pPage++;
2061	}
2062	}
2063	Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
2064	GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
2065
2066	/*
2067	* Make the changes.
2068	*/
2069	pgmLock(pVM);
2070
2071	pCur->RamRange.GCPhys = GCPhys;
2072	pCur->RamRange.GCPhysLast = GCPhysLast;
2073	pCur->fMapped = true;
2074	pCur->fOverlapping = fRamExists;
2075
2076	if (fRamExists)
2077	{
2078	/** @todo use pgmR3PhysFreePageRange here. */
2079	uint32_t cPendingPages = 0;
2080	PGMMFREEPAGESREQ pReq;
2081	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2082	AssertLogRelRCReturn(rc, rc);
2083
2084	/* replace the pages, freeing all present RAM pages. */
2085	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2086	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2087	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2088	while (cPagesLeft-- > 0)
2089	{
2090	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
2091	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
2092
2093	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
2094	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
2095	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
2096	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
2097
2098	pVM->pgm.s.cZeroPages--;
2099	GCPhys += PAGE_SIZE;
2100	pPageSrc++;
2101	pPageDst++;
2102	}
2103
2104	/* Flush physical page map TLB. */
2105	PGMPhysInvalidatePageMapTLB(pVM);
2106
2107	if (cPendingPages)
2108	{
2109	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2110	AssertLogRelRCReturn(rc, rc);
2111	}
2112	GMMR3FreePagesCleanup(pReq);
2113	pgmUnlock(pVM);
2114	}
2115	else
2116	{
2117	RTGCPHYS cb = pCur->RamRange.cb;
2118
2119	/* link in the ram range */
2120	pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
2121	pgmUnlock(pVM);
2122
2123	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
2124	}
2125
2126	PGMPhysInvalidatePageMapTLB(pVM);
2127	return VINF_SUCCESS;
2128	}
2129
2130
2131	/**
2132	* Unmaps a MMIO2 region.
2133	*
2134	* This is done when a guest / the bios / state loading changes the
2135	* PCI config. The replacing of base memory has the same restrictions
2136	* as during registration, of course.
2137	*/
2138	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2139	{
2140	/*
2141	* Validate input
2142	*/
2143	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2144	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2145	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2146	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2147	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2148	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2149
2150	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2151	AssertReturn(pCur, VERR_NOT_FOUND);
2152	AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
2153	AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
2154	Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
2155
2156	Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
2157	pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
2158
2159	/*
2160	* Unmap it.
2161	*/
2162	pgmLock(pVM);
2163
2164	RTGCPHYS GCPhysRangeREM;
2165	RTGCPHYS cbRangeREM;
2166	bool fInformREM;
2167	if (pCur->fOverlapping)
2168	{
2169	/* Restore the RAM pages we've replaced. */
2170	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2171	while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
2172	pRam = pRam->pNextR3;
2173
2174	RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
2175	Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
2176	PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2177	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2178	while (cPagesLeft-- > 0)
2179	{
2180	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
2181	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
2182	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
2183	PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
2184	PGM_PAGE_SET_PDE_TYPE(pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
2185
2186	pVM->pgm.s.cZeroPages++;
2187	pPageDst++;
2188	}
2189
2190	/* Flush physical page map TLB. */
2191	PGMPhysInvalidatePageMapTLB(pVM);
2192
2193	GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
2194	cbRangeREM = RTGCPHYS_MAX; /* ditto */
2195	fInformREM = false;
2196	}
2197	else
2198	{
2199	GCPhysRangeREM = pCur->RamRange.GCPhys;
2200	cbRangeREM = pCur->RamRange.cb;
2201	fInformREM = true;
2202
2203	pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
2204	}
2205
2206	pCur->RamRange.GCPhys = NIL_RTGCPHYS;
2207	pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
2208	pCur->fOverlapping = false;
2209	pCur->fMapped = false;
2210
2211	PGMPhysInvalidatePageMapTLB(pVM);
2212	pgmUnlock(pVM);
2213
2214	if (fInformREM)
2215	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2216
2217	return VINF_SUCCESS;
2218	}
2219
2220
2221	/**
2222	* Checks if the given address is an MMIO2 base address or not.
2223	*
2224	* @returns true/false accordingly.
2225	* @param pVM Pointer to the shared VM structure.
2226	* @param pDevIns The owner of the memory, optional.
2227	* @param GCPhys The address to check.
2228	*/
2229	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2230	{
2231	/*
2232	* Validate input
2233	*/
2234	VM_ASSERT_EMT_RETURN(pVM, false);
2235	AssertPtrReturn(pDevIns, false);
2236	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
2237	AssertReturn(GCPhys != 0, false);
2238	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
2239
2240	/*
2241	* Search the list.
2242	*/
2243	pgmLock(pVM);
2244	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2245	if (pCur->RamRange.GCPhys == GCPhys)
2246	{
2247	Assert(pCur->fMapped);
2248	pgmUnlock(pVM);
2249	return true;
2250	}
2251	pgmUnlock(pVM);
2252	return false;
2253	}
2254
2255
2256	/**
2257	* Gets the HC physical address of a page in the MMIO2 region.
2258	*
2259	* This is API is intended for MMHyper and shouldn't be called
2260	* by anyone else...
2261	*
2262	* @returns VBox status code.
2263	* @param pVM Pointer to the shared VM structure.
2264	* @param pDevIns The owner of the memory, optional.
2265	* @param iRegion The region.
2266	* @param off The page expressed an offset into the MMIO2 region.
2267	* @param pHCPhys Where to store the result.
2268	*/
2269	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2270	{
2271	/*
2272	* Validate input
2273	*/
2274	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2275	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2276	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2277
2278	pgmLock(pVM);
2279	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2280	AssertReturn(pCur, VERR_NOT_FOUND);
2281	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2282
2283	PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2284	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2285	pgmUnlock(pVM);
2286	return VINF_SUCCESS;
2287	}
2288
2289
2290	/**
2291	* Maps a portion of an MMIO2 region into kernel space (host).
2292	*
2293	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
2294	* or the VM is terminated.
2295	*
2296	* @return VBox status code.
2297	*
2298	* @param pVM Pointer to the shared VM structure.
2299	* @param pDevIns The device owning the MMIO2 memory.
2300	* @param iRegion The region.
2301	* @param off The offset into the region. Must be page aligned.
2302	* @param cb The number of bytes to map. Must be page aligned.
2303	* @param pszDesc Mapping description.
2304	* @param pR0Ptr Where to store the R0 address.
2305	*/
2306	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2307	const char *pszDesc, PRTR0PTR pR0Ptr)
2308	{
2309	/*
2310	* Validate input.
2311	*/
2312	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2313	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2314	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2315
2316	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2317	AssertReturn(pCur, VERR_NOT_FOUND);
2318	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2319	AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2320	AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2321
2322	/*
2323	* Pass the request on to the support library/driver.
2324	*/
2325	int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2326
2327	return rc;
2328	}
2329
2330
2331	/**
2332	* Registers a ROM image.
2333	*
2334	* Shadowed ROM images requires double the amount of backing memory, so,
2335	* don't use that unless you have to. Shadowing of ROM images is process
2336	* where we can select where the reads go and where the writes go. On real
2337	* hardware the chipset provides means to configure this. We provide
2338	* PGMR3PhysProtectROM() for this purpose.
2339	*
2340	* A read-only copy of the ROM image will always be kept around while we
2341	* will allocate RAM pages for the changes on demand (unless all memory
2342	* is configured to be preallocated).
2343	*
2344	* @returns VBox status.
2345	* @param pVM VM Handle.
2346	* @param pDevIns The device instance owning the ROM.
2347	* @param GCPhys First physical address in the range.
2348	* Must be page aligned!
2349	* @param cbRange The size of the range (in bytes).
2350	* Must be page aligned!
2351	* @param pvBinary Pointer to the binary data backing the ROM image.
2352	* This must be exactly \a cbRange in size.
2353	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2354	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2355	* @param pszDesc Pointer to description string. This must not be freed.
2356	*
2357	* @remark There is no way to remove the rom, automatically on device cleanup or
2358	* manually from the device yet. This isn't difficult in any way, it's
2359	* just not something we expect to be necessary for a while.
2360	*/
2361	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2362	const void pvBinary, uint32_t fFlags, const char pszDesc)
2363	{
2364	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2365	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2366
2367	/*
2368	* Validate input.
2369	*/
2370	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2371	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2372	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2373	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2374	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2375	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2376	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2377	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2378	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2379
2380	const uint32_t cPages = cb >> PAGE_SHIFT;
2381
2382	/*
2383	* Find the ROM location in the ROM list first.
2384	*/
2385	PPGMROMRANGE pRomPrev = NULL;
2386	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2387	while (pRom && GCPhysLast >= pRom->GCPhys)
2388	{
2389	if ( GCPhys <= pRom->GCPhysLast
2390	&& GCPhysLast >= pRom->GCPhys)
2391	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2392	GCPhys, GCPhysLast, pszDesc,
2393	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2394	VERR_PGM_RAM_CONFLICT);
2395	/* next */
2396	pRomPrev = pRom;
2397	pRom = pRom->pNextR3;
2398	}
2399
2400	/*
2401	* Find the RAM location and check for conflicts.
2402	*
2403	* Conflict detection is a bit different than for RAM
2404	* registration since a ROM can be located within a RAM
2405	* range. So, what we have to check for is other memory
2406	* types (other than RAM that is) and that we don't span
2407	* more than one RAM range (layz).
2408	*/
2409	bool fRamExists = false;
2410	PPGMRAMRANGE pRamPrev = NULL;
2411	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2412	while (pRam && GCPhysLast >= pRam->GCPhys)
2413	{
2414	if ( GCPhys <= pRam->GCPhysLast
2415	&& GCPhysLast >= pRam->GCPhys)
2416	{
2417	/* completely within? */
2418	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2419	&& GCPhysLast <= pRam->GCPhysLast,
2420	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2421	GCPhys, GCPhysLast, pszDesc,
2422	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2423	VERR_PGM_RAM_CONFLICT);
2424	fRamExists = true;
2425	break;
2426	}
2427
2428	/* next */
2429	pRamPrev = pRam;
2430	pRam = pRam->pNextR3;
2431	}
2432	if (fRamExists)
2433	{
2434	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2435	uint32_t cPagesLeft = cPages;
2436	while (cPagesLeft-- > 0)
2437	{
2438	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2439	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2440	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2441	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2442	Assert(PGM_PAGE_IS_ZERO(pPage));
2443	pPage++;
2444	}
2445	}
2446
2447	/*
2448	* Update the base memory reservation if necessary.
2449	*/
2450	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
2451	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2452	cExtraBaseCost += cPages;
2453	if (cExtraBaseCost)
2454	{
2455	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2456	if (RT_FAILURE(rc))
2457	return rc;
2458	}
2459
2460	/*
2461	* Allocate memory for the virgin copy of the RAM.
2462	*/
2463	PGMMALLOCATEPAGESREQ pReq;
2464	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2465	AssertRCReturn(rc, rc);
2466
2467	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2468	{
2469	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2470	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2471	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2472	}
2473
2474	pgmLock(pVM);
2475	rc = GMMR3AllocatePagesPerform(pVM, pReq);
2476	pgmUnlock(pVM);
2477	if (RT_FAILURE(rc))
2478	{
2479	GMMR3AllocatePagesCleanup(pReq);
2480	return rc;
2481	}
2482
2483	/*
2484	* Allocate the new ROM range and RAM range (if necessary).
2485	*/
2486	PPGMROMRANGE pRomNew;
2487	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2488	if (RT_SUCCESS(rc))
2489	{
2490	PPGMRAMRANGE pRamNew = NULL;
2491	if (!fRamExists)
2492	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2493	if (RT_SUCCESS(rc))
2494	{
2495	pgmLock(pVM);
2496
2497	/*
2498	* Initialize and insert the RAM range (if required).
2499	*/
2500	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2501	if (!fRamExists)
2502	{
2503	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2504	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2505	pRamNew->GCPhys = GCPhys;
2506	pRamNew->GCPhysLast = GCPhysLast;
2507	pRamNew->cb = cb;
2508	pRamNew->pszDesc = pszDesc;
2509	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
2510	pRamNew->pvR3 = NULL;
2511	pRamNew->paLSPages = NULL;
2512
2513	PPGMPAGE pPage = &pRamNew->aPages[0];
2514	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2515	{
2516	PGM_PAGE_INIT(pPage,
2517	pReq->aPages[iPage].HCPhysGCPhys,
2518	pReq->aPages[iPage].idPage,
2519	PGMPAGETYPE_ROM,
2520	PGM_PAGE_STATE_ALLOCATED);
2521
2522	pRomPage->Virgin = *pPage;
2523	}
2524
2525	pVM->pgm.s.cAllPages += cPages;
2526	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2527	}
2528	else
2529	{
2530	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2531	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2532	{
2533	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2534	PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2535	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2536	PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2537
2538	pRomPage->Virgin = *pPage;
2539	}
2540
2541	pRamNew = pRam;
2542
2543	pVM->pgm.s.cZeroPages -= cPages;
2544	}
2545	pVM->pgm.s.cPrivatePages += cPages;
2546
2547	/* Flush physical page map TLB. */
2548	PGMPhysInvalidatePageMapTLB(pVM);
2549
2550	pgmUnlock(pVM);
2551
2552
2553	/*
2554	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2555	*
2556	* If it's shadowed we'll register the handler after the ROM notification
2557	* so we get the access handler callbacks that we should. If it isn't
2558	* shadowed we'll do it the other way around to make REM use the built-in
2559	* ROM behavior and not the handler behavior (which is to route all access
2560	* to PGM atm).
2561	*/
2562	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2563	{
2564	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2565	rc = PGMR3HandlerPhysicalRegister(pVM,
2566	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2567	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2568	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2569	GCPhys, GCPhysLast,
2570	pgmR3PhysRomWriteHandler, pRomNew,
2571	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2572	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2573	}
2574	else
2575	{
2576	rc = PGMR3HandlerPhysicalRegister(pVM,
2577	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2578	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2579	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2580	GCPhys, GCPhysLast,
2581	pgmR3PhysRomWriteHandler, pRomNew,
2582	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2583	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2584	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2585	}
2586	if (RT_SUCCESS(rc))
2587	{
2588	pgmLock(pVM);
2589
2590	/*
2591	* Copy the image over to the virgin pages.
2592	* This must be done after linking in the RAM range.
2593	*/
2594	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2595	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2596	{
2597	void *pvDstPage;
2598	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
2599	if (RT_FAILURE(rc))
2600	{
2601	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2602	break;
2603	}
2604	memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2605	}
2606	if (RT_SUCCESS(rc))
2607	{
2608	/*
2609	* Initialize the ROM range.
2610	* Note that the Virgin member of the pages has already been initialized above.
2611	*/
2612	pRomNew->GCPhys = GCPhys;
2613	pRomNew->GCPhysLast = GCPhysLast;
2614	pRomNew->cb = cb;
2615	pRomNew->fFlags = fFlags;
2616	pRomNew->idSavedState = UINT8_MAX;
2617	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2618	pRomNew->pszDesc = pszDesc;
2619
2620	for (unsigned iPage = 0; iPage < cPages; iPage++)
2621	{
2622	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2623	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2624	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2625	}
2626
2627	/* update the page count stats for the shadow pages. */
2628	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2629	{
2630	pVM->pgm.s.cZeroPages += cPages;
2631	pVM->pgm.s.cAllPages += cPages;
2632	}
2633
2634	/*
2635	* Insert the ROM range, tell REM and return successfully.
2636	*/
2637	pRomNew->pNextR3 = pRom;
2638	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2639	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2640
2641	if (pRomPrev)
2642	{
2643	pRomPrev->pNextR3 = pRomNew;
2644	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2645	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2646	}
2647	else
2648	{
2649	pVM->pgm.s.pRomRangesR3 = pRomNew;
2650	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2651	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2652	}
2653
2654	PGMPhysInvalidatePageMapTLB(pVM);
2655	GMMR3AllocatePagesCleanup(pReq);
2656	pgmUnlock(pVM);
2657	return VINF_SUCCESS;
2658	}
2659
2660	/* bail out */
2661
2662	pgmUnlock(pVM);
2663	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2664	AssertRC(rc2);
2665	pgmLock(pVM);
2666	}
2667
2668	if (!fRamExists)
2669	{
2670	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2671	MMHyperFree(pVM, pRamNew);
2672	}
2673	}
2674	MMHyperFree(pVM, pRomNew);
2675	}
2676
2677	/** @todo Purge the mapping cache or something... */
2678	GMMR3FreeAllocatedPages(pVM, pReq);
2679	GMMR3AllocatePagesCleanup(pReq);
2680	pgmUnlock(pVM);
2681	return rc;
2682	}
2683
2684
2685	/**
2686	* \#PF Handler callback for ROM write accesses.
2687	*
2688	* @returns VINF_SUCCESS if the handler have carried out the operation.
2689	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2690	* @param pVM VM Handle.
2691	* @param GCPhys The physical address the guest is writing to.
2692	* @param pvPhys The HC mapping of that address.
2693	* @param pvBuf What the guest is reading/writing.
2694	* @param cbBuf How much it's reading/writing.
2695	* @param enmAccessType The access type.
2696	* @param pvUser User argument.
2697	*/
2698	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2699	{
2700	PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2701	const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2702	Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2703	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2704	Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2705
2706	if (enmAccessType == PGMACCESSTYPE_READ)
2707	{
2708	switch (pRomPage->enmProt)
2709	{
2710	/*
2711	* Take the default action.
2712	*/
2713	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2714	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2715	case PGMROMPROT_READ_ROM_WRITE_RAM:
2716	case PGMROMPROT_READ_RAM_WRITE_RAM:
2717	return VINF_PGM_HANDLER_DO_DEFAULT;
2718
2719	default:
2720	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2721	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2722	VERR_INTERNAL_ERROR);
2723	}
2724	}
2725	else
2726	{
2727	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2728	switch (pRomPage->enmProt)
2729	{
2730	/*
2731	* Ignore writes.
2732	*/
2733	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2734	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2735	return VINF_SUCCESS;
2736
2737	/*
2738	* Write to the ram page.
2739	*/
2740	case PGMROMPROT_READ_ROM_WRITE_RAM:
2741	case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's way simpler that way. */
2742	{
2743	/* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2744	Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2745
2746	/*
2747	* Take the lock, do lazy allocation, map the page and copy the data.
2748	*
2749	* Note that we have to bypass the mapping TLB since it works on
2750	* guest physical addresses and entering the shadow page would
2751	* kind of screw things up...
2752	*/
2753	int rc = pgmLock(pVM);
2754	AssertRC(rc);
2755
2756	PPGMPAGE pShadowPage = &pRomPage->Shadow;
2757	if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2758	{
2759	pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2760	AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2761	}
2762
2763	void *pvDstPage;
2764	rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
2765	if (RT_SUCCESS(rc))
2766	{
2767	memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2768	pRomPage->LiveSave.fWrittenTo = true;
2769	}
2770
2771	pgmUnlock(pVM);
2772	return rc;
2773	}
2774
2775	default:
2776	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2777	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2778	VERR_INTERNAL_ERROR);
2779	}
2780	}
2781	}
2782
2783
2784	/**
2785	* Called by PGMR3Reset to reset the shadow, switch to the virgin,
2786	* and verify that the virgin part is untouched.
2787	*
2788	* This is done after the normal memory has been cleared.
2789	*
2790	* ASSUMES that the caller owns the PGM lock.
2791	*
2792	* @param pVM The VM handle.
2793	*/
2794	int pgmR3PhysRomReset(PVM pVM)
2795	{
2796	Assert(PGMIsLockOwner(pVM));
2797	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2798	{
2799	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2800
2801	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2802	{
2803	/*
2804	* Reset the physical handler.
2805	*/
2806	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2807	AssertRCReturn(rc, rc);
2808
2809	/*
2810	* What we do with the shadow pages depends on the memory
2811	* preallocation option. If not enabled, we'll just throw
2812	* out all the dirty pages and replace them by the zero page.
2813	*/
2814	if (!pVM->pgm.s.fRamPreAlloc)
2815	{
2816	/* Free the dirty pages. */
2817	uint32_t cPendingPages = 0;
2818	PGMMFREEPAGESREQ pReq;
2819	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2820	AssertRCReturn(rc, rc);
2821
2822	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2823	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
2824	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
2825	{
2826	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2827	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2828	AssertLogRelRCReturn(rc, rc);
2829	}
2830
2831	if (cPendingPages)
2832	{
2833	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2834	AssertLogRelRCReturn(rc, rc);
2835	}
2836	GMMR3FreePagesCleanup(pReq);
2837	}
2838	else
2839	{
2840	/* clear all the shadow pages. */
2841	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2842	{
2843	Assert(!PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
2844	void *pvDstPage;
2845	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2846	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
2847	if (RT_FAILURE(rc))
2848	break;
2849	ASMMemZeroPage(pvDstPage);
2850	}
2851	AssertRCReturn(rc, rc);
2852	}
2853	}
2854
2855	#ifdef VBOX_STRICT
2856	/*
2857	* Verify that the virgin page is unchanged if possible.
2858	*/
2859	if (pRom->pvOriginal)
2860	{
2861	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
2862	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2863	{
2864	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2865	void const *pvDstPage;
2866	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
2867	if (RT_FAILURE(rc))
2868	break;
2869	if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2870	LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2871	GCPhys, pRom->pszDesc));
2872	}
2873	}
2874	#endif
2875	}
2876
2877	return VINF_SUCCESS;
2878	}
2879
2880
2881	/**
2882	* Change the shadowing of a range of ROM pages.
2883	*
2884	* This is intended for implementing chipset specific memory registers
2885	* and will not be very strict about the input. It will silently ignore
2886	* any pages that are not the part of a shadowed ROM.
2887	*
2888	* @returns VBox status code.
2889	* @retval VINF_PGM_SYNC_CR3
2890	*
2891	* @param pVM Pointer to the shared VM structure.
2892	* @param GCPhys Where to start. Page aligned.
2893	* @param cb How much to change. Page aligned.
2894	* @param enmProt The new ROM protection.
2895	*/
2896	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2897	{
2898	/*
2899	* Check input
2900	*/
2901	if (!cb)
2902	return VINF_SUCCESS;
2903	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2904	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2905	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2906	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2907	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2908
2909	/*
2910	* Process the request.
2911	*/
2912	pgmLock(pVM);
2913	int rc = VINF_SUCCESS;
2914	bool fFlushTLB = false;
2915	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2916	{
2917	if ( GCPhys <= pRom->GCPhysLast
2918	&& GCPhysLast >= pRom->GCPhys
2919	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2920	{
2921	/*
2922	* Iterate the relevant pages and make necessary the changes.
2923	*/
2924	bool fChanges = false;
2925	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2926	? pRom->cb >> PAGE_SHIFT
2927	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2928	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2929	iPage < cPages;
2930	iPage++)
2931	{
2932	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2933	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2934	{
2935	fChanges = true;
2936
2937	/* flush references to the page. */
2938	PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2939	int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage, &fFlushTLB);
2940	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
2941	rc = rc2;
2942
2943	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2944	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2945
2946	pOld = pRamPage;
2947	pRamPage = pNew;
2948	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2949	}
2950	pRomPage->enmProt = enmProt;
2951	}
2952
2953	/*
2954	* Reset the access handler if we made changes, no need
2955	* to optimize this.
2956	*/
2957	if (fChanges)
2958	{
2959	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2960	if (RT_FAILURE(rc2))
2961	{
2962	pgmUnlock(pVM);
2963	AssertRC(rc);
2964	return rc2;
2965	}
2966	}
2967
2968	/* Advance - cb isn't updated. */
2969	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2970	}
2971	}
2972	pgmUnlock(pVM);
2973	if (fFlushTLB)
2974	PGM_INVL_ALL_VCPU_TLBS(pVM);
2975
2976	return rc;
2977	}
2978
2979
2980	/**
2981	* Sets the Address Gate 20 state.
2982	*
2983	* @param pVCpu The VCPU to operate on.
2984	* @param fEnable True if the gate should be enabled.
2985	* False if the gate should be disabled.
2986	*/
2987	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
2988	{
2989	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
2990	if (pVCpu->pgm.s.fA20Enabled != fEnable)
2991	{
2992	pVCpu->pgm.s.fA20Enabled = fEnable;
2993	pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2994	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
2995	/** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2996	}
2997	}
2998
2999
3000	/**
3001	* Tree enumeration callback for dealing with age rollover.
3002	* It will perform a simple compression of the current age.
3003	*/
3004	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
3005	{
3006	Assert(PGMIsLockOwner((PVM)pvUser));
3007	/* Age compression - ASSUMES iNow == 4. */
3008	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3009	if (pChunk->iAge >= UINT32_C(0xffffff00))
3010	pChunk->iAge = 3;
3011	else if (pChunk->iAge >= UINT32_C(0xfffff000))
3012	pChunk->iAge = 2;
3013	else if (pChunk->iAge)
3014	pChunk->iAge = 1;
3015	else /* iAge = 0 */
3016	pChunk->iAge = 4;
3017
3018	/* reinsert */
3019	PVM pVM = (PVM)pvUser;
3020	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
3021	pChunk->AgeCore.Key = pChunk->iAge;
3022	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3023	return 0;
3024	}
3025
3026
3027	/**
3028	* Tree enumeration callback that updates the chunks that have
3029	* been used since the last
3030	*/
3031	static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
3032	{
3033	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3034	if (!pChunk->iAge)
3035	{
3036	PVM pVM = (PVM)pvUser;
3037	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
3038	pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
3039	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3040	}
3041
3042	return 0;
3043	}
3044
3045
3046	/**
3047	* Performs ageing of the ring-3 chunk mappings.
3048	*
3049	* @param pVM The VM handle.
3050	*/
3051	VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
3052	{
3053	pgmLock(pVM);
3054	pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
3055	pVM->pgm.s.ChunkR3Map.iNow++;
3056	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
3057	{
3058	pVM->pgm.s.ChunkR3Map.iNow = 4;
3059	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
3060	}
3061	else
3062	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingCallback, pVM);
3063	pgmUnlock(pVM);
3064	}
3065
3066
3067	/**
3068	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
3069	*/
3070	typedef struct PGMR3PHYSCHUNKUNMAPCB
3071	{
3072	PVM pVM; /*< The VM handle. /
3073	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
3074	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
3075
3076
3077	/**
3078	* Callback used to find the mapping that's been unused for
3079	* the longest time.
3080	*/
3081	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
3082	{
3083	do
3084	{
3085	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
3086	if ( pChunk->iAge
3087	&& !pChunk->cRefs)
3088	{
3089	/*
3090	* Check that it's not in any of the TLBs.
3091	*/
3092	PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
3093	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3094	if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
3095	{
3096	pChunk = NULL;
3097	break;
3098	}
3099	if (pChunk)
3100	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
3101	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
3102	{
3103	pChunk = NULL;
3104	break;
3105	}
3106	if (pChunk)
3107	{
3108	((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
3109	return 1; /* done */
3110	}
3111	}
3112
3113	/* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
3114	pNode = pNode->pList;
3115	} while (pNode);
3116	return 0;
3117	}
3118
3119
3120	/**
3121	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
3122	*
3123	* The candidate will not be part of any TLBs, so no need to flush
3124	* anything afterwards.
3125	*
3126	* @returns Chunk id.
3127	* @param pVM The VM handle.
3128	*/
3129	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
3130	{
3131	Assert(PGMIsLockOwner(pVM));
3132
3133	/*
3134	* Do tree ageing first?
3135	*/
3136	if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
3137	PGMR3PhysChunkAgeing(pVM);
3138
3139	/*
3140	* Enumerate the age tree starting with the left most node.
3141	*/
3142	PGMR3PHYSCHUNKUNMAPCB Args;
3143	Args.pVM = pVM;
3144	Args.pChunk = NULL;
3145	if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
3146	return Args.pChunk->Core.Key;
3147	return INT32_MAX;
3148	}
3149
3150
3151	/**
3152	* Maps the given chunk into the ring-3 mapping cache.
3153	*
3154	* This will call ring-0.
3155	*
3156	* @returns VBox status code.
3157	* @param pVM The VM handle.
3158	* @param idChunk The chunk in question.
3159	* @param ppChunk Where to store the chunk tracking structure.
3160	*
3161	* @remarks Called from within the PGM critical section.
3162	*/
3163	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
3164	{
3165	int rc;
3166
3167	Assert(PGMIsLockOwner(pVM));
3168	/*
3169	* Allocate a new tracking structure first.
3170	*/
3171	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3172	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
3173	#else
3174	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
3175	#endif
3176	AssertReturn(pChunk, VERR_NO_MEMORY);
3177	pChunk->Core.Key = idChunk;
3178	pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
3179	pChunk->iAge = 0;
3180	pChunk->cRefs = 0;
3181	pChunk->cPermRefs = 0;
3182	pChunk->pv = NULL;
3183
3184	/*
3185	* Request the ring-0 part to map the chunk in question and if
3186	* necessary unmap another one to make space in the mapping cache.
3187	*/
3188	GMMMAPUNMAPCHUNKREQ Req;
3189	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3190	Req.Hdr.cbReq = sizeof(Req);
3191	Req.pvR3 = NULL;
3192	Req.idChunkMap = idChunk;
3193	Req.idChunkUnmap = NIL_GMM_CHUNKID;
3194	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3195	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
3196	/** @todo This is wrong. Any thread in the VM process should be able to do this,
3197	* there are depenenecies on this. What currently saves the day is that
3198	* we don't unmap anything and that all non-zero memory will therefore
3199	* be present when non-EMTs tries to access it. */
3200	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3201	if (RT_SUCCESS(rc))
3202	{
3203	/*
3204	* Update the tree.
3205	*/
3206	/* insert the new one. */
3207	AssertPtr(Req.pvR3);
3208	pChunk->pv = Req.pvR3;
3209	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
3210	AssertRelease(fRc);
3211	pVM->pgm.s.ChunkR3Map.c++;
3212
3213	fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3214	AssertRelease(fRc);
3215
3216	/* remove the unmapped one. */
3217	if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
3218	{
3219	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
3220	AssertRelease(pUnmappedChunk);
3221	pUnmappedChunk->pv = NULL;
3222	pUnmappedChunk->Core.Key = UINT32_MAX;
3223	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3224	MMR3HeapFree(pUnmappedChunk);
3225	#else
3226	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3227	#endif
3228	pVM->pgm.s.ChunkR3Map.c--;
3229
3230	/* Chunk removed, so clear the page map TBL as well (might still be referenced). */
3231	PGMPhysInvalidatePageMapTLB(pVM);
3232	}
3233	}
3234	else
3235	{
3236	AssertRC(rc);
3237	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3238	MMR3HeapFree(pChunk);
3239	#else
3240	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
3241	#endif
3242	pChunk = NULL;
3243	}
3244
3245	*ppChunk = pChunk;
3246	return rc;
3247	}
3248
3249
3250	/**
3251	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3252	*
3253	* @returns see pgmR3PhysChunkMap.
3254	* @param pVM The VM handle.
3255	* @param idChunk The chunk to map.
3256	*/
3257	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3258	{
3259	PPGMCHUNKR3MAP pChunk;
3260	int rc;
3261
3262	pgmLock(pVM);
3263	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3264	pgmUnlock(pVM);
3265	return rc;
3266	}
3267
3268
3269	/**
3270	* Invalidates the TLB for the ring-3 mapping cache.
3271	*
3272	* @param pVM The VM handle.
3273	*/
3274	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3275	{
3276	pgmLock(pVM);
3277	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3278	{
3279	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3280	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3281	}
3282	/* The page map TLB references chunks, so invalidate that one too. */
3283	PGMPhysInvalidatePageMapTLB(pVM);
3284	pgmUnlock(pVM);
3285	}
3286
3287
3288	/**
3289	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_PAGE to allocate a large (2MB) page
3290	* for use with a nested paging PDE.
3291	*
3292	* @returns The following VBox status codes.
3293	* @retval VINF_SUCCESS on success.
3294	* @retval VINF_EM_NO_MEMORY if we're out of memory.
3295	*
3296	* @param pVM The VM handle.
3297	* @param GCPhys GC physical start address of the 2 MB range
3298	*/
3299	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
3300	{
3301	pgmLock(pVM);
3302
3303	STAM_PROFILE_START(&pVM->pgm.s.StatAllocLargePage, a);
3304	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
3305	STAM_PROFILE_STOP(&pVM->pgm.s.StatAllocLargePage, a);
3306	if (RT_SUCCESS(rc))
3307	{
3308	Assert(pVM->pgm.s.cLargeHandyPages == 1);
3309
3310	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
3311	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
3312
3313	void *pv;
3314
3315	/* Map the large page into our address space.
3316	*
3317	* Note: assuming that within the 2 MB range:
3318	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
3319	* - user space mapping is continuous as well
3320	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
3321	*/
3322	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
3323	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", idPage, HCPhys, rc));
3324
3325	if (RT_SUCCESS(rc))
3326	{
3327	/*
3328	* Clear the pages.
3329	*/
3330	STAM_PROFILE_START(&pVM->pgm.s.StatClearLargePage, b);
3331	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
3332	{
3333	ASMMemZeroPage(pv);
3334
3335	PPGMPAGE pPage;
3336	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
3337	AssertRC(rc);
3338
3339	Assert(PGM_PAGE_IS_ZERO(pPage));
3340	STAM_COUNTER_INC(&pVM->pgm.s.StatRZPageReplaceZero);
3341	pVM->pgm.s.cZeroPages--;
3342
3343	/*
3344	* Do the PGMPAGE modifications.
3345	*/
3346	pVM->pgm.s.cPrivatePages++;
3347	PGM_PAGE_SET_HCPHYS(pPage, HCPhys);
3348	PGM_PAGE_SET_PAGEID(pPage, idPage);
3349	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
3350	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_PDE);
3351
3352	/* Somewhat dirty assumption that page ids are increasing. */
3353	idPage++;
3354
3355	HCPhys += PAGE_SIZE;
3356	GCPhys += PAGE_SIZE;
3357
3358	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
3359
3360	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
3361	}
3362	STAM_PROFILE_STOP(&pVM->pgm.s.StatClearLargePage, b);
3363
3364	/* Flush all TLBs. */
3365	PGM_INVL_ALL_VCPU_TLBS(pVM);
3366	PGMPhysInvalidatePageMapTLB(pVM);
3367	}
3368	pVM->pgm.s.cLargeHandyPages = 0;
3369	}
3370
3371	pgmUnlock(pVM);
3372	return rc;
3373	}
3374
3375
3376	/**
3377	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3378	*
3379	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3380	* signal and clear the out of memory condition. When contracted, this API is
3381	* used to try clear the condition when the user wants to resume.
3382	*
3383	* @returns The following VBox status codes.
3384	* @retval VINF_SUCCESS on success. FFs cleared.
3385	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3386	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3387	*
3388	* @param pVM The VM handle.
3389	*
3390	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3391	* in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3392	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3393	* handler.
3394	*/
3395	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3396	{
3397	pgmLock(pVM);
3398
3399	/*
3400	* Allocate more pages, noting down the index of the first new page.
3401	*/
3402	uint32_t iClear = pVM->pgm.s.cHandyPages;
3403	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3404	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3405	int rcAlloc = VINF_SUCCESS;
3406	int rcSeed = VINF_SUCCESS;
3407	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3408	while (rc == VERR_GMM_SEED_ME)
3409	{
3410	void *pvChunk;
3411	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3412	if (RT_SUCCESS(rc))
3413	{
3414	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3415	if (RT_FAILURE(rc))
3416	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3417	}
3418	if (RT_SUCCESS(rc))
3419	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3420	}
3421
3422	if (RT_SUCCESS(rc))
3423	{
3424	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3425	Assert(pVM->pgm.s.cHandyPages > 0);
3426	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3427	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3428
3429	/*
3430	* Clear the pages.
3431	*/
3432	while (iClear < pVM->pgm.s.cHandyPages)
3433	{
3434	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3435	void *pv;
3436	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3437	AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3438	ASMMemZeroPage(pv);
3439	iClear++;
3440	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3441	}
3442	}
3443	else
3444	{
3445	/*
3446	* We should never get here unless there is a genuine shortage of
3447	* memory (or some internal error). Flag the error so the VM can be
3448	* suspended ASAP and the user informed. If we're totally out of
3449	* handy pages we will return failure.
3450	*/
3451	/* Report the failure. */
3452	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3453	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3454	rc, rcAlloc, rcSeed,
3455	pVM->pgm.s.cHandyPages,
3456	pVM->pgm.s.cAllPages,
3457	pVM->pgm.s.cPrivatePages,
3458	pVM->pgm.s.cSharedPages,
3459	pVM->pgm.s.cZeroPages));
3460	if ( rc != VERR_NO_MEMORY
3461	&& rc != VERR_LOCK_FAILED)
3462	{
3463	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3464	{
3465	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3466	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3467	pVM->pgm.s.aHandyPages[i].idSharedPage));
3468	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3469	if (idPage != NIL_GMM_PAGEID)
3470	{
3471	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3472	pRam;
3473	pRam = pRam->pNextR3)
3474	{
3475	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3476	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3477	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3478	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3479	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3480	}
3481	}
3482	}
3483	}
3484
3485	/* Set the FFs and adjust rc. */
3486	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3487	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3488	if ( rc == VERR_NO_MEMORY
3489	\|\| rc == VERR_LOCK_FAILED)
3490	rc = VINF_EM_NO_MEMORY;
3491	}
3492
3493	pgmUnlock(pVM);
3494	return rc;
3495	}
3496
3497
3498	/**
3499	* Frees the specified RAM page and replaces it with the ZERO page.
3500	*
3501	* This is used by ballooning, remapping MMIO2 and RAM reset.
3502	*
3503	* @param pVM Pointer to the shared VM structure.
3504	* @param pReq Pointer to the request.
3505	* @param pPage Pointer to the page structure.
3506	* @param GCPhys The guest physical address of the page, if applicable.
3507	*
3508	* @remarks The caller must own the PGM lock.
3509	*/
3510	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3511	{
3512	/*
3513	* Assert sanity.
3514	*/
3515	Assert(PGMIsLockOwner(pVM));
3516	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3517	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3518	{
3519	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3520	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3521	}
3522
3523	if ( PGM_PAGE_IS_ZERO(pPage)
3524	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3525	return VINF_SUCCESS;
3526
3527	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3528	Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3529	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3530	\|\| idPage > GMM_PAGEID_LAST
3531	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3532	{
3533	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3534	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3535	}
3536
3537	/* update page count stats. */
3538	if (PGM_PAGE_IS_SHARED(pPage))
3539	pVM->pgm.s.cSharedPages--;
3540	else
3541	pVM->pgm.s.cPrivatePages--;
3542	pVM->pgm.s.cZeroPages++;
3543
3544	/* Deal with write monitored pages. */
3545	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
3546	{
3547	PGM_PAGE_SET_WRITTEN_TO(pPage);
3548	pVM->pgm.s.cWrittenToPages++;
3549	}
3550
3551	/*
3552	* pPage = ZERO page.
3553	*/
3554	PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3555	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3556	PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3557	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
3558
3559	/* Flush physical page map TLB entry. */
3560	PGMPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
3561
3562	/*
3563	* Make sure it's not in the handy page array.
3564	*/
3565	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3566	{
3567	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3568	{
3569	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3570	break;
3571	}
3572	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3573	{
3574	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3575	break;
3576	}
3577	}
3578
3579	/*
3580	* Push it onto the page array.
3581	*/
3582	uint32_t iPage = *pcPendingPages;
3583	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3584	*pcPendingPages += 1;
3585
3586	pReq->aPages[iPage].idPage = idPage;
3587
3588	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3589	return VINF_SUCCESS;
3590
3591	/*
3592	* Flush the pages.
3593	*/
3594	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3595	if (RT_SUCCESS(rc))
3596	{
3597	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3598	*pcPendingPages = 0;
3599	}
3600	return rc;
3601	}
3602
3603
3604	/**
3605	* Converts a GC physical address to a HC ring-3 pointer, with some
3606	* additional checks.
3607	*
3608	* @returns VBox status code.
3609	* @retval VINF_SUCCESS on success.
3610	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3611	* access handler of some kind.
3612	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3613	* accesses or is odd in any way.
3614	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3615	*
3616	* @param pVM The VM handle.
3617	* @param GCPhys The GC physical address to convert.
3618	* @param fWritable Whether write access is required.
3619	* @param ppv Where to store the pointer corresponding to GCPhys on
3620	* success.
3621	*/
3622	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3623	{
3624	pgmLock(pVM);
3625
3626	PPGMRAMRANGE pRam;
3627	PPGMPAGE pPage;
3628	int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3629	if (RT_SUCCESS(rc))
3630	{
3631	if (PGM_PAGE_IS_BALLOONED(pPage))
3632	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3633	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3634	rc = VINF_SUCCESS;
3635	else
3636	{
3637	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3638	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3639	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3640	{
3641	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3642	* in -norawr0 mode. */
3643	if (fWritable)
3644	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3645	}
3646	else
3647	{
3648	/* Temporarily disabled physical handler(s), since the recompiler
3649	doesn't get notified when it's reset we'll have to pretend it's
3650	operating normally. */
3651	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3652	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3653	else
3654	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3655	}
3656	}
3657	if (RT_SUCCESS(rc))
3658	{
3659	int rc2;
3660
3661	/* Make sure what we return is writable. */
3662	if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3663	switch (PGM_PAGE_GET_STATE(pPage))
3664	{
3665	case PGM_PAGE_STATE_ALLOCATED:
3666	break;
3667	case PGM_PAGE_STATE_BALLOONED:
3668	AssertFailed();
3669	break;
3670	case PGM_PAGE_STATE_ZERO:
3671	case PGM_PAGE_STATE_SHARED:
3672	case PGM_PAGE_STATE_WRITE_MONITORED:
3673	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3674	AssertLogRelRCReturn(rc2, rc2);
3675	break;
3676	}
3677
3678	/* Get a ring-3 mapping of the address. */
3679	PPGMPAGER3MAPTLBE pTlbe;
3680	rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3681	AssertLogRelRCReturn(rc2, rc2);
3682	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
3683	/** @todo mapping/locking hell; this isn't horribly efficient since
3684	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
3685
3686	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
3687	}
3688	else
3689	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3690
3691	/* else: handler catching all access, no pointer returned. */
3692	}
3693	else
3694	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3695
3696	pgmUnlock(pVM);
3697	return rc;
3698	}
3699

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source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 27746

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