PGMPhys.cpp@ 27948

Last change on this file since 27948 was 27750, checked in by vboxsync, 15 years ago
Reset the balloon state when the VM resets
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1	/* $Id: PGMPhys.cpp 27750 2010-03-26 15:28:11Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_PHYS
27	#include <VBox/pgm.h>
28	#include <VBox/iom.h>
29	#include <VBox/mm.h>
30	#include <VBox/stam.h>
31	#include <VBox/rem.h>
32	#include <VBox/pdmdev.h>
33	#include "PGMInternal.h"
34	#include <VBox/vm.h>
35	#include "PGMInline.h"
36	#include <VBox/sup.h>
37	#include <VBox/param.h>
38	#include <VBox/err.h>
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/alloc.h>
42	#include <iprt/asm.h>
43	#include <iprt/thread.h>
44	#include <iprt/string.h>
45
46
47	/*******************************************************************************
48	* Defined Constants And Macros *
49	*******************************************************************************/
50	/** The number of pages to free in one batch. */
51	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
52
53
54	/*******************************************************************************
55	* Internal Functions *
56	*******************************************************************************/
57	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
58	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
59
60
61	/*
62	* PGMR3PhysReadU8-64
63	* PGMR3PhysWriteU8-64
64	*/
65	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
66	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
67	#define PGMPHYS_DATASIZE 1
68	#define PGMPHYS_DATATYPE uint8_t
69	#include "PGMPhysRWTmpl.h"
70
71	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
72	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
73	#define PGMPHYS_DATASIZE 2
74	#define PGMPHYS_DATATYPE uint16_t
75	#include "PGMPhysRWTmpl.h"
76
77	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
78	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
79	#define PGMPHYS_DATASIZE 4
80	#define PGMPHYS_DATATYPE uint32_t
81	#include "PGMPhysRWTmpl.h"
82
83	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
84	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
85	#define PGMPHYS_DATASIZE 8
86	#define PGMPHYS_DATATYPE uint64_t
87	#include "PGMPhysRWTmpl.h"
88
89
90	/**
91	* EMT worker for PGMR3PhysReadExternal.
92	*/
93	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
94	{
95	PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
96	return VINF_SUCCESS;
97	}
98
99
100	/**
101	* Write to physical memory, external users.
102	*
103	* @returns VBox status code.
104	* @retval VINF_SUCCESS.
105	*
106	* @param pVM VM Handle.
107	* @param GCPhys Physical address to write to.
108	* @param pvBuf What to write.
109	* @param cbWrite How many bytes to write.
110	*
111	* @thread Any but EMTs.
112	*/
113	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
114	{
115	VM_ASSERT_OTHER_THREAD(pVM);
116
117	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
118	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
119
120	pgmLock(pVM);
121
122	/*
123	* Copy loop on ram ranges.
124	*/
125	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
126	for (;;)
127	{
128	/* Find range. */
129	while (pRam && GCPhys > pRam->GCPhysLast)
130	pRam = pRam->CTX_SUFF(pNext);
131	/* Inside range or not? */
132	if (pRam && GCPhys >= pRam->GCPhys)
133	{
134	/*
135	* Must work our way thru this page by page.
136	*/
137	RTGCPHYS off = GCPhys - pRam->GCPhys;
138	while (off < pRam->cb)
139	{
140	unsigned iPage = off >> PAGE_SHIFT;
141	PPGMPAGE pPage = &pRam->aPages[iPage];
142
143	/*
144	* If the page has an ALL access handler, we'll have to
145	* delegate the job to EMT.
146	*/
147	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
148	{
149	pgmUnlock(pVM);
150
151	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 4,
152	pVM, &GCPhys, pvBuf, cbRead);
153	}
154	Assert(!PGM_PAGE_IS_MMIO(pPage));
155
156	/*
157	* Simple stuff, go ahead.
158	*/
159	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
160	if (cb > cbRead)
161	cb = cbRead;
162	const void *pvSrc;
163	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
164	if (RT_SUCCESS(rc))
165	memcpy(pvBuf, pvSrc, cb);
166	else
167	{
168	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
169	pRam->GCPhys + off, pPage, rc));
170	memset(pvBuf, 0xff, cb);
171	}
172
173	/* next page */
174	if (cb >= cbRead)
175	{
176	pgmUnlock(pVM);
177	return VINF_SUCCESS;
178	}
179	cbRead -= cb;
180	off += cb;
181	GCPhys += cb;
182	pvBuf = (char *)pvBuf + cb;
183	} /* walk pages in ram range. */
184	}
185	else
186	{
187	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
188
189	/*
190	* Unassigned address space.
191	*/
192	if (!pRam)
193	break;
194	size_t cb = pRam->GCPhys - GCPhys;
195	if (cb >= cbRead)
196	{
197	memset(pvBuf, 0xff, cbRead);
198	break;
199	}
200	memset(pvBuf, 0xff, cb);
201
202	cbRead -= cb;
203	pvBuf = (char *)pvBuf + cb;
204	GCPhys += cb;
205	}
206	} /* Ram range walk */
207
208	pgmUnlock(pVM);
209
210	return VINF_SUCCESS;
211	}
212
213
214	/**
215	* EMT worker for PGMR3PhysWriteExternal.
216	*/
217	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
218	{
219	/** @todo VERR_EM_NO_MEMORY */
220	PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
221	return VINF_SUCCESS;
222	}
223
224
225	/**
226	* Write to physical memory, external users.
227	*
228	* @returns VBox status code.
229	* @retval VINF_SUCCESS.
230	* @retval VERR_EM_NO_MEMORY.
231	*
232	* @param pVM VM Handle.
233	* @param GCPhys Physical address to write to.
234	* @param pvBuf What to write.
235	* @param cbWrite How many bytes to write.
236	* @param pszWho Who is writing. For tracking down who is writing
237	* after we've saved the state.
238	*
239	* @thread Any but EMTs.
240	*/
241	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void pvBuf, size_t cbWrite, const char pszWho)
242	{
243	VM_ASSERT_OTHER_THREAD(pVM);
244
245	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
246	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x pszWho=%s\n",
247	GCPhys, cbWrite, pszWho));
248	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
249	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
250
251	pgmLock(pVM);
252
253	/*
254	* Copy loop on ram ranges, stop when we hit something difficult.
255	*/
256	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
257	for (;;)
258	{
259	/* Find range. */
260	while (pRam && GCPhys > pRam->GCPhysLast)
261	pRam = pRam->CTX_SUFF(pNext);
262	/* Inside range or not? */
263	if (pRam && GCPhys >= pRam->GCPhys)
264	{
265	/*
266	* Must work our way thru this page by page.
267	*/
268	RTGCPTR off = GCPhys - pRam->GCPhys;
269	while (off < pRam->cb)
270	{
271	RTGCPTR iPage = off >> PAGE_SHIFT;
272	PPGMPAGE pPage = &pRam->aPages[iPage];
273
274	/*
275	* Is the page problematic, we have to do the work on the EMT.
276	*
277	* Allocating writable pages and access handlers are
278	* problematic, write monitored pages are simple and can be
279	* dealth with here.
280	*/
281	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
282	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
283	{
284	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
285	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
286	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
287	else
288	{
289	pgmUnlock(pVM);
290
291	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 4,
292	pVM, &GCPhys, pvBuf, cbWrite);
293	}
294	}
295	Assert(!PGM_PAGE_IS_MMIO(pPage));
296
297	/*
298	* Simple stuff, go ahead.
299	*/
300	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
301	if (cb > cbWrite)
302	cb = cbWrite;
303	void *pvDst;
304	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
305	if (RT_SUCCESS(rc))
306	memcpy(pvDst, pvBuf, cb);
307	else
308	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
309	pRam->GCPhys + off, pPage, rc));
310
311	/* next page */
312	if (cb >= cbWrite)
313	{
314	pgmUnlock(pVM);
315	return VINF_SUCCESS;
316	}
317
318	cbWrite -= cb;
319	off += cb;
320	GCPhys += cb;
321	pvBuf = (const char *)pvBuf + cb;
322	} /* walk pages in ram range */
323	}
324	else
325	{
326	/*
327	* Unassigned address space, skip it.
328	*/
329	if (!pRam)
330	break;
331	size_t cb = pRam->GCPhys - GCPhys;
332	if (cb >= cbWrite)
333	break;
334	cbWrite -= cb;
335	pvBuf = (const char *)pvBuf + cb;
336	GCPhys += cb;
337	}
338	} /* Ram range walk */
339
340	pgmUnlock(pVM);
341	return VINF_SUCCESS;
342	}
343
344
345	/**
346	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
347	*
348	* @returns see PGMR3PhysGCPhys2CCPtrExternal
349	* @param pVM The VM handle.
350	* @param pGCPhys Pointer to the guest physical address.
351	* @param ppv Where to store the mapping address.
352	* @param pLock Where to store the lock.
353	*/
354	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
355	{
356	/*
357	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
358	* an access handler after it succeeds.
359	*/
360	int rc = pgmLock(pVM);
361	AssertRCReturn(rc, rc);
362
363	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
364	if (RT_SUCCESS(rc))
365	{
366	PPGMPAGEMAPTLBE pTlbe;
367	int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
368	AssertFatalRC(rc2);
369	PPGMPAGE pPage = pTlbe->pPage;
370	if (PGM_PAGE_IS_MMIO(pPage))
371	{
372	PGMPhysReleasePageMappingLock(pVM, pLock);
373	rc = VERR_PGM_PHYS_PAGE_RESERVED;
374	}
375	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
376	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
377	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
378	#endif
379	)
380	{
381	/* We must flush any corresponding pgm pool page here, otherwise we'll
382	* not be informed about writes and keep bogus gst->shw mappings around.
383	*/
384	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
385	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
386	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
387	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
388	}
389	}
390
391	pgmUnlock(pVM);
392	return rc;
393	}
394
395
396	/**
397	* Requests the mapping of a guest page into ring-3, external threads.
398	*
399	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
400	* release it.
401	*
402	* This API will assume your intention is to write to the page, and will
403	* therefore replace shared and zero pages. If you do not intend to modify the
404	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
405	*
406	* @returns VBox status code.
407	* @retval VINF_SUCCESS on success.
408	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
409	* backing or if the page has any active access handlers. The caller
410	* must fall back on using PGMR3PhysWriteExternal.
411	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
412	*
413	* @param pVM The VM handle.
414	* @param GCPhys The guest physical address of the page that should be mapped.
415	* @param ppv Where to store the address corresponding to GCPhys.
416	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
417	*
418	* @remark Avoid calling this API from within critical sections (other than the
419	* PGM one) because of the deadlock risk when we have to delegating the
420	* task to an EMT.
421	* @thread Any.
422	*/
423	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
424	{
425	AssertPtr(ppv);
426	AssertPtr(pLock);
427
428	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
429
430	int rc = pgmLock(pVM);
431	AssertRCReturn(rc, rc);
432
433	/*
434	* Query the Physical TLB entry for the page (may fail).
435	*/
436	PPGMPAGEMAPTLBE pTlbe;
437	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
438	if (RT_SUCCESS(rc))
439	{
440	PPGMPAGE pPage = pTlbe->pPage;
441	if (PGM_PAGE_IS_MMIO(pPage))
442	rc = VERR_PGM_PHYS_PAGE_RESERVED;
443	else
444	{
445	/*
446	* If the page is shared, the zero page, or being write monitored
447	* it must be converted to an page that's writable if possible.
448	* We can only deal with write monitored pages here, the rest have
449	* to be on an EMT.
450	*/
451	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
452	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
453	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
454	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
455	#endif
456	)
457	{
458	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
459	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
460	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
461	&& !pgmPoolIsDirtyPage(pVM, GCPhys)
462	#endif
463	)
464	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
465	else
466	{
467	pgmUnlock(pVM);
468
469	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
470	pVM, &GCPhys, ppv, pLock);
471	}
472	}
473
474	/*
475	* Now, just perform the locking and calculate the return address.
476	*/
477	PPGMPAGEMAP pMap = pTlbe->pMap;
478	if (pMap)
479	pMap->cRefs++;
480
481	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
482	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
483	{
484	if (cLocks == 0)
485	pVM->pgm.s.cWriteLockedPages++;
486	PGM_PAGE_INC_WRITE_LOCKS(pPage);
487	}
488	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
489	{
490	PGM_PAGE_INC_WRITE_LOCKS(pPage);
491	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
492	if (pMap)
493	pMap->cRefs++; /* Extra ref to prevent it from going away. */
494	}
495
496	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
497	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
498	pLock->pvMap = pMap;
499	}
500	}
501
502	pgmUnlock(pVM);
503	return rc;
504	}
505
506
507	/**
508	* Requests the mapping of a guest page into ring-3, external threads.
509	*
510	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
511	* release it.
512	*
513	* @returns VBox status code.
514	* @retval VINF_SUCCESS on success.
515	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
516	* backing or if the page as an active ALL access handler. The caller
517	* must fall back on using PGMPhysRead.
518	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
519	*
520	* @param pVM The VM handle.
521	* @param GCPhys The guest physical address of the page that should be mapped.
522	* @param ppv Where to store the address corresponding to GCPhys.
523	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
524	*
525	* @remark Avoid calling this API from within critical sections (other than
526	* the PGM one) because of the deadlock risk.
527	* @thread Any.
528	*/
529	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
530	{
531	int rc = pgmLock(pVM);
532	AssertRCReturn(rc, rc);
533
534	/*
535	* Query the Physical TLB entry for the page (may fail).
536	*/
537	PPGMPAGEMAPTLBE pTlbe;
538	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
539	if (RT_SUCCESS(rc))
540	{
541	PPGMPAGE pPage = pTlbe->pPage;
542	#if 1
543	/* MMIO pages doesn't have any readable backing. */
544	if (PGM_PAGE_IS_MMIO(pPage))
545	rc = VERR_PGM_PHYS_PAGE_RESERVED;
546	#else
547	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
548	rc = VERR_PGM_PHYS_PAGE_RESERVED;
549	#endif
550	else
551	{
552	/*
553	* Now, just perform the locking and calculate the return address.
554	*/
555	PPGMPAGEMAP pMap = pTlbe->pMap;
556	if (pMap)
557	pMap->cRefs++;
558
559	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
560	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
561	{
562	if (cLocks == 0)
563	pVM->pgm.s.cReadLockedPages++;
564	PGM_PAGE_INC_READ_LOCKS(pPage);
565	}
566	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
567	{
568	PGM_PAGE_INC_READ_LOCKS(pPage);
569	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
570	if (pMap)
571	pMap->cRefs++; /* Extra ref to prevent it from going away. */
572	}
573
574	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
575	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
576	pLock->pvMap = pMap;
577	}
578	}
579
580	pgmUnlock(pVM);
581	return rc;
582	}
583
584
585	/**
586	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
587	*
588	* Called when anything was relocated.
589	*
590	* @param pVM Pointer to the shared VM structure.
591	*/
592	void pgmR3PhysRelinkRamRanges(PVM pVM)
593	{
594	PPGMRAMRANGE pCur;
595
596	#ifdef VBOX_STRICT
597	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
598	{
599	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
600	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
601	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
602	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
603	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
604	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
605	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
606	Assert( pCur2 == pCur
607	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
608	}
609	#endif
610
611	pCur = pVM->pgm.s.pRamRangesR3;
612	if (pCur)
613	{
614	pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
615	pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
616
617	for (; pCur->pNextR3; pCur = pCur->pNextR3)
618	{
619	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
620	pCur->pNextRC = pCur->pNextR3->pSelfRC;
621	}
622
623	Assert(pCur->pNextR0 == NIL_RTR0PTR);
624	Assert(pCur->pNextRC == NIL_RTRCPTR);
625	}
626	else
627	{
628	Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
629	Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
630	}
631	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
632	}
633
634
635	/**
636	* Links a new RAM range into the list.
637	*
638	* @param pVM Pointer to the shared VM structure.
639	* @param pNew Pointer to the new list entry.
640	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
641	*/
642	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
643	{
644	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
645	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
646	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
647
648	pgmLock(pVM);
649
650	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
651	pNew->pNextR3 = pRam;
652	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
653	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
654
655	if (pPrev)
656	{
657	pPrev->pNextR3 = pNew;
658	pPrev->pNextR0 = pNew->pSelfR0;
659	pPrev->pNextRC = pNew->pSelfRC;
660	}
661	else
662	{
663	pVM->pgm.s.pRamRangesR3 = pNew;
664	pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
665	pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
666	}
667	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
668	pgmUnlock(pVM);
669	}
670
671
672	/**
673	* Unlink an existing RAM range from the list.
674	*
675	* @param pVM Pointer to the shared VM structure.
676	* @param pRam Pointer to the new list entry.
677	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
678	*/
679	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
680	{
681	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
682	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
683	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
684
685	pgmLock(pVM);
686
687	PPGMRAMRANGE pNext = pRam->pNextR3;
688	if (pPrev)
689	{
690	pPrev->pNextR3 = pNext;
691	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
692	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
693	}
694	else
695	{
696	Assert(pVM->pgm.s.pRamRangesR3 == pRam);
697	pVM->pgm.s.pRamRangesR3 = pNext;
698	pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
699	pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
700	}
701	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
702	pgmUnlock(pVM);
703	}
704
705
706	/**
707	* Unlink an existing RAM range from the list.
708	*
709	* @param pVM Pointer to the shared VM structure.
710	* @param pRam Pointer to the new list entry.
711	*/
712	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
713	{
714	pgmLock(pVM);
715
716	/* find prev. */
717	PPGMRAMRANGE pPrev = NULL;
718	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
719	while (pCur != pRam)
720	{
721	pPrev = pCur;
722	pCur = pCur->pNextR3;
723	}
724	AssertFatal(pCur);
725
726	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
727	pgmUnlock(pVM);
728	}
729
730
731	/**
732	* Frees a range of pages, replacing them with ZERO pages of the specified type.
733	*
734	* @returns VBox status code.
735	* @param pVM The VM handle.
736	* @param pRam The RAM range in which the pages resides.
737	* @param GCPhys The address of the first page.
738	* @param GCPhysLast The address of the last page.
739	* @param uType The page type to replace then with.
740	*/
741	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
742	{
743	Assert(PGMIsLockOwner(pVM));
744	uint32_t cPendingPages = 0;
745	PGMMFREEPAGESREQ pReq;
746	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
747	AssertLogRelRCReturn(rc, rc);
748
749	/* Iterate the pages. */
750	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
751	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
752	while (cPagesLeft-- > 0)
753	{
754	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
755	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
756
757	PGM_PAGE_SET_TYPE(pPageDst, uType);
758
759	GCPhys += PAGE_SIZE;
760	pPageDst++;
761	}
762
763	if (cPendingPages)
764	{
765	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
766	AssertLogRelRCReturn(rc, rc);
767	}
768	GMMR3FreePagesCleanup(pReq);
769
770	return rc;
771	}
772
773	/**
774	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
775	*
776	* This is only called on one of the EMTs while the other ones are waiting for
777	* it to complete this function.
778	*
779	* @returns VINF_SUCCESS (VBox strict status code).
780	* @param pVM The VM handle.
781	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
782	* @param pvUser User parameter
783	*/
784	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
785	{
786	uintptr_t paUser = (uintptr_t )pvUser;
787	bool fInflate = !!paUser[0];
788	unsigned cPages = paUser[1];
789	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
790	uint32_t cPendingPages = 0;
791	PGMMFREEPAGESREQ pReq;
792	int rc;
793
794	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
795	pgmLock(pVM);
796
797	if (fInflate)
798	{
799	/* Replace pages with ZERO pages. */
800	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
801	if (RT_FAILURE(rc))
802	{
803	pgmUnlock(pVM);
804	AssertLogRelRC(rc);
805	return rc;
806	}
807
808	/* Iterate the pages. */
809	for (unsigned i = 0; i < cPages; i++)
810	{
811	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
812	if ( pPage == NULL
813	\|\| pPage->uTypeY != PGMPAGETYPE_RAM)
814	{
815	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], (pPage) ? pPage->uTypeY : 0));
816	break;
817	}
818
819	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
820
821	/* Flush the shadow PT if this page was previously used as a guest page table. */
822	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
823
824	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i]);
825	if (RT_FAILURE(rc))
826	{
827	pgmUnlock(pVM);
828	AssertLogRelRC(rc);
829	return rc;
830	}
831	Assert(PGM_PAGE_IS_ZERO(pPage));
832	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_BALLOONED);
833	}
834
835	if (cPendingPages)
836	{
837	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
838	if (RT_FAILURE(rc))
839	{
840	pgmUnlock(pVM);
841	AssertLogRelRC(rc);
842	return rc;
843	}
844	}
845	GMMR3FreePagesCleanup(pReq);
846
847	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
848	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
849	}
850	else
851	{
852	/* Iterate the pages. */
853	for (unsigned i = 0; i < cPages; i++)
854	{
855	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
856	AssertBreak(pPage && pPage->uTypeY == PGMPAGETYPE_RAM);
857
858	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
859
860	Assert(PGM_PAGE_IS_BALLOONED(pPage));
861
862	/* Change back to zero page. */
863	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
864	}
865
866	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
867	}
868
869	/* Notify GMM about the balloon change. */
870	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
871	if (RT_SUCCESS(rc))
872	{
873	if (!fInflate)
874	{
875	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
876	pVM->pgm.s.cBalloonedPages -= cPages;
877	}
878	else
879	pVM->pgm.s.cBalloonedPages += cPages;
880	}
881
882	pgmUnlock(pVM);
883
884	/* Flush the recompiler's TLB as well. */
885	for (unsigned i = 0; i < pVM->cCpus; i++)
886	CPUMSetChangedFlags(&pVM->aCpus[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
887
888	AssertLogRelRC(rc);
889	return rc;
890	}
891
892	/**
893	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
894	*
895	* @returns VBox status code.
896	* @param pVM The VM handle.
897	* @param fInflate Inflate or deflate memory balloon
898	* @param cPages Number of pages to free
899	* @param paPhysPage Array of guest physical addresses
900	*/
901	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
902	{
903	uintptr_t paUser[3];
904
905	paUser[0] = fInflate;
906	paUser[1] = cPages;
907	paUser[2] = (uintptr_t)paPhysPage;
908	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
909	AssertRC(rc);
910
911	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
912	RTMemFree(paPhysPage);
913	}
914
915	/**
916	* Inflate or deflate a memory balloon
917	*
918	* @returns VBox status code.
919	* @param pVM The VM handle.
920	* @param fInflate Inflate or deflate memory balloon
921	* @param cPages Number of pages to free
922	* @param paPhysPage Array of guest physical addresses
923	*/
924	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
925	{
926	int rc;
927
928	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
929	* In the SMP case we post a request packet to postpone the job.
930	*/
931	if (pVM->cCpus > 1)
932	{
933	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
934	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
935	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
936
937	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
938
939	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
940	AssertRC(rc);
941	}
942	else
943	{
944	uintptr_t paUser[3];
945
946	paUser[0] = fInflate;
947	paUser[1] = cPages;
948	paUser[2] = (uintptr_t)paPhysPage;
949	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
950	AssertRC(rc);
951	}
952	return rc;
953	}
954
955
956	/**
957	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
958	*
959	* @param pVM The VM handle.
960	* @param pNew The new RAM range.
961	* @param GCPhys The address of the RAM range.
962	* @param GCPhysLast The last address of the RAM range.
963	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
964	* if in HMA.
965	* @param R0PtrNew Ditto for R0.
966	* @param pszDesc The description.
967	* @param pPrev The previous RAM range (for linking).
968	*/
969	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
970	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
971	{
972	/*
973	* Initialize the range.
974	*/
975	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
976	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
977	pNew->GCPhys = GCPhys;
978	pNew->GCPhysLast = GCPhysLast;
979	pNew->cb = GCPhysLast - GCPhys + 1;
980	pNew->pszDesc = pszDesc;
981	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
982	pNew->pvR3 = NULL;
983	pNew->paLSPages = NULL;
984
985	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
986	RTGCPHYS iPage = cPages;
987	while (iPage-- > 0)
988	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
989
990	/* Update the page count stats. */
991	pVM->pgm.s.cZeroPages += cPages;
992	pVM->pgm.s.cAllPages += cPages;
993
994	/*
995	* Link it.
996	*/
997	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
998	}
999
1000
1001	/**
1002	* Relocate a floating RAM range.
1003	*
1004	* @copydoc FNPGMRELOCATE.
1005	*/
1006	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
1007	{
1008	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
1009	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
1010	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
1011
1012	switch (enmMode)
1013	{
1014	case PGMRELOCATECALL_SUGGEST:
1015	return true;
1016	case PGMRELOCATECALL_RELOCATE:
1017	{
1018	/* Update myself and then relink all the ranges. */
1019	pgmLock(pVM);
1020	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
1021	pgmR3PhysRelinkRamRanges(pVM);
1022	pgmUnlock(pVM);
1023	return true;
1024	}
1025
1026	default:
1027	AssertFailedReturn(false);
1028	}
1029	}
1030
1031
1032	/**
1033	* PGMR3PhysRegisterRam worker that registers a high chunk.
1034	*
1035	* @returns VBox status code.
1036	* @param pVM The VM handle.
1037	* @param GCPhys The address of the RAM.
1038	* @param cRamPages The number of RAM pages to register.
1039	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1040	* @param iChunk The chunk number.
1041	* @param pszDesc The RAM range description.
1042	* @param ppPrev Previous RAM range pointer. In/Out.
1043	*/
1044	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1045	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1046	PPGMRAMRANGE *ppPrev)
1047	{
1048	const char *pszDescChunk = iChunk == 0
1049	? pszDesc
1050	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1051	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1052
1053	/*
1054	* Allocate memory for the new chunk.
1055	*/
1056	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1057	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1058	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1059	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1060	void *pvChunk = NULL;
1061	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
1062	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1063	VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
1064	#else
1065	NULL,
1066	#endif
1067	paChunkPages);
1068	if (RT_SUCCESS(rc))
1069	{
1070	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1071	if (!VMMIsHwVirtExtForced(pVM))
1072	R0PtrChunk = NIL_RTR0PTR;
1073	#else
1074	R0PtrChunk = (uintptr_t)pvChunk;
1075	#endif
1076	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1077
1078	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1079
1080	/*
1081	* Create a mapping and map the pages into it.
1082	* We push these in below the HMA.
1083	*/
1084	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1085	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1086	if (RT_SUCCESS(rc))
1087	{
1088	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1089
1090	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1091	RTGCPTR GCPtrPage = GCPtrChunk;
1092	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1093	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1094	if (RT_SUCCESS(rc))
1095	{
1096	/*
1097	* Ok, init and link the range.
1098	*/
1099	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1100	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1101	*ppPrev = pNew;
1102	}
1103	}
1104
1105	if (RT_FAILURE(rc))
1106	SUPR3PageFreeEx(pvChunk, cChunkPages);
1107	}
1108
1109	RTMemTmpFree(paChunkPages);
1110	return rc;
1111	}
1112
1113
1114	/**
1115	* Sets up a range RAM.
1116	*
1117	* This will check for conflicting registrations, make a resource
1118	* reservation for the memory (with GMM), and setup the per-page
1119	* tracking structures (PGMPAGE).
1120	*
1121	* @returns VBox stutus code.
1122	* @param pVM Pointer to the shared VM structure.
1123	* @param GCPhys The physical address of the RAM.
1124	* @param cb The size of the RAM.
1125	* @param pszDesc The description - not copied, so, don't free or change it.
1126	*/
1127	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1128	{
1129	/*
1130	* Validate input.
1131	*/
1132	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1133	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1134	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1135	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1136	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1137	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1138	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1139	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1140
1141	pgmLock(pVM);
1142
1143	/*
1144	* Find range location and check for conflicts.
1145	* (We don't lock here because the locking by EMT is only required on update.)
1146	*/
1147	PPGMRAMRANGE pPrev = NULL;
1148	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1149	while (pRam && GCPhysLast >= pRam->GCPhys)
1150	{
1151	if ( GCPhysLast >= pRam->GCPhys
1152	&& GCPhys <= pRam->GCPhysLast)
1153	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1154	GCPhys, GCPhysLast, pszDesc,
1155	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1156	VERR_PGM_RAM_CONFLICT);
1157
1158	/* next */
1159	pPrev = pRam;
1160	pRam = pRam->pNextR3;
1161	}
1162
1163	/*
1164	* Register it with GMM (the API bitches).
1165	*/
1166	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1167	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1168	if (RT_FAILURE(rc))
1169	{
1170	pgmUnlock(pVM);
1171	return rc;
1172	}
1173
1174	if ( GCPhys >= _4G
1175	&& cPages > 256)
1176	{
1177	/*
1178	* The PGMRAMRANGE structures for the high memory can get very big.
1179	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1180	* allocation size limit there and also to avoid being unable to find
1181	* guest mapping space for them, we split this memory up into 4MB in
1182	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1183	* mode.
1184	*
1185	* The first and last page of each mapping are guard pages and marked
1186	* not-present. So, we've got 4186112 and 16769024 bytes available for
1187	* the PGMRAMRANGE structure.
1188	*
1189	* Note! The sizes used here will influence the saved state.
1190	*/
1191	uint32_t cbChunk;
1192	uint32_t cPagesPerChunk;
1193	if (VMMIsHwVirtExtForced(pVM))
1194	{
1195	cbChunk = 16U*_1M;
1196	cPagesPerChunk = 1048048; /* max ~1048059 */
1197	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1198	}
1199	else
1200	{
1201	cbChunk = 4U*_1M;
1202	cPagesPerChunk = 261616; /* max ~261627 */
1203	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1204	}
1205	AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1206
1207	RTGCPHYS cPagesLeft = cPages;
1208	RTGCPHYS GCPhysChunk = GCPhys;
1209	uint32_t iChunk = 0;
1210	while (cPagesLeft > 0)
1211	{
1212	uint32_t cPagesInChunk = cPagesLeft;
1213	if (cPagesInChunk > cPagesPerChunk)
1214	cPagesInChunk = cPagesPerChunk;
1215
1216	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1217	AssertRCReturn(rc, rc);
1218
1219	/* advance */
1220	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1221	cPagesLeft -= cPagesInChunk;
1222	iChunk++;
1223	}
1224	}
1225	else
1226	{
1227	/*
1228	* Allocate, initialize and link the new RAM range.
1229	*/
1230	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1231	PPGMRAMRANGE pNew;
1232	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1233	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1234
1235	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1236	}
1237	PGMPhysInvalidatePageMapTLB(pVM);
1238	pgmUnlock(pVM);
1239
1240	/*
1241	* Notify REM.
1242	*/
1243	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1244
1245	return VINF_SUCCESS;
1246	}
1247
1248
1249	/**
1250	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1251	*
1252	* We do this late in the init process so that all the ROM and MMIO ranges have
1253	* been registered already and we don't go wasting memory on them.
1254	*
1255	* @returns VBox status code.
1256	*
1257	* @param pVM Pointer to the shared VM structure.
1258	*/
1259	int pgmR3PhysRamPreAllocate(PVM pVM)
1260	{
1261	Assert(pVM->pgm.s.fRamPreAlloc);
1262	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1263
1264	/*
1265	* Walk the RAM ranges and allocate all RAM pages, halt at
1266	* the first allocation error.
1267	*/
1268	uint64_t cPages = 0;
1269	uint64_t NanoTS = RTTimeNanoTS();
1270	pgmLock(pVM);
1271	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1272	{
1273	PPGMPAGE pPage = &pRam->aPages[0];
1274	RTGCPHYS GCPhys = pRam->GCPhys;
1275	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1276	while (cLeft-- > 0)
1277	{
1278	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1279	{
1280	switch (PGM_PAGE_GET_STATE(pPage))
1281	{
1282	case PGM_PAGE_STATE_ZERO:
1283	{
1284	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1285	if (RT_FAILURE(rc))
1286	{
1287	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1288	pgmUnlock(pVM);
1289	return rc;
1290	}
1291	cPages++;
1292	break;
1293	}
1294
1295	case PGM_PAGE_STATE_BALLOONED:
1296	case PGM_PAGE_STATE_ALLOCATED:
1297	case PGM_PAGE_STATE_WRITE_MONITORED:
1298	case PGM_PAGE_STATE_SHARED:
1299	/* nothing to do here. */
1300	break;
1301	}
1302	}
1303
1304	/* next */
1305	pPage++;
1306	GCPhys += PAGE_SIZE;
1307	}
1308	}
1309	pgmUnlock(pVM);
1310	NanoTS = RTTimeNanoTS() - NanoTS;
1311
1312	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1313	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1314	return VINF_SUCCESS;
1315	}
1316
1317
1318	/**
1319	* Resets (zeros) the RAM.
1320	*
1321	* ASSUMES that the caller owns the PGM lock.
1322	*
1323	* @returns VBox status code.
1324	* @param pVM Pointer to the shared VM structure.
1325	*/
1326	int pgmR3PhysRamReset(PVM pVM)
1327	{
1328	Assert(PGMIsLockOwner(pVM));
1329
1330	/* Reset the memory balloon. */
1331	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1332	AssertRC(rc);
1333
1334	/*
1335	* We batch up pages that should be freed instead of calling GMM for
1336	* each and every one of them.
1337	*/
1338	uint32_t cPendingPages = 0;
1339	PGMMFREEPAGESREQ pReq;
1340	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1341	AssertLogRelRCReturn(rc, rc);
1342
1343	/*
1344	* Walk the ram ranges.
1345	*/
1346	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1347	{
1348	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1349	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1350
1351	if (!pVM->pgm.s.fRamPreAlloc)
1352	{
1353	/* Replace all RAM pages by ZERO pages. */
1354	while (iPage-- > 0)
1355	{
1356	PPGMPAGE pPage = &pRam->aPages[iPage];
1357	switch (PGM_PAGE_GET_TYPE(pPage))
1358	{
1359	case PGMPAGETYPE_RAM:
1360	/* Do not replace pages part of a 2 MB continuous range with zero pages, but zero them instead. */
1361	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
1362	{
1363	void *pvPage;
1364	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1365	AssertLogRelRCReturn(rc, rc);
1366	ASMMemZeroPage(pvPage);
1367	}
1368	else
1369	if (PGM_PAGE_IS_BALLOONED(pPage))
1370	{
1371	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1372	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
1373	}
1374	else
1375	if (!PGM_PAGE_IS_ZERO(pPage))
1376	{
1377	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1378	AssertLogRelRCReturn(rc, rc);
1379	}
1380	break;
1381
1382	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1383	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1384	break;
1385
1386	case PGMPAGETYPE_MMIO2:
1387	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1388	case PGMPAGETYPE_ROM:
1389	case PGMPAGETYPE_MMIO:
1390	break;
1391	default:
1392	AssertFailed();
1393	}
1394	} /* for each page */
1395	}
1396	else
1397	{
1398	/* Zero the memory. */
1399	while (iPage-- > 0)
1400	{
1401	PPGMPAGE pPage = &pRam->aPages[iPage];
1402	switch (PGM_PAGE_GET_TYPE(pPage))
1403	{
1404	case PGMPAGETYPE_RAM:
1405	switch (PGM_PAGE_GET_STATE(pPage))
1406	{
1407	case PGM_PAGE_STATE_ZERO:
1408	break;
1409
1410	case PGM_PAGE_STATE_BALLOONED:
1411	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1412	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
1413	break;
1414
1415	case PGM_PAGE_STATE_SHARED:
1416	case PGM_PAGE_STATE_WRITE_MONITORED:
1417	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1418	AssertLogRelRCReturn(rc, rc);
1419	/* no break */
1420
1421	case PGM_PAGE_STATE_ALLOCATED:
1422	{
1423	void *pvPage;
1424	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1425	AssertLogRelRCReturn(rc, rc);
1426	ASMMemZeroPage(pvPage);
1427	break;
1428	}
1429	}
1430	break;
1431
1432	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1433	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1434	break;
1435
1436	case PGMPAGETYPE_MMIO2:
1437	case PGMPAGETYPE_ROM_SHADOW:
1438	case PGMPAGETYPE_ROM:
1439	case PGMPAGETYPE_MMIO:
1440	break;
1441	default:
1442	AssertFailed();
1443
1444	}
1445	} /* for each page */
1446	}
1447
1448	}
1449
1450	/*
1451	* Finish off any pages pending freeing.
1452	*/
1453	if (cPendingPages)
1454	{
1455	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1456	AssertLogRelRCReturn(rc, rc);
1457	}
1458	GMMR3FreePagesCleanup(pReq);
1459
1460	return VINF_SUCCESS;
1461	}
1462
1463
1464	/**
1465	* This is the interface IOM is using to register an MMIO region.
1466	*
1467	* It will check for conflicts and ensure that a RAM range structure
1468	* is present before calling the PGMR3HandlerPhysicalRegister API to
1469	* register the callbacks.
1470	*
1471	* @returns VBox status code.
1472	*
1473	* @param pVM Pointer to the shared VM structure.
1474	* @param GCPhys The start of the MMIO region.
1475	* @param cb The size of the MMIO region.
1476	* @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1477	* @param pvUserR3 The user argument for R3.
1478	* @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1479	* @param pvUserR0 The user argument for R0.
1480	* @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1481	* @param pvUserRC The user argument for RC.
1482	* @param pszDesc The description of the MMIO region.
1483	*/
1484	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1485	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1486	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1487	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1488	R3PTRTYPE(const char *) pszDesc)
1489	{
1490	/*
1491	* Assert on some assumption.
1492	*/
1493	VM_ASSERT_EMT(pVM);
1494	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1495	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1496	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1497	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1498
1499	/*
1500	* Make sure there's a RAM range structure for the region.
1501	*/
1502	int rc;
1503	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1504	bool fRamExists = false;
1505	PPGMRAMRANGE pRamPrev = NULL;
1506	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1507	while (pRam && GCPhysLast >= pRam->GCPhys)
1508	{
1509	if ( GCPhysLast >= pRam->GCPhys
1510	&& GCPhys <= pRam->GCPhysLast)
1511	{
1512	/* Simplification: all within the same range. */
1513	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1514	&& GCPhysLast <= pRam->GCPhysLast,
1515	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1516	GCPhys, GCPhysLast, pszDesc,
1517	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1518	VERR_PGM_RAM_CONFLICT);
1519
1520	/* Check that it's all RAM or MMIO pages. */
1521	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1522	uint32_t cLeft = cb >> PAGE_SHIFT;
1523	while (cLeft-- > 0)
1524	{
1525	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1526	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1527	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1528	GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1529	VERR_PGM_RAM_CONFLICT);
1530	pPage++;
1531	}
1532
1533	/* Looks good. */
1534	fRamExists = true;
1535	break;
1536	}
1537
1538	/* next */
1539	pRamPrev = pRam;
1540	pRam = pRam->pNextR3;
1541	}
1542	PPGMRAMRANGE pNew;
1543	if (fRamExists)
1544	{
1545	pNew = NULL;
1546
1547	/*
1548	* Make all the pages in the range MMIO/ZERO pages, freeing any
1549	* RAM pages currently mapped here. This might not be 100% correct
1550	* for PCI memory, but we're doing the same thing for MMIO2 pages.
1551	*/
1552	rc = pgmLock(pVM);
1553	if (RT_SUCCESS(rc))
1554	{
1555	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1556	pgmUnlock(pVM);
1557	}
1558	AssertRCReturn(rc, rc);
1559	}
1560	else
1561	{
1562	pgmLock(pVM);
1563
1564	/*
1565	* No RAM range, insert an ad hoc one.
1566	*
1567	* Note that we don't have to tell REM about this range because
1568	* PGMHandlerPhysicalRegisterEx will do that for us.
1569	*/
1570	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1571
1572	const uint32_t cPages = cb >> PAGE_SHIFT;
1573	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1574	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1575	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1576
1577	/* Initialize the range. */
1578	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1579	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1580	pNew->GCPhys = GCPhys;
1581	pNew->GCPhysLast = GCPhysLast;
1582	pNew->cb = cb;
1583	pNew->pszDesc = pszDesc;
1584	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
1585	pNew->pvR3 = NULL;
1586	pNew->paLSPages = NULL;
1587
1588	uint32_t iPage = cPages;
1589	while (iPage-- > 0)
1590	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1591	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1592
1593	/* update the page count stats. */
1594	pVM->pgm.s.cPureMmioPages += cPages;
1595	pVM->pgm.s.cAllPages += cPages;
1596
1597	/* link it */
1598	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1599
1600	pgmUnlock(pVM);
1601	}
1602
1603	/*
1604	* Register the access handler.
1605	*/
1606	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1607	pfnHandlerR3, pvUserR3,
1608	pfnHandlerR0, pvUserR0,
1609	pfnHandlerRC, pvUserRC, pszDesc);
1610	if ( RT_FAILURE(rc)
1611	&& !fRamExists)
1612	{
1613	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
1614	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1615
1616	/* remove the ad hoc range. */
1617	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1618	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1619	MMHyperFree(pVM, pRam);
1620	}
1621	PGMPhysInvalidatePageMapTLB(pVM);
1622
1623	return rc;
1624	}
1625
1626
1627	/**
1628	* This is the interface IOM is using to register an MMIO region.
1629	*
1630	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
1631	* any ad hoc PGMRAMRANGE left behind.
1632	*
1633	* @returns VBox status code.
1634	* @param pVM Pointer to the shared VM structure.
1635	* @param GCPhys The start of the MMIO region.
1636	* @param cb The size of the MMIO region.
1637	*/
1638	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1639	{
1640	VM_ASSERT_EMT(pVM);
1641
1642	/*
1643	* First deregister the handler, then check if we should remove the ram range.
1644	*/
1645	int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1646	if (RT_SUCCESS(rc))
1647	{
1648	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1649	PPGMRAMRANGE pRamPrev = NULL;
1650	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1651	while (pRam && GCPhysLast >= pRam->GCPhys)
1652	{
1653	/** @todo We're being a bit too careful here. rewrite. */
1654	if ( GCPhysLast == pRam->GCPhysLast
1655	&& GCPhys == pRam->GCPhys)
1656	{
1657	Assert(pRam->cb == cb);
1658
1659	/*
1660	* See if all the pages are dead MMIO pages.
1661	*/
1662	uint32_t const cPages = cb >> PAGE_SHIFT;
1663	bool fAllMMIO = true;
1664	uint32_t iPage = 0;
1665	uint32_t cLeft = cPages;
1666	while (cLeft-- > 0)
1667	{
1668	PPGMPAGE pPage = &pRam->aPages[iPage];
1669	if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1670	/\|\| not-out-of-action later /)
1671	{
1672	fAllMMIO = false;
1673	Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1674	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1675	break;
1676	}
1677	Assert(PGM_PAGE_IS_ZERO(pPage));
1678	pPage++;
1679	}
1680	if (fAllMMIO)
1681	{
1682	/*
1683	* Ad-hoc range, unlink and free it.
1684	*/
1685	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
1686	GCPhys, GCPhysLast, pRam->pszDesc));
1687
1688	pVM->pgm.s.cAllPages -= cPages;
1689	pVM->pgm.s.cPureMmioPages -= cPages;
1690
1691	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1692	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1693	MMHyperFree(pVM, pRam);
1694	break;
1695	}
1696	}
1697
1698	/*
1699	* Range match? It will all be within one range (see PGMAllHandler.cpp).
1700	*/
1701	if ( GCPhysLast >= pRam->GCPhys
1702	&& GCPhys <= pRam->GCPhysLast)
1703	{
1704	Assert(GCPhys >= pRam->GCPhys);
1705	Assert(GCPhysLast <= pRam->GCPhysLast);
1706
1707	/*
1708	* Turn the pages back into RAM pages.
1709	*/
1710	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1711	uint32_t cLeft = cb >> PAGE_SHIFT;
1712	while (cLeft--)
1713	{
1714	PPGMPAGE pPage = &pRam->aPages[iPage];
1715	AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1716	AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1717	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1718	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1719	}
1720	break;
1721	}
1722
1723	/* next */
1724	pRamPrev = pRam;
1725	pRam = pRam->pNextR3;
1726	}
1727	}
1728
1729	PGMPhysInvalidatePageMapTLB(pVM);
1730	return rc;
1731	}
1732
1733
1734	/**
1735	* Locate a MMIO2 range.
1736	*
1737	* @returns Pointer to the MMIO2 range.
1738	* @param pVM Pointer to the shared VM structure.
1739	* @param pDevIns The device instance owning the region.
1740	* @param iRegion The region.
1741	*/
1742	DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1743	{
1744	/*
1745	* Search the list.
1746	*/
1747	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1748	if ( pCur->pDevInsR3 == pDevIns
1749	&& pCur->iRegion == iRegion)
1750	return pCur;
1751	return NULL;
1752	}
1753
1754
1755	/**
1756	* Allocate and register an MMIO2 region.
1757	*
1758	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1759	* RAM associated with a device. It is also non-shared memory with a
1760	* permanent ring-3 mapping and page backing (presently).
1761	*
1762	* A MMIO2 range may overlap with base memory if a lot of RAM
1763	* is configured for the VM, in which case we'll drop the base
1764	* memory pages. Presently we will make no attempt to preserve
1765	* anything that happens to be present in the base memory that
1766	* is replaced, this is of course incorrectly but it's too much
1767	* effort.
1768	*
1769	* @returns VBox status code.
1770	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1771	* @retval VERR_ALREADY_EXISTS if the region already exists.
1772	*
1773	* @param pVM Pointer to the shared VM structure.
1774	* @param pDevIns The device instance owning the region.
1775	* @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1776	* this number has to be the number of that region. Otherwise
1777	* it can be any number safe UINT8_MAX.
1778	* @param cb The size of the region. Must be page aligned.
1779	* @param fFlags Reserved for future use, must be zero.
1780	* @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1781	* @param pszDesc The description.
1782	*/
1783	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc)
1784	{
1785	/*
1786	* Validate input.
1787	*/
1788	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1789	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1790	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1791	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1792	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1793	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1794	AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1795	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1796	AssertReturn(cb, VERR_INVALID_PARAMETER);
1797	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1798
1799	const uint32_t cPages = cb >> PAGE_SHIFT;
1800	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1801	AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1802
1803	/*
1804	* For the 2nd+ instance, mangle the description string so it's unique.
1805	*/
1806	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
1807	{
1808	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1809	if (!pszDesc)
1810	return VERR_NO_MEMORY;
1811	}
1812
1813	/*
1814	* Try reserve and allocate the backing memory first as this is what is
1815	* most likely to fail.
1816	*/
1817	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1818	if (RT_SUCCESS(rc))
1819	{
1820	void *pvPages;
1821	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1822	if (RT_SUCCESS(rc))
1823	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
1824	if (RT_SUCCESS(rc))
1825	{
1826	memset(pvPages, 0, cPages * PAGE_SIZE);
1827
1828	/*
1829	* Create the MMIO2 range record for it.
1830	*/
1831	const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1832	PPGMMMIO2RANGE pNew;
1833	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1834	AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1835	if (RT_SUCCESS(rc))
1836	{
1837	pNew->pDevInsR3 = pDevIns;
1838	pNew->pvR3 = pvPages;
1839	//pNew->pNext = NULL;
1840	//pNew->fMapped = false;
1841	//pNew->fOverlapping = false;
1842	pNew->iRegion = iRegion;
1843	pNew->idSavedState = UINT8_MAX;
1844	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1845	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1846	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1847	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1848	pNew->RamRange.pszDesc = pszDesc;
1849	pNew->RamRange.cb = cb;
1850	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
1851	pNew->RamRange.pvR3 = pvPages;
1852	//pNew->RamRange.paLSPages = NULL;
1853
1854	uint32_t iPage = cPages;
1855	while (iPage-- > 0)
1856	{
1857	PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1858	paPages[iPage].Phys, NIL_GMM_PAGEID,
1859	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1860	}
1861
1862	/* update page count stats */
1863	pVM->pgm.s.cAllPages += cPages;
1864	pVM->pgm.s.cPrivatePages += cPages;
1865
1866	/*
1867	* Link it into the list.
1868	* Since there is no particular order, just push it.
1869	*/
1870	pgmLock(pVM);
1871	pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1872	pVM->pgm.s.pMmio2RangesR3 = pNew;
1873	pgmUnlock(pVM);
1874
1875	*ppv = pvPages;
1876	RTMemTmpFree(paPages);
1877	PGMPhysInvalidatePageMapTLB(pVM);
1878	return VINF_SUCCESS;
1879	}
1880
1881	SUPR3PageFreeEx(pvPages, cPages);
1882	}
1883	RTMemTmpFree(paPages);
1884	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1885	}
1886	if (pDevIns->iInstance > 0)
1887	MMR3HeapFree((void *)pszDesc);
1888	return rc;
1889	}
1890
1891
1892	/**
1893	* Deregisters and frees an MMIO2 region.
1894	*
1895	* Any physical (and virtual) access handlers registered for the region must
1896	* be deregistered before calling this function.
1897	*
1898	* @returns VBox status code.
1899	* @param pVM Pointer to the shared VM structure.
1900	* @param pDevIns The device instance owning the region.
1901	* @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1902	*/
1903	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1904	{
1905	/*
1906	* Validate input.
1907	*/
1908	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1909	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1910	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1911
1912	pgmLock(pVM);
1913	int rc = VINF_SUCCESS;
1914	unsigned cFound = 0;
1915	PPGMMMIO2RANGE pPrev = NULL;
1916	PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1917	while (pCur)
1918	{
1919	if ( pCur->pDevInsR3 == pDevIns
1920	&& ( iRegion == UINT32_MAX
1921	\|\| pCur->iRegion == iRegion))
1922	{
1923	cFound++;
1924
1925	/*
1926	* Unmap it if it's mapped.
1927	*/
1928	if (pCur->fMapped)
1929	{
1930	int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1931	AssertRC(rc2);
1932	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1933	rc = rc2;
1934	}
1935
1936	/*
1937	* Unlink it
1938	*/
1939	PPGMMMIO2RANGE pNext = pCur->pNextR3;
1940	if (pPrev)
1941	pPrev->pNextR3 = pNext;
1942	else
1943	pVM->pgm.s.pMmio2RangesR3 = pNext;
1944	pCur->pNextR3 = NULL;
1945
1946	/*
1947	* Free the memory.
1948	*/
1949	int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1950	AssertRC(rc2);
1951	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1952	rc = rc2;
1953
1954	uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1955	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1956	AssertRC(rc2);
1957	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1958	rc = rc2;
1959
1960	/* we're leaking hyper memory here if done at runtime. */
1961	#ifdef VBOX_STRICT
1962	VMSTATE const enmState = VMR3GetState(pVM);
1963	AssertMsg( enmState == VMSTATE_POWERING_OFF
1964	\|\| enmState == VMSTATE_POWERING_OFF_LS
1965	\|\| enmState == VMSTATE_OFF
1966	\|\| enmState == VMSTATE_OFF_LS
1967	\|\| enmState == VMSTATE_DESTROYING
1968	\|\| enmState == VMSTATE_TERMINATED
1969	\|\| enmState == VMSTATE_CREATING
1970	, ("%s\n", VMR3GetStateName(enmState)));
1971	#endif
1972	/*rc = MMHyperFree(pVM, pCur);
1973	AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1974
1975
1976	/* update page count stats */
1977	pVM->pgm.s.cAllPages -= cPages;
1978	pVM->pgm.s.cPrivatePages -= cPages;
1979
1980	/* next */
1981	pCur = pNext;
1982	}
1983	else
1984	{
1985	pPrev = pCur;
1986	pCur = pCur->pNextR3;
1987	}
1988	}
1989	PGMPhysInvalidatePageMapTLB(pVM);
1990	pgmUnlock(pVM);
1991	return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1992	}
1993
1994
1995	/**
1996	* Maps a MMIO2 region.
1997	*
1998	* This is done when a guest / the bios / state loading changes the
1999	* PCI config. The replacing of base memory has the same restrictions
2000	* as during registration, of course.
2001	*
2002	* @returns VBox status code.
2003	*
2004	* @param pVM Pointer to the shared VM structure.
2005	* @param pDevIns The
2006	*/
2007	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2008	{
2009	/*
2010	* Validate input
2011	*/
2012	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2013	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2014	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2015	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2016	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2017	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2018
2019	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2020	AssertReturn(pCur, VERR_NOT_FOUND);
2021	AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
2022	Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
2023	Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
2024
2025	const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
2026	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2027
2028	/*
2029	* Find our location in the ram range list, checking for
2030	* restriction we don't bother implementing yet (partially overlapping).
2031	*/
2032	bool fRamExists = false;
2033	PPGMRAMRANGE pRamPrev = NULL;
2034	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2035	while (pRam && GCPhysLast >= pRam->GCPhys)
2036	{
2037	if ( GCPhys <= pRam->GCPhysLast
2038	&& GCPhysLast >= pRam->GCPhys)
2039	{
2040	/* completely within? */
2041	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2042	&& GCPhysLast <= pRam->GCPhysLast,
2043	("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
2044	GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
2045	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2046	VERR_PGM_RAM_CONFLICT);
2047	fRamExists = true;
2048	break;
2049	}
2050
2051	/* next */
2052	pRamPrev = pRam;
2053	pRam = pRam->pNextR3;
2054	}
2055	if (fRamExists)
2056	{
2057	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2058	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2059	while (cPagesLeft-- > 0)
2060	{
2061	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2062	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
2063	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
2064	VERR_PGM_RAM_CONFLICT);
2065	pPage++;
2066	}
2067	}
2068	Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
2069	GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
2070
2071	/*
2072	* Make the changes.
2073	*/
2074	pgmLock(pVM);
2075
2076	pCur->RamRange.GCPhys = GCPhys;
2077	pCur->RamRange.GCPhysLast = GCPhysLast;
2078	pCur->fMapped = true;
2079	pCur->fOverlapping = fRamExists;
2080
2081	if (fRamExists)
2082	{
2083	/** @todo use pgmR3PhysFreePageRange here. */
2084	uint32_t cPendingPages = 0;
2085	PGMMFREEPAGESREQ pReq;
2086	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2087	AssertLogRelRCReturn(rc, rc);
2088
2089	/* replace the pages, freeing all present RAM pages. */
2090	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2091	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2092	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2093	while (cPagesLeft-- > 0)
2094	{
2095	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
2096	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
2097
2098	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
2099	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
2100	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
2101	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
2102
2103	pVM->pgm.s.cZeroPages--;
2104	GCPhys += PAGE_SIZE;
2105	pPageSrc++;
2106	pPageDst++;
2107	}
2108
2109	/* Flush physical page map TLB. */
2110	PGMPhysInvalidatePageMapTLB(pVM);
2111
2112	if (cPendingPages)
2113	{
2114	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2115	AssertLogRelRCReturn(rc, rc);
2116	}
2117	GMMR3FreePagesCleanup(pReq);
2118	pgmUnlock(pVM);
2119	}
2120	else
2121	{
2122	RTGCPHYS cb = pCur->RamRange.cb;
2123
2124	/* link in the ram range */
2125	pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
2126	pgmUnlock(pVM);
2127
2128	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
2129	}
2130
2131	PGMPhysInvalidatePageMapTLB(pVM);
2132	return VINF_SUCCESS;
2133	}
2134
2135
2136	/**
2137	* Unmaps a MMIO2 region.
2138	*
2139	* This is done when a guest / the bios / state loading changes the
2140	* PCI config. The replacing of base memory has the same restrictions
2141	* as during registration, of course.
2142	*/
2143	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2144	{
2145	/*
2146	* Validate input
2147	*/
2148	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2149	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2150	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2151	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2152	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2153	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2154
2155	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2156	AssertReturn(pCur, VERR_NOT_FOUND);
2157	AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
2158	AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
2159	Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
2160
2161	Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
2162	pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
2163
2164	/*
2165	* Unmap it.
2166	*/
2167	pgmLock(pVM);
2168
2169	RTGCPHYS GCPhysRangeREM;
2170	RTGCPHYS cbRangeREM;
2171	bool fInformREM;
2172	if (pCur->fOverlapping)
2173	{
2174	/* Restore the RAM pages we've replaced. */
2175	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2176	while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
2177	pRam = pRam->pNextR3;
2178
2179	RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
2180	Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
2181	PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2182	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2183	while (cPagesLeft-- > 0)
2184	{
2185	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
2186	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
2187	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
2188	PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
2189	PGM_PAGE_SET_PDE_TYPE(pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
2190
2191	pVM->pgm.s.cZeroPages++;
2192	pPageDst++;
2193	}
2194
2195	/* Flush physical page map TLB. */
2196	PGMPhysInvalidatePageMapTLB(pVM);
2197
2198	GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
2199	cbRangeREM = RTGCPHYS_MAX; /* ditto */
2200	fInformREM = false;
2201	}
2202	else
2203	{
2204	GCPhysRangeREM = pCur->RamRange.GCPhys;
2205	cbRangeREM = pCur->RamRange.cb;
2206	fInformREM = true;
2207
2208	pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
2209	}
2210
2211	pCur->RamRange.GCPhys = NIL_RTGCPHYS;
2212	pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
2213	pCur->fOverlapping = false;
2214	pCur->fMapped = false;
2215
2216	PGMPhysInvalidatePageMapTLB(pVM);
2217	pgmUnlock(pVM);
2218
2219	if (fInformREM)
2220	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2221
2222	return VINF_SUCCESS;
2223	}
2224
2225
2226	/**
2227	* Checks if the given address is an MMIO2 base address or not.
2228	*
2229	* @returns true/false accordingly.
2230	* @param pVM Pointer to the shared VM structure.
2231	* @param pDevIns The owner of the memory, optional.
2232	* @param GCPhys The address to check.
2233	*/
2234	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2235	{
2236	/*
2237	* Validate input
2238	*/
2239	VM_ASSERT_EMT_RETURN(pVM, false);
2240	AssertPtrReturn(pDevIns, false);
2241	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
2242	AssertReturn(GCPhys != 0, false);
2243	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
2244
2245	/*
2246	* Search the list.
2247	*/
2248	pgmLock(pVM);
2249	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2250	if (pCur->RamRange.GCPhys == GCPhys)
2251	{
2252	Assert(pCur->fMapped);
2253	pgmUnlock(pVM);
2254	return true;
2255	}
2256	pgmUnlock(pVM);
2257	return false;
2258	}
2259
2260
2261	/**
2262	* Gets the HC physical address of a page in the MMIO2 region.
2263	*
2264	* This is API is intended for MMHyper and shouldn't be called
2265	* by anyone else...
2266	*
2267	* @returns VBox status code.
2268	* @param pVM Pointer to the shared VM structure.
2269	* @param pDevIns The owner of the memory, optional.
2270	* @param iRegion The region.
2271	* @param off The page expressed an offset into the MMIO2 region.
2272	* @param pHCPhys Where to store the result.
2273	*/
2274	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2275	{
2276	/*
2277	* Validate input
2278	*/
2279	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2280	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2281	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2282
2283	pgmLock(pVM);
2284	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2285	AssertReturn(pCur, VERR_NOT_FOUND);
2286	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2287
2288	PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2289	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2290	pgmUnlock(pVM);
2291	return VINF_SUCCESS;
2292	}
2293
2294
2295	/**
2296	* Maps a portion of an MMIO2 region into kernel space (host).
2297	*
2298	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
2299	* or the VM is terminated.
2300	*
2301	* @return VBox status code.
2302	*
2303	* @param pVM Pointer to the shared VM structure.
2304	* @param pDevIns The device owning the MMIO2 memory.
2305	* @param iRegion The region.
2306	* @param off The offset into the region. Must be page aligned.
2307	* @param cb The number of bytes to map. Must be page aligned.
2308	* @param pszDesc Mapping description.
2309	* @param pR0Ptr Where to store the R0 address.
2310	*/
2311	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2312	const char *pszDesc, PRTR0PTR pR0Ptr)
2313	{
2314	/*
2315	* Validate input.
2316	*/
2317	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2318	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2319	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2320
2321	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2322	AssertReturn(pCur, VERR_NOT_FOUND);
2323	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2324	AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2325	AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2326
2327	/*
2328	* Pass the request on to the support library/driver.
2329	*/
2330	int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2331
2332	return rc;
2333	}
2334
2335
2336	/**
2337	* Registers a ROM image.
2338	*
2339	* Shadowed ROM images requires double the amount of backing memory, so,
2340	* don't use that unless you have to. Shadowing of ROM images is process
2341	* where we can select where the reads go and where the writes go. On real
2342	* hardware the chipset provides means to configure this. We provide
2343	* PGMR3PhysProtectROM() for this purpose.
2344	*
2345	* A read-only copy of the ROM image will always be kept around while we
2346	* will allocate RAM pages for the changes on demand (unless all memory
2347	* is configured to be preallocated).
2348	*
2349	* @returns VBox status.
2350	* @param pVM VM Handle.
2351	* @param pDevIns The device instance owning the ROM.
2352	* @param GCPhys First physical address in the range.
2353	* Must be page aligned!
2354	* @param cbRange The size of the range (in bytes).
2355	* Must be page aligned!
2356	* @param pvBinary Pointer to the binary data backing the ROM image.
2357	* This must be exactly \a cbRange in size.
2358	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2359	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2360	* @param pszDesc Pointer to description string. This must not be freed.
2361	*
2362	* @remark There is no way to remove the rom, automatically on device cleanup or
2363	* manually from the device yet. This isn't difficult in any way, it's
2364	* just not something we expect to be necessary for a while.
2365	*/
2366	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2367	const void pvBinary, uint32_t fFlags, const char pszDesc)
2368	{
2369	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2370	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2371
2372	/*
2373	* Validate input.
2374	*/
2375	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2376	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2377	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2378	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2379	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2380	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2381	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2382	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2383	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2384
2385	const uint32_t cPages = cb >> PAGE_SHIFT;
2386
2387	/*
2388	* Find the ROM location in the ROM list first.
2389	*/
2390	PPGMROMRANGE pRomPrev = NULL;
2391	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2392	while (pRom && GCPhysLast >= pRom->GCPhys)
2393	{
2394	if ( GCPhys <= pRom->GCPhysLast
2395	&& GCPhysLast >= pRom->GCPhys)
2396	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2397	GCPhys, GCPhysLast, pszDesc,
2398	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2399	VERR_PGM_RAM_CONFLICT);
2400	/* next */
2401	pRomPrev = pRom;
2402	pRom = pRom->pNextR3;
2403	}
2404
2405	/*
2406	* Find the RAM location and check for conflicts.
2407	*
2408	* Conflict detection is a bit different than for RAM
2409	* registration since a ROM can be located within a RAM
2410	* range. So, what we have to check for is other memory
2411	* types (other than RAM that is) and that we don't span
2412	* more than one RAM range (layz).
2413	*/
2414	bool fRamExists = false;
2415	PPGMRAMRANGE pRamPrev = NULL;
2416	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2417	while (pRam && GCPhysLast >= pRam->GCPhys)
2418	{
2419	if ( GCPhys <= pRam->GCPhysLast
2420	&& GCPhysLast >= pRam->GCPhys)
2421	{
2422	/* completely within? */
2423	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2424	&& GCPhysLast <= pRam->GCPhysLast,
2425	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2426	GCPhys, GCPhysLast, pszDesc,
2427	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2428	VERR_PGM_RAM_CONFLICT);
2429	fRamExists = true;
2430	break;
2431	}
2432
2433	/* next */
2434	pRamPrev = pRam;
2435	pRam = pRam->pNextR3;
2436	}
2437	if (fRamExists)
2438	{
2439	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2440	uint32_t cPagesLeft = cPages;
2441	while (cPagesLeft-- > 0)
2442	{
2443	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2444	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2445	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2446	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2447	Assert(PGM_PAGE_IS_ZERO(pPage));
2448	pPage++;
2449	}
2450	}
2451
2452	/*
2453	* Update the base memory reservation if necessary.
2454	*/
2455	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
2456	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2457	cExtraBaseCost += cPages;
2458	if (cExtraBaseCost)
2459	{
2460	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2461	if (RT_FAILURE(rc))
2462	return rc;
2463	}
2464
2465	/*
2466	* Allocate memory for the virgin copy of the RAM.
2467	*/
2468	PGMMALLOCATEPAGESREQ pReq;
2469	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2470	AssertRCReturn(rc, rc);
2471
2472	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2473	{
2474	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2475	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2476	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2477	}
2478
2479	pgmLock(pVM);
2480	rc = GMMR3AllocatePagesPerform(pVM, pReq);
2481	pgmUnlock(pVM);
2482	if (RT_FAILURE(rc))
2483	{
2484	GMMR3AllocatePagesCleanup(pReq);
2485	return rc;
2486	}
2487
2488	/*
2489	* Allocate the new ROM range and RAM range (if necessary).
2490	*/
2491	PPGMROMRANGE pRomNew;
2492	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2493	if (RT_SUCCESS(rc))
2494	{
2495	PPGMRAMRANGE pRamNew = NULL;
2496	if (!fRamExists)
2497	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2498	if (RT_SUCCESS(rc))
2499	{
2500	pgmLock(pVM);
2501
2502	/*
2503	* Initialize and insert the RAM range (if required).
2504	*/
2505	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2506	if (!fRamExists)
2507	{
2508	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2509	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2510	pRamNew->GCPhys = GCPhys;
2511	pRamNew->GCPhysLast = GCPhysLast;
2512	pRamNew->cb = cb;
2513	pRamNew->pszDesc = pszDesc;
2514	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
2515	pRamNew->pvR3 = NULL;
2516	pRamNew->paLSPages = NULL;
2517
2518	PPGMPAGE pPage = &pRamNew->aPages[0];
2519	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2520	{
2521	PGM_PAGE_INIT(pPage,
2522	pReq->aPages[iPage].HCPhysGCPhys,
2523	pReq->aPages[iPage].idPage,
2524	PGMPAGETYPE_ROM,
2525	PGM_PAGE_STATE_ALLOCATED);
2526
2527	pRomPage->Virgin = *pPage;
2528	}
2529
2530	pVM->pgm.s.cAllPages += cPages;
2531	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2532	}
2533	else
2534	{
2535	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2536	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2537	{
2538	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2539	PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2540	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2541	PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2542
2543	pRomPage->Virgin = *pPage;
2544	}
2545
2546	pRamNew = pRam;
2547
2548	pVM->pgm.s.cZeroPages -= cPages;
2549	}
2550	pVM->pgm.s.cPrivatePages += cPages;
2551
2552	/* Flush physical page map TLB. */
2553	PGMPhysInvalidatePageMapTLB(pVM);
2554
2555	pgmUnlock(pVM);
2556
2557
2558	/*
2559	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2560	*
2561	* If it's shadowed we'll register the handler after the ROM notification
2562	* so we get the access handler callbacks that we should. If it isn't
2563	* shadowed we'll do it the other way around to make REM use the built-in
2564	* ROM behavior and not the handler behavior (which is to route all access
2565	* to PGM atm).
2566	*/
2567	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2568	{
2569	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2570	rc = PGMR3HandlerPhysicalRegister(pVM,
2571	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2572	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2573	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2574	GCPhys, GCPhysLast,
2575	pgmR3PhysRomWriteHandler, pRomNew,
2576	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2577	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2578	}
2579	else
2580	{
2581	rc = PGMR3HandlerPhysicalRegister(pVM,
2582	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2583	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2584	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2585	GCPhys, GCPhysLast,
2586	pgmR3PhysRomWriteHandler, pRomNew,
2587	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2588	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2589	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2590	}
2591	if (RT_SUCCESS(rc))
2592	{
2593	pgmLock(pVM);
2594
2595	/*
2596	* Copy the image over to the virgin pages.
2597	* This must be done after linking in the RAM range.
2598	*/
2599	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2600	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2601	{
2602	void *pvDstPage;
2603	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
2604	if (RT_FAILURE(rc))
2605	{
2606	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2607	break;
2608	}
2609	memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2610	}
2611	if (RT_SUCCESS(rc))
2612	{
2613	/*
2614	* Initialize the ROM range.
2615	* Note that the Virgin member of the pages has already been initialized above.
2616	*/
2617	pRomNew->GCPhys = GCPhys;
2618	pRomNew->GCPhysLast = GCPhysLast;
2619	pRomNew->cb = cb;
2620	pRomNew->fFlags = fFlags;
2621	pRomNew->idSavedState = UINT8_MAX;
2622	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2623	pRomNew->pszDesc = pszDesc;
2624
2625	for (unsigned iPage = 0; iPage < cPages; iPage++)
2626	{
2627	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2628	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2629	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2630	}
2631
2632	/* update the page count stats for the shadow pages. */
2633	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2634	{
2635	pVM->pgm.s.cZeroPages += cPages;
2636	pVM->pgm.s.cAllPages += cPages;
2637	}
2638
2639	/*
2640	* Insert the ROM range, tell REM and return successfully.
2641	*/
2642	pRomNew->pNextR3 = pRom;
2643	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2644	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2645
2646	if (pRomPrev)
2647	{
2648	pRomPrev->pNextR3 = pRomNew;
2649	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2650	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2651	}
2652	else
2653	{
2654	pVM->pgm.s.pRomRangesR3 = pRomNew;
2655	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2656	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2657	}
2658
2659	PGMPhysInvalidatePageMapTLB(pVM);
2660	GMMR3AllocatePagesCleanup(pReq);
2661	pgmUnlock(pVM);
2662	return VINF_SUCCESS;
2663	}
2664
2665	/* bail out */
2666
2667	pgmUnlock(pVM);
2668	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2669	AssertRC(rc2);
2670	pgmLock(pVM);
2671	}
2672
2673	if (!fRamExists)
2674	{
2675	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2676	MMHyperFree(pVM, pRamNew);
2677	}
2678	}
2679	MMHyperFree(pVM, pRomNew);
2680	}
2681
2682	/** @todo Purge the mapping cache or something... */
2683	GMMR3FreeAllocatedPages(pVM, pReq);
2684	GMMR3AllocatePagesCleanup(pReq);
2685	pgmUnlock(pVM);
2686	return rc;
2687	}
2688
2689
2690	/**
2691	* \#PF Handler callback for ROM write accesses.
2692	*
2693	* @returns VINF_SUCCESS if the handler have carried out the operation.
2694	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2695	* @param pVM VM Handle.
2696	* @param GCPhys The physical address the guest is writing to.
2697	* @param pvPhys The HC mapping of that address.
2698	* @param pvBuf What the guest is reading/writing.
2699	* @param cbBuf How much it's reading/writing.
2700	* @param enmAccessType The access type.
2701	* @param pvUser User argument.
2702	*/
2703	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2704	{
2705	PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2706	const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2707	Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2708	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2709	Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2710
2711	if (enmAccessType == PGMACCESSTYPE_READ)
2712	{
2713	switch (pRomPage->enmProt)
2714	{
2715	/*
2716	* Take the default action.
2717	*/
2718	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2719	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2720	case PGMROMPROT_READ_ROM_WRITE_RAM:
2721	case PGMROMPROT_READ_RAM_WRITE_RAM:
2722	return VINF_PGM_HANDLER_DO_DEFAULT;
2723
2724	default:
2725	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2726	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2727	VERR_INTERNAL_ERROR);
2728	}
2729	}
2730	else
2731	{
2732	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2733	switch (pRomPage->enmProt)
2734	{
2735	/*
2736	* Ignore writes.
2737	*/
2738	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2739	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2740	return VINF_SUCCESS;
2741
2742	/*
2743	* Write to the ram page.
2744	*/
2745	case PGMROMPROT_READ_ROM_WRITE_RAM:
2746	case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's way simpler that way. */
2747	{
2748	/* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2749	Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2750
2751	/*
2752	* Take the lock, do lazy allocation, map the page and copy the data.
2753	*
2754	* Note that we have to bypass the mapping TLB since it works on
2755	* guest physical addresses and entering the shadow page would
2756	* kind of screw things up...
2757	*/
2758	int rc = pgmLock(pVM);
2759	AssertRC(rc);
2760
2761	PPGMPAGE pShadowPage = &pRomPage->Shadow;
2762	if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2763	{
2764	pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2765	AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2766	}
2767
2768	void *pvDstPage;
2769	rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
2770	if (RT_SUCCESS(rc))
2771	{
2772	memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2773	pRomPage->LiveSave.fWrittenTo = true;
2774	}
2775
2776	pgmUnlock(pVM);
2777	return rc;
2778	}
2779
2780	default:
2781	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2782	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2783	VERR_INTERNAL_ERROR);
2784	}
2785	}
2786	}
2787
2788
2789	/**
2790	* Called by PGMR3Reset to reset the shadow, switch to the virgin,
2791	* and verify that the virgin part is untouched.
2792	*
2793	* This is done after the normal memory has been cleared.
2794	*
2795	* ASSUMES that the caller owns the PGM lock.
2796	*
2797	* @param pVM The VM handle.
2798	*/
2799	int pgmR3PhysRomReset(PVM pVM)
2800	{
2801	Assert(PGMIsLockOwner(pVM));
2802	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2803	{
2804	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2805
2806	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2807	{
2808	/*
2809	* Reset the physical handler.
2810	*/
2811	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2812	AssertRCReturn(rc, rc);
2813
2814	/*
2815	* What we do with the shadow pages depends on the memory
2816	* preallocation option. If not enabled, we'll just throw
2817	* out all the dirty pages and replace them by the zero page.
2818	*/
2819	if (!pVM->pgm.s.fRamPreAlloc)
2820	{
2821	/* Free the dirty pages. */
2822	uint32_t cPendingPages = 0;
2823	PGMMFREEPAGESREQ pReq;
2824	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2825	AssertRCReturn(rc, rc);
2826
2827	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2828	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
2829	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
2830	{
2831	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2832	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2833	AssertLogRelRCReturn(rc, rc);
2834	}
2835
2836	if (cPendingPages)
2837	{
2838	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2839	AssertLogRelRCReturn(rc, rc);
2840	}
2841	GMMR3FreePagesCleanup(pReq);
2842	}
2843	else
2844	{
2845	/* clear all the shadow pages. */
2846	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2847	{
2848	Assert(!PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
2849	void *pvDstPage;
2850	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2851	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
2852	if (RT_FAILURE(rc))
2853	break;
2854	ASMMemZeroPage(pvDstPage);
2855	}
2856	AssertRCReturn(rc, rc);
2857	}
2858	}
2859
2860	#ifdef VBOX_STRICT
2861	/*
2862	* Verify that the virgin page is unchanged if possible.
2863	*/
2864	if (pRom->pvOriginal)
2865	{
2866	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
2867	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2868	{
2869	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2870	void const *pvDstPage;
2871	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
2872	if (RT_FAILURE(rc))
2873	break;
2874	if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2875	LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2876	GCPhys, pRom->pszDesc));
2877	}
2878	}
2879	#endif
2880	}
2881
2882	return VINF_SUCCESS;
2883	}
2884
2885
2886	/**
2887	* Change the shadowing of a range of ROM pages.
2888	*
2889	* This is intended for implementing chipset specific memory registers
2890	* and will not be very strict about the input. It will silently ignore
2891	* any pages that are not the part of a shadowed ROM.
2892	*
2893	* @returns VBox status code.
2894	* @retval VINF_PGM_SYNC_CR3
2895	*
2896	* @param pVM Pointer to the shared VM structure.
2897	* @param GCPhys Where to start. Page aligned.
2898	* @param cb How much to change. Page aligned.
2899	* @param enmProt The new ROM protection.
2900	*/
2901	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2902	{
2903	/*
2904	* Check input
2905	*/
2906	if (!cb)
2907	return VINF_SUCCESS;
2908	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2909	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2910	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2911	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2912	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2913
2914	/*
2915	* Process the request.
2916	*/
2917	pgmLock(pVM);
2918	int rc = VINF_SUCCESS;
2919	bool fFlushTLB = false;
2920	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2921	{
2922	if ( GCPhys <= pRom->GCPhysLast
2923	&& GCPhysLast >= pRom->GCPhys
2924	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2925	{
2926	/*
2927	* Iterate the relevant pages and make necessary the changes.
2928	*/
2929	bool fChanges = false;
2930	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2931	? pRom->cb >> PAGE_SHIFT
2932	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2933	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2934	iPage < cPages;
2935	iPage++)
2936	{
2937	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2938	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2939	{
2940	fChanges = true;
2941
2942	/* flush references to the page. */
2943	PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2944	int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage, &fFlushTLB);
2945	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
2946	rc = rc2;
2947
2948	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2949	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2950
2951	pOld = pRamPage;
2952	pRamPage = pNew;
2953	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2954	}
2955	pRomPage->enmProt = enmProt;
2956	}
2957
2958	/*
2959	* Reset the access handler if we made changes, no need
2960	* to optimize this.
2961	*/
2962	if (fChanges)
2963	{
2964	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2965	if (RT_FAILURE(rc2))
2966	{
2967	pgmUnlock(pVM);
2968	AssertRC(rc);
2969	return rc2;
2970	}
2971	}
2972
2973	/* Advance - cb isn't updated. */
2974	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2975	}
2976	}
2977	pgmUnlock(pVM);
2978	if (fFlushTLB)
2979	PGM_INVL_ALL_VCPU_TLBS(pVM);
2980
2981	return rc;
2982	}
2983
2984
2985	/**
2986	* Sets the Address Gate 20 state.
2987	*
2988	* @param pVCpu The VCPU to operate on.
2989	* @param fEnable True if the gate should be enabled.
2990	* False if the gate should be disabled.
2991	*/
2992	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
2993	{
2994	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
2995	if (pVCpu->pgm.s.fA20Enabled != fEnable)
2996	{
2997	pVCpu->pgm.s.fA20Enabled = fEnable;
2998	pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2999	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
3000	/** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
3001	}
3002	}
3003
3004
3005	/**
3006	* Tree enumeration callback for dealing with age rollover.
3007	* It will perform a simple compression of the current age.
3008	*/
3009	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
3010	{
3011	Assert(PGMIsLockOwner((PVM)pvUser));
3012	/* Age compression - ASSUMES iNow == 4. */
3013	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3014	if (pChunk->iAge >= UINT32_C(0xffffff00))
3015	pChunk->iAge = 3;
3016	else if (pChunk->iAge >= UINT32_C(0xfffff000))
3017	pChunk->iAge = 2;
3018	else if (pChunk->iAge)
3019	pChunk->iAge = 1;
3020	else /* iAge = 0 */
3021	pChunk->iAge = 4;
3022
3023	/* reinsert */
3024	PVM pVM = (PVM)pvUser;
3025	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
3026	pChunk->AgeCore.Key = pChunk->iAge;
3027	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3028	return 0;
3029	}
3030
3031
3032	/**
3033	* Tree enumeration callback that updates the chunks that have
3034	* been used since the last
3035	*/
3036	static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
3037	{
3038	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3039	if (!pChunk->iAge)
3040	{
3041	PVM pVM = (PVM)pvUser;
3042	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
3043	pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
3044	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3045	}
3046
3047	return 0;
3048	}
3049
3050
3051	/**
3052	* Performs ageing of the ring-3 chunk mappings.
3053	*
3054	* @param pVM The VM handle.
3055	*/
3056	VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
3057	{
3058	pgmLock(pVM);
3059	pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
3060	pVM->pgm.s.ChunkR3Map.iNow++;
3061	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
3062	{
3063	pVM->pgm.s.ChunkR3Map.iNow = 4;
3064	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
3065	}
3066	else
3067	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingCallback, pVM);
3068	pgmUnlock(pVM);
3069	}
3070
3071
3072	/**
3073	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
3074	*/
3075	typedef struct PGMR3PHYSCHUNKUNMAPCB
3076	{
3077	PVM pVM; /*< The VM handle. /
3078	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
3079	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
3080
3081
3082	/**
3083	* Callback used to find the mapping that's been unused for
3084	* the longest time.
3085	*/
3086	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
3087	{
3088	do
3089	{
3090	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
3091	if ( pChunk->iAge
3092	&& !pChunk->cRefs)
3093	{
3094	/*
3095	* Check that it's not in any of the TLBs.
3096	*/
3097	PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
3098	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3099	if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
3100	{
3101	pChunk = NULL;
3102	break;
3103	}
3104	if (pChunk)
3105	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
3106	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
3107	{
3108	pChunk = NULL;
3109	break;
3110	}
3111	if (pChunk)
3112	{
3113	((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
3114	return 1; /* done */
3115	}
3116	}
3117
3118	/* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
3119	pNode = pNode->pList;
3120	} while (pNode);
3121	return 0;
3122	}
3123
3124
3125	/**
3126	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
3127	*
3128	* The candidate will not be part of any TLBs, so no need to flush
3129	* anything afterwards.
3130	*
3131	* @returns Chunk id.
3132	* @param pVM The VM handle.
3133	*/
3134	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
3135	{
3136	Assert(PGMIsLockOwner(pVM));
3137
3138	/*
3139	* Do tree ageing first?
3140	*/
3141	if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
3142	PGMR3PhysChunkAgeing(pVM);
3143
3144	/*
3145	* Enumerate the age tree starting with the left most node.
3146	*/
3147	PGMR3PHYSCHUNKUNMAPCB Args;
3148	Args.pVM = pVM;
3149	Args.pChunk = NULL;
3150	if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
3151	return Args.pChunk->Core.Key;
3152	return INT32_MAX;
3153	}
3154
3155
3156	/**
3157	* Maps the given chunk into the ring-3 mapping cache.
3158	*
3159	* This will call ring-0.
3160	*
3161	* @returns VBox status code.
3162	* @param pVM The VM handle.
3163	* @param idChunk The chunk in question.
3164	* @param ppChunk Where to store the chunk tracking structure.
3165	*
3166	* @remarks Called from within the PGM critical section.
3167	*/
3168	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
3169	{
3170	int rc;
3171
3172	Assert(PGMIsLockOwner(pVM));
3173	/*
3174	* Allocate a new tracking structure first.
3175	*/
3176	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3177	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
3178	#else
3179	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
3180	#endif
3181	AssertReturn(pChunk, VERR_NO_MEMORY);
3182	pChunk->Core.Key = idChunk;
3183	pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
3184	pChunk->iAge = 0;
3185	pChunk->cRefs = 0;
3186	pChunk->cPermRefs = 0;
3187	pChunk->pv = NULL;
3188
3189	/*
3190	* Request the ring-0 part to map the chunk in question and if
3191	* necessary unmap another one to make space in the mapping cache.
3192	*/
3193	GMMMAPUNMAPCHUNKREQ Req;
3194	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3195	Req.Hdr.cbReq = sizeof(Req);
3196	Req.pvR3 = NULL;
3197	Req.idChunkMap = idChunk;
3198	Req.idChunkUnmap = NIL_GMM_CHUNKID;
3199	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3200	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
3201	/** @todo This is wrong. Any thread in the VM process should be able to do this,
3202	* there are depenenecies on this. What currently saves the day is that
3203	* we don't unmap anything and that all non-zero memory will therefore
3204	* be present when non-EMTs tries to access it. */
3205	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3206	if (RT_SUCCESS(rc))
3207	{
3208	/*
3209	* Update the tree.
3210	*/
3211	/* insert the new one. */
3212	AssertPtr(Req.pvR3);
3213	pChunk->pv = Req.pvR3;
3214	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
3215	AssertRelease(fRc);
3216	pVM->pgm.s.ChunkR3Map.c++;
3217
3218	fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3219	AssertRelease(fRc);
3220
3221	/* remove the unmapped one. */
3222	if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
3223	{
3224	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
3225	AssertRelease(pUnmappedChunk);
3226	pUnmappedChunk->pv = NULL;
3227	pUnmappedChunk->Core.Key = UINT32_MAX;
3228	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3229	MMR3HeapFree(pUnmappedChunk);
3230	#else
3231	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3232	#endif
3233	pVM->pgm.s.ChunkR3Map.c--;
3234
3235	/* Chunk removed, so clear the page map TBL as well (might still be referenced). */
3236	PGMPhysInvalidatePageMapTLB(pVM);
3237	}
3238	}
3239	else
3240	{
3241	AssertRC(rc);
3242	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3243	MMR3HeapFree(pChunk);
3244	#else
3245	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
3246	#endif
3247	pChunk = NULL;
3248	}
3249
3250	*ppChunk = pChunk;
3251	return rc;
3252	}
3253
3254
3255	/**
3256	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3257	*
3258	* @returns see pgmR3PhysChunkMap.
3259	* @param pVM The VM handle.
3260	* @param idChunk The chunk to map.
3261	*/
3262	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3263	{
3264	PPGMCHUNKR3MAP pChunk;
3265	int rc;
3266
3267	pgmLock(pVM);
3268	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3269	pgmUnlock(pVM);
3270	return rc;
3271	}
3272
3273
3274	/**
3275	* Invalidates the TLB for the ring-3 mapping cache.
3276	*
3277	* @param pVM The VM handle.
3278	*/
3279	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3280	{
3281	pgmLock(pVM);
3282	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3283	{
3284	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3285	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3286	}
3287	/* The page map TLB references chunks, so invalidate that one too. */
3288	PGMPhysInvalidatePageMapTLB(pVM);
3289	pgmUnlock(pVM);
3290	}
3291
3292
3293	/**
3294	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_PAGE to allocate a large (2MB) page
3295	* for use with a nested paging PDE.
3296	*
3297	* @returns The following VBox status codes.
3298	* @retval VINF_SUCCESS on success.
3299	* @retval VINF_EM_NO_MEMORY if we're out of memory.
3300	*
3301	* @param pVM The VM handle.
3302	* @param GCPhys GC physical start address of the 2 MB range
3303	*/
3304	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
3305	{
3306	pgmLock(pVM);
3307
3308	STAM_PROFILE_START(&pVM->pgm.s.StatAllocLargePage, a);
3309	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
3310	STAM_PROFILE_STOP(&pVM->pgm.s.StatAllocLargePage, a);
3311	if (RT_SUCCESS(rc))
3312	{
3313	Assert(pVM->pgm.s.cLargeHandyPages == 1);
3314
3315	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
3316	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
3317
3318	void *pv;
3319
3320	/* Map the large page into our address space.
3321	*
3322	* Note: assuming that within the 2 MB range:
3323	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
3324	* - user space mapping is continuous as well
3325	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
3326	*/
3327	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
3328	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", idPage, HCPhys, rc));
3329
3330	if (RT_SUCCESS(rc))
3331	{
3332	/*
3333	* Clear the pages.
3334	*/
3335	STAM_PROFILE_START(&pVM->pgm.s.StatClearLargePage, b);
3336	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
3337	{
3338	ASMMemZeroPage(pv);
3339
3340	PPGMPAGE pPage;
3341	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
3342	AssertRC(rc);
3343
3344	Assert(PGM_PAGE_IS_ZERO(pPage));
3345	STAM_COUNTER_INC(&pVM->pgm.s.StatRZPageReplaceZero);
3346	pVM->pgm.s.cZeroPages--;
3347
3348	/*
3349	* Do the PGMPAGE modifications.
3350	*/
3351	pVM->pgm.s.cPrivatePages++;
3352	PGM_PAGE_SET_HCPHYS(pPage, HCPhys);
3353	PGM_PAGE_SET_PAGEID(pPage, idPage);
3354	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
3355	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_PDE);
3356
3357	/* Somewhat dirty assumption that page ids are increasing. */
3358	idPage++;
3359
3360	HCPhys += PAGE_SIZE;
3361	GCPhys += PAGE_SIZE;
3362
3363	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
3364
3365	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
3366	}
3367	STAM_PROFILE_STOP(&pVM->pgm.s.StatClearLargePage, b);
3368
3369	/* Flush all TLBs. */
3370	PGM_INVL_ALL_VCPU_TLBS(pVM);
3371	PGMPhysInvalidatePageMapTLB(pVM);
3372	}
3373	pVM->pgm.s.cLargeHandyPages = 0;
3374	}
3375
3376	pgmUnlock(pVM);
3377	return rc;
3378	}
3379
3380
3381	/**
3382	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3383	*
3384	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3385	* signal and clear the out of memory condition. When contracted, this API is
3386	* used to try clear the condition when the user wants to resume.
3387	*
3388	* @returns The following VBox status codes.
3389	* @retval VINF_SUCCESS on success. FFs cleared.
3390	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3391	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3392	*
3393	* @param pVM The VM handle.
3394	*
3395	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3396	* in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3397	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3398	* handler.
3399	*/
3400	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3401	{
3402	pgmLock(pVM);
3403
3404	/*
3405	* Allocate more pages, noting down the index of the first new page.
3406	*/
3407	uint32_t iClear = pVM->pgm.s.cHandyPages;
3408	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3409	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3410	int rcAlloc = VINF_SUCCESS;
3411	int rcSeed = VINF_SUCCESS;
3412	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3413	while (rc == VERR_GMM_SEED_ME)
3414	{
3415	void *pvChunk;
3416	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3417	if (RT_SUCCESS(rc))
3418	{
3419	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3420	if (RT_FAILURE(rc))
3421	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3422	}
3423	if (RT_SUCCESS(rc))
3424	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3425	}
3426
3427	if (RT_SUCCESS(rc))
3428	{
3429	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3430	Assert(pVM->pgm.s.cHandyPages > 0);
3431	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3432	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3433
3434	/*
3435	* Clear the pages.
3436	*/
3437	while (iClear < pVM->pgm.s.cHandyPages)
3438	{
3439	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3440	void *pv;
3441	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3442	AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3443	ASMMemZeroPage(pv);
3444	iClear++;
3445	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3446	}
3447	}
3448	else
3449	{
3450	/*
3451	* We should never get here unless there is a genuine shortage of
3452	* memory (or some internal error). Flag the error so the VM can be
3453	* suspended ASAP and the user informed. If we're totally out of
3454	* handy pages we will return failure.
3455	*/
3456	/* Report the failure. */
3457	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3458	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3459	rc, rcAlloc, rcSeed,
3460	pVM->pgm.s.cHandyPages,
3461	pVM->pgm.s.cAllPages,
3462	pVM->pgm.s.cPrivatePages,
3463	pVM->pgm.s.cSharedPages,
3464	pVM->pgm.s.cZeroPages));
3465	if ( rc != VERR_NO_MEMORY
3466	&& rc != VERR_LOCK_FAILED)
3467	{
3468	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3469	{
3470	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3471	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3472	pVM->pgm.s.aHandyPages[i].idSharedPage));
3473	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3474	if (idPage != NIL_GMM_PAGEID)
3475	{
3476	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3477	pRam;
3478	pRam = pRam->pNextR3)
3479	{
3480	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3481	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3482	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3483	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3484	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3485	}
3486	}
3487	}
3488	}
3489
3490	/* Set the FFs and adjust rc. */
3491	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3492	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3493	if ( rc == VERR_NO_MEMORY
3494	\|\| rc == VERR_LOCK_FAILED)
3495	rc = VINF_EM_NO_MEMORY;
3496	}
3497
3498	pgmUnlock(pVM);
3499	return rc;
3500	}
3501
3502
3503	/**
3504	* Frees the specified RAM page and replaces it with the ZERO page.
3505	*
3506	* This is used by ballooning, remapping MMIO2 and RAM reset.
3507	*
3508	* @param pVM Pointer to the shared VM structure.
3509	* @param pReq Pointer to the request.
3510	* @param pPage Pointer to the page structure.
3511	* @param GCPhys The guest physical address of the page, if applicable.
3512	*
3513	* @remarks The caller must own the PGM lock.
3514	*/
3515	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3516	{
3517	/*
3518	* Assert sanity.
3519	*/
3520	Assert(PGMIsLockOwner(pVM));
3521	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3522	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3523	{
3524	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3525	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3526	}
3527
3528	if ( PGM_PAGE_IS_ZERO(pPage)
3529	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3530	return VINF_SUCCESS;
3531
3532	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3533	Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3534	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3535	\|\| idPage > GMM_PAGEID_LAST
3536	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3537	{
3538	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3539	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3540	}
3541
3542	/* update page count stats. */
3543	if (PGM_PAGE_IS_SHARED(pPage))
3544	pVM->pgm.s.cSharedPages--;
3545	else
3546	pVM->pgm.s.cPrivatePages--;
3547	pVM->pgm.s.cZeroPages++;
3548
3549	/* Deal with write monitored pages. */
3550	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
3551	{
3552	PGM_PAGE_SET_WRITTEN_TO(pPage);
3553	pVM->pgm.s.cWrittenToPages++;
3554	}
3555
3556	/*
3557	* pPage = ZERO page.
3558	*/
3559	PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3560	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3561	PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3562	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
3563
3564	/* Flush physical page map TLB entry. */
3565	PGMPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
3566
3567	/*
3568	* Make sure it's not in the handy page array.
3569	*/
3570	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3571	{
3572	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3573	{
3574	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3575	break;
3576	}
3577	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3578	{
3579	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3580	break;
3581	}
3582	}
3583
3584	/*
3585	* Push it onto the page array.
3586	*/
3587	uint32_t iPage = *pcPendingPages;
3588	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3589	*pcPendingPages += 1;
3590
3591	pReq->aPages[iPage].idPage = idPage;
3592
3593	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3594	return VINF_SUCCESS;
3595
3596	/*
3597	* Flush the pages.
3598	*/
3599	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3600	if (RT_SUCCESS(rc))
3601	{
3602	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3603	*pcPendingPages = 0;
3604	}
3605	return rc;
3606	}
3607
3608
3609	/**
3610	* Converts a GC physical address to a HC ring-3 pointer, with some
3611	* additional checks.
3612	*
3613	* @returns VBox status code.
3614	* @retval VINF_SUCCESS on success.
3615	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3616	* access handler of some kind.
3617	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3618	* accesses or is odd in any way.
3619	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3620	*
3621	* @param pVM The VM handle.
3622	* @param GCPhys The GC physical address to convert.
3623	* @param fWritable Whether write access is required.
3624	* @param ppv Where to store the pointer corresponding to GCPhys on
3625	* success.
3626	*/
3627	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3628	{
3629	pgmLock(pVM);
3630
3631	PPGMRAMRANGE pRam;
3632	PPGMPAGE pPage;
3633	int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3634	if (RT_SUCCESS(rc))
3635	{
3636	if (PGM_PAGE_IS_BALLOONED(pPage))
3637	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3638	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3639	rc = VINF_SUCCESS;
3640	else
3641	{
3642	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3643	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3644	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3645	{
3646	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3647	* in -norawr0 mode. */
3648	if (fWritable)
3649	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3650	}
3651	else
3652	{
3653	/* Temporarily disabled physical handler(s), since the recompiler
3654	doesn't get notified when it's reset we'll have to pretend it's
3655	operating normally. */
3656	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3657	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3658	else
3659	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3660	}
3661	}
3662	if (RT_SUCCESS(rc))
3663	{
3664	int rc2;
3665
3666	/* Make sure what we return is writable. */
3667	if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3668	switch (PGM_PAGE_GET_STATE(pPage))
3669	{
3670	case PGM_PAGE_STATE_ALLOCATED:
3671	break;
3672	case PGM_PAGE_STATE_BALLOONED:
3673	AssertFailed();
3674	break;
3675	case PGM_PAGE_STATE_ZERO:
3676	case PGM_PAGE_STATE_SHARED:
3677	case PGM_PAGE_STATE_WRITE_MONITORED:
3678	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3679	AssertLogRelRCReturn(rc2, rc2);
3680	break;
3681	}
3682
3683	/* Get a ring-3 mapping of the address. */
3684	PPGMPAGER3MAPTLBE pTlbe;
3685	rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3686	AssertLogRelRCReturn(rc2, rc2);
3687	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
3688	/** @todo mapping/locking hell; this isn't horribly efficient since
3689	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
3690
3691	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
3692	}
3693	else
3694	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3695
3696	/* else: handler catching all access, no pointer returned. */
3697	}
3698	else
3699	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3700
3701	pgmUnlock(pVM);
3702	return rc;
3703	}
3704

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source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 27948

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