PGMPhys.cpp@ 28003

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1	/* $Id: PGMPhys.cpp 28003 2010-04-06 12:44:09Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_PHYS
27	#include <VBox/pgm.h>
28	#include <VBox/iom.h>
29	#include <VBox/mm.h>
30	#include <VBox/stam.h>
31	#include <VBox/rem.h>
32	#include <VBox/pdmdev.h>
33	#include "PGMInternal.h"
34	#include <VBox/vm.h>
35	#include "PGMInline.h"
36	#include <VBox/sup.h>
37	#include <VBox/param.h>
38	#include <VBox/err.h>
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/alloc.h>
42	#include <iprt/asm.h>
43	#include <iprt/thread.h>
44	#include <iprt/string.h>
45
46
47	/*******************************************************************************
48	* Defined Constants And Macros *
49	*******************************************************************************/
50	/** The number of pages to free in one batch. */
51	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
52
53
54	/*******************************************************************************
55	* Internal Functions *
56	*******************************************************************************/
57	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
58	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
59
60
61	/*
62	* PGMR3PhysReadU8-64
63	* PGMR3PhysWriteU8-64
64	*/
65	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
66	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
67	#define PGMPHYS_DATASIZE 1
68	#define PGMPHYS_DATATYPE uint8_t
69	#include "PGMPhysRWTmpl.h"
70
71	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
72	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
73	#define PGMPHYS_DATASIZE 2
74	#define PGMPHYS_DATATYPE uint16_t
75	#include "PGMPhysRWTmpl.h"
76
77	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
78	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
79	#define PGMPHYS_DATASIZE 4
80	#define PGMPHYS_DATATYPE uint32_t
81	#include "PGMPhysRWTmpl.h"
82
83	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
84	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
85	#define PGMPHYS_DATASIZE 8
86	#define PGMPHYS_DATATYPE uint64_t
87	#include "PGMPhysRWTmpl.h"
88
89
90	/**
91	* EMT worker for PGMR3PhysReadExternal.
92	*/
93	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
94	{
95	PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
96	return VINF_SUCCESS;
97	}
98
99
100	/**
101	* Write to physical memory, external users.
102	*
103	* @returns VBox status code.
104	* @retval VINF_SUCCESS.
105	*
106	* @param pVM VM Handle.
107	* @param GCPhys Physical address to write to.
108	* @param pvBuf What to write.
109	* @param cbWrite How many bytes to write.
110	*
111	* @thread Any but EMTs.
112	*/
113	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
114	{
115	VM_ASSERT_OTHER_THREAD(pVM);
116
117	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
118	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
119
120	pgmLock(pVM);
121
122	/*
123	* Copy loop on ram ranges.
124	*/
125	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
126	for (;;)
127	{
128	/* Find range. */
129	while (pRam && GCPhys > pRam->GCPhysLast)
130	pRam = pRam->CTX_SUFF(pNext);
131	/* Inside range or not? */
132	if (pRam && GCPhys >= pRam->GCPhys)
133	{
134	/*
135	* Must work our way thru this page by page.
136	*/
137	RTGCPHYS off = GCPhys - pRam->GCPhys;
138	while (off < pRam->cb)
139	{
140	unsigned iPage = off >> PAGE_SHIFT;
141	PPGMPAGE pPage = &pRam->aPages[iPage];
142
143	/*
144	* If the page has an ALL access handler, we'll have to
145	* delegate the job to EMT.
146	*/
147	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
148	{
149	pgmUnlock(pVM);
150
151	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 4,
152	pVM, &GCPhys, pvBuf, cbRead);
153	}
154	Assert(!PGM_PAGE_IS_MMIO(pPage));
155
156	/*
157	* Simple stuff, go ahead.
158	*/
159	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
160	if (cb > cbRead)
161	cb = cbRead;
162	const void *pvSrc;
163	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
164	if (RT_SUCCESS(rc))
165	memcpy(pvBuf, pvSrc, cb);
166	else
167	{
168	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
169	pRam->GCPhys + off, pPage, rc));
170	memset(pvBuf, 0xff, cb);
171	}
172
173	/* next page */
174	if (cb >= cbRead)
175	{
176	pgmUnlock(pVM);
177	return VINF_SUCCESS;
178	}
179	cbRead -= cb;
180	off += cb;
181	GCPhys += cb;
182	pvBuf = (char *)pvBuf + cb;
183	} /* walk pages in ram range. */
184	}
185	else
186	{
187	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
188
189	/*
190	* Unassigned address space.
191	*/
192	if (!pRam)
193	break;
194	size_t cb = pRam->GCPhys - GCPhys;
195	if (cb >= cbRead)
196	{
197	memset(pvBuf, 0xff, cbRead);
198	break;
199	}
200	memset(pvBuf, 0xff, cb);
201
202	cbRead -= cb;
203	pvBuf = (char *)pvBuf + cb;
204	GCPhys += cb;
205	}
206	} /* Ram range walk */
207
208	pgmUnlock(pVM);
209
210	return VINF_SUCCESS;
211	}
212
213
214	/**
215	* EMT worker for PGMR3PhysWriteExternal.
216	*/
217	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
218	{
219	/** @todo VERR_EM_NO_MEMORY */
220	PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
221	return VINF_SUCCESS;
222	}
223
224
225	/**
226	* Write to physical memory, external users.
227	*
228	* @returns VBox status code.
229	* @retval VINF_SUCCESS.
230	* @retval VERR_EM_NO_MEMORY.
231	*
232	* @param pVM VM Handle.
233	* @param GCPhys Physical address to write to.
234	* @param pvBuf What to write.
235	* @param cbWrite How many bytes to write.
236	* @param pszWho Who is writing. For tracking down who is writing
237	* after we've saved the state.
238	*
239	* @thread Any but EMTs.
240	*/
241	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void pvBuf, size_t cbWrite, const char pszWho)
242	{
243	VM_ASSERT_OTHER_THREAD(pVM);
244
245	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
246	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x pszWho=%s\n",
247	GCPhys, cbWrite, pszWho));
248	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
249	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
250
251	pgmLock(pVM);
252
253	/*
254	* Copy loop on ram ranges, stop when we hit something difficult.
255	*/
256	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
257	for (;;)
258	{
259	/* Find range. */
260	while (pRam && GCPhys > pRam->GCPhysLast)
261	pRam = pRam->CTX_SUFF(pNext);
262	/* Inside range or not? */
263	if (pRam && GCPhys >= pRam->GCPhys)
264	{
265	/*
266	* Must work our way thru this page by page.
267	*/
268	RTGCPTR off = GCPhys - pRam->GCPhys;
269	while (off < pRam->cb)
270	{
271	RTGCPTR iPage = off >> PAGE_SHIFT;
272	PPGMPAGE pPage = &pRam->aPages[iPage];
273
274	/*
275	* Is the page problematic, we have to do the work on the EMT.
276	*
277	* Allocating writable pages and access handlers are
278	* problematic, write monitored pages are simple and can be
279	* dealth with here.
280	*/
281	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
282	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
283	{
284	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
285	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
286	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
287	else
288	{
289	pgmUnlock(pVM);
290
291	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 4,
292	pVM, &GCPhys, pvBuf, cbWrite);
293	}
294	}
295	Assert(!PGM_PAGE_IS_MMIO(pPage));
296
297	/*
298	* Simple stuff, go ahead.
299	*/
300	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
301	if (cb > cbWrite)
302	cb = cbWrite;
303	void *pvDst;
304	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
305	if (RT_SUCCESS(rc))
306	memcpy(pvDst, pvBuf, cb);
307	else
308	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
309	pRam->GCPhys + off, pPage, rc));
310
311	/* next page */
312	if (cb >= cbWrite)
313	{
314	pgmUnlock(pVM);
315	return VINF_SUCCESS;
316	}
317
318	cbWrite -= cb;
319	off += cb;
320	GCPhys += cb;
321	pvBuf = (const char *)pvBuf + cb;
322	} /* walk pages in ram range */
323	}
324	else
325	{
326	/*
327	* Unassigned address space, skip it.
328	*/
329	if (!pRam)
330	break;
331	size_t cb = pRam->GCPhys - GCPhys;
332	if (cb >= cbWrite)
333	break;
334	cbWrite -= cb;
335	pvBuf = (const char *)pvBuf + cb;
336	GCPhys += cb;
337	}
338	} /* Ram range walk */
339
340	pgmUnlock(pVM);
341	return VINF_SUCCESS;
342	}
343
344
345	/**
346	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
347	*
348	* @returns see PGMR3PhysGCPhys2CCPtrExternal
349	* @param pVM The VM handle.
350	* @param pGCPhys Pointer to the guest physical address.
351	* @param ppv Where to store the mapping address.
352	* @param pLock Where to store the lock.
353	*/
354	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
355	{
356	/*
357	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
358	* an access handler after it succeeds.
359	*/
360	int rc = pgmLock(pVM);
361	AssertRCReturn(rc, rc);
362
363	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
364	if (RT_SUCCESS(rc))
365	{
366	PPGMPAGEMAPTLBE pTlbe;
367	int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
368	AssertFatalRC(rc2);
369	PPGMPAGE pPage = pTlbe->pPage;
370	if (PGM_PAGE_IS_MMIO(pPage))
371	{
372	PGMPhysReleasePageMappingLock(pVM, pLock);
373	rc = VERR_PGM_PHYS_PAGE_RESERVED;
374	}
375	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
376	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
377	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
378	#endif
379	)
380	{
381	/* We must flush any corresponding pgm pool page here, otherwise we'll
382	* not be informed about writes and keep bogus gst->shw mappings around.
383	*/
384	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
385	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
386	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
387	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
388	}
389	}
390
391	pgmUnlock(pVM);
392	return rc;
393	}
394
395
396	/**
397	* Requests the mapping of a guest page into ring-3, external threads.
398	*
399	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
400	* release it.
401	*
402	* This API will assume your intention is to write to the page, and will
403	* therefore replace shared and zero pages. If you do not intend to modify the
404	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
405	*
406	* @returns VBox status code.
407	* @retval VINF_SUCCESS on success.
408	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
409	* backing or if the page has any active access handlers. The caller
410	* must fall back on using PGMR3PhysWriteExternal.
411	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
412	*
413	* @param pVM The VM handle.
414	* @param GCPhys The guest physical address of the page that should be mapped.
415	* @param ppv Where to store the address corresponding to GCPhys.
416	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
417	*
418	* @remark Avoid calling this API from within critical sections (other than the
419	* PGM one) because of the deadlock risk when we have to delegating the
420	* task to an EMT.
421	* @thread Any.
422	*/
423	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
424	{
425	AssertPtr(ppv);
426	AssertPtr(pLock);
427
428	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
429
430	int rc = pgmLock(pVM);
431	AssertRCReturn(rc, rc);
432
433	/*
434	* Query the Physical TLB entry for the page (may fail).
435	*/
436	PPGMPAGEMAPTLBE pTlbe;
437	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
438	if (RT_SUCCESS(rc))
439	{
440	PPGMPAGE pPage = pTlbe->pPage;
441	if (PGM_PAGE_IS_MMIO(pPage))
442	rc = VERR_PGM_PHYS_PAGE_RESERVED;
443	else
444	{
445	/*
446	* If the page is shared, the zero page, or being write monitored
447	* it must be converted to an page that's writable if possible.
448	* We can only deal with write monitored pages here, the rest have
449	* to be on an EMT.
450	*/
451	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
452	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
453	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
454	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
455	#endif
456	)
457	{
458	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
459	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
460	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
461	&& !pgmPoolIsDirtyPage(pVM, GCPhys)
462	#endif
463	)
464	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
465	else
466	{
467	pgmUnlock(pVM);
468
469	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
470	pVM, &GCPhys, ppv, pLock);
471	}
472	}
473
474	/*
475	* Now, just perform the locking and calculate the return address.
476	*/
477	PPGMPAGEMAP pMap = pTlbe->pMap;
478	if (pMap)
479	pMap->cRefs++;
480
481	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
482	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
483	{
484	if (cLocks == 0)
485	pVM->pgm.s.cWriteLockedPages++;
486	PGM_PAGE_INC_WRITE_LOCKS(pPage);
487	}
488	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
489	{
490	PGM_PAGE_INC_WRITE_LOCKS(pPage);
491	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
492	if (pMap)
493	pMap->cRefs++; /* Extra ref to prevent it from going away. */
494	}
495
496	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
497	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
498	pLock->pvMap = pMap;
499	}
500	}
501
502	pgmUnlock(pVM);
503	return rc;
504	}
505
506
507	/**
508	* Requests the mapping of a guest page into ring-3, external threads.
509	*
510	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
511	* release it.
512	*
513	* @returns VBox status code.
514	* @retval VINF_SUCCESS on success.
515	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
516	* backing or if the page as an active ALL access handler. The caller
517	* must fall back on using PGMPhysRead.
518	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
519	*
520	* @param pVM The VM handle.
521	* @param GCPhys The guest physical address of the page that should be mapped.
522	* @param ppv Where to store the address corresponding to GCPhys.
523	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
524	*
525	* @remark Avoid calling this API from within critical sections (other than
526	* the PGM one) because of the deadlock risk.
527	* @thread Any.
528	*/
529	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
530	{
531	int rc = pgmLock(pVM);
532	AssertRCReturn(rc, rc);
533
534	/*
535	* Query the Physical TLB entry for the page (may fail).
536	*/
537	PPGMPAGEMAPTLBE pTlbe;
538	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
539	if (RT_SUCCESS(rc))
540	{
541	PPGMPAGE pPage = pTlbe->pPage;
542	#if 1
543	/* MMIO pages doesn't have any readable backing. */
544	if (PGM_PAGE_IS_MMIO(pPage))
545	rc = VERR_PGM_PHYS_PAGE_RESERVED;
546	#else
547	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
548	rc = VERR_PGM_PHYS_PAGE_RESERVED;
549	#endif
550	else
551	{
552	/*
553	* Now, just perform the locking and calculate the return address.
554	*/
555	PPGMPAGEMAP pMap = pTlbe->pMap;
556	if (pMap)
557	pMap->cRefs++;
558
559	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
560	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
561	{
562	if (cLocks == 0)
563	pVM->pgm.s.cReadLockedPages++;
564	PGM_PAGE_INC_READ_LOCKS(pPage);
565	}
566	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
567	{
568	PGM_PAGE_INC_READ_LOCKS(pPage);
569	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
570	if (pMap)
571	pMap->cRefs++; /* Extra ref to prevent it from going away. */
572	}
573
574	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
575	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
576	pLock->pvMap = pMap;
577	}
578	}
579
580	pgmUnlock(pVM);
581	return rc;
582	}
583
584
585	/**
586	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
587	*
588	* Called when anything was relocated.
589	*
590	* @param pVM Pointer to the shared VM structure.
591	*/
592	void pgmR3PhysRelinkRamRanges(PVM pVM)
593	{
594	PPGMRAMRANGE pCur;
595
596	#ifdef VBOX_STRICT
597	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
598	{
599	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
600	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
601	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
602	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
603	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
604	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
605	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
606	Assert( pCur2 == pCur
607	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
608	}
609	#endif
610
611	pCur = pVM->pgm.s.pRamRangesR3;
612	if (pCur)
613	{
614	pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
615	pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
616
617	for (; pCur->pNextR3; pCur = pCur->pNextR3)
618	{
619	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
620	pCur->pNextRC = pCur->pNextR3->pSelfRC;
621	}
622
623	Assert(pCur->pNextR0 == NIL_RTR0PTR);
624	Assert(pCur->pNextRC == NIL_RTRCPTR);
625	}
626	else
627	{
628	Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
629	Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
630	}
631	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
632	}
633
634
635	/**
636	* Links a new RAM range into the list.
637	*
638	* @param pVM Pointer to the shared VM structure.
639	* @param pNew Pointer to the new list entry.
640	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
641	*/
642	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
643	{
644	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
645	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
646	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
647
648	pgmLock(pVM);
649
650	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
651	pNew->pNextR3 = pRam;
652	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
653	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
654
655	if (pPrev)
656	{
657	pPrev->pNextR3 = pNew;
658	pPrev->pNextR0 = pNew->pSelfR0;
659	pPrev->pNextRC = pNew->pSelfRC;
660	}
661	else
662	{
663	pVM->pgm.s.pRamRangesR3 = pNew;
664	pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
665	pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
666	}
667	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
668	pgmUnlock(pVM);
669	}
670
671
672	/**
673	* Unlink an existing RAM range from the list.
674	*
675	* @param pVM Pointer to the shared VM structure.
676	* @param pRam Pointer to the new list entry.
677	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
678	*/
679	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
680	{
681	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
682	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
683	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
684
685	pgmLock(pVM);
686
687	PPGMRAMRANGE pNext = pRam->pNextR3;
688	if (pPrev)
689	{
690	pPrev->pNextR3 = pNext;
691	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
692	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
693	}
694	else
695	{
696	Assert(pVM->pgm.s.pRamRangesR3 == pRam);
697	pVM->pgm.s.pRamRangesR3 = pNext;
698	pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
699	pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
700	}
701	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
702	pgmUnlock(pVM);
703	}
704
705
706	/**
707	* Unlink an existing RAM range from the list.
708	*
709	* @param pVM Pointer to the shared VM structure.
710	* @param pRam Pointer to the new list entry.
711	*/
712	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
713	{
714	pgmLock(pVM);
715
716	/* find prev. */
717	PPGMRAMRANGE pPrev = NULL;
718	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
719	while (pCur != pRam)
720	{
721	pPrev = pCur;
722	pCur = pCur->pNextR3;
723	}
724	AssertFatal(pCur);
725
726	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
727	pgmUnlock(pVM);
728	}
729
730
731	/**
732	* Frees a range of pages, replacing them with ZERO pages of the specified type.
733	*
734	* @returns VBox status code.
735	* @param pVM The VM handle.
736	* @param pRam The RAM range in which the pages resides.
737	* @param GCPhys The address of the first page.
738	* @param GCPhysLast The address of the last page.
739	* @param uType The page type to replace then with.
740	*/
741	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
742	{
743	Assert(PGMIsLockOwner(pVM));
744	uint32_t cPendingPages = 0;
745	PGMMFREEPAGESREQ pReq;
746	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
747	AssertLogRelRCReturn(rc, rc);
748
749	/* Iterate the pages. */
750	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
751	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
752	while (cPagesLeft-- > 0)
753	{
754	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
755	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
756
757	PGM_PAGE_SET_TYPE(pPageDst, uType);
758
759	GCPhys += PAGE_SIZE;
760	pPageDst++;
761	}
762
763	if (cPendingPages)
764	{
765	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
766	AssertLogRelRCReturn(rc, rc);
767	}
768	GMMR3FreePagesCleanup(pReq);
769
770	return rc;
771	}
772
773	/**
774	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
775	*
776	* This is only called on one of the EMTs while the other ones are waiting for
777	* it to complete this function.
778	*
779	* @returns VINF_SUCCESS (VBox strict status code).
780	* @param pVM The VM handle.
781	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
782	* @param pvUser User parameter
783	*/
784	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
785	{
786	uintptr_t paUser = (uintptr_t )pvUser;
787	bool fInflate = !!paUser[0];
788	unsigned cPages = paUser[1];
789	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
790	uint32_t cPendingPages = 0;
791	PGMMFREEPAGESREQ pReq;
792	int rc;
793
794	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
795	pgmLock(pVM);
796
797	if (fInflate)
798	{
799	/* Replace pages with ZERO pages. */
800	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
801	if (RT_FAILURE(rc))
802	{
803	pgmUnlock(pVM);
804	AssertLogRelRC(rc);
805	return rc;
806	}
807
808	/* Iterate the pages. */
809	for (unsigned i = 0; i < cPages; i++)
810	{
811	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
812	if ( pPage == NULL
813	\|\| pPage->uTypeY != PGMPAGETYPE_RAM)
814	{
815	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], (pPage) ? pPage->uTypeY : 0));
816	break;
817	}
818
819	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
820
821	/* Flush the shadow PT if this page was previously used as a guest page table. */
822	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
823
824	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i]);
825	if (RT_FAILURE(rc))
826	{
827	pgmUnlock(pVM);
828	AssertLogRelRC(rc);
829	return rc;
830	}
831	Assert(PGM_PAGE_IS_ZERO(pPage));
832	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_BALLOONED);
833	}
834
835	if (cPendingPages)
836	{
837	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
838	if (RT_FAILURE(rc))
839	{
840	pgmUnlock(pVM);
841	AssertLogRelRC(rc);
842	return rc;
843	}
844	}
845	GMMR3FreePagesCleanup(pReq);
846
847	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
848	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
849	}
850	else
851	{
852	/* Iterate the pages. */
853	for (unsigned i = 0; i < cPages; i++)
854	{
855	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
856	AssertBreak(pPage && pPage->uTypeY == PGMPAGETYPE_RAM);
857
858	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
859
860	Assert(PGM_PAGE_IS_BALLOONED(pPage));
861
862	/* Change back to zero page. */
863	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
864	}
865
866	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
867	}
868
869	/* Notify GMM about the balloon change. */
870	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
871	if (RT_SUCCESS(rc))
872	{
873	if (!fInflate)
874	{
875	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
876	pVM->pgm.s.cBalloonedPages -= cPages;
877	}
878	else
879	pVM->pgm.s.cBalloonedPages += cPages;
880	}
881
882	pgmUnlock(pVM);
883
884	/* Flush the recompiler's TLB as well. */
885	for (unsigned i = 0; i < pVM->cCpus; i++)
886	CPUMSetChangedFlags(&pVM->aCpus[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
887
888	AssertLogRelRC(rc);
889	return rc;
890	}
891
892	/**
893	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
894	*
895	* @returns VBox status code.
896	* @param pVM The VM handle.
897	* @param fInflate Inflate or deflate memory balloon
898	* @param cPages Number of pages to free
899	* @param paPhysPage Array of guest physical addresses
900	*/
901	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
902	{
903	uintptr_t paUser[3];
904
905	paUser[0] = fInflate;
906	paUser[1] = cPages;
907	paUser[2] = (uintptr_t)paPhysPage;
908	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
909	AssertRC(rc);
910
911	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
912	RTMemFree(paPhysPage);
913	}
914
915	/**
916	* Inflate or deflate a memory balloon
917	*
918	* @returns VBox status code.
919	* @param pVM The VM handle.
920	* @param fInflate Inflate or deflate memory balloon
921	* @param cPages Number of pages to free
922	* @param paPhysPage Array of guest physical addresses
923	*/
924	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
925	{
926	int rc;
927
928	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
929	* In the SMP case we post a request packet to postpone the job.
930	*/
931	if (pVM->cCpus > 1)
932	{
933	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
934	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
935	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
936
937	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
938
939	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
940	AssertRC(rc);
941	}
942	else
943	{
944	uintptr_t paUser[3];
945
946	paUser[0] = fInflate;
947	paUser[1] = cPages;
948	paUser[2] = (uintptr_t)paPhysPage;
949	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
950	AssertRC(rc);
951	}
952	return rc;
953	}
954
955	/**
956	* Query the VM and host balloon sizes
957	*
958	* @returns VBox status code.
959	* @param pVM The VM handle.
960	* @param puVMBalloonSize Pointer to VM balloon size (in megabytes)
961	* @param puTotalBalloonSize Pointer to total balloon size of all VMs (in megabytes)
962	*/
963	VMMR3DECL(int) PGMR3QueryBalloonSize(PVM pVM, unsigned puVMBalloonSize, unsigned puTotalBalloonSize)
964	{
965	int rc = VINF_SUCCESS;
966
967	if (puVMBalloonSize)
968	puVMBalloonSize = pVM->pgm.s.cBalloonedPages _4K / _1M;
969
970	if (puTotalBalloonSize)
971	{
972	uint64_t cPages = 0;
973	rc = GMMR3QueryTotalBalloonSize(pVM, &cPages);
974	AssertRC(rc);
975	puTotalBalloonSize = (unsigned) (cPages _4K / _1M);
976	}
977
978	return rc;
979	}
980
981	/**
982	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
983	*
984	* @param pVM The VM handle.
985	* @param pNew The new RAM range.
986	* @param GCPhys The address of the RAM range.
987	* @param GCPhysLast The last address of the RAM range.
988	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
989	* if in HMA.
990	* @param R0PtrNew Ditto for R0.
991	* @param pszDesc The description.
992	* @param pPrev The previous RAM range (for linking).
993	*/
994	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
995	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
996	{
997	/*
998	* Initialize the range.
999	*/
1000	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
1001	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
1002	pNew->GCPhys = GCPhys;
1003	pNew->GCPhysLast = GCPhysLast;
1004	pNew->cb = GCPhysLast - GCPhys + 1;
1005	pNew->pszDesc = pszDesc;
1006	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
1007	pNew->pvR3 = NULL;
1008	pNew->paLSPages = NULL;
1009
1010	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1011	RTGCPHYS iPage = cPages;
1012	while (iPage-- > 0)
1013	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1014
1015	/* Update the page count stats. */
1016	pVM->pgm.s.cZeroPages += cPages;
1017	pVM->pgm.s.cAllPages += cPages;
1018
1019	/*
1020	* Link it.
1021	*/
1022	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1023	}
1024
1025
1026	/**
1027	* Relocate a floating RAM range.
1028	*
1029	* @copydoc FNPGMRELOCATE.
1030	*/
1031	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
1032	{
1033	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
1034	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
1035	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
1036
1037	switch (enmMode)
1038	{
1039	case PGMRELOCATECALL_SUGGEST:
1040	return true;
1041	case PGMRELOCATECALL_RELOCATE:
1042	{
1043	/* Update myself and then relink all the ranges. */
1044	pgmLock(pVM);
1045	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
1046	pgmR3PhysRelinkRamRanges(pVM);
1047	pgmUnlock(pVM);
1048	return true;
1049	}
1050
1051	default:
1052	AssertFailedReturn(false);
1053	}
1054	}
1055
1056
1057	/**
1058	* PGMR3PhysRegisterRam worker that registers a high chunk.
1059	*
1060	* @returns VBox status code.
1061	* @param pVM The VM handle.
1062	* @param GCPhys The address of the RAM.
1063	* @param cRamPages The number of RAM pages to register.
1064	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1065	* @param iChunk The chunk number.
1066	* @param pszDesc The RAM range description.
1067	* @param ppPrev Previous RAM range pointer. In/Out.
1068	*/
1069	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1070	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1071	PPGMRAMRANGE *ppPrev)
1072	{
1073	const char *pszDescChunk = iChunk == 0
1074	? pszDesc
1075	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1076	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1077
1078	/*
1079	* Allocate memory for the new chunk.
1080	*/
1081	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1082	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1083	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1084	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1085	void *pvChunk = NULL;
1086	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
1087	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1088	VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
1089	#else
1090	NULL,
1091	#endif
1092	paChunkPages);
1093	if (RT_SUCCESS(rc))
1094	{
1095	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1096	if (!VMMIsHwVirtExtForced(pVM))
1097	R0PtrChunk = NIL_RTR0PTR;
1098	#else
1099	R0PtrChunk = (uintptr_t)pvChunk;
1100	#endif
1101	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1102
1103	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1104
1105	/*
1106	* Create a mapping and map the pages into it.
1107	* We push these in below the HMA.
1108	*/
1109	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1110	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1111	if (RT_SUCCESS(rc))
1112	{
1113	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1114
1115	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1116	RTGCPTR GCPtrPage = GCPtrChunk;
1117	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1118	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1119	if (RT_SUCCESS(rc))
1120	{
1121	/*
1122	* Ok, init and link the range.
1123	*/
1124	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1125	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1126	*ppPrev = pNew;
1127	}
1128	}
1129
1130	if (RT_FAILURE(rc))
1131	SUPR3PageFreeEx(pvChunk, cChunkPages);
1132	}
1133
1134	RTMemTmpFree(paChunkPages);
1135	return rc;
1136	}
1137
1138
1139	/**
1140	* Sets up a range RAM.
1141	*
1142	* This will check for conflicting registrations, make a resource
1143	* reservation for the memory (with GMM), and setup the per-page
1144	* tracking structures (PGMPAGE).
1145	*
1146	* @returns VBox stutus code.
1147	* @param pVM Pointer to the shared VM structure.
1148	* @param GCPhys The physical address of the RAM.
1149	* @param cb The size of the RAM.
1150	* @param pszDesc The description - not copied, so, don't free or change it.
1151	*/
1152	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1153	{
1154	/*
1155	* Validate input.
1156	*/
1157	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1158	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1159	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1160	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1161	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1162	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1163	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1164	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1165
1166	pgmLock(pVM);
1167
1168	/*
1169	* Find range location and check for conflicts.
1170	* (We don't lock here because the locking by EMT is only required on update.)
1171	*/
1172	PPGMRAMRANGE pPrev = NULL;
1173	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1174	while (pRam && GCPhysLast >= pRam->GCPhys)
1175	{
1176	if ( GCPhysLast >= pRam->GCPhys
1177	&& GCPhys <= pRam->GCPhysLast)
1178	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1179	GCPhys, GCPhysLast, pszDesc,
1180	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1181	VERR_PGM_RAM_CONFLICT);
1182
1183	/* next */
1184	pPrev = pRam;
1185	pRam = pRam->pNextR3;
1186	}
1187
1188	/*
1189	* Register it with GMM (the API bitches).
1190	*/
1191	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1192	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1193	if (RT_FAILURE(rc))
1194	{
1195	pgmUnlock(pVM);
1196	return rc;
1197	}
1198
1199	if ( GCPhys >= _4G
1200	&& cPages > 256)
1201	{
1202	/*
1203	* The PGMRAMRANGE structures for the high memory can get very big.
1204	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1205	* allocation size limit there and also to avoid being unable to find
1206	* guest mapping space for them, we split this memory up into 4MB in
1207	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1208	* mode.
1209	*
1210	* The first and last page of each mapping are guard pages and marked
1211	* not-present. So, we've got 4186112 and 16769024 bytes available for
1212	* the PGMRAMRANGE structure.
1213	*
1214	* Note! The sizes used here will influence the saved state.
1215	*/
1216	uint32_t cbChunk;
1217	uint32_t cPagesPerChunk;
1218	if (VMMIsHwVirtExtForced(pVM))
1219	{
1220	cbChunk = 16U*_1M;
1221	cPagesPerChunk = 1048048; /* max ~1048059 */
1222	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1223	}
1224	else
1225	{
1226	cbChunk = 4U*_1M;
1227	cPagesPerChunk = 261616; /* max ~261627 */
1228	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1229	}
1230	AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1231
1232	RTGCPHYS cPagesLeft = cPages;
1233	RTGCPHYS GCPhysChunk = GCPhys;
1234	uint32_t iChunk = 0;
1235	while (cPagesLeft > 0)
1236	{
1237	uint32_t cPagesInChunk = cPagesLeft;
1238	if (cPagesInChunk > cPagesPerChunk)
1239	cPagesInChunk = cPagesPerChunk;
1240
1241	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1242	AssertRCReturn(rc, rc);
1243
1244	/* advance */
1245	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1246	cPagesLeft -= cPagesInChunk;
1247	iChunk++;
1248	}
1249	}
1250	else
1251	{
1252	/*
1253	* Allocate, initialize and link the new RAM range.
1254	*/
1255	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1256	PPGMRAMRANGE pNew;
1257	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1258	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1259
1260	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1261	}
1262	PGMPhysInvalidatePageMapTLB(pVM);
1263	pgmUnlock(pVM);
1264
1265	/*
1266	* Notify REM.
1267	*/
1268	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1269
1270	return VINF_SUCCESS;
1271	}
1272
1273
1274	/**
1275	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1276	*
1277	* We do this late in the init process so that all the ROM and MMIO ranges have
1278	* been registered already and we don't go wasting memory on them.
1279	*
1280	* @returns VBox status code.
1281	*
1282	* @param pVM Pointer to the shared VM structure.
1283	*/
1284	int pgmR3PhysRamPreAllocate(PVM pVM)
1285	{
1286	Assert(pVM->pgm.s.fRamPreAlloc);
1287	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1288
1289	/*
1290	* Walk the RAM ranges and allocate all RAM pages, halt at
1291	* the first allocation error.
1292	*/
1293	uint64_t cPages = 0;
1294	uint64_t NanoTS = RTTimeNanoTS();
1295	pgmLock(pVM);
1296	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1297	{
1298	PPGMPAGE pPage = &pRam->aPages[0];
1299	RTGCPHYS GCPhys = pRam->GCPhys;
1300	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1301	while (cLeft-- > 0)
1302	{
1303	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1304	{
1305	switch (PGM_PAGE_GET_STATE(pPage))
1306	{
1307	case PGM_PAGE_STATE_ZERO:
1308	{
1309	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1310	if (RT_FAILURE(rc))
1311	{
1312	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1313	pgmUnlock(pVM);
1314	return rc;
1315	}
1316	cPages++;
1317	break;
1318	}
1319
1320	case PGM_PAGE_STATE_BALLOONED:
1321	case PGM_PAGE_STATE_ALLOCATED:
1322	case PGM_PAGE_STATE_WRITE_MONITORED:
1323	case PGM_PAGE_STATE_SHARED:
1324	/* nothing to do here. */
1325	break;
1326	}
1327	}
1328
1329	/* next */
1330	pPage++;
1331	GCPhys += PAGE_SIZE;
1332	}
1333	}
1334	pgmUnlock(pVM);
1335	NanoTS = RTTimeNanoTS() - NanoTS;
1336
1337	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1338	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1339	return VINF_SUCCESS;
1340	}
1341
1342
1343	/**
1344	* Resets (zeros) the RAM.
1345	*
1346	* ASSUMES that the caller owns the PGM lock.
1347	*
1348	* @returns VBox status code.
1349	* @param pVM Pointer to the shared VM structure.
1350	*/
1351	int pgmR3PhysRamReset(PVM pVM)
1352	{
1353	Assert(PGMIsLockOwner(pVM));
1354
1355	/* Reset the memory balloon. */
1356	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1357	AssertRC(rc);
1358
1359	/*
1360	* We batch up pages that should be freed instead of calling GMM for
1361	* each and every one of them.
1362	*/
1363	uint32_t cPendingPages = 0;
1364	PGMMFREEPAGESREQ pReq;
1365	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1366	AssertLogRelRCReturn(rc, rc);
1367
1368	/*
1369	* Walk the ram ranges.
1370	*/
1371	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1372	{
1373	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1374	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1375
1376	if (!pVM->pgm.s.fRamPreAlloc)
1377	{
1378	/* Replace all RAM pages by ZERO pages. */
1379	while (iPage-- > 0)
1380	{
1381	PPGMPAGE pPage = &pRam->aPages[iPage];
1382	switch (PGM_PAGE_GET_TYPE(pPage))
1383	{
1384	case PGMPAGETYPE_RAM:
1385	/* Do not replace pages part of a 2 MB continuous range with zero pages, but zero them instead. */
1386	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
1387	{
1388	void *pvPage;
1389	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1390	AssertLogRelRCReturn(rc, rc);
1391	ASMMemZeroPage(pvPage);
1392	}
1393	else
1394	if (PGM_PAGE_IS_BALLOONED(pPage))
1395	{
1396	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1397	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
1398	}
1399	else
1400	if (!PGM_PAGE_IS_ZERO(pPage))
1401	{
1402	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1403	AssertLogRelRCReturn(rc, rc);
1404	}
1405	break;
1406
1407	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1408	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1409	break;
1410
1411	case PGMPAGETYPE_MMIO2:
1412	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1413	case PGMPAGETYPE_ROM:
1414	case PGMPAGETYPE_MMIO:
1415	break;
1416	default:
1417	AssertFailed();
1418	}
1419	} /* for each page */
1420	}
1421	else
1422	{
1423	/* Zero the memory. */
1424	while (iPage-- > 0)
1425	{
1426	PPGMPAGE pPage = &pRam->aPages[iPage];
1427	switch (PGM_PAGE_GET_TYPE(pPage))
1428	{
1429	case PGMPAGETYPE_RAM:
1430	switch (PGM_PAGE_GET_STATE(pPage))
1431	{
1432	case PGM_PAGE_STATE_ZERO:
1433	break;
1434
1435	case PGM_PAGE_STATE_BALLOONED:
1436	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1437	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
1438	break;
1439
1440	case PGM_PAGE_STATE_SHARED:
1441	case PGM_PAGE_STATE_WRITE_MONITORED:
1442	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1443	AssertLogRelRCReturn(rc, rc);
1444	/* no break */
1445
1446	case PGM_PAGE_STATE_ALLOCATED:
1447	{
1448	void *pvPage;
1449	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1450	AssertLogRelRCReturn(rc, rc);
1451	ASMMemZeroPage(pvPage);
1452	break;
1453	}
1454	}
1455	break;
1456
1457	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1458	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1459	break;
1460
1461	case PGMPAGETYPE_MMIO2:
1462	case PGMPAGETYPE_ROM_SHADOW:
1463	case PGMPAGETYPE_ROM:
1464	case PGMPAGETYPE_MMIO:
1465	break;
1466	default:
1467	AssertFailed();
1468
1469	}
1470	} /* for each page */
1471	}
1472
1473	}
1474
1475	/*
1476	* Finish off any pages pending freeing.
1477	*/
1478	if (cPendingPages)
1479	{
1480	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1481	AssertLogRelRCReturn(rc, rc);
1482	}
1483	GMMR3FreePagesCleanup(pReq);
1484
1485	return VINF_SUCCESS;
1486	}
1487
1488
1489	/**
1490	* This is the interface IOM is using to register an MMIO region.
1491	*
1492	* It will check for conflicts and ensure that a RAM range structure
1493	* is present before calling the PGMR3HandlerPhysicalRegister API to
1494	* register the callbacks.
1495	*
1496	* @returns VBox status code.
1497	*
1498	* @param pVM Pointer to the shared VM structure.
1499	* @param GCPhys The start of the MMIO region.
1500	* @param cb The size of the MMIO region.
1501	* @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1502	* @param pvUserR3 The user argument for R3.
1503	* @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1504	* @param pvUserR0 The user argument for R0.
1505	* @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1506	* @param pvUserRC The user argument for RC.
1507	* @param pszDesc The description of the MMIO region.
1508	*/
1509	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1510	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1511	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1512	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1513	R3PTRTYPE(const char *) pszDesc)
1514	{
1515	/*
1516	* Assert on some assumption.
1517	*/
1518	VM_ASSERT_EMT(pVM);
1519	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1520	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1521	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1522	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1523
1524	/*
1525	* Make sure there's a RAM range structure for the region.
1526	*/
1527	int rc;
1528	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1529	bool fRamExists = false;
1530	PPGMRAMRANGE pRamPrev = NULL;
1531	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1532	while (pRam && GCPhysLast >= pRam->GCPhys)
1533	{
1534	if ( GCPhysLast >= pRam->GCPhys
1535	&& GCPhys <= pRam->GCPhysLast)
1536	{
1537	/* Simplification: all within the same range. */
1538	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1539	&& GCPhysLast <= pRam->GCPhysLast,
1540	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1541	GCPhys, GCPhysLast, pszDesc,
1542	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1543	VERR_PGM_RAM_CONFLICT);
1544
1545	/* Check that it's all RAM or MMIO pages. */
1546	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1547	uint32_t cLeft = cb >> PAGE_SHIFT;
1548	while (cLeft-- > 0)
1549	{
1550	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1551	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1552	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1553	GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1554	VERR_PGM_RAM_CONFLICT);
1555	pPage++;
1556	}
1557
1558	/* Looks good. */
1559	fRamExists = true;
1560	break;
1561	}
1562
1563	/* next */
1564	pRamPrev = pRam;
1565	pRam = pRam->pNextR3;
1566	}
1567	PPGMRAMRANGE pNew;
1568	if (fRamExists)
1569	{
1570	pNew = NULL;
1571
1572	/*
1573	* Make all the pages in the range MMIO/ZERO pages, freeing any
1574	* RAM pages currently mapped here. This might not be 100% correct
1575	* for PCI memory, but we're doing the same thing for MMIO2 pages.
1576	*/
1577	rc = pgmLock(pVM);
1578	if (RT_SUCCESS(rc))
1579	{
1580	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1581	pgmUnlock(pVM);
1582	}
1583	AssertRCReturn(rc, rc);
1584	}
1585	else
1586	{
1587	pgmLock(pVM);
1588
1589	/*
1590	* No RAM range, insert an ad hoc one.
1591	*
1592	* Note that we don't have to tell REM about this range because
1593	* PGMHandlerPhysicalRegisterEx will do that for us.
1594	*/
1595	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1596
1597	const uint32_t cPages = cb >> PAGE_SHIFT;
1598	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1599	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1600	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1601
1602	/* Initialize the range. */
1603	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1604	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1605	pNew->GCPhys = GCPhys;
1606	pNew->GCPhysLast = GCPhysLast;
1607	pNew->cb = cb;
1608	pNew->pszDesc = pszDesc;
1609	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
1610	pNew->pvR3 = NULL;
1611	pNew->paLSPages = NULL;
1612
1613	uint32_t iPage = cPages;
1614	while (iPage-- > 0)
1615	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1616	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1617
1618	/* update the page count stats. */
1619	pVM->pgm.s.cPureMmioPages += cPages;
1620	pVM->pgm.s.cAllPages += cPages;
1621
1622	/* link it */
1623	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1624
1625	pgmUnlock(pVM);
1626	}
1627
1628	/*
1629	* Register the access handler.
1630	*/
1631	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1632	pfnHandlerR3, pvUserR3,
1633	pfnHandlerR0, pvUserR0,
1634	pfnHandlerRC, pvUserRC, pszDesc);
1635	if ( RT_FAILURE(rc)
1636	&& !fRamExists)
1637	{
1638	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
1639	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1640
1641	/* remove the ad hoc range. */
1642	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1643	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1644	MMHyperFree(pVM, pRam);
1645	}
1646	PGMPhysInvalidatePageMapTLB(pVM);
1647
1648	return rc;
1649	}
1650
1651
1652	/**
1653	* This is the interface IOM is using to register an MMIO region.
1654	*
1655	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
1656	* any ad hoc PGMRAMRANGE left behind.
1657	*
1658	* @returns VBox status code.
1659	* @param pVM Pointer to the shared VM structure.
1660	* @param GCPhys The start of the MMIO region.
1661	* @param cb The size of the MMIO region.
1662	*/
1663	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1664	{
1665	VM_ASSERT_EMT(pVM);
1666
1667	/*
1668	* First deregister the handler, then check if we should remove the ram range.
1669	*/
1670	int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1671	if (RT_SUCCESS(rc))
1672	{
1673	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1674	PPGMRAMRANGE pRamPrev = NULL;
1675	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1676	while (pRam && GCPhysLast >= pRam->GCPhys)
1677	{
1678	/** @todo We're being a bit too careful here. rewrite. */
1679	if ( GCPhysLast == pRam->GCPhysLast
1680	&& GCPhys == pRam->GCPhys)
1681	{
1682	Assert(pRam->cb == cb);
1683
1684	/*
1685	* See if all the pages are dead MMIO pages.
1686	*/
1687	uint32_t const cPages = cb >> PAGE_SHIFT;
1688	bool fAllMMIO = true;
1689	uint32_t iPage = 0;
1690	uint32_t cLeft = cPages;
1691	while (cLeft-- > 0)
1692	{
1693	PPGMPAGE pPage = &pRam->aPages[iPage];
1694	if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1695	/\|\| not-out-of-action later /)
1696	{
1697	fAllMMIO = false;
1698	Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1699	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1700	break;
1701	}
1702	Assert(PGM_PAGE_IS_ZERO(pPage));
1703	pPage++;
1704	}
1705	if (fAllMMIO)
1706	{
1707	/*
1708	* Ad-hoc range, unlink and free it.
1709	*/
1710	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
1711	GCPhys, GCPhysLast, pRam->pszDesc));
1712
1713	pVM->pgm.s.cAllPages -= cPages;
1714	pVM->pgm.s.cPureMmioPages -= cPages;
1715
1716	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1717	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1718	MMHyperFree(pVM, pRam);
1719	break;
1720	}
1721	}
1722
1723	/*
1724	* Range match? It will all be within one range (see PGMAllHandler.cpp).
1725	*/
1726	if ( GCPhysLast >= pRam->GCPhys
1727	&& GCPhys <= pRam->GCPhysLast)
1728	{
1729	Assert(GCPhys >= pRam->GCPhys);
1730	Assert(GCPhysLast <= pRam->GCPhysLast);
1731
1732	/*
1733	* Turn the pages back into RAM pages.
1734	*/
1735	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1736	uint32_t cLeft = cb >> PAGE_SHIFT;
1737	while (cLeft--)
1738	{
1739	PPGMPAGE pPage = &pRam->aPages[iPage];
1740	AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1741	AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1742	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1743	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1744	}
1745	break;
1746	}
1747
1748	/* next */
1749	pRamPrev = pRam;
1750	pRam = pRam->pNextR3;
1751	}
1752	}
1753
1754	PGMPhysInvalidatePageMapTLB(pVM);
1755	return rc;
1756	}
1757
1758
1759	/**
1760	* Locate a MMIO2 range.
1761	*
1762	* @returns Pointer to the MMIO2 range.
1763	* @param pVM Pointer to the shared VM structure.
1764	* @param pDevIns The device instance owning the region.
1765	* @param iRegion The region.
1766	*/
1767	DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1768	{
1769	/*
1770	* Search the list.
1771	*/
1772	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1773	if ( pCur->pDevInsR3 == pDevIns
1774	&& pCur->iRegion == iRegion)
1775	return pCur;
1776	return NULL;
1777	}
1778
1779
1780	/**
1781	* Allocate and register an MMIO2 region.
1782	*
1783	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1784	* RAM associated with a device. It is also non-shared memory with a
1785	* permanent ring-3 mapping and page backing (presently).
1786	*
1787	* A MMIO2 range may overlap with base memory if a lot of RAM
1788	* is configured for the VM, in which case we'll drop the base
1789	* memory pages. Presently we will make no attempt to preserve
1790	* anything that happens to be present in the base memory that
1791	* is replaced, this is of course incorrectly but it's too much
1792	* effort.
1793	*
1794	* @returns VBox status code.
1795	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1796	* @retval VERR_ALREADY_EXISTS if the region already exists.
1797	*
1798	* @param pVM Pointer to the shared VM structure.
1799	* @param pDevIns The device instance owning the region.
1800	* @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1801	* this number has to be the number of that region. Otherwise
1802	* it can be any number safe UINT8_MAX.
1803	* @param cb The size of the region. Must be page aligned.
1804	* @param fFlags Reserved for future use, must be zero.
1805	* @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1806	* @param pszDesc The description.
1807	*/
1808	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc)
1809	{
1810	/*
1811	* Validate input.
1812	*/
1813	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1814	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1815	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1816	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1817	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1818	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1819	AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1820	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1821	AssertReturn(cb, VERR_INVALID_PARAMETER);
1822	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1823
1824	const uint32_t cPages = cb >> PAGE_SHIFT;
1825	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1826	AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1827
1828	/*
1829	* For the 2nd+ instance, mangle the description string so it's unique.
1830	*/
1831	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
1832	{
1833	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1834	if (!pszDesc)
1835	return VERR_NO_MEMORY;
1836	}
1837
1838	/*
1839	* Try reserve and allocate the backing memory first as this is what is
1840	* most likely to fail.
1841	*/
1842	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1843	if (RT_SUCCESS(rc))
1844	{
1845	void *pvPages;
1846	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1847	if (RT_SUCCESS(rc))
1848	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
1849	if (RT_SUCCESS(rc))
1850	{
1851	memset(pvPages, 0, cPages * PAGE_SIZE);
1852
1853	/*
1854	* Create the MMIO2 range record for it.
1855	*/
1856	const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1857	PPGMMMIO2RANGE pNew;
1858	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1859	AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1860	if (RT_SUCCESS(rc))
1861	{
1862	pNew->pDevInsR3 = pDevIns;
1863	pNew->pvR3 = pvPages;
1864	//pNew->pNext = NULL;
1865	//pNew->fMapped = false;
1866	//pNew->fOverlapping = false;
1867	pNew->iRegion = iRegion;
1868	pNew->idSavedState = UINT8_MAX;
1869	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1870	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1871	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1872	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1873	pNew->RamRange.pszDesc = pszDesc;
1874	pNew->RamRange.cb = cb;
1875	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
1876	pNew->RamRange.pvR3 = pvPages;
1877	//pNew->RamRange.paLSPages = NULL;
1878
1879	uint32_t iPage = cPages;
1880	while (iPage-- > 0)
1881	{
1882	PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1883	paPages[iPage].Phys, NIL_GMM_PAGEID,
1884	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1885	}
1886
1887	/* update page count stats */
1888	pVM->pgm.s.cAllPages += cPages;
1889	pVM->pgm.s.cPrivatePages += cPages;
1890
1891	/*
1892	* Link it into the list.
1893	* Since there is no particular order, just push it.
1894	*/
1895	pgmLock(pVM);
1896	pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1897	pVM->pgm.s.pMmio2RangesR3 = pNew;
1898	pgmUnlock(pVM);
1899
1900	*ppv = pvPages;
1901	RTMemTmpFree(paPages);
1902	PGMPhysInvalidatePageMapTLB(pVM);
1903	return VINF_SUCCESS;
1904	}
1905
1906	SUPR3PageFreeEx(pvPages, cPages);
1907	}
1908	RTMemTmpFree(paPages);
1909	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1910	}
1911	if (pDevIns->iInstance > 0)
1912	MMR3HeapFree((void *)pszDesc);
1913	return rc;
1914	}
1915
1916
1917	/**
1918	* Deregisters and frees an MMIO2 region.
1919	*
1920	* Any physical (and virtual) access handlers registered for the region must
1921	* be deregistered before calling this function.
1922	*
1923	* @returns VBox status code.
1924	* @param pVM Pointer to the shared VM structure.
1925	* @param pDevIns The device instance owning the region.
1926	* @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1927	*/
1928	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1929	{
1930	/*
1931	* Validate input.
1932	*/
1933	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1934	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1935	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1936
1937	pgmLock(pVM);
1938	int rc = VINF_SUCCESS;
1939	unsigned cFound = 0;
1940	PPGMMMIO2RANGE pPrev = NULL;
1941	PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1942	while (pCur)
1943	{
1944	if ( pCur->pDevInsR3 == pDevIns
1945	&& ( iRegion == UINT32_MAX
1946	\|\| pCur->iRegion == iRegion))
1947	{
1948	cFound++;
1949
1950	/*
1951	* Unmap it if it's mapped.
1952	*/
1953	if (pCur->fMapped)
1954	{
1955	int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1956	AssertRC(rc2);
1957	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1958	rc = rc2;
1959	}
1960
1961	/*
1962	* Unlink it
1963	*/
1964	PPGMMMIO2RANGE pNext = pCur->pNextR3;
1965	if (pPrev)
1966	pPrev->pNextR3 = pNext;
1967	else
1968	pVM->pgm.s.pMmio2RangesR3 = pNext;
1969	pCur->pNextR3 = NULL;
1970
1971	/*
1972	* Free the memory.
1973	*/
1974	int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1975	AssertRC(rc2);
1976	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1977	rc = rc2;
1978
1979	uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1980	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1981	AssertRC(rc2);
1982	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1983	rc = rc2;
1984
1985	/* we're leaking hyper memory here if done at runtime. */
1986	#ifdef VBOX_STRICT
1987	VMSTATE const enmState = VMR3GetState(pVM);
1988	AssertMsg( enmState == VMSTATE_POWERING_OFF
1989	\|\| enmState == VMSTATE_POWERING_OFF_LS
1990	\|\| enmState == VMSTATE_OFF
1991	\|\| enmState == VMSTATE_OFF_LS
1992	\|\| enmState == VMSTATE_DESTROYING
1993	\|\| enmState == VMSTATE_TERMINATED
1994	\|\| enmState == VMSTATE_CREATING
1995	, ("%s\n", VMR3GetStateName(enmState)));
1996	#endif
1997	/*rc = MMHyperFree(pVM, pCur);
1998	AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1999
2000
2001	/* update page count stats */
2002	pVM->pgm.s.cAllPages -= cPages;
2003	pVM->pgm.s.cPrivatePages -= cPages;
2004
2005	/* next */
2006	pCur = pNext;
2007	}
2008	else
2009	{
2010	pPrev = pCur;
2011	pCur = pCur->pNextR3;
2012	}
2013	}
2014	PGMPhysInvalidatePageMapTLB(pVM);
2015	pgmUnlock(pVM);
2016	return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
2017	}
2018
2019
2020	/**
2021	* Maps a MMIO2 region.
2022	*
2023	* This is done when a guest / the bios / state loading changes the
2024	* PCI config. The replacing of base memory has the same restrictions
2025	* as during registration, of course.
2026	*
2027	* @returns VBox status code.
2028	*
2029	* @param pVM Pointer to the shared VM structure.
2030	* @param pDevIns The
2031	*/
2032	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2033	{
2034	/*
2035	* Validate input
2036	*/
2037	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2038	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2039	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2040	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2041	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2042	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2043
2044	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2045	AssertReturn(pCur, VERR_NOT_FOUND);
2046	AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
2047	Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
2048	Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
2049
2050	const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
2051	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2052
2053	/*
2054	* Find our location in the ram range list, checking for
2055	* restriction we don't bother implementing yet (partially overlapping).
2056	*/
2057	bool fRamExists = false;
2058	PPGMRAMRANGE pRamPrev = NULL;
2059	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2060	while (pRam && GCPhysLast >= pRam->GCPhys)
2061	{
2062	if ( GCPhys <= pRam->GCPhysLast
2063	&& GCPhysLast >= pRam->GCPhys)
2064	{
2065	/* completely within? */
2066	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2067	&& GCPhysLast <= pRam->GCPhysLast,
2068	("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
2069	GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
2070	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2071	VERR_PGM_RAM_CONFLICT);
2072	fRamExists = true;
2073	break;
2074	}
2075
2076	/* next */
2077	pRamPrev = pRam;
2078	pRam = pRam->pNextR3;
2079	}
2080	if (fRamExists)
2081	{
2082	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2083	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2084	while (cPagesLeft-- > 0)
2085	{
2086	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2087	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
2088	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
2089	VERR_PGM_RAM_CONFLICT);
2090	pPage++;
2091	}
2092	}
2093	Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
2094	GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
2095
2096	/*
2097	* Make the changes.
2098	*/
2099	pgmLock(pVM);
2100
2101	pCur->RamRange.GCPhys = GCPhys;
2102	pCur->RamRange.GCPhysLast = GCPhysLast;
2103	pCur->fMapped = true;
2104	pCur->fOverlapping = fRamExists;
2105
2106	if (fRamExists)
2107	{
2108	/** @todo use pgmR3PhysFreePageRange here. */
2109	uint32_t cPendingPages = 0;
2110	PGMMFREEPAGESREQ pReq;
2111	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2112	AssertLogRelRCReturn(rc, rc);
2113
2114	/* replace the pages, freeing all present RAM pages. */
2115	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2116	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2117	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2118	while (cPagesLeft-- > 0)
2119	{
2120	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
2121	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
2122
2123	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
2124	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
2125	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
2126	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
2127
2128	pVM->pgm.s.cZeroPages--;
2129	GCPhys += PAGE_SIZE;
2130	pPageSrc++;
2131	pPageDst++;
2132	}
2133
2134	/* Flush physical page map TLB. */
2135	PGMPhysInvalidatePageMapTLB(pVM);
2136
2137	if (cPendingPages)
2138	{
2139	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2140	AssertLogRelRCReturn(rc, rc);
2141	}
2142	GMMR3FreePagesCleanup(pReq);
2143	pgmUnlock(pVM);
2144	}
2145	else
2146	{
2147	RTGCPHYS cb = pCur->RamRange.cb;
2148
2149	/* link in the ram range */
2150	pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
2151	pgmUnlock(pVM);
2152
2153	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
2154	}
2155
2156	PGMPhysInvalidatePageMapTLB(pVM);
2157	return VINF_SUCCESS;
2158	}
2159
2160
2161	/**
2162	* Unmaps a MMIO2 region.
2163	*
2164	* This is done when a guest / the bios / state loading changes the
2165	* PCI config. The replacing of base memory has the same restrictions
2166	* as during registration, of course.
2167	*/
2168	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2169	{
2170	/*
2171	* Validate input
2172	*/
2173	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2174	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2175	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2176	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2177	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2178	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2179
2180	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2181	AssertReturn(pCur, VERR_NOT_FOUND);
2182	AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
2183	AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
2184	Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
2185
2186	Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
2187	pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
2188
2189	/*
2190	* Unmap it.
2191	*/
2192	pgmLock(pVM);
2193
2194	RTGCPHYS GCPhysRangeREM;
2195	RTGCPHYS cbRangeREM;
2196	bool fInformREM;
2197	if (pCur->fOverlapping)
2198	{
2199	/* Restore the RAM pages we've replaced. */
2200	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2201	while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
2202	pRam = pRam->pNextR3;
2203
2204	RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
2205	Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
2206	PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2207	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2208	while (cPagesLeft-- > 0)
2209	{
2210	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
2211	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
2212	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
2213	PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
2214	PGM_PAGE_SET_PDE_TYPE(pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
2215
2216	pVM->pgm.s.cZeroPages++;
2217	pPageDst++;
2218	}
2219
2220	/* Flush physical page map TLB. */
2221	PGMPhysInvalidatePageMapTLB(pVM);
2222
2223	GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
2224	cbRangeREM = RTGCPHYS_MAX; /* ditto */
2225	fInformREM = false;
2226	}
2227	else
2228	{
2229	GCPhysRangeREM = pCur->RamRange.GCPhys;
2230	cbRangeREM = pCur->RamRange.cb;
2231	fInformREM = true;
2232
2233	pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
2234	}
2235
2236	pCur->RamRange.GCPhys = NIL_RTGCPHYS;
2237	pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
2238	pCur->fOverlapping = false;
2239	pCur->fMapped = false;
2240
2241	PGMPhysInvalidatePageMapTLB(pVM);
2242	pgmUnlock(pVM);
2243
2244	if (fInformREM)
2245	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2246
2247	return VINF_SUCCESS;
2248	}
2249
2250
2251	/**
2252	* Checks if the given address is an MMIO2 base address or not.
2253	*
2254	* @returns true/false accordingly.
2255	* @param pVM Pointer to the shared VM structure.
2256	* @param pDevIns The owner of the memory, optional.
2257	* @param GCPhys The address to check.
2258	*/
2259	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2260	{
2261	/*
2262	* Validate input
2263	*/
2264	VM_ASSERT_EMT_RETURN(pVM, false);
2265	AssertPtrReturn(pDevIns, false);
2266	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
2267	AssertReturn(GCPhys != 0, false);
2268	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
2269
2270	/*
2271	* Search the list.
2272	*/
2273	pgmLock(pVM);
2274	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2275	if (pCur->RamRange.GCPhys == GCPhys)
2276	{
2277	Assert(pCur->fMapped);
2278	pgmUnlock(pVM);
2279	return true;
2280	}
2281	pgmUnlock(pVM);
2282	return false;
2283	}
2284
2285
2286	/**
2287	* Gets the HC physical address of a page in the MMIO2 region.
2288	*
2289	* This is API is intended for MMHyper and shouldn't be called
2290	* by anyone else...
2291	*
2292	* @returns VBox status code.
2293	* @param pVM Pointer to the shared VM structure.
2294	* @param pDevIns The owner of the memory, optional.
2295	* @param iRegion The region.
2296	* @param off The page expressed an offset into the MMIO2 region.
2297	* @param pHCPhys Where to store the result.
2298	*/
2299	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2300	{
2301	/*
2302	* Validate input
2303	*/
2304	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2305	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2306	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2307
2308	pgmLock(pVM);
2309	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2310	AssertReturn(pCur, VERR_NOT_FOUND);
2311	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2312
2313	PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2314	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2315	pgmUnlock(pVM);
2316	return VINF_SUCCESS;
2317	}
2318
2319
2320	/**
2321	* Maps a portion of an MMIO2 region into kernel space (host).
2322	*
2323	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
2324	* or the VM is terminated.
2325	*
2326	* @return VBox status code.
2327	*
2328	* @param pVM Pointer to the shared VM structure.
2329	* @param pDevIns The device owning the MMIO2 memory.
2330	* @param iRegion The region.
2331	* @param off The offset into the region. Must be page aligned.
2332	* @param cb The number of bytes to map. Must be page aligned.
2333	* @param pszDesc Mapping description.
2334	* @param pR0Ptr Where to store the R0 address.
2335	*/
2336	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2337	const char *pszDesc, PRTR0PTR pR0Ptr)
2338	{
2339	/*
2340	* Validate input.
2341	*/
2342	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2343	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2344	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2345
2346	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2347	AssertReturn(pCur, VERR_NOT_FOUND);
2348	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2349	AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2350	AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2351
2352	/*
2353	* Pass the request on to the support library/driver.
2354	*/
2355	int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2356
2357	return rc;
2358	}
2359
2360
2361	/**
2362	* Registers a ROM image.
2363	*
2364	* Shadowed ROM images requires double the amount of backing memory, so,
2365	* don't use that unless you have to. Shadowing of ROM images is process
2366	* where we can select where the reads go and where the writes go. On real
2367	* hardware the chipset provides means to configure this. We provide
2368	* PGMR3PhysProtectROM() for this purpose.
2369	*
2370	* A read-only copy of the ROM image will always be kept around while we
2371	* will allocate RAM pages for the changes on demand (unless all memory
2372	* is configured to be preallocated).
2373	*
2374	* @returns VBox status.
2375	* @param pVM VM Handle.
2376	* @param pDevIns The device instance owning the ROM.
2377	* @param GCPhys First physical address in the range.
2378	* Must be page aligned!
2379	* @param cbRange The size of the range (in bytes).
2380	* Must be page aligned!
2381	* @param pvBinary Pointer to the binary data backing the ROM image.
2382	* This must be exactly \a cbRange in size.
2383	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2384	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2385	* @param pszDesc Pointer to description string. This must not be freed.
2386	*
2387	* @remark There is no way to remove the rom, automatically on device cleanup or
2388	* manually from the device yet. This isn't difficult in any way, it's
2389	* just not something we expect to be necessary for a while.
2390	*/
2391	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2392	const void pvBinary, uint32_t fFlags, const char pszDesc)
2393	{
2394	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2395	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2396
2397	/*
2398	* Validate input.
2399	*/
2400	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2401	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2402	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2403	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2404	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2405	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2406	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2407	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2408	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2409
2410	const uint32_t cPages = cb >> PAGE_SHIFT;
2411
2412	/*
2413	* Find the ROM location in the ROM list first.
2414	*/
2415	PPGMROMRANGE pRomPrev = NULL;
2416	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2417	while (pRom && GCPhysLast >= pRom->GCPhys)
2418	{
2419	if ( GCPhys <= pRom->GCPhysLast
2420	&& GCPhysLast >= pRom->GCPhys)
2421	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2422	GCPhys, GCPhysLast, pszDesc,
2423	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2424	VERR_PGM_RAM_CONFLICT);
2425	/* next */
2426	pRomPrev = pRom;
2427	pRom = pRom->pNextR3;
2428	}
2429
2430	/*
2431	* Find the RAM location and check for conflicts.
2432	*
2433	* Conflict detection is a bit different than for RAM
2434	* registration since a ROM can be located within a RAM
2435	* range. So, what we have to check for is other memory
2436	* types (other than RAM that is) and that we don't span
2437	* more than one RAM range (layz).
2438	*/
2439	bool fRamExists = false;
2440	PPGMRAMRANGE pRamPrev = NULL;
2441	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2442	while (pRam && GCPhysLast >= pRam->GCPhys)
2443	{
2444	if ( GCPhys <= pRam->GCPhysLast
2445	&& GCPhysLast >= pRam->GCPhys)
2446	{
2447	/* completely within? */
2448	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2449	&& GCPhysLast <= pRam->GCPhysLast,
2450	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2451	GCPhys, GCPhysLast, pszDesc,
2452	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2453	VERR_PGM_RAM_CONFLICT);
2454	fRamExists = true;
2455	break;
2456	}
2457
2458	/* next */
2459	pRamPrev = pRam;
2460	pRam = pRam->pNextR3;
2461	}
2462	if (fRamExists)
2463	{
2464	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2465	uint32_t cPagesLeft = cPages;
2466	while (cPagesLeft-- > 0)
2467	{
2468	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2469	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2470	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2471	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2472	Assert(PGM_PAGE_IS_ZERO(pPage));
2473	pPage++;
2474	}
2475	}
2476
2477	/*
2478	* Update the base memory reservation if necessary.
2479	*/
2480	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
2481	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2482	cExtraBaseCost += cPages;
2483	if (cExtraBaseCost)
2484	{
2485	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2486	if (RT_FAILURE(rc))
2487	return rc;
2488	}
2489
2490	/*
2491	* Allocate memory for the virgin copy of the RAM.
2492	*/
2493	PGMMALLOCATEPAGESREQ pReq;
2494	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2495	AssertRCReturn(rc, rc);
2496
2497	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2498	{
2499	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2500	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2501	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2502	}
2503
2504	pgmLock(pVM);
2505	rc = GMMR3AllocatePagesPerform(pVM, pReq);
2506	pgmUnlock(pVM);
2507	if (RT_FAILURE(rc))
2508	{
2509	GMMR3AllocatePagesCleanup(pReq);
2510	return rc;
2511	}
2512
2513	/*
2514	* Allocate the new ROM range and RAM range (if necessary).
2515	*/
2516	PPGMROMRANGE pRomNew;
2517	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2518	if (RT_SUCCESS(rc))
2519	{
2520	PPGMRAMRANGE pRamNew = NULL;
2521	if (!fRamExists)
2522	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2523	if (RT_SUCCESS(rc))
2524	{
2525	pgmLock(pVM);
2526
2527	/*
2528	* Initialize and insert the RAM range (if required).
2529	*/
2530	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2531	if (!fRamExists)
2532	{
2533	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2534	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2535	pRamNew->GCPhys = GCPhys;
2536	pRamNew->GCPhysLast = GCPhysLast;
2537	pRamNew->cb = cb;
2538	pRamNew->pszDesc = pszDesc;
2539	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
2540	pRamNew->pvR3 = NULL;
2541	pRamNew->paLSPages = NULL;
2542
2543	PPGMPAGE pPage = &pRamNew->aPages[0];
2544	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2545	{
2546	PGM_PAGE_INIT(pPage,
2547	pReq->aPages[iPage].HCPhysGCPhys,
2548	pReq->aPages[iPage].idPage,
2549	PGMPAGETYPE_ROM,
2550	PGM_PAGE_STATE_ALLOCATED);
2551
2552	pRomPage->Virgin = *pPage;
2553	}
2554
2555	pVM->pgm.s.cAllPages += cPages;
2556	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2557	}
2558	else
2559	{
2560	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2561	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2562	{
2563	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2564	PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2565	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2566	PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2567
2568	pRomPage->Virgin = *pPage;
2569	}
2570
2571	pRamNew = pRam;
2572
2573	pVM->pgm.s.cZeroPages -= cPages;
2574	}
2575	pVM->pgm.s.cPrivatePages += cPages;
2576
2577	/* Flush physical page map TLB. */
2578	PGMPhysInvalidatePageMapTLB(pVM);
2579
2580	pgmUnlock(pVM);
2581
2582
2583	/*
2584	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2585	*
2586	* If it's shadowed we'll register the handler after the ROM notification
2587	* so we get the access handler callbacks that we should. If it isn't
2588	* shadowed we'll do it the other way around to make REM use the built-in
2589	* ROM behavior and not the handler behavior (which is to route all access
2590	* to PGM atm).
2591	*/
2592	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2593	{
2594	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2595	rc = PGMR3HandlerPhysicalRegister(pVM,
2596	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2597	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2598	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2599	GCPhys, GCPhysLast,
2600	pgmR3PhysRomWriteHandler, pRomNew,
2601	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2602	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2603	}
2604	else
2605	{
2606	rc = PGMR3HandlerPhysicalRegister(pVM,
2607	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2608	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2609	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2610	GCPhys, GCPhysLast,
2611	pgmR3PhysRomWriteHandler, pRomNew,
2612	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2613	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2614	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2615	}
2616	if (RT_SUCCESS(rc))
2617	{
2618	pgmLock(pVM);
2619
2620	/*
2621	* Copy the image over to the virgin pages.
2622	* This must be done after linking in the RAM range.
2623	*/
2624	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2625	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2626	{
2627	void *pvDstPage;
2628	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
2629	if (RT_FAILURE(rc))
2630	{
2631	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2632	break;
2633	}
2634	memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2635	}
2636	if (RT_SUCCESS(rc))
2637	{
2638	/*
2639	* Initialize the ROM range.
2640	* Note that the Virgin member of the pages has already been initialized above.
2641	*/
2642	pRomNew->GCPhys = GCPhys;
2643	pRomNew->GCPhysLast = GCPhysLast;
2644	pRomNew->cb = cb;
2645	pRomNew->fFlags = fFlags;
2646	pRomNew->idSavedState = UINT8_MAX;
2647	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2648	pRomNew->pszDesc = pszDesc;
2649
2650	for (unsigned iPage = 0; iPage < cPages; iPage++)
2651	{
2652	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2653	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2654	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2655	}
2656
2657	/* update the page count stats for the shadow pages. */
2658	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2659	{
2660	pVM->pgm.s.cZeroPages += cPages;
2661	pVM->pgm.s.cAllPages += cPages;
2662	}
2663
2664	/*
2665	* Insert the ROM range, tell REM and return successfully.
2666	*/
2667	pRomNew->pNextR3 = pRom;
2668	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2669	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2670
2671	if (pRomPrev)
2672	{
2673	pRomPrev->pNextR3 = pRomNew;
2674	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2675	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2676	}
2677	else
2678	{
2679	pVM->pgm.s.pRomRangesR3 = pRomNew;
2680	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2681	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2682	}
2683
2684	PGMPhysInvalidatePageMapTLB(pVM);
2685	GMMR3AllocatePagesCleanup(pReq);
2686	pgmUnlock(pVM);
2687	return VINF_SUCCESS;
2688	}
2689
2690	/* bail out */
2691
2692	pgmUnlock(pVM);
2693	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2694	AssertRC(rc2);
2695	pgmLock(pVM);
2696	}
2697
2698	if (!fRamExists)
2699	{
2700	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2701	MMHyperFree(pVM, pRamNew);
2702	}
2703	}
2704	MMHyperFree(pVM, pRomNew);
2705	}
2706
2707	/** @todo Purge the mapping cache or something... */
2708	GMMR3FreeAllocatedPages(pVM, pReq);
2709	GMMR3AllocatePagesCleanup(pReq);
2710	pgmUnlock(pVM);
2711	return rc;
2712	}
2713
2714
2715	/**
2716	* \#PF Handler callback for ROM write accesses.
2717	*
2718	* @returns VINF_SUCCESS if the handler have carried out the operation.
2719	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2720	* @param pVM VM Handle.
2721	* @param GCPhys The physical address the guest is writing to.
2722	* @param pvPhys The HC mapping of that address.
2723	* @param pvBuf What the guest is reading/writing.
2724	* @param cbBuf How much it's reading/writing.
2725	* @param enmAccessType The access type.
2726	* @param pvUser User argument.
2727	*/
2728	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2729	{
2730	PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2731	const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2732	Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2733	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2734	Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2735
2736	if (enmAccessType == PGMACCESSTYPE_READ)
2737	{
2738	switch (pRomPage->enmProt)
2739	{
2740	/*
2741	* Take the default action.
2742	*/
2743	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2744	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2745	case PGMROMPROT_READ_ROM_WRITE_RAM:
2746	case PGMROMPROT_READ_RAM_WRITE_RAM:
2747	return VINF_PGM_HANDLER_DO_DEFAULT;
2748
2749	default:
2750	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2751	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2752	VERR_INTERNAL_ERROR);
2753	}
2754	}
2755	else
2756	{
2757	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2758	switch (pRomPage->enmProt)
2759	{
2760	/*
2761	* Ignore writes.
2762	*/
2763	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2764	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2765	return VINF_SUCCESS;
2766
2767	/*
2768	* Write to the ram page.
2769	*/
2770	case PGMROMPROT_READ_ROM_WRITE_RAM:
2771	case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's way simpler that way. */
2772	{
2773	/* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2774	Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2775
2776	/*
2777	* Take the lock, do lazy allocation, map the page and copy the data.
2778	*
2779	* Note that we have to bypass the mapping TLB since it works on
2780	* guest physical addresses and entering the shadow page would
2781	* kind of screw things up...
2782	*/
2783	int rc = pgmLock(pVM);
2784	AssertRC(rc);
2785
2786	PPGMPAGE pShadowPage = &pRomPage->Shadow;
2787	if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2788	{
2789	pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2790	AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2791	}
2792
2793	void *pvDstPage;
2794	rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
2795	if (RT_SUCCESS(rc))
2796	{
2797	memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2798	pRomPage->LiveSave.fWrittenTo = true;
2799	}
2800
2801	pgmUnlock(pVM);
2802	return rc;
2803	}
2804
2805	default:
2806	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2807	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2808	VERR_INTERNAL_ERROR);
2809	}
2810	}
2811	}
2812
2813
2814	/**
2815	* Called by PGMR3Reset to reset the shadow, switch to the virgin,
2816	* and verify that the virgin part is untouched.
2817	*
2818	* This is done after the normal memory has been cleared.
2819	*
2820	* ASSUMES that the caller owns the PGM lock.
2821	*
2822	* @param pVM The VM handle.
2823	*/
2824	int pgmR3PhysRomReset(PVM pVM)
2825	{
2826	Assert(PGMIsLockOwner(pVM));
2827	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2828	{
2829	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2830
2831	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2832	{
2833	/*
2834	* Reset the physical handler.
2835	*/
2836	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2837	AssertRCReturn(rc, rc);
2838
2839	/*
2840	* What we do with the shadow pages depends on the memory
2841	* preallocation option. If not enabled, we'll just throw
2842	* out all the dirty pages and replace them by the zero page.
2843	*/
2844	if (!pVM->pgm.s.fRamPreAlloc)
2845	{
2846	/* Free the dirty pages. */
2847	uint32_t cPendingPages = 0;
2848	PGMMFREEPAGESREQ pReq;
2849	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2850	AssertRCReturn(rc, rc);
2851
2852	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2853	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
2854	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
2855	{
2856	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2857	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2858	AssertLogRelRCReturn(rc, rc);
2859	}
2860
2861	if (cPendingPages)
2862	{
2863	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2864	AssertLogRelRCReturn(rc, rc);
2865	}
2866	GMMR3FreePagesCleanup(pReq);
2867	}
2868	else
2869	{
2870	/* clear all the shadow pages. */
2871	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2872	{
2873	Assert(!PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
2874	void *pvDstPage;
2875	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2876	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
2877	if (RT_FAILURE(rc))
2878	break;
2879	ASMMemZeroPage(pvDstPage);
2880	}
2881	AssertRCReturn(rc, rc);
2882	}
2883	}
2884
2885	#ifdef VBOX_STRICT
2886	/*
2887	* Verify that the virgin page is unchanged if possible.
2888	*/
2889	if (pRom->pvOriginal)
2890	{
2891	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
2892	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2893	{
2894	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2895	void const *pvDstPage;
2896	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
2897	if (RT_FAILURE(rc))
2898	break;
2899	if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2900	LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2901	GCPhys, pRom->pszDesc));
2902	}
2903	}
2904	#endif
2905	}
2906
2907	return VINF_SUCCESS;
2908	}
2909
2910
2911	/**
2912	* Change the shadowing of a range of ROM pages.
2913	*
2914	* This is intended for implementing chipset specific memory registers
2915	* and will not be very strict about the input. It will silently ignore
2916	* any pages that are not the part of a shadowed ROM.
2917	*
2918	* @returns VBox status code.
2919	* @retval VINF_PGM_SYNC_CR3
2920	*
2921	* @param pVM Pointer to the shared VM structure.
2922	* @param GCPhys Where to start. Page aligned.
2923	* @param cb How much to change. Page aligned.
2924	* @param enmProt The new ROM protection.
2925	*/
2926	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2927	{
2928	/*
2929	* Check input
2930	*/
2931	if (!cb)
2932	return VINF_SUCCESS;
2933	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2934	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2935	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2936	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2937	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2938
2939	/*
2940	* Process the request.
2941	*/
2942	pgmLock(pVM);
2943	int rc = VINF_SUCCESS;
2944	bool fFlushTLB = false;
2945	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2946	{
2947	if ( GCPhys <= pRom->GCPhysLast
2948	&& GCPhysLast >= pRom->GCPhys
2949	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2950	{
2951	/*
2952	* Iterate the relevant pages and make necessary the changes.
2953	*/
2954	bool fChanges = false;
2955	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2956	? pRom->cb >> PAGE_SHIFT
2957	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2958	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2959	iPage < cPages;
2960	iPage++)
2961	{
2962	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2963	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2964	{
2965	fChanges = true;
2966
2967	/* flush references to the page. */
2968	PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2969	int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage, &fFlushTLB);
2970	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
2971	rc = rc2;
2972
2973	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2974	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2975
2976	pOld = pRamPage;
2977	pRamPage = pNew;
2978	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2979	}
2980	pRomPage->enmProt = enmProt;
2981	}
2982
2983	/*
2984	* Reset the access handler if we made changes, no need
2985	* to optimize this.
2986	*/
2987	if (fChanges)
2988	{
2989	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2990	if (RT_FAILURE(rc2))
2991	{
2992	pgmUnlock(pVM);
2993	AssertRC(rc);
2994	return rc2;
2995	}
2996	}
2997
2998	/* Advance - cb isn't updated. */
2999	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
3000	}
3001	}
3002	pgmUnlock(pVM);
3003	if (fFlushTLB)
3004	PGM_INVL_ALL_VCPU_TLBS(pVM);
3005
3006	return rc;
3007	}
3008
3009
3010	/**
3011	* Sets the Address Gate 20 state.
3012	*
3013	* @param pVCpu The VCPU to operate on.
3014	* @param fEnable True if the gate should be enabled.
3015	* False if the gate should be disabled.
3016	*/
3017	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
3018	{
3019	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
3020	if (pVCpu->pgm.s.fA20Enabled != fEnable)
3021	{
3022	pVCpu->pgm.s.fA20Enabled = fEnable;
3023	pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
3024	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
3025	/** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
3026	}
3027	}
3028
3029
3030	/**
3031	* Tree enumeration callback for dealing with age rollover.
3032	* It will perform a simple compression of the current age.
3033	*/
3034	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
3035	{
3036	Assert(PGMIsLockOwner((PVM)pvUser));
3037	/* Age compression - ASSUMES iNow == 4. */
3038	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3039	if (pChunk->iAge >= UINT32_C(0xffffff00))
3040	pChunk->iAge = 3;
3041	else if (pChunk->iAge >= UINT32_C(0xfffff000))
3042	pChunk->iAge = 2;
3043	else if (pChunk->iAge)
3044	pChunk->iAge = 1;
3045	else /* iAge = 0 */
3046	pChunk->iAge = 4;
3047
3048	/* reinsert */
3049	PVM pVM = (PVM)pvUser;
3050	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
3051	pChunk->AgeCore.Key = pChunk->iAge;
3052	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3053	return 0;
3054	}
3055
3056
3057	/**
3058	* Tree enumeration callback that updates the chunks that have
3059	* been used since the last
3060	*/
3061	static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
3062	{
3063	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3064	if (!pChunk->iAge)
3065	{
3066	PVM pVM = (PVM)pvUser;
3067	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
3068	pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
3069	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3070	}
3071
3072	return 0;
3073	}
3074
3075
3076	/**
3077	* Performs ageing of the ring-3 chunk mappings.
3078	*
3079	* @param pVM The VM handle.
3080	*/
3081	VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
3082	{
3083	pgmLock(pVM);
3084	pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
3085	pVM->pgm.s.ChunkR3Map.iNow++;
3086	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
3087	{
3088	pVM->pgm.s.ChunkR3Map.iNow = 4;
3089	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
3090	}
3091	else
3092	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingCallback, pVM);
3093	pgmUnlock(pVM);
3094	}
3095
3096
3097	/**
3098	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
3099	*/
3100	typedef struct PGMR3PHYSCHUNKUNMAPCB
3101	{
3102	PVM pVM; /*< The VM handle. /
3103	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
3104	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
3105
3106
3107	/**
3108	* Callback used to find the mapping that's been unused for
3109	* the longest time.
3110	*/
3111	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
3112	{
3113	do
3114	{
3115	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
3116	if ( pChunk->iAge
3117	&& !pChunk->cRefs)
3118	{
3119	/*
3120	* Check that it's not in any of the TLBs.
3121	*/
3122	PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
3123	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3124	if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
3125	{
3126	pChunk = NULL;
3127	break;
3128	}
3129	if (pChunk)
3130	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
3131	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
3132	{
3133	pChunk = NULL;
3134	break;
3135	}
3136	if (pChunk)
3137	{
3138	((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
3139	return 1; /* done */
3140	}
3141	}
3142
3143	/* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
3144	pNode = pNode->pList;
3145	} while (pNode);
3146	return 0;
3147	}
3148
3149
3150	/**
3151	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
3152	*
3153	* The candidate will not be part of any TLBs, so no need to flush
3154	* anything afterwards.
3155	*
3156	* @returns Chunk id.
3157	* @param pVM The VM handle.
3158	*/
3159	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
3160	{
3161	Assert(PGMIsLockOwner(pVM));
3162
3163	/*
3164	* Do tree ageing first?
3165	*/
3166	if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
3167	PGMR3PhysChunkAgeing(pVM);
3168
3169	/*
3170	* Enumerate the age tree starting with the left most node.
3171	*/
3172	PGMR3PHYSCHUNKUNMAPCB Args;
3173	Args.pVM = pVM;
3174	Args.pChunk = NULL;
3175	if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
3176	return Args.pChunk->Core.Key;
3177	return INT32_MAX;
3178	}
3179
3180
3181	/**
3182	* Maps the given chunk into the ring-3 mapping cache.
3183	*
3184	* This will call ring-0.
3185	*
3186	* @returns VBox status code.
3187	* @param pVM The VM handle.
3188	* @param idChunk The chunk in question.
3189	* @param ppChunk Where to store the chunk tracking structure.
3190	*
3191	* @remarks Called from within the PGM critical section.
3192	*/
3193	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
3194	{
3195	int rc;
3196
3197	Assert(PGMIsLockOwner(pVM));
3198	/*
3199	* Allocate a new tracking structure first.
3200	*/
3201	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3202	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
3203	#else
3204	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
3205	#endif
3206	AssertReturn(pChunk, VERR_NO_MEMORY);
3207	pChunk->Core.Key = idChunk;
3208	pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
3209	pChunk->iAge = 0;
3210	pChunk->cRefs = 0;
3211	pChunk->cPermRefs = 0;
3212	pChunk->pv = NULL;
3213
3214	/*
3215	* Request the ring-0 part to map the chunk in question and if
3216	* necessary unmap another one to make space in the mapping cache.
3217	*/
3218	GMMMAPUNMAPCHUNKREQ Req;
3219	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3220	Req.Hdr.cbReq = sizeof(Req);
3221	Req.pvR3 = NULL;
3222	Req.idChunkMap = idChunk;
3223	Req.idChunkUnmap = NIL_GMM_CHUNKID;
3224	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3225	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
3226	/** @todo This is wrong. Any thread in the VM process should be able to do this,
3227	* there are depenenecies on this. What currently saves the day is that
3228	* we don't unmap anything and that all non-zero memory will therefore
3229	* be present when non-EMTs tries to access it. */
3230	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3231	if (RT_SUCCESS(rc))
3232	{
3233	/*
3234	* Update the tree.
3235	*/
3236	/* insert the new one. */
3237	AssertPtr(Req.pvR3);
3238	pChunk->pv = Req.pvR3;
3239	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
3240	AssertRelease(fRc);
3241	pVM->pgm.s.ChunkR3Map.c++;
3242
3243	fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3244	AssertRelease(fRc);
3245
3246	/* remove the unmapped one. */
3247	if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
3248	{
3249	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
3250	AssertRelease(pUnmappedChunk);
3251	pUnmappedChunk->pv = NULL;
3252	pUnmappedChunk->Core.Key = UINT32_MAX;
3253	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3254	MMR3HeapFree(pUnmappedChunk);
3255	#else
3256	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3257	#endif
3258	pVM->pgm.s.ChunkR3Map.c--;
3259
3260	/* Chunk removed, so clear the page map TBL as well (might still be referenced). */
3261	PGMPhysInvalidatePageMapTLB(pVM);
3262	}
3263	}
3264	else
3265	{
3266	AssertRC(rc);
3267	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3268	MMR3HeapFree(pChunk);
3269	#else
3270	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
3271	#endif
3272	pChunk = NULL;
3273	}
3274
3275	*ppChunk = pChunk;
3276	return rc;
3277	}
3278
3279
3280	/**
3281	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3282	*
3283	* @returns see pgmR3PhysChunkMap.
3284	* @param pVM The VM handle.
3285	* @param idChunk The chunk to map.
3286	*/
3287	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3288	{
3289	PPGMCHUNKR3MAP pChunk;
3290	int rc;
3291
3292	pgmLock(pVM);
3293	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3294	pgmUnlock(pVM);
3295	return rc;
3296	}
3297
3298
3299	/**
3300	* Invalidates the TLB for the ring-3 mapping cache.
3301	*
3302	* @param pVM The VM handle.
3303	*/
3304	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3305	{
3306	pgmLock(pVM);
3307	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3308	{
3309	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3310	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3311	}
3312	/* The page map TLB references chunks, so invalidate that one too. */
3313	PGMPhysInvalidatePageMapTLB(pVM);
3314	pgmUnlock(pVM);
3315	}
3316
3317
3318	/**
3319	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_PAGE to allocate a large (2MB) page
3320	* for use with a nested paging PDE.
3321	*
3322	* @returns The following VBox status codes.
3323	* @retval VINF_SUCCESS on success.
3324	* @retval VINF_EM_NO_MEMORY if we're out of memory.
3325	*
3326	* @param pVM The VM handle.
3327	* @param GCPhys GC physical start address of the 2 MB range
3328	*/
3329	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
3330	{
3331	pgmLock(pVM);
3332
3333	STAM_PROFILE_START(&pVM->pgm.s.StatAllocLargePage, a);
3334	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
3335	STAM_PROFILE_STOP(&pVM->pgm.s.StatAllocLargePage, a);
3336	if (RT_SUCCESS(rc))
3337	{
3338	Assert(pVM->pgm.s.cLargeHandyPages == 1);
3339
3340	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
3341	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
3342
3343	void *pv;
3344
3345	/* Map the large page into our address space.
3346	*
3347	* Note: assuming that within the 2 MB range:
3348	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
3349	* - user space mapping is continuous as well
3350	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
3351	*/
3352	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
3353	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", idPage, HCPhys, rc));
3354
3355	if (RT_SUCCESS(rc))
3356	{
3357	/*
3358	* Clear the pages.
3359	*/
3360	STAM_PROFILE_START(&pVM->pgm.s.StatClearLargePage, b);
3361	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
3362	{
3363	ASMMemZeroPage(pv);
3364
3365	PPGMPAGE pPage;
3366	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
3367	AssertRC(rc);
3368
3369	Assert(PGM_PAGE_IS_ZERO(pPage));
3370	STAM_COUNTER_INC(&pVM->pgm.s.StatRZPageReplaceZero);
3371	pVM->pgm.s.cZeroPages--;
3372
3373	/*
3374	* Do the PGMPAGE modifications.
3375	*/
3376	pVM->pgm.s.cPrivatePages++;
3377	PGM_PAGE_SET_HCPHYS(pPage, HCPhys);
3378	PGM_PAGE_SET_PAGEID(pPage, idPage);
3379	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
3380	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_PDE);
3381
3382	/* Somewhat dirty assumption that page ids are increasing. */
3383	idPage++;
3384
3385	HCPhys += PAGE_SIZE;
3386	GCPhys += PAGE_SIZE;
3387
3388	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
3389
3390	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
3391	}
3392	STAM_PROFILE_STOP(&pVM->pgm.s.StatClearLargePage, b);
3393
3394	/* Flush all TLBs. */
3395	PGM_INVL_ALL_VCPU_TLBS(pVM);
3396	PGMPhysInvalidatePageMapTLB(pVM);
3397	}
3398	pVM->pgm.s.cLargeHandyPages = 0;
3399	}
3400
3401	pgmUnlock(pVM);
3402	return rc;
3403	}
3404
3405
3406	/**
3407	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3408	*
3409	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3410	* signal and clear the out of memory condition. When contracted, this API is
3411	* used to try clear the condition when the user wants to resume.
3412	*
3413	* @returns The following VBox status codes.
3414	* @retval VINF_SUCCESS on success. FFs cleared.
3415	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3416	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3417	*
3418	* @param pVM The VM handle.
3419	*
3420	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3421	* in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3422	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3423	* handler.
3424	*/
3425	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3426	{
3427	pgmLock(pVM);
3428
3429	/*
3430	* Allocate more pages, noting down the index of the first new page.
3431	*/
3432	uint32_t iClear = pVM->pgm.s.cHandyPages;
3433	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3434	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3435	int rcAlloc = VINF_SUCCESS;
3436	int rcSeed = VINF_SUCCESS;
3437	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3438	while (rc == VERR_GMM_SEED_ME)
3439	{
3440	void *pvChunk;
3441	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3442	if (RT_SUCCESS(rc))
3443	{
3444	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3445	if (RT_FAILURE(rc))
3446	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3447	}
3448	if (RT_SUCCESS(rc))
3449	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3450	}
3451
3452	if (RT_SUCCESS(rc))
3453	{
3454	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3455	Assert(pVM->pgm.s.cHandyPages > 0);
3456	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3457	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3458
3459	/*
3460	* Clear the pages.
3461	*/
3462	while (iClear < pVM->pgm.s.cHandyPages)
3463	{
3464	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3465	void *pv;
3466	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3467	AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3468	ASMMemZeroPage(pv);
3469	iClear++;
3470	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3471	}
3472	}
3473	else
3474	{
3475	/*
3476	* We should never get here unless there is a genuine shortage of
3477	* memory (or some internal error). Flag the error so the VM can be
3478	* suspended ASAP and the user informed. If we're totally out of
3479	* handy pages we will return failure.
3480	*/
3481	/* Report the failure. */
3482	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3483	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3484	rc, rcAlloc, rcSeed,
3485	pVM->pgm.s.cHandyPages,
3486	pVM->pgm.s.cAllPages,
3487	pVM->pgm.s.cPrivatePages,
3488	pVM->pgm.s.cSharedPages,
3489	pVM->pgm.s.cZeroPages));
3490	if ( rc != VERR_NO_MEMORY
3491	&& rc != VERR_LOCK_FAILED)
3492	{
3493	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3494	{
3495	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3496	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3497	pVM->pgm.s.aHandyPages[i].idSharedPage));
3498	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3499	if (idPage != NIL_GMM_PAGEID)
3500	{
3501	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3502	pRam;
3503	pRam = pRam->pNextR3)
3504	{
3505	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3506	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3507	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3508	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3509	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3510	}
3511	}
3512	}
3513	}
3514
3515	/* Set the FFs and adjust rc. */
3516	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3517	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3518	if ( rc == VERR_NO_MEMORY
3519	\|\| rc == VERR_LOCK_FAILED)
3520	rc = VINF_EM_NO_MEMORY;
3521	}
3522
3523	pgmUnlock(pVM);
3524	return rc;
3525	}
3526
3527
3528	/**
3529	* Frees the specified RAM page and replaces it with the ZERO page.
3530	*
3531	* This is used by ballooning, remapping MMIO2 and RAM reset.
3532	*
3533	* @param pVM Pointer to the shared VM structure.
3534	* @param pReq Pointer to the request.
3535	* @param pPage Pointer to the page structure.
3536	* @param GCPhys The guest physical address of the page, if applicable.
3537	*
3538	* @remarks The caller must own the PGM lock.
3539	*/
3540	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3541	{
3542	/*
3543	* Assert sanity.
3544	*/
3545	Assert(PGMIsLockOwner(pVM));
3546	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3547	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3548	{
3549	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3550	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3551	}
3552
3553	if ( PGM_PAGE_IS_ZERO(pPage)
3554	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3555	return VINF_SUCCESS;
3556
3557	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3558	Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3559	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3560	\|\| idPage > GMM_PAGEID_LAST
3561	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3562	{
3563	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3564	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3565	}
3566
3567	/* update page count stats. */
3568	if (PGM_PAGE_IS_SHARED(pPage))
3569	pVM->pgm.s.cSharedPages--;
3570	else
3571	pVM->pgm.s.cPrivatePages--;
3572	pVM->pgm.s.cZeroPages++;
3573
3574	/* Deal with write monitored pages. */
3575	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
3576	{
3577	PGM_PAGE_SET_WRITTEN_TO(pPage);
3578	pVM->pgm.s.cWrittenToPages++;
3579	}
3580
3581	/*
3582	* pPage = ZERO page.
3583	*/
3584	PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3585	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3586	PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3587	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
3588
3589	/* Flush physical page map TLB entry. */
3590	PGMPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
3591
3592	/*
3593	* Make sure it's not in the handy page array.
3594	*/
3595	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3596	{
3597	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3598	{
3599	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3600	break;
3601	}
3602	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3603	{
3604	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3605	break;
3606	}
3607	}
3608
3609	/*
3610	* Push it onto the page array.
3611	*/
3612	uint32_t iPage = *pcPendingPages;
3613	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3614	*pcPendingPages += 1;
3615
3616	pReq->aPages[iPage].idPage = idPage;
3617
3618	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3619	return VINF_SUCCESS;
3620
3621	/*
3622	* Flush the pages.
3623	*/
3624	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3625	if (RT_SUCCESS(rc))
3626	{
3627	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3628	*pcPendingPages = 0;
3629	}
3630	return rc;
3631	}
3632
3633
3634	/**
3635	* Converts a GC physical address to a HC ring-3 pointer, with some
3636	* additional checks.
3637	*
3638	* @returns VBox status code.
3639	* @retval VINF_SUCCESS on success.
3640	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3641	* access handler of some kind.
3642	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3643	* accesses or is odd in any way.
3644	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3645	*
3646	* @param pVM The VM handle.
3647	* @param GCPhys The GC physical address to convert.
3648	* @param fWritable Whether write access is required.
3649	* @param ppv Where to store the pointer corresponding to GCPhys on
3650	* success.
3651	*/
3652	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3653	{
3654	pgmLock(pVM);
3655
3656	PPGMRAMRANGE pRam;
3657	PPGMPAGE pPage;
3658	int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3659	if (RT_SUCCESS(rc))
3660	{
3661	if (PGM_PAGE_IS_BALLOONED(pPage))
3662	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3663	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3664	rc = VINF_SUCCESS;
3665	else
3666	{
3667	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3668	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3669	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3670	{
3671	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3672	* in -norawr0 mode. */
3673	if (fWritable)
3674	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3675	}
3676	else
3677	{
3678	/* Temporarily disabled physical handler(s), since the recompiler
3679	doesn't get notified when it's reset we'll have to pretend it's
3680	operating normally. */
3681	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3682	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3683	else
3684	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3685	}
3686	}
3687	if (RT_SUCCESS(rc))
3688	{
3689	int rc2;
3690
3691	/* Make sure what we return is writable. */
3692	if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3693	switch (PGM_PAGE_GET_STATE(pPage))
3694	{
3695	case PGM_PAGE_STATE_ALLOCATED:
3696	break;
3697	case PGM_PAGE_STATE_BALLOONED:
3698	AssertFailed();
3699	break;
3700	case PGM_PAGE_STATE_ZERO:
3701	case PGM_PAGE_STATE_SHARED:
3702	case PGM_PAGE_STATE_WRITE_MONITORED:
3703	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3704	AssertLogRelRCReturn(rc2, rc2);
3705	break;
3706	}
3707
3708	/* Get a ring-3 mapping of the address. */
3709	PPGMPAGER3MAPTLBE pTlbe;
3710	rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3711	AssertLogRelRCReturn(rc2, rc2);
3712	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
3713	/** @todo mapping/locking hell; this isn't horribly efficient since
3714	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
3715
3716	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
3717	}
3718	else
3719	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3720
3721	/* else: handler catching all access, no pointer returned. */
3722	}
3723	else
3724	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3725
3726	pgmUnlock(pVM);
3727	return rc;
3728	}
3729

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source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 28003

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