PGMPhys.cpp@ 31938

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1	/* $Id: PGMPhys.cpp 31938 2010-08-24 17:17:48Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_PHYS
23	#include <VBox/pgm.h>
24	#include <VBox/iom.h>
25	#include <VBox/mm.h>
26	#include <VBox/stam.h>
27	#include <VBox/rem.h>
28	#include <VBox/pdmdev.h>
29	#include "PGMInternal.h"
30	#include <VBox/vm.h>
31	#include "PGMInline.h"
32	#include <VBox/sup.h>
33	#include <VBox/param.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <iprt/assert.h>
37	#include <iprt/alloc.h>
38	#include <iprt/asm.h>
39	#include <iprt/thread.h>
40	#include <iprt/string.h>
41
42
43	/*******************************************************************************
44	* Defined Constants And Macros *
45	*******************************************************************************/
46	/** The number of pages to free in one batch. */
47	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
48
49
50	/*******************************************************************************
51	* Internal Functions *
52	*******************************************************************************/
53	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
54
55
56	/*
57	* PGMR3PhysReadU8-64
58	* PGMR3PhysWriteU8-64
59	*/
60	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
61	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
62	#define PGMPHYS_DATASIZE 1
63	#define PGMPHYS_DATATYPE uint8_t
64	#include "PGMPhysRWTmpl.h"
65
66	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
67	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
68	#define PGMPHYS_DATASIZE 2
69	#define PGMPHYS_DATATYPE uint16_t
70	#include "PGMPhysRWTmpl.h"
71
72	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
73	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
74	#define PGMPHYS_DATASIZE 4
75	#define PGMPHYS_DATATYPE uint32_t
76	#include "PGMPhysRWTmpl.h"
77
78	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
79	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
80	#define PGMPHYS_DATASIZE 8
81	#define PGMPHYS_DATATYPE uint64_t
82	#include "PGMPhysRWTmpl.h"
83
84
85	/**
86	* EMT worker for PGMR3PhysReadExternal.
87	*/
88	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
89	{
90	PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
91	return VINF_SUCCESS;
92	}
93
94
95	/**
96	* Write to physical memory, external users.
97	*
98	* @returns VBox status code.
99	* @retval VINF_SUCCESS.
100	*
101	* @param pVM VM Handle.
102	* @param GCPhys Physical address to write to.
103	* @param pvBuf What to write.
104	* @param cbWrite How many bytes to write.
105	*
106	* @thread Any but EMTs.
107	*/
108	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
109	{
110	VM_ASSERT_OTHER_THREAD(pVM);
111
112	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
113	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
114
115	pgmLock(pVM);
116
117	/*
118	* Copy loop on ram ranges.
119	*/
120	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
121	for (;;)
122	{
123	/* Find range. */
124	while (pRam && GCPhys > pRam->GCPhysLast)
125	pRam = pRam->CTX_SUFF(pNext);
126	/* Inside range or not? */
127	if (pRam && GCPhys >= pRam->GCPhys)
128	{
129	/*
130	* Must work our way thru this page by page.
131	*/
132	RTGCPHYS off = GCPhys - pRam->GCPhys;
133	while (off < pRam->cb)
134	{
135	unsigned iPage = off >> PAGE_SHIFT;
136	PPGMPAGE pPage = &pRam->aPages[iPage];
137
138	/*
139	* If the page has an ALL access handler, we'll have to
140	* delegate the job to EMT.
141	*/
142	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
143	{
144	pgmUnlock(pVM);
145
146	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 4,
147	pVM, &GCPhys, pvBuf, cbRead);
148	}
149	Assert(!PGM_PAGE_IS_MMIO(pPage));
150
151	/*
152	* Simple stuff, go ahead.
153	*/
154	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
155	if (cb > cbRead)
156	cb = cbRead;
157	const void *pvSrc;
158	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
159	if (RT_SUCCESS(rc))
160	memcpy(pvBuf, pvSrc, cb);
161	else
162	{
163	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
164	pRam->GCPhys + off, pPage, rc));
165	memset(pvBuf, 0xff, cb);
166	}
167
168	/* next page */
169	if (cb >= cbRead)
170	{
171	pgmUnlock(pVM);
172	return VINF_SUCCESS;
173	}
174	cbRead -= cb;
175	off += cb;
176	GCPhys += cb;
177	pvBuf = (char *)pvBuf + cb;
178	} /* walk pages in ram range. */
179	}
180	else
181	{
182	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
183
184	/*
185	* Unassigned address space.
186	*/
187	if (!pRam)
188	break;
189	size_t cb = pRam->GCPhys - GCPhys;
190	if (cb >= cbRead)
191	{
192	memset(pvBuf, 0xff, cbRead);
193	break;
194	}
195	memset(pvBuf, 0xff, cb);
196
197	cbRead -= cb;
198	pvBuf = (char *)pvBuf + cb;
199	GCPhys += cb;
200	}
201	} /* Ram range walk */
202
203	pgmUnlock(pVM);
204
205	return VINF_SUCCESS;
206	}
207
208
209	/**
210	* EMT worker for PGMR3PhysWriteExternal.
211	*/
212	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
213	{
214	/** @todo VERR_EM_NO_MEMORY */
215	PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
216	return VINF_SUCCESS;
217	}
218
219
220	/**
221	* Write to physical memory, external users.
222	*
223	* @returns VBox status code.
224	* @retval VINF_SUCCESS.
225	* @retval VERR_EM_NO_MEMORY.
226	*
227	* @param pVM VM Handle.
228	* @param GCPhys Physical address to write to.
229	* @param pvBuf What to write.
230	* @param cbWrite How many bytes to write.
231	* @param pszWho Who is writing. For tracking down who is writing
232	* after we've saved the state.
233	*
234	* @thread Any but EMTs.
235	*/
236	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void pvBuf, size_t cbWrite, const char pszWho)
237	{
238	VM_ASSERT_OTHER_THREAD(pVM);
239
240	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
241	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x pszWho=%s\n",
242	GCPhys, cbWrite, pszWho));
243	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
244	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
245
246	pgmLock(pVM);
247
248	/*
249	* Copy loop on ram ranges, stop when we hit something difficult.
250	*/
251	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
252	for (;;)
253	{
254	/* Find range. */
255	while (pRam && GCPhys > pRam->GCPhysLast)
256	pRam = pRam->CTX_SUFF(pNext);
257	/* Inside range or not? */
258	if (pRam && GCPhys >= pRam->GCPhys)
259	{
260	/*
261	* Must work our way thru this page by page.
262	*/
263	RTGCPTR off = GCPhys - pRam->GCPhys;
264	while (off < pRam->cb)
265	{
266	RTGCPTR iPage = off >> PAGE_SHIFT;
267	PPGMPAGE pPage = &pRam->aPages[iPage];
268
269	/*
270	* Is the page problematic, we have to do the work on the EMT.
271	*
272	* Allocating writable pages and access handlers are
273	* problematic, write monitored pages are simple and can be
274	* dealth with here.
275	*/
276	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
277	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
278	{
279	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
280	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
281	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
282	else
283	{
284	pgmUnlock(pVM);
285
286	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 4,
287	pVM, &GCPhys, pvBuf, cbWrite);
288	}
289	}
290	Assert(!PGM_PAGE_IS_MMIO(pPage));
291
292	/*
293	* Simple stuff, go ahead.
294	*/
295	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
296	if (cb > cbWrite)
297	cb = cbWrite;
298	void *pvDst;
299	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
300	if (RT_SUCCESS(rc))
301	memcpy(pvDst, pvBuf, cb);
302	else
303	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
304	pRam->GCPhys + off, pPage, rc));
305
306	/* next page */
307	if (cb >= cbWrite)
308	{
309	pgmUnlock(pVM);
310	return VINF_SUCCESS;
311	}
312
313	cbWrite -= cb;
314	off += cb;
315	GCPhys += cb;
316	pvBuf = (const char *)pvBuf + cb;
317	} /* walk pages in ram range */
318	}
319	else
320	{
321	/*
322	* Unassigned address space, skip it.
323	*/
324	if (!pRam)
325	break;
326	size_t cb = pRam->GCPhys - GCPhys;
327	if (cb >= cbWrite)
328	break;
329	cbWrite -= cb;
330	pvBuf = (const char *)pvBuf + cb;
331	GCPhys += cb;
332	}
333	} /* Ram range walk */
334
335	pgmUnlock(pVM);
336	return VINF_SUCCESS;
337	}
338
339
340	/**
341	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
342	*
343	* @returns see PGMR3PhysGCPhys2CCPtrExternal
344	* @param pVM The VM handle.
345	* @param pGCPhys Pointer to the guest physical address.
346	* @param ppv Where to store the mapping address.
347	* @param pLock Where to store the lock.
348	*/
349	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
350	{
351	/*
352	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
353	* an access handler after it succeeds.
354	*/
355	int rc = pgmLock(pVM);
356	AssertRCReturn(rc, rc);
357
358	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
359	if (RT_SUCCESS(rc))
360	{
361	PPGMPAGEMAPTLBE pTlbe;
362	int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
363	AssertFatalRC(rc2);
364	PPGMPAGE pPage = pTlbe->pPage;
365	if (PGM_PAGE_IS_MMIO(pPage))
366	{
367	PGMPhysReleasePageMappingLock(pVM, pLock);
368	rc = VERR_PGM_PHYS_PAGE_RESERVED;
369	}
370	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
371	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
372	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
373	#endif
374	)
375	{
376	/* We must flush any corresponding pgm pool page here, otherwise we'll
377	* not be informed about writes and keep bogus gst->shw mappings around.
378	*/
379	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
380	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
381	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
382	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
383	}
384	}
385
386	pgmUnlock(pVM);
387	return rc;
388	}
389
390
391	/**
392	* Requests the mapping of a guest page into ring-3, external threads.
393	*
394	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
395	* release it.
396	*
397	* This API will assume your intention is to write to the page, and will
398	* therefore replace shared and zero pages. If you do not intend to modify the
399	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
400	*
401	* @returns VBox status code.
402	* @retval VINF_SUCCESS on success.
403	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
404	* backing or if the page has any active access handlers. The caller
405	* must fall back on using PGMR3PhysWriteExternal.
406	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
407	*
408	* @param pVM The VM handle.
409	* @param GCPhys The guest physical address of the page that should be mapped.
410	* @param ppv Where to store the address corresponding to GCPhys.
411	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
412	*
413	* @remark Avoid calling this API from within critical sections (other than the
414	* PGM one) because of the deadlock risk when we have to delegating the
415	* task to an EMT.
416	* @thread Any.
417	*/
418	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
419	{
420	AssertPtr(ppv);
421	AssertPtr(pLock);
422
423	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
424
425	int rc = pgmLock(pVM);
426	AssertRCReturn(rc, rc);
427
428	/*
429	* Query the Physical TLB entry for the page (may fail).
430	*/
431	PPGMPAGEMAPTLBE pTlbe;
432	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
433	if (RT_SUCCESS(rc))
434	{
435	PPGMPAGE pPage = pTlbe->pPage;
436	if (PGM_PAGE_IS_MMIO(pPage))
437	rc = VERR_PGM_PHYS_PAGE_RESERVED;
438	else
439	{
440	/*
441	* If the page is shared, the zero page, or being write monitored
442	* it must be converted to an page that's writable if possible.
443	* We can only deal with write monitored pages here, the rest have
444	* to be on an EMT.
445	*/
446	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
447	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
448	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
449	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
450	#endif
451	)
452	{
453	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
454	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
455	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
456	&& !pgmPoolIsDirtyPage(pVM, GCPhys)
457	#endif
458	)
459	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
460	else
461	{
462	pgmUnlock(pVM);
463
464	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
465	pVM, &GCPhys, ppv, pLock);
466	}
467	}
468
469	/*
470	* Now, just perform the locking and calculate the return address.
471	*/
472	PPGMPAGEMAP pMap = pTlbe->pMap;
473	if (pMap)
474	pMap->cRefs++;
475
476	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
477	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
478	{
479	if (cLocks == 0)
480	pVM->pgm.s.cWriteLockedPages++;
481	PGM_PAGE_INC_WRITE_LOCKS(pPage);
482	}
483	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
484	{
485	PGM_PAGE_INC_WRITE_LOCKS(pPage);
486	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
487	if (pMap)
488	pMap->cRefs++; /* Extra ref to prevent it from going away. */
489	}
490
491	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
492	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
493	pLock->pvMap = pMap;
494	}
495	}
496
497	pgmUnlock(pVM);
498	return rc;
499	}
500
501
502	/**
503	* Requests the mapping of a guest page into ring-3, external threads.
504	*
505	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
506	* release it.
507	*
508	* @returns VBox status code.
509	* @retval VINF_SUCCESS on success.
510	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
511	* backing or if the page as an active ALL access handler. The caller
512	* must fall back on using PGMPhysRead.
513	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
514	*
515	* @param pVM The VM handle.
516	* @param GCPhys The guest physical address of the page that should be mapped.
517	* @param ppv Where to store the address corresponding to GCPhys.
518	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
519	*
520	* @remark Avoid calling this API from within critical sections (other than
521	* the PGM one) because of the deadlock risk.
522	* @thread Any.
523	*/
524	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
525	{
526	int rc = pgmLock(pVM);
527	AssertRCReturn(rc, rc);
528
529	/*
530	* Query the Physical TLB entry for the page (may fail).
531	*/
532	PPGMPAGEMAPTLBE pTlbe;
533	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
534	if (RT_SUCCESS(rc))
535	{
536	PPGMPAGE pPage = pTlbe->pPage;
537	#if 1
538	/* MMIO pages doesn't have any readable backing. */
539	if (PGM_PAGE_IS_MMIO(pPage))
540	rc = VERR_PGM_PHYS_PAGE_RESERVED;
541	#else
542	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
543	rc = VERR_PGM_PHYS_PAGE_RESERVED;
544	#endif
545	else
546	{
547	/*
548	* Now, just perform the locking and calculate the return address.
549	*/
550	PPGMPAGEMAP pMap = pTlbe->pMap;
551	if (pMap)
552	pMap->cRefs++;
553
554	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
555	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
556	{
557	if (cLocks == 0)
558	pVM->pgm.s.cReadLockedPages++;
559	PGM_PAGE_INC_READ_LOCKS(pPage);
560	}
561	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
562	{
563	PGM_PAGE_INC_READ_LOCKS(pPage);
564	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
565	if (pMap)
566	pMap->cRefs++; /* Extra ref to prevent it from going away. */
567	}
568
569	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
570	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
571	pLock->pvMap = pMap;
572	}
573	}
574
575	pgmUnlock(pVM);
576	return rc;
577	}
578
579
580	/**
581	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
582	*
583	* Called when anything was relocated.
584	*
585	* @param pVM Pointer to the shared VM structure.
586	*/
587	void pgmR3PhysRelinkRamRanges(PVM pVM)
588	{
589	PPGMRAMRANGE pCur;
590
591	#ifdef VBOX_STRICT
592	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
593	{
594	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
595	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
596	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
597	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
598	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
599	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
600	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
601	Assert( pCur2 == pCur
602	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
603	}
604	#endif
605
606	pCur = pVM->pgm.s.pRamRangesR3;
607	if (pCur)
608	{
609	pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
610	pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
611
612	for (; pCur->pNextR3; pCur = pCur->pNextR3)
613	{
614	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
615	pCur->pNextRC = pCur->pNextR3->pSelfRC;
616	}
617
618	Assert(pCur->pNextR0 == NIL_RTR0PTR);
619	Assert(pCur->pNextRC == NIL_RTRCPTR);
620	}
621	else
622	{
623	Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
624	Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
625	}
626	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
627	}
628
629
630	/**
631	* Links a new RAM range into the list.
632	*
633	* @param pVM Pointer to the shared VM structure.
634	* @param pNew Pointer to the new list entry.
635	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
636	*/
637	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
638	{
639	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
640	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
641	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
642
643	pgmLock(pVM);
644
645	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
646	pNew->pNextR3 = pRam;
647	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
648	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
649
650	if (pPrev)
651	{
652	pPrev->pNextR3 = pNew;
653	pPrev->pNextR0 = pNew->pSelfR0;
654	pPrev->pNextRC = pNew->pSelfRC;
655	}
656	else
657	{
658	pVM->pgm.s.pRamRangesR3 = pNew;
659	pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
660	pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
661	}
662	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
663	pgmUnlock(pVM);
664	}
665
666
667	/**
668	* Unlink an existing RAM range from the list.
669	*
670	* @param pVM Pointer to the shared VM structure.
671	* @param pRam Pointer to the new list entry.
672	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
673	*/
674	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
675	{
676	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
677	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
678	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
679
680	pgmLock(pVM);
681
682	PPGMRAMRANGE pNext = pRam->pNextR3;
683	if (pPrev)
684	{
685	pPrev->pNextR3 = pNext;
686	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
687	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
688	}
689	else
690	{
691	Assert(pVM->pgm.s.pRamRangesR3 == pRam);
692	pVM->pgm.s.pRamRangesR3 = pNext;
693	pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
694	pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
695	}
696	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
697	pgmUnlock(pVM);
698	}
699
700
701	/**
702	* Unlink an existing RAM range from the list.
703	*
704	* @param pVM Pointer to the shared VM structure.
705	* @param pRam Pointer to the new list entry.
706	*/
707	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
708	{
709	pgmLock(pVM);
710
711	/* find prev. */
712	PPGMRAMRANGE pPrev = NULL;
713	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
714	while (pCur != pRam)
715	{
716	pPrev = pCur;
717	pCur = pCur->pNextR3;
718	}
719	AssertFatal(pCur);
720
721	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
722	pgmUnlock(pVM);
723	}
724
725
726	/**
727	* Frees a range of pages, replacing them with ZERO pages of the specified type.
728	*
729	* @returns VBox status code.
730	* @param pVM The VM handle.
731	* @param pRam The RAM range in which the pages resides.
732	* @param GCPhys The address of the first page.
733	* @param GCPhysLast The address of the last page.
734	* @param uType The page type to replace then with.
735	*/
736	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
737	{
738	Assert(PGMIsLockOwner(pVM));
739	uint32_t cPendingPages = 0;
740	PGMMFREEPAGESREQ pReq;
741	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
742	AssertLogRelRCReturn(rc, rc);
743
744	/* Iterate the pages. */
745	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
746	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
747	while (cPagesLeft-- > 0)
748	{
749	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
750	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
751
752	PGM_PAGE_SET_TYPE(pPageDst, uType);
753
754	GCPhys += PAGE_SIZE;
755	pPageDst++;
756	}
757
758	if (cPendingPages)
759	{
760	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
761	AssertLogRelRCReturn(rc, rc);
762	}
763	GMMR3FreePagesCleanup(pReq);
764
765	return rc;
766	}
767
768	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
769	/**
770	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
771	*
772	* This is only called on one of the EMTs while the other ones are waiting for
773	* it to complete this function.
774	*
775	* @returns VINF_SUCCESS (VBox strict status code).
776	* @param pVM The VM handle.
777	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
778	* @param pvUser User parameter
779	*/
780	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
781	{
782	uintptr_t paUser = (uintptr_t )pvUser;
783	bool fInflate = !!paUser[0];
784	unsigned cPages = paUser[1];
785	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
786	uint32_t cPendingPages = 0;
787	PGMMFREEPAGESREQ pReq;
788	int rc;
789
790	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
791	pgmLock(pVM);
792
793	if (fInflate)
794	{
795	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
796	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
797
798	/* Replace pages with ZERO pages. */
799	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
800	if (RT_FAILURE(rc))
801	{
802	pgmUnlock(pVM);
803	AssertLogRelRC(rc);
804	return rc;
805	}
806
807	/* Iterate the pages. */
808	for (unsigned i = 0; i < cPages; i++)
809	{
810	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
811	if ( pPage == NULL
812	\|\| pPage->uTypeY != PGMPAGETYPE_RAM)
813	{
814	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], (pPage) ? pPage->uTypeY : 0));
815	break;
816	}
817
818	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
819
820	/* Flush the shadow PT if this page was previously used as a guest page table. */
821	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
822
823	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i]);
824	if (RT_FAILURE(rc))
825	{
826	pgmUnlock(pVM);
827	AssertLogRelRC(rc);
828	return rc;
829	}
830	Assert(PGM_PAGE_IS_ZERO(pPage));
831	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_BALLOONED);
832	}
833
834	if (cPendingPages)
835	{
836	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
837	if (RT_FAILURE(rc))
838	{
839	pgmUnlock(pVM);
840	AssertLogRelRC(rc);
841	return rc;
842	}
843	}
844	GMMR3FreePagesCleanup(pReq);
845	}
846	else
847	{
848	/* Iterate the pages. */
849	for (unsigned i = 0; i < cPages; i++)
850	{
851	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
852	AssertBreak(pPage && pPage->uTypeY == PGMPAGETYPE_RAM);
853
854	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
855
856	Assert(PGM_PAGE_IS_BALLOONED(pPage));
857
858	/* Change back to zero page. */
859	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
860	}
861
862	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
863	}
864
865	/* Notify GMM about the balloon change. */
866	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
867	if (RT_SUCCESS(rc))
868	{
869	if (!fInflate)
870	{
871	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
872	pVM->pgm.s.cBalloonedPages -= cPages;
873	}
874	else
875	pVM->pgm.s.cBalloonedPages += cPages;
876	}
877
878	pgmUnlock(pVM);
879
880	/* Flush the recompiler's TLB as well. */
881	for (VMCPUID i = 0; i < pVM->cCpus; i++)
882	CPUMSetChangedFlags(&pVM->aCpus[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
883
884	AssertLogRelRC(rc);
885	return rc;
886	}
887
888	/**
889	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
890	*
891	* @returns VBox status code.
892	* @param pVM The VM handle.
893	* @param fInflate Inflate or deflate memory balloon
894	* @param cPages Number of pages to free
895	* @param paPhysPage Array of guest physical addresses
896	*/
897	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
898	{
899	uintptr_t paUser[3];
900
901	paUser[0] = fInflate;
902	paUser[1] = cPages;
903	paUser[2] = (uintptr_t)paPhysPage;
904	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
905	AssertRC(rc);
906
907	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
908	RTMemFree(paPhysPage);
909	}
910	#endif
911
912	/**
913	* Inflate or deflate a memory balloon
914	*
915	* @returns VBox status code.
916	* @param pVM The VM handle.
917	* @param fInflate Inflate or deflate memory balloon
918	* @param cPages Number of pages to free
919	* @param paPhysPage Array of guest physical addresses
920	*/
921	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
922	{
923	/* This must match GMMR0Init; currently we only support memory ballooning on all 64-bit hosts except Mac OS X */
924	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
925	int rc;
926
927	/* Older additions (ancient non-functioning balloon code) pass wrong physical addresses. */
928	AssertReturn(!(paPhysPage[0] & 0xfff), VERR_INVALID_PARAMETER);
929
930	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
931	* In the SMP case we post a request packet to postpone the job.
932	*/
933	if (pVM->cCpus > 1)
934	{
935	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
936	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
937	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
938
939	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
940
941	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
942	AssertRC(rc);
943	}
944	else
945	{
946	uintptr_t paUser[3];
947
948	paUser[0] = fInflate;
949	paUser[1] = cPages;
950	paUser[2] = (uintptr_t)paPhysPage;
951	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
952	AssertRC(rc);
953	}
954	return rc;
955	#else
956	return VERR_NOT_IMPLEMENTED;
957	#endif
958	}
959
960	/**
961	* Rendezvous callback used by PGMR3WriteProtectRAM that write protects all physical RAM
962	*
963	* This is only called on one of the EMTs while the other ones are waiting for
964	* it to complete this function.
965	*
966	* @returns VINF_SUCCESS (VBox strict status code).
967	* @param pVM The VM handle.
968	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
969	* @param pvUser User parameter
970	*/
971	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
972	{
973	int rc = VINF_SUCCESS;
974
975	pgmLock(pVM);
976	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
977	pgmPoolResetDirtyPages(pVM);
978	#endif
979
980	/** @todo pointless to write protect the physical page pointed to by RSP. */
981
982	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
983	pRam;
984	pRam = pRam->CTX_SUFF(pNext))
985	{
986	if (!PGM_RAM_RANGE_IS_AD_HOC(pRam))
987	{
988	unsigned iPage = pRam->cb >> PAGE_SHIFT;
989	while (iPage-- > 0)
990	{
991	PPGMPAGE pPage = &pRam->aPages[iPage];
992	if (RT_LIKELY(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM))
993	{
994	/*
995	* A RAM page.
996	*/
997	switch (PGM_PAGE_GET_STATE(pPage))
998	{
999	case PGM_PAGE_STATE_ALLOCATED:
1000	/** @todo Optimize this: Don't always re-enable write
1001	* monitoring if the page is known to be very busy. */
1002	if (PGM_PAGE_IS_WRITTEN_TO(pPage))
1003	{
1004	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1005	/* Remember this dirty page for the next (memory) sync. */
1006	PGM_PAGE_SET_FT_DIRTY(pPage);
1007	}
1008
1009	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_WRITE_MONITORED);
1010	break;
1011
1012	case PGM_PAGE_STATE_SHARED:
1013	AssertFailed();
1014	break;
1015
1016	case PGM_PAGE_STATE_WRITE_MONITORED: /* nothing to change. */
1017	default:
1018	break;
1019	}
1020	}
1021	}
1022	}
1023	}
1024	pgmR3PoolWriteProtectPages(pVM);
1025	PGM_INVL_ALL_VCPU_TLBS(pVM);
1026	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1027	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1028
1029	pgmUnlock(pVM);
1030	return rc;
1031	}
1032
1033	/**
1034	* Protect all physical RAM to monitor writes
1035	*
1036	* @returns VBox status code.
1037	* @param pVM The VM handle.
1038	*/
1039	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM)
1040	{
1041	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1042
1043	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysWriteProtectRAMRendezvous, NULL);
1044	AssertRC(rc);
1045	return rc;
1046	}
1047
1048	/**
1049	* Enumerate all dirty FT pages
1050	*
1051	* @returns VBox status code.
1052	* @param pVM The VM handle.
1053	* @param pfnEnum Enumerate callback handler
1054	* @param pvUser Enumerate callback handler parameter
1055	*/
1056	VMMR3DECL(int) PGMR3PhysEnumDirtyFTPages(PVM pVM, PFNPGMENUMDIRTYFTPAGES pfnEnum, void *pvUser)
1057	{
1058	int rc = VINF_SUCCESS;
1059
1060	pgmLock(pVM);
1061	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1062	pRam;
1063	pRam = pRam->CTX_SUFF(pNext))
1064	{
1065	if (!PGM_RAM_RANGE_IS_AD_HOC(pRam))
1066	{
1067	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1068	while (iPage-- > 0)
1069	{
1070	PPGMPAGE pPage = &pRam->aPages[iPage];
1071	if (RT_LIKELY(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM))
1072	{
1073	/*
1074	* A RAM page.
1075	*/
1076	switch (PGM_PAGE_GET_STATE(pPage))
1077	{
1078	case PGM_PAGE_STATE_ALLOCATED:
1079	if ( !PGM_PAGE_IS_WRITTEN_TO(pPage)
1080	&& PGM_PAGE_IS_FT_DIRTY(pPage))
1081	{
1082	/** @todo this is risky; the range might be changed, but little choice as the sync costs a lot of time */
1083	pgmUnlock(pVM);
1084	pfnEnum(pVM, pRam->GCPhys + iPage * PAGE_SIZE, 0, 0, pvUser);
1085	pgmLock(pVM);
1086	PGM_PAGE_CLEAR_FT_DIRTY(pPage);
1087	}
1088	break;
1089	}
1090	}
1091	}
1092	}
1093	}
1094	pgmUnlock(pVM);
1095	return rc;
1096	}
1097
1098	/**
1099	* Query the amount of free memory inside VMMR0
1100	*
1101	* @returns VBox status code.
1102	* @param pVM The VM handle.
1103	* @param puTotalAllocSize Pointer to total allocated memory inside VMMR0 (in bytes)
1104	* @param puTotalFreeSize Pointer to total free (allocated but not used yet) memory inside VMMR0 (in bytes)
1105	* @param puTotalBalloonSize Pointer to total ballooned memory inside VMMR0 (in bytes)
1106	* @param puTotalSharedSize Pointer to total shared memory inside VMMR0 (in bytes)
1107	*/
1108	VMMR3DECL(int) PGMR3QueryVMMMemoryStats(PVM pVM, uint64_t puTotalAllocSize, uint64_t puTotalFreeSize, uint64_t puTotalBalloonSize, uint64_t puTotalSharedSize)
1109	{
1110	int rc;
1111
1112	uint64_t cAllocPages = 0, cFreePages = 0, cBalloonPages = 0, cSharedPages = 0;
1113	rc = GMMR3QueryHypervisorMemoryStats(pVM, &cAllocPages, &cFreePages, &cBalloonPages, &cSharedPages);
1114	AssertRCReturn(rc, rc);
1115
1116	if (puTotalAllocSize)
1117	puTotalAllocSize = cAllocPages _4K;
1118
1119	if (puTotalFreeSize)
1120	puTotalFreeSize = cFreePages _4K;
1121
1122	if (puTotalBalloonSize)
1123	puTotalBalloonSize = cBalloonPages _4K;
1124
1125	if (puTotalSharedSize)
1126	puTotalSharedSize = cSharedPages _4K;
1127
1128	Log(("PGMR3QueryVMMMemoryStats: all=%x free=%x ballooned=%x shared=%x\n", cAllocPages, cFreePages, cBalloonPages, cSharedPages));
1129	return VINF_SUCCESS;
1130	}
1131
1132	/**
1133	* Query memory stats for the VM
1134	*
1135	* @returns VBox status code.
1136	* @param pVM The VM handle.
1137	* @param puTotalAllocSize Pointer to total allocated memory inside the VM (in bytes)
1138	* @param puTotalFreeSize Pointer to total free (allocated but not used yet) memory inside the VM (in bytes)
1139	* @param puTotalBalloonSize Pointer to total ballooned memory inside the VM (in bytes)
1140	* @param puTotalSharedSize Pointer to total shared memory inside the VM (in bytes)
1141	*/
1142	VMMR3DECL(int) PGMR3QueryMemoryStats(PVM pVM, uint64_t pulTotalMem, uint64_t pulPrivateMem, uint64_t puTotalSharedMem, uint64_t puTotalZeroMem)
1143	{
1144	if (pulTotalMem)
1145	pulTotalMem = (uint64_t)pVM->pgm.s.cAllPages _4K;
1146
1147	if (pulPrivateMem)
1148	pulPrivateMem = (uint64_t)pVM->pgm.s.cPrivatePages _4K;
1149
1150	if (puTotalSharedMem)
1151	puTotalSharedMem = (uint64_t)pVM->pgm.s.cReusedSharedPages _4K;
1152
1153	if (puTotalZeroMem)
1154	puTotalZeroMem = (uint64_t)pVM->pgm.s.cZeroPages _4K;
1155
1156	Log(("PGMR3QueryMemoryStats: all=%x private=%x reused=%x zero=%x\n", pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cReusedSharedPages, pVM->pgm.s.cZeroPages));
1157	return VINF_SUCCESS;
1158	}
1159
1160	/**
1161	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
1162	*
1163	* @param pVM The VM handle.
1164	* @param pNew The new RAM range.
1165	* @param GCPhys The address of the RAM range.
1166	* @param GCPhysLast The last address of the RAM range.
1167	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
1168	* if in HMA.
1169	* @param R0PtrNew Ditto for R0.
1170	* @param pszDesc The description.
1171	* @param pPrev The previous RAM range (for linking).
1172	*/
1173	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
1174	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
1175	{
1176	/*
1177	* Initialize the range.
1178	*/
1179	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
1180	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
1181	pNew->GCPhys = GCPhys;
1182	pNew->GCPhysLast = GCPhysLast;
1183	pNew->cb = GCPhysLast - GCPhys + 1;
1184	pNew->pszDesc = pszDesc;
1185	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
1186	pNew->pvR3 = NULL;
1187	pNew->paLSPages = NULL;
1188
1189	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1190	RTGCPHYS iPage = cPages;
1191	while (iPage-- > 0)
1192	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1193
1194	/* Update the page count stats. */
1195	pVM->pgm.s.cZeroPages += cPages;
1196	pVM->pgm.s.cAllPages += cPages;
1197
1198	/*
1199	* Link it.
1200	*/
1201	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1202	}
1203
1204
1205	/**
1206	* Relocate a floating RAM range.
1207	*
1208	* @copydoc FNPGMRELOCATE.
1209	*/
1210	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
1211	{
1212	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
1213	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
1214	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
1215
1216	switch (enmMode)
1217	{
1218	case PGMRELOCATECALL_SUGGEST:
1219	return true;
1220	case PGMRELOCATECALL_RELOCATE:
1221	{
1222	/* Update myself and then relink all the ranges. */
1223	pgmLock(pVM);
1224	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
1225	pgmR3PhysRelinkRamRanges(pVM);
1226	pgmUnlock(pVM);
1227	return true;
1228	}
1229
1230	default:
1231	AssertFailedReturn(false);
1232	}
1233	}
1234
1235
1236	/**
1237	* PGMR3PhysRegisterRam worker that registers a high chunk.
1238	*
1239	* @returns VBox status code.
1240	* @param pVM The VM handle.
1241	* @param GCPhys The address of the RAM.
1242	* @param cRamPages The number of RAM pages to register.
1243	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1244	* @param iChunk The chunk number.
1245	* @param pszDesc The RAM range description.
1246	* @param ppPrev Previous RAM range pointer. In/Out.
1247	*/
1248	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1249	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1250	PPGMRAMRANGE *ppPrev)
1251	{
1252	const char *pszDescChunk = iChunk == 0
1253	? pszDesc
1254	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1255	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1256
1257	/*
1258	* Allocate memory for the new chunk.
1259	*/
1260	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1261	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1262	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1263	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1264	void *pvChunk = NULL;
1265	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
1266	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1267	VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
1268	#else
1269	NULL,
1270	#endif
1271	paChunkPages);
1272	if (RT_SUCCESS(rc))
1273	{
1274	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1275	if (!VMMIsHwVirtExtForced(pVM))
1276	R0PtrChunk = NIL_RTR0PTR;
1277	#else
1278	R0PtrChunk = (uintptr_t)pvChunk;
1279	#endif
1280	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1281
1282	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1283
1284	/*
1285	* Create a mapping and map the pages into it.
1286	* We push these in below the HMA.
1287	*/
1288	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1289	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1290	if (RT_SUCCESS(rc))
1291	{
1292	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1293
1294	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1295	RTGCPTR GCPtrPage = GCPtrChunk;
1296	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1297	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1298	if (RT_SUCCESS(rc))
1299	{
1300	/*
1301	* Ok, init and link the range.
1302	*/
1303	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1304	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1305	*ppPrev = pNew;
1306	}
1307	}
1308
1309	if (RT_FAILURE(rc))
1310	SUPR3PageFreeEx(pvChunk, cChunkPages);
1311	}
1312
1313	RTMemTmpFree(paChunkPages);
1314	return rc;
1315	}
1316
1317
1318	/**
1319	* Sets up a range RAM.
1320	*
1321	* This will check for conflicting registrations, make a resource
1322	* reservation for the memory (with GMM), and setup the per-page
1323	* tracking structures (PGMPAGE).
1324	*
1325	* @returns VBox stutus code.
1326	* @param pVM Pointer to the shared VM structure.
1327	* @param GCPhys The physical address of the RAM.
1328	* @param cb The size of the RAM.
1329	* @param pszDesc The description - not copied, so, don't free or change it.
1330	*/
1331	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1332	{
1333	/*
1334	* Validate input.
1335	*/
1336	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1337	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1338	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1339	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1340	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1341	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1342	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1343	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1344
1345	pgmLock(pVM);
1346
1347	/*
1348	* Find range location and check for conflicts.
1349	* (We don't lock here because the locking by EMT is only required on update.)
1350	*/
1351	PPGMRAMRANGE pPrev = NULL;
1352	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1353	while (pRam && GCPhysLast >= pRam->GCPhys)
1354	{
1355	if ( GCPhysLast >= pRam->GCPhys
1356	&& GCPhys <= pRam->GCPhysLast)
1357	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1358	GCPhys, GCPhysLast, pszDesc,
1359	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1360	VERR_PGM_RAM_CONFLICT);
1361
1362	/* next */
1363	pPrev = pRam;
1364	pRam = pRam->pNextR3;
1365	}
1366
1367	/*
1368	* Register it with GMM (the API bitches).
1369	*/
1370	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1371	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1372	if (RT_FAILURE(rc))
1373	{
1374	pgmUnlock(pVM);
1375	return rc;
1376	}
1377
1378	if ( GCPhys >= _4G
1379	&& cPages > 256)
1380	{
1381	/*
1382	* The PGMRAMRANGE structures for the high memory can get very big.
1383	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1384	* allocation size limit there and also to avoid being unable to find
1385	* guest mapping space for them, we split this memory up into 4MB in
1386	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1387	* mode.
1388	*
1389	* The first and last page of each mapping are guard pages and marked
1390	* not-present. So, we've got 4186112 and 16769024 bytes available for
1391	* the PGMRAMRANGE structure.
1392	*
1393	* Note! The sizes used here will influence the saved state.
1394	*/
1395	uint32_t cbChunk;
1396	uint32_t cPagesPerChunk;
1397	if (VMMIsHwVirtExtForced(pVM))
1398	{
1399	cbChunk = 16U*_1M;
1400	cPagesPerChunk = 1048048; /* max ~1048059 */
1401	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1402	}
1403	else
1404	{
1405	cbChunk = 4U*_1M;
1406	cPagesPerChunk = 261616; /* max ~261627 */
1407	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1408	}
1409	AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1410
1411	RTGCPHYS cPagesLeft = cPages;
1412	RTGCPHYS GCPhysChunk = GCPhys;
1413	uint32_t iChunk = 0;
1414	while (cPagesLeft > 0)
1415	{
1416	uint32_t cPagesInChunk = cPagesLeft;
1417	if (cPagesInChunk > cPagesPerChunk)
1418	cPagesInChunk = cPagesPerChunk;
1419
1420	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1421	AssertRCReturn(rc, rc);
1422
1423	/* advance */
1424	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1425	cPagesLeft -= cPagesInChunk;
1426	iChunk++;
1427	}
1428	}
1429	else
1430	{
1431	/*
1432	* Allocate, initialize and link the new RAM range.
1433	*/
1434	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1435	PPGMRAMRANGE pNew;
1436	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1437	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1438
1439	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1440	}
1441	PGMPhysInvalidatePageMapTLB(pVM);
1442	pgmUnlock(pVM);
1443
1444	/*
1445	* Notify REM.
1446	*/
1447	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1448
1449	return VINF_SUCCESS;
1450	}
1451
1452
1453	/**
1454	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1455	*
1456	* We do this late in the init process so that all the ROM and MMIO ranges have
1457	* been registered already and we don't go wasting memory on them.
1458	*
1459	* @returns VBox status code.
1460	*
1461	* @param pVM Pointer to the shared VM structure.
1462	*/
1463	int pgmR3PhysRamPreAllocate(PVM pVM)
1464	{
1465	Assert(pVM->pgm.s.fRamPreAlloc);
1466	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1467
1468	/*
1469	* Walk the RAM ranges and allocate all RAM pages, halt at
1470	* the first allocation error.
1471	*/
1472	uint64_t cPages = 0;
1473	uint64_t NanoTS = RTTimeNanoTS();
1474	pgmLock(pVM);
1475	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1476	{
1477	PPGMPAGE pPage = &pRam->aPages[0];
1478	RTGCPHYS GCPhys = pRam->GCPhys;
1479	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1480	while (cLeft-- > 0)
1481	{
1482	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1483	{
1484	switch (PGM_PAGE_GET_STATE(pPage))
1485	{
1486	case PGM_PAGE_STATE_ZERO:
1487	{
1488	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1489	if (RT_FAILURE(rc))
1490	{
1491	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1492	pgmUnlock(pVM);
1493	return rc;
1494	}
1495	cPages++;
1496	break;
1497	}
1498
1499	case PGM_PAGE_STATE_BALLOONED:
1500	case PGM_PAGE_STATE_ALLOCATED:
1501	case PGM_PAGE_STATE_WRITE_MONITORED:
1502	case PGM_PAGE_STATE_SHARED:
1503	/* nothing to do here. */
1504	break;
1505	}
1506	}
1507
1508	/* next */
1509	pPage++;
1510	GCPhys += PAGE_SIZE;
1511	}
1512	}
1513	pgmUnlock(pVM);
1514	NanoTS = RTTimeNanoTS() - NanoTS;
1515
1516	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1517	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1518	return VINF_SUCCESS;
1519	}
1520
1521
1522	/**
1523	* Resets (zeros) the RAM.
1524	*
1525	* ASSUMES that the caller owns the PGM lock.
1526	*
1527	* @returns VBox status code.
1528	* @param pVM Pointer to the shared VM structure.
1529	*/
1530	int pgmR3PhysRamReset(PVM pVM)
1531	{
1532	Assert(PGMIsLockOwner(pVM));
1533
1534	/* Reset the memory balloon. */
1535	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1536	AssertRC(rc);
1537
1538	#ifdef VBOX_WITH_PAGE_SHARING
1539	/* Clear all registered shared modules. */
1540	rc = GMMR3ResetSharedModules(pVM);
1541	AssertRC(rc);
1542	#endif
1543	/* Reset counters. */
1544	pVM->pgm.s.cReusedSharedPages = 0;
1545	pVM->pgm.s.cBalloonedPages = 0;
1546
1547	/*
1548	* We batch up pages that should be freed instead of calling GMM for
1549	* each and every one of them.
1550	*/
1551	uint32_t cPendingPages = 0;
1552	PGMMFREEPAGESREQ pReq;
1553	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1554	AssertLogRelRCReturn(rc, rc);
1555
1556	/*
1557	* Walk the ram ranges.
1558	*/
1559	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1560	{
1561	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1562	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1563
1564	if (!pVM->pgm.s.fRamPreAlloc)
1565	{
1566	/* Replace all RAM pages by ZERO pages. */
1567	while (iPage-- > 0)
1568	{
1569	PPGMPAGE pPage = &pRam->aPages[iPage];
1570	switch (PGM_PAGE_GET_TYPE(pPage))
1571	{
1572	case PGMPAGETYPE_RAM:
1573	/* Do not replace pages part of a 2 MB continuous range with zero pages, but zero them instead. */
1574	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
1575	{
1576	void *pvPage;
1577	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1578	AssertLogRelRCReturn(rc, rc);
1579	ASMMemZeroPage(pvPage);
1580	}
1581	else
1582	if (PGM_PAGE_IS_BALLOONED(pPage))
1583	{
1584	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1585	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
1586	}
1587	else
1588	if (!PGM_PAGE_IS_ZERO(pPage))
1589	{
1590	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1591	AssertLogRelRCReturn(rc, rc);
1592	}
1593	break;
1594
1595	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1596	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1597	break;
1598
1599	case PGMPAGETYPE_MMIO2:
1600	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1601	case PGMPAGETYPE_ROM:
1602	case PGMPAGETYPE_MMIO:
1603	break;
1604	default:
1605	AssertFailed();
1606	}
1607	} /* for each page */
1608	}
1609	else
1610	{
1611	/* Zero the memory. */
1612	while (iPage-- > 0)
1613	{
1614	PPGMPAGE pPage = &pRam->aPages[iPage];
1615	switch (PGM_PAGE_GET_TYPE(pPage))
1616	{
1617	case PGMPAGETYPE_RAM:
1618	switch (PGM_PAGE_GET_STATE(pPage))
1619	{
1620	case PGM_PAGE_STATE_ZERO:
1621	break;
1622
1623	case PGM_PAGE_STATE_BALLOONED:
1624	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1625	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
1626	break;
1627
1628	case PGM_PAGE_STATE_SHARED:
1629	case PGM_PAGE_STATE_WRITE_MONITORED:
1630	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1631	AssertLogRelRCReturn(rc, rc);
1632	/* no break */
1633
1634	case PGM_PAGE_STATE_ALLOCATED:
1635	{
1636	void *pvPage;
1637	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1638	AssertLogRelRCReturn(rc, rc);
1639	ASMMemZeroPage(pvPage);
1640	break;
1641	}
1642	}
1643	break;
1644
1645	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1646	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1647	break;
1648
1649	case PGMPAGETYPE_MMIO2:
1650	case PGMPAGETYPE_ROM_SHADOW:
1651	case PGMPAGETYPE_ROM:
1652	case PGMPAGETYPE_MMIO:
1653	break;
1654	default:
1655	AssertFailed();
1656
1657	}
1658	} /* for each page */
1659	}
1660
1661	}
1662
1663	/*
1664	* Finish off any pages pending freeing.
1665	*/
1666	if (cPendingPages)
1667	{
1668	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1669	AssertLogRelRCReturn(rc, rc);
1670	}
1671	GMMR3FreePagesCleanup(pReq);
1672
1673	return VINF_SUCCESS;
1674	}
1675
1676	/**
1677	* Frees all RAM during VM termination
1678	*
1679	* ASSUMES that the caller owns the PGM lock.
1680	*
1681	* @returns VBox status code.
1682	* @param pVM Pointer to the shared VM structure.
1683	*/
1684	int pgmR3PhysRamTerm(PVM pVM)
1685	{
1686	Assert(PGMIsLockOwner(pVM));
1687
1688	/* Reset the memory balloon. */
1689	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1690	AssertRC(rc);
1691
1692	#ifdef VBOX_WITH_PAGE_SHARING
1693	/* Clear all registered shared modules. */
1694	rc = GMMR3ResetSharedModules(pVM);
1695	AssertRC(rc);
1696	#endif
1697
1698	/*
1699	* We batch up pages that should be freed instead of calling GMM for
1700	* each and every one of them.
1701	*/
1702	uint32_t cPendingPages = 0;
1703	PGMMFREEPAGESREQ pReq;
1704	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1705	AssertLogRelRCReturn(rc, rc);
1706
1707	/*
1708	* Walk the ram ranges.
1709	*/
1710	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1711	{
1712	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1713	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1714
1715	/* Replace all RAM pages by ZERO pages. */
1716	while (iPage-- > 0)
1717	{
1718	PPGMPAGE pPage = &pRam->aPages[iPage];
1719	switch (PGM_PAGE_GET_TYPE(pPage))
1720	{
1721	case PGMPAGETYPE_RAM:
1722	/* Free all shared pages. Private pages are automatically freed during GMM VM cleanup. */
1723	if (PGM_PAGE_IS_SHARED(pPage))
1724	{
1725	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1726	AssertLogRelRCReturn(rc, rc);
1727	}
1728	break;
1729
1730	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1731	case PGMPAGETYPE_MMIO2:
1732	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1733	case PGMPAGETYPE_ROM:
1734	case PGMPAGETYPE_MMIO:
1735	break;
1736	default:
1737	AssertFailed();
1738	}
1739	} /* for each page */
1740	}
1741
1742	/*
1743	* Finish off any pages pending freeing.
1744	*/
1745	if (cPendingPages)
1746	{
1747	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1748	AssertLogRelRCReturn(rc, rc);
1749	}
1750	GMMR3FreePagesCleanup(pReq);
1751	return VINF_SUCCESS;
1752	}
1753
1754	/**
1755	* This is the interface IOM is using to register an MMIO region.
1756	*
1757	* It will check for conflicts and ensure that a RAM range structure
1758	* is present before calling the PGMR3HandlerPhysicalRegister API to
1759	* register the callbacks.
1760	*
1761	* @returns VBox status code.
1762	*
1763	* @param pVM Pointer to the shared VM structure.
1764	* @param GCPhys The start of the MMIO region.
1765	* @param cb The size of the MMIO region.
1766	* @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1767	* @param pvUserR3 The user argument for R3.
1768	* @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1769	* @param pvUserR0 The user argument for R0.
1770	* @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1771	* @param pvUserRC The user argument for RC.
1772	* @param pszDesc The description of the MMIO region.
1773	*/
1774	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1775	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1776	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1777	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1778	R3PTRTYPE(const char *) pszDesc)
1779	{
1780	/*
1781	* Assert on some assumption.
1782	*/
1783	VM_ASSERT_EMT(pVM);
1784	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1785	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1786	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1787	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1788
1789	/*
1790	* Make sure there's a RAM range structure for the region.
1791	*/
1792	int rc;
1793	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1794	bool fRamExists = false;
1795	PPGMRAMRANGE pRamPrev = NULL;
1796	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1797	while (pRam && GCPhysLast >= pRam->GCPhys)
1798	{
1799	if ( GCPhysLast >= pRam->GCPhys
1800	&& GCPhys <= pRam->GCPhysLast)
1801	{
1802	/* Simplification: all within the same range. */
1803	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1804	&& GCPhysLast <= pRam->GCPhysLast,
1805	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1806	GCPhys, GCPhysLast, pszDesc,
1807	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1808	VERR_PGM_RAM_CONFLICT);
1809
1810	/* Check that it's all RAM or MMIO pages. */
1811	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1812	uint32_t cLeft = cb >> PAGE_SHIFT;
1813	while (cLeft-- > 0)
1814	{
1815	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1816	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1817	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1818	GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1819	VERR_PGM_RAM_CONFLICT);
1820	pPage++;
1821	}
1822
1823	/* Looks good. */
1824	fRamExists = true;
1825	break;
1826	}
1827
1828	/* next */
1829	pRamPrev = pRam;
1830	pRam = pRam->pNextR3;
1831	}
1832	PPGMRAMRANGE pNew;
1833	if (fRamExists)
1834	{
1835	pNew = NULL;
1836
1837	/*
1838	* Make all the pages in the range MMIO/ZERO pages, freeing any
1839	* RAM pages currently mapped here. This might not be 100% correct
1840	* for PCI memory, but we're doing the same thing for MMIO2 pages.
1841	*/
1842	rc = pgmLock(pVM);
1843	if (RT_SUCCESS(rc))
1844	{
1845	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1846	pgmUnlock(pVM);
1847	}
1848	AssertRCReturn(rc, rc);
1849
1850	/* Force a PGM pool flush as guest ram references have been changed. */
1851	/** todo; not entirely SMP safe; assuming for now the guest takes care of this internally (not touch mapped mmio while changing the mapping). */
1852	PVMCPU pVCpu = VMMGetCpu(pVM);
1853	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
1854	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1855	}
1856	else
1857	{
1858	pgmLock(pVM);
1859
1860	/*
1861	* No RAM range, insert an ad hoc one.
1862	*
1863	* Note that we don't have to tell REM about this range because
1864	* PGMHandlerPhysicalRegisterEx will do that for us.
1865	*/
1866	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1867
1868	const uint32_t cPages = cb >> PAGE_SHIFT;
1869	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1870	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1871	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1872
1873	/* Initialize the range. */
1874	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1875	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1876	pNew->GCPhys = GCPhys;
1877	pNew->GCPhysLast = GCPhysLast;
1878	pNew->cb = cb;
1879	pNew->pszDesc = pszDesc;
1880	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
1881	pNew->pvR3 = NULL;
1882	pNew->paLSPages = NULL;
1883
1884	uint32_t iPage = cPages;
1885	while (iPage-- > 0)
1886	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1887	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1888
1889	/* update the page count stats. */
1890	pVM->pgm.s.cPureMmioPages += cPages;
1891	pVM->pgm.s.cAllPages += cPages;
1892
1893	/* link it */
1894	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1895
1896	pgmUnlock(pVM);
1897	}
1898
1899	/*
1900	* Register the access handler.
1901	*/
1902	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1903	pfnHandlerR3, pvUserR3,
1904	pfnHandlerR0, pvUserR0,
1905	pfnHandlerRC, pvUserRC, pszDesc);
1906	if ( RT_FAILURE(rc)
1907	&& !fRamExists)
1908	{
1909	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
1910	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1911
1912	/* remove the ad hoc range. */
1913	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1914	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1915	MMHyperFree(pVM, pRam);
1916	}
1917	PGMPhysInvalidatePageMapTLB(pVM);
1918
1919	return rc;
1920	}
1921
1922
1923	/**
1924	* This is the interface IOM is using to register an MMIO region.
1925	*
1926	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
1927	* any ad hoc PGMRAMRANGE left behind.
1928	*
1929	* @returns VBox status code.
1930	* @param pVM Pointer to the shared VM structure.
1931	* @param GCPhys The start of the MMIO region.
1932	* @param cb The size of the MMIO region.
1933	*/
1934	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1935	{
1936	VM_ASSERT_EMT(pVM);
1937
1938	/*
1939	* First deregister the handler, then check if we should remove the ram range.
1940	*/
1941	int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1942	if (RT_SUCCESS(rc))
1943	{
1944	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1945	PPGMRAMRANGE pRamPrev = NULL;
1946	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1947	while (pRam && GCPhysLast >= pRam->GCPhys)
1948	{
1949	/** @todo We're being a bit too careful here. rewrite. */
1950	if ( GCPhysLast == pRam->GCPhysLast
1951	&& GCPhys == pRam->GCPhys)
1952	{
1953	Assert(pRam->cb == cb);
1954
1955	/*
1956	* See if all the pages are dead MMIO pages.
1957	*/
1958	uint32_t const cPages = cb >> PAGE_SHIFT;
1959	bool fAllMMIO = true;
1960	uint32_t iPage = 0;
1961	uint32_t cLeft = cPages;
1962	while (cLeft-- > 0)
1963	{
1964	PPGMPAGE pPage = &pRam->aPages[iPage];
1965	if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1966	/\|\| not-out-of-action later /)
1967	{
1968	fAllMMIO = false;
1969	Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1970	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1971	break;
1972	}
1973	Assert(PGM_PAGE_IS_ZERO(pPage));
1974	pPage++;
1975	}
1976	if (fAllMMIO)
1977	{
1978	/*
1979	* Ad-hoc range, unlink and free it.
1980	*/
1981	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
1982	GCPhys, GCPhysLast, pRam->pszDesc));
1983
1984	pVM->pgm.s.cAllPages -= cPages;
1985	pVM->pgm.s.cPureMmioPages -= cPages;
1986
1987	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1988	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1989	MMHyperFree(pVM, pRam);
1990	break;
1991	}
1992	}
1993
1994	/*
1995	* Range match? It will all be within one range (see PGMAllHandler.cpp).
1996	*/
1997	if ( GCPhysLast >= pRam->GCPhys
1998	&& GCPhys <= pRam->GCPhysLast)
1999	{
2000	Assert(GCPhys >= pRam->GCPhys);
2001	Assert(GCPhysLast <= pRam->GCPhysLast);
2002
2003	/*
2004	* Turn the pages back into RAM pages.
2005	*/
2006	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2007	uint32_t cLeft = cb >> PAGE_SHIFT;
2008	while (cLeft--)
2009	{
2010	PPGMPAGE pPage = &pRam->aPages[iPage];
2011	AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2012	AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2013	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2014	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
2015	}
2016	break;
2017	}
2018
2019	/* next */
2020	pRamPrev = pRam;
2021	pRam = pRam->pNextR3;
2022	}
2023	}
2024
2025	/* Force a PGM pool flush as guest ram references have been changed. */
2026	/** todo; not entirely SMP safe; assuming for now the guest takes care of this internally (not touch mapped mmio while changing the mapping). */
2027	PVMCPU pVCpu = VMMGetCpu(pVM);
2028	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2029	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2030
2031	PGMPhysInvalidatePageMapTLB(pVM);
2032	return rc;
2033	}
2034
2035
2036	/**
2037	* Locate a MMIO2 range.
2038	*
2039	* @returns Pointer to the MMIO2 range.
2040	* @param pVM Pointer to the shared VM structure.
2041	* @param pDevIns The device instance owning the region.
2042	* @param iRegion The region.
2043	*/
2044	DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
2045	{
2046	/*
2047	* Search the list.
2048	*/
2049	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2050	if ( pCur->pDevInsR3 == pDevIns
2051	&& pCur->iRegion == iRegion)
2052	return pCur;
2053	return NULL;
2054	}
2055
2056
2057	/**
2058	* Allocate and register an MMIO2 region.
2059	*
2060	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2061	* associated with a device. It is also non-shared memory with a permanent
2062	* ring-3 mapping and page backing (presently).
2063	*
2064	* A MMIO2 range may overlap with base memory if a lot of RAM is configured for
2065	* the VM, in which case we'll drop the base memory pages. Presently we will
2066	* make no attempt to preserve anything that happens to be present in the base
2067	* memory that is replaced, this is of course incorrectly but it's too much
2068	* effort.
2069	*
2070	* @returns VBox status code.
2071	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
2072	* memory.
2073	* @retval VERR_ALREADY_EXISTS if the region already exists.
2074	*
2075	* @param pVM Pointer to the shared VM structure.
2076	* @param pDevIns The device instance owning the region.
2077	* @param iRegion The region number. If the MMIO2 memory is a PCI
2078	* I/O region this number has to be the number of that
2079	* region. Otherwise it can be any number safe
2080	* UINT8_MAX.
2081	* @param cb The size of the region. Must be page aligned.
2082	* @param fFlags Reserved for future use, must be zero.
2083	* @param ppv Where to store the pointer to the ring-3 mapping of
2084	* the memory.
2085	* @param pszDesc The description.
2086	*/
2087	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc)
2088	{
2089	/*
2090	* Validate input.
2091	*/
2092	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2093	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2094	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2095	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
2096	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2097	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2098	AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
2099	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2100	AssertReturn(cb, VERR_INVALID_PARAMETER);
2101	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
2102
2103	const uint32_t cPages = cb >> PAGE_SHIFT;
2104	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
2105	AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
2106
2107	/*
2108	* For the 2nd+ instance, mangle the description string so it's unique.
2109	*/
2110	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
2111	{
2112	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
2113	if (!pszDesc)
2114	return VERR_NO_MEMORY;
2115	}
2116
2117	/*
2118	* Try reserve and allocate the backing memory first as this is what is
2119	* most likely to fail.
2120	*/
2121	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
2122	if (RT_SUCCESS(rc))
2123	{
2124	void *pvPages;
2125	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
2126	if (RT_SUCCESS(rc))
2127	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
2128	if (RT_SUCCESS(rc))
2129	{
2130	memset(pvPages, 0, cPages * PAGE_SIZE);
2131
2132	/*
2133	* Create the MMIO2 range record for it.
2134	*/
2135	const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
2136	PPGMMMIO2RANGE pNew;
2137	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2138	AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
2139	if (RT_SUCCESS(rc))
2140	{
2141	pNew->pDevInsR3 = pDevIns;
2142	pNew->pvR3 = pvPages;
2143	//pNew->pNext = NULL;
2144	//pNew->fMapped = false;
2145	//pNew->fOverlapping = false;
2146	pNew->iRegion = iRegion;
2147	pNew->idSavedState = UINT8_MAX;
2148	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
2149	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
2150	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
2151	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
2152	pNew->RamRange.pszDesc = pszDesc;
2153	pNew->RamRange.cb = cb;
2154	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
2155	pNew->RamRange.pvR3 = pvPages;
2156	//pNew->RamRange.paLSPages = NULL;
2157
2158	uint32_t iPage = cPages;
2159	while (iPage-- > 0)
2160	{
2161	PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
2162	paPages[iPage].Phys, NIL_GMM_PAGEID,
2163	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
2164	}
2165
2166	/* update page count stats */
2167	pVM->pgm.s.cAllPages += cPages;
2168	pVM->pgm.s.cPrivatePages += cPages;
2169
2170	/*
2171	* Link it into the list.
2172	* Since there is no particular order, just push it.
2173	*/
2174	pgmLock(pVM);
2175	pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
2176	pVM->pgm.s.pMmio2RangesR3 = pNew;
2177	pgmUnlock(pVM);
2178
2179	*ppv = pvPages;
2180	RTMemTmpFree(paPages);
2181	PGMPhysInvalidatePageMapTLB(pVM);
2182	return VINF_SUCCESS;
2183	}
2184
2185	SUPR3PageFreeEx(pvPages, cPages);
2186	}
2187	RTMemTmpFree(paPages);
2188	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
2189	}
2190	if (pDevIns->iInstance > 0)
2191	MMR3HeapFree((void *)pszDesc);
2192	return rc;
2193	}
2194
2195
2196	/**
2197	* Deregisters and frees an MMIO2 region.
2198	*
2199	* Any physical (and virtual) access handlers registered for the region must
2200	* be deregistered before calling this function.
2201	*
2202	* @returns VBox status code.
2203	* @param pVM Pointer to the shared VM structure.
2204	* @param pDevIns The device instance owning the region.
2205	* @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
2206	*/
2207	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
2208	{
2209	/*
2210	* Validate input.
2211	*/
2212	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2213	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2214	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
2215
2216	pgmLock(pVM);
2217	int rc = VINF_SUCCESS;
2218	unsigned cFound = 0;
2219	PPGMMMIO2RANGE pPrev = NULL;
2220	PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
2221	while (pCur)
2222	{
2223	if ( pCur->pDevInsR3 == pDevIns
2224	&& ( iRegion == UINT32_MAX
2225	\|\| pCur->iRegion == iRegion))
2226	{
2227	cFound++;
2228
2229	/*
2230	* Unmap it if it's mapped.
2231	*/
2232	if (pCur->fMapped)
2233	{
2234	int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
2235	AssertRC(rc2);
2236	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2237	rc = rc2;
2238	}
2239
2240	/*
2241	* Unlink it
2242	*/
2243	PPGMMMIO2RANGE pNext = pCur->pNextR3;
2244	if (pPrev)
2245	pPrev->pNextR3 = pNext;
2246	else
2247	pVM->pgm.s.pMmio2RangesR3 = pNext;
2248	pCur->pNextR3 = NULL;
2249
2250	/*
2251	* Free the memory.
2252	*/
2253	int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
2254	AssertRC(rc2);
2255	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2256	rc = rc2;
2257
2258	uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
2259	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
2260	AssertRC(rc2);
2261	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2262	rc = rc2;
2263
2264	/* we're leaking hyper memory here if done at runtime. */
2265	#ifdef VBOX_STRICT
2266	VMSTATE const enmState = VMR3GetState(pVM);
2267	AssertMsg( enmState == VMSTATE_POWERING_OFF
2268	\|\| enmState == VMSTATE_POWERING_OFF_LS
2269	\|\| enmState == VMSTATE_OFF
2270	\|\| enmState == VMSTATE_OFF_LS
2271	\|\| enmState == VMSTATE_DESTROYING
2272	\|\| enmState == VMSTATE_TERMINATED
2273	\|\| enmState == VMSTATE_CREATING
2274	, ("%s\n", VMR3GetStateName(enmState)));
2275	#endif
2276	/*rc = MMHyperFree(pVM, pCur);
2277	AssertRCReturn(rc, rc); - not safe, see the alloc call. */
2278
2279
2280	/* update page count stats */
2281	pVM->pgm.s.cAllPages -= cPages;
2282	pVM->pgm.s.cPrivatePages -= cPages;
2283
2284	/* next */
2285	pCur = pNext;
2286	}
2287	else
2288	{
2289	pPrev = pCur;
2290	pCur = pCur->pNextR3;
2291	}
2292	}
2293	PGMPhysInvalidatePageMapTLB(pVM);
2294	pgmUnlock(pVM);
2295	return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
2296	}
2297
2298
2299	/**
2300	* Maps a MMIO2 region.
2301	*
2302	* This is done when a guest / the bios / state loading changes the
2303	* PCI config. The replacing of base memory has the same restrictions
2304	* as during registration, of course.
2305	*
2306	* @returns VBox status code.
2307	*
2308	* @param pVM Pointer to the shared VM structure.
2309	* @param pDevIns The
2310	*/
2311	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2312	{
2313	/*
2314	* Validate input
2315	*/
2316	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2317	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2318	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2319	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2320	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2321	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2322
2323	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2324	AssertReturn(pCur, VERR_NOT_FOUND);
2325	AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
2326	Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
2327	Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
2328
2329	const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
2330	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2331
2332	/*
2333	* Find our location in the ram range list, checking for
2334	* restriction we don't bother implementing yet (partially overlapping).
2335	*/
2336	bool fRamExists = false;
2337	PPGMRAMRANGE pRamPrev = NULL;
2338	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2339	while (pRam && GCPhysLast >= pRam->GCPhys)
2340	{
2341	if ( GCPhys <= pRam->GCPhysLast
2342	&& GCPhysLast >= pRam->GCPhys)
2343	{
2344	/* completely within? */
2345	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2346	&& GCPhysLast <= pRam->GCPhysLast,
2347	("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
2348	GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
2349	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2350	VERR_PGM_RAM_CONFLICT);
2351	fRamExists = true;
2352	break;
2353	}
2354
2355	/* next */
2356	pRamPrev = pRam;
2357	pRam = pRam->pNextR3;
2358	}
2359	if (fRamExists)
2360	{
2361	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2362	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2363	while (cPagesLeft-- > 0)
2364	{
2365	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2366	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
2367	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
2368	VERR_PGM_RAM_CONFLICT);
2369	pPage++;
2370	}
2371	}
2372	Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
2373	GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
2374
2375	/*
2376	* Make the changes.
2377	*/
2378	pgmLock(pVM);
2379
2380	pCur->RamRange.GCPhys = GCPhys;
2381	pCur->RamRange.GCPhysLast = GCPhysLast;
2382	pCur->fMapped = true;
2383	pCur->fOverlapping = fRamExists;
2384
2385	if (fRamExists)
2386	{
2387	/** @todo use pgmR3PhysFreePageRange here. */
2388	uint32_t cPendingPages = 0;
2389	PGMMFREEPAGESREQ pReq;
2390	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2391	AssertLogRelRCReturn(rc, rc);
2392
2393	/* replace the pages, freeing all present RAM pages. */
2394	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2395	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2396	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2397	while (cPagesLeft-- > 0)
2398	{
2399	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
2400	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
2401
2402	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
2403	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
2404	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
2405	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
2406	PGM_PAGE_SET_PDE_TYPE(pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
2407	PGM_PAGE_SET_PTE_INDEX(pPageDst, 0);
2408	PGM_PAGE_SET_TRACKING(pPageDst, 0);
2409
2410	pVM->pgm.s.cZeroPages--;
2411	GCPhys += PAGE_SIZE;
2412	pPageSrc++;
2413	pPageDst++;
2414	}
2415
2416	/* Flush physical page map TLB. */
2417	PGMPhysInvalidatePageMapTLB(pVM);
2418
2419	if (cPendingPages)
2420	{
2421	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2422	AssertLogRelRCReturn(rc, rc);
2423	}
2424	GMMR3FreePagesCleanup(pReq);
2425
2426	/* Force a PGM pool flush as guest ram references have been changed. */
2427	/** todo; not entirely SMP safe; assuming for now the guest takes care of this internally (not touch mapped mmio while changing the mapping). */
2428	PVMCPU pVCpu = VMMGetCpu(pVM);
2429	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2430	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2431
2432	pgmUnlock(pVM);
2433	}
2434	else
2435	{
2436	RTGCPHYS cb = pCur->RamRange.cb;
2437
2438	/* Clear the tracking data of pages we're going to reactivate. */
2439	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2440	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2441	while (cPagesLeft-- > 0)
2442	{
2443	PGM_PAGE_SET_TRACKING(pPageSrc, 0);
2444	PGM_PAGE_SET_PTE_INDEX(pPageSrc, 0);
2445	pPageSrc++;
2446	}
2447
2448	/* link in the ram range */
2449	pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
2450	pgmUnlock(pVM);
2451
2452	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
2453	}
2454
2455	PGMPhysInvalidatePageMapTLB(pVM);
2456	return VINF_SUCCESS;
2457	}
2458
2459
2460	/**
2461	* Unmaps a MMIO2 region.
2462	*
2463	* This is done when a guest / the bios / state loading changes the
2464	* PCI config. The replacing of base memory has the same restrictions
2465	* as during registration, of course.
2466	*/
2467	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2468	{
2469	/*
2470	* Validate input
2471	*/
2472	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2473	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2474	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2475	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2476	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2477	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2478
2479	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2480	AssertReturn(pCur, VERR_NOT_FOUND);
2481	AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
2482	AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
2483	Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
2484
2485	Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
2486	pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
2487
2488	/*
2489	* Unmap it.
2490	*/
2491	pgmLock(pVM);
2492
2493	RTGCPHYS GCPhysRangeREM;
2494	RTGCPHYS cbRangeREM;
2495	bool fInformREM;
2496	if (pCur->fOverlapping)
2497	{
2498	/* Restore the RAM pages we've replaced. */
2499	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2500	while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
2501	pRam = pRam->pNextR3;
2502
2503	PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2504	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2505	while (cPagesLeft-- > 0)
2506	{
2507	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
2508	pVM->pgm.s.cZeroPages++;
2509	pPageDst++;
2510	}
2511
2512	/* Flush physical page map TLB. */
2513	PGMPhysInvalidatePageMapTLB(pVM);
2514
2515	GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
2516	cbRangeREM = RTGCPHYS_MAX; /* ditto */
2517	fInformREM = false;
2518	}
2519	else
2520	{
2521	GCPhysRangeREM = pCur->RamRange.GCPhys;
2522	cbRangeREM = pCur->RamRange.cb;
2523	fInformREM = true;
2524
2525	pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
2526	}
2527
2528	pCur->RamRange.GCPhys = NIL_RTGCPHYS;
2529	pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
2530	pCur->fOverlapping = false;
2531	pCur->fMapped = false;
2532
2533	/* Force a PGM pool flush as guest ram references have been changed. */
2534	/** todo; not entirely SMP safe; assuming for now the guest takes care of this internally (not touch mapped mmio while changing the mapping). */
2535	PVMCPU pVCpu = VMMGetCpu(pVM);
2536	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2537	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2538
2539	PGMPhysInvalidatePageMapTLB(pVM);
2540	pgmUnlock(pVM);
2541
2542	if (fInformREM)
2543	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2544
2545	return VINF_SUCCESS;
2546	}
2547
2548
2549	/**
2550	* Checks if the given address is an MMIO2 base address or not.
2551	*
2552	* @returns true/false accordingly.
2553	* @param pVM Pointer to the shared VM structure.
2554	* @param pDevIns The owner of the memory, optional.
2555	* @param GCPhys The address to check.
2556	*/
2557	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2558	{
2559	/*
2560	* Validate input
2561	*/
2562	VM_ASSERT_EMT_RETURN(pVM, false);
2563	AssertPtrReturn(pDevIns, false);
2564	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
2565	AssertReturn(GCPhys != 0, false);
2566	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
2567
2568	/*
2569	* Search the list.
2570	*/
2571	pgmLock(pVM);
2572	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2573	if (pCur->RamRange.GCPhys == GCPhys)
2574	{
2575	Assert(pCur->fMapped);
2576	pgmUnlock(pVM);
2577	return true;
2578	}
2579	pgmUnlock(pVM);
2580	return false;
2581	}
2582
2583
2584	/**
2585	* Gets the HC physical address of a page in the MMIO2 region.
2586	*
2587	* This is API is intended for MMHyper and shouldn't be called
2588	* by anyone else...
2589	*
2590	* @returns VBox status code.
2591	* @param pVM Pointer to the shared VM structure.
2592	* @param pDevIns The owner of the memory, optional.
2593	* @param iRegion The region.
2594	* @param off The page expressed an offset into the MMIO2 region.
2595	* @param pHCPhys Where to store the result.
2596	*/
2597	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2598	{
2599	/*
2600	* Validate input
2601	*/
2602	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2603	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2604	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2605
2606	pgmLock(pVM);
2607	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2608	AssertReturn(pCur, VERR_NOT_FOUND);
2609	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2610
2611	PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2612	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2613	pgmUnlock(pVM);
2614	return VINF_SUCCESS;
2615	}
2616
2617
2618	/**
2619	* Maps a portion of an MMIO2 region into kernel space (host).
2620	*
2621	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
2622	* or the VM is terminated.
2623	*
2624	* @return VBox status code.
2625	*
2626	* @param pVM Pointer to the shared VM structure.
2627	* @param pDevIns The device owning the MMIO2 memory.
2628	* @param iRegion The region.
2629	* @param off The offset into the region. Must be page aligned.
2630	* @param cb The number of bytes to map. Must be page aligned.
2631	* @param pszDesc Mapping description.
2632	* @param pR0Ptr Where to store the R0 address.
2633	*/
2634	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2635	const char *pszDesc, PRTR0PTR pR0Ptr)
2636	{
2637	/*
2638	* Validate input.
2639	*/
2640	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2641	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2642	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2643
2644	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2645	AssertReturn(pCur, VERR_NOT_FOUND);
2646	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2647	AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2648	AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2649
2650	/*
2651	* Pass the request on to the support library/driver.
2652	*/
2653	int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2654
2655	return rc;
2656	}
2657
2658
2659	/**
2660	* Registers a ROM image.
2661	*
2662	* Shadowed ROM images requires double the amount of backing memory, so,
2663	* don't use that unless you have to. Shadowing of ROM images is process
2664	* where we can select where the reads go and where the writes go. On real
2665	* hardware the chipset provides means to configure this. We provide
2666	* PGMR3PhysProtectROM() for this purpose.
2667	*
2668	* A read-only copy of the ROM image will always be kept around while we
2669	* will allocate RAM pages for the changes on demand (unless all memory
2670	* is configured to be preallocated).
2671	*
2672	* @returns VBox status.
2673	* @param pVM VM Handle.
2674	* @param pDevIns The device instance owning the ROM.
2675	* @param GCPhys First physical address in the range.
2676	* Must be page aligned!
2677	* @param cbRange The size of the range (in bytes).
2678	* Must be page aligned!
2679	* @param pvBinary Pointer to the binary data backing the ROM image.
2680	* This must be exactly \a cbRange in size.
2681	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2682	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2683	* @param pszDesc Pointer to description string. This must not be freed.
2684	*
2685	* @remark There is no way to remove the rom, automatically on device cleanup or
2686	* manually from the device yet. This isn't difficult in any way, it's
2687	* just not something we expect to be necessary for a while.
2688	*/
2689	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2690	const void pvBinary, uint32_t fFlags, const char pszDesc)
2691	{
2692	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2693	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2694
2695	/*
2696	* Validate input.
2697	*/
2698	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2699	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2700	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2701	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2702	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2703	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2704	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2705	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2706	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2707
2708	const uint32_t cPages = cb >> PAGE_SHIFT;
2709
2710	/*
2711	* Find the ROM location in the ROM list first.
2712	*/
2713	PPGMROMRANGE pRomPrev = NULL;
2714	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2715	while (pRom && GCPhysLast >= pRom->GCPhys)
2716	{
2717	if ( GCPhys <= pRom->GCPhysLast
2718	&& GCPhysLast >= pRom->GCPhys)
2719	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2720	GCPhys, GCPhysLast, pszDesc,
2721	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2722	VERR_PGM_RAM_CONFLICT);
2723	/* next */
2724	pRomPrev = pRom;
2725	pRom = pRom->pNextR3;
2726	}
2727
2728	/*
2729	* Find the RAM location and check for conflicts.
2730	*
2731	* Conflict detection is a bit different than for RAM
2732	* registration since a ROM can be located within a RAM
2733	* range. So, what we have to check for is other memory
2734	* types (other than RAM that is) and that we don't span
2735	* more than one RAM range (layz).
2736	*/
2737	bool fRamExists = false;
2738	PPGMRAMRANGE pRamPrev = NULL;
2739	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2740	while (pRam && GCPhysLast >= pRam->GCPhys)
2741	{
2742	if ( GCPhys <= pRam->GCPhysLast
2743	&& GCPhysLast >= pRam->GCPhys)
2744	{
2745	/* completely within? */
2746	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2747	&& GCPhysLast <= pRam->GCPhysLast,
2748	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2749	GCPhys, GCPhysLast, pszDesc,
2750	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2751	VERR_PGM_RAM_CONFLICT);
2752	fRamExists = true;
2753	break;
2754	}
2755
2756	/* next */
2757	pRamPrev = pRam;
2758	pRam = pRam->pNextR3;
2759	}
2760	if (fRamExists)
2761	{
2762	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2763	uint32_t cPagesLeft = cPages;
2764	while (cPagesLeft-- > 0)
2765	{
2766	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2767	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2768	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2769	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2770	Assert(PGM_PAGE_IS_ZERO(pPage));
2771	pPage++;
2772	}
2773	}
2774
2775	/*
2776	* Update the base memory reservation if necessary.
2777	*/
2778	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
2779	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2780	cExtraBaseCost += cPages;
2781	if (cExtraBaseCost)
2782	{
2783	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2784	if (RT_FAILURE(rc))
2785	return rc;
2786	}
2787
2788	/*
2789	* Allocate memory for the virgin copy of the RAM.
2790	*/
2791	PGMMALLOCATEPAGESREQ pReq;
2792	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2793	AssertRCReturn(rc, rc);
2794
2795	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2796	{
2797	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2798	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2799	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2800	}
2801
2802	pgmLock(pVM);
2803	rc = GMMR3AllocatePagesPerform(pVM, pReq);
2804	pgmUnlock(pVM);
2805	if (RT_FAILURE(rc))
2806	{
2807	GMMR3AllocatePagesCleanup(pReq);
2808	return rc;
2809	}
2810
2811	/*
2812	* Allocate the new ROM range and RAM range (if necessary).
2813	*/
2814	PPGMROMRANGE pRomNew;
2815	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2816	if (RT_SUCCESS(rc))
2817	{
2818	PPGMRAMRANGE pRamNew = NULL;
2819	if (!fRamExists)
2820	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2821	if (RT_SUCCESS(rc))
2822	{
2823	pgmLock(pVM);
2824
2825	/*
2826	* Initialize and insert the RAM range (if required).
2827	*/
2828	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2829	if (!fRamExists)
2830	{
2831	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2832	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2833	pRamNew->GCPhys = GCPhys;
2834	pRamNew->GCPhysLast = GCPhysLast;
2835	pRamNew->cb = cb;
2836	pRamNew->pszDesc = pszDesc;
2837	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
2838	pRamNew->pvR3 = NULL;
2839	pRamNew->paLSPages = NULL;
2840
2841	PPGMPAGE pPage = &pRamNew->aPages[0];
2842	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2843	{
2844	PGM_PAGE_INIT(pPage,
2845	pReq->aPages[iPage].HCPhysGCPhys,
2846	pReq->aPages[iPage].idPage,
2847	PGMPAGETYPE_ROM,
2848	PGM_PAGE_STATE_ALLOCATED);
2849
2850	pRomPage->Virgin = *pPage;
2851	}
2852
2853	pVM->pgm.s.cAllPages += cPages;
2854	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2855	}
2856	else
2857	{
2858	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2859	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2860	{
2861	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2862	PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2863	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2864	PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2865	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
2866	PGM_PAGE_SET_PTE_INDEX(pPage, 0);
2867	PGM_PAGE_SET_TRACKING(pPage, 0);
2868
2869	pRomPage->Virgin = *pPage;
2870	}
2871
2872	pRamNew = pRam;
2873
2874	pVM->pgm.s.cZeroPages -= cPages;
2875	}
2876	pVM->pgm.s.cPrivatePages += cPages;
2877
2878	/* Flush physical page map TLB. */
2879	PGMPhysInvalidatePageMapTLB(pVM);
2880
2881	pgmUnlock(pVM);
2882
2883
2884	/*
2885	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2886	*
2887	* If it's shadowed we'll register the handler after the ROM notification
2888	* so we get the access handler callbacks that we should. If it isn't
2889	* shadowed we'll do it the other way around to make REM use the built-in
2890	* ROM behavior and not the handler behavior (which is to route all access
2891	* to PGM atm).
2892	*/
2893	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2894	{
2895	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2896	rc = PGMR3HandlerPhysicalRegister(pVM,
2897	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2898	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2899	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2900	GCPhys, GCPhysLast,
2901	pgmR3PhysRomWriteHandler, pRomNew,
2902	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2903	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2904	}
2905	else
2906	{
2907	rc = PGMR3HandlerPhysicalRegister(pVM,
2908	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2909	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2910	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2911	GCPhys, GCPhysLast,
2912	pgmR3PhysRomWriteHandler, pRomNew,
2913	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2914	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2915	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2916	}
2917	if (RT_SUCCESS(rc))
2918	{
2919	pgmLock(pVM);
2920
2921	/*
2922	* Copy the image over to the virgin pages.
2923	* This must be done after linking in the RAM range.
2924	*/
2925	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2926	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2927	{
2928	void *pvDstPage;
2929	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
2930	if (RT_FAILURE(rc))
2931	{
2932	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2933	break;
2934	}
2935	memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2936	}
2937	if (RT_SUCCESS(rc))
2938	{
2939	/*
2940	* Initialize the ROM range.
2941	* Note that the Virgin member of the pages has already been initialized above.
2942	*/
2943	pRomNew->GCPhys = GCPhys;
2944	pRomNew->GCPhysLast = GCPhysLast;
2945	pRomNew->cb = cb;
2946	pRomNew->fFlags = fFlags;
2947	pRomNew->idSavedState = UINT8_MAX;
2948	#ifdef VBOX_STRICT
2949	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY
2950	? pvBinary : RTMemDup(pvBinary, cPages * PAGE_SIZE);
2951	#else
2952	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2953	#endif
2954	pRomNew->pszDesc = pszDesc;
2955
2956	for (unsigned iPage = 0; iPage < cPages; iPage++)
2957	{
2958	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2959	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2960	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2961	}
2962
2963	/* update the page count stats for the shadow pages. */
2964	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2965	{
2966	pVM->pgm.s.cZeroPages += cPages;
2967	pVM->pgm.s.cAllPages += cPages;
2968	}
2969
2970	/*
2971	* Insert the ROM range, tell REM and return successfully.
2972	*/
2973	pRomNew->pNextR3 = pRom;
2974	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2975	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2976
2977	if (pRomPrev)
2978	{
2979	pRomPrev->pNextR3 = pRomNew;
2980	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2981	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2982	}
2983	else
2984	{
2985	pVM->pgm.s.pRomRangesR3 = pRomNew;
2986	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2987	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2988	}
2989
2990	PGMPhysInvalidatePageMapTLB(pVM);
2991	GMMR3AllocatePagesCleanup(pReq);
2992	pgmUnlock(pVM);
2993	return VINF_SUCCESS;
2994	}
2995
2996	/* bail out */
2997
2998	pgmUnlock(pVM);
2999	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
3000	AssertRC(rc2);
3001	pgmLock(pVM);
3002	}
3003
3004	if (!fRamExists)
3005	{
3006	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
3007	MMHyperFree(pVM, pRamNew);
3008	}
3009	}
3010	MMHyperFree(pVM, pRomNew);
3011	}
3012
3013	/** @todo Purge the mapping cache or something... */
3014	GMMR3FreeAllocatedPages(pVM, pReq);
3015	GMMR3AllocatePagesCleanup(pReq);
3016	pgmUnlock(pVM);
3017	return rc;
3018	}
3019
3020
3021	/**
3022	* \#PF Handler callback for ROM write accesses.
3023	*
3024	* @returns VINF_SUCCESS if the handler have carried out the operation.
3025	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
3026	* @param pVM VM Handle.
3027	* @param GCPhys The physical address the guest is writing to.
3028	* @param pvPhys The HC mapping of that address.
3029	* @param pvBuf What the guest is reading/writing.
3030	* @param cbBuf How much it's reading/writing.
3031	* @param enmAccessType The access type.
3032	* @param pvUser User argument.
3033	*/
3034	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
3035	PGMACCESSTYPE enmAccessType, void *pvUser)
3036	{
3037	PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
3038	const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
3039	Assert(iPage < (pRom->cb >> PAGE_SHIFT));
3040	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
3041	Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
3042
3043	if (enmAccessType == PGMACCESSTYPE_READ)
3044	{
3045	switch (pRomPage->enmProt)
3046	{
3047	/*
3048	* Take the default action.
3049	*/
3050	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
3051	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
3052	case PGMROMPROT_READ_ROM_WRITE_RAM:
3053	case PGMROMPROT_READ_RAM_WRITE_RAM:
3054	return VINF_PGM_HANDLER_DO_DEFAULT;
3055
3056	default:
3057	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
3058	pRom->aPages[iPage].enmProt, iPage, GCPhys),
3059	VERR_INTERNAL_ERROR);
3060	}
3061	}
3062	else
3063	{
3064	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
3065	switch (pRomPage->enmProt)
3066	{
3067	/*
3068	* Ignore writes.
3069	*/
3070	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
3071	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
3072	return VINF_SUCCESS;
3073
3074	/*
3075	* Write to the RAM page.
3076	*/
3077	case PGMROMPROT_READ_ROM_WRITE_RAM:
3078	case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's way simpler that way. */
3079	{
3080	/* This should be impossible now, pvPhys doesn't work cross page anylonger. */
3081	Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
3082
3083	/*
3084	* Take the lock, do lazy allocation, map the page and copy the data.
3085	*
3086	* Note that we have to bypass the mapping TLB since it works on
3087	* guest physical addresses and entering the shadow page would
3088	* kind of screw things up...
3089	*/
3090	int rc = pgmLock(pVM);
3091	AssertRC(rc);
3092
3093	PPGMPAGE pShadowPage = &pRomPage->Shadow;
3094	if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
3095	{
3096	pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
3097	AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
3098	}
3099
3100	void *pvDstPage;
3101	rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
3102	if (RT_SUCCESS(rc))
3103	{
3104	memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
3105	pRomPage->LiveSave.fWrittenTo = true;
3106	}
3107
3108	pgmUnlock(pVM);
3109	return rc;
3110	}
3111
3112	default:
3113	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
3114	pRom->aPages[iPage].enmProt, iPage, GCPhys),
3115	VERR_INTERNAL_ERROR);
3116	}
3117	}
3118	}
3119
3120
3121	/**
3122	* Called by PGMR3Reset to reset the shadow, switch to the virgin,
3123	* and verify that the virgin part is untouched.
3124	*
3125	* This is done after the normal memory has been cleared.
3126	*
3127	* ASSUMES that the caller owns the PGM lock.
3128	*
3129	* @param pVM The VM handle.
3130	*/
3131	int pgmR3PhysRomReset(PVM pVM)
3132	{
3133	Assert(PGMIsLockOwner(pVM));
3134	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
3135	{
3136	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
3137
3138	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
3139	{
3140	/*
3141	* Reset the physical handler.
3142	*/
3143	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
3144	AssertRCReturn(rc, rc);
3145
3146	/*
3147	* What we do with the shadow pages depends on the memory
3148	* preallocation option. If not enabled, we'll just throw
3149	* out all the dirty pages and replace them by the zero page.
3150	*/
3151	if (!pVM->pgm.s.fRamPreAlloc)
3152	{
3153	/* Free the dirty pages. */
3154	uint32_t cPendingPages = 0;
3155	PGMMFREEPAGESREQ pReq;
3156	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3157	AssertRCReturn(rc, rc);
3158
3159	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3160	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
3161	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
3162	{
3163	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
3164	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow,
3165	pRom->GCPhys + (iPage << PAGE_SHIFT));
3166	AssertLogRelRCReturn(rc, rc);
3167	}
3168
3169	if (cPendingPages)
3170	{
3171	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
3172	AssertLogRelRCReturn(rc, rc);
3173	}
3174	GMMR3FreePagesCleanup(pReq);
3175	}
3176	else
3177	{
3178	/* clear all the shadow pages. */
3179	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3180	{
3181	Assert(!PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow));
3182	Assert(!PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
3183	void *pvDstPage;
3184	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
3185	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
3186	if (RT_FAILURE(rc))
3187	break;
3188	ASMMemZeroPage(pvDstPage);
3189	}
3190	AssertRCReturn(rc, rc);
3191	}
3192	}
3193
3194	#ifdef VBOX_STRICT
3195	/*
3196	* Verify that the virgin page is unchanged if possible.
3197	*/
3198	if (pRom->pvOriginal)
3199	{
3200	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
3201	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
3202	{
3203	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
3204	void const *pvDstPage;
3205	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
3206	if (RT_FAILURE(rc))
3207	break;
3208	if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
3209	LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
3210	GCPhys, pRom->pszDesc));
3211	}
3212	}
3213	#endif
3214	}
3215
3216	return VINF_SUCCESS;
3217	}
3218
3219
3220	/**
3221	* Called by PGMR3Term to free resources.
3222	*
3223	* ASSUMES that the caller owns the PGM lock.
3224	*
3225	* @param pVM The VM handle.
3226	*/
3227	void pgmR3PhysRomTerm(PVM pVM)
3228	{
3229	#ifdef RT_STRICT
3230	/*
3231	* Free the heap copy of the original bits.
3232	*/
3233	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
3234	{
3235	if ( pRom->pvOriginal
3236	&& !(pRom->fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY))
3237	{
3238	RTMemFree((void *)pRom->pvOriginal);
3239	pRom->pvOriginal = NULL;
3240	}
3241	}
3242	#endif
3243	}
3244
3245
3246	/**
3247	* Change the shadowing of a range of ROM pages.
3248	*
3249	* This is intended for implementing chipset specific memory registers
3250	* and will not be very strict about the input. It will silently ignore
3251	* any pages that are not the part of a shadowed ROM.
3252	*
3253	* @returns VBox status code.
3254	* @retval VINF_PGM_SYNC_CR3
3255	*
3256	* @param pVM Pointer to the shared VM structure.
3257	* @param GCPhys Where to start. Page aligned.
3258	* @param cb How much to change. Page aligned.
3259	* @param enmProt The new ROM protection.
3260	*/
3261	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
3262	{
3263	/*
3264	* Check input
3265	*/
3266	if (!cb)
3267	return VINF_SUCCESS;
3268	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3269	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3270	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
3271	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3272	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
3273
3274	/*
3275	* Process the request.
3276	*/
3277	pgmLock(pVM);
3278	int rc = VINF_SUCCESS;
3279	bool fFlushTLB = false;
3280	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
3281	{
3282	if ( GCPhys <= pRom->GCPhysLast
3283	&& GCPhysLast >= pRom->GCPhys
3284	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
3285	{
3286	/*
3287	* Iterate the relevant pages and make necessary the changes.
3288	*/
3289	bool fChanges = false;
3290	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
3291	? pRom->cb >> PAGE_SHIFT
3292	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
3293	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
3294	iPage < cPages;
3295	iPage++)
3296	{
3297	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
3298	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
3299	{
3300	fChanges = true;
3301
3302	/* flush references to the page. */
3303	PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
3304	int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage, &fFlushTLB);
3305	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
3306	rc = rc2;
3307
3308	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
3309	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
3310
3311	pOld = pRamPage;
3312	pRamPage = pNew;
3313	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
3314	}
3315	pRomPage->enmProt = enmProt;
3316	}
3317
3318	/*
3319	* Reset the access handler if we made changes, no need
3320	* to optimize this.
3321	*/
3322	if (fChanges)
3323	{
3324	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
3325	if (RT_FAILURE(rc2))
3326	{
3327	pgmUnlock(pVM);
3328	AssertRC(rc);
3329	return rc2;
3330	}
3331	}
3332
3333	/* Advance - cb isn't updated. */
3334	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
3335	}
3336	}
3337	pgmUnlock(pVM);
3338	if (fFlushTLB)
3339	PGM_INVL_ALL_VCPU_TLBS(pVM);
3340
3341	return rc;
3342	}
3343
3344
3345	/**
3346	* Sets the Address Gate 20 state.
3347	*
3348	* @param pVCpu The VCPU to operate on.
3349	* @param fEnable True if the gate should be enabled.
3350	* False if the gate should be disabled.
3351	*/
3352	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
3353	{
3354	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
3355	if (pVCpu->pgm.s.fA20Enabled != fEnable)
3356	{
3357	pVCpu->pgm.s.fA20Enabled = fEnable;
3358	pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
3359	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
3360	/** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
3361	}
3362	}
3363
3364	#ifdef PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
3365	/**
3366	* Tree enumeration callback for dealing with age rollover.
3367	* It will perform a simple compression of the current age.
3368	*/
3369	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
3370	{
3371	Assert(PGMIsLockOwner((PVM)pvUser));
3372	/* Age compression - ASSUMES iNow == 4. */
3373	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3374	if (pChunk->iAge >= UINT32_C(0xffffff00))
3375	pChunk->iAge = 3;
3376	else if (pChunk->iAge >= UINT32_C(0xfffff000))
3377	pChunk->iAge = 2;
3378	else if (pChunk->iAge)
3379	pChunk->iAge = 1;
3380	else /* iAge = 0 */
3381	pChunk->iAge = 4;
3382	return 0;
3383	}
3384
3385
3386	/**
3387	* Tree enumeration callback that updates the chunks that have
3388	* been used since the last
3389	*/
3390	static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
3391	{
3392	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3393	if (!pChunk->iAge)
3394	{
3395	PVM pVM = (PVM)pvUser;
3396	pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
3397	}
3398	return 0;
3399	}
3400
3401
3402	/**
3403	* Performs ageing of the ring-3 chunk mappings.
3404	*
3405	* @param pVM The VM handle.
3406	*/
3407	VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
3408	{
3409	pgmLock(pVM);
3410	pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
3411	pVM->pgm.s.ChunkR3Map.iNow++;
3412	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
3413	{
3414	pVM->pgm.s.ChunkR3Map.iNow = 4;
3415	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
3416	}
3417	else
3418	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingCallback, pVM);
3419	pgmUnlock(pVM);
3420	}
3421
3422
3423	/**
3424	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
3425	*/
3426	typedef struct PGMR3PHYSCHUNKUNMAPCB
3427	{
3428	PVM pVM; /*< The VM handle. /
3429	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
3430	uint32_t iLastAge; /*< Highest age found so far. /
3431	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
3432
3433
3434	/**
3435	* Callback used to find the mapping that's been unused for
3436	* the longest time.
3437	*/
3438	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLU32NODECORE pNode, void *pvUser)
3439	{
3440	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3441	PPGMR3PHYSCHUNKUNMAPCB pArg = (PPGMR3PHYSCHUNKUNMAPCB)pvUser;
3442
3443	if ( pChunk->iAge
3444	&& !pChunk->cRefs
3445	&& pArg->iLastAge < pChunk->iAge)
3446	{
3447	/*
3448	* Check that it's not in any of the TLBs.
3449	*/
3450	PVM pVM = pArg->pVM;
3451	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3452	if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
3453	{
3454	pChunk = NULL;
3455	break;
3456	}
3457	if (pChunk)
3458	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
3459	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
3460	{
3461	pChunk = NULL;
3462	break;
3463	}
3464	if (pChunk)
3465	{
3466	pArg->pChunk = pChunk;
3467	pArg->iLastAge = pChunk->iAge;
3468	}
3469	}
3470	return 0;
3471	}
3472
3473
3474	/**
3475	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
3476	*
3477	* The candidate will not be part of any TLBs, so no need to flush
3478	* anything afterwards.
3479	*
3480	* @returns Chunk id.
3481	* @param pVM The VM handle.
3482	*/
3483	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
3484	{
3485	Assert(PGMIsLockOwner(pVM));
3486
3487	/*
3488	* Do tree ageing first?
3489	*/
3490	if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
3491	{
3492	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkAging, a);
3493	PGMR3PhysChunkAgeing(pVM);
3494	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkAging, a);
3495	}
3496
3497	/*
3498	* Enumerate the age tree starting with the left most node.
3499	*/
3500	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
3501	PGMR3PHYSCHUNKUNMAPCB Args;
3502	Args.pVM = pVM;
3503	Args.pChunk = NULL;
3504	Args.iLastAge = 0;
3505	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, &Args);
3506	Assert(Args.pChunk);
3507	if (Args.pChunk)
3508	{
3509	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
3510	return Args.pChunk->Core.Key;
3511	}
3512
3513	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
3514	return INT32_MAX;
3515	}
3516
3517	/**
3518	* Rendezvous callback used by pgmR3PhysUnmapChunk that unmaps a chunk
3519	*
3520	* This is only called on one of the EMTs while the other ones are waiting for
3521	* it to complete this function.
3522	*
3523	* @returns VINF_SUCCESS (VBox strict status code).
3524	* @param pVM The VM handle.
3525	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
3526	* @param pvUser User pointer. Unused
3527	*
3528	*/
3529	DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
3530	{
3531	int rc = VINF_SUCCESS;
3532	pgmLock(pVM);
3533
3534	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3535	{
3536	/* Flush the pgm pool cache; call the internal rendezvous handler as we're already in a rendezvous handler here. */
3537	/* todo: also not really efficient to unmap a chunk that contains PD or PT pages. */
3538	pgmR3PoolClearAllRendezvous(pVM, &pVM->aCpus[0], NULL /* no need to flush the REM TLB as we already did that above */);
3539
3540	/*
3541	* Request the ring-0 part to unmap a chunk to make space in the mapping cache.
3542	*/
3543	GMMMAPUNMAPCHUNKREQ Req;
3544	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3545	Req.Hdr.cbReq = sizeof(Req);
3546	Req.pvR3 = NULL;
3547	Req.idChunkMap = NIL_GMM_CHUNKID;
3548	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
3549
3550	if (Req.idChunkUnmap != INT32_MAX)
3551	{
3552	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
3553	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3554	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
3555	if (RT_SUCCESS(rc))
3556	{
3557	/* remove the unmapped one. */
3558	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
3559	AssertRelease(pUnmappedChunk);
3560	pUnmappedChunk->pv = NULL;
3561	pUnmappedChunk->Core.Key = UINT32_MAX;
3562	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3563	MMR3HeapFree(pUnmappedChunk);
3564	#else
3565	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3566	#endif
3567	pVM->pgm.s.ChunkR3Map.c--;
3568	pVM->pgm.s.cUnmappedChunks++;
3569
3570	/* Flush dangling PGM pointers (R3 & R0 ptrs to GC physical addresses) */
3571	/* todo: we should not flush chunks which include cr3 mappings. */
3572	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3573	{
3574	PPGMCPU pPGM = &pVM->aCpus[idCpu].pgm.s;
3575
3576	pPGM->pGst32BitPdR3 = NULL;
3577	pPGM->pGstPaePdptR3 = NULL;
3578	pPGM->pGstAmd64Pml4R3 = NULL;
3579	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3580	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
3581	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
3582	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
3583	#endif
3584	for (unsigned i = 0; i < RT_ELEMENTS(pPGM->apGstPaePDsR3); i++)
3585	{
3586	pPGM->apGstPaePDsR3[i] = NULL;
3587	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3588	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
3589	#endif
3590	}
3591
3592	/* Flush REM TLBs. */
3593	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3594	}
3595
3596	/* Flush REM translation blocks. */
3597	REMFlushTBs(pVM);
3598	}
3599	}
3600	}
3601	pgmUnlock(pVM);
3602	return rc;
3603	}
3604
3605	/**
3606	* Unmap a chunk to free up virtual address space (request packet handler for pgmR3PhysChunkMap)
3607	*
3608	* @returns VBox status code.
3609	* @param pVM The VM to operate on.
3610	*/
3611	void pgmR3PhysUnmapChunk(PVM pVM)
3612	{
3613	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysUnmapChunkRendezvous, NULL);
3614	AssertRC(rc);
3615	}
3616	#endif /* PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST */
3617
3618	/**
3619	* Maps the given chunk into the ring-3 mapping cache.
3620	*
3621	* This will call ring-0.
3622	*
3623	* @returns VBox status code.
3624	* @param pVM The VM handle.
3625	* @param idChunk The chunk in question.
3626	* @param ppChunk Where to store the chunk tracking structure.
3627	*
3628	* @remarks Called from within the PGM critical section.
3629	* @remarks Can be called from any thread!
3630	*/
3631	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
3632	{
3633	int rc;
3634
3635	Assert(PGMIsLockOwner(pVM));
3636	/*
3637	* Allocate a new tracking structure first.
3638	*/
3639	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3640	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
3641	#else
3642	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
3643	#endif
3644	AssertReturn(pChunk, VERR_NO_MEMORY);
3645	pChunk->Core.Key = idChunk;
3646
3647	/*
3648	* Request the ring-0 part to map the chunk in question.
3649	*/
3650	GMMMAPUNMAPCHUNKREQ Req;
3651	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3652	Req.Hdr.cbReq = sizeof(Req);
3653	Req.pvR3 = NULL;
3654	Req.idChunkMap = idChunk;
3655	Req.idChunkUnmap = NIL_GMM_CHUNKID;
3656
3657	/* Must be callable from any thread, so can't use VMMR3CallR0. */
3658	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
3659	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, NIL_VMCPUID, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3660	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
3661	if (RT_SUCCESS(rc))
3662	{
3663	/*
3664	* Update the tree.
3665	*/
3666	/* insert the new one. */
3667	AssertPtr(Req.pvR3);
3668	pChunk->pv = Req.pvR3;
3669	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
3670	AssertRelease(fRc);
3671	pVM->pgm.s.ChunkR3Map.c++;
3672	pVM->pgm.s.cMappedChunks++;
3673
3674	/* If we're running out of virtual address space, then we should unmap another chunk. */
3675	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3676	{
3677	#ifdef PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
3678	/* Postpone the unmap operation (which requires a rendezvous operation) as we own the PGM lock here. */
3679	rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysUnmapChunk, 1, pVM);
3680	AssertRC(rc);
3681	#else
3682	AssertFatalFailed(); /* can't happen */
3683	#endif
3684	}
3685	}
3686	else
3687	{
3688	AssertRC(rc);
3689	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3690	MMR3HeapFree(pChunk);
3691	#else
3692	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
3693	#endif
3694	pChunk = NULL;
3695	}
3696
3697	*ppChunk = pChunk;
3698	return rc;
3699	}
3700
3701
3702	/**
3703	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3704	*
3705	* @returns see pgmR3PhysChunkMap.
3706	* @param pVM The VM handle.
3707	* @param idChunk The chunk to map.
3708	*/
3709	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3710	{
3711	PPGMCHUNKR3MAP pChunk;
3712	int rc;
3713
3714	pgmLock(pVM);
3715	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3716	pgmUnlock(pVM);
3717	return rc;
3718	}
3719
3720
3721	/**
3722	* Invalidates the TLB for the ring-3 mapping cache.
3723	*
3724	* @param pVM The VM handle.
3725	*/
3726	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3727	{
3728	pgmLock(pVM);
3729	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3730	{
3731	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3732	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3733	}
3734	/* The page map TLB references chunks, so invalidate that one too. */
3735	PGMPhysInvalidatePageMapTLB(pVM);
3736	pgmUnlock(pVM);
3737	}
3738
3739
3740	/**
3741	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_PAGE to allocate a large (2MB) page
3742	* for use with a nested paging PDE.
3743	*
3744	* @returns The following VBox status codes.
3745	* @retval VINF_SUCCESS on success.
3746	* @retval VINF_EM_NO_MEMORY if we're out of memory.
3747	*
3748	* @param pVM The VM handle.
3749	* @param GCPhys GC physical start address of the 2 MB range
3750	*/
3751	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
3752	{
3753	pgmLock(pVM);
3754
3755	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
3756	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
3757	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
3758	if (RT_SUCCESS(rc))
3759	{
3760	Assert(pVM->pgm.s.cLargeHandyPages == 1);
3761
3762	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
3763	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
3764
3765	void *pv;
3766
3767	/* Map the large page into our address space.
3768	*
3769	* Note: assuming that within the 2 MB range:
3770	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
3771	* - user space mapping is continuous as well
3772	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
3773	*/
3774	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
3775	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n", idPage, HCPhys, rc));
3776
3777	if (RT_SUCCESS(rc))
3778	{
3779	/*
3780	* Clear the pages.
3781	*/
3782	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
3783	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
3784	{
3785	ASMMemZeroPage(pv);
3786
3787	PPGMPAGE pPage;
3788	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
3789	AssertRC(rc);
3790
3791	Assert(PGM_PAGE_IS_ZERO(pPage));
3792	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRZPageReplaceZero);
3793	pVM->pgm.s.cZeroPages--;
3794
3795	/*
3796	* Do the PGMPAGE modifications.
3797	*/
3798	pVM->pgm.s.cPrivatePages++;
3799	PGM_PAGE_SET_HCPHYS(pPage, HCPhys);
3800	PGM_PAGE_SET_PAGEID(pPage, idPage);
3801	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
3802	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_PDE);
3803	PGM_PAGE_SET_PTE_INDEX(pPage, 0);
3804	PGM_PAGE_SET_TRACKING(pPage, 0);
3805
3806	/* Somewhat dirty assumption that page ids are increasing. */
3807	idPage++;
3808
3809	HCPhys += PAGE_SIZE;
3810	GCPhys += PAGE_SIZE;
3811
3812	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
3813
3814	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
3815	}
3816	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
3817
3818	/* Flush all TLBs. */
3819	PGM_INVL_ALL_VCPU_TLBS(pVM);
3820	PGMPhysInvalidatePageMapTLB(pVM);
3821	}
3822	pVM->pgm.s.cLargeHandyPages = 0;
3823	}
3824
3825	pgmUnlock(pVM);
3826	return rc;
3827	}
3828
3829
3830	/**
3831	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3832	*
3833	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3834	* signal and clear the out of memory condition. When contracted, this API is
3835	* used to try clear the condition when the user wants to resume.
3836	*
3837	* @returns The following VBox status codes.
3838	* @retval VINF_SUCCESS on success. FFs cleared.
3839	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3840	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3841	*
3842	* @param pVM The VM handle.
3843	*
3844	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3845	* in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3846	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3847	* handler.
3848	*/
3849	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3850	{
3851	pgmLock(pVM);
3852
3853	/*
3854	* Allocate more pages, noting down the index of the first new page.
3855	*/
3856	uint32_t iClear = pVM->pgm.s.cHandyPages;
3857	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3858	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3859	int rcAlloc = VINF_SUCCESS;
3860	int rcSeed = VINF_SUCCESS;
3861	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3862	while (rc == VERR_GMM_SEED_ME)
3863	{
3864	void *pvChunk;
3865	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3866	if (RT_SUCCESS(rc))
3867	{
3868	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3869	if (RT_FAILURE(rc))
3870	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3871	}
3872	if (RT_SUCCESS(rc))
3873	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3874	}
3875
3876	/* todo: we should split this up into an allocate and flush operation. sometimes you want to flush and not allocate more (which will trigger the vm account limit error) */
3877	if ( rc == VERR_GMM_HIT_VM_ACCOUNT_LIMIT
3878	&& pVM->pgm.s.cHandyPages > 0)
3879	{
3880	/* Still handy pages left, so don't panic. */
3881	rc = VINF_SUCCESS;
3882	}
3883
3884	if (RT_SUCCESS(rc))
3885	{
3886	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3887	Assert(pVM->pgm.s.cHandyPages > 0);
3888	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3889	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3890
3891	/*
3892	* Clear the pages.
3893	*/
3894	while (iClear < pVM->pgm.s.cHandyPages)
3895	{
3896	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3897	void *pv;
3898	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3899	AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n", pPage->idPage, pPage->HCPhysGCPhys, rc));
3900	ASMMemZeroPage(pv);
3901	iClear++;
3902	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3903	}
3904	}
3905	else
3906	{
3907	uint64_t cAllocPages, cMaxPages, cBalloonPages;
3908
3909	/*
3910	* We should never get here unless there is a genuine shortage of
3911	* memory (or some internal error). Flag the error so the VM can be
3912	* suspended ASAP and the user informed. If we're totally out of
3913	* handy pages we will return failure.
3914	*/
3915	/* Report the failure. */
3916	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3917	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3918	rc, rcAlloc, rcSeed,
3919	pVM->pgm.s.cHandyPages,
3920	pVM->pgm.s.cAllPages,
3921	pVM->pgm.s.cPrivatePages,
3922	pVM->pgm.s.cSharedPages,
3923	pVM->pgm.s.cZeroPages));
3924
3925	if (GMMR3QueryMemoryStats(pVM, &cAllocPages, &cMaxPages, &cBalloonPages) == VINF_SUCCESS)
3926	{
3927	LogRel(("GMM: Statistics:\n"
3928	" Allocated pages: %RX64\n"
3929	" Maximum pages: %RX64\n"
3930	" Ballooned pages: %RX64\n", cAllocPages, cMaxPages, cBalloonPages));
3931	}
3932
3933	if ( rc != VERR_NO_MEMORY
3934	&& rc != VERR_LOCK_FAILED)
3935	{
3936	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3937	{
3938	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3939	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3940	pVM->pgm.s.aHandyPages[i].idSharedPage));
3941	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3942	if (idPage != NIL_GMM_PAGEID)
3943	{
3944	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3945	pRam;
3946	pRam = pRam->pNextR3)
3947	{
3948	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3949	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3950	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3951	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3952	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3953	}
3954	}
3955	}
3956	}
3957
3958	/* Set the FFs and adjust rc. */
3959	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3960	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3961	if ( rc == VERR_NO_MEMORY
3962	\|\| rc == VERR_LOCK_FAILED)
3963	rc = VINF_EM_NO_MEMORY;
3964	}
3965
3966	pgmUnlock(pVM);
3967	return rc;
3968	}
3969
3970
3971	/**
3972	* Frees the specified RAM page and replaces it with the ZERO page.
3973	*
3974	* This is used by ballooning, remapping MMIO2 and RAM reset.
3975	*
3976	* @param pVM Pointer to the shared VM structure.
3977	* @param pReq Pointer to the request.
3978	* @param pPage Pointer to the page structure.
3979	* @param GCPhys The guest physical address of the page, if applicable.
3980	*
3981	* @remarks The caller must own the PGM lock.
3982	*/
3983	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3984	{
3985	/*
3986	* Assert sanity.
3987	*/
3988	Assert(PGMIsLockOwner(pVM));
3989	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3990	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3991	{
3992	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3993	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3994	}
3995
3996	if ( PGM_PAGE_IS_ZERO(pPage)
3997	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3998	return VINF_SUCCESS;
3999
4000	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
4001	Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
4002	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
4003	\|\| idPage > GMM_PAGEID_LAST
4004	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
4005	{
4006	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
4007	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
4008	}
4009
4010	/* update page count stats. */
4011	if (PGM_PAGE_IS_SHARED(pPage))
4012	pVM->pgm.s.cSharedPages--;
4013	else
4014	pVM->pgm.s.cPrivatePages--;
4015	pVM->pgm.s.cZeroPages++;
4016
4017	/* Deal with write monitored pages. */
4018	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
4019	{
4020	PGM_PAGE_SET_WRITTEN_TO(pPage);
4021	pVM->pgm.s.cWrittenToPages++;
4022	}
4023
4024	/*
4025	* pPage = ZERO page.
4026	*/
4027	PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
4028	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
4029	PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
4030	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4031	PGM_PAGE_SET_PTE_INDEX(pPage, 0);
4032	PGM_PAGE_SET_TRACKING(pPage, 0);
4033
4034	/* Flush physical page map TLB entry. */
4035	PGMPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
4036
4037	/*
4038	* Make sure it's not in the handy page array.
4039	*/
4040	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
4041	{
4042	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
4043	{
4044	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
4045	break;
4046	}
4047	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
4048	{
4049	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
4050	break;
4051	}
4052	}
4053
4054	/*
4055	* Push it onto the page array.
4056	*/
4057	uint32_t iPage = *pcPendingPages;
4058	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
4059	*pcPendingPages += 1;
4060
4061	pReq->aPages[iPage].idPage = idPage;
4062
4063	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
4064	return VINF_SUCCESS;
4065
4066	/*
4067	* Flush the pages.
4068	*/
4069	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
4070	if (RT_SUCCESS(rc))
4071	{
4072	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4073	*pcPendingPages = 0;
4074	}
4075	return rc;
4076	}
4077
4078
4079	/**
4080	* Converts a GC physical address to a HC ring-3 pointer, with some
4081	* additional checks.
4082	*
4083	* @returns VBox status code.
4084	* @retval VINF_SUCCESS on success.
4085	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
4086	* access handler of some kind.
4087	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
4088	* accesses or is odd in any way.
4089	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
4090	*
4091	* @param pVM The VM handle.
4092	* @param GCPhys The GC physical address to convert.
4093	* @param fWritable Whether write access is required.
4094	* @param ppv Where to store the pointer corresponding to GCPhys on
4095	* success.
4096	*/
4097	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
4098	{
4099	pgmLock(pVM);
4100
4101	PPGMRAMRANGE pRam;
4102	PPGMPAGE pPage;
4103	int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
4104	if (RT_SUCCESS(rc))
4105	{
4106	if (PGM_PAGE_IS_BALLOONED(pPage))
4107	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
4108	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
4109	rc = VINF_SUCCESS;
4110	else
4111	{
4112	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
4113	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
4114	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
4115	{
4116	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
4117	* in -norawr0 mode. */
4118	if (fWritable)
4119	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
4120	}
4121	else
4122	{
4123	/* Temporarily disabled physical handler(s), since the recompiler
4124	doesn't get notified when it's reset we'll have to pretend it's
4125	operating normally. */
4126	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
4127	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
4128	else
4129	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
4130	}
4131	}
4132	if (RT_SUCCESS(rc))
4133	{
4134	int rc2;
4135
4136	/* Make sure what we return is writable. */
4137	if (fWritable)
4138	switch (PGM_PAGE_GET_STATE(pPage))
4139	{
4140	case PGM_PAGE_STATE_ALLOCATED:
4141	break;
4142	case PGM_PAGE_STATE_BALLOONED:
4143	AssertFailed();
4144	break;
4145	case PGM_PAGE_STATE_ZERO:
4146	case PGM_PAGE_STATE_SHARED:
4147	if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
4148	break;
4149	case PGM_PAGE_STATE_WRITE_MONITORED:
4150	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
4151	AssertLogRelRCReturn(rc2, rc2);
4152	break;
4153	}
4154
4155	/* Get a ring-3 mapping of the address. */
4156	PPGMPAGER3MAPTLBE pTlbe;
4157	rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
4158	AssertLogRelRCReturn(rc2, rc2);
4159	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
4160	/** @todo mapping/locking hell; this isn't horribly efficient since
4161	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
4162
4163	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
4164	}
4165	else
4166	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
4167
4168	/* else: handler catching all access, no pointer returned. */
4169	}
4170	else
4171	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
4172
4173	pgmUnlock(pVM);
4174	return rc;
4175	}
4176

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source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 31938

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