PGMPhys.cpp@ 32963

Last change on this file since 32963 was 32307, checked in by vboxsync, 14 years ago
Include other range types too (FTM)
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1	/* $Id: PGMPhys.cpp 32307 2010-09-08 11:34:31Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_PHYS
23	#include <VBox/pgm.h>
24	#include <VBox/iom.h>
25	#include <VBox/mm.h>
26	#include <VBox/stam.h>
27	#include <VBox/rem.h>
28	#include <VBox/pdmdev.h>
29	#include "PGMInternal.h"
30	#include <VBox/vm.h>
31	#include "PGMInline.h"
32	#include <VBox/sup.h>
33	#include <VBox/param.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <iprt/assert.h>
37	#include <iprt/alloc.h>
38	#include <iprt/asm.h>
39	#include <iprt/thread.h>
40	#include <iprt/string.h>
41
42
43	/*******************************************************************************
44	* Defined Constants And Macros *
45	*******************************************************************************/
46	/** The number of pages to free in one batch. */
47	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
48
49
50	/*******************************************************************************
51	* Internal Functions *
52	*******************************************************************************/
53	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
54
55
56	/*
57	* PGMR3PhysReadU8-64
58	* PGMR3PhysWriteU8-64
59	*/
60	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
61	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
62	#define PGMPHYS_DATASIZE 1
63	#define PGMPHYS_DATATYPE uint8_t
64	#include "PGMPhysRWTmpl.h"
65
66	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
67	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
68	#define PGMPHYS_DATASIZE 2
69	#define PGMPHYS_DATATYPE uint16_t
70	#include "PGMPhysRWTmpl.h"
71
72	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
73	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
74	#define PGMPHYS_DATASIZE 4
75	#define PGMPHYS_DATATYPE uint32_t
76	#include "PGMPhysRWTmpl.h"
77
78	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
79	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
80	#define PGMPHYS_DATASIZE 8
81	#define PGMPHYS_DATATYPE uint64_t
82	#include "PGMPhysRWTmpl.h"
83
84
85	/**
86	* EMT worker for PGMR3PhysReadExternal.
87	*/
88	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
89	{
90	PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
91	return VINF_SUCCESS;
92	}
93
94
95	/**
96	* Read from physical memory, external users.
97	*
98	* @returns VBox status code.
99	* @retval VINF_SUCCESS.
100	*
101	* @param pVM VM Handle.
102	* @param GCPhys Physical address to read from.
103	* @param pvBuf Where to read into.
104	* @param cbRead How many bytes to read.
105	*
106	* @thread Any but EMTs.
107	*/
108	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
109	{
110	VM_ASSERT_OTHER_THREAD(pVM);
111
112	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
113	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
114
115	pgmLock(pVM);
116
117	/*
118	* Copy loop on ram ranges.
119	*/
120	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
121	for (;;)
122	{
123	/* Find range. */
124	while (pRam && GCPhys > pRam->GCPhysLast)
125	pRam = pRam->CTX_SUFF(pNext);
126	/* Inside range or not? */
127	if (pRam && GCPhys >= pRam->GCPhys)
128	{
129	/*
130	* Must work our way thru this page by page.
131	*/
132	RTGCPHYS off = GCPhys - pRam->GCPhys;
133	while (off < pRam->cb)
134	{
135	unsigned iPage = off >> PAGE_SHIFT;
136	PPGMPAGE pPage = &pRam->aPages[iPage];
137
138	/*
139	* If the page has an ALL access handler, we'll have to
140	* delegate the job to EMT.
141	*/
142	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
143	{
144	pgmUnlock(pVM);
145
146	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 4,
147	pVM, &GCPhys, pvBuf, cbRead);
148	}
149	Assert(!PGM_PAGE_IS_MMIO(pPage));
150
151	/*
152	* Simple stuff, go ahead.
153	*/
154	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
155	if (cb > cbRead)
156	cb = cbRead;
157	const void *pvSrc;
158	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
159	if (RT_SUCCESS(rc))
160	memcpy(pvBuf, pvSrc, cb);
161	else
162	{
163	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
164	pRam->GCPhys + off, pPage, rc));
165	memset(pvBuf, 0xff, cb);
166	}
167
168	/* next page */
169	if (cb >= cbRead)
170	{
171	pgmUnlock(pVM);
172	return VINF_SUCCESS;
173	}
174	cbRead -= cb;
175	off += cb;
176	GCPhys += cb;
177	pvBuf = (char *)pvBuf + cb;
178	} /* walk pages in ram range. */
179	}
180	else
181	{
182	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
183
184	/*
185	* Unassigned address space.
186	*/
187	if (!pRam)
188	break;
189	size_t cb = pRam->GCPhys - GCPhys;
190	if (cb >= cbRead)
191	{
192	memset(pvBuf, 0xff, cbRead);
193	break;
194	}
195	memset(pvBuf, 0xff, cb);
196
197	cbRead -= cb;
198	pvBuf = (char *)pvBuf + cb;
199	GCPhys += cb;
200	}
201	} /* Ram range walk */
202
203	pgmUnlock(pVM);
204
205	return VINF_SUCCESS;
206	}
207
208
209	/**
210	* EMT worker for PGMR3PhysWriteExternal.
211	*/
212	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
213	{
214	/** @todo VERR_EM_NO_MEMORY */
215	PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
216	return VINF_SUCCESS;
217	}
218
219
220	/**
221	* Write to physical memory, external users.
222	*
223	* @returns VBox status code.
224	* @retval VINF_SUCCESS.
225	* @retval VERR_EM_NO_MEMORY.
226	*
227	* @param pVM VM Handle.
228	* @param GCPhys Physical address to write to.
229	* @param pvBuf What to write.
230	* @param cbWrite How many bytes to write.
231	* @param pszWho Who is writing. For tracking down who is writing
232	* after we've saved the state.
233	*
234	* @thread Any but EMTs.
235	*/
236	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void pvBuf, size_t cbWrite, const char pszWho)
237	{
238	VM_ASSERT_OTHER_THREAD(pVM);
239
240	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
241	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x pszWho=%s\n",
242	GCPhys, cbWrite, pszWho));
243	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
244	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
245
246	pgmLock(pVM);
247
248	/*
249	* Copy loop on ram ranges, stop when we hit something difficult.
250	*/
251	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
252	for (;;)
253	{
254	/* Find range. */
255	while (pRam && GCPhys > pRam->GCPhysLast)
256	pRam = pRam->CTX_SUFF(pNext);
257	/* Inside range or not? */
258	if (pRam && GCPhys >= pRam->GCPhys)
259	{
260	/*
261	* Must work our way thru this page by page.
262	*/
263	RTGCPTR off = GCPhys - pRam->GCPhys;
264	while (off < pRam->cb)
265	{
266	RTGCPTR iPage = off >> PAGE_SHIFT;
267	PPGMPAGE pPage = &pRam->aPages[iPage];
268
269	/*
270	* Is the page problematic, we have to do the work on the EMT.
271	*
272	* Allocating writable pages and access handlers are
273	* problematic, write monitored pages are simple and can be
274	* dealt with here.
275	*/
276	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
277	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
278	{
279	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
280	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
281	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
282	else
283	{
284	pgmUnlock(pVM);
285
286	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 4,
287	pVM, &GCPhys, pvBuf, cbWrite);
288	}
289	}
290	Assert(!PGM_PAGE_IS_MMIO(pPage));
291
292	/*
293	* Simple stuff, go ahead.
294	*/
295	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
296	if (cb > cbWrite)
297	cb = cbWrite;
298	void *pvDst;
299	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
300	if (RT_SUCCESS(rc))
301	memcpy(pvDst, pvBuf, cb);
302	else
303	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
304	pRam->GCPhys + off, pPage, rc));
305
306	/* next page */
307	if (cb >= cbWrite)
308	{
309	pgmUnlock(pVM);
310	return VINF_SUCCESS;
311	}
312
313	cbWrite -= cb;
314	off += cb;
315	GCPhys += cb;
316	pvBuf = (const char *)pvBuf + cb;
317	} /* walk pages in ram range */
318	}
319	else
320	{
321	/*
322	* Unassigned address space, skip it.
323	*/
324	if (!pRam)
325	break;
326	size_t cb = pRam->GCPhys - GCPhys;
327	if (cb >= cbWrite)
328	break;
329	cbWrite -= cb;
330	pvBuf = (const char *)pvBuf + cb;
331	GCPhys += cb;
332	}
333	} /* Ram range walk */
334
335	pgmUnlock(pVM);
336	return VINF_SUCCESS;
337	}
338
339
340	/**
341	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
342	*
343	* @returns see PGMR3PhysGCPhys2CCPtrExternal
344	* @param pVM The VM handle.
345	* @param pGCPhys Pointer to the guest physical address.
346	* @param ppv Where to store the mapping address.
347	* @param pLock Where to store the lock.
348	*/
349	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
350	{
351	/*
352	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
353	* an access handler after it succeeds.
354	*/
355	int rc = pgmLock(pVM);
356	AssertRCReturn(rc, rc);
357
358	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
359	if (RT_SUCCESS(rc))
360	{
361	PPGMPAGEMAPTLBE pTlbe;
362	int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
363	AssertFatalRC(rc2);
364	PPGMPAGE pPage = pTlbe->pPage;
365	if (PGM_PAGE_IS_MMIO(pPage))
366	{
367	PGMPhysReleasePageMappingLock(pVM, pLock);
368	rc = VERR_PGM_PHYS_PAGE_RESERVED;
369	}
370	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
371	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
372	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
373	#endif
374	)
375	{
376	/* We must flush any corresponding pgm pool page here, otherwise we'll
377	* not be informed about writes and keep bogus gst->shw mappings around.
378	*/
379	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
380	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
381	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
382	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
383	}
384	}
385
386	pgmUnlock(pVM);
387	return rc;
388	}
389
390
391	/**
392	* Requests the mapping of a guest page into ring-3, external threads.
393	*
394	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
395	* release it.
396	*
397	* This API will assume your intention is to write to the page, and will
398	* therefore replace shared and zero pages. If you do not intend to modify the
399	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
400	*
401	* @returns VBox status code.
402	* @retval VINF_SUCCESS on success.
403	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
404	* backing or if the page has any active access handlers. The caller
405	* must fall back on using PGMR3PhysWriteExternal.
406	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
407	*
408	* @param pVM The VM handle.
409	* @param GCPhys The guest physical address of the page that should be mapped.
410	* @param ppv Where to store the address corresponding to GCPhys.
411	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
412	*
413	* @remark Avoid calling this API from within critical sections (other than the
414	* PGM one) because of the deadlock risk when we have to delegating the
415	* task to an EMT.
416	* @thread Any.
417	*/
418	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
419	{
420	AssertPtr(ppv);
421	AssertPtr(pLock);
422
423	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
424
425	int rc = pgmLock(pVM);
426	AssertRCReturn(rc, rc);
427
428	/*
429	* Query the Physical TLB entry for the page (may fail).
430	*/
431	PPGMPAGEMAPTLBE pTlbe;
432	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
433	if (RT_SUCCESS(rc))
434	{
435	PPGMPAGE pPage = pTlbe->pPage;
436	if (PGM_PAGE_IS_MMIO(pPage))
437	rc = VERR_PGM_PHYS_PAGE_RESERVED;
438	else
439	{
440	/*
441	* If the page is shared, the zero page, or being write monitored
442	* it must be converted to an page that's writable if possible.
443	* We can only deal with write monitored pages here, the rest have
444	* to be on an EMT.
445	*/
446	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
447	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
448	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
449	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
450	#endif
451	)
452	{
453	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
454	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
455	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
456	&& !pgmPoolIsDirtyPage(pVM, GCPhys)
457	#endif
458	)
459	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
460	else
461	{
462	pgmUnlock(pVM);
463
464	return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
465	pVM, &GCPhys, ppv, pLock);
466	}
467	}
468
469	/*
470	* Now, just perform the locking and calculate the return address.
471	*/
472	PPGMPAGEMAP pMap = pTlbe->pMap;
473	if (pMap)
474	pMap->cRefs++;
475
476	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
477	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
478	{
479	if (cLocks == 0)
480	pVM->pgm.s.cWriteLockedPages++;
481	PGM_PAGE_INC_WRITE_LOCKS(pPage);
482	}
483	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
484	{
485	PGM_PAGE_INC_WRITE_LOCKS(pPage);
486	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
487	if (pMap)
488	pMap->cRefs++; /* Extra ref to prevent it from going away. */
489	}
490
491	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
492	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
493	pLock->pvMap = pMap;
494	}
495	}
496
497	pgmUnlock(pVM);
498	return rc;
499	}
500
501
502	/**
503	* Requests the mapping of a guest page into ring-3, external threads.
504	*
505	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
506	* release it.
507	*
508	* @returns VBox status code.
509	* @retval VINF_SUCCESS on success.
510	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
511	* backing or if the page as an active ALL access handler. The caller
512	* must fall back on using PGMPhysRead.
513	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
514	*
515	* @param pVM The VM handle.
516	* @param GCPhys The guest physical address of the page that should be mapped.
517	* @param ppv Where to store the address corresponding to GCPhys.
518	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
519	*
520	* @remark Avoid calling this API from within critical sections (other than
521	* the PGM one) because of the deadlock risk.
522	* @thread Any.
523	*/
524	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
525	{
526	int rc = pgmLock(pVM);
527	AssertRCReturn(rc, rc);
528
529	/*
530	* Query the Physical TLB entry for the page (may fail).
531	*/
532	PPGMPAGEMAPTLBE pTlbe;
533	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
534	if (RT_SUCCESS(rc))
535	{
536	PPGMPAGE pPage = pTlbe->pPage;
537	#if 1
538	/* MMIO pages doesn't have any readable backing. */
539	if (PGM_PAGE_IS_MMIO(pPage))
540	rc = VERR_PGM_PHYS_PAGE_RESERVED;
541	#else
542	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
543	rc = VERR_PGM_PHYS_PAGE_RESERVED;
544	#endif
545	else
546	{
547	/*
548	* Now, just perform the locking and calculate the return address.
549	*/
550	PPGMPAGEMAP pMap = pTlbe->pMap;
551	if (pMap)
552	pMap->cRefs++;
553
554	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
555	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
556	{
557	if (cLocks == 0)
558	pVM->pgm.s.cReadLockedPages++;
559	PGM_PAGE_INC_READ_LOCKS(pPage);
560	}
561	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
562	{
563	PGM_PAGE_INC_READ_LOCKS(pPage);
564	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
565	if (pMap)
566	pMap->cRefs++; /* Extra ref to prevent it from going away. */
567	}
568
569	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
570	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
571	pLock->pvMap = pMap;
572	}
573	}
574
575	pgmUnlock(pVM);
576	return rc;
577	}
578
579
580	/**
581	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
582	*
583	* Called when anything was relocated.
584	*
585	* @param pVM Pointer to the shared VM structure.
586	*/
587	void pgmR3PhysRelinkRamRanges(PVM pVM)
588	{
589	PPGMRAMRANGE pCur;
590
591	#ifdef VBOX_STRICT
592	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
593	{
594	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
595	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
596	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
597	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
598	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
599	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
600	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
601	Assert( pCur2 == pCur
602	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
603	}
604	#endif
605
606	pCur = pVM->pgm.s.pRamRangesR3;
607	if (pCur)
608	{
609	pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
610	pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
611
612	for (; pCur->pNextR3; pCur = pCur->pNextR3)
613	{
614	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
615	pCur->pNextRC = pCur->pNextR3->pSelfRC;
616	}
617
618	Assert(pCur->pNextR0 == NIL_RTR0PTR);
619	Assert(pCur->pNextRC == NIL_RTRCPTR);
620	}
621	else
622	{
623	Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
624	Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
625	}
626	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
627	}
628
629
630	/**
631	* Links a new RAM range into the list.
632	*
633	* @param pVM Pointer to the shared VM structure.
634	* @param pNew Pointer to the new list entry.
635	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
636	*/
637	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
638	{
639	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
640	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
641	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
642
643	pgmLock(pVM);
644
645	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
646	pNew->pNextR3 = pRam;
647	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
648	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
649
650	if (pPrev)
651	{
652	pPrev->pNextR3 = pNew;
653	pPrev->pNextR0 = pNew->pSelfR0;
654	pPrev->pNextRC = pNew->pSelfRC;
655	}
656	else
657	{
658	pVM->pgm.s.pRamRangesR3 = pNew;
659	pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
660	pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
661	}
662	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
663	pgmUnlock(pVM);
664	}
665
666
667	/**
668	* Unlink an existing RAM range from the list.
669	*
670	* @param pVM Pointer to the shared VM structure.
671	* @param pRam Pointer to the new list entry.
672	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
673	*/
674	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
675	{
676	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
677	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
678	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
679
680	pgmLock(pVM);
681
682	PPGMRAMRANGE pNext = pRam->pNextR3;
683	if (pPrev)
684	{
685	pPrev->pNextR3 = pNext;
686	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
687	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
688	}
689	else
690	{
691	Assert(pVM->pgm.s.pRamRangesR3 == pRam);
692	pVM->pgm.s.pRamRangesR3 = pNext;
693	pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
694	pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
695	}
696	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
697	pgmUnlock(pVM);
698	}
699
700
701	/**
702	* Unlink an existing RAM range from the list.
703	*
704	* @param pVM Pointer to the shared VM structure.
705	* @param pRam Pointer to the new list entry.
706	*/
707	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
708	{
709	pgmLock(pVM);
710
711	/* find prev. */
712	PPGMRAMRANGE pPrev = NULL;
713	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
714	while (pCur != pRam)
715	{
716	pPrev = pCur;
717	pCur = pCur->pNextR3;
718	}
719	AssertFatal(pCur);
720
721	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
722	pgmUnlock(pVM);
723	}
724
725
726	/**
727	* Frees a range of pages, replacing them with ZERO pages of the specified type.
728	*
729	* @returns VBox status code.
730	* @param pVM The VM handle.
731	* @param pRam The RAM range in which the pages resides.
732	* @param GCPhys The address of the first page.
733	* @param GCPhysLast The address of the last page.
734	* @param uType The page type to replace then with.
735	*/
736	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
737	{
738	Assert(PGMIsLockOwner(pVM));
739	uint32_t cPendingPages = 0;
740	PGMMFREEPAGESREQ pReq;
741	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
742	AssertLogRelRCReturn(rc, rc);
743
744	/* Iterate the pages. */
745	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
746	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
747	while (cPagesLeft-- > 0)
748	{
749	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
750	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
751
752	PGM_PAGE_SET_TYPE(pPageDst, uType);
753
754	GCPhys += PAGE_SIZE;
755	pPageDst++;
756	}
757
758	if (cPendingPages)
759	{
760	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
761	AssertLogRelRCReturn(rc, rc);
762	}
763	GMMR3FreePagesCleanup(pReq);
764
765	return rc;
766	}
767
768	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
769	/**
770	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
771	*
772	* This is only called on one of the EMTs while the other ones are waiting for
773	* it to complete this function.
774	*
775	* @returns VINF_SUCCESS (VBox strict status code).
776	* @param pVM The VM handle.
777	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
778	* @param pvUser User parameter
779	*/
780	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
781	{
782	uintptr_t paUser = (uintptr_t )pvUser;
783	bool fInflate = !!paUser[0];
784	unsigned cPages = paUser[1];
785	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
786	uint32_t cPendingPages = 0;
787	PGMMFREEPAGESREQ pReq;
788	int rc;
789
790	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
791	pgmLock(pVM);
792
793	if (fInflate)
794	{
795	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
796	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
797
798	/* Replace pages with ZERO pages. */
799	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
800	if (RT_FAILURE(rc))
801	{
802	pgmUnlock(pVM);
803	AssertLogRelRC(rc);
804	return rc;
805	}
806
807	/* Iterate the pages. */
808	for (unsigned i = 0; i < cPages; i++)
809	{
810	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
811	if ( pPage == NULL
812	\|\| pPage->uTypeY != PGMPAGETYPE_RAM)
813	{
814	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], (pPage) ? pPage->uTypeY : 0));
815	break;
816	}
817
818	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
819
820	/* Flush the shadow PT if this page was previously used as a guest page table. */
821	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
822
823	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i]);
824	if (RT_FAILURE(rc))
825	{
826	pgmUnlock(pVM);
827	AssertLogRelRC(rc);
828	return rc;
829	}
830	Assert(PGM_PAGE_IS_ZERO(pPage));
831	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_BALLOONED);
832	}
833
834	if (cPendingPages)
835	{
836	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
837	if (RT_FAILURE(rc))
838	{
839	pgmUnlock(pVM);
840	AssertLogRelRC(rc);
841	return rc;
842	}
843	}
844	GMMR3FreePagesCleanup(pReq);
845	}
846	else
847	{
848	/* Iterate the pages. */
849	for (unsigned i = 0; i < cPages; i++)
850	{
851	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, paPhysPage[i]);
852	AssertBreak(pPage && pPage->uTypeY == PGMPAGETYPE_RAM);
853
854	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
855
856	Assert(PGM_PAGE_IS_BALLOONED(pPage));
857
858	/* Change back to zero page. */
859	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
860	}
861
862	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
863	}
864
865	/* Notify GMM about the balloon change. */
866	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
867	if (RT_SUCCESS(rc))
868	{
869	if (!fInflate)
870	{
871	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
872	pVM->pgm.s.cBalloonedPages -= cPages;
873	}
874	else
875	pVM->pgm.s.cBalloonedPages += cPages;
876	}
877
878	pgmUnlock(pVM);
879
880	/* Flush the recompiler's TLB as well. */
881	for (VMCPUID i = 0; i < pVM->cCpus; i++)
882	CPUMSetChangedFlags(&pVM->aCpus[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
883
884	AssertLogRelRC(rc);
885	return rc;
886	}
887
888	/**
889	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
890	*
891	* @returns VBox status code.
892	* @param pVM The VM handle.
893	* @param fInflate Inflate or deflate memory balloon
894	* @param cPages Number of pages to free
895	* @param paPhysPage Array of guest physical addresses
896	*/
897	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
898	{
899	uintptr_t paUser[3];
900
901	paUser[0] = fInflate;
902	paUser[1] = cPages;
903	paUser[2] = (uintptr_t)paPhysPage;
904	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
905	AssertRC(rc);
906
907	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
908	RTMemFree(paPhysPage);
909	}
910	#endif
911
912	/**
913	* Inflate or deflate a memory balloon
914	*
915	* @returns VBox status code.
916	* @param pVM The VM handle.
917	* @param fInflate Inflate or deflate memory balloon
918	* @param cPages Number of pages to free
919	* @param paPhysPage Array of guest physical addresses
920	*/
921	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
922	{
923	/* This must match GMMR0Init; currently we only support memory ballooning on all 64-bit hosts except Mac OS X */
924	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
925	int rc;
926
927	/* Older additions (ancient non-functioning balloon code) pass wrong physical addresses. */
928	AssertReturn(!(paPhysPage[0] & 0xfff), VERR_INVALID_PARAMETER);
929
930	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
931	* In the SMP case we post a request packet to postpone the job.
932	*/
933	if (pVM->cCpus > 1)
934	{
935	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
936	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
937	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
938
939	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
940
941	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
942	AssertRC(rc);
943	}
944	else
945	{
946	uintptr_t paUser[3];
947
948	paUser[0] = fInflate;
949	paUser[1] = cPages;
950	paUser[2] = (uintptr_t)paPhysPage;
951	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
952	AssertRC(rc);
953	}
954	return rc;
955	#else
956	return VERR_NOT_IMPLEMENTED;
957	#endif
958	}
959
960	/**
961	* Rendezvous callback used by PGMR3WriteProtectRAM that write protects all physical RAM
962	*
963	* This is only called on one of the EMTs while the other ones are waiting for
964	* it to complete this function.
965	*
966	* @returns VINF_SUCCESS (VBox strict status code).
967	* @param pVM The VM handle.
968	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
969	* @param pvUser User parameter
970	*/
971	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
972	{
973	int rc = VINF_SUCCESS;
974
975	pgmLock(pVM);
976	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
977	pgmPoolResetDirtyPages(pVM);
978	#endif
979
980	/** @todo pointless to write protect the physical page pointed to by RSP. */
981
982	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
983	pRam;
984	pRam = pRam->CTX_SUFF(pNext))
985	{
986	unsigned cPages = pRam->cb >> PAGE_SHIFT;
987	for (unsigned iPage = 0; iPage < cPages; iPage++)
988	{
989	PPGMPAGE pPage = &pRam->aPages[iPage];
990	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
991
992	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
993	\|\| enmPageType == PGMPAGETYPE_MMIO2)
994	{
995	/*
996	* A RAM page.
997	*/
998	switch (PGM_PAGE_GET_STATE(pPage))
999	{
1000	case PGM_PAGE_STATE_ALLOCATED:
1001	/** @todo Optimize this: Don't always re-enable write
1002	* monitoring if the page is known to be very busy. */
1003	if (PGM_PAGE_IS_WRITTEN_TO(pPage))
1004	{
1005	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1006	/* Remember this dirty page for the next (memory) sync. */
1007	PGM_PAGE_SET_FT_DIRTY(pPage);
1008	}
1009
1010	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_WRITE_MONITORED);
1011	pVM->pgm.s.cMonitoredPages++;
1012	break;
1013
1014	case PGM_PAGE_STATE_SHARED:
1015	AssertFailed();
1016	break;
1017
1018	case PGM_PAGE_STATE_WRITE_MONITORED: /* nothing to change. */
1019	default:
1020	break;
1021	}
1022	}
1023	}
1024	}
1025	pgmR3PoolWriteProtectPages(pVM);
1026	PGM_INVL_ALL_VCPU_TLBS(pVM);
1027	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1028	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1029
1030	pgmUnlock(pVM);
1031	return rc;
1032	}
1033
1034	/**
1035	* Protect all physical RAM to monitor writes
1036	*
1037	* @returns VBox status code.
1038	* @param pVM The VM handle.
1039	*/
1040	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM)
1041	{
1042	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1043
1044	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysWriteProtectRAMRendezvous, NULL);
1045	AssertRC(rc);
1046	return rc;
1047	}
1048
1049	/**
1050	* Enumerate all dirty FT pages
1051	*
1052	* @returns VBox status code.
1053	* @param pVM The VM handle.
1054	* @param pfnEnum Enumerate callback handler
1055	* @param pvUser Enumerate callback handler parameter
1056	*/
1057	VMMR3DECL(int) PGMR3PhysEnumDirtyFTPages(PVM pVM, PFNPGMENUMDIRTYFTPAGES pfnEnum, void *pvUser)
1058	{
1059	int rc = VINF_SUCCESS;
1060
1061	pgmLock(pVM);
1062	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1063	pRam;
1064	pRam = pRam->CTX_SUFF(pNext))
1065	{
1066	unsigned cPages = pRam->cb >> PAGE_SHIFT;
1067	for (unsigned iPage = 0; iPage < cPages; iPage++)
1068	{
1069	PPGMPAGE pPage = &pRam->aPages[iPage];
1070	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
1071
1072	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
1073	\|\| enmPageType == PGMPAGETYPE_MMIO2)
1074	{
1075	/*
1076	* A RAM page.
1077	*/
1078	switch (PGM_PAGE_GET_STATE(pPage))
1079	{
1080	case PGM_PAGE_STATE_ALLOCATED:
1081	case PGM_PAGE_STATE_WRITE_MONITORED:
1082	if ( !PGM_PAGE_IS_WRITTEN_TO(pPage) /* not very recently updated? */
1083	&& PGM_PAGE_IS_FT_DIRTY(pPage))
1084	{
1085	unsigned cbPageRange = PAGE_SIZE;
1086	unsigned iPageClean = iPage + 1;
1087	RTGCPHYS GCPhysPage = pRam->GCPhys + iPage * PAGE_SIZE;
1088	uint8_t *pu8Page = NULL;
1089	PGMPAGEMAPLOCK Lock;
1090
1091	/* Find the next clean page, so we can merge adjacent dirty pages. */
1092	for (; iPageClean < cPages; iPageClean++)
1093	{
1094	PPGMPAGE pPageNext = &pRam->aPages[iPageClean];
1095	if ( RT_UNLIKELY(PGM_PAGE_GET_TYPE(pPageNext) != PGMPAGETYPE_RAM)
1096	\|\| PGM_PAGE_GET_STATE(pPageNext) != PGM_PAGE_STATE_ALLOCATED
1097	\|\| PGM_PAGE_IS_WRITTEN_TO(pPageNext)
1098	\|\| !PGM_PAGE_IS_FT_DIRTY(pPageNext)
1099	/* Crossing a chunk boundary? */
1100	\|\| (GCPhysPage & GMM_PAGEID_IDX_MASK) != ((GCPhysPage + cbPageRange) & GMM_PAGEID_IDX_MASK)
1101	)
1102	break;
1103
1104	cbPageRange += PAGE_SIZE;
1105	}
1106
1107	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhysPage, (const void **)&pu8Page, &Lock);
1108	if (RT_SUCCESS(rc))
1109	{
1110	/** @todo this is risky; the range might be changed, but little choice as the sync costs a lot of time */
1111	pgmUnlock(pVM);
1112	pfnEnum(pVM, GCPhysPage, pu8Page, cbPageRange, pvUser);
1113	pgmLock(pVM);
1114	PGMPhysReleasePageMappingLock(pVM, &Lock);
1115	}
1116
1117	for (iPage; iPage < iPageClean; iPage++)
1118	PGM_PAGE_CLEAR_FT_DIRTY(&pRam->aPages[iPage]);
1119
1120	iPage = iPageClean - 1;
1121	}
1122	break;
1123	}
1124	}
1125	}
1126	}
1127	pgmUnlock(pVM);
1128	return rc;
1129	}
1130
1131
1132	/**
1133	* Gets the number of ram ranges.
1134	*
1135	* @returns Number of ram ranges. Returns UINT32_MAX if @a pVM is invalid.
1136	* @param pVM The VM handle.
1137	*/
1138	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM)
1139	{
1140	VM_ASSERT_VALID_EXT_RETURN(pVM, UINT32_MAX);
1141
1142	pgmLock(pVM);
1143	uint32_t cRamRanges = 0;
1144	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRanges); pCur; pCur = pCur->CTX_SUFF(pNext))
1145	cRamRanges++;
1146	pgmUnlock(pVM);
1147	return cRamRanges;
1148	}
1149
1150
1151	/**
1152	* Get information about a range.
1153	*
1154	* @returns VINF_SUCCESS or VERR_OUT_OF_RANGE.
1155	* @param pVM The VM handle
1156	* @param iRange The ordinal of the range.
1157	* @param pGCPhysStart Where to return the start of the range. Optional.
1158	* @param pGCPhysLast Where to return the address of the last byte in the
1159	* range. Optional.
1160	* @param pfIsMmio Where to indicate that this is a pure MMIO range.
1161	* Optional.
1162	*/
1163	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1164	const char *ppszDesc, bool pfIsMmio)
1165	{
1166	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1167
1168	pgmLock(pVM);
1169	uint32_t iCurRange = 0;
1170	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRanges); pCur; pCur = pCur->CTX_SUFF(pNext), iCurRange++)
1171	if (iCurRange == iRange)
1172	{
1173	if (pGCPhysStart)
1174	*pGCPhysStart = pCur->GCPhys;
1175	if (pGCPhysLast)
1176	*pGCPhysLast = pCur->GCPhysLast;
1177	if (pfIsMmio)
1178	*pfIsMmio = !!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO);
1179
1180	pgmUnlock(pVM);
1181	return VINF_SUCCESS;
1182	}
1183	pgmUnlock(pVM);
1184	return VERR_OUT_OF_RANGE;
1185	}
1186
1187
1188	/**
1189	* Query the amount of free memory inside VMMR0
1190	*
1191	* @returns VBox status code.
1192	* @param pVM The VM handle.
1193	* @param puTotalAllocSize Pointer to total allocated memory inside VMMR0 (in bytes)
1194	* @param puTotalFreeSize Pointer to total free (allocated but not used yet) memory inside VMMR0 (in bytes)
1195	* @param puTotalBalloonSize Pointer to total ballooned memory inside VMMR0 (in bytes)
1196	* @param puTotalSharedSize Pointer to total shared memory inside VMMR0 (in bytes)
1197	*/
1198	VMMR3DECL(int) PGMR3QueryVMMMemoryStats(PVM pVM, uint64_t puTotalAllocSize, uint64_t puTotalFreeSize, uint64_t puTotalBalloonSize, uint64_t puTotalSharedSize)
1199	{
1200	int rc;
1201
1202	uint64_t cAllocPages = 0, cFreePages = 0, cBalloonPages = 0, cSharedPages = 0;
1203	rc = GMMR3QueryHypervisorMemoryStats(pVM, &cAllocPages, &cFreePages, &cBalloonPages, &cSharedPages);
1204	AssertRCReturn(rc, rc);
1205
1206	if (puTotalAllocSize)
1207	puTotalAllocSize = cAllocPages _4K;
1208
1209	if (puTotalFreeSize)
1210	puTotalFreeSize = cFreePages _4K;
1211
1212	if (puTotalBalloonSize)
1213	puTotalBalloonSize = cBalloonPages _4K;
1214
1215	if (puTotalSharedSize)
1216	puTotalSharedSize = cSharedPages _4K;
1217
1218	Log(("PGMR3QueryVMMMemoryStats: all=%x free=%x ballooned=%x shared=%x\n", cAllocPages, cFreePages, cBalloonPages, cSharedPages));
1219	return VINF_SUCCESS;
1220	}
1221
1222	/**
1223	* Query memory stats for the VM
1224	*
1225	* @returns VBox status code.
1226	* @param pVM The VM handle.
1227	* @param puTotalAllocSize Pointer to total allocated memory inside the VM (in bytes)
1228	* @param puTotalFreeSize Pointer to total free (allocated but not used yet) memory inside the VM (in bytes)
1229	* @param puTotalBalloonSize Pointer to total ballooned memory inside the VM (in bytes)
1230	* @param puTotalSharedSize Pointer to total shared memory inside the VM (in bytes)
1231	*/
1232	VMMR3DECL(int) PGMR3QueryMemoryStats(PVM pVM, uint64_t pulTotalMem, uint64_t pulPrivateMem, uint64_t puTotalSharedMem, uint64_t puTotalZeroMem)
1233	{
1234	if (pulTotalMem)
1235	pulTotalMem = (uint64_t)pVM->pgm.s.cAllPages _4K;
1236
1237	if (pulPrivateMem)
1238	pulPrivateMem = (uint64_t)pVM->pgm.s.cPrivatePages _4K;
1239
1240	if (puTotalSharedMem)
1241	puTotalSharedMem = (uint64_t)pVM->pgm.s.cReusedSharedPages _4K;
1242
1243	if (puTotalZeroMem)
1244	puTotalZeroMem = (uint64_t)pVM->pgm.s.cZeroPages _4K;
1245
1246	Log(("PGMR3QueryMemoryStats: all=%x private=%x reused=%x zero=%x\n", pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cReusedSharedPages, pVM->pgm.s.cZeroPages));
1247	return VINF_SUCCESS;
1248	}
1249
1250	/**
1251	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
1252	*
1253	* @param pVM The VM handle.
1254	* @param pNew The new RAM range.
1255	* @param GCPhys The address of the RAM range.
1256	* @param GCPhysLast The last address of the RAM range.
1257	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
1258	* if in HMA.
1259	* @param R0PtrNew Ditto for R0.
1260	* @param pszDesc The description.
1261	* @param pPrev The previous RAM range (for linking).
1262	*/
1263	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
1264	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
1265	{
1266	/*
1267	* Initialize the range.
1268	*/
1269	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
1270	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
1271	pNew->GCPhys = GCPhys;
1272	pNew->GCPhysLast = GCPhysLast;
1273	pNew->cb = GCPhysLast - GCPhys + 1;
1274	pNew->pszDesc = pszDesc;
1275	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
1276	pNew->pvR3 = NULL;
1277	pNew->paLSPages = NULL;
1278
1279	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1280	RTGCPHYS iPage = cPages;
1281	while (iPage-- > 0)
1282	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1283
1284	/* Update the page count stats. */
1285	pVM->pgm.s.cZeroPages += cPages;
1286	pVM->pgm.s.cAllPages += cPages;
1287
1288	/*
1289	* Link it.
1290	*/
1291	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1292	}
1293
1294
1295	/**
1296	* Relocate a floating RAM range.
1297	*
1298	* @copydoc FNPGMRELOCATE.
1299	*/
1300	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
1301	{
1302	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
1303	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
1304	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
1305
1306	switch (enmMode)
1307	{
1308	case PGMRELOCATECALL_SUGGEST:
1309	return true;
1310	case PGMRELOCATECALL_RELOCATE:
1311	{
1312	/* Update myself and then relink all the ranges. */
1313	pgmLock(pVM);
1314	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
1315	pgmR3PhysRelinkRamRanges(pVM);
1316	pgmUnlock(pVM);
1317	return true;
1318	}
1319
1320	default:
1321	AssertFailedReturn(false);
1322	}
1323	}
1324
1325
1326	/**
1327	* PGMR3PhysRegisterRam worker that registers a high chunk.
1328	*
1329	* @returns VBox status code.
1330	* @param pVM The VM handle.
1331	* @param GCPhys The address of the RAM.
1332	* @param cRamPages The number of RAM pages to register.
1333	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1334	* @param iChunk The chunk number.
1335	* @param pszDesc The RAM range description.
1336	* @param ppPrev Previous RAM range pointer. In/Out.
1337	*/
1338	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1339	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1340	PPGMRAMRANGE *ppPrev)
1341	{
1342	const char *pszDescChunk = iChunk == 0
1343	? pszDesc
1344	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1345	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1346
1347	/*
1348	* Allocate memory for the new chunk.
1349	*/
1350	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1351	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1352	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1353	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1354	void *pvChunk = NULL;
1355	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
1356	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1357	VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
1358	#else
1359	NULL,
1360	#endif
1361	paChunkPages);
1362	if (RT_SUCCESS(rc))
1363	{
1364	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1365	if (!VMMIsHwVirtExtForced(pVM))
1366	R0PtrChunk = NIL_RTR0PTR;
1367	#else
1368	R0PtrChunk = (uintptr_t)pvChunk;
1369	#endif
1370	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1371
1372	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1373
1374	/*
1375	* Create a mapping and map the pages into it.
1376	* We push these in below the HMA.
1377	*/
1378	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1379	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1380	if (RT_SUCCESS(rc))
1381	{
1382	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1383
1384	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1385	RTGCPTR GCPtrPage = GCPtrChunk;
1386	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1387	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1388	if (RT_SUCCESS(rc))
1389	{
1390	/*
1391	* Ok, init and link the range.
1392	*/
1393	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1394	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1395	*ppPrev = pNew;
1396	}
1397	}
1398
1399	if (RT_FAILURE(rc))
1400	SUPR3PageFreeEx(pvChunk, cChunkPages);
1401	}
1402
1403	RTMemTmpFree(paChunkPages);
1404	return rc;
1405	}
1406
1407
1408	/**
1409	* Sets up a range RAM.
1410	*
1411	* This will check for conflicting registrations, make a resource
1412	* reservation for the memory (with GMM), and setup the per-page
1413	* tracking structures (PGMPAGE).
1414	*
1415	* @returns VBox stutus code.
1416	* @param pVM Pointer to the shared VM structure.
1417	* @param GCPhys The physical address of the RAM.
1418	* @param cb The size of the RAM.
1419	* @param pszDesc The description - not copied, so, don't free or change it.
1420	*/
1421	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1422	{
1423	/*
1424	* Validate input.
1425	*/
1426	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1427	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1428	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1429	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1430	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1431	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1432	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1433	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1434
1435	pgmLock(pVM);
1436
1437	/*
1438	* Find range location and check for conflicts.
1439	* (We don't lock here because the locking by EMT is only required on update.)
1440	*/
1441	PPGMRAMRANGE pPrev = NULL;
1442	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1443	while (pRam && GCPhysLast >= pRam->GCPhys)
1444	{
1445	if ( GCPhysLast >= pRam->GCPhys
1446	&& GCPhys <= pRam->GCPhysLast)
1447	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1448	GCPhys, GCPhysLast, pszDesc,
1449	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1450	VERR_PGM_RAM_CONFLICT);
1451
1452	/* next */
1453	pPrev = pRam;
1454	pRam = pRam->pNextR3;
1455	}
1456
1457	/*
1458	* Register it with GMM (the API bitches).
1459	*/
1460	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1461	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1462	if (RT_FAILURE(rc))
1463	{
1464	pgmUnlock(pVM);
1465	return rc;
1466	}
1467
1468	if ( GCPhys >= _4G
1469	&& cPages > 256)
1470	{
1471	/*
1472	* The PGMRAMRANGE structures for the high memory can get very big.
1473	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1474	* allocation size limit there and also to avoid being unable to find
1475	* guest mapping space for them, we split this memory up into 4MB in
1476	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1477	* mode.
1478	*
1479	* The first and last page of each mapping are guard pages and marked
1480	* not-present. So, we've got 4186112 and 16769024 bytes available for
1481	* the PGMRAMRANGE structure.
1482	*
1483	* Note! The sizes used here will influence the saved state.
1484	*/
1485	uint32_t cbChunk;
1486	uint32_t cPagesPerChunk;
1487	if (VMMIsHwVirtExtForced(pVM))
1488	{
1489	cbChunk = 16U*_1M;
1490	cPagesPerChunk = 1048048; /* max ~1048059 */
1491	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1492	}
1493	else
1494	{
1495	cbChunk = 4U*_1M;
1496	cPagesPerChunk = 261616; /* max ~261627 */
1497	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1498	}
1499	AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1500
1501	RTGCPHYS cPagesLeft = cPages;
1502	RTGCPHYS GCPhysChunk = GCPhys;
1503	uint32_t iChunk = 0;
1504	while (cPagesLeft > 0)
1505	{
1506	uint32_t cPagesInChunk = cPagesLeft;
1507	if (cPagesInChunk > cPagesPerChunk)
1508	cPagesInChunk = cPagesPerChunk;
1509
1510	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1511	AssertRCReturn(rc, rc);
1512
1513	/* advance */
1514	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1515	cPagesLeft -= cPagesInChunk;
1516	iChunk++;
1517	}
1518	}
1519	else
1520	{
1521	/*
1522	* Allocate, initialize and link the new RAM range.
1523	*/
1524	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1525	PPGMRAMRANGE pNew;
1526	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1527	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1528
1529	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1530	}
1531	PGMPhysInvalidatePageMapTLB(pVM);
1532	pgmUnlock(pVM);
1533
1534	/*
1535	* Notify REM.
1536	*/
1537	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1538
1539	return VINF_SUCCESS;
1540	}
1541
1542
1543	/**
1544	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1545	*
1546	* We do this late in the init process so that all the ROM and MMIO ranges have
1547	* been registered already and we don't go wasting memory on them.
1548	*
1549	* @returns VBox status code.
1550	*
1551	* @param pVM Pointer to the shared VM structure.
1552	*/
1553	int pgmR3PhysRamPreAllocate(PVM pVM)
1554	{
1555	Assert(pVM->pgm.s.fRamPreAlloc);
1556	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1557
1558	/*
1559	* Walk the RAM ranges and allocate all RAM pages, halt at
1560	* the first allocation error.
1561	*/
1562	uint64_t cPages = 0;
1563	uint64_t NanoTS = RTTimeNanoTS();
1564	pgmLock(pVM);
1565	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1566	{
1567	PPGMPAGE pPage = &pRam->aPages[0];
1568	RTGCPHYS GCPhys = pRam->GCPhys;
1569	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1570	while (cLeft-- > 0)
1571	{
1572	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1573	{
1574	switch (PGM_PAGE_GET_STATE(pPage))
1575	{
1576	case PGM_PAGE_STATE_ZERO:
1577	{
1578	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1579	if (RT_FAILURE(rc))
1580	{
1581	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1582	pgmUnlock(pVM);
1583	return rc;
1584	}
1585	cPages++;
1586	break;
1587	}
1588
1589	case PGM_PAGE_STATE_BALLOONED:
1590	case PGM_PAGE_STATE_ALLOCATED:
1591	case PGM_PAGE_STATE_WRITE_MONITORED:
1592	case PGM_PAGE_STATE_SHARED:
1593	/* nothing to do here. */
1594	break;
1595	}
1596	}
1597
1598	/* next */
1599	pPage++;
1600	GCPhys += PAGE_SIZE;
1601	}
1602	}
1603	pgmUnlock(pVM);
1604	NanoTS = RTTimeNanoTS() - NanoTS;
1605
1606	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1607	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1608	return VINF_SUCCESS;
1609	}
1610
1611
1612	/**
1613	* Resets (zeros) the RAM.
1614	*
1615	* ASSUMES that the caller owns the PGM lock.
1616	*
1617	* @returns VBox status code.
1618	* @param pVM Pointer to the shared VM structure.
1619	*/
1620	int pgmR3PhysRamReset(PVM pVM)
1621	{
1622	Assert(PGMIsLockOwner(pVM));
1623
1624	/* Reset the memory balloon. */
1625	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1626	AssertRC(rc);
1627
1628	#ifdef VBOX_WITH_PAGE_SHARING
1629	/* Clear all registered shared modules. */
1630	rc = GMMR3ResetSharedModules(pVM);
1631	AssertRC(rc);
1632	#endif
1633	/* Reset counters. */
1634	pVM->pgm.s.cReusedSharedPages = 0;
1635	pVM->pgm.s.cBalloonedPages = 0;
1636
1637	/*
1638	* We batch up pages that should be freed instead of calling GMM for
1639	* each and every one of them.
1640	*/
1641	uint32_t cPendingPages = 0;
1642	PGMMFREEPAGESREQ pReq;
1643	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1644	AssertLogRelRCReturn(rc, rc);
1645
1646	/*
1647	* Walk the ram ranges.
1648	*/
1649	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1650	{
1651	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1652	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1653
1654	if (!pVM->pgm.s.fRamPreAlloc)
1655	{
1656	/* Replace all RAM pages by ZERO pages. */
1657	while (iPage-- > 0)
1658	{
1659	PPGMPAGE pPage = &pRam->aPages[iPage];
1660	switch (PGM_PAGE_GET_TYPE(pPage))
1661	{
1662	case PGMPAGETYPE_RAM:
1663	/* Do not replace pages part of a 2 MB continuous range with zero pages, but zero them instead. */
1664	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
1665	{
1666	void *pvPage;
1667	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1668	AssertLogRelRCReturn(rc, rc);
1669	ASMMemZeroPage(pvPage);
1670	}
1671	else
1672	if (PGM_PAGE_IS_BALLOONED(pPage))
1673	{
1674	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1675	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
1676	}
1677	else
1678	if (!PGM_PAGE_IS_ZERO(pPage))
1679	{
1680	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1681	AssertLogRelRCReturn(rc, rc);
1682	}
1683	break;
1684
1685	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1686	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
1687	true /fDoAccounting/);
1688	break;
1689
1690	case PGMPAGETYPE_MMIO2:
1691	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1692	case PGMPAGETYPE_ROM:
1693	case PGMPAGETYPE_MMIO:
1694	break;
1695	default:
1696	AssertFailed();
1697	}
1698	} /* for each page */
1699	}
1700	else
1701	{
1702	/* Zero the memory. */
1703	while (iPage-- > 0)
1704	{
1705	PPGMPAGE pPage = &pRam->aPages[iPage];
1706	switch (PGM_PAGE_GET_TYPE(pPage))
1707	{
1708	case PGMPAGETYPE_RAM:
1709	switch (PGM_PAGE_GET_STATE(pPage))
1710	{
1711	case PGM_PAGE_STATE_ZERO:
1712	break;
1713
1714	case PGM_PAGE_STATE_BALLOONED:
1715	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1716	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
1717	break;
1718
1719	case PGM_PAGE_STATE_SHARED:
1720	case PGM_PAGE_STATE_WRITE_MONITORED:
1721	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1722	AssertLogRelRCReturn(rc, rc);
1723	/* no break */
1724
1725	case PGM_PAGE_STATE_ALLOCATED:
1726	{
1727	void *pvPage;
1728	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1729	AssertLogRelRCReturn(rc, rc);
1730	ASMMemZeroPage(pvPage);
1731	break;
1732	}
1733	}
1734	break;
1735
1736	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1737	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
1738	true /fDoAccounting/);
1739	break;
1740
1741	case PGMPAGETYPE_MMIO2:
1742	case PGMPAGETYPE_ROM_SHADOW:
1743	case PGMPAGETYPE_ROM:
1744	case PGMPAGETYPE_MMIO:
1745	break;
1746	default:
1747	AssertFailed();
1748
1749	}
1750	} /* for each page */
1751	}
1752
1753	}
1754
1755	/*
1756	* Finish off any pages pending freeing.
1757	*/
1758	if (cPendingPages)
1759	{
1760	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1761	AssertLogRelRCReturn(rc, rc);
1762	}
1763	GMMR3FreePagesCleanup(pReq);
1764
1765	return VINF_SUCCESS;
1766	}
1767
1768	/**
1769	* Frees all RAM during VM termination
1770	*
1771	* ASSUMES that the caller owns the PGM lock.
1772	*
1773	* @returns VBox status code.
1774	* @param pVM Pointer to the shared VM structure.
1775	*/
1776	int pgmR3PhysRamTerm(PVM pVM)
1777	{
1778	Assert(PGMIsLockOwner(pVM));
1779
1780	/* Reset the memory balloon. */
1781	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1782	AssertRC(rc);
1783
1784	#ifdef VBOX_WITH_PAGE_SHARING
1785	/* Clear all registered shared modules. */
1786	rc = GMMR3ResetSharedModules(pVM);
1787	AssertRC(rc);
1788	#endif
1789
1790	/*
1791	* We batch up pages that should be freed instead of calling GMM for
1792	* each and every one of them.
1793	*/
1794	uint32_t cPendingPages = 0;
1795	PGMMFREEPAGESREQ pReq;
1796	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1797	AssertLogRelRCReturn(rc, rc);
1798
1799	/*
1800	* Walk the ram ranges.
1801	*/
1802	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1803	{
1804	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1805	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1806
1807	/* Replace all RAM pages by ZERO pages. */
1808	while (iPage-- > 0)
1809	{
1810	PPGMPAGE pPage = &pRam->aPages[iPage];
1811	switch (PGM_PAGE_GET_TYPE(pPage))
1812	{
1813	case PGMPAGETYPE_RAM:
1814	/* Free all shared pages. Private pages are automatically freed during GMM VM cleanup. */
1815	if (PGM_PAGE_IS_SHARED(pPage))
1816	{
1817	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1818	AssertLogRelRCReturn(rc, rc);
1819	}
1820	break;
1821
1822	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1823	case PGMPAGETYPE_MMIO2:
1824	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1825	case PGMPAGETYPE_ROM:
1826	case PGMPAGETYPE_MMIO:
1827	break;
1828	default:
1829	AssertFailed();
1830	}
1831	} /* for each page */
1832	}
1833
1834	/*
1835	* Finish off any pages pending freeing.
1836	*/
1837	if (cPendingPages)
1838	{
1839	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1840	AssertLogRelRCReturn(rc, rc);
1841	}
1842	GMMR3FreePagesCleanup(pReq);
1843	return VINF_SUCCESS;
1844	}
1845
1846	/**
1847	* This is the interface IOM is using to register an MMIO region.
1848	*
1849	* It will check for conflicts and ensure that a RAM range structure
1850	* is present before calling the PGMR3HandlerPhysicalRegister API to
1851	* register the callbacks.
1852	*
1853	* @returns VBox status code.
1854	*
1855	* @param pVM Pointer to the shared VM structure.
1856	* @param GCPhys The start of the MMIO region.
1857	* @param cb The size of the MMIO region.
1858	* @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1859	* @param pvUserR3 The user argument for R3.
1860	* @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1861	* @param pvUserR0 The user argument for R0.
1862	* @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1863	* @param pvUserRC The user argument for RC.
1864	* @param pszDesc The description of the MMIO region.
1865	*/
1866	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1867	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1868	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1869	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1870	R3PTRTYPE(const char *) pszDesc)
1871	{
1872	/*
1873	* Assert on some assumption.
1874	*/
1875	VM_ASSERT_EMT(pVM);
1876	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1877	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1878	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1879	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1880
1881	/*
1882	* Make sure there's a RAM range structure for the region.
1883	*/
1884	int rc;
1885	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1886	bool fRamExists = false;
1887	PPGMRAMRANGE pRamPrev = NULL;
1888	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1889	while (pRam && GCPhysLast >= pRam->GCPhys)
1890	{
1891	if ( GCPhysLast >= pRam->GCPhys
1892	&& GCPhys <= pRam->GCPhysLast)
1893	{
1894	/* Simplification: all within the same range. */
1895	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1896	&& GCPhysLast <= pRam->GCPhysLast,
1897	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1898	GCPhys, GCPhysLast, pszDesc,
1899	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1900	VERR_PGM_RAM_CONFLICT);
1901
1902	/* Check that it's all RAM or MMIO pages. */
1903	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1904	uint32_t cLeft = cb >> PAGE_SHIFT;
1905	while (cLeft-- > 0)
1906	{
1907	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1908	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1909	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1910	GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1911	VERR_PGM_RAM_CONFLICT);
1912	pPage++;
1913	}
1914
1915	/* Looks good. */
1916	fRamExists = true;
1917	break;
1918	}
1919
1920	/* next */
1921	pRamPrev = pRam;
1922	pRam = pRam->pNextR3;
1923	}
1924	PPGMRAMRANGE pNew;
1925	if (fRamExists)
1926	{
1927	pNew = NULL;
1928
1929	/*
1930	* Make all the pages in the range MMIO/ZERO pages, freeing any
1931	* RAM pages currently mapped here. This might not be 100% correct
1932	* for PCI memory, but we're doing the same thing for MMIO2 pages.
1933	*/
1934	rc = pgmLock(pVM);
1935	if (RT_SUCCESS(rc))
1936	{
1937	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1938	pgmUnlock(pVM);
1939	}
1940	AssertRCReturn(rc, rc);
1941
1942	/* Force a PGM pool flush as guest ram references have been changed. */
1943	/** todo; not entirely SMP safe; assuming for now the guest takes care of this internally (not touch mapped mmio while changing the mapping). */
1944	PVMCPU pVCpu = VMMGetCpu(pVM);
1945	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
1946	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1947	}
1948	else
1949	{
1950	pgmLock(pVM);
1951
1952	/*
1953	* No RAM range, insert an ad hoc one.
1954	*
1955	* Note that we don't have to tell REM about this range because
1956	* PGMHandlerPhysicalRegisterEx will do that for us.
1957	*/
1958	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1959
1960	const uint32_t cPages = cb >> PAGE_SHIFT;
1961	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1962	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1963	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1964
1965	/* Initialize the range. */
1966	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1967	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1968	pNew->GCPhys = GCPhys;
1969	pNew->GCPhysLast = GCPhysLast;
1970	pNew->cb = cb;
1971	pNew->pszDesc = pszDesc;
1972	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
1973	pNew->pvR3 = NULL;
1974	pNew->paLSPages = NULL;
1975
1976	uint32_t iPage = cPages;
1977	while (iPage-- > 0)
1978	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1979	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1980
1981	/* update the page count stats. */
1982	pVM->pgm.s.cPureMmioPages += cPages;
1983	pVM->pgm.s.cAllPages += cPages;
1984
1985	/* link it */
1986	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1987
1988	pgmUnlock(pVM);
1989	}
1990
1991	/*
1992	* Register the access handler.
1993	*/
1994	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1995	pfnHandlerR3, pvUserR3,
1996	pfnHandlerR0, pvUserR0,
1997	pfnHandlerRC, pvUserRC, pszDesc);
1998	if ( RT_FAILURE(rc)
1999	&& !fRamExists)
2000	{
2001	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
2002	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
2003
2004	/* remove the ad hoc range. */
2005	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
2006	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
2007	MMHyperFree(pVM, pRam);
2008	}
2009	PGMPhysInvalidatePageMapTLB(pVM);
2010
2011	return rc;
2012	}
2013
2014
2015	/**
2016	* This is the interface IOM is using to register an MMIO region.
2017	*
2018	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
2019	* any ad hoc PGMRAMRANGE left behind.
2020	*
2021	* @returns VBox status code.
2022	* @param pVM Pointer to the shared VM structure.
2023	* @param GCPhys The start of the MMIO region.
2024	* @param cb The size of the MMIO region.
2025	*/
2026	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
2027	{
2028	VM_ASSERT_EMT(pVM);
2029
2030	/*
2031	* First deregister the handler, then check if we should remove the ram range.
2032	*/
2033	int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2034	if (RT_SUCCESS(rc))
2035	{
2036	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2037	PPGMRAMRANGE pRamPrev = NULL;
2038	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2039	while (pRam && GCPhysLast >= pRam->GCPhys)
2040	{
2041	/** @todo We're being a bit too careful here. rewrite. */
2042	if ( GCPhysLast == pRam->GCPhysLast
2043	&& GCPhys == pRam->GCPhys)
2044	{
2045	Assert(pRam->cb == cb);
2046
2047	/*
2048	* See if all the pages are dead MMIO pages.
2049	*/
2050	uint32_t const cPages = cb >> PAGE_SHIFT;
2051	bool fAllMMIO = true;
2052	uint32_t iPage = 0;
2053	uint32_t cLeft = cPages;
2054	while (cLeft-- > 0)
2055	{
2056	PPGMPAGE pPage = &pRam->aPages[iPage];
2057	if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
2058	/\|\| not-out-of-action later /)
2059	{
2060	fAllMMIO = false;
2061	Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
2062	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2063	break;
2064	}
2065	Assert(PGM_PAGE_IS_ZERO(pPage));
2066	pPage++;
2067	}
2068	if (fAllMMIO)
2069	{
2070	/*
2071	* Ad-hoc range, unlink and free it.
2072	*/
2073	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
2074	GCPhys, GCPhysLast, pRam->pszDesc));
2075
2076	pVM->pgm.s.cAllPages -= cPages;
2077	pVM->pgm.s.cPureMmioPages -= cPages;
2078
2079	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
2080	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
2081	MMHyperFree(pVM, pRam);
2082	break;
2083	}
2084	}
2085
2086	/*
2087	* Range match? It will all be within one range (see PGMAllHandler.cpp).
2088	*/
2089	if ( GCPhysLast >= pRam->GCPhys
2090	&& GCPhys <= pRam->GCPhysLast)
2091	{
2092	Assert(GCPhys >= pRam->GCPhys);
2093	Assert(GCPhysLast <= pRam->GCPhysLast);
2094
2095	/*
2096	* Turn the pages back into RAM pages.
2097	*/
2098	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2099	uint32_t cLeft = cb >> PAGE_SHIFT;
2100	while (cLeft--)
2101	{
2102	PPGMPAGE pPage = &pRam->aPages[iPage];
2103	AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2104	AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2105	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2106	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
2107	}
2108	break;
2109	}
2110
2111	/* next */
2112	pRamPrev = pRam;
2113	pRam = pRam->pNextR3;
2114	}
2115	}
2116
2117	/* Force a PGM pool flush as guest ram references have been changed. */
2118	/** todo; not entirely SMP safe; assuming for now the guest takes care of this internally (not touch mapped mmio while changing the mapping). */
2119	PVMCPU pVCpu = VMMGetCpu(pVM);
2120	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2121	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2122
2123	PGMPhysInvalidatePageMapTLB(pVM);
2124	return rc;
2125	}
2126
2127
2128	/**
2129	* Locate a MMIO2 range.
2130	*
2131	* @returns Pointer to the MMIO2 range.
2132	* @param pVM Pointer to the shared VM structure.
2133	* @param pDevIns The device instance owning the region.
2134	* @param iRegion The region.
2135	*/
2136	DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
2137	{
2138	/*
2139	* Search the list.
2140	*/
2141	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2142	if ( pCur->pDevInsR3 == pDevIns
2143	&& pCur->iRegion == iRegion)
2144	return pCur;
2145	return NULL;
2146	}
2147
2148
2149	/**
2150	* Allocate and register an MMIO2 region.
2151	*
2152	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2153	* associated with a device. It is also non-shared memory with a permanent
2154	* ring-3 mapping and page backing (presently).
2155	*
2156	* A MMIO2 range may overlap with base memory if a lot of RAM is configured for
2157	* the VM, in which case we'll drop the base memory pages. Presently we will
2158	* make no attempt to preserve anything that happens to be present in the base
2159	* memory that is replaced, this is of course incorrectly but it's too much
2160	* effort.
2161	*
2162	* @returns VBox status code.
2163	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
2164	* memory.
2165	* @retval VERR_ALREADY_EXISTS if the region already exists.
2166	*
2167	* @param pVM Pointer to the shared VM structure.
2168	* @param pDevIns The device instance owning the region.
2169	* @param iRegion The region number. If the MMIO2 memory is a PCI
2170	* I/O region this number has to be the number of that
2171	* region. Otherwise it can be any number safe
2172	* UINT8_MAX.
2173	* @param cb The size of the region. Must be page aligned.
2174	* @param fFlags Reserved for future use, must be zero.
2175	* @param ppv Where to store the pointer to the ring-3 mapping of
2176	* the memory.
2177	* @param pszDesc The description.
2178	*/
2179	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc)
2180	{
2181	/*
2182	* Validate input.
2183	*/
2184	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2185	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2186	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2187	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
2188	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2189	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2190	AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
2191	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2192	AssertReturn(cb, VERR_INVALID_PARAMETER);
2193	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
2194
2195	const uint32_t cPages = cb >> PAGE_SHIFT;
2196	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
2197	AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
2198
2199	/*
2200	* For the 2nd+ instance, mangle the description string so it's unique.
2201	*/
2202	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
2203	{
2204	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
2205	if (!pszDesc)
2206	return VERR_NO_MEMORY;
2207	}
2208
2209	/*
2210	* Try reserve and allocate the backing memory first as this is what is
2211	* most likely to fail.
2212	*/
2213	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
2214	if (RT_SUCCESS(rc))
2215	{
2216	void *pvPages;
2217	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
2218	if (RT_SUCCESS(rc))
2219	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
2220	if (RT_SUCCESS(rc))
2221	{
2222	memset(pvPages, 0, cPages * PAGE_SIZE);
2223
2224	/*
2225	* Create the MMIO2 range record for it.
2226	*/
2227	const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
2228	PPGMMMIO2RANGE pNew;
2229	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2230	AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
2231	if (RT_SUCCESS(rc))
2232	{
2233	pNew->pDevInsR3 = pDevIns;
2234	pNew->pvR3 = pvPages;
2235	//pNew->pNext = NULL;
2236	//pNew->fMapped = false;
2237	//pNew->fOverlapping = false;
2238	pNew->iRegion = iRegion;
2239	pNew->idSavedState = UINT8_MAX;
2240	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
2241	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
2242	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
2243	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
2244	pNew->RamRange.pszDesc = pszDesc;
2245	pNew->RamRange.cb = cb;
2246	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
2247	pNew->RamRange.pvR3 = pvPages;
2248	//pNew->RamRange.paLSPages = NULL;
2249
2250	uint32_t iPage = cPages;
2251	while (iPage-- > 0)
2252	{
2253	PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
2254	paPages[iPage].Phys, NIL_GMM_PAGEID,
2255	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
2256	}
2257
2258	/* update page count stats */
2259	pVM->pgm.s.cAllPages += cPages;
2260	pVM->pgm.s.cPrivatePages += cPages;
2261
2262	/*
2263	* Link it into the list.
2264	* Since there is no particular order, just push it.
2265	*/
2266	pgmLock(pVM);
2267	pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
2268	pVM->pgm.s.pMmio2RangesR3 = pNew;
2269	pgmUnlock(pVM);
2270
2271	*ppv = pvPages;
2272	RTMemTmpFree(paPages);
2273	PGMPhysInvalidatePageMapTLB(pVM);
2274	return VINF_SUCCESS;
2275	}
2276
2277	SUPR3PageFreeEx(pvPages, cPages);
2278	}
2279	RTMemTmpFree(paPages);
2280	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
2281	}
2282	if (pDevIns->iInstance > 0)
2283	MMR3HeapFree((void *)pszDesc);
2284	return rc;
2285	}
2286
2287
2288	/**
2289	* Deregisters and frees an MMIO2 region.
2290	*
2291	* Any physical (and virtual) access handlers registered for the region must
2292	* be deregistered before calling this function.
2293	*
2294	* @returns VBox status code.
2295	* @param pVM Pointer to the shared VM structure.
2296	* @param pDevIns The device instance owning the region.
2297	* @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
2298	*/
2299	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
2300	{
2301	/*
2302	* Validate input.
2303	*/
2304	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2305	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2306	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
2307
2308	pgmLock(pVM);
2309	int rc = VINF_SUCCESS;
2310	unsigned cFound = 0;
2311	PPGMMMIO2RANGE pPrev = NULL;
2312	PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
2313	while (pCur)
2314	{
2315	if ( pCur->pDevInsR3 == pDevIns
2316	&& ( iRegion == UINT32_MAX
2317	\|\| pCur->iRegion == iRegion))
2318	{
2319	cFound++;
2320
2321	/*
2322	* Unmap it if it's mapped.
2323	*/
2324	if (pCur->fMapped)
2325	{
2326	int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
2327	AssertRC(rc2);
2328	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2329	rc = rc2;
2330	}
2331
2332	/*
2333	* Unlink it
2334	*/
2335	PPGMMMIO2RANGE pNext = pCur->pNextR3;
2336	if (pPrev)
2337	pPrev->pNextR3 = pNext;
2338	else
2339	pVM->pgm.s.pMmio2RangesR3 = pNext;
2340	pCur->pNextR3 = NULL;
2341
2342	/*
2343	* Free the memory.
2344	*/
2345	int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
2346	AssertRC(rc2);
2347	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2348	rc = rc2;
2349
2350	uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
2351	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
2352	AssertRC(rc2);
2353	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2354	rc = rc2;
2355
2356	/* we're leaking hyper memory here if done at runtime. */
2357	#ifdef VBOX_STRICT
2358	VMSTATE const enmState = VMR3GetState(pVM);
2359	AssertMsg( enmState == VMSTATE_POWERING_OFF
2360	\|\| enmState == VMSTATE_POWERING_OFF_LS
2361	\|\| enmState == VMSTATE_OFF
2362	\|\| enmState == VMSTATE_OFF_LS
2363	\|\| enmState == VMSTATE_DESTROYING
2364	\|\| enmState == VMSTATE_TERMINATED
2365	\|\| enmState == VMSTATE_CREATING
2366	, ("%s\n", VMR3GetStateName(enmState)));
2367	#endif
2368	/*rc = MMHyperFree(pVM, pCur);
2369	AssertRCReturn(rc, rc); - not safe, see the alloc call. */
2370
2371
2372	/* update page count stats */
2373	pVM->pgm.s.cAllPages -= cPages;
2374	pVM->pgm.s.cPrivatePages -= cPages;
2375
2376	/* next */
2377	pCur = pNext;
2378	}
2379	else
2380	{
2381	pPrev = pCur;
2382	pCur = pCur->pNextR3;
2383	}
2384	}
2385	PGMPhysInvalidatePageMapTLB(pVM);
2386	pgmUnlock(pVM);
2387	return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
2388	}
2389
2390
2391	/**
2392	* Maps a MMIO2 region.
2393	*
2394	* This is done when a guest / the bios / state loading changes the
2395	* PCI config. The replacing of base memory has the same restrictions
2396	* as during registration, of course.
2397	*
2398	* @returns VBox status code.
2399	*
2400	* @param pVM Pointer to the shared VM structure.
2401	* @param pDevIns The
2402	*/
2403	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2404	{
2405	/*
2406	* Validate input
2407	*/
2408	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2409	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2410	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2411	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2412	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2413	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2414
2415	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2416	AssertReturn(pCur, VERR_NOT_FOUND);
2417	AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
2418	Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
2419	Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
2420
2421	const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
2422	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2423
2424	/*
2425	* Find our location in the ram range list, checking for
2426	* restriction we don't bother implementing yet (partially overlapping).
2427	*/
2428	bool fRamExists = false;
2429	PPGMRAMRANGE pRamPrev = NULL;
2430	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2431	while (pRam && GCPhysLast >= pRam->GCPhys)
2432	{
2433	if ( GCPhys <= pRam->GCPhysLast
2434	&& GCPhysLast >= pRam->GCPhys)
2435	{
2436	/* completely within? */
2437	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2438	&& GCPhysLast <= pRam->GCPhysLast,
2439	("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
2440	GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
2441	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2442	VERR_PGM_RAM_CONFLICT);
2443	fRamExists = true;
2444	break;
2445	}
2446
2447	/* next */
2448	pRamPrev = pRam;
2449	pRam = pRam->pNextR3;
2450	}
2451	if (fRamExists)
2452	{
2453	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2454	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2455	while (cPagesLeft-- > 0)
2456	{
2457	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2458	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
2459	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
2460	VERR_PGM_RAM_CONFLICT);
2461	pPage++;
2462	}
2463	}
2464	Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
2465	GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
2466
2467	/*
2468	* Make the changes.
2469	*/
2470	pgmLock(pVM);
2471
2472	pCur->RamRange.GCPhys = GCPhys;
2473	pCur->RamRange.GCPhysLast = GCPhysLast;
2474	pCur->fMapped = true;
2475	pCur->fOverlapping = fRamExists;
2476
2477	if (fRamExists)
2478	{
2479	/** @todo use pgmR3PhysFreePageRange here. */
2480	uint32_t cPendingPages = 0;
2481	PGMMFREEPAGESREQ pReq;
2482	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2483	AssertLogRelRCReturn(rc, rc);
2484
2485	/* replace the pages, freeing all present RAM pages. */
2486	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2487	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2488	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2489	while (cPagesLeft-- > 0)
2490	{
2491	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
2492	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
2493
2494	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
2495	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
2496	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
2497	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
2498	PGM_PAGE_SET_PDE_TYPE(pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
2499	PGM_PAGE_SET_PTE_INDEX(pPageDst, 0);
2500	PGM_PAGE_SET_TRACKING(pPageDst, 0);
2501
2502	pVM->pgm.s.cZeroPages--;
2503	GCPhys += PAGE_SIZE;
2504	pPageSrc++;
2505	pPageDst++;
2506	}
2507
2508	/* Flush physical page map TLB. */
2509	PGMPhysInvalidatePageMapTLB(pVM);
2510
2511	if (cPendingPages)
2512	{
2513	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2514	AssertLogRelRCReturn(rc, rc);
2515	}
2516	GMMR3FreePagesCleanup(pReq);
2517
2518	/* Force a PGM pool flush as guest ram references have been changed. */
2519	/** todo; not entirely SMP safe; assuming for now the guest takes care of this internally (not touch mapped mmio while changing the mapping). */
2520	PVMCPU pVCpu = VMMGetCpu(pVM);
2521	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2522	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2523
2524	pgmUnlock(pVM);
2525	}
2526	else
2527	{
2528	RTGCPHYS cb = pCur->RamRange.cb;
2529
2530	/* Clear the tracking data of pages we're going to reactivate. */
2531	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2532	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2533	while (cPagesLeft-- > 0)
2534	{
2535	PGM_PAGE_SET_TRACKING(pPageSrc, 0);
2536	PGM_PAGE_SET_PTE_INDEX(pPageSrc, 0);
2537	pPageSrc++;
2538	}
2539
2540	/* link in the ram range */
2541	pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
2542	pgmUnlock(pVM);
2543
2544	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
2545	}
2546
2547	PGMPhysInvalidatePageMapTLB(pVM);
2548	return VINF_SUCCESS;
2549	}
2550
2551
2552	/**
2553	* Unmaps a MMIO2 region.
2554	*
2555	* This is done when a guest / the bios / state loading changes the
2556	* PCI config. The replacing of base memory has the same restrictions
2557	* as during registration, of course.
2558	*/
2559	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2560	{
2561	/*
2562	* Validate input
2563	*/
2564	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2565	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2566	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2567	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2568	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2569	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2570
2571	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2572	AssertReturn(pCur, VERR_NOT_FOUND);
2573	AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
2574	AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
2575	Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
2576
2577	Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
2578	pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
2579
2580	/*
2581	* Unmap it.
2582	*/
2583	pgmLock(pVM);
2584
2585	RTGCPHYS GCPhysRangeREM;
2586	RTGCPHYS cbRangeREM;
2587	bool fInformREM;
2588	if (pCur->fOverlapping)
2589	{
2590	/* Restore the RAM pages we've replaced. */
2591	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2592	while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
2593	pRam = pRam->pNextR3;
2594
2595	PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2596	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2597	while (cPagesLeft-- > 0)
2598	{
2599	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
2600	pVM->pgm.s.cZeroPages++;
2601	pPageDst++;
2602	}
2603
2604	/* Flush physical page map TLB. */
2605	PGMPhysInvalidatePageMapTLB(pVM);
2606
2607	GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
2608	cbRangeREM = RTGCPHYS_MAX; /* ditto */
2609	fInformREM = false;
2610	}
2611	else
2612	{
2613	GCPhysRangeREM = pCur->RamRange.GCPhys;
2614	cbRangeREM = pCur->RamRange.cb;
2615	fInformREM = true;
2616
2617	pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
2618	}
2619
2620	pCur->RamRange.GCPhys = NIL_RTGCPHYS;
2621	pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
2622	pCur->fOverlapping = false;
2623	pCur->fMapped = false;
2624
2625	/* Force a PGM pool flush as guest ram references have been changed. */
2626	/** todo; not entirely SMP safe; assuming for now the guest takes care of this internally (not touch mapped mmio while changing the mapping). */
2627	PVMCPU pVCpu = VMMGetCpu(pVM);
2628	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2629	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2630
2631	PGMPhysInvalidatePageMapTLB(pVM);
2632	pgmUnlock(pVM);
2633
2634	if (fInformREM)
2635	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2636
2637	return VINF_SUCCESS;
2638	}
2639
2640
2641	/**
2642	* Checks if the given address is an MMIO2 base address or not.
2643	*
2644	* @returns true/false accordingly.
2645	* @param pVM Pointer to the shared VM structure.
2646	* @param pDevIns The owner of the memory, optional.
2647	* @param GCPhys The address to check.
2648	*/
2649	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2650	{
2651	/*
2652	* Validate input
2653	*/
2654	VM_ASSERT_EMT_RETURN(pVM, false);
2655	AssertPtrReturn(pDevIns, false);
2656	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
2657	AssertReturn(GCPhys != 0, false);
2658	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
2659
2660	/*
2661	* Search the list.
2662	*/
2663	pgmLock(pVM);
2664	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2665	if (pCur->RamRange.GCPhys == GCPhys)
2666	{
2667	Assert(pCur->fMapped);
2668	pgmUnlock(pVM);
2669	return true;
2670	}
2671	pgmUnlock(pVM);
2672	return false;
2673	}
2674
2675
2676	/**
2677	* Gets the HC physical address of a page in the MMIO2 region.
2678	*
2679	* This is API is intended for MMHyper and shouldn't be called
2680	* by anyone else...
2681	*
2682	* @returns VBox status code.
2683	* @param pVM Pointer to the shared VM structure.
2684	* @param pDevIns The owner of the memory, optional.
2685	* @param iRegion The region.
2686	* @param off The page expressed an offset into the MMIO2 region.
2687	* @param pHCPhys Where to store the result.
2688	*/
2689	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2690	{
2691	/*
2692	* Validate input
2693	*/
2694	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2695	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2696	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2697
2698	pgmLock(pVM);
2699	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2700	AssertReturn(pCur, VERR_NOT_FOUND);
2701	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2702
2703	PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2704	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2705	pgmUnlock(pVM);
2706	return VINF_SUCCESS;
2707	}
2708
2709
2710	/**
2711	* Maps a portion of an MMIO2 region into kernel space (host).
2712	*
2713	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
2714	* or the VM is terminated.
2715	*
2716	* @return VBox status code.
2717	*
2718	* @param pVM Pointer to the shared VM structure.
2719	* @param pDevIns The device owning the MMIO2 memory.
2720	* @param iRegion The region.
2721	* @param off The offset into the region. Must be page aligned.
2722	* @param cb The number of bytes to map. Must be page aligned.
2723	* @param pszDesc Mapping description.
2724	* @param pR0Ptr Where to store the R0 address.
2725	*/
2726	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2727	const char *pszDesc, PRTR0PTR pR0Ptr)
2728	{
2729	/*
2730	* Validate input.
2731	*/
2732	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2733	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2734	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2735
2736	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2737	AssertReturn(pCur, VERR_NOT_FOUND);
2738	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2739	AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2740	AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2741
2742	/*
2743	* Pass the request on to the support library/driver.
2744	*/
2745	int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2746
2747	return rc;
2748	}
2749
2750
2751	/**
2752	* Registers a ROM image.
2753	*
2754	* Shadowed ROM images requires double the amount of backing memory, so,
2755	* don't use that unless you have to. Shadowing of ROM images is process
2756	* where we can select where the reads go and where the writes go. On real
2757	* hardware the chipset provides means to configure this. We provide
2758	* PGMR3PhysProtectROM() for this purpose.
2759	*
2760	* A read-only copy of the ROM image will always be kept around while we
2761	* will allocate RAM pages for the changes on demand (unless all memory
2762	* is configured to be preallocated).
2763	*
2764	* @returns VBox status.
2765	* @param pVM VM Handle.
2766	* @param pDevIns The device instance owning the ROM.
2767	* @param GCPhys First physical address in the range.
2768	* Must be page aligned!
2769	* @param cbRange The size of the range (in bytes).
2770	* Must be page aligned!
2771	* @param pvBinary Pointer to the binary data backing the ROM image.
2772	* This must be exactly \a cbRange in size.
2773	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2774	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2775	* @param pszDesc Pointer to description string. This must not be freed.
2776	*
2777	* @remark There is no way to remove the rom, automatically on device cleanup or
2778	* manually from the device yet. This isn't difficult in any way, it's
2779	* just not something we expect to be necessary for a while.
2780	*/
2781	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2782	const void pvBinary, uint32_t fFlags, const char pszDesc)
2783	{
2784	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2785	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2786
2787	/*
2788	* Validate input.
2789	*/
2790	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2791	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2792	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2793	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2794	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2795	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2796	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2797	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2798	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2799
2800	const uint32_t cPages = cb >> PAGE_SHIFT;
2801
2802	/*
2803	* Find the ROM location in the ROM list first.
2804	*/
2805	PPGMROMRANGE pRomPrev = NULL;
2806	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2807	while (pRom && GCPhysLast >= pRom->GCPhys)
2808	{
2809	if ( GCPhys <= pRom->GCPhysLast
2810	&& GCPhysLast >= pRom->GCPhys)
2811	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2812	GCPhys, GCPhysLast, pszDesc,
2813	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2814	VERR_PGM_RAM_CONFLICT);
2815	/* next */
2816	pRomPrev = pRom;
2817	pRom = pRom->pNextR3;
2818	}
2819
2820	/*
2821	* Find the RAM location and check for conflicts.
2822	*
2823	* Conflict detection is a bit different than for RAM
2824	* registration since a ROM can be located within a RAM
2825	* range. So, what we have to check for is other memory
2826	* types (other than RAM that is) and that we don't span
2827	* more than one RAM range (layz).
2828	*/
2829	bool fRamExists = false;
2830	PPGMRAMRANGE pRamPrev = NULL;
2831	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2832	while (pRam && GCPhysLast >= pRam->GCPhys)
2833	{
2834	if ( GCPhys <= pRam->GCPhysLast
2835	&& GCPhysLast >= pRam->GCPhys)
2836	{
2837	/* completely within? */
2838	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2839	&& GCPhysLast <= pRam->GCPhysLast,
2840	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2841	GCPhys, GCPhysLast, pszDesc,
2842	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2843	VERR_PGM_RAM_CONFLICT);
2844	fRamExists = true;
2845	break;
2846	}
2847
2848	/* next */
2849	pRamPrev = pRam;
2850	pRam = pRam->pNextR3;
2851	}
2852	if (fRamExists)
2853	{
2854	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2855	uint32_t cPagesLeft = cPages;
2856	while (cPagesLeft-- > 0)
2857	{
2858	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2859	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2860	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2861	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2862	Assert(PGM_PAGE_IS_ZERO(pPage));
2863	pPage++;
2864	}
2865	}
2866
2867	/*
2868	* Update the base memory reservation if necessary.
2869	*/
2870	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
2871	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2872	cExtraBaseCost += cPages;
2873	if (cExtraBaseCost)
2874	{
2875	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2876	if (RT_FAILURE(rc))
2877	return rc;
2878	}
2879
2880	/*
2881	* Allocate memory for the virgin copy of the RAM.
2882	*/
2883	PGMMALLOCATEPAGESREQ pReq;
2884	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2885	AssertRCReturn(rc, rc);
2886
2887	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2888	{
2889	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2890	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2891	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2892	}
2893
2894	pgmLock(pVM);
2895	rc = GMMR3AllocatePagesPerform(pVM, pReq);
2896	pgmUnlock(pVM);
2897	if (RT_FAILURE(rc))
2898	{
2899	GMMR3AllocatePagesCleanup(pReq);
2900	return rc;
2901	}
2902
2903	/*
2904	* Allocate the new ROM range and RAM range (if necessary).
2905	*/
2906	PPGMROMRANGE pRomNew;
2907	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2908	if (RT_SUCCESS(rc))
2909	{
2910	PPGMRAMRANGE pRamNew = NULL;
2911	if (!fRamExists)
2912	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2913	if (RT_SUCCESS(rc))
2914	{
2915	pgmLock(pVM);
2916
2917	/*
2918	* Initialize and insert the RAM range (if required).
2919	*/
2920	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2921	if (!fRamExists)
2922	{
2923	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2924	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2925	pRamNew->GCPhys = GCPhys;
2926	pRamNew->GCPhysLast = GCPhysLast;
2927	pRamNew->cb = cb;
2928	pRamNew->pszDesc = pszDesc;
2929	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
2930	pRamNew->pvR3 = NULL;
2931	pRamNew->paLSPages = NULL;
2932
2933	PPGMPAGE pPage = &pRamNew->aPages[0];
2934	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2935	{
2936	PGM_PAGE_INIT(pPage,
2937	pReq->aPages[iPage].HCPhysGCPhys,
2938	pReq->aPages[iPage].idPage,
2939	PGMPAGETYPE_ROM,
2940	PGM_PAGE_STATE_ALLOCATED);
2941
2942	pRomPage->Virgin = *pPage;
2943	}
2944
2945	pVM->pgm.s.cAllPages += cPages;
2946	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2947	}
2948	else
2949	{
2950	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2951	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2952	{
2953	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2954	PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2955	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2956	PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2957	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
2958	PGM_PAGE_SET_PTE_INDEX(pPage, 0);
2959	PGM_PAGE_SET_TRACKING(pPage, 0);
2960
2961	pRomPage->Virgin = *pPage;
2962	}
2963
2964	pRamNew = pRam;
2965
2966	pVM->pgm.s.cZeroPages -= cPages;
2967	}
2968	pVM->pgm.s.cPrivatePages += cPages;
2969
2970	/* Flush physical page map TLB. */
2971	PGMPhysInvalidatePageMapTLB(pVM);
2972
2973	pgmUnlock(pVM);
2974
2975
2976	/*
2977	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2978	*
2979	* If it's shadowed we'll register the handler after the ROM notification
2980	* so we get the access handler callbacks that we should. If it isn't
2981	* shadowed we'll do it the other way around to make REM use the built-in
2982	* ROM behavior and not the handler behavior (which is to route all access
2983	* to PGM atm).
2984	*/
2985	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2986	{
2987	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2988	rc = PGMR3HandlerPhysicalRegister(pVM,
2989	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2990	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2991	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2992	GCPhys, GCPhysLast,
2993	pgmR3PhysRomWriteHandler, pRomNew,
2994	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2995	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2996	}
2997	else
2998	{
2999	rc = PGMR3HandlerPhysicalRegister(pVM,
3000	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
3001	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
3002	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
3003	GCPhys, GCPhysLast,
3004	pgmR3PhysRomWriteHandler, pRomNew,
3005	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
3006	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
3007	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
3008	}
3009	if (RT_SUCCESS(rc))
3010	{
3011	pgmLock(pVM);
3012
3013	/*
3014	* Copy the image over to the virgin pages.
3015	* This must be done after linking in the RAM range.
3016	*/
3017	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
3018	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
3019	{
3020	void *pvDstPage;
3021	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
3022	if (RT_FAILURE(rc))
3023	{
3024	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
3025	break;
3026	}
3027	memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
3028	}
3029	if (RT_SUCCESS(rc))
3030	{
3031	/*
3032	* Initialize the ROM range.
3033	* Note that the Virgin member of the pages has already been initialized above.
3034	*/
3035	pRomNew->GCPhys = GCPhys;
3036	pRomNew->GCPhysLast = GCPhysLast;
3037	pRomNew->cb = cb;
3038	pRomNew->fFlags = fFlags;
3039	pRomNew->idSavedState = UINT8_MAX;
3040	#ifdef VBOX_STRICT
3041	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY
3042	? pvBinary : RTMemDup(pvBinary, cPages * PAGE_SIZE);
3043	#else
3044	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
3045	#endif
3046	pRomNew->pszDesc = pszDesc;
3047
3048	for (unsigned iPage = 0; iPage < cPages; iPage++)
3049	{
3050	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
3051	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
3052	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
3053	}
3054
3055	/* update the page count stats for the shadow pages. */
3056	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
3057	{
3058	pVM->pgm.s.cZeroPages += cPages;
3059	pVM->pgm.s.cAllPages += cPages;
3060	}
3061
3062	/*
3063	* Insert the ROM range, tell REM and return successfully.
3064	*/
3065	pRomNew->pNextR3 = pRom;
3066	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
3067	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
3068
3069	if (pRomPrev)
3070	{
3071	pRomPrev->pNextR3 = pRomNew;
3072	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
3073	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
3074	}
3075	else
3076	{
3077	pVM->pgm.s.pRomRangesR3 = pRomNew;
3078	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
3079	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
3080	}
3081
3082	PGMPhysInvalidatePageMapTLB(pVM);
3083	GMMR3AllocatePagesCleanup(pReq);
3084	pgmUnlock(pVM);
3085	return VINF_SUCCESS;
3086	}
3087
3088	/* bail out */
3089
3090	pgmUnlock(pVM);
3091	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
3092	AssertRC(rc2);
3093	pgmLock(pVM);
3094	}
3095
3096	if (!fRamExists)
3097	{
3098	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
3099	MMHyperFree(pVM, pRamNew);
3100	}
3101	}
3102	MMHyperFree(pVM, pRomNew);
3103	}
3104
3105	/** @todo Purge the mapping cache or something... */
3106	GMMR3FreeAllocatedPages(pVM, pReq);
3107	GMMR3AllocatePagesCleanup(pReq);
3108	pgmUnlock(pVM);
3109	return rc;
3110	}
3111
3112
3113	/**
3114	* \#PF Handler callback for ROM write accesses.
3115	*
3116	* @returns VINF_SUCCESS if the handler have carried out the operation.
3117	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
3118	* @param pVM VM Handle.
3119	* @param GCPhys The physical address the guest is writing to.
3120	* @param pvPhys The HC mapping of that address.
3121	* @param pvBuf What the guest is reading/writing.
3122	* @param cbBuf How much it's reading/writing.
3123	* @param enmAccessType The access type.
3124	* @param pvUser User argument.
3125	*/
3126	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
3127	PGMACCESSTYPE enmAccessType, void *pvUser)
3128	{
3129	PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
3130	const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
3131	Assert(iPage < (pRom->cb >> PAGE_SHIFT));
3132	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
3133	Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
3134
3135	if (enmAccessType == PGMACCESSTYPE_READ)
3136	{
3137	switch (pRomPage->enmProt)
3138	{
3139	/*
3140	* Take the default action.
3141	*/
3142	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
3143	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
3144	case PGMROMPROT_READ_ROM_WRITE_RAM:
3145	case PGMROMPROT_READ_RAM_WRITE_RAM:
3146	return VINF_PGM_HANDLER_DO_DEFAULT;
3147
3148	default:
3149	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
3150	pRom->aPages[iPage].enmProt, iPage, GCPhys),
3151	VERR_INTERNAL_ERROR);
3152	}
3153	}
3154	else
3155	{
3156	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
3157	switch (pRomPage->enmProt)
3158	{
3159	/*
3160	* Ignore writes.
3161	*/
3162	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
3163	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
3164	return VINF_SUCCESS;
3165
3166	/*
3167	* Write to the RAM page.
3168	*/
3169	case PGMROMPROT_READ_ROM_WRITE_RAM:
3170	case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's way simpler that way. */
3171	{
3172	/* This should be impossible now, pvPhys doesn't work cross page anylonger. */
3173	Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
3174
3175	/*
3176	* Take the lock, do lazy allocation, map the page and copy the data.
3177	*
3178	* Note that we have to bypass the mapping TLB since it works on
3179	* guest physical addresses and entering the shadow page would
3180	* kind of screw things up...
3181	*/
3182	int rc = pgmLock(pVM);
3183	AssertRC(rc);
3184
3185	PPGMPAGE pShadowPage = &pRomPage->Shadow;
3186	if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
3187	{
3188	pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
3189	AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
3190	}
3191
3192	void *pvDstPage;
3193	rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
3194	if (RT_SUCCESS(rc))
3195	{
3196	memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
3197	pRomPage->LiveSave.fWrittenTo = true;
3198	}
3199
3200	pgmUnlock(pVM);
3201	return rc;
3202	}
3203
3204	default:
3205	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
3206	pRom->aPages[iPage].enmProt, iPage, GCPhys),
3207	VERR_INTERNAL_ERROR);
3208	}
3209	}
3210	}
3211
3212
3213	/**
3214	* Called by PGMR3Reset to reset the shadow, switch to the virgin,
3215	* and verify that the virgin part is untouched.
3216	*
3217	* This is done after the normal memory has been cleared.
3218	*
3219	* ASSUMES that the caller owns the PGM lock.
3220	*
3221	* @param pVM The VM handle.
3222	*/
3223	int pgmR3PhysRomReset(PVM pVM)
3224	{
3225	Assert(PGMIsLockOwner(pVM));
3226	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
3227	{
3228	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
3229
3230	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
3231	{
3232	/*
3233	* Reset the physical handler.
3234	*/
3235	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
3236	AssertRCReturn(rc, rc);
3237
3238	/*
3239	* What we do with the shadow pages depends on the memory
3240	* preallocation option. If not enabled, we'll just throw
3241	* out all the dirty pages and replace them by the zero page.
3242	*/
3243	if (!pVM->pgm.s.fRamPreAlloc)
3244	{
3245	/* Free the dirty pages. */
3246	uint32_t cPendingPages = 0;
3247	PGMMFREEPAGESREQ pReq;
3248	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3249	AssertRCReturn(rc, rc);
3250
3251	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3252	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
3253	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
3254	{
3255	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
3256	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow,
3257	pRom->GCPhys + (iPage << PAGE_SHIFT));
3258	AssertLogRelRCReturn(rc, rc);
3259	}
3260
3261	if (cPendingPages)
3262	{
3263	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
3264	AssertLogRelRCReturn(rc, rc);
3265	}
3266	GMMR3FreePagesCleanup(pReq);
3267	}
3268	else
3269	{
3270	/* clear all the shadow pages. */
3271	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3272	{
3273	Assert(!PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow));
3274	Assert(!PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
3275	void *pvDstPage;
3276	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
3277	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
3278	if (RT_FAILURE(rc))
3279	break;
3280	ASMMemZeroPage(pvDstPage);
3281	}
3282	AssertRCReturn(rc, rc);
3283	}
3284	}
3285
3286	#ifdef VBOX_STRICT
3287	/*
3288	* Verify that the virgin page is unchanged if possible.
3289	*/
3290	if (pRom->pvOriginal)
3291	{
3292	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
3293	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
3294	{
3295	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
3296	void const *pvDstPage;
3297	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
3298	if (RT_FAILURE(rc))
3299	break;
3300	if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
3301	LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
3302	GCPhys, pRom->pszDesc));
3303	}
3304	}
3305	#endif
3306	}
3307
3308	return VINF_SUCCESS;
3309	}
3310
3311
3312	/**
3313	* Called by PGMR3Term to free resources.
3314	*
3315	* ASSUMES that the caller owns the PGM lock.
3316	*
3317	* @param pVM The VM handle.
3318	*/
3319	void pgmR3PhysRomTerm(PVM pVM)
3320	{
3321	#ifdef RT_STRICT
3322	/*
3323	* Free the heap copy of the original bits.
3324	*/
3325	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
3326	{
3327	if ( pRom->pvOriginal
3328	&& !(pRom->fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY))
3329	{
3330	RTMemFree((void *)pRom->pvOriginal);
3331	pRom->pvOriginal = NULL;
3332	}
3333	}
3334	#endif
3335	}
3336
3337
3338	/**
3339	* Change the shadowing of a range of ROM pages.
3340	*
3341	* This is intended for implementing chipset specific memory registers
3342	* and will not be very strict about the input. It will silently ignore
3343	* any pages that are not the part of a shadowed ROM.
3344	*
3345	* @returns VBox status code.
3346	* @retval VINF_PGM_SYNC_CR3
3347	*
3348	* @param pVM Pointer to the shared VM structure.
3349	* @param GCPhys Where to start. Page aligned.
3350	* @param cb How much to change. Page aligned.
3351	* @param enmProt The new ROM protection.
3352	*/
3353	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
3354	{
3355	/*
3356	* Check input
3357	*/
3358	if (!cb)
3359	return VINF_SUCCESS;
3360	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3361	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3362	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
3363	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3364	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
3365
3366	/*
3367	* Process the request.
3368	*/
3369	pgmLock(pVM);
3370	int rc = VINF_SUCCESS;
3371	bool fFlushTLB = false;
3372	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
3373	{
3374	if ( GCPhys <= pRom->GCPhysLast
3375	&& GCPhysLast >= pRom->GCPhys
3376	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
3377	{
3378	/*
3379	* Iterate the relevant pages and make necessary the changes.
3380	*/
3381	bool fChanges = false;
3382	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
3383	? pRom->cb >> PAGE_SHIFT
3384	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
3385	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
3386	iPage < cPages;
3387	iPage++)
3388	{
3389	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
3390	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
3391	{
3392	fChanges = true;
3393
3394	/* flush references to the page. */
3395	PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
3396	int rc2 = pgmPoolTrackUpdateGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage,
3397	true /fFlushPTEs/, &fFlushTLB);
3398	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
3399	rc = rc2;
3400
3401	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
3402	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
3403
3404	pOld = pRamPage;
3405	pRamPage = pNew;
3406	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
3407	}
3408	pRomPage->enmProt = enmProt;
3409	}
3410
3411	/*
3412	* Reset the access handler if we made changes, no need
3413	* to optimize this.
3414	*/
3415	if (fChanges)
3416	{
3417	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
3418	if (RT_FAILURE(rc2))
3419	{
3420	pgmUnlock(pVM);
3421	AssertRC(rc);
3422	return rc2;
3423	}
3424	}
3425
3426	/* Advance - cb isn't updated. */
3427	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
3428	}
3429	}
3430	pgmUnlock(pVM);
3431	if (fFlushTLB)
3432	PGM_INVL_ALL_VCPU_TLBS(pVM);
3433
3434	return rc;
3435	}
3436
3437
3438	/**
3439	* Sets the Address Gate 20 state.
3440	*
3441	* @param pVCpu The VCPU to operate on.
3442	* @param fEnable True if the gate should be enabled.
3443	* False if the gate should be disabled.
3444	*/
3445	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
3446	{
3447	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
3448	if (pVCpu->pgm.s.fA20Enabled != fEnable)
3449	{
3450	pVCpu->pgm.s.fA20Enabled = fEnable;
3451	pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
3452	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
3453	/** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
3454	}
3455	}
3456
3457	#ifdef PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
3458	/**
3459	* Tree enumeration callback for dealing with age rollover.
3460	* It will perform a simple compression of the current age.
3461	*/
3462	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
3463	{
3464	Assert(PGMIsLockOwner((PVM)pvUser));
3465	/* Age compression - ASSUMES iNow == 4. */
3466	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3467	if (pChunk->iAge >= UINT32_C(0xffffff00))
3468	pChunk->iAge = 3;
3469	else if (pChunk->iAge >= UINT32_C(0xfffff000))
3470	pChunk->iAge = 2;
3471	else if (pChunk->iAge)
3472	pChunk->iAge = 1;
3473	else /* iAge = 0 */
3474	pChunk->iAge = 4;
3475	return 0;
3476	}
3477
3478
3479	/**
3480	* Tree enumeration callback that updates the chunks that have
3481	* been used since the last
3482	*/
3483	static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
3484	{
3485	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3486	if (!pChunk->iAge)
3487	{
3488	PVM pVM = (PVM)pvUser;
3489	pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
3490	}
3491	return 0;
3492	}
3493
3494
3495	/**
3496	* Performs ageing of the ring-3 chunk mappings.
3497	*
3498	* @param pVM The VM handle.
3499	*/
3500	VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
3501	{
3502	pgmLock(pVM);
3503	pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
3504	pVM->pgm.s.ChunkR3Map.iNow++;
3505	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
3506	{
3507	pVM->pgm.s.ChunkR3Map.iNow = 4;
3508	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
3509	}
3510	else
3511	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingCallback, pVM);
3512	pgmUnlock(pVM);
3513	}
3514
3515
3516	/**
3517	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
3518	*/
3519	typedef struct PGMR3PHYSCHUNKUNMAPCB
3520	{
3521	PVM pVM; /*< The VM handle. /
3522	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
3523	uint32_t iLastAge; /*< Highest age found so far. /
3524	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
3525
3526
3527	/**
3528	* Callback used to find the mapping that's been unused for
3529	* the longest time.
3530	*/
3531	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLU32NODECORE pNode, void *pvUser)
3532	{
3533	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3534	PPGMR3PHYSCHUNKUNMAPCB pArg = (PPGMR3PHYSCHUNKUNMAPCB)pvUser;
3535
3536	if ( pChunk->iAge
3537	&& !pChunk->cRefs
3538	&& pArg->iLastAge < pChunk->iAge)
3539	{
3540	/*
3541	* Check that it's not in any of the TLBs.
3542	*/
3543	PVM pVM = pArg->pVM;
3544	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3545	if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
3546	{
3547	pChunk = NULL;
3548	break;
3549	}
3550	if (pChunk)
3551	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
3552	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
3553	{
3554	pChunk = NULL;
3555	break;
3556	}
3557	if (pChunk)
3558	{
3559	pArg->pChunk = pChunk;
3560	pArg->iLastAge = pChunk->iAge;
3561	}
3562	}
3563	return 0;
3564	}
3565
3566
3567	/**
3568	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
3569	*
3570	* The candidate will not be part of any TLBs, so no need to flush
3571	* anything afterwards.
3572	*
3573	* @returns Chunk id.
3574	* @param pVM The VM handle.
3575	*/
3576	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
3577	{
3578	Assert(PGMIsLockOwner(pVM));
3579
3580	/*
3581	* Do tree ageing first?
3582	*/
3583	if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
3584	{
3585	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkAging, a);
3586	PGMR3PhysChunkAgeing(pVM);
3587	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkAging, a);
3588	}
3589
3590	/*
3591	* Enumerate the age tree starting with the left most node.
3592	*/
3593	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
3594	PGMR3PHYSCHUNKUNMAPCB Args;
3595	Args.pVM = pVM;
3596	Args.pChunk = NULL;
3597	Args.iLastAge = 0;
3598	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, &Args);
3599	Assert(Args.pChunk);
3600	if (Args.pChunk)
3601	{
3602	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
3603	return Args.pChunk->Core.Key;
3604	}
3605
3606	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
3607	return INT32_MAX;
3608	}
3609
3610	/**
3611	* Rendezvous callback used by pgmR3PhysUnmapChunk that unmaps a chunk
3612	*
3613	* This is only called on one of the EMTs while the other ones are waiting for
3614	* it to complete this function.
3615	*
3616	* @returns VINF_SUCCESS (VBox strict status code).
3617	* @param pVM The VM handle.
3618	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
3619	* @param pvUser User pointer. Unused
3620	*
3621	*/
3622	DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
3623	{
3624	int rc = VINF_SUCCESS;
3625	pgmLock(pVM);
3626
3627	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3628	{
3629	/* Flush the pgm pool cache; call the internal rendezvous handler as we're already in a rendezvous handler here. */
3630	/* todo: also not really efficient to unmap a chunk that contains PD or PT pages. */
3631	pgmR3PoolClearAllRendezvous(pVM, &pVM->aCpus[0], NULL /* no need to flush the REM TLB as we already did that above */);
3632
3633	/*
3634	* Request the ring-0 part to unmap a chunk to make space in the mapping cache.
3635	*/
3636	GMMMAPUNMAPCHUNKREQ Req;
3637	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3638	Req.Hdr.cbReq = sizeof(Req);
3639	Req.pvR3 = NULL;
3640	Req.idChunkMap = NIL_GMM_CHUNKID;
3641	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
3642
3643	if (Req.idChunkUnmap != INT32_MAX)
3644	{
3645	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
3646	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3647	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
3648	if (RT_SUCCESS(rc))
3649	{
3650	/* remove the unmapped one. */
3651	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
3652	AssertRelease(pUnmappedChunk);
3653	pUnmappedChunk->pv = NULL;
3654	pUnmappedChunk->Core.Key = UINT32_MAX;
3655	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3656	MMR3HeapFree(pUnmappedChunk);
3657	#else
3658	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3659	#endif
3660	pVM->pgm.s.ChunkR3Map.c--;
3661	pVM->pgm.s.cUnmappedChunks++;
3662
3663	/* Flush dangling PGM pointers (R3 & R0 ptrs to GC physical addresses) */
3664	/* todo: we should not flush chunks which include cr3 mappings. */
3665	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3666	{
3667	PPGMCPU pPGM = &pVM->aCpus[idCpu].pgm.s;
3668
3669	pPGM->pGst32BitPdR3 = NULL;
3670	pPGM->pGstPaePdptR3 = NULL;
3671	pPGM->pGstAmd64Pml4R3 = NULL;
3672	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3673	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
3674	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
3675	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
3676	#endif
3677	for (unsigned i = 0; i < RT_ELEMENTS(pPGM->apGstPaePDsR3); i++)
3678	{
3679	pPGM->apGstPaePDsR3[i] = NULL;
3680	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3681	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
3682	#endif
3683	}
3684
3685	/* Flush REM TLBs. */
3686	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3687	}
3688
3689	/* Flush REM translation blocks. */
3690	REMFlushTBs(pVM);
3691	}
3692	}
3693	}
3694	pgmUnlock(pVM);
3695	return rc;
3696	}
3697
3698	/**
3699	* Unmap a chunk to free up virtual address space (request packet handler for pgmR3PhysChunkMap)
3700	*
3701	* @returns VBox status code.
3702	* @param pVM The VM to operate on.
3703	*/
3704	void pgmR3PhysUnmapChunk(PVM pVM)
3705	{
3706	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysUnmapChunkRendezvous, NULL);
3707	AssertRC(rc);
3708	}
3709	#endif /* PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST */
3710
3711	/**
3712	* Maps the given chunk into the ring-3 mapping cache.
3713	*
3714	* This will call ring-0.
3715	*
3716	* @returns VBox status code.
3717	* @param pVM The VM handle.
3718	* @param idChunk The chunk in question.
3719	* @param ppChunk Where to store the chunk tracking structure.
3720	*
3721	* @remarks Called from within the PGM critical section.
3722	* @remarks Can be called from any thread!
3723	*/
3724	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
3725	{
3726	int rc;
3727
3728	Assert(PGMIsLockOwner(pVM));
3729	/*
3730	* Allocate a new tracking structure first.
3731	*/
3732	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3733	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
3734	#else
3735	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
3736	#endif
3737	AssertReturn(pChunk, VERR_NO_MEMORY);
3738	pChunk->Core.Key = idChunk;
3739
3740	/*
3741	* Request the ring-0 part to map the chunk in question.
3742	*/
3743	GMMMAPUNMAPCHUNKREQ Req;
3744	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3745	Req.Hdr.cbReq = sizeof(Req);
3746	Req.pvR3 = NULL;
3747	Req.idChunkMap = idChunk;
3748	Req.idChunkUnmap = NIL_GMM_CHUNKID;
3749
3750	/* Must be callable from any thread, so can't use VMMR3CallR0. */
3751	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
3752	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, NIL_VMCPUID, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3753	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
3754	if (RT_SUCCESS(rc))
3755	{
3756	/*
3757	* Update the tree.
3758	*/
3759	/* insert the new one. */
3760	AssertPtr(Req.pvR3);
3761	pChunk->pv = Req.pvR3;
3762	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
3763	AssertRelease(fRc);
3764	pVM->pgm.s.ChunkR3Map.c++;
3765	pVM->pgm.s.cMappedChunks++;
3766
3767	/* If we're running out of virtual address space, then we should unmap another chunk. */
3768	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3769	{
3770	#ifdef PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
3771	/* Postpone the unmap operation (which requires a rendezvous operation) as we own the PGM lock here. */
3772	rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysUnmapChunk, 1, pVM);
3773	AssertRC(rc);
3774	#else
3775	AssertFatalFailed(); /* can't happen */
3776	#endif
3777	}
3778	}
3779	else
3780	{
3781	AssertRC(rc);
3782	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3783	MMR3HeapFree(pChunk);
3784	#else
3785	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
3786	#endif
3787	pChunk = NULL;
3788	}
3789
3790	*ppChunk = pChunk;
3791	return rc;
3792	}
3793
3794
3795	/**
3796	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3797	*
3798	* @returns see pgmR3PhysChunkMap.
3799	* @param pVM The VM handle.
3800	* @param idChunk The chunk to map.
3801	*/
3802	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3803	{
3804	PPGMCHUNKR3MAP pChunk;
3805	int rc;
3806
3807	pgmLock(pVM);
3808	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3809	pgmUnlock(pVM);
3810	return rc;
3811	}
3812
3813
3814	/**
3815	* Invalidates the TLB for the ring-3 mapping cache.
3816	*
3817	* @param pVM The VM handle.
3818	*/
3819	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3820	{
3821	pgmLock(pVM);
3822	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3823	{
3824	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3825	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3826	}
3827	/* The page map TLB references chunks, so invalidate that one too. */
3828	PGMPhysInvalidatePageMapTLB(pVM);
3829	pgmUnlock(pVM);
3830	}
3831
3832
3833	/**
3834	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_PAGE to allocate a large (2MB) page
3835	* for use with a nested paging PDE.
3836	*
3837	* @returns The following VBox status codes.
3838	* @retval VINF_SUCCESS on success.
3839	* @retval VINF_EM_NO_MEMORY if we're out of memory.
3840	*
3841	* @param pVM The VM handle.
3842	* @param GCPhys GC physical start address of the 2 MB range
3843	*/
3844	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
3845	{
3846	pgmLock(pVM);
3847
3848	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
3849	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
3850	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
3851	if (RT_SUCCESS(rc))
3852	{
3853	Assert(pVM->pgm.s.cLargeHandyPages == 1);
3854
3855	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
3856	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
3857
3858	void *pv;
3859
3860	/* Map the large page into our address space.
3861	*
3862	* Note: assuming that within the 2 MB range:
3863	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
3864	* - user space mapping is continuous as well
3865	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
3866	*/
3867	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
3868	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n", idPage, HCPhys, rc));
3869
3870	if (RT_SUCCESS(rc))
3871	{
3872	/*
3873	* Clear the pages.
3874	*/
3875	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
3876	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
3877	{
3878	ASMMemZeroPage(pv);
3879
3880	PPGMPAGE pPage;
3881	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
3882	AssertRC(rc);
3883
3884	Assert(PGM_PAGE_IS_ZERO(pPage));
3885	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRZPageReplaceZero);
3886	pVM->pgm.s.cZeroPages--;
3887
3888	/*
3889	* Do the PGMPAGE modifications.
3890	*/
3891	pVM->pgm.s.cPrivatePages++;
3892	PGM_PAGE_SET_HCPHYS(pPage, HCPhys);
3893	PGM_PAGE_SET_PAGEID(pPage, idPage);
3894	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
3895	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_PDE);
3896	PGM_PAGE_SET_PTE_INDEX(pPage, 0);
3897	PGM_PAGE_SET_TRACKING(pPage, 0);
3898
3899	/* Somewhat dirty assumption that page ids are increasing. */
3900	idPage++;
3901
3902	HCPhys += PAGE_SIZE;
3903	GCPhys += PAGE_SIZE;
3904
3905	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
3906
3907	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
3908	}
3909	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
3910
3911	/* Flush all TLBs. */
3912	PGM_INVL_ALL_VCPU_TLBS(pVM);
3913	PGMPhysInvalidatePageMapTLB(pVM);
3914	}
3915	pVM->pgm.s.cLargeHandyPages = 0;
3916	}
3917
3918	pgmUnlock(pVM);
3919	return rc;
3920	}
3921
3922
3923	/**
3924	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3925	*
3926	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3927	* signal and clear the out of memory condition. When contracted, this API is
3928	* used to try clear the condition when the user wants to resume.
3929	*
3930	* @returns The following VBox status codes.
3931	* @retval VINF_SUCCESS on success. FFs cleared.
3932	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3933	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3934	*
3935	* @param pVM The VM handle.
3936	*
3937	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3938	* in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3939	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3940	* handler.
3941	*/
3942	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3943	{
3944	pgmLock(pVM);
3945
3946	/*
3947	* Allocate more pages, noting down the index of the first new page.
3948	*/
3949	uint32_t iClear = pVM->pgm.s.cHandyPages;
3950	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3951	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3952	int rcAlloc = VINF_SUCCESS;
3953	int rcSeed = VINF_SUCCESS;
3954	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3955	while (rc == VERR_GMM_SEED_ME)
3956	{
3957	void *pvChunk;
3958	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3959	if (RT_SUCCESS(rc))
3960	{
3961	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3962	if (RT_FAILURE(rc))
3963	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3964	}
3965	if (RT_SUCCESS(rc))
3966	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3967	}
3968
3969	/* todo: we should split this up into an allocate and flush operation. sometimes you want to flush and not allocate more (which will trigger the vm account limit error) */
3970	if ( rc == VERR_GMM_HIT_VM_ACCOUNT_LIMIT
3971	&& pVM->pgm.s.cHandyPages > 0)
3972	{
3973	/* Still handy pages left, so don't panic. */
3974	rc = VINF_SUCCESS;
3975	}
3976
3977	if (RT_SUCCESS(rc))
3978	{
3979	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3980	Assert(pVM->pgm.s.cHandyPages > 0);
3981	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3982	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3983
3984	/*
3985	* Clear the pages.
3986	*/
3987	while (iClear < pVM->pgm.s.cHandyPages)
3988	{
3989	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3990	void *pv;
3991	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3992	AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n", pPage->idPage, pPage->HCPhysGCPhys, rc));
3993	ASMMemZeroPage(pv);
3994	iClear++;
3995	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3996	}
3997	}
3998	else
3999	{
4000	uint64_t cAllocPages, cMaxPages, cBalloonPages;
4001
4002	/*
4003	* We should never get here unless there is a genuine shortage of
4004	* memory (or some internal error). Flag the error so the VM can be
4005	* suspended ASAP and the user informed. If we're totally out of
4006	* handy pages we will return failure.
4007	*/
4008	/* Report the failure. */
4009	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
4010	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
4011	rc, rcAlloc, rcSeed,
4012	pVM->pgm.s.cHandyPages,
4013	pVM->pgm.s.cAllPages,
4014	pVM->pgm.s.cPrivatePages,
4015	pVM->pgm.s.cSharedPages,
4016	pVM->pgm.s.cZeroPages));
4017
4018	if (GMMR3QueryMemoryStats(pVM, &cAllocPages, &cMaxPages, &cBalloonPages) == VINF_SUCCESS)
4019	{
4020	LogRel(("GMM: Statistics:\n"
4021	" Allocated pages: %RX64\n"
4022	" Maximum pages: %RX64\n"
4023	" Ballooned pages: %RX64\n", cAllocPages, cMaxPages, cBalloonPages));
4024	}
4025
4026	if ( rc != VERR_NO_MEMORY
4027	&& rc != VERR_LOCK_FAILED)
4028	{
4029	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
4030	{
4031	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
4032	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
4033	pVM->pgm.s.aHandyPages[i].idSharedPage));
4034	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
4035	if (idPage != NIL_GMM_PAGEID)
4036	{
4037	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4038	pRam;
4039	pRam = pRam->pNextR3)
4040	{
4041	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
4042	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4043	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
4044	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
4045	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
4046	}
4047	}
4048	}
4049	}
4050
4051	/* Set the FFs and adjust rc. */
4052	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
4053	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
4054	if ( rc == VERR_NO_MEMORY
4055	\|\| rc == VERR_LOCK_FAILED)
4056	rc = VINF_EM_NO_MEMORY;
4057	}
4058
4059	pgmUnlock(pVM);
4060	return rc;
4061	}
4062
4063
4064	/**
4065	* Frees the specified RAM page and replaces it with the ZERO page.
4066	*
4067	* This is used by ballooning, remapping MMIO2 and RAM reset.
4068	*
4069	* @param pVM Pointer to the shared VM structure.
4070	* @param pReq Pointer to the request.
4071	* @param pPage Pointer to the page structure.
4072	* @param GCPhys The guest physical address of the page, if applicable.
4073	*
4074	* @remarks The caller must own the PGM lock.
4075	*/
4076	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
4077	{
4078	/*
4079	* Assert sanity.
4080	*/
4081	Assert(PGMIsLockOwner(pVM));
4082	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
4083	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
4084	{
4085	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
4086	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
4087	}
4088
4089	if ( PGM_PAGE_IS_ZERO(pPage)
4090	\|\| PGM_PAGE_IS_BALLOONED(pPage))
4091	return VINF_SUCCESS;
4092
4093	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
4094	Log3(("pgmPhysFreePage: idPage=%#x GCPhys=%RGp pPage=%R[pgmpage]\n", idPage, GCPhys, pPage));
4095	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
4096	\|\| idPage > GMM_PAGEID_LAST
4097	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
4098	{
4099	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
4100	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
4101	}
4102
4103	/* update page count stats. */
4104	if (PGM_PAGE_IS_SHARED(pPage))
4105	pVM->pgm.s.cSharedPages--;
4106	else
4107	pVM->pgm.s.cPrivatePages--;
4108	pVM->pgm.s.cZeroPages++;
4109
4110	/* Deal with write monitored pages. */
4111	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
4112	{
4113	PGM_PAGE_SET_WRITTEN_TO(pPage);
4114	pVM->pgm.s.cWrittenToPages++;
4115	}
4116
4117	/*
4118	* pPage = ZERO page.
4119	*/
4120	PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
4121	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
4122	PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
4123	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4124	PGM_PAGE_SET_PTE_INDEX(pPage, 0);
4125	PGM_PAGE_SET_TRACKING(pPage, 0);
4126
4127	/* Flush physical page map TLB entry. */
4128	PGMPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
4129
4130	/*
4131	* Make sure it's not in the handy page array.
4132	*/
4133	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
4134	{
4135	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
4136	{
4137	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
4138	break;
4139	}
4140	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
4141	{
4142	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
4143	break;
4144	}
4145	}
4146
4147	/*
4148	* Push it onto the page array.
4149	*/
4150	uint32_t iPage = *pcPendingPages;
4151	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
4152	*pcPendingPages += 1;
4153
4154	pReq->aPages[iPage].idPage = idPage;
4155
4156	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
4157	return VINF_SUCCESS;
4158
4159	/*
4160	* Flush the pages.
4161	*/
4162	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
4163	if (RT_SUCCESS(rc))
4164	{
4165	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4166	*pcPendingPages = 0;
4167	}
4168	return rc;
4169	}
4170
4171
4172	/**
4173	* Converts a GC physical address to a HC ring-3 pointer, with some
4174	* additional checks.
4175	*
4176	* @returns VBox status code.
4177	* @retval VINF_SUCCESS on success.
4178	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
4179	* access handler of some kind.
4180	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
4181	* accesses or is odd in any way.
4182	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
4183	*
4184	* @param pVM The VM handle.
4185	* @param GCPhys The GC physical address to convert.
4186	* @param fWritable Whether write access is required.
4187	* @param ppv Where to store the pointer corresponding to GCPhys on
4188	* success.
4189	*/
4190	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
4191	{
4192	pgmLock(pVM);
4193
4194	PPGMRAMRANGE pRam;
4195	PPGMPAGE pPage;
4196	int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
4197	if (RT_SUCCESS(rc))
4198	{
4199	if (PGM_PAGE_IS_BALLOONED(pPage))
4200	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
4201	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
4202	rc = VINF_SUCCESS;
4203	else
4204	{
4205	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
4206	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
4207	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
4208	{
4209	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
4210	* in -norawr0 mode. */
4211	if (fWritable)
4212	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
4213	}
4214	else
4215	{
4216	/* Temporarily disabled physical handler(s), since the recompiler
4217	doesn't get notified when it's reset we'll have to pretend it's
4218	operating normally. */
4219	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
4220	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
4221	else
4222	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
4223	}
4224	}
4225	if (RT_SUCCESS(rc))
4226	{
4227	int rc2;
4228
4229	/* Make sure what we return is writable. */
4230	if (fWritable)
4231	switch (PGM_PAGE_GET_STATE(pPage))
4232	{
4233	case PGM_PAGE_STATE_ALLOCATED:
4234	break;
4235	case PGM_PAGE_STATE_BALLOONED:
4236	AssertFailed();
4237	break;
4238	case PGM_PAGE_STATE_ZERO:
4239	case PGM_PAGE_STATE_SHARED:
4240	if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
4241	break;
4242	case PGM_PAGE_STATE_WRITE_MONITORED:
4243	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
4244	AssertLogRelRCReturn(rc2, rc2);
4245	break;
4246	}
4247
4248	/* Get a ring-3 mapping of the address. */
4249	PPGMPAGER3MAPTLBE pTlbe;
4250	rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
4251	AssertLogRelRCReturn(rc2, rc2);
4252	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
4253	/** @todo mapping/locking hell; this isn't horribly efficient since
4254	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
4255
4256	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
4257	}
4258	else
4259	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
4260
4261	/* else: handler catching all access, no pointer returned. */
4262	}
4263	else
4264	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
4265
4266	pgmUnlock(pVM);
4267	return rc;
4268	}
4269

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source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 32963

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