VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 7732

Last change on this file since 7732 was 7731, checked in by vboxsync, 17 years ago

MMIO cleanup in progress.
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File size: 73.3 KB
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1/* $Id: PGMPhys.cpp 7731 2008-04-03 17:05:29Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM
23#include <VBox/pgm.h>
24#include <VBox/cpum.h>
25#include <VBox/iom.h>
26#include <VBox/sup.h>
27#include <VBox/mm.h>
28#include <VBox/stam.h>
29#include <VBox/rem.h>
30#include <VBox/csam.h>
31#include "PGMInternal.h"
32#include <VBox/vm.h>
33#include <VBox/dbg.h>
34#include <VBox/param.h>
35#include <VBox/err.h>
36#include <iprt/assert.h>
37#include <iprt/alloc.h>
38#include <iprt/asm.h>
39#include <VBox/log.h>
40#include <iprt/thread.h>
41#include <iprt/string.h>
42
43
44/*******************************************************************************
45* Internal Functions *
46*******************************************************************************/
47/*static - shut up warning */
48DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
49
50
51
52/*
53 * PGMR3PhysReadByte/Word/Dword
54 * PGMR3PhysWriteByte/Word/Dword
55 */
56/** @todo rename and add U64. */
57
58#define PGMPHYSFN_READNAME PGMR3PhysReadByte
59#define PGMPHYSFN_WRITENAME PGMR3PhysWriteByte
60#define PGMPHYS_DATASIZE 1
61#define PGMPHYS_DATATYPE uint8_t
62#include "PGMPhys.h"
63
64#define PGMPHYSFN_READNAME PGMR3PhysReadWord
65#define PGMPHYSFN_WRITENAME PGMR3PhysWriteWord
66#define PGMPHYS_DATASIZE 2
67#define PGMPHYS_DATATYPE uint16_t
68#include "PGMPhys.h"
69
70#define PGMPHYSFN_READNAME PGMR3PhysReadDword
71#define PGMPHYSFN_WRITENAME PGMR3PhysWriteDword
72#define PGMPHYS_DATASIZE 4
73#define PGMPHYS_DATATYPE uint32_t
74#include "PGMPhys.h"
75
76
77
78/**
79 * Links a new RAM range into the list.
80 *
81 * @param pVM Pointer to the shared VM structure.
82 * @param pNew Pointer to the new list entry.
83 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
84 */
85static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
86{
87 pgmLock(pVM);
88
89 PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
90 pNew->pNextR3 = pRam;
91 pNew->pNextR0 = pRam ? MMHyperCCToR0(pVM, pRam) : NIL_RTR0PTR;
92 pNew->pNextGC = pRam ? MMHyperCCToGC(pVM, pRam) : NIL_RTGCPTR;
93
94 if (pPrev)
95 {
96 pPrev->pNextR3 = pNew;
97 pPrev->pNextR0 = MMHyperCCToR0(pVM, pNew);
98 pPrev->pNextGC = MMHyperCCToGC(pVM, pNew);
99 }
100 else
101 {
102 pVM->pgm.s.pRamRangesR3 = pNew;
103 pVM->pgm.s.pRamRangesR0 = MMHyperCCToR0(pVM, pNew);
104 pVM->pgm.s.pRamRangesGC = MMHyperCCToGC(pVM, pNew);
105 }
106
107 pgmUnlock(pVM);
108}
109
110
111/**
112 * Unlink an existing RAM range from the list.
113 *
114 * @param pVM Pointer to the shared VM structure.
115 * @param pRam Pointer to the new list entry.
116 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
117 */
118static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
119{
120 Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
121
122 pgmLock(pVM);
123
124 PPGMRAMRANGE pNext = pRam->pNextR3;
125 if (pPrev)
126 {
127 pPrev->pNextR3 = pNext;
128 pPrev->pNextR0 = pNext ? MMHyperCCToR0(pVM, pNext) : NIL_RTR0PTR;
129 pPrev->pNextGC = pNext ? MMHyperCCToGC(pVM, pNext) : NIL_RTGCPTR;
130 }
131 else
132 {
133 Assert(pVM->pgm.s.pRamRangesR3 == pRam);
134 pVM->pgm.s.pRamRangesR3 = pNext;
135 pVM->pgm.s.pRamRangesR0 = pNext ? MMHyperCCToR0(pVM, pNext) : NIL_RTR0PTR;
136 pVM->pgm.s.pRamRangesGC = pNext ? MMHyperCCToGC(pVM, pNext) : NIL_RTGCPTR;
137 }
138
139 pgmUnlock(pVM);
140}
141
142
143/**
144 * Unlink an existing RAM range from the list.
145 *
146 * @param pVM Pointer to the shared VM structure.
147 * @param pRam Pointer to the new list entry.
148 */
149static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
150{
151 /* find prev. */
152 PPGMRAMRANGE pPrev = NULL;
153 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
154 while (pCur != pRam)
155 {
156 pPrev = pCur;
157 pCur = pCur->pNextR3;
158 }
159 AssertFatal(pCur);
160
161 pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
162}
163
164
165
166/**
167 * Sets up a range RAM.
168 *
169 * This will check for conflicting registrations, make a resource
170 * reservation for the memory (with GMM), and setup the per-page
171 * tracking structures (PGMPAGE).
172 *
173 * @returns VBox stutus code.
174 * @param pVM Pointer to the shared VM structure.
175 * @param GCPhys The physical address of the RAM.
176 * @param cb The size of the RAM.
177 * @param pszDesc The description - not copied, so, don't free or change it.
178 */
179PGMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
180{
181 /*
182 * Validate input.
183 */
184 Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
185 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
186 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
187 AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
188 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
189 AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
190 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
191 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
192
193 /*
194 * Find range location and check for conflicts.
195 * (We don't lock here because the locking by EMT is only required on update.)
196 */
197 PPGMRAMRANGE pPrev = NULL;
198 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
199 while (pRam && GCPhysLast >= pRam->GCPhys)
200 {
201 if ( GCPhys <= pRam->GCPhysLast
202 && GCPhysLast >= pRam->GCPhys)
203 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
204 GCPhys, GCPhysLast, pszDesc,
205 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
206 VERR_PGM_RAM_CONFLICT);
207
208 /* next */
209 pPrev = pRam;
210 pRam = pRam->pNextR3;
211 }
212
213 /*
214 * Register it with GMM (the API bitches).
215 */
216 const RTGCPHYS cPages = cb >> PAGE_SHIFT;
217 int rc = MMR3IncreaseBaseReservation(pVM, cPages);
218 if (RT_FAILURE(rc))
219 return rc;
220
221 /*
222 * Allocate RAM range.
223 */
224 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
225 PPGMRAMRANGE pNew;
226 rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
227 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
228
229 /*
230 * Initialize the range.
231 */
232 pNew->GCPhys = GCPhys;
233 pNew->GCPhysLast = GCPhysLast;
234 pNew->pszDesc = pszDesc;
235 pNew->cb = cb;
236 pNew->fFlags = 0;
237 pNew->pvHC = NULL;
238
239 pNew->pavHCChunkHC = NULL;
240 pNew->pavHCChunkGC = 0;
241
242#ifndef VBOX_WITH_NEW_PHYS_CODE
243 /* Allocate memory for chunk to HC ptr lookup array. */
244 rc = MMHyperAlloc(pVM, (cb >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(void *), 16, MM_TAG_PGM, (void **)&pNew->pavHCChunkHC);
245 AssertRCReturn(rc, rc);
246 pNew->pavHCChunkGC = MMHyperCCToGC(pVM, pNew->pavHCChunkHC);
247 pNew->fFlags |= MM_RAM_FLAGS_DYNAMIC_ALLOC;
248
249#endif
250 RTGCPHYS iPage = cPages;
251 while (iPage-- > 0)
252 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
253
254 /*
255 * Insert the new RAM range.
256 */
257 pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
258
259 /*
260 * Notify REM.
261 */
262#ifdef VBOX_WITH_NEW_PHYS_CODE
263 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, 0);
264#else
265 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, MM_RAM_FLAGS_DYNAMIC_ALLOC);
266#endif
267
268 return VINF_SUCCESS;
269}
270
271
272/**
273 * This is the interface IOM is using to register an MMIO region.
274 *
275 * It will check for conflicts and ensure that a RAM range structure
276 * is present before calling the PGMR3HandlerPhysicalRegister API to
277 * register the callbacks.
278 *
279 */
280PDMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
281 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
282 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
283 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC, RTGCPTR pvUserGC,
284 R3PTRTYPE(const char *) pszDesc)
285{
286
287 int rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhys + (cb - 1),
288 pfnHandlerR3, pvUserR3,
289 pfnHandlerR0, pvUserR0,
290 pfnHandlerGC, pvUserGC, pszDesc);
291 return rc;
292}
293
294
295/**
296 * This is the interface IOM is using to register an MMIO region.
297 *
298 * It will validate the MMIO region, call PGMHandlerPhysicalDeregister,
299 * and free the RAM range if one was allocated specially for this MMIO
300 * region.
301 */
302PDMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
303{
304 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
305
306 return rc;
307}
308
309
310/**
311 * Locate a MMIO2 range.
312 *
313 * @returns Pointer to the MMIO2 range.
314 * @param pVM Pointer to the shared VM structure.
315 * @param pDevIns The device instance owning the region.
316 * @param iRegion The region.
317 */
318DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
319{
320 /*
321 * Search the list.
322 */
323 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
324 if (pCur->pDevInsR3 == pDevIns)
325 return pCur;
326 return NULL;
327}
328
329
330/**
331 * Allocate and register a MMIO2 region.
332 *
333 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
334 * RAM associated with a device. It is also non-shared memory with a
335 * permanent ring-3 mapping and page backing (presently).
336 *
337 * A MMIO2 range may overlap with base memory if a lot of RAM
338 * is configured for the VM, in which case we'll drop the base
339 * memory pages. Presently we will make no attempt to preserve
340 * anything that happens to be present in the base memory that
341 * is replaced, this is of course incorrectly but it's too much
342 * effort.
343 *
344 * @returns VBox status code.
345 * @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
346 * @retval VERR_ALREADY_EXISTS if the region already exists.
347 *
348 * @param pVM Pointer to the shared VM structure.
349 * @param pDevIns The device instance owning the region.
350 * @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
351 * this number has to be the number of that region. Otherwise
352 * it can be any number safe UINT8_MAX.
353 * @param cb The size of the region. Must be page aligned.
354 * @param ppv Where to store the pointer to the ring-3 mapping of the memory.
355 * @param pszDesc The description.
356 */
357PDMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, void **ppv, const char *pszDesc)
358{
359 /*
360 * Validate input.
361 */
362 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
363 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
364 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
365 AssertPtrReturn(ppv, VERR_INVALID_POINTER);
366 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
367 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
368 AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
369 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
370 AssertReturn(cb, VERR_INVALID_PARAMETER);
371
372 const uint32_t cPages = cb >> PAGE_SHIFT;
373 AssertLogRelReturn((RTGCPHYS)cPages << PAGE_SHIFT == cb, VERR_INVALID_PARAMETER);
374 AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
375
376 /*
377 * Try reserve and allocate the backing memory first as this is what is
378 * most likely to fail.
379 */
380 int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
381 if (RT_FAILURE(rc))
382 return rc;
383
384 void *pvPages;
385 PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
386 if (RT_SUCCESS(rc))
387 rc = SUPPageAllocLockedEx(cPages, &pvPages, paPages);
388 if (RT_SUCCESS(rc))
389 {
390 /*
391 * Create the MMIO2 range record for it.
392 */
393 const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
394 PPGMMMIO2RANGE pNew;
395 rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
396 AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
397 if (RT_SUCCESS(rc))
398 {
399 pNew->pDevInsR3 = pDevIns;
400 pNew->pvR3 = pvPages;
401 //pNew->pNext = NULL;
402 //pNew->fMapped = false;
403 //pNew->fOverlapping = false;
404 pNew->iRegion = iRegion;
405 pNew->RamRange.GCPhys = NIL_RTGCPHYS;
406 pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
407 pNew->RamRange.pszDesc = pszDesc;
408 pNew->RamRange.cb = cb;
409 //pNew->RamRange.fFlags = 0;
410
411 pNew->RamRange.pvHC = pvPages; ///@todo remove this
412 pNew->RamRange.pavHCChunkHC = NULL; ///@todo remove this
413 pNew->RamRange.pavHCChunkGC = 0; ///@todo remove this
414
415 uint32_t iPage = cPages;
416 while (iPage-- > 0)
417 {
418 PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
419 paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
420 PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
421 }
422
423 /*
424 * Link it into the list.
425 * Since there is no particular order, just push it.
426 */
427 pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
428 pVM->pgm.s.pMmio2RangesR3 = pNew;
429
430 *ppv = pvPages;
431 RTMemTmpFree(paPages);
432 return VINF_SUCCESS;
433 }
434
435 SUPPageFreeLocked(pvPages, cPages);
436 }
437 RTMemTmpFree(paPages);
438 MMR3AdjustFixedReservation(pVM, -cPages, pszDesc);
439 return rc;
440}
441
442
443/**
444 * Deregisters and frees a MMIO2 region.
445 *
446 * Any physical (and virtual) access handlers registered for the region must
447 * be deregistered before calling this function.
448 *
449 * @returns VBox status code.
450 * @param pVM Pointer to the shared VM structure.
451 * @param pDevIns The device instance owning the region.
452 * @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
453 */
454PDMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
455{
456 /*
457 * Validate input.
458 */
459 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
460 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
461 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
462
463 int rc = VINF_SUCCESS;
464 unsigned cFound = 0;
465 PPGMMMIO2RANGE pPrev = NULL;
466 PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
467 while (pCur)
468 {
469 if ( pCur->pDevInsR3 == pDevIns
470 && ( iRegion == UINT32_MAX
471 || pCur->iRegion == iRegion))
472 {
473 cFound++;
474
475 /*
476 * Unmap it if it's mapped.
477 */
478 if (pCur->fMapped)
479 {
480 int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
481 AssertRC(rc2);
482 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
483 rc = rc2;
484 }
485
486 /*
487 * Unlink it
488 */
489 PPGMMMIO2RANGE pNext = pCur->pNextR3;
490 if (pPrev)
491 pPrev->pNextR3 = pNext;
492 else
493 pVM->pgm.s.pMmio2RangesR3 = pNext;
494 pCur->pNextR3 = NULL;
495
496 /*
497 * Free the memory.
498 */
499 int rc2 = SUPPageFreeLocked(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
500 AssertRC(rc2);
501 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
502 rc = rc2;
503
504 rc2 = MMR3AdjustFixedReservation(pVM, -(pCur->RamRange.cb >> PAGE_SHIFT), pCur->RamRange.pszDesc);
505 AssertRC(rc2);
506 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
507 rc = rc2;
508
509 /* we're leaking hyper memory here if done at runtime. */
510 Assert( VMR3GetState(pVM) == VMSTATE_OFF
511 || VMR3GetState(pVM) == VMSTATE_DESTROYING
512 || VMR3GetState(pVM) == VMSTATE_TERMINATED);
513 /*rc = MMHyperFree(pVM, pCur);
514 AssertRCReturn(rc, rc); - not safe, see the alloc call. */
515
516 /* next */
517 pCur = pNext;
518 }
519 else
520 {
521 pPrev = pCur;
522 pCur = pCur->pNextR3;
523 }
524 }
525
526 return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
527}
528
529
530/**
531 * Maps a MMIO2 region.
532 *
533 * This is done when a guest / the bios / state loading changes the
534 * PCI config. The replacing of base memory has the same restrictions
535 * as during registration, of course.
536 *
537 * @returns VBox status code.
538 *
539 * @param pVM Pointer to the shared VM structure.
540 * @param pDevIns The
541 */
542PDMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
543{
544 /*
545 * Validate input
546 */
547 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
548 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
549 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
550 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
551 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
552 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
553
554 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
555 AssertReturn(pCur, VERR_NOT_FOUND);
556 AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
557 Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
558 Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
559
560 const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
561 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
562
563 /*
564 * Find our location in the ram range list, checking for
565 * restriction we don't bother implementing yet (partially overlapping).
566 */
567 bool fRamExists = false;
568 PPGMRAMRANGE pRamPrev = NULL;
569 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
570 while (pRam && GCPhysLast >= pRam->GCPhys)
571 {
572 if ( GCPhys <= pRam->GCPhysLast
573 && GCPhysLast >= pRam->GCPhys)
574 {
575 /* completely within? */
576 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
577 && GCPhysLast <= pRam->GCPhysLast,
578 ("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
579 GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
580 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
581 VERR_PGM_RAM_CONFLICT);
582 fRamExists = true;
583 break;
584 }
585
586 /* next */
587 pRamPrev = pRam;
588 pRam = pRam->pNextR3;
589 }
590 if (fRamExists)
591 {
592 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
593 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
594 while (cPagesLeft-- > 0)
595 {
596 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
597 ("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
598 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
599 VERR_PGM_RAM_CONFLICT);
600 pPage++;
601 }
602 }
603 Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
604 GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
605
606 /*
607 * Make the changes.
608 */
609 pgmLock(pVM);
610
611 pCur->RamRange.GCPhys = GCPhys;
612 pCur->RamRange.GCPhysLast = GCPhysLast;
613 pCur->fMapped = true;
614 pCur->fOverlapping = fRamExists;
615
616 if (fRamExists)
617 {
618 /* replace the pages, freeing all present RAM pages. */
619 PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
620 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
621 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
622 while (cPagesLeft-- > 0)
623 {
624 pgmPhysFreePage(pVM, pPageDst, GCPhys);
625
626 RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
627 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
628 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
629 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
630
631 GCPhys += PAGE_SIZE;
632 pPageSrc++;
633 pPageDst++;
634 }
635 }
636 else
637 {
638 /* link in the ram range */
639 pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
640 REMR3NotifyPhysRamRegister(pVM, GCPhys, pCur->RamRange.cb, 0);
641 }
642
643 pgmUnlock(pVM);
644
645 return VINF_SUCCESS;
646}
647
648
649/**
650 * Unmaps a MMIO2 region.
651 *
652 * This is done when a guest / the bios / state loading changes the
653 * PCI config. The replacing of base memory has the same restrictions
654 * as during registration, of course.
655 */
656PDMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
657{
658 /*
659 * Validate input
660 */
661 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
662 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
663 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
664 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
665 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
666 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
667
668 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
669 AssertReturn(pCur, VERR_NOT_FOUND);
670 AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
671 AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
672 Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
673
674 Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
675 pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
676
677 /*
678 * Unmap it.
679 */
680 pgmLock(pVM);
681
682 if (pCur->fOverlapping)
683 {
684 /* Restore the RAM pages we've replaced. */
685 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
686 while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
687 pRam = pRam->pNextR3;
688
689 RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
690 Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
691 PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
692 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
693 while (cPagesLeft-- > 0)
694 {
695 PGM_PAGE_SET_HCPHYS(pPageDst, pVM->pgm.s.HCPhysZeroPg);
696 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
697 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
698
699 pPageDst++;
700 }
701 }
702 else
703 {
704 REMR3NotifyPhysReserve(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb);
705 pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
706 }
707
708 pCur->RamRange.GCPhys = NIL_RTGCPHYS;
709 pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
710 pCur->fOverlapping = false;
711 pCur->fMapped = false;
712
713 pgmUnlock(pVM);
714
715 return VINF_SUCCESS;
716}
717
718
719/**
720 * Checks if the given address is an MMIO2 base address or not.
721 *
722 * @returns true/false accordingly.
723 * @param pVM Pointer to the shared VM structure.
724 * @param pDevIns The owner of the memory, optional.
725 * @param GCPhys The address to check.
726 */
727PDMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
728{
729 /*
730 * Validate input
731 */
732 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
733 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
734 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
735 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
736 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
737
738 /*
739 * Search the list.
740 */
741 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
742 if (pCur->RamRange.GCPhys == GCPhys)
743 {
744 Assert(pCur->fMapped);
745 return true;
746 }
747 return false;
748}
749
750
751/**
752 * Gets the HC physical address of a page in the MMIO2 region.
753 *
754 * This is API is intended for MMHyper and shouldn't be called
755 * by anyone else...
756 *
757 * @returns VBox status code.
758 * @param pVM Pointer to the shared VM structure.
759 * @param pDevIns The owner of the memory, optional.
760 * @param iRegion The region.
761 * @param off The page expressed an offset into the MMIO2 region.
762 * @param pHCPhys Where to store the result.
763 */
764PDMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
765{
766 /*
767 * Validate input
768 */
769 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
770 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
771 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
772
773 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
774 AssertReturn(pCur, VERR_NOT_FOUND);
775 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
776
777 PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
778 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
779 return VINF_SUCCESS;
780}
781
782
783/**
784 * Registers a ROM image.
785 *
786 * Shadowed ROM images requires double the amount of backing memory, so,
787 * don't use that unless you have to. Shadowing of ROM images is process
788 * where we can select where the reads go and where the writes go. On real
789 * hardware the chipset provides means to configure this. We provide
790 * PGMR3PhysProtectROM() for this purpose.
791 *
792 * A read-only copy of the ROM image will always be kept around while we
793 * will allocate RAM pages for the changes on demand (unless all memory
794 * is configured to be preallocated).
795 *
796 * @returns VBox status.
797 * @param pVM VM Handle.
798 * @param pDevIns The device instance owning the ROM.
799 * @param GCPhys First physical address in the range.
800 * Must be page aligned!
801 * @param cbRange The size of the range (in bytes).
802 * Must be page aligned!
803 * @param pvBinary Pointer to the binary data backing the ROM image.
804 * This must be exactly \a cbRange in size.
805 * @param fFlags Mask of flags. PGMPHYS_ROM_FLAG_SHADOWED
806 * and/or PGMPHYS_ROM_FLAG_PERMANENT_BINARY.
807 * @param pszDesc Pointer to description string. This must not be freed.
808 *
809 * @remark There is no way to remove the rom, automatically on device cleanup or
810 * manually from the device yet. This isn't difficult in any way, it's
811 * just not something we expect to be necessary for a while.
812 */
813PGMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
814 const void *pvBinary, uint32_t fFlags, const char *pszDesc)
815{
816 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
817 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
818
819 /*
820 * Validate input.
821 */
822 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
823 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
824 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
825 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
826 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
827 AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
828 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
829 AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAG_SHADOWED | PGMPHYS_ROM_FLAG_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
830 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
831
832 const uint32_t cPages = cb >> PAGE_SHIFT;
833
834 /*
835 * Find the ROM location in the ROM list first.
836 */
837 PPGMROMRANGE pRomPrev = NULL;
838 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
839 while (pRom && GCPhysLast >= pRom->GCPhys)
840 {
841 if ( GCPhys <= pRom->GCPhysLast
842 && GCPhysLast >= pRom->GCPhys)
843 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
844 GCPhys, GCPhysLast, pszDesc,
845 pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
846 VERR_PGM_RAM_CONFLICT);
847 /* next */
848 pRomPrev = pRom;
849 pRom = pRom->pNextR3;
850 }
851
852 /*
853 * Find the RAM location and check for conflicts.
854 *
855 * Conflict detection is a bit different than for RAM
856 * registration since a ROM can be located within a RAM
857 * range. So, what we have to check for is other memory
858 * types (other than RAM that is) and that we don't span
859 * more than one RAM range (layz).
860 */
861 bool fRamExists = false;
862 PPGMRAMRANGE pRamPrev = NULL;
863 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
864 while (pRam && GCPhysLast >= pRam->GCPhys)
865 {
866 if ( GCPhys <= pRam->GCPhysLast
867 && GCPhysLast >= pRam->GCPhys)
868 {
869 /* completely within? */
870 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
871 && GCPhysLast <= pRam->GCPhysLast,
872 ("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
873 GCPhys, GCPhysLast, pszDesc,
874 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
875 VERR_PGM_RAM_CONFLICT);
876 fRamExists = true;
877 break;
878 }
879
880 /* next */
881 pRamPrev = pRam;
882 pRam = pRam->pNextR3;
883 }
884 if (fRamExists)
885 {
886 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
887 uint32_t cPagesLeft = cPages;
888 while (cPagesLeft-- > 0)
889 {
890 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
891 ("%RGp isn't a RAM page (%d) - registering %RGp-%RGp (%s).\n",
892 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pszDesc),
893 VERR_PGM_RAM_CONFLICT);
894 Assert(PGM_PAGE_IS_ZERO(pPage));
895 pPage++;
896 }
897 }
898
899 /*
900 * Update the base memory reservation if necessary.
901 */
902 uint32_t cExtraBaseCost = fRamExists ? cPages : 0;
903 if (fFlags & PGMPHYS_ROM_FLAG_SHADOWED)
904 cExtraBaseCost += cPages;
905 if (cExtraBaseCost)
906 {
907 int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
908 if (RT_FAILURE(rc))
909 return rc;
910 }
911
912 /*
913 * Allocate memory for the virgin copy of the RAM.
914 */
915 PGMMALLOCATEPAGESREQ pReq;
916 int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
917 AssertRCReturn(rc, rc);
918
919 for (uint32_t iPage = 0; iPage < cPages; iPage++)
920 {
921 pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
922 pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
923 pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
924 }
925
926 pgmLock(pVM);
927 rc = GMMR3AllocatePagesPerform(pVM, pReq);
928 pgmUnlock(pVM);
929 if (RT_FAILURE(rc))
930 {
931 GMMR3AllocatePagesCleanup(pReq);
932 return rc;
933 }
934
935 /*
936 * Allocate the new ROM range and RAM range (if necessary).
937 */
938 PPGMROMRANGE pRomNew;
939 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
940 if (RT_SUCCESS(rc))
941 {
942 PPGMRAMRANGE pRamNew = NULL;
943 if (!fRamExists)
944 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
945 if (RT_SUCCESS(rc))
946 {
947 pgmLock(pVM);
948
949 /*
950 * Initialize and insert the RAM range (if required).
951 */
952 PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
953 if (!fRamExists)
954 {
955 pRamNew->GCPhys = GCPhys;
956 pRamNew->GCPhysLast = GCPhysLast;
957 pRamNew->pszDesc = pszDesc;
958 pRamNew->cb = cb;
959 pRamNew->fFlags = 0;
960 pRamNew->pvHC = NULL;
961
962 PPGMPAGE pPage = &pRamNew->aPages[0];
963 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
964 {
965 PGM_PAGE_INIT(pPage,
966 pReq->aPages[iPage].HCPhysGCPhys,
967 pReq->aPages[iPage].idPage,
968 PGMPAGETYPE_ROM,
969 PGM_PAGE_STATE_ALLOCATED);
970
971 pRomPage->Virgin = *pPage;
972 }
973
974 pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
975 }
976 else
977 {
978 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
979 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
980 {
981 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
982 PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
983 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
984 PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
985
986 pRomPage->Virgin = *pPage;
987 }
988
989 pRamNew = pRam;
990 }
991 pgmUnlock(pVM);
992
993
994 /*
995 * Register the write access handler for the range (PGMROMPROT_READ_ROM_WRITE_IGNORE).
996 */
997 rc = PGMR3HandlerPhysicalRegister(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhys, GCPhysLast,
998#if 0 /** @todo we actually need a ring-3 write handler here for shadowed ROMs, so hack REM! */
999 pgmR3PhysRomWriteHandler, pRomNew,
1000#else
1001 NULL, NULL,
1002#endif
1003 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
1004 NULL, "pgmPhysRomWriteHandler", MMHyperCCToGC(pVM, pRomNew), pszDesc);
1005 if (RT_SUCCESS(rc))
1006 {
1007 pgmLock(pVM);
1008
1009 /*
1010 * Copy the image over to the virgin pages.
1011 * This must be done after linking in the RAM range.
1012 */
1013 PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
1014 for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
1015 {
1016 void *pvDstPage;
1017 PPGMPAGEMAP pMapIgnored;
1018 rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pMapIgnored, &pvDstPage);
1019 if (RT_FAILURE(rc))
1020 {
1021 VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
1022 break;
1023 }
1024 memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
1025 }
1026 if (RT_SUCCESS(rc))
1027 {
1028 /*
1029 * Initialize the ROM range.
1030 * Note that the Virgin member of the pages has already been initialized above.
1031 */
1032 pRomNew->GCPhys = GCPhys;
1033 pRomNew->GCPhysLast = GCPhysLast;
1034 pRomNew->cb = cb;
1035 pRomNew->fFlags = fFlags;
1036 pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAG_PERMANENT_BINARY ? pvBinary : NULL;
1037 pRomNew->pszDesc = pszDesc;
1038
1039 for (unsigned iPage = 0; iPage < cPages; iPage++)
1040 {
1041 PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
1042 pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
1043 PGM_PAGE_INIT_ZERO_REAL(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
1044 }
1045
1046 /*
1047 * Insert the ROM range, tell REM and return successfully.
1048 */
1049 pRomNew->pNextR3 = pRom;
1050 pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
1051 pRomNew->pNextGC = pRom ? MMHyperCCToGC(pVM, pRom) : NIL_RTGCPTR;
1052
1053 if (pRomPrev)
1054 {
1055 pRomPrev->pNextR3 = pRomNew;
1056 pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
1057 pRomPrev->pNextGC = MMHyperCCToGC(pVM, pRomNew);
1058 }
1059 else
1060 {
1061 pVM->pgm.s.pRomRangesR3 = pRomNew;
1062 pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
1063 pVM->pgm.s.pRomRangesGC = MMHyperCCToGC(pVM, pRomNew);
1064 }
1065
1066 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false); /** @todo fix shadowing and REM. */
1067
1068 GMMR3AllocatePagesCleanup(pReq);
1069 pgmUnlock(pVM);
1070 return VINF_SUCCESS;
1071 }
1072
1073 /* bail out */
1074
1075 pgmUnlock(pVM);
1076 int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1077 AssertRC(rc2);
1078 pgmLock(pVM);
1079 }
1080
1081 pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
1082 if (pRamNew)
1083 MMHyperFree(pVM, pRamNew);
1084 }
1085 MMHyperFree(pVM, pRomNew);
1086 }
1087
1088 /** @todo Purge the mapping cache or something... */
1089 GMMR3FreeAllocatedPages(pVM, pReq);
1090 GMMR3AllocatePagesCleanup(pReq);
1091 pgmUnlock(pVM);
1092 return rc;
1093}
1094
1095
1096/**
1097 * \#PF Handler callback for ROM write accesses.
1098 *
1099 * @returns VINF_SUCCESS if the handler have carried out the operation.
1100 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1101 * @param pVM VM Handle.
1102 * @param GCPhys The physical address the guest is writing to.
1103 * @param pvPhys The HC mapping of that address.
1104 * @param pvBuf What the guest is reading/writing.
1105 * @param cbBuf How much it's reading/writing.
1106 * @param enmAccessType The access type.
1107 * @param pvUser User argument.
1108 */
1109/*static - shut up warning */
1110 DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1111{
1112 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
1113 const uint32_t iPage = GCPhys - pRom->GCPhys;
1114 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
1115 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
1116 switch (pRomPage->enmProt)
1117 {
1118 /*
1119 * Ignore.
1120 */
1121 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
1122 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
1123 return VINF_SUCCESS;
1124
1125 /*
1126 * Write to the ram page.
1127 */
1128 case PGMROMPROT_READ_ROM_WRITE_RAM:
1129 case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
1130 {
1131 /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
1132 Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
1133
1134 /*
1135 * Take the lock, do lazy allocation, map the page and copy the data.
1136 *
1137 * Note that we have to bypass the mapping TLB since it works on
1138 * guest physical addresses and entering the shadow page would
1139 * kind of screw things up...
1140 */
1141 int rc = pgmLock(pVM);
1142 AssertRC(rc);
1143
1144 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pRomPage->Shadow) != PGM_PAGE_STATE_ALLOCATED))
1145 {
1146 rc = pgmPhysPageMakeWritable(pVM, &pRomPage->Shadow, GCPhys);
1147 if (RT_FAILURE(rc))
1148 {
1149 pgmUnlock(pVM);
1150 return rc;
1151 }
1152 }
1153
1154 void *pvDstPage;
1155 PPGMPAGEMAP pMapIgnored;
1156 rc = pgmPhysPageMap(pVM, &pRomPage->Shadow, GCPhys & X86_PTE_PG_MASK, &pMapIgnored, &pvDstPage);
1157 if (RT_SUCCESS(rc))
1158 memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
1159
1160 pgmUnlock(pVM);
1161 return rc;
1162 }
1163
1164 default:
1165 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
1166 pRom->aPages[iPage].enmProt, iPage, GCPhys),
1167 VERR_INTERNAL_ERROR);
1168 }
1169}
1170
1171
1172
1173/**
1174 * Called by PGMR3Reset to reset the shadow, switch to the virgin,
1175 * and verify that the virgin part is untouched.
1176 *
1177 * This is done after the normal memory has been cleared.
1178 *
1179 * @param pVM The VM handle.
1180 */
1181int pgmR3PhysRomReset(PVM pVM)
1182{
1183 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
1184 {
1185 const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
1186
1187 if (pRom->fFlags & PGMPHYS_ROM_FLAG_SHADOWED)
1188 {
1189 /*
1190 * Reset the physical handler.
1191 */
1192 int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
1193 AssertRCReturn(rc, rc);
1194
1195 /*
1196 * What we do with the shadow pages depends on the memory
1197 * preallocation option. If not enabled, we'll just throw
1198 * out all the dirty pages and replace them by the zero page.
1199 */
1200 if (1)///@todo !pVM->pgm.f.fRamPreAlloc)
1201 {
1202 /* Count dirty shadow pages. */
1203 uint32_t cDirty = 0;
1204 uint32_t iPage = cPages;
1205 while (iPage-- > 0)
1206 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1207 cDirty++;
1208 if (cDirty)
1209 {
1210 /* Free the dirty pages. */
1211 PGMMFREEPAGESREQ pReq;
1212 rc = GMMR3FreePagesPrepare(pVM, &pReq, cDirty, GMMACCOUNT_BASE);
1213 AssertRCReturn(rc, rc);
1214
1215 uint32_t iReqPage = 0;
1216 for (iPage = 0; iPage < cPages; iPage++)
1217 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1218 {
1219 pReq->aPages[iReqPage].idPage = PGM_PAGE_GET_PAGEID(&pRom->aPages[iPage].Shadow);
1220 iReqPage++;
1221 }
1222
1223 rc = GMMR3FreePagesPerform(pVM, pReq);
1224 GMMR3FreePagesCleanup(pReq);
1225 AssertRCReturn(rc, rc);
1226
1227 /* setup the zero page. */
1228 for (iPage = 0; iPage < cPages; iPage++)
1229 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1230 PGM_PAGE_INIT_ZERO_REAL(&pRom->aPages[iPage].Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
1231 }
1232 }
1233 else
1234 {
1235 /* clear all the pages. */
1236 pgmLock(pVM);
1237 for (uint32_t iPage = 0; iPage < cPages; iPage++)
1238 {
1239 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
1240 rc = pgmPhysPageMakeWritable(pVM, &pRom->aPages[iPage].Shadow, GCPhys);
1241 if (RT_FAILURE(rc))
1242 break;
1243
1244 void *pvDstPage;
1245 PPGMPAGEMAP pMapIgnored;
1246 rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pMapIgnored, &pvDstPage);
1247 if (RT_FAILURE(rc))
1248 break;
1249 memset(pvDstPage, 0, PAGE_SIZE);
1250 }
1251 pgmUnlock(pVM);
1252 AssertRCReturn(rc, rc);
1253 }
1254 }
1255
1256#ifdef VBOX_STRICT
1257 /*
1258 * Verify that the virgin page is unchanged if possible.
1259 */
1260 if (pRom->pvOriginal)
1261 {
1262 uint8_t const *pbSrcPage = (uint8_t const *)pRom->pvOriginal;
1263 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
1264 {
1265 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
1266 PPGMPAGEMAP pMapIgnored;
1267 void *pvDstPage;
1268 int rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pMapIgnored, &pvDstPage);
1269 if (RT_FAILURE(rc))
1270 break;
1271 if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
1272 LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
1273 GCPhys, pRom->pszDesc));
1274 }
1275 }
1276#endif
1277 }
1278
1279 return VINF_SUCCESS;
1280}
1281
1282
1283/**
1284 * Change the shadowing of a range of ROM pages.
1285 *
1286 * This is intended for implementing chipset specific memory registers
1287 * and will not be very strict about the input. It will silently ignore
1288 * any pages that are not the part of a shadowed ROM.
1289 *
1290 * @returns VBox status code.
1291 * @param pVM Pointer to the shared VM structure.
1292 * @param GCPhys Where to start. Page aligned.
1293 * @param cb How much to change. Page aligned.
1294 * @param enmProt The new ROM protection.
1295 */
1296PGMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
1297{
1298 /*
1299 * Check input
1300 */
1301 if (!cb)
1302 return VINF_SUCCESS;
1303 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1304 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1305 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1306 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1307 AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
1308
1309 /*
1310 * Process the request.
1311 */
1312 bool fFlushedPool = false;
1313 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
1314 if ( GCPhys <= pRom->GCPhysLast
1315 && GCPhysLast >= pRom->GCPhys)
1316 {
1317 /*
1318 * Iterate the relevant pages and the ncessary make changes.
1319 */
1320 bool fChanges = false;
1321 uint32_t const cPages = pRom->GCPhysLast > GCPhysLast
1322 ? pRom->cb >> PAGE_SHIFT
1323 : (GCPhysLast - pRom->GCPhys) >> PAGE_SHIFT;
1324 for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
1325 iPage < cPages;
1326 iPage++)
1327 {
1328 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
1329 if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
1330 {
1331 fChanges = true;
1332
1333 /* flush the page pool first so we don't leave any usage references dangling. */
1334 if (!fFlushedPool)
1335 {
1336 pgmPoolFlushAll(pVM);
1337 fFlushedPool = true;
1338 }
1339
1340 PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
1341 PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
1342 PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
1343
1344 *pOld = *pRamPage;
1345 *pRamPage = *pNew;
1346 /** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
1347 }
1348 }
1349
1350 /*
1351 * Reset the access handler if we made changes, no need
1352 * to optimize this.
1353 */
1354 if (fChanges)
1355 {
1356 int rc = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
1357 AssertRCReturn(rc, rc);
1358 }
1359
1360 /* Advance - cb isn't updated. */
1361 GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
1362 }
1363
1364 return VINF_SUCCESS;
1365}
1366
1367
1368/**
1369 * Interface that the MMR3RamRegister(), MMR3RomRegister() and MMIO handler
1370 * registration APIs calls to inform PGM about memory registrations.
1371 *
1372 * It registers the physical memory range with PGM. MM is responsible
1373 * for the toplevel things - allocation and locking - while PGM is taking
1374 * care of all the details and implements the physical address space virtualization.
1375 *
1376 * @returns VBox status.
1377 * @param pVM The VM handle.
1378 * @param pvRam HC virtual address of the RAM range. (page aligned)
1379 * @param GCPhys GC physical address of the RAM range. (page aligned)
1380 * @param cb Size of the RAM range. (page aligned)
1381 * @param fFlags Flags, MM_RAM_*.
1382 * @param paPages Pointer an array of physical page descriptors.
1383 * @param pszDesc Description string.
1384 */
1385PGMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc)
1386{
1387 /*
1388 * Validate input.
1389 * (Not so important because callers are only MMR3PhysRegister()
1390 * and PGMR3HandlerPhysicalRegisterEx(), but anyway...)
1391 */
1392 Log(("PGMR3PhysRegister %08X %x bytes flags %x %s\n", GCPhys, cb, fFlags, pszDesc));
1393
1394 Assert((fFlags & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_DYNAMIC_ALLOC)) || paPages);
1395 /*Assert(!(fFlags & MM_RAM_FLAGS_RESERVED) || !paPages);*/
1396 Assert((fFlags == (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO)) || (fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) || pvRam);
1397 /*Assert(!(fFlags & MM_RAM_FLAGS_RESERVED) || !pvRam);*/
1398 Assert(!(fFlags & ~0xfff));
1399 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
1400 Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
1401 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2 | MM_RAM_FLAGS_DYNAMIC_ALLOC)));
1402 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
1403 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1404 if (GCPhysLast < GCPhys)
1405 {
1406 AssertMsgFailed(("The range wraps! GCPhys=%VGp cb=%#x\n", GCPhys, cb));
1407 return VERR_INVALID_PARAMETER;
1408 }
1409
1410 /*
1411 * Find range location and check for conflicts.
1412 */
1413 PPGMRAMRANGE pPrev = NULL;
1414 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
1415 while (pCur)
1416 {
1417 if (GCPhys <= pCur->GCPhysLast && GCPhysLast >= pCur->GCPhys)
1418 {
1419 AssertMsgFailed(("Conflict! This cannot happen!\n"));
1420 return VERR_PGM_RAM_CONFLICT;
1421 }
1422 if (GCPhysLast < pCur->GCPhys)
1423 break;
1424
1425 /* next */
1426 pPrev = pCur;
1427 pCur = pCur->pNextR3;
1428 }
1429
1430 /*
1431 * Allocate RAM range.
1432 * Small ranges are allocated from the heap, big ones have separate mappings.
1433 */
1434 size_t cbRam = RT_OFFSETOF(PGMRAMRANGE, aPages[cb >> PAGE_SHIFT]);
1435 PPGMRAMRANGE pNew;
1436 RTGCPTR GCPtrNew;
1437 int rc = VERR_NO_MEMORY;
1438 if (cbRam > PAGE_SIZE / 2)
1439 { /* large */
1440 cbRam = RT_ALIGN_Z(cbRam, PAGE_SIZE);
1441 rc = SUPPageAlloc(cbRam >> PAGE_SHIFT, (void **)&pNew);
1442 if (VBOX_SUCCESS(rc))
1443 {
1444 rc = MMR3HyperMapHCRam(pVM, pNew, cbRam, true, pszDesc, &GCPtrNew);
1445 if (VBOX_SUCCESS(rc))
1446 {
1447 Assert(MMHyperHC2GC(pVM, pNew) == GCPtrNew);
1448 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1449 }
1450 else
1451 {
1452 AssertMsgFailed(("MMR3HyperMapHCRam(,,%#x,,,) -> %Vrc\n", cbRam, rc));
1453 SUPPageFree(pNew, cbRam >> PAGE_SHIFT);
1454 }
1455 }
1456 else
1457 AssertMsgFailed(("SUPPageAlloc(%#x,,) -> %Vrc\n", cbRam >> PAGE_SHIFT, rc));
1458
1459 }
1460/** @todo Make VGA and VMMDev register their memory at init time before the hma size is fixated. */
1461 if (RT_FAILURE(rc))
1462 { /* small + fallback (vga) */
1463 rc = MMHyperAlloc(pVM, cbRam, 16, MM_TAG_PGM, (void **)&pNew);
1464 if (VBOX_SUCCESS(rc))
1465 GCPtrNew = MMHyperHC2GC(pVM, pNew);
1466 else
1467 AssertMsgFailed(("MMHyperAlloc(,%#x,,,) -> %Vrc\n", cbRam, cb));
1468 }
1469 if (VBOX_SUCCESS(rc))
1470 {
1471 /*
1472 * Initialize the range.
1473 */
1474 pNew->pvHC = pvRam;
1475 pNew->GCPhys = GCPhys;
1476 pNew->GCPhysLast = GCPhysLast;
1477 pNew->cb = cb;
1478 pNew->fFlags = fFlags;
1479 pNew->pavHCChunkHC = NULL;
1480 pNew->pavHCChunkGC = 0;
1481
1482 unsigned iPage = cb >> PAGE_SHIFT;
1483 if (paPages)
1484 {
1485 while (iPage-- > 0)
1486 {
1487 PGM_PAGE_INIT(&pNew->aPages[iPage], paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
1488 fFlags & MM_RAM_FLAGS_MMIO2 ? PGMPAGETYPE_MMIO2 : PGMPAGETYPE_RAM,
1489 PGM_PAGE_STATE_ALLOCATED);
1490 pNew->aPages[iPage].HCPhys |= fFlags; /** @todo PAGE FLAGS*/
1491 }
1492 }
1493 else if (fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1494 {
1495 /* Allocate memory for chunk to HC ptr lookup array. */
1496 rc = MMHyperAlloc(pVM, (cb >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(void *), 16, MM_TAG_PGM, (void **)&pNew->pavHCChunkHC);
1497 AssertMsgReturn(rc == VINF_SUCCESS, ("MMHyperAlloc(,%#x,,,) -> %Vrc\n", cbRam, cb), rc);
1498
1499 pNew->pavHCChunkGC = MMHyperHC2GC(pVM, pNew->pavHCChunkHC);
1500 Assert(pNew->pavHCChunkGC);
1501
1502 /* Physical memory will be allocated on demand. */
1503 while (iPage-- > 0)
1504 {
1505 PGM_PAGE_INIT(&pNew->aPages[iPage], 0, NIL_GMM_PAGEID, PGMPAGETYPE_RAM, PGM_PAGE_STATE_ZERO);
1506 pNew->aPages[iPage].HCPhys = fFlags; /** @todo PAGE FLAGS */
1507 }
1508 }
1509 else
1510 {
1511 Assert(fFlags == (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO));
1512 RTHCPHYS HCPhysDummyPage = MMR3PageDummyHCPhys(pVM);
1513 while (iPage-- > 0)
1514 {
1515 PGM_PAGE_INIT(&pNew->aPages[iPage], HCPhysDummyPage, NIL_GMM_PAGEID, PGMPAGETYPE_MMIO, PGM_PAGE_STATE_ZERO);
1516 pNew->aPages[iPage].HCPhys |= fFlags; /** @todo PAGE FLAGS*/
1517 }
1518 }
1519
1520 /*
1521 * Insert the new RAM range.
1522 */
1523 pgmLock(pVM);
1524 pNew->pNextR3 = pCur;
1525 pNew->pNextR0 = pCur ? MMHyperCCToR0(pVM, pCur) : NIL_RTR0PTR;
1526 pNew->pNextGC = pCur ? MMHyperCCToGC(pVM, pCur) : NIL_RTGCPTR;
1527 if (pPrev)
1528 {
1529 pPrev->pNextR3 = pNew;
1530 pPrev->pNextR0 = MMHyperCCToR0(pVM, pNew);
1531 pPrev->pNextGC = GCPtrNew;
1532 }
1533 else
1534 {
1535 pVM->pgm.s.pRamRangesR3 = pNew;
1536 pVM->pgm.s.pRamRangesR0 = MMHyperCCToR0(pVM, pNew);
1537 pVM->pgm.s.pRamRangesGC = GCPtrNew;
1538 }
1539 pgmUnlock(pVM);
1540 }
1541 return rc;
1542}
1543
1544#ifndef VBOX_WITH_NEW_PHYS_CODE
1545
1546/**
1547 * Register a chunk of a the physical memory range with PGM. MM is responsible
1548 * for the toplevel things - allocation and locking - while PGM is taking
1549 * care of all the details and implements the physical address space virtualization.
1550 *
1551 *
1552 * @returns VBox status.
1553 * @param pVM The VM handle.
1554 * @param pvRam HC virtual address of the RAM range. (page aligned)
1555 * @param GCPhys GC physical address of the RAM range. (page aligned)
1556 * @param cb Size of the RAM range. (page aligned)
1557 * @param fFlags Flags, MM_RAM_*.
1558 * @param paPages Pointer an array of physical page descriptors.
1559 * @param pszDesc Description string.
1560 */
1561PGMR3DECL(int) PGMR3PhysRegisterChunk(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc)
1562{
1563 NOREF(pszDesc);
1564
1565 /*
1566 * Validate input.
1567 * (Not so important because callers are only MMR3PhysRegister()
1568 * and PGMR3HandlerPhysicalRegisterEx(), but anyway...)
1569 */
1570 Log(("PGMR3PhysRegisterChunk %08X %x bytes flags %x %s\n", GCPhys, cb, fFlags, pszDesc));
1571
1572 Assert(paPages);
1573 Assert(pvRam);
1574 Assert(!(fFlags & ~0xfff));
1575 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
1576 Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
1577 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2 | MM_RAM_FLAGS_DYNAMIC_ALLOC)));
1578 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
1579 Assert(VM_IS_EMT(pVM));
1580 Assert(!(GCPhys & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
1581 Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
1582
1583 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1584 if (GCPhysLast < GCPhys)
1585 {
1586 AssertMsgFailed(("The range wraps! GCPhys=%VGp cb=%#x\n", GCPhys, cb));
1587 return VERR_INVALID_PARAMETER;
1588 }
1589
1590 /*
1591 * Find existing range location.
1592 */
1593 PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1594 while (pRam)
1595 {
1596 RTGCPHYS off = GCPhys - pRam->GCPhys;
1597 if ( off < pRam->cb
1598 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
1599 break;
1600
1601 pRam = CTXALLSUFF(pRam->pNext);
1602 }
1603 AssertReturn(pRam, VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS);
1604
1605 unsigned off = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1606 unsigned iPage = cb >> PAGE_SHIFT;
1607 if (paPages)
1608 {
1609 while (iPage-- > 0)
1610 pRam->aPages[off + iPage].HCPhys = (paPages[iPage].Phys & X86_PTE_PAE_PG_MASK) | fFlags; /** @todo PAGE FLAGS */
1611 }
1612 off >>= (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1613 pRam->pavHCChunkHC[off] = pvRam;
1614
1615 /* Notify the recompiler. */
1616 REMR3NotifyPhysRamChunkRegister(pVM, GCPhys, PGM_DYNAMIC_CHUNK_SIZE, (RTHCUINTPTR)pvRam, fFlags);
1617
1618 return VINF_SUCCESS;
1619}
1620
1621
1622/**
1623 * Allocate missing physical pages for an existing guest RAM range.
1624 *
1625 * @returns VBox status.
1626 * @param pVM The VM handle.
1627 * @param GCPhys GC physical address of the RAM range. (page aligned)
1628 */
1629PGMR3DECL(int) PGM3PhysGrowRange(PVM pVM, PCRTGCPHYS pGCPhys)
1630{
1631 RTGCPHYS GCPhys = *pGCPhys;
1632
1633 /*
1634 * Walk range list.
1635 */
1636 pgmLock(pVM);
1637
1638 PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1639 while (pRam)
1640 {
1641 RTGCPHYS off = GCPhys - pRam->GCPhys;
1642 if ( off < pRam->cb
1643 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
1644 {
1645 bool fRangeExists = false;
1646 unsigned off = (GCPhys - pRam->GCPhys) >> PGM_DYNAMIC_CHUNK_SHIFT;
1647
1648 /** @note A request made from another thread may end up in EMT after somebody else has already allocated the range. */
1649 if (pRam->pavHCChunkHC[off])
1650 fRangeExists = true;
1651
1652 pgmUnlock(pVM);
1653 if (fRangeExists)
1654 return VINF_SUCCESS;
1655 return pgmr3PhysGrowRange(pVM, GCPhys);
1656 }
1657
1658 pRam = CTXALLSUFF(pRam->pNext);
1659 }
1660 pgmUnlock(pVM);
1661 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
1662}
1663
1664
1665/**
1666 * Allocate missing physical pages for an existing guest RAM range.
1667 *
1668 * @returns VBox status.
1669 * @param pVM The VM handle.
1670 * @param pRamRange RAM range
1671 * @param GCPhys GC physical address of the RAM range. (page aligned)
1672 */
1673int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys)
1674{
1675 void *pvRam;
1676 int rc;
1677
1678 /* We must execute this function in the EMT thread, otherwise we'll run into problems. */
1679 if (!VM_IS_EMT(pVM))
1680 {
1681 PVMREQ pReq;
1682 const RTGCPHYS GCPhysParam = GCPhys;
1683
1684 AssertMsg(!PDMCritSectIsOwner(&pVM->pgm.s.CritSect), ("We own the PGM lock -> deadlock danger!!\n"));
1685
1686 rc = VMR3ReqCall(pVM, &pReq, RT_INDEFINITE_WAIT, (PFNRT)PGM3PhysGrowRange, 2, pVM, &GCPhysParam);
1687 if (VBOX_SUCCESS(rc))
1688 {
1689 rc = pReq->iStatus;
1690 VMR3ReqFree(pReq);
1691 }
1692 return rc;
1693 }
1694
1695 /* Round down to chunk boundary */
1696 GCPhys = GCPhys & PGM_DYNAMIC_CHUNK_BASE_MASK;
1697
1698 STAM_COUNTER_INC(&pVM->pgm.s.StatDynRamGrow);
1699 STAM_COUNTER_ADD(&pVM->pgm.s.StatDynRamTotal, PGM_DYNAMIC_CHUNK_SIZE/(1024*1024));
1700
1701 Log(("pgmr3PhysGrowRange: allocate chunk of size 0x%X at %VGp\n", PGM_DYNAMIC_CHUNK_SIZE, GCPhys));
1702
1703 unsigned cPages = PGM_DYNAMIC_CHUNK_SIZE >> PAGE_SHIFT;
1704
1705 for (;;)
1706 {
1707 rc = SUPPageAlloc(cPages, &pvRam);
1708 if (VBOX_SUCCESS(rc))
1709 {
1710
1711 rc = MMR3PhysRegisterEx(pVM, pvRam, GCPhys, PGM_DYNAMIC_CHUNK_SIZE, 0, MM_PHYS_TYPE_DYNALLOC_CHUNK, "Main Memory");
1712 if (VBOX_SUCCESS(rc))
1713 return rc;
1714
1715 SUPPageFree(pvRam, cPages);
1716 }
1717
1718 VMSTATE enmVMState = VMR3GetState(pVM);
1719 if (enmVMState != VMSTATE_RUNNING)
1720 {
1721 AssertMsgFailed(("Out of memory while trying to allocate a guest RAM chunk at %VGp!\n", GCPhys));
1722 LogRel(("PGM: Out of memory while trying to allocate a guest RAM chunk at %VGp (VMstate=%s)!\n", GCPhys, VMR3GetStateName(enmVMState)));
1723 return rc;
1724 }
1725
1726 LogRel(("pgmr3PhysGrowRange: out of memory. pause until the user resumes execution.\n"));
1727
1728 /* Pause first, then inform Main. */
1729 rc = VMR3SuspendNoSave(pVM);
1730 AssertRC(rc);
1731
1732 VMSetRuntimeError(pVM, false, "HostMemoryLow", "Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM.");
1733
1734 /* Wait for resume event; will only return in that case. If the VM is stopped, the EMT thread will be destroyed. */
1735 rc = VMR3WaitForResume(pVM);
1736
1737 /* Retry */
1738 LogRel(("pgmr3PhysGrowRange: VM execution resumed -> retry.\n"));
1739 }
1740}
1741
1742#endif /* !VBOX_WITH_NEW_PHYS_CODE */
1743
1744
1745/**
1746 * Interface MMR3RomRegister() and MMR3PhysReserve calls to update the
1747 * flags of existing RAM ranges.
1748 *
1749 * @returns VBox status.
1750 * @param pVM The VM handle.
1751 * @param GCPhys GC physical address of the RAM range. (page aligned)
1752 * @param cb Size of the RAM range. (page aligned)
1753 * @param fFlags The Or flags, MM_RAM_* \#defines.
1754 * @param fMask The and mask for the flags.
1755 */
1756PGMR3DECL(int) PGMR3PhysSetFlags(PVM pVM, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, unsigned fMask)
1757{
1758 Log(("PGMR3PhysSetFlags %08X %x %x %x\n", GCPhys, cb, fFlags, fMask));
1759
1760 /*
1761 * Validate input.
1762 * (Not so important because caller is always MMR3RomRegister() and MMR3PhysReserve(), but anyway...)
1763 */
1764 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2)));
1765 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
1766 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
1767 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1768 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1769
1770 /*
1771 * Lookup the range.
1772 */
1773 PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1774 while (pRam && GCPhys > pRam->GCPhysLast)
1775 pRam = CTXALLSUFF(pRam->pNext);
1776 if ( !pRam
1777 || GCPhys > pRam->GCPhysLast
1778 || GCPhysLast < pRam->GCPhys)
1779 {
1780 AssertMsgFailed(("No RAM range for %VGp-%VGp\n", GCPhys, GCPhysLast));
1781 return VERR_INVALID_PARAMETER;
1782 }
1783
1784 /*
1785 * Update the requested flags.
1786 */
1787 RTHCPHYS fFullMask = ~(RTHCPHYS)(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2)
1788 | fMask;
1789 unsigned iPageEnd = (GCPhysLast - pRam->GCPhys + 1) >> PAGE_SHIFT;
1790 unsigned iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1791 for ( ; iPage < iPageEnd; iPage++)
1792 pRam->aPages[iPage].HCPhys = (pRam->aPages[iPage].HCPhys & fFullMask) | fFlags; /** @todo PAGE FLAGS */
1793
1794 return VINF_SUCCESS;
1795}
1796
1797
1798/**
1799 * Sets the Address Gate 20 state.
1800 *
1801 * @param pVM VM handle.
1802 * @param fEnable True if the gate should be enabled.
1803 * False if the gate should be disabled.
1804 */
1805PGMDECL(void) PGMR3PhysSetA20(PVM pVM, bool fEnable)
1806{
1807 LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVM->pgm.s.fA20Enabled));
1808 if (pVM->pgm.s.fA20Enabled != (RTUINT)fEnable)
1809 {
1810 pVM->pgm.s.fA20Enabled = fEnable;
1811 pVM->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
1812 REMR3A20Set(pVM, fEnable);
1813 }
1814}
1815
1816
1817/**
1818 * Tree enumeration callback for dealing with age rollover.
1819 * It will perform a simple compression of the current age.
1820 */
1821static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
1822{
1823 /* Age compression - ASSUMES iNow == 4. */
1824 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
1825 if (pChunk->iAge >= UINT32_C(0xffffff00))
1826 pChunk->iAge = 3;
1827 else if (pChunk->iAge >= UINT32_C(0xfffff000))
1828 pChunk->iAge = 2;
1829 else if (pChunk->iAge)
1830 pChunk->iAge = 1;
1831 else /* iAge = 0 */
1832 pChunk->iAge = 4;
1833
1834 /* reinsert */
1835 PVM pVM = (PVM)pvUser;
1836 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
1837 pChunk->AgeCore.Key = pChunk->iAge;
1838 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
1839 return 0;
1840}
1841
1842
1843/**
1844 * Tree enumeration callback that updates the chunks that have
1845 * been used since the last
1846 */
1847static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
1848{
1849 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
1850 if (!pChunk->iAge)
1851 {
1852 PVM pVM = (PVM)pvUser;
1853 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
1854 pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
1855 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
1856 }
1857
1858 return 0;
1859}
1860
1861
1862/**
1863 * Performs ageing of the ring-3 chunk mappings.
1864 *
1865 * @param pVM The VM handle.
1866 */
1867PGMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
1868{
1869 pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
1870 pVM->pgm.s.ChunkR3Map.iNow++;
1871 if (pVM->pgm.s.ChunkR3Map.iNow == 0)
1872 {
1873 pVM->pgm.s.ChunkR3Map.iNow = 4;
1874 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
1875 }
1876 else
1877 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingCallback, pVM);
1878}
1879
1880
1881/**
1882 * The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
1883 */
1884typedef struct PGMR3PHYSCHUNKUNMAPCB
1885{
1886 PVM pVM; /**< The VM handle. */
1887 PPGMCHUNKR3MAP pChunk; /**< The chunk to unmap. */
1888} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
1889
1890
1891/**
1892 * Callback used to find the mapping that's been unused for
1893 * the longest time.
1894 */
1895static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
1896{
1897 do
1898 {
1899 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
1900 if ( pChunk->iAge
1901 && !pChunk->cRefs)
1902 {
1903 /*
1904 * Check that it's not in any of the TLBs.
1905 */
1906 PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
1907 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1908 if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
1909 {
1910 pChunk = NULL;
1911 break;
1912 }
1913 if (pChunk)
1914 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
1915 if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
1916 {
1917 pChunk = NULL;
1918 break;
1919 }
1920 if (pChunk)
1921 {
1922 ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
1923 return 1; /* done */
1924 }
1925 }
1926
1927 /* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
1928 pNode = pNode->pList;
1929 } while (pNode);
1930 return 0;
1931}
1932
1933
1934/**
1935 * Finds a good candidate for unmapping when the ring-3 mapping cache is full.
1936 *
1937 * The candidate will not be part of any TLBs, so no need to flush
1938 * anything afterwards.
1939 *
1940 * @returns Chunk id.
1941 * @param pVM The VM handle.
1942 */
1943static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
1944{
1945 /*
1946 * Do tree ageing first?
1947 */
1948 if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
1949 PGMR3PhysChunkAgeing(pVM);
1950
1951 /*
1952 * Enumerate the age tree starting with the left most node.
1953 */
1954 PGMR3PHYSCHUNKUNMAPCB Args;
1955 Args.pVM = pVM;
1956 Args.pChunk = NULL;
1957 if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /*fFromLeft*/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
1958 return Args.pChunk->Core.Key;
1959 return INT32_MAX;
1960}
1961
1962
1963/**
1964 * Maps the given chunk into the ring-3 mapping cache.
1965 *
1966 * This will call ring-0.
1967 *
1968 * @returns VBox status code.
1969 * @param pVM The VM handle.
1970 * @param idChunk The chunk in question.
1971 * @param ppChunk Where to store the chunk tracking structure.
1972 *
1973 * @remarks Called from within the PGM critical section.
1974 */
1975int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
1976{
1977 int rc;
1978 /*
1979 * Allocate a new tracking structure first.
1980 */
1981#if 0 /* for later when we've got a separate mapping method for ring-0. */
1982 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
1983 AssertReturn(pChunk, VERR_NO_MEMORY);
1984#else
1985 PPGMCHUNKR3MAP pChunk;
1986 rc = MMHyperAlloc(pVM, sizeof(*pChunk), 0, MM_TAG_PGM_CHUNK_MAPPING, (void **)&pChunk);
1987 AssertRCReturn(rc, rc);
1988#endif
1989 pChunk->Core.Key = idChunk;
1990 pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
1991 pChunk->iAge = 0;
1992 pChunk->cRefs = 0;
1993 pChunk->cPermRefs = 0;
1994 pChunk->pv = NULL;
1995
1996 /*
1997 * Request the ring-0 part to map the chunk in question and if
1998 * necessary unmap another one to make space in the mapping cache.
1999 */
2000 GMMMAPUNMAPCHUNKREQ Req;
2001 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2002 Req.Hdr.cbReq = sizeof(Req);
2003 Req.pvR3 = NULL;
2004 Req.idChunkMap = idChunk;
2005 Req.idChunkUnmap = INT32_MAX;
2006 if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
2007 Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
2008 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
2009 if (VBOX_SUCCESS(rc))
2010 {
2011 /*
2012 * Update the tree.
2013 */
2014 /* insert the new one. */
2015 AssertPtr(Req.pvR3);
2016 pChunk->pv = Req.pvR3;
2017 bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
2018 AssertRelease(fRc);
2019 pVM->pgm.s.ChunkR3Map.c++;
2020
2021 fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2022 AssertRelease(fRc);
2023
2024 /* remove the unmapped one. */
2025 if (Req.idChunkUnmap != INT32_MAX)
2026 {
2027 PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
2028 AssertRelease(pUnmappedChunk);
2029 pUnmappedChunk->pv = NULL;
2030 pUnmappedChunk->Core.Key = UINT32_MAX;
2031#if 0 /* for later when we've got a separate mapping method for ring-0. */
2032 MMR3HeapFree(pUnmappedChunk);
2033#else
2034 MMHyperFree(pVM, pUnmappedChunk);
2035#endif
2036 pVM->pgm.s.ChunkR3Map.c--;
2037 }
2038 }
2039 else
2040 {
2041 AssertRC(rc);
2042#if 0 /* for later when we've got a separate mapping method for ring-0. */
2043 MMR3HeapFree(pChunk);
2044#else
2045 MMHyperFree(pVM, pChunk);
2046#endif
2047 pChunk = NULL;
2048 }
2049
2050 *ppChunk = pChunk;
2051 return rc;
2052}
2053
2054
2055/**
2056 * For VMMCALLHOST_PGM_MAP_CHUNK, considered internal.
2057 *
2058 * @returns see pgmR3PhysChunkMap.
2059 * @param pVM The VM handle.
2060 * @param idChunk The chunk to map.
2061 */
2062PDMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
2063{
2064 PPGMCHUNKR3MAP pChunk;
2065 return pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
2066}
2067
2068
2069/**
2070 * Invalidates the TLB for the ring-3 mapping cache.
2071 *
2072 * @param pVM The VM handle.
2073 */
2074PGMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
2075{
2076 pgmLock(pVM);
2077 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2078 {
2079 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
2080 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
2081 }
2082 pgmUnlock(pVM);
2083}
2084
2085
2086/**
2087 * Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES.
2088 *
2089 * @returns The following VBox status codes.
2090 * @retval VINF_SUCCESS on success. FF cleared.
2091 * @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in this case.
2092 *
2093 * @param pVM The VM handle.
2094 */
2095PDMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
2096{
2097 pgmLock(pVM);
2098 int rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
2099 if (rc == VERR_GMM_SEED_ME)
2100 {
2101 void *pvChunk;
2102 rc = SUPPageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
2103 if (VBOX_SUCCESS(rc))
2104 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
2105 if (VBOX_FAILURE(rc))
2106 {
2107 LogRel(("PGM: GMM Seeding failed, rc=%Vrc\n", rc));
2108 rc = VINF_EM_NO_MEMORY;
2109 }
2110 }
2111 pgmUnlock(pVM);
2112 Assert(rc == VINF_SUCCESS || rc == VINF_EM_NO_MEMORY);
2113 return rc;
2114}
2115
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