PGMSavedState.cpp@ 26638

Last change on this file since 26638 was 26165, checked in by vboxsync, 15 years ago
PDM: s/szDeviceName/szName/g - PDMDEVREG & PDMUSBREG.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 112.8 KB

Line
1	/* $Id: PGMSavedState.cpp 26165 2010-02-02 19:50:31Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/pgm.h>
28	#include <VBox/stam.h>
29	#include <VBox/ssm.h>
30	#include <VBox/pdmdrv.h>
31	#include <VBox/pdmdev.h>
32	#include "PGMInternal.h"
33	#include <VBox/vm.h>
34	#include "PGMInline.h"
35
36	#include <VBox/param.h>
37	#include <VBox/err.h>
38
39	#include <iprt/asm.h>
40	#include <iprt/assert.h>
41	#include <iprt/crc32.h>
42	#include <iprt/mem.h>
43	#include <iprt/sha.h>
44	#include <iprt/string.h>
45	#include <iprt/thread.h>
46
47
48	/*******************************************************************************
49	* Defined Constants And Macros *
50	*******************************************************************************/
51	/** Saved state data unit version.
52	* @todo remove the guest mappings from the saved state at next version change! */
53	#define PGM_SAVED_STATE_VERSION 11
54	/** Saved state data unit version used during 3.1 development, misses the RAM
55	* config. */
56	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
57	/** Saved state data unit version for 3.0 (pre teleportation). */
58	#define PGM_SAVED_STATE_VERSION_3_0_0 9
59	/** Saved state data unit version for 2.2.2 and later. */
60	#define PGM_SAVED_STATE_VERSION_2_2_2 8
61	/** Saved state data unit version for 2.2.0. */
62	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
63	/** Saved state data unit version. */
64	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
65
66
67	/** @name Sparse state record types
68	* @{ */
69	/** Zero page. No data. */
70	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
71	/** Raw page. */
72	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
73	/** Raw MMIO2 page. */
74	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
75	/** Zero MMIO2 page. */
76	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
77	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
78	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
79	/** Raw shadowed ROM page. The protection (8-bit) preceeds the raw bits. */
80	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
81	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
82	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
83	/** ROM protection (8-bit). */
84	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
85	/** The last record type. */
86	#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
87	/** End marker. */
88	#define PGM_STATE_REC_END UINT8_C(0xff)
89	/** Flag indicating that the data is preceeded by the page address.
90	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
91	* range ID and a 32-bit page index.
92	*/
93	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
94	/** @} */
95
96	/** The CRC-32 for a zero page. */
97	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
98	/** The CRC-32 for a zero half page. */
99	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
100
101
102	/*******************************************************************************
103	* Structures and Typedefs *
104	*******************************************************************************/
105	/** For loading old saved states. (pre-smp) */
106	typedef struct
107	{
108	/** If set no conflict checks are required. (boolean) */
109	bool fMappingsFixed;
110	/** Size of fixed mapping */
111	uint32_t cbMappingFixed;
112	/** Base address (GC) of fixed mapping */
113	RTGCPTR GCPtrMappingFixed;
114	/** A20 gate mask.
115	* Our current approach to A20 emulation is to let REM do it and don't bother
116	* anywhere else. The interesting Guests will be operating with it enabled anyway.
117	* But whould need arrise, we'll subject physical addresses to this mask. */
118	RTGCPHYS GCPhysA20Mask;
119	/** A20 gate state - boolean! */
120	bool fA20Enabled;
121	/** The guest paging mode. */
122	PGMMODE enmGuestMode;
123	} PGMOLD;
124
125
126	/*******************************************************************************
127	* Global Variables *
128	*******************************************************************************/
129	/** PGM fields to save/load. */
130	static const SSMFIELD s_aPGMFields[] =
131	{
132	SSMFIELD_ENTRY( PGM, fMappingsFixed),
133	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
134	SSMFIELD_ENTRY( PGM, cbMappingFixed),
135	SSMFIELD_ENTRY_TERM()
136	};
137
138	static const SSMFIELD s_aPGMCpuFields[] =
139	{
140	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
141	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
142	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
143	SSMFIELD_ENTRY_TERM()
144	};
145
146	static const SSMFIELD s_aPGMFields_Old[] =
147	{
148	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
149	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
150	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
151	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
152	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
153	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
154	SSMFIELD_ENTRY_TERM()
155	};
156
157
158	/**
159	* Find the ROM tracking structure for the given page.
160	*
161	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
162	* that it's a ROM page.
163	* @param pVM The VM handle.
164	* @param GCPhys The address of the ROM page.
165	*/
166	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
167	{
168	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
169	pRomRange;
170	pRomRange = pRomRange->CTX_SUFF(pNext))
171	{
172	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
173	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
174	return &pRomRange->aPages[off >> PAGE_SHIFT];
175	}
176	return NULL;
177	}
178
179
180	/**
181	* Prepares the ROM pages for a live save.
182	*
183	* @returns VBox status code.
184	* @param pVM The VM handle.
185	*/
186	static int pgmR3PrepRomPages(PVM pVM)
187	{
188	/*
189	* Initialize the live save tracking in the ROM page descriptors.
190	*/
191	pgmLock(pVM);
192	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
193	{
194	PPGMRAMRANGE pRamHint = NULL;;
195	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
196
197	for (uint32_t iPage = 0; iPage < cPages; iPage++)
198	{
199	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
200	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
201	pRom->aPages[iPage].LiveSave.fDirty = true;
202	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
203	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
204	{
205	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
206	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
207	else
208	{
209	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
210	PPGMPAGE pPage;
211	int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
212	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
213	if (RT_SUCCESS(rc))
214	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage);
215	else
216	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
217	}
218	}
219	}
220
221	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
222	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
223	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
224	}
225	pgmUnlock(pVM);
226
227	return VINF_SUCCESS;
228	}
229
230
231	/**
232	* Assigns IDs to the ROM ranges and saves them.
233	*
234	* @returns VBox status code.
235	* @param pVM The VM handle.
236	* @param pSSM Saved state handle.
237	*/
238	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
239	{
240	pgmLock(pVM);
241	uint8_t id = 1;
242	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
243	{
244	pRom->idSavedState = id;
245	SSMR3PutU8(pSSM, id);
246	SSMR3PutStrZ(pSSM, ""); /* device name */
247	SSMR3PutU32(pSSM, 0); /* device instance */
248	SSMR3PutU8(pSSM, 0); /* region */
249	SSMR3PutStrZ(pSSM, pRom->pszDesc);
250	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
251	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
252	if (RT_FAILURE(rc))
253	break;
254	}
255	pgmUnlock(pVM);
256	return SSMR3PutU8(pSSM, UINT8_MAX);
257	}
258
259
260	/**
261	* Loads the ROM range ID assignments.
262	*
263	* @returns VBox status code.
264	*
265	* @param pVM The VM handle.
266	* @param pSSM The saved state handle.
267	*/
268	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
269	{
270	Assert(PGMIsLockOwner(pVM));
271
272	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
273	pRom->idSavedState = UINT8_MAX;
274
275	for (;;)
276	{
277	/*
278	* Read the data.
279	*/
280	uint8_t id;
281	int rc = SSMR3GetU8(pSSM, &id);
282	if (RT_FAILURE(rc))
283	return rc;
284	if (id == UINT8_MAX)
285	{
286	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
287	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX, ("%s\n", pRom->pszDesc));
288	return VINF_SUCCESS; /* the end */
289	}
290	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
291
292	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
293	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
294	AssertLogRelRCReturn(rc, rc);
295
296	uint32_t uInstance;
297	SSMR3GetU32(pSSM, &uInstance);
298	uint8_t iRegion;
299	SSMR3GetU8(pSSM, &iRegion);
300
301	char szDesc[64];
302	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
303	AssertLogRelRCReturn(rc, rc);
304
305	RTGCPHYS GCPhys;
306	SSMR3GetGCPhys(pSSM, &GCPhys);
307	RTGCPHYS cb;
308	rc = SSMR3GetGCPhys(pSSM, &cb);
309	if (RT_FAILURE(rc))
310	return rc;
311	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
312	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
313
314	/*
315	* Locate a matching ROM range.
316	*/
317	AssertLogRelMsgReturn( uInstance == 0
318	&& iRegion == 0
319	&& szDevName[0] == '\0',
320	("GCPhys=%RGp %s\n", GCPhys, szDesc),
321	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
322	PPGMROMRANGE pRom;
323	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
324	{
325	if ( pRom->idSavedState == UINT8_MAX
326	&& !strcmp(pRom->pszDesc, szDesc))
327	{
328	pRom->idSavedState = id;
329	break;
330	}
331	}
332	if (!pRom)
333	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
334	} /* forever */
335	}
336
337
338	/**
339	* Scan ROM pages.
340	*
341	* @param pVM The VM handle.
342	*/
343	static void pgmR3ScanRomPages(PVM pVM)
344	{
345	/*
346	* The shadow ROMs.
347	*/
348	pgmLock(pVM);
349	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
350	{
351	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
352	{
353	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
354	for (uint32_t iPage = 0; iPage < cPages; iPage++)
355	{
356	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
357	if (pRomPage->LiveSave.fWrittenTo)
358	{
359	pRomPage->LiveSave.fWrittenTo = false;
360	if (!pRomPage->LiveSave.fDirty)
361	{
362	pRomPage->LiveSave.fDirty = true;
363	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
364	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
365	}
366	pRomPage->LiveSave.fDirtiedRecently = true;
367	}
368	else
369	pRomPage->LiveSave.fDirtiedRecently = false;
370	}
371	}
372	}
373	pgmUnlock(pVM);
374	}
375
376
377	/**
378	* Takes care of the virgin ROM pages in the first pass.
379	*
380	* This is an attempt at simplifying the handling of ROM pages a little bit.
381	* This ASSUMES that no new ROM ranges will be added and that they won't be
382	* relinked in any way.
383	*
384	* @param pVM The VM handle.
385	* @param pSSM The SSM handle.
386	* @param fLiveSave Whether we're in a live save or not.
387	*/
388	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
389	{
390	pgmLock(pVM);
391	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
392	{
393	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
394	for (uint32_t iPage = 0; iPage < cPages; iPage++)
395	{
396	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
397	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
398
399	/* Get the virgin page descriptor. */
400	PPGMPAGE pPage;
401	if (PGMROMPROT_IS_ROM(enmProt))
402	pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
403	else
404	pPage = &pRom->aPages[iPage].Virgin;
405
406	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
407	int rc = VINF_SUCCESS;
408	char abPage[PAGE_SIZE];
409	if (!PGM_PAGE_IS_ZERO(pPage))
410	{
411	void const *pvPage;
412	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
413	if (RT_SUCCESS(rc))
414	memcpy(abPage, pvPage, PAGE_SIZE);
415	}
416	else
417	ASMMemZeroPage(abPage);
418	pgmUnlock(pVM);
419	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
420
421	/* Save it. */
422	if (iPage > 0)
423	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
424	else
425	{
426	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
427	SSMR3PutU8(pSSM, pRom->idSavedState);
428	SSMR3PutU32(pSSM, iPage);
429	}
430	SSMR3PutU8(pSSM, (uint8_t)enmProt);
431	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
432	if (RT_FAILURE(rc))
433	return rc;
434
435	/* Update state. */
436	pgmLock(pVM);
437	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
438	if (fLiveSave)
439	{
440	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
441	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
442	pVM->pgm.s.LiveSave.cSavedPages++;
443	}
444	}
445	}
446	pgmUnlock(pVM);
447	return VINF_SUCCESS;
448	}
449
450
451	/**
452	* Saves dirty pages in the shadowed ROM ranges.
453	*
454	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
455	*
456	* @returns VBox status code.
457	* @param pVM The VM handle.
458	* @param pSSM The SSM handle.
459	* @param fLiveSave Whether it's a live save or not.
460	* @param fFinalPass Whether this is the final pass or not.
461	*/
462	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
463	{
464	/*
465	* The Shadowed ROMs.
466	*
467	* ASSUMES that the ROM ranges are fixed.
468	* ASSUMES that all the ROM ranges are mapped.
469	*/
470	pgmLock(pVM);
471	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
472	{
473	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
474	{
475	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
476	uint32_t iPrevPage = cPages;
477	for (uint32_t iPage = 0; iPage < cPages; iPage++)
478	{
479	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
480	if ( !fLiveSave
481	\|\| ( pRomPage->LiveSave.fDirty
482	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
483	&& !pRomPage->LiveSave.fWrittenTo)
484	\|\| fFinalPass
485	)
486	)
487	)
488	{
489	uint8_t abPage[PAGE_SIZE];
490	PGMROMPROT enmProt = pRomPage->enmProt;
491	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
492	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
493	bool fZero = PGM_PAGE_IS_ZERO(pPage);
494	int rc = VINF_SUCCESS;
495	if (!fZero)
496	{
497	void const *pvPage;
498	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
499	if (RT_SUCCESS(rc))
500	memcpy(abPage, pvPage, PAGE_SIZE);
501	}
502	if (fLiveSave && RT_SUCCESS(rc))
503	{
504	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
505	pRomPage->LiveSave.fDirty = false;
506	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
507	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
508	pVM->pgm.s.LiveSave.cSavedPages++;
509	}
510	pgmUnlock(pVM);
511	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
512
513	if (iPage - 1U == iPrevPage && iPage > 0)
514	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
515	else
516	{
517	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
518	SSMR3PutU8(pSSM, pRom->idSavedState);
519	SSMR3PutU32(pSSM, iPage);
520	}
521	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
522	if (!fZero)
523	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
524	if (RT_FAILURE(rc))
525	return rc;
526
527	pgmLock(pVM);
528	iPrevPage = iPage;
529	}
530	/*
531	* In the final pass, make sure the protection is in sync.
532	*/
533	else if ( fFinalPass
534	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
535	{
536	PGMROMPROT enmProt = pRomPage->enmProt;
537	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
538	pgmUnlock(pVM);
539
540	if (iPage - 1U == iPrevPage && iPage > 0)
541	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
542	else
543	{
544	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
545	SSMR3PutU8(pSSM, pRom->idSavedState);
546	SSMR3PutU32(pSSM, iPage);
547	}
548	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
549	if (RT_FAILURE(rc))
550	return rc;
551
552	pgmLock(pVM);
553	iPrevPage = iPage;
554	}
555	}
556	}
557	}
558	pgmUnlock(pVM);
559	return VINF_SUCCESS;
560	}
561
562
563	/**
564	* Cleans up ROM pages after a live save.
565	*
566	* @param pVM The VM handle.
567	*/
568	static void pgmR3DoneRomPages(PVM pVM)
569	{
570	NOREF(pVM);
571	}
572
573
574	/**
575	* Prepares the MMIO2 pages for a live save.
576	*
577	* @returns VBox status code.
578	* @param pVM The VM handle.
579	*/
580	static int pgmR3PrepMmio2Pages(PVM pVM)
581	{
582	/*
583	* Initialize the live save tracking in the MMIO2 ranges.
584	* ASSUME nothing changes here.
585	*/
586	pgmLock(pVM);
587	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
588	{
589	uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
590	pgmUnlock(pVM);
591
592	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
593	if (!paLSPages)
594	return VERR_NO_MEMORY;
595	for (uint32_t iPage = 0; iPage < cPages; iPage++)
596	{
597	/* Initialize it as a dirty zero page. */
598	paLSPages[iPage].fDirty = true;
599	paLSPages[iPage].cUnchangedScans = 0;
600	paLSPages[iPage].fZero = true;
601	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
602	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
603	}
604
605	pgmLock(pVM);
606	pMmio2->paLSPages = paLSPages;
607	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
608	}
609	pgmUnlock(pVM);
610	return VINF_SUCCESS;
611	}
612
613
614	/**
615	* Assigns IDs to the MMIO2 ranges and saves them.
616	*
617	* @returns VBox status code.
618	* @param pVM The VM handle.
619	* @param pSSM Saved state handle.
620	*/
621	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
622	{
623	pgmLock(pVM);
624	uint8_t id = 1;
625	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
626	{
627	pMmio2->idSavedState = id;
628	SSMR3PutU8(pSSM, id);
629	SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pReg->szName);
630	SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
631	SSMR3PutU8(pSSM, pMmio2->iRegion);
632	SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
633	int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
634	if (RT_FAILURE(rc))
635	break;
636	}
637	pgmUnlock(pVM);
638	return SSMR3PutU8(pSSM, UINT8_MAX);
639	}
640
641
642	/**
643	* Loads the MMIO2 range ID assignments.
644	*
645	* @returns VBox status code.
646	*
647	* @param pVM The VM handle.
648	* @param pSSM The saved state handle.
649	*/
650	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
651	{
652	Assert(PGMIsLockOwner(pVM));
653
654	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
655	pMmio2->idSavedState = UINT8_MAX;
656
657	for (;;)
658	{
659	/*
660	* Read the data.
661	*/
662	uint8_t id;
663	int rc = SSMR3GetU8(pSSM, &id);
664	if (RT_FAILURE(rc))
665	return rc;
666	if (id == UINT8_MAX)
667	{
668	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
669	AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
670	return VINF_SUCCESS; /* the end */
671	}
672	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
673
674	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
675	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
676	AssertLogRelRCReturn(rc, rc);
677
678	uint32_t uInstance;
679	SSMR3GetU32(pSSM, &uInstance);
680	uint8_t iRegion;
681	SSMR3GetU8(pSSM, &iRegion);
682
683	char szDesc[64];
684	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
685	AssertLogRelRCReturn(rc, rc);
686
687	RTGCPHYS cb;
688	rc = SSMR3GetGCPhys(pSSM, &cb);
689	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
690
691	/*
692	* Locate a matching MMIO2 range.
693	*/
694	PPGMMMIO2RANGE pMmio2;
695	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
696	{
697	if ( pMmio2->idSavedState == UINT8_MAX
698	&& pMmio2->iRegion == iRegion
699	&& pMmio2->pDevInsR3->iInstance == uInstance
700	&& !strcmp(pMmio2->pDevInsR3->pReg->szName, szDevName))
701	{
702	pMmio2->idSavedState = id;
703	break;
704	}
705	}
706	if (!pMmio2)
707	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
708	szDesc, szDevName, uInstance, iRegion);
709
710	/*
711	* Validate the configuration, the size of the MMIO2 region should be
712	* the same.
713	*/
714	if (cb != pMmio2->RamRange.cb)
715	{
716	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
717	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
718	if (cb > pMmio2->RamRange.cb) /* bad idea? */
719	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
720	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
721	}
722	} /* forever */
723	}
724
725
726	/**
727	* Scans one MMIO2 page.
728	*
729	* @returns True if changed, false if unchanged.
730	*
731	* @param pVM The VM handle
732	* @param pbPage The page bits.
733	* @param pLSPage The live save tracking structure for the page.
734	*
735	*/
736	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
737	{
738	/*
739	* Special handling of zero pages.
740	*/
741	bool const fZero = pLSPage->fZero;
742	if (fZero)
743	{
744	if (ASMMemIsZeroPage(pbPage))
745	{
746	/* Not modified. */
747	if (pLSPage->fDirty)
748	pLSPage->cUnchangedScans++;
749	return false;
750	}
751
752	pLSPage->fZero = false;
753	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
754	}
755	else
756	{
757	/*
758	* CRC the first half, if it doesn't match the page is dirty and
759	* we won't check the 2nd half (we'll do that next time).
760	*/
761	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
762	if (u32CrcH1 == pLSPage->u32CrcH1)
763	{
764	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
765	if (u32CrcH2 == pLSPage->u32CrcH2)
766	{
767	/* Probably not modified. */
768	if (pLSPage->fDirty)
769	pLSPage->cUnchangedScans++;
770	return false;
771	}
772
773	pLSPage->u32CrcH2 = u32CrcH2;
774	}
775	else
776	{
777	pLSPage->u32CrcH1 = u32CrcH1;
778	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
779	&& ASMMemIsZeroPage(pbPage))
780	{
781	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
782	pLSPage->fZero = true;
783	}
784	}
785	}
786
787	/* dirty page path */
788	pLSPage->cUnchangedScans = 0;
789	if (!pLSPage->fDirty)
790	{
791	pLSPage->fDirty = true;
792	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
793	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
794	if (fZero)
795	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
796	}
797	return true;
798	}
799
800
801	/**
802	* Scan for MMIO2 page modifications.
803	*
804	* @param pVM The VM handle.
805	* @param uPass The pass number.
806	*/
807	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
808	{
809	/*
810	* Since this is a bit expensive we lower the scan rate after a little while.
811	*/
812	if ( ( (uPass & 3) != 0
813	&& uPass > 10)
814	\|\| uPass == SSM_PASS_FINAL)
815	return;
816
817	pgmLock(pVM); /* paranoia */
818	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
819	{
820	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
821	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
822	pgmUnlock(pVM);
823
824	for (uint32_t iPage = 0; iPage < cPages; iPage++)
825	{
826	uint8_t const pbPage = (uint8_t const )pMmio2->pvR3 + iPage * PAGE_SIZE;
827	pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
828	}
829
830	pgmLock(pVM);
831	}
832	pgmUnlock(pVM);
833
834	}
835
836
837	/**
838	* Save quiescent MMIO2 pages.
839	*
840	* @returns VBox status code.
841	* @param pVM The VM handle.
842	* @param pSSM The SSM handle.
843	* @param fLiveSave Whether it's a live save or not.
844	* @param uPass The pass number.
845	*/
846	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
847	{
848	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
849	* device that we wish to know about changes.) */
850
851	int rc = VINF_SUCCESS;
852	if (uPass == SSM_PASS_FINAL)
853	{
854	/*
855	* The mop up round.
856	*/
857	pgmLock(pVM);
858	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
859	pMmio2 && RT_SUCCESS(rc);
860	pMmio2 = pMmio2->pNextR3)
861	{
862	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
863	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
864	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
865	uint32_t iPageLast = cPages;
866	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
867	{
868	uint8_t u8Type;
869	if (!fLiveSave)
870	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
871	else
872	{
873	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
874	if ( !paLSPages[iPage].fDirty
875	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
876	{
877	if (paLSPages[iPage].fZero)
878	continue;
879
880	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
881	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
882	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
883	continue;
884	}
885	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
886	pVM->pgm.s.LiveSave.cSavedPages++;
887	}
888
889	if (iPage != 0 && iPage == iPageLast + 1)
890	rc = SSMR3PutU8(pSSM, u8Type);
891	else
892	{
893	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
894	SSMR3PutU8(pSSM, pMmio2->idSavedState);
895	rc = SSMR3PutU32(pSSM, iPage);
896	}
897	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
898	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
899	if (RT_FAILURE(rc))
900	break;
901	iPageLast = iPage;
902	}
903	}
904	pgmUnlock(pVM);
905	}
906	/*
907	* Reduce the rate after a little while since the current MMIO2 approach is
908	* a bit expensive.
909	* We position it two passes after the scan pass to avoid saving busy pages.
910	*/
911	else if ( uPass <= 10
912	\|\| (uPass & 3) == 2)
913	{
914	pgmLock(pVM);
915	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
916	pMmio2 && RT_SUCCESS(rc);
917	pMmio2 = pMmio2->pNextR3)
918	{
919	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
920	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
921	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
922	uint32_t iPageLast = cPages;
923	pgmUnlock(pVM);
924
925	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
926	{
927	/* Skip clean pages and pages which hasn't quiesced. */
928	if (!paLSPages[iPage].fDirty)
929	continue;
930	if (paLSPages[iPage].cUnchangedScans < 3)
931	continue;
932	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
933	continue;
934
935	/* Save it. */
936	bool const fZero = paLSPages[iPage].fZero;
937	uint8_t abPage[PAGE_SIZE];
938	if (!fZero)
939	{
940	memcpy(abPage, pbPage, PAGE_SIZE);
941	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
942	}
943
944	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
945	if (iPage != 0 && iPage == iPageLast + 1)
946	rc = SSMR3PutU8(pSSM, u8Type);
947	else
948	{
949	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
950	SSMR3PutU8(pSSM, pMmio2->idSavedState);
951	rc = SSMR3PutU32(pSSM, iPage);
952	}
953	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
954	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
955	if (RT_FAILURE(rc))
956	break;
957
958	/* Housekeeping. */
959	paLSPages[iPage].fDirty = false;
960	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
961	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
962	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
963	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
964	pVM->pgm.s.LiveSave.cSavedPages++;
965	iPageLast = iPage;
966	}
967
968	pgmLock(pVM);
969	}
970	pgmUnlock(pVM);
971	}
972
973	return rc;
974	}
975
976
977	/**
978	* Cleans up MMIO2 pages after a live save.
979	*
980	* @param pVM The VM handle.
981	*/
982	static void pgmR3DoneMmio2Pages(PVM pVM)
983	{
984	/*
985	* Free the tracking structures for the MMIO2 pages.
986	* We do the freeing outside the lock in case the VM is running.
987	*/
988	pgmLock(pVM);
989	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
990	{
991	void *pvMmio2ToFree = pMmio2->paLSPages;
992	if (pvMmio2ToFree)
993	{
994	pMmio2->paLSPages = NULL;
995	pgmUnlock(pVM);
996	MMR3HeapFree(pvMmio2ToFree);
997	pgmLock(pVM);
998	}
999	}
1000	pgmUnlock(pVM);
1001	}
1002
1003
1004	/**
1005	* Prepares the RAM pages for a live save.
1006	*
1007	* @returns VBox status code.
1008	* @param pVM The VM handle.
1009	*/
1010	static int pgmR3PrepRamPages(PVM pVM)
1011	{
1012
1013	/*
1014	* Try allocating tracking structures for the ram ranges.
1015	*
1016	* To avoid lock contention, we leave the lock every time we're allocating
1017	* a new array. This means we'll have to ditch the allocation and start
1018	* all over again if the RAM range list changes in-between.
1019	*
1020	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1021	* for cleaning up.
1022	*/
1023	PPGMRAMRANGE pCur;
1024	pgmLock(pVM);
1025	do
1026	{
1027	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1028	{
1029	if ( !pCur->paLSPages
1030	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1031	{
1032	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1033	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1034	pgmUnlock(pVM);
1035	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1036	if (!paLSPages)
1037	return VERR_NO_MEMORY;
1038	pgmLock(pVM);
1039	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1040	{
1041	pgmUnlock(pVM);
1042	MMR3HeapFree(paLSPages);
1043	pgmLock(pVM);
1044	break; /* try again */
1045	}
1046	pCur->paLSPages = paLSPages;
1047
1048	/*
1049	* Initialize the array.
1050	*/
1051	uint32_t iPage = cPages;
1052	while (iPage-- > 0)
1053	{
1054	/** @todo yield critsect! (after moving this away from EMT0) */
1055	PCPGMPAGE pPage = &pCur->aPages[iPage];
1056	paLSPages[iPage].cDirtied = 0;
1057	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1058	paLSPages[iPage].fWriteMonitored = 0;
1059	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1060	paLSPages[iPage].u2Reserved = 0;
1061	switch (PGM_PAGE_GET_TYPE(pPage))
1062	{
1063	case PGMPAGETYPE_RAM:
1064	if (PGM_PAGE_IS_ZERO(pPage))
1065	{
1066	paLSPages[iPage].fZero = 1;
1067	paLSPages[iPage].fShared = 0;
1068	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1069	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1070	#endif
1071	}
1072	else if (PGM_PAGE_IS_SHARED(pPage))
1073	{
1074	paLSPages[iPage].fZero = 0;
1075	paLSPages[iPage].fShared = 1;
1076	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1077	paLSPages[iPage].u32Crc = UINT32_MAX;
1078	#endif
1079	}
1080	else
1081	{
1082	paLSPages[iPage].fZero = 0;
1083	paLSPages[iPage].fShared = 0;
1084	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1085	paLSPages[iPage].u32Crc = UINT32_MAX;
1086	#endif
1087	}
1088	paLSPages[iPage].fIgnore = 0;
1089	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1090	break;
1091
1092	case PGMPAGETYPE_ROM_SHADOW:
1093	case PGMPAGETYPE_ROM:
1094	{
1095	paLSPages[iPage].fZero = 0;
1096	paLSPages[iPage].fShared = 0;
1097	paLSPages[iPage].fDirty = 0;
1098	paLSPages[iPage].fIgnore = 1;
1099	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1100	paLSPages[iPage].u32Crc = UINT32_MAX;
1101	#endif
1102	pVM->pgm.s.LiveSave.cIgnoredPages++;
1103	break;
1104	}
1105
1106	default:
1107	AssertMsgFailed(("%R[pgmpage]", pPage));
1108	case PGMPAGETYPE_MMIO2:
1109	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1110	paLSPages[iPage].fZero = 0;
1111	paLSPages[iPage].fShared = 0;
1112	paLSPages[iPage].fDirty = 0;
1113	paLSPages[iPage].fIgnore = 1;
1114	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1115	paLSPages[iPage].u32Crc = UINT32_MAX;
1116	#endif
1117	pVM->pgm.s.LiveSave.cIgnoredPages++;
1118	break;
1119
1120	case PGMPAGETYPE_MMIO:
1121	paLSPages[iPage].fZero = 0;
1122	paLSPages[iPage].fShared = 0;
1123	paLSPages[iPage].fDirty = 0;
1124	paLSPages[iPage].fIgnore = 1;
1125	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1126	paLSPages[iPage].u32Crc = UINT32_MAX;
1127	#endif
1128	pVM->pgm.s.LiveSave.cIgnoredPages++;
1129	break;
1130	}
1131	}
1132	}
1133	}
1134	} while (pCur);
1135	pgmUnlock(pVM);
1136
1137	return VINF_SUCCESS;
1138	}
1139
1140
1141	/**
1142	* Saves the RAM configuration.
1143	*
1144	* @returns VBox status code.
1145	* @param pVM The VM handle.
1146	* @param pSSM The saved state handle.
1147	*/
1148	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1149	{
1150	uint32_t cbRamHole = 0;
1151	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1152	AssertRCReturn(rc, rc);
1153
1154	uint64_t cbRam = 0;
1155	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1156	AssertRCReturn(rc, rc);
1157
1158	SSMR3PutU32(pSSM, cbRamHole);
1159	return SSMR3PutU64(pSSM, cbRam);
1160	}
1161
1162
1163	/**
1164	* Loads and verifies the RAM configuration.
1165	*
1166	* @returns VBox status code.
1167	* @param pVM The VM handle.
1168	* @param pSSM The saved state handle.
1169	*/
1170	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1171	{
1172	uint32_t cbRamHoleCfg = 0;
1173	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1174	AssertRCReturn(rc, rc);
1175
1176	uint64_t cbRamCfg = 0;
1177	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1178	AssertRCReturn(rc, rc);
1179
1180	uint32_t cbRamHoleSaved;
1181	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1182
1183	uint64_t cbRamSaved;
1184	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1185	AssertRCReturn(rc, rc);
1186
1187	if ( cbRamHoleCfg != cbRamHoleSaved
1188	\|\| cbRamCfg != cbRamSaved)
1189	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1190	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1191	return VINF_SUCCESS;
1192	}
1193
1194	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1195
1196	/**
1197	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1198	* info with it.
1199	*
1200	* @param pVM The VM handle.
1201	* @param pCur The current RAM range.
1202	* @param paLSPages The current array of live save page tracking
1203	* structures.
1204	* @param iPage The page index.
1205	*/
1206	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1207	{
1208	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1209	void const *pvPage;
1210	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1211	if (RT_SUCCESS(rc))
1212	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1213	else
1214	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1215	}
1216
1217
1218	/**
1219	* Verifies the CRC-32 for a page given it's raw bits.
1220	*
1221	* @param pvPage The page bits.
1222	* @param pCur The current RAM range.
1223	* @param paLSPages The current array of live save page tracking
1224	* structures.
1225	* @param iPage The page index.
1226	*/
1227	static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1228	{
1229	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1230	{
1231	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1232	Assert(!PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) \|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1233	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1234	("%08x != %08x for %RGp %R[pgmpage]\n", paLSPages[iPage].u32Crc, u32Crc,
1235	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1236	}
1237	}
1238
1239
1240	/**
1241	* Verfies the CRC-32 for a RAM page.
1242	*
1243	* @param pVM The VM handle.
1244	* @param pCur The current RAM range.
1245	* @param paLSPages The current array of live save page tracking
1246	* structures.
1247	* @param iPage The page index.
1248	*/
1249	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1250	{
1251	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1252	{
1253	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1254	void const *pvPage;
1255	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1256	if (RT_SUCCESS(rc))
1257	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage);
1258	}
1259	}
1260
1261	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1262
1263	/**
1264	* Scan for RAM page modifications and reprotect them.
1265	*
1266	* @param pVM The VM handle.
1267	* @param fFinalPass Whether this is the final pass or not.
1268	*/
1269	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1270	{
1271	/*
1272	* The RAM.
1273	*/
1274	RTGCPHYS GCPhysCur = 0;
1275	PPGMRAMRANGE pCur;
1276	pgmLock(pVM);
1277	do
1278	{
1279	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1280	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1281	{
1282	if ( pCur->GCPhysLast > GCPhysCur
1283	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1284	{
1285	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1286	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1287	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1288	GCPhysCur = 0;
1289	for (; iPage < cPages; iPage++)
1290	{
1291	/* Do yield first. */
1292	if ( !fFinalPass
1293	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1294	&& (iPage & 0x7ff) == 0x100
1295	#endif
1296	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1297	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1298	{
1299	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1300	break; /* restart */
1301	}
1302
1303	/* Skip already ignored pages. */
1304	if (paLSPages[iPage].fIgnore)
1305	continue;
1306
1307	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1308	{
1309	/*
1310	* A RAM page.
1311	*/
1312	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1313	{
1314	case PGM_PAGE_STATE_ALLOCATED:
1315	/** @todo Optimize this: Don't always re-enable write
1316	* monitoring if the page is known to be very busy. */
1317	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1318	{
1319	Assert(paLSPages[iPage].fWriteMonitored);
1320	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1321	Assert(pVM->pgm.s.cWrittenToPages > 0);
1322	pVM->pgm.s.cWrittenToPages--;
1323	}
1324	else
1325	{
1326	Assert(!paLSPages[iPage].fWriteMonitored);
1327	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1328	}
1329
1330	if (!paLSPages[iPage].fDirty)
1331	{
1332	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1333	if (paLSPages[iPage].fZero)
1334	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1335	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1336	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1337	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1338	}
1339
1340	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1341	pVM->pgm.s.cMonitoredPages++;
1342	paLSPages[iPage].fWriteMonitored = 1;
1343	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1344	paLSPages[iPage].fDirty = 1;
1345	paLSPages[iPage].fZero = 0;
1346	paLSPages[iPage].fShared = 0;
1347	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1348	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1349	#endif
1350	break;
1351
1352	case PGM_PAGE_STATE_WRITE_MONITORED:
1353	Assert(paLSPages[iPage].fWriteMonitored);
1354	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1355	{
1356	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1357	if (paLSPages[iPage].fWriteMonitoredJustNow)
1358	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1359	else
1360	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1361	#endif
1362	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1363	}
1364	else
1365	{
1366	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1367	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1368	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1369	#endif
1370	if (!paLSPages[iPage].fDirty)
1371	{
1372	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1373	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1374	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1375	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1376	}
1377	}
1378	break;
1379
1380	case PGM_PAGE_STATE_ZERO:
1381	if (!paLSPages[iPage].fZero)
1382	{
1383	if (!paLSPages[iPage].fDirty)
1384	{
1385	paLSPages[iPage].fDirty = 1;
1386	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1387	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1388	}
1389	paLSPages[iPage].fZero = 1;
1390	paLSPages[iPage].fShared = 0;
1391	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1392	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1393	#endif
1394	}
1395	break;
1396
1397	case PGM_PAGE_STATE_SHARED:
1398	if (!paLSPages[iPage].fShared)
1399	{
1400	if (!paLSPages[iPage].fDirty)
1401	{
1402	paLSPages[iPage].fDirty = 1;
1403	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1404	if (paLSPages[iPage].fZero)
1405	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1406	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1407	}
1408	paLSPages[iPage].fZero = 0;
1409	paLSPages[iPage].fShared = 1;
1410	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1411	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1412	#endif
1413	}
1414	break;
1415	}
1416	}
1417	else
1418	{
1419	/*
1420	* All other types => Ignore the page.
1421	*/
1422	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1423	paLSPages[iPage].fIgnore = 1;
1424	if (paLSPages[iPage].fWriteMonitored)
1425	{
1426	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1427	* pages! */
1428	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1429	{
1430	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1431	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1432	Assert(pVM->pgm.s.cMonitoredPages > 0);
1433	pVM->pgm.s.cMonitoredPages--;
1434	}
1435	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1436	{
1437	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1438	Assert(pVM->pgm.s.cWrittenToPages > 0);
1439	pVM->pgm.s.cWrittenToPages--;
1440	}
1441	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1442	}
1443
1444	/** @todo the counting doesn't quite work out here. fix later? */
1445	if (paLSPages[iPage].fDirty)
1446	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1447	else
1448	{
1449	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1450	if (paLSPages[iPage].fZero)
1451	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1452	}
1453	pVM->pgm.s.LiveSave.cIgnoredPages++;
1454	}
1455	} /* for each page in range */
1456
1457	if (GCPhysCur != 0)
1458	break; /* Yield + ramrange change */
1459	GCPhysCur = pCur->GCPhysLast;
1460	}
1461	} /* for each range */
1462	} while (pCur);
1463	pgmUnlock(pVM);
1464	}
1465
1466
1467	/**
1468	* Save quiescent RAM pages.
1469	*
1470	* @returns VBox status code.
1471	* @param pVM The VM handle.
1472	* @param pSSM The SSM handle.
1473	* @param fLiveSave Whether it's a live save or not.
1474	* @param uPass The pass number.
1475	*/
1476	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1477	{
1478	/*
1479	* The RAM.
1480	*/
1481	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1482	RTGCPHYS GCPhysCur = 0;
1483	PPGMRAMRANGE pCur;
1484	pgmLock(pVM);
1485	do
1486	{
1487	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1488	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1489	{
1490	if ( pCur->GCPhysLast > GCPhysCur
1491	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1492	{
1493	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1494	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1495	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1496	GCPhysCur = 0;
1497	for (; iPage < cPages; iPage++)
1498	{
1499	/* Do yield first. */
1500	if ( uPass != SSM_PASS_FINAL
1501	&& (iPage & 0x7ff) == 0x100
1502	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1503	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1504	{
1505	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1506	break; /* restart */
1507	}
1508
1509	/*
1510	* Only save pages that hasn't changed since last scan and are dirty.
1511	*/
1512	if ( uPass != SSM_PASS_FINAL
1513	&& paLSPages)
1514	{
1515	if (!paLSPages[iPage].fDirty)
1516	continue;
1517	if (paLSPages[iPage].fWriteMonitoredJustNow)
1518	continue;
1519	if (paLSPages[iPage].fIgnore)
1520	continue;
1521	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM) /* in case of recent ramppings */
1522	continue;
1523	if ( PGM_PAGE_GET_STATE(&pCur->aPages[iPage])
1524	!= ( paLSPages[iPage].fZero
1525	? PGM_PAGE_STATE_ZERO
1526	: paLSPages[iPage].fShared
1527	? PGM_PAGE_STATE_SHARED
1528	: PGM_PAGE_STATE_WRITE_MONITORED))
1529	continue;
1530	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1531	continue;
1532	}
1533	else
1534	{
1535	if ( paLSPages
1536	&& !paLSPages[iPage].fDirty
1537	&& !paLSPages[iPage].fIgnore)
1538	{
1539	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1540	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1541	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1542	#endif
1543	continue;
1544	}
1545	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1546	continue;
1547	}
1548
1549	/*
1550	* Do the saving outside the PGM critsect since SSM may block on I/O.
1551	*/
1552	int rc;
1553	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1554	bool fZero = PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]);
1555
1556	if (!fZero)
1557	{
1558	/*
1559	* Copy the page and then save it outside the lock (since any
1560	* SSM call may block).
1561	*/
1562	uint8_t abPage[PAGE_SIZE];
1563	void const *pvPage;
1564	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1565	if (RT_SUCCESS(rc))
1566	{
1567	memcpy(abPage, pvPage, PAGE_SIZE);
1568	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1569	if (paLSPages)
1570	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage);
1571	#endif
1572	}
1573	pgmUnlock(pVM);
1574	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1575
1576	if (GCPhys == GCPhysLast + PAGE_SIZE)
1577	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1578	else
1579	{
1580	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1581	SSMR3PutGCPhys(pSSM, GCPhys);
1582	}
1583	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1584	}
1585	else
1586	{
1587	/*
1588	* Dirty zero page.
1589	*/
1590	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1591	if (paLSPages)
1592	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1593	#endif
1594	pgmUnlock(pVM);
1595
1596	if (GCPhys == GCPhysLast + PAGE_SIZE)
1597	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1598	else
1599	{
1600	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1601	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1602	}
1603	}
1604	if (RT_FAILURE(rc))
1605	return rc;
1606
1607	pgmLock(pVM);
1608	GCPhysLast = GCPhys;
1609	if (paLSPages)
1610	{
1611	paLSPages[iPage].fDirty = 0;
1612	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1613	if (fZero)
1614	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1615	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1616	pVM->pgm.s.LiveSave.cSavedPages++;
1617	}
1618	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1619	{
1620	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1621	break; /* restart */
1622	}
1623
1624	} /* for each page in range */
1625
1626	if (GCPhysCur != 0)
1627	break; /* Yield + ramrange change */
1628	GCPhysCur = pCur->GCPhysLast;
1629	}
1630	} /* for each range */
1631	} while (pCur);
1632	pgmUnlock(pVM);
1633
1634	return VINF_SUCCESS;
1635	}
1636
1637
1638	/**
1639	* Cleans up RAM pages after a live save.
1640	*
1641	* @param pVM The VM handle.
1642	*/
1643	static void pgmR3DoneRamPages(PVM pVM)
1644	{
1645	/*
1646	* Free the tracking arrays and disable write monitoring.
1647	*
1648	* Play nice with the PGM lock in case we're called while the VM is still
1649	* running. This means we have to delay the freeing since we wish to use
1650	* paLSPages as an indicator of which RAM ranges which we need to scan for
1651	* write monitored pages.
1652	*/
1653	void *pvToFree = NULL;
1654	PPGMRAMRANGE pCur;
1655	uint32_t cMonitoredPages = 0;
1656	pgmLock(pVM);
1657	do
1658	{
1659	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1660	{
1661	if (pCur->paLSPages)
1662	{
1663	if (pvToFree)
1664	{
1665	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1666	pgmUnlock(pVM);
1667	MMR3HeapFree(pvToFree);
1668	pvToFree = NULL;
1669	pgmLock(pVM);
1670	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1671	break; /* start over again. */
1672	}
1673
1674	pvToFree = pCur->paLSPages;
1675	pCur->paLSPages = NULL;
1676
1677	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1678	while (iPage--)
1679	{
1680	PPGMPAGE pPage = &pCur->aPages[iPage];
1681	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1682	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1683	{
1684	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1685	cMonitoredPages++;
1686	}
1687	}
1688	}
1689	}
1690	} while (pCur);
1691
1692	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1693	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1694	pVM->pgm.s.cMonitoredPages = 0;
1695	else
1696	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1697
1698	pgmUnlock(pVM);
1699
1700	MMR3HeapFree(pvToFree);
1701	pvToFree = NULL;
1702	}
1703
1704
1705	/**
1706	* Execute a live save pass.
1707	*
1708	* @returns VBox status code.
1709	*
1710	* @param pVM The VM handle.
1711	* @param pSSM The SSM handle.
1712	*/
1713	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1714	{
1715	int rc;
1716
1717	/*
1718	* Save the MMIO2 and ROM range IDs in pass 0.
1719	*/
1720	if (uPass == 0)
1721	{
1722	rc = pgmR3SaveRamConfig(pVM, pSSM);
1723	if (RT_FAILURE(rc))
1724	return rc;
1725	rc = pgmR3SaveRomRanges(pVM, pSSM);
1726	if (RT_FAILURE(rc))
1727	return rc;
1728	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1729	if (RT_FAILURE(rc))
1730	return rc;
1731	}
1732	/*
1733	* Reset the page-per-second estimate to avoid inflation by the initial
1734	* load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1735	*/
1736	else if (uPass == 7)
1737	{
1738	pVM->pgm.s.LiveSave.cSavedPages = 0;
1739	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1740	}
1741
1742	/*
1743	* Do the scanning.
1744	*/
1745	pgmR3ScanRomPages(pVM);
1746	pgmR3ScanMmio2Pages(pVM, uPass);
1747	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1748	pgmR3PoolClearAll(pVM); /** @todo this could perhaps be optimized a bit. */
1749
1750	/*
1751	* Save the pages.
1752	*/
1753	if (uPass == 0)
1754	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1755	else
1756	rc = VINF_SUCCESS;
1757	if (RT_SUCCESS(rc))
1758	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1759	if (RT_SUCCESS(rc))
1760	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1761	if (RT_SUCCESS(rc))
1762	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1763	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1764
1765	return rc;
1766	}
1767
1768
1769	/**
1770	* Votes on whether the live save phase is done or not.
1771	*
1772	* @returns VBox status code.
1773	*
1774	* @param pVM The VM handle.
1775	* @param pSSM The SSM handle.
1776	* @param uPass The data pass.
1777	*/
1778	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1779	{
1780	/*
1781	* Update and calculate parameters used in the decision making.
1782	*/
1783	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1784
1785	/* update history. */
1786	pgmLock(pVM);
1787	uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1788	pgmUnlock(pVM);
1789	uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1790	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1791	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1792	+ cWrittenToPages;
1793	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1794	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1795	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1796
1797	/* calc shortterm average (4 passes). */
1798	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1799	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1800	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1801	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1802	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1803	uint32_t const cDirtyPagesShort = cTotal / 4;
1804	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1805
1806	/* calc longterm average. */
1807	cTotal = 0;
1808	if (uPass < cHistoryEntries)
1809	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1810	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1811	else
1812	for (i = 0; i < cHistoryEntries; i++)
1813	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1814	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1815	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1816
1817	/* estimate the speed */
1818	uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1819	uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1820	/ ((long double)cNsElapsed / 1000000000.0) );
1821	pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1822
1823	/*
1824	* Try make a decision.
1825	*/
1826	if ( cDirtyPagesShort <= cDirtyPagesLong
1827	&& ( cDirtyNow <= cDirtyPagesShort
1828	\|\| cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1829	)
1830	)
1831	{
1832	if (uPass > 10)
1833	{
1834	uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1835	uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1836	uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1837	if (cMsMaxDowntime < 32)
1838	cMsMaxDowntime = 32;
1839	if ( ( cMsLeftLong <= cMsMaxDowntime
1840	&& cMsLeftShort < cMsMaxDowntime)
1841	\|\| cMsLeftShort < cMsMaxDowntime / 2
1842	)
1843	{
1844	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u\|%ums cDirtyPagesLong=%u\|%ums cMsMaxDowntime=%u\n",
1845	uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1846	return VINF_SUCCESS;
1847	}
1848	}
1849	else
1850	{
1851	if ( ( cDirtyPagesShort <= 128
1852	&& cDirtyPagesLong <= 1024)
1853	\|\| cDirtyPagesLong <= 256
1854	)
1855	{
1856	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1857	return VINF_SUCCESS;
1858	}
1859	}
1860	}
1861	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1862	}
1863
1864
1865	/**
1866	* Prepare for a live save operation.
1867	*
1868	* This will attempt to allocate and initialize the tracking structures. It
1869	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1870	* pgmR3SaveDone will do the cleanups.
1871	*
1872	* @returns VBox status code.
1873	*
1874	* @param pVM The VM handle.
1875	* @param pSSM The SSM handle.
1876	*/
1877	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1878	{
1879	/*
1880	* Indicate that we will be using the write monitoring.
1881	*/
1882	pgmLock(pVM);
1883	/** @todo find a way of mediating this when more users are added. */
1884	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1885	{
1886	pgmUnlock(pVM);
1887	AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1888	}
1889	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1890	pgmUnlock(pVM);
1891
1892	/*
1893	* Initialize the statistics.
1894	*/
1895	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1896	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1897	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1898	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1899	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1900	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1901	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1902	pVM->pgm.s.LiveSave.fActive = true;
1903	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
1904	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
1905	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
1906	pVM->pgm.s.LiveSave.cSavedPages = 0;
1907	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1908	pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
1909
1910	/*
1911	* Per page type.
1912	*/
1913	int rc = pgmR3PrepRomPages(pVM);
1914	if (RT_SUCCESS(rc))
1915	rc = pgmR3PrepMmio2Pages(pVM);
1916	if (RT_SUCCESS(rc))
1917	rc = pgmR3PrepRamPages(pVM);
1918	return rc;
1919	}
1920
1921
1922	/**
1923	* Execute state save operation.
1924	*
1925	* @returns VBox status code.
1926	* @param pVM VM Handle.
1927	* @param pSSM SSM operation handle.
1928	*/
1929	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1930	{
1931	int rc;
1932	unsigned i;
1933	PPGM pPGM = &pVM->pgm.s;
1934
1935	/*
1936	* Lock PGM and set the no-more-writes indicator.
1937	*/
1938	pgmLock(pVM);
1939	pVM->pgm.s.fNoMorePhysWrites = true;
1940
1941	/*
1942	* Save basic data (required / unaffected by relocation).
1943	*/
1944	bool const fMappingsFixed = pVM->pgm.s.fMappingsFixed;
1945	pVM->pgm.s.fMappingsFixed \|= pVM->pgm.s.fMappingsFixedRestored;
1946	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
1947	pVM->pgm.s.fMappingsFixed = fMappingsFixed;
1948
1949	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1950	SSMR3PutStruct(pSSM, &pVM->aCpus[idCpu].pgm.s, &s_aPGMCpuFields[0]);
1951
1952	/*
1953	* The guest mappings.
1954	*/
1955	i = 0;
1956	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1957	{
1958	SSMR3PutU32( pSSM, i);
1959	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1960	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
1961	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1962	}
1963	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
1964
1965	/*
1966	* Save the (remainder of the) memory.
1967	*/
1968	if (RT_SUCCESS(rc))
1969	{
1970	if (pVM->pgm.s.LiveSave.fActive)
1971	{
1972	pgmR3ScanRomPages(pVM);
1973	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
1974	pgmR3ScanRamPages(pVM, true /fFinalPass/);
1975
1976	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
1977	if (RT_SUCCESS(rc))
1978	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1979	if (RT_SUCCESS(rc))
1980	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1981	}
1982	else
1983	{
1984	rc = pgmR3SaveRamConfig(pVM, pSSM);
1985	if (RT_SUCCESS(rc))
1986	rc = pgmR3SaveRomRanges(pVM, pSSM);
1987	if (RT_SUCCESS(rc))
1988	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1989	if (RT_SUCCESS(rc))
1990	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
1991	if (RT_SUCCESS(rc))
1992	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
1993	if (RT_SUCCESS(rc))
1994	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
1995	if (RT_SUCCESS(rc))
1996	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
1997	}
1998	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1999	}
2000
2001	pgmUnlock(pVM);
2002	return rc;
2003	}
2004
2005
2006	/**
2007	* Cleans up after an save state operation.
2008	*
2009	* @returns VBox status code.
2010	* @param pVM VM Handle.
2011	* @param pSSM SSM operation handle.
2012	*/
2013	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2014	{
2015	/*
2016	* Do per page type cleanups first.
2017	*/
2018	if (pVM->pgm.s.LiveSave.fActive)
2019	{
2020	pgmR3DoneRomPages(pVM);
2021	pgmR3DoneMmio2Pages(pVM);
2022	pgmR3DoneRamPages(pVM);
2023	}
2024
2025	/*
2026	* Clear the live save indicator and disengage write monitoring.
2027	*/
2028	pgmLock(pVM);
2029	pVM->pgm.s.LiveSave.fActive = false;
2030	/** @todo this is blindly assuming that we're the only user of write
2031	* monitoring. Fix this when more users are added. */
2032	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2033	pgmUnlock(pVM);
2034
2035	return VINF_SUCCESS;
2036	}
2037
2038
2039	/**
2040	* Prepare state load operation.
2041	*
2042	* @returns VBox status code.
2043	* @param pVM VM Handle.
2044	* @param pSSM SSM operation handle.
2045	*/
2046	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2047	{
2048	/*
2049	* Call the reset function to make sure all the memory is cleared.
2050	*/
2051	PGMR3Reset(pVM);
2052	pVM->pgm.s.LiveSave.fActive = false;
2053	NOREF(pSSM);
2054	return VINF_SUCCESS;
2055	}
2056
2057
2058	/**
2059	* Load an ignored page.
2060	*
2061	* @returns VBox status code.
2062	* @param pSSM The saved state handle.
2063	*/
2064	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2065	{
2066	uint8_t abPage[PAGE_SIZE];
2067	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2068	}
2069
2070
2071	/**
2072	* Loads a page without any bits in the saved state, i.e. making sure it's
2073	* really zero.
2074	*
2075	* @returns VBox status code.
2076	* @param pVM The VM handle.
2077	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2078	* state).
2079	* @param pPage The guest page tracking structure.
2080	* @param GCPhys The page address.
2081	* @param pRam The ram range (logging).
2082	*/
2083	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2084	{
2085	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2086	&& uType != PGMPAGETYPE_INVALID)
2087	return VERR_SSM_UNEXPECTED_DATA;
2088
2089	/* I think this should be sufficient. */
2090	if (!PGM_PAGE_IS_ZERO(pPage))
2091	return VERR_SSM_UNEXPECTED_DATA;
2092
2093	NOREF(pVM);
2094	NOREF(GCPhys);
2095	NOREF(pRam);
2096	return VINF_SUCCESS;
2097	}
2098
2099
2100	/**
2101	* Loads a page from the saved state.
2102	*
2103	* @returns VBox status code.
2104	* @param pVM The VM handle.
2105	* @param pSSM The SSM handle.
2106	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2107	* state).
2108	* @param pPage The guest page tracking structure.
2109	* @param GCPhys The page address.
2110	* @param pRam The ram range (logging).
2111	*/
2112	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2113	{
2114	/*
2115	* Match up the type, dealing with MMIO2 aliases (dropped).
2116	*/
2117	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2118	\|\| uType == PGMPAGETYPE_INVALID,
2119	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2120	VERR_SSM_UNEXPECTED_DATA);
2121
2122	/*
2123	* Load the page.
2124	*/
2125	void *pvPage;
2126	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2127	if (RT_SUCCESS(rc))
2128	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2129
2130	return rc;
2131	}
2132
2133
2134	/**
2135	* Loads a page (counter part to pgmR3SavePage).
2136	*
2137	* @returns VBox status code, fully bitched errors.
2138	* @param pVM The VM handle.
2139	* @param pSSM The SSM handle.
2140	* @param uType The page type.
2141	* @param pPage The page.
2142	* @param GCPhys The page address.
2143	* @param pRam The RAM range (for error messages).
2144	*/
2145	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2146	{
2147	uint8_t uState;
2148	int rc = SSMR3GetU8(pSSM, &uState);
2149	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2150	if (uState == 0 /* zero */)
2151	rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2152	else if (uState == 1)
2153	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2154	else
2155	rc = VERR_INTERNAL_ERROR;
2156	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2157	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2158	rc);
2159	return VINF_SUCCESS;
2160	}
2161
2162
2163	/**
2164	* Loads a shadowed ROM page.
2165	*
2166	* @returns VBox status code, errors are fully bitched.
2167	* @param pVM The VM handle.
2168	* @param pSSM The saved state handle.
2169	* @param pPage The page.
2170	* @param GCPhys The page address.
2171	* @param pRam The RAM range (for error messages).
2172	*/
2173	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2174	{
2175	/*
2176	* Load and set the protection first, then load the two pages, the first
2177	* one is the active the other is the passive.
2178	*/
2179	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2180	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2181
2182	uint8_t uProt;
2183	int rc = SSMR3GetU8(pSSM, &uProt);
2184	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2185	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2186	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2187	&& enmProt < PGMROMPROT_END,
2188	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2189	VERR_SSM_UNEXPECTED_DATA);
2190
2191	if (pRomPage->enmProt != enmProt)
2192	{
2193	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2194	AssertLogRelRCReturn(rc, rc);
2195	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2196	}
2197
2198	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2199	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2200	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2201	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2202
2203	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2204	* used down the line (will the 2nd page will be written to the first
2205	* one because of a false TLB hit since the TLB is using GCPhys and
2206	* doesn't check the HCPhys of the desired page). */
2207	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2208	if (RT_SUCCESS(rc))
2209	{
2210	pPageActive = pPage;
2211	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2212	}
2213	return rc;
2214	}
2215
2216	/**
2217	* Ram range flags and bits for older versions of the saved state.
2218	*
2219	* @returns VBox status code.
2220	*
2221	* @param pVM The VM handle
2222	* @param pSSM The SSM handle.
2223	* @param uVersion The saved state version.
2224	*/
2225	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2226	{
2227	PPGM pPGM = &pVM->pgm.s;
2228
2229	/*
2230	* Ram range flags and bits.
2231	*/
2232	uint32_t i = 0;
2233	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2234	{
2235	/* Check the seqence number / separator. */
2236	uint32_t u32Sep;
2237	int rc = SSMR3GetU32(pSSM, &u32Sep);
2238	if (RT_FAILURE(rc))
2239	return rc;
2240	if (u32Sep == ~0U)
2241	break;
2242	if (u32Sep != i)
2243	{
2244	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2245	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2246	}
2247	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2248
2249	/* Get the range details. */
2250	RTGCPHYS GCPhys;
2251	SSMR3GetGCPhys(pSSM, &GCPhys);
2252	RTGCPHYS GCPhysLast;
2253	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2254	RTGCPHYS cb;
2255	SSMR3GetGCPhys(pSSM, &cb);
2256	uint8_t fHaveBits;
2257	rc = SSMR3GetU8(pSSM, &fHaveBits);
2258	if (RT_FAILURE(rc))
2259	return rc;
2260	if (fHaveBits & ~1)
2261	{
2262	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2263	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2264	}
2265	size_t cchDesc = 0;
2266	char szDesc[256];
2267	szDesc[0] = '\0';
2268	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2269	{
2270	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2271	if (RT_FAILURE(rc))
2272	return rc;
2273	/* Since we've modified the description strings in r45878, only compare
2274	them if the saved state is more recent. */
2275	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2276	cchDesc = strlen(szDesc);
2277	}
2278
2279	/*
2280	* Match it up with the current range.
2281	*
2282	* Note there is a hack for dealing with the high BIOS mapping
2283	* in the old saved state format, this means we might not have
2284	* a 1:1 match on success.
2285	*/
2286	if ( ( GCPhys != pRam->GCPhys
2287	\|\| GCPhysLast != pRam->GCPhysLast
2288	\|\| cb != pRam->cb
2289	\|\| ( cchDesc
2290	&& strcmp(szDesc, pRam->pszDesc)) )
2291	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2292	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2293	\|\| GCPhys != UINT32_C(0xfff80000)
2294	\|\| GCPhysLast != UINT32_C(0xffffffff)
2295	\|\| pRam->GCPhysLast != GCPhysLast
2296	\|\| pRam->GCPhys < GCPhys
2297	\|\| !fHaveBits)
2298	)
2299	{
2300	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2301	"State : %RGp-%RGp %RGp bytes %s %s\n",
2302	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2303	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2304	/*
2305	* If we're loading a state for debugging purpose, don't make a fuss if
2306	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2307	*/
2308	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2309	\|\| GCPhys < 8 * _1M)
2310	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2311	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2312	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2313	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2314
2315	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2316	continue;
2317	}
2318
2319	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2320	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2321	{
2322	/*
2323	* Load the pages one by one.
2324	*/
2325	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2326	{
2327	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2328	PPGMPAGE pPage = &pRam->aPages[iPage];
2329	uint8_t uType;
2330	rc = SSMR3GetU8(pSSM, &uType);
2331	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2332	if (uType == PGMPAGETYPE_ROM_SHADOW)
2333	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2334	else
2335	rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2336	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2337	}
2338	}
2339	else
2340	{
2341	/*
2342	* Old format.
2343	*/
2344
2345	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2346	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2347	uint32_t fFlags = 0;
2348	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2349	{
2350	uint16_t u16Flags;
2351	rc = SSMR3GetU16(pSSM, &u16Flags);
2352	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2353	fFlags \|= u16Flags;
2354	}
2355
2356	/* Load the bits */
2357	if ( !fHaveBits
2358	&& GCPhysLast < UINT32_C(0xe0000000))
2359	{
2360	/*
2361	* Dynamic chunks.
2362	*/
2363	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2364	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2365	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2366	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2367
2368	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2369	{
2370	uint8_t fPresent;
2371	rc = SSMR3GetU8(pSSM, &fPresent);
2372	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2373	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2374	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2375	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2376
2377	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2378	{
2379	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2380	PPGMPAGE pPage = &pRam->aPages[iPage];
2381	if (fPresent)
2382	{
2383	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2384	rc = pgmR3LoadPageToDevNullOld(pSSM);
2385	else
2386	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2387	}
2388	else
2389	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2390	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2391	}
2392	}
2393	}
2394	else if (pRam->pvR3)
2395	{
2396	/*
2397	* MMIO2.
2398	*/
2399	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2400	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2401	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2402	AssertLogRelMsgReturn(pRam->pvR3,
2403	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2404	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2405
2406	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2407	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2408	}
2409	else if (GCPhysLast < UINT32_C(0xfff80000))
2410	{
2411	/*
2412	* PCI MMIO, no pages saved.
2413	*/
2414	}
2415	else
2416	{
2417	/*
2418	* Load the 0xfff80000..0xffffffff BIOS range.
2419	* It starts with X reserved pages that we have to skip over since
2420	* the RAMRANGE create by the new code won't include those.
2421	*/
2422	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2423	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2424	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2425	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2426	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2427	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2428	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2429
2430	/* Skip wasted reserved pages before the ROM. */
2431	while (GCPhys < pRam->GCPhys)
2432	{
2433	rc = pgmR3LoadPageToDevNullOld(pSSM);
2434	GCPhys += PAGE_SIZE;
2435	}
2436
2437	/* Load the bios pages. */
2438	cPages = pRam->cb >> PAGE_SHIFT;
2439	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2440	{
2441	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2442	PPGMPAGE pPage = &pRam->aPages[iPage];
2443
2444	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2445	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2446	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2447	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2448	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2449	}
2450	}
2451	}
2452	}
2453
2454	return VINF_SUCCESS;
2455	}
2456
2457
2458	/**
2459	* Worker for pgmR3Load and pgmR3LoadLocked.
2460	*
2461	* @returns VBox status code.
2462	*
2463	* @param pVM The VM handle.
2464	* @param pSSM The SSM handle.
2465	* @param uVersion The saved state version.
2466	*
2467	* @todo This needs splitting up if more record types or code twists are
2468	* added...
2469	*/
2470	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2471	{
2472	/*
2473	* Process page records until we hit the terminator.
2474	*/
2475	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2476	PPGMRAMRANGE pRamHint = NULL;
2477	uint8_t id = UINT8_MAX;
2478	uint32_t iPage = UINT32_MAX - 10;
2479	PPGMROMRANGE pRom = NULL;
2480	PPGMMMIO2RANGE pMmio2 = NULL;
2481	for (;;)
2482	{
2483	/*
2484	* Get the record type and flags.
2485	*/
2486	uint8_t u8;
2487	int rc = SSMR3GetU8(pSSM, &u8);
2488	if (RT_FAILURE(rc))
2489	return rc;
2490	if (u8 == PGM_STATE_REC_END)
2491	return VINF_SUCCESS;
2492	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2493	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2494	{
2495	/*
2496	* RAM page.
2497	*/
2498	case PGM_STATE_REC_RAM_ZERO:
2499	case PGM_STATE_REC_RAM_RAW:
2500	{
2501	/*
2502	* Get the address and resolve it into a page descriptor.
2503	*/
2504	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2505	GCPhys += PAGE_SIZE;
2506	else
2507	{
2508	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2509	if (RT_FAILURE(rc))
2510	return rc;
2511	}
2512	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2513
2514	PPGMPAGE pPage;
2515	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2516	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2517
2518	/*
2519	* Take action according to the record type.
2520	*/
2521	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2522	{
2523	case PGM_STATE_REC_RAM_ZERO:
2524	{
2525	if (PGM_PAGE_IS_ZERO(pPage))
2526	break;
2527	/** @todo implement zero page replacing. */
2528	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2529	void *pvDstPage;
2530	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2531	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2532	ASMMemZeroPage(pvDstPage);
2533	break;
2534	}
2535
2536	case PGM_STATE_REC_RAM_RAW:
2537	{
2538	void *pvDstPage;
2539	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2540	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2541	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2542	if (RT_FAILURE(rc))
2543	return rc;
2544	break;
2545	}
2546
2547	default:
2548	AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2549	}
2550	id = UINT8_MAX;
2551	break;
2552	}
2553
2554	/*
2555	* MMIO2 page.
2556	*/
2557	case PGM_STATE_REC_MMIO2_RAW:
2558	case PGM_STATE_REC_MMIO2_ZERO:
2559	{
2560	/*
2561	* Get the ID + page number and resolved that into a MMIO2 page.
2562	*/
2563	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2564	iPage++;
2565	else
2566	{
2567	SSMR3GetU8(pSSM, &id);
2568	rc = SSMR3GetU32(pSSM, &iPage);
2569	if (RT_FAILURE(rc))
2570	return rc;
2571	}
2572	if ( !pMmio2
2573	\|\| pMmio2->idSavedState != id)
2574	{
2575	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2576	if (pMmio2->idSavedState == id)
2577	break;
2578	AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2579	}
2580	AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2581	void pvDstPage = (uint8_t )pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2582
2583	/*
2584	* Load the page bits.
2585	*/
2586	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2587	ASMMemZeroPage(pvDstPage);
2588	else
2589	{
2590	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2591	if (RT_FAILURE(rc))
2592	return rc;
2593	}
2594	GCPhys = NIL_RTGCPHYS;
2595	break;
2596	}
2597
2598	/*
2599	* ROM pages.
2600	*/
2601	case PGM_STATE_REC_ROM_VIRGIN:
2602	case PGM_STATE_REC_ROM_SHW_RAW:
2603	case PGM_STATE_REC_ROM_SHW_ZERO:
2604	case PGM_STATE_REC_ROM_PROT:
2605	{
2606	/*
2607	* Get the ID + page number and resolved that into a ROM page descriptor.
2608	*/
2609	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2610	iPage++;
2611	else
2612	{
2613	SSMR3GetU8(pSSM, &id);
2614	rc = SSMR3GetU32(pSSM, &iPage);
2615	if (RT_FAILURE(rc))
2616	return rc;
2617	}
2618	if ( !pRom
2619	\|\| pRom->idSavedState != id)
2620	{
2621	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2622	if (pRom->idSavedState == id)
2623	break;
2624	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2625	}
2626	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2627	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2628	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2629
2630	/*
2631	* Get and set the protection.
2632	*/
2633	uint8_t u8Prot;
2634	rc = SSMR3GetU8(pSSM, &u8Prot);
2635	if (RT_FAILURE(rc))
2636	return rc;
2637	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2638	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2639
2640	if (enmProt != pRomPage->enmProt)
2641	{
2642	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2643	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2644	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2645	GCPhys, enmProt, pRom->pszDesc);
2646	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2647	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2648	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2649	}
2650	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2651	break; /* done */
2652
2653	/*
2654	* Get the right page descriptor.
2655	*/
2656	PPGMPAGE pRealPage;
2657	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2658	{
2659	case PGM_STATE_REC_ROM_VIRGIN:
2660	if (!PGMROMPROT_IS_ROM(enmProt))
2661	pRealPage = &pRomPage->Virgin;
2662	else
2663	pRealPage = NULL;
2664	break;
2665
2666	case PGM_STATE_REC_ROM_SHW_RAW:
2667	case PGM_STATE_REC_ROM_SHW_ZERO:
2668	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2669	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2670	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2671	GCPhys, enmProt, pRom->pszDesc);
2672	if (PGMROMPROT_IS_ROM(enmProt))
2673	pRealPage = &pRomPage->Shadow;
2674	else
2675	pRealPage = NULL;
2676	break;
2677
2678	default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2679	}
2680	if (!pRealPage)
2681	{
2682	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2683	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2684	}
2685
2686	/*
2687	* Make it writable and map it (if necessary).
2688	*/
2689	void *pvDstPage = NULL;
2690	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2691	{
2692	case PGM_STATE_REC_ROM_SHW_ZERO:
2693	if (PGM_PAGE_IS_ZERO(pRealPage))
2694	break;
2695	/** @todo implement zero page replacing. */
2696	/* fall thru */
2697	case PGM_STATE_REC_ROM_VIRGIN:
2698	case PGM_STATE_REC_ROM_SHW_RAW:
2699	{
2700	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2701	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2702	break;
2703	}
2704	}
2705
2706	/*
2707	* Load the bits.
2708	*/
2709	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2710	{
2711	case PGM_STATE_REC_ROM_SHW_ZERO:
2712	if (pvDstPage)
2713	ASMMemZeroPage(pvDstPage);
2714	break;
2715
2716	case PGM_STATE_REC_ROM_VIRGIN:
2717	case PGM_STATE_REC_ROM_SHW_RAW:
2718	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2719	if (RT_FAILURE(rc))
2720	return rc;
2721	break;
2722	}
2723	GCPhys = NIL_RTGCPHYS;
2724	break;
2725	}
2726
2727	/*
2728	* Unknown type.
2729	*/
2730	default:
2731	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2732	}
2733	} /* forever */
2734	}
2735
2736
2737	/**
2738	* Worker for pgmR3Load.
2739	*
2740	* @returns VBox status code.
2741	*
2742	* @param pVM The VM handle.
2743	* @param pSSM The SSM handle.
2744	* @param uVersion The saved state version.
2745	*/
2746	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2747	{
2748	PPGM pPGM = &pVM->pgm.s;
2749	int rc;
2750	uint32_t u32Sep;
2751
2752	/*
2753	* Load basic data (required / unaffected by relocation).
2754	*/
2755	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2756	{
2757	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2758	AssertLogRelRCReturn(rc, rc);
2759
2760	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2761	{
2762	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2763	AssertLogRelRCReturn(rc, rc);
2764	}
2765	}
2766	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2767	{
2768	AssertRelease(pVM->cCpus == 1);
2769
2770	PGMOLD pgmOld;
2771	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2772	AssertLogRelRCReturn(rc, rc);
2773
2774	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2775	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2776	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2777
2778	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2779	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2780	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2781	}
2782	else
2783	{
2784	AssertRelease(pVM->cCpus == 1);
2785
2786	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2787	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2788	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2789
2790	uint32_t cbRamSizeIgnored;
2791	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2792	if (RT_FAILURE(rc))
2793	return rc;
2794	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2795
2796	uint32_t u32 = 0;
2797	SSMR3GetUInt(pSSM, &u32);
2798	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2799	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2800	RTUINT uGuestMode;
2801	SSMR3GetUInt(pSSM, &uGuestMode);
2802	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2803
2804	/* check separator. */
2805	SSMR3GetU32(pSSM, &u32Sep);
2806	if (RT_FAILURE(rc))
2807	return rc;
2808	if (u32Sep != (uint32_t)~0)
2809	{
2810	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2811	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2812	}
2813	}
2814
2815	/*
2816	* The guest mappings - skipped now, see re-fixation in the caller.
2817	*/
2818	uint32_t i = 0;
2819	for (;; i++)
2820	{
2821	rc = SSMR3GetU32(pSSM, &u32Sep); /* seqence number */
2822	if (RT_FAILURE(rc))
2823	return rc;
2824	if (u32Sep == ~0U)
2825	break;
2826	AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2827
2828	char szDesc[256];
2829	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2830	if (RT_FAILURE(rc))
2831	return rc;
2832	RTGCPTR GCPtrIgnore;
2833	SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
2834	rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
2835	if (RT_FAILURE(rc))
2836	return rc;
2837	}
2838
2839	/*
2840	* Load the RAM contents.
2841	*/
2842	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2843	{
2844	if (!pVM->pgm.s.LiveSave.fActive)
2845	{
2846	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2847	{
2848	rc = pgmR3LoadRamConfig(pVM, pSSM);
2849	if (RT_FAILURE(rc))
2850	return rc;
2851	}
2852	rc = pgmR3LoadRomRanges(pVM, pSSM);
2853	if (RT_FAILURE(rc))
2854	return rc;
2855	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2856	if (RT_FAILURE(rc))
2857	return rc;
2858	}
2859
2860	rc = pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2861	}
2862	else
2863	rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2864	return rc;
2865	}
2866
2867
2868	/**
2869	* Execute state load operation.
2870	*
2871	* @returns VBox status code.
2872	* @param pVM VM Handle.
2873	* @param pSSM SSM operation handle.
2874	* @param uVersion Data layout version.
2875	* @param uPass The data pass.
2876	*/
2877	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2878	{
2879	int rc;
2880	PPGM pPGM = &pVM->pgm.s;
2881
2882	/*
2883	* Validate version.
2884	*/
2885	if ( ( uPass != SSM_PASS_FINAL
2886	&& uVersion != PGM_SAVED_STATE_VERSION
2887	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2888	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
2889	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
2890	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
2891	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
2892	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
2893	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2894	)
2895	{
2896	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
2897	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2898	}
2899
2900	/*
2901	* Do the loading while owning the lock because a bunch of the functions
2902	* we're using requires this.
2903	*/
2904	if (uPass != SSM_PASS_FINAL)
2905	{
2906	pgmLock(pVM);
2907	if (uPass != 0)
2908	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2909	else
2910	{
2911	pVM->pgm.s.LiveSave.fActive = true;
2912	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2913	rc = pgmR3LoadRamConfig(pVM, pSSM);
2914	else
2915	rc = VINF_SUCCESS;
2916	if (RT_SUCCESS(rc))
2917	rc = pgmR3LoadRomRanges(pVM, pSSM);
2918	if (RT_SUCCESS(rc))
2919	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2920	if (RT_SUCCESS(rc))
2921	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2922	}
2923	pgmUnlock(pVM);
2924	}
2925	else
2926	{
2927	pgmLock(pVM);
2928	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
2929	pVM->pgm.s.LiveSave.fActive = false;
2930	pgmUnlock(pVM);
2931	if (RT_SUCCESS(rc))
2932	{
2933	/*
2934	* We require a full resync now.
2935	*/
2936	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2937	{
2938	PVMCPU pVCpu = &pVM->aCpus[i];
2939	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2940	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2941	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2942	}
2943
2944	pgmR3HandlerPhysicalUpdateAll(pVM);
2945
2946	/*
2947	* Change the paging mode and restore PGMCPU::GCPhysCR3.
2948	* (The latter requires the CPUM state to be restored already.)
2949	*/
2950	if (CPUMR3IsStateRestorePending(pVM))
2951	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
2952	N_("PGM was unexpectedly restored before CPUM"));
2953
2954	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2955	{
2956	PVMCPU pVCpu = &pVM->aCpus[i];
2957
2958	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
2959	AssertLogRelRCReturn(rc, rc);
2960
2961	/* Restore pVM->pgm.s.GCPhysCR3. */
2962	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2963	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
2964	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
2965	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2966	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
2967	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2968	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2969	else
2970	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2971	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2972	}
2973
2974	/*
2975	* Try re-fixate the guest mappings.
2976	*/
2977	pVM->pgm.s.fMappingsFixedRestored = false;
2978	if ( pVM->pgm.s.fMappingsFixed
2979	&& pgmMapAreMappingsEnabled(&pVM->pgm.s))
2980	{
2981	RTGCPTR GCPtrFixed = pVM->pgm.s.GCPtrMappingFixed;
2982	uint32_t cbFixed = pVM->pgm.s.cbMappingFixed;
2983	pVM->pgm.s.fMappingsFixed = false;
2984
2985	uint32_t cbRequired;
2986	int rc2 = PGMR3MappingsSize(pVM, &cbRequired); AssertRC(rc2);
2987	if ( RT_SUCCESS(rc2)
2988	&& cbRequired > cbFixed)
2989	rc2 = VERR_OUT_OF_RANGE;
2990	if (RT_SUCCESS(rc2))
2991	rc2 = pgmR3MappingsFixInternal(pVM, GCPtrFixed, cbFixed);
2992	if (RT_FAILURE(rc2))
2993	{
2994	LogRel(("PGM: Unable to re-fixate the guest mappings at %RGv-%RGv: rc=%Rrc (cbRequired=%#x)\n",
2995	GCPtrFixed, GCPtrFixed + cbFixed, rc2, cbRequired));
2996	pVM->pgm.s.fMappingsFixed = false;
2997	pVM->pgm.s.fMappingsFixedRestored = true;
2998	pVM->pgm.s.GCPtrMappingFixed = GCPtrFixed;
2999	pVM->pgm.s.cbMappingFixed = cbFixed;
3000	}
3001	}
3002	else
3003	{
3004	/* We used to set fixed + disabled while we only use disabled now,
3005	so wipe the state to avoid any confusion. */
3006	pVM->pgm.s.fMappingsFixed = false;
3007	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
3008	pVM->pgm.s.cbMappingFixed = 0;
3009	}
3010
3011	/*
3012	* If we have floating mappings, do a CR3 sync now to make sure the HMA
3013	* doesn't conflict with guest code / data and thereby cause trouble
3014	* when restoring other components like PATM.
3015	*/
3016	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3017	{
3018	PVMCPU pVCpu = &pVM->aCpus[0];
3019	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
3020	if (RT_FAILURE(rc))
3021	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3022	N_("PGMSyncCR3 failed unexpectedly with rc=%Rrc"), rc);
3023
3024	/* Make sure to re-sync before executing code. */
3025	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3026	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3027	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3028	}
3029	}
3030	}
3031
3032	return rc;
3033	}
3034
3035
3036	/**
3037	* Registers the saved state callbacks with SSM.
3038	*
3039	* @returns VBox status code.
3040	* @param pVM Pointer to VM structure.
3041	* @param cbRam The RAM size.
3042	*/
3043	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3044	{
3045	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3046	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3047	NULL, pgmR3SaveExec, pgmR3SaveDone,
3048	pgmR3LoadPrep, pgmR3Load, NULL);
3049	}
3050

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source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 26638

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