VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 33980

Last change on this file since 33980 was 33780, checked in by vboxsync, 14 years ago

During state loading; don't free a zero page if it's part of a large page.
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1/* $Id: PGMSavedState.cpp 33780 2010-11-04 15:54:03Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, The Saved State Part.
4 */
5
6/*
7 * Copyright (C) 2006-2009 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM
23#include <VBox/pgm.h>
24#include <VBox/stam.h>
25#include <VBox/ssm.h>
26#include <VBox/pdmdrv.h>
27#include <VBox/pdmdev.h>
28#include "PGMInternal.h"
29#include <VBox/vm.h>
30#include "PGMInline.h"
31
32#include <VBox/param.h>
33#include <VBox/err.h>
34#include <VBox/ftm.h>
35
36#include <iprt/asm.h>
37#include <iprt/assert.h>
38#include <iprt/crc.h>
39#include <iprt/mem.h>
40#include <iprt/sha.h>
41#include <iprt/string.h>
42#include <iprt/thread.h>
43
44
45/*******************************************************************************
46* Defined Constants And Macros *
47*******************************************************************************/
48/** Saved state data unit version.
49 * @todo remove the guest mappings from the saved state at next version change! */
50#define PGM_SAVED_STATE_VERSION 12
51/** Saved state before the balloon change. */
52#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
53/** Saved state data unit version used during 3.1 development, misses the RAM
54 * config. */
55#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
56/** Saved state data unit version for 3.0 (pre teleportation). */
57#define PGM_SAVED_STATE_VERSION_3_0_0 9
58/** Saved state data unit version for 2.2.2 and later. */
59#define PGM_SAVED_STATE_VERSION_2_2_2 8
60/** Saved state data unit version for 2.2.0. */
61#define PGM_SAVED_STATE_VERSION_RR_DESC 7
62/** Saved state data unit version. */
63#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
64
65
66/** @name Sparse state record types
67 * @{ */
68/** Zero page. No data. */
69#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
70/** Raw page. */
71#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
72/** Raw MMIO2 page. */
73#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
74/** Zero MMIO2 page. */
75#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
76/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
77#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
78/** Raw shadowed ROM page. The protection (8-bit) precedes the raw bits. */
79#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
80/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
81#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
82/** ROM protection (8-bit). */
83#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
84/** The last record type. */
85#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
86/** End marker. */
87#define PGM_STATE_REC_END UINT8_C(0xff)
88/** Flag indicating that the data is preceded by the page address.
89 * For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
90 * range ID and a 32-bit page index.
91 */
92#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
93/** @} */
94
95/** The CRC-32 for a zero page. */
96#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
97/** The CRC-32 for a zero half page. */
98#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
99
100
101/*******************************************************************************
102* Structures and Typedefs *
103*******************************************************************************/
104/** For loading old saved states. (pre-smp) */
105typedef struct
106{
107 /** If set no conflict checks are required. (boolean) */
108 bool fMappingsFixed;
109 /** Size of fixed mapping */
110 uint32_t cbMappingFixed;
111 /** Base address (GC) of fixed mapping */
112 RTGCPTR GCPtrMappingFixed;
113 /** A20 gate mask.
114 * Our current approach to A20 emulation is to let REM do it and don't bother
115 * anywhere else. The interesting guests will be operating with it enabled anyway.
116 * But should the need arise, we'll subject physical addresses to this mask. */
117 RTGCPHYS GCPhysA20Mask;
118 /** A20 gate state - boolean! */
119 bool fA20Enabled;
120 /** The guest paging mode. */
121 PGMMODE enmGuestMode;
122} PGMOLD;
123
124
125/*******************************************************************************
126* Global Variables *
127*******************************************************************************/
128/** PGM fields to save/load. */
129
130static const SSMFIELD s_aPGMFields[] =
131{
132 SSMFIELD_ENTRY( PGM, fMappingsFixed),
133 SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
134 SSMFIELD_ENTRY( PGM, cbMappingFixed),
135 SSMFIELD_ENTRY( PGM, cBalloonedPages),
136 SSMFIELD_ENTRY_TERM()
137};
138
139static const SSMFIELD s_aPGMFieldsPreBalloon[] =
140{
141 SSMFIELD_ENTRY( PGM, fMappingsFixed),
142 SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
143 SSMFIELD_ENTRY( PGM, cbMappingFixed),
144 SSMFIELD_ENTRY_TERM()
145};
146
147static const SSMFIELD s_aPGMCpuFields[] =
148{
149 SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
150 SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
151 SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
152 SSMFIELD_ENTRY_TERM()
153};
154
155static const SSMFIELD s_aPGMFields_Old[] =
156{
157 SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
158 SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
159 SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
160 SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
161 SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
162 SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
163 SSMFIELD_ENTRY_TERM()
164};
165
166
167/**
168 * Find the ROM tracking structure for the given page.
169 *
170 * @returns Pointer to the ROM page structure. NULL if the caller didn't check
171 * that it's a ROM page.
172 * @param pVM The VM handle.
173 * @param GCPhys The address of the ROM page.
174 */
175static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
176{
177 for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
178 pRomRange;
179 pRomRange = pRomRange->CTX_SUFF(pNext))
180 {
181 RTGCPHYS off = GCPhys - pRomRange->GCPhys;
182 if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
183 return &pRomRange->aPages[off >> PAGE_SHIFT];
184 }
185 return NULL;
186}
187
188
189/**
190 * Prepares the ROM pages for a live save.
191 *
192 * @returns VBox status code.
193 * @param pVM The VM handle.
194 */
195static int pgmR3PrepRomPages(PVM pVM)
196{
197 /*
198 * Initialize the live save tracking in the ROM page descriptors.
199 */
200 pgmLock(pVM);
201 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
202 {
203 PPGMRAMRANGE pRamHint = NULL;;
204 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
205
206 for (uint32_t iPage = 0; iPage < cPages; iPage++)
207 {
208 pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
209 pRom->aPages[iPage].LiveSave.fWrittenTo = false;
210 pRom->aPages[iPage].LiveSave.fDirty = true;
211 pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
212 if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
213 {
214 if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
215 pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
216 else
217 {
218 RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
219 PPGMPAGE pPage;
220 int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
221 AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
222 if (RT_SUCCESS(rc))
223 pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage) && !PGM_PAGE_IS_BALLOONED(pPage);
224 else
225 pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
226 }
227 }
228 }
229
230 pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
231 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
232 pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
233 }
234 pgmUnlock(pVM);
235
236 return VINF_SUCCESS;
237}
238
239
240/**
241 * Assigns IDs to the ROM ranges and saves them.
242 *
243 * @returns VBox status code.
244 * @param pVM The VM handle.
245 * @param pSSM Saved state handle.
246 */
247static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
248{
249 pgmLock(pVM);
250 uint8_t id = 1;
251 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
252 {
253 pRom->idSavedState = id;
254 SSMR3PutU8(pSSM, id);
255 SSMR3PutStrZ(pSSM, ""); /* device name */
256 SSMR3PutU32(pSSM, 0); /* device instance */
257 SSMR3PutU8(pSSM, 0); /* region */
258 SSMR3PutStrZ(pSSM, pRom->pszDesc);
259 SSMR3PutGCPhys(pSSM, pRom->GCPhys);
260 int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
261 if (RT_FAILURE(rc))
262 break;
263 }
264 pgmUnlock(pVM);
265 return SSMR3PutU8(pSSM, UINT8_MAX);
266}
267
268
269/**
270 * Loads the ROM range ID assignments.
271 *
272 * @returns VBox status code.
273 *
274 * @param pVM The VM handle.
275 * @param pSSM The saved state handle.
276 */
277static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
278{
279 Assert(PGMIsLockOwner(pVM));
280
281 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
282 pRom->idSavedState = UINT8_MAX;
283
284 for (;;)
285 {
286 /*
287 * Read the data.
288 */
289 uint8_t id;
290 int rc = SSMR3GetU8(pSSM, &id);
291 if (RT_FAILURE(rc))
292 return rc;
293 if (id == UINT8_MAX)
294 {
295 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
296 AssertLogRelMsg(pRom->idSavedState != UINT8_MAX,
297 ("The \"%s\" ROM was not found in the saved state. Probably due to some misconfiguration\n",
298 pRom->pszDesc));
299 return VINF_SUCCESS; /* the end */
300 }
301 AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
302
303 char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
304 rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
305 AssertLogRelRCReturn(rc, rc);
306
307 uint32_t uInstance;
308 SSMR3GetU32(pSSM, &uInstance);
309 uint8_t iRegion;
310 SSMR3GetU8(pSSM, &iRegion);
311
312 char szDesc[64];
313 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
314 AssertLogRelRCReturn(rc, rc);
315
316 RTGCPHYS GCPhys;
317 SSMR3GetGCPhys(pSSM, &GCPhys);
318 RTGCPHYS cb;
319 rc = SSMR3GetGCPhys(pSSM, &cb);
320 if (RT_FAILURE(rc))
321 return rc;
322 AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
323 AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
324
325 /*
326 * Locate a matching ROM range.
327 */
328 AssertLogRelMsgReturn( uInstance == 0
329 && iRegion == 0
330 && szDevName[0] == '\0',
331 ("GCPhys=%RGp %s\n", GCPhys, szDesc),
332 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
333 PPGMROMRANGE pRom;
334 for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
335 {
336 if ( pRom->idSavedState == UINT8_MAX
337 && !strcmp(pRom->pszDesc, szDesc))
338 {
339 pRom->idSavedState = id;
340 break;
341 }
342 }
343 if (!pRom)
344 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
345 } /* forever */
346}
347
348
349/**
350 * Scan ROM pages.
351 *
352 * @param pVM The VM handle.
353 */
354static void pgmR3ScanRomPages(PVM pVM)
355{
356 /*
357 * The shadow ROMs.
358 */
359 pgmLock(pVM);
360 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
361 {
362 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
363 {
364 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
365 for (uint32_t iPage = 0; iPage < cPages; iPage++)
366 {
367 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
368 if (pRomPage->LiveSave.fWrittenTo)
369 {
370 pRomPage->LiveSave.fWrittenTo = false;
371 if (!pRomPage->LiveSave.fDirty)
372 {
373 pRomPage->LiveSave.fDirty = true;
374 pVM->pgm.s.LiveSave.Rom.cReadyPages--;
375 pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
376 }
377 pRomPage->LiveSave.fDirtiedRecently = true;
378 }
379 else
380 pRomPage->LiveSave.fDirtiedRecently = false;
381 }
382 }
383 }
384 pgmUnlock(pVM);
385}
386
387
388/**
389 * Takes care of the virgin ROM pages in the first pass.
390 *
391 * This is an attempt at simplifying the handling of ROM pages a little bit.
392 * This ASSUMES that no new ROM ranges will be added and that they won't be
393 * relinked in any way.
394 *
395 * @param pVM The VM handle.
396 * @param pSSM The SSM handle.
397 * @param fLiveSave Whether we're in a live save or not.
398 */
399static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
400{
401 if (FTMIsDeltaLoadSaveActive(pVM))
402 return VINF_SUCCESS; /* nothing to do as nothing has changed here */
403
404 pgmLock(pVM);
405 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
406 {
407 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
408 for (uint32_t iPage = 0; iPage < cPages; iPage++)
409 {
410 RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
411 PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
412
413 /* Get the virgin page descriptor. */
414 PPGMPAGE pPage;
415 if (PGMROMPROT_IS_ROM(enmProt))
416 pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
417 else
418 pPage = &pRom->aPages[iPage].Virgin;
419
420 /* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
421 int rc = VINF_SUCCESS;
422 char abPage[PAGE_SIZE];
423 if ( !PGM_PAGE_IS_ZERO(pPage)
424 && !PGM_PAGE_IS_BALLOONED(pPage))
425 {
426 void const *pvPage;
427 rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
428 if (RT_SUCCESS(rc))
429 memcpy(abPage, pvPage, PAGE_SIZE);
430 }
431 else
432 ASMMemZeroPage(abPage);
433 pgmUnlock(pVM);
434 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
435
436 /* Save it. */
437 if (iPage > 0)
438 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
439 else
440 {
441 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN | PGM_STATE_REC_FLAG_ADDR);
442 SSMR3PutU8(pSSM, pRom->idSavedState);
443 SSMR3PutU32(pSSM, iPage);
444 }
445 SSMR3PutU8(pSSM, (uint8_t)enmProt);
446 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
447 if (RT_FAILURE(rc))
448 return rc;
449
450 /* Update state. */
451 pgmLock(pVM);
452 pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
453 if (fLiveSave)
454 {
455 pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
456 pVM->pgm.s.LiveSave.Rom.cReadyPages++;
457 pVM->pgm.s.LiveSave.cSavedPages++;
458 }
459 }
460 }
461 pgmUnlock(pVM);
462 return VINF_SUCCESS;
463}
464
465
466/**
467 * Saves dirty pages in the shadowed ROM ranges.
468 *
469 * Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
470 *
471 * @returns VBox status code.
472 * @param pVM The VM handle.
473 * @param pSSM The SSM handle.
474 * @param fLiveSave Whether it's a live save or not.
475 * @param fFinalPass Whether this is the final pass or not.
476 */
477static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
478{
479 if (FTMIsDeltaLoadSaveActive(pVM))
480 return VINF_SUCCESS; /* nothing to do as we deal with those pages separately */
481
482 /*
483 * The Shadowed ROMs.
484 *
485 * ASSUMES that the ROM ranges are fixed.
486 * ASSUMES that all the ROM ranges are mapped.
487 */
488 pgmLock(pVM);
489 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
490 {
491 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
492 {
493 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
494 uint32_t iPrevPage = cPages;
495 for (uint32_t iPage = 0; iPage < cPages; iPage++)
496 {
497 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
498 if ( !fLiveSave
499 || ( pRomPage->LiveSave.fDirty
500 && ( ( !pRomPage->LiveSave.fDirtiedRecently
501 && !pRomPage->LiveSave.fWrittenTo)
502 || fFinalPass
503 )
504 )
505 )
506 {
507 uint8_t abPage[PAGE_SIZE];
508 PGMROMPROT enmProt = pRomPage->enmProt;
509 RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
510 PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
511 bool fZero = PGM_PAGE_IS_ZERO(pPage) || PGM_PAGE_IS_BALLOONED(pPage);
512 int rc = VINF_SUCCESS;
513 if (!fZero)
514 {
515 void const *pvPage;
516 rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
517 if (RT_SUCCESS(rc))
518 memcpy(abPage, pvPage, PAGE_SIZE);
519 }
520 if (fLiveSave && RT_SUCCESS(rc))
521 {
522 pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
523 pRomPage->LiveSave.fDirty = false;
524 pVM->pgm.s.LiveSave.Rom.cReadyPages++;
525 pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
526 pVM->pgm.s.LiveSave.cSavedPages++;
527 }
528 pgmUnlock(pVM);
529 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
530
531 if (iPage - 1U == iPrevPage && iPage > 0)
532 SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
533 else
534 {
535 SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) | PGM_STATE_REC_FLAG_ADDR);
536 SSMR3PutU8(pSSM, pRom->idSavedState);
537 SSMR3PutU32(pSSM, iPage);
538 }
539 rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
540 if (!fZero)
541 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
542 if (RT_FAILURE(rc))
543 return rc;
544
545 pgmLock(pVM);
546 iPrevPage = iPage;
547 }
548 /*
549 * In the final pass, make sure the protection is in sync.
550 */
551 else if ( fFinalPass
552 && pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
553 {
554 PGMROMPROT enmProt = pRomPage->enmProt;
555 pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
556 pgmUnlock(pVM);
557
558 if (iPage - 1U == iPrevPage && iPage > 0)
559 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
560 else
561 {
562 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT | PGM_STATE_REC_FLAG_ADDR);
563 SSMR3PutU8(pSSM, pRom->idSavedState);
564 SSMR3PutU32(pSSM, iPage);
565 }
566 int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
567 if (RT_FAILURE(rc))
568 return rc;
569
570 pgmLock(pVM);
571 iPrevPage = iPage;
572 }
573 }
574 }
575 }
576 pgmUnlock(pVM);
577 return VINF_SUCCESS;
578}
579
580
581/**
582 * Cleans up ROM pages after a live save.
583 *
584 * @param pVM The VM handle.
585 */
586static void pgmR3DoneRomPages(PVM pVM)
587{
588 NOREF(pVM);
589}
590
591
592/**
593 * Prepares the MMIO2 pages for a live save.
594 *
595 * @returns VBox status code.
596 * @param pVM The VM handle.
597 */
598static int pgmR3PrepMmio2Pages(PVM pVM)
599{
600 /*
601 * Initialize the live save tracking in the MMIO2 ranges.
602 * ASSUME nothing changes here.
603 */
604 pgmLock(pVM);
605 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
606 {
607 uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
608 pgmUnlock(pVM);
609
610 PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
611 if (!paLSPages)
612 return VERR_NO_MEMORY;
613 for (uint32_t iPage = 0; iPage < cPages; iPage++)
614 {
615 /* Initialize it as a dirty zero page. */
616 paLSPages[iPage].fDirty = true;
617 paLSPages[iPage].cUnchangedScans = 0;
618 paLSPages[iPage].fZero = true;
619 paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
620 paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
621 }
622
623 pgmLock(pVM);
624 pMmio2->paLSPages = paLSPages;
625 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
626 }
627 pgmUnlock(pVM);
628 return VINF_SUCCESS;
629}
630
631
632/**
633 * Assigns IDs to the MMIO2 ranges and saves them.
634 *
635 * @returns VBox status code.
636 * @param pVM The VM handle.
637 * @param pSSM Saved state handle.
638 */
639static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
640{
641 pgmLock(pVM);
642 uint8_t id = 1;
643 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
644 {
645 pMmio2->idSavedState = id;
646 SSMR3PutU8(pSSM, id);
647 SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pReg->szName);
648 SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
649 SSMR3PutU8(pSSM, pMmio2->iRegion);
650 SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
651 int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
652 if (RT_FAILURE(rc))
653 break;
654 }
655 pgmUnlock(pVM);
656 return SSMR3PutU8(pSSM, UINT8_MAX);
657}
658
659
660/**
661 * Loads the MMIO2 range ID assignments.
662 *
663 * @returns VBox status code.
664 *
665 * @param pVM The VM handle.
666 * @param pSSM The saved state handle.
667 */
668static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
669{
670 Assert(PGMIsLockOwner(pVM));
671
672 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
673 pMmio2->idSavedState = UINT8_MAX;
674
675 for (;;)
676 {
677 /*
678 * Read the data.
679 */
680 uint8_t id;
681 int rc = SSMR3GetU8(pSSM, &id);
682 if (RT_FAILURE(rc))
683 return rc;
684 if (id == UINT8_MAX)
685 {
686 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
687 AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
688 return VINF_SUCCESS; /* the end */
689 }
690 AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
691
692 char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
693 rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
694 AssertLogRelRCReturn(rc, rc);
695
696 uint32_t uInstance;
697 SSMR3GetU32(pSSM, &uInstance);
698 uint8_t iRegion;
699 SSMR3GetU8(pSSM, &iRegion);
700
701 char szDesc[64];
702 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
703 AssertLogRelRCReturn(rc, rc);
704
705 RTGCPHYS cb;
706 rc = SSMR3GetGCPhys(pSSM, &cb);
707 AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
708
709 /*
710 * Locate a matching MMIO2 range.
711 */
712 PPGMMMIO2RANGE pMmio2;
713 for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
714 {
715 if ( pMmio2->idSavedState == UINT8_MAX
716 && pMmio2->iRegion == iRegion
717 && pMmio2->pDevInsR3->iInstance == uInstance
718 && !strcmp(pMmio2->pDevInsR3->pReg->szName, szDevName))
719 {
720 pMmio2->idSavedState = id;
721 break;
722 }
723 }
724 if (!pMmio2)
725 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
726 szDesc, szDevName, uInstance, iRegion);
727
728 /*
729 * Validate the configuration, the size of the MMIO2 region should be
730 * the same.
731 */
732 if (cb != pMmio2->RamRange.cb)
733 {
734 LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
735 pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
736 if (cb > pMmio2->RamRange.cb) /* bad idea? */
737 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
738 pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
739 }
740 } /* forever */
741}
742
743
744/**
745 * Scans one MMIO2 page.
746 *
747 * @returns True if changed, false if unchanged.
748 *
749 * @param pVM The VM handle
750 * @param pbPage The page bits.
751 * @param pLSPage The live save tracking structure for the page.
752 *
753 */
754DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
755{
756 /*
757 * Special handling of zero pages.
758 */
759 bool const fZero = pLSPage->fZero;
760 if (fZero)
761 {
762 if (ASMMemIsZeroPage(pbPage))
763 {
764 /* Not modified. */
765 if (pLSPage->fDirty)
766 pLSPage->cUnchangedScans++;
767 return false;
768 }
769
770 pLSPage->fZero = false;
771 pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
772 }
773 else
774 {
775 /*
776 * CRC the first half, if it doesn't match the page is dirty and
777 * we won't check the 2nd half (we'll do that next time).
778 */
779 uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
780 if (u32CrcH1 == pLSPage->u32CrcH1)
781 {
782 uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
783 if (u32CrcH2 == pLSPage->u32CrcH2)
784 {
785 /* Probably not modified. */
786 if (pLSPage->fDirty)
787 pLSPage->cUnchangedScans++;
788 return false;
789 }
790
791 pLSPage->u32CrcH2 = u32CrcH2;
792 }
793 else
794 {
795 pLSPage->u32CrcH1 = u32CrcH1;
796 if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
797 && ASMMemIsZeroPage(pbPage))
798 {
799 pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
800 pLSPage->fZero = true;
801 }
802 }
803 }
804
805 /* dirty page path */
806 pLSPage->cUnchangedScans = 0;
807 if (!pLSPage->fDirty)
808 {
809 pLSPage->fDirty = true;
810 pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
811 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
812 if (fZero)
813 pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
814 }
815 return true;
816}
817
818
819/**
820 * Scan for MMIO2 page modifications.
821 *
822 * @param pVM The VM handle.
823 * @param uPass The pass number.
824 */
825static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
826{
827 /*
828 * Since this is a bit expensive we lower the scan rate after a little while.
829 */
830 if ( ( (uPass & 3) != 0
831 && uPass > 10)
832 || uPass == SSM_PASS_FINAL)
833 return;
834
835 pgmLock(pVM); /* paranoia */
836 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
837 {
838 PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
839 uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
840 pgmUnlock(pVM);
841
842 for (uint32_t iPage = 0; iPage < cPages; iPage++)
843 {
844 uint8_t const *pbPage = (uint8_t const *)pMmio2->pvR3 + iPage * PAGE_SIZE;
845 pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
846 }
847
848 pgmLock(pVM);
849 }
850 pgmUnlock(pVM);
851
852}
853
854
855/**
856 * Save quiescent MMIO2 pages.
857 *
858 * @returns VBox status code.
859 * @param pVM The VM handle.
860 * @param pSSM The SSM handle.
861 * @param fLiveSave Whether it's a live save or not.
862 * @param uPass The pass number.
863 */
864static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
865{
866 /** @todo implement live saving of MMIO2 pages. (Need some way of telling the
867 * device that we wish to know about changes.) */
868
869 int rc = VINF_SUCCESS;
870 if (uPass == SSM_PASS_FINAL)
871 {
872 /*
873 * The mop up round.
874 */
875 pgmLock(pVM);
876 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
877 pMmio2 && RT_SUCCESS(rc);
878 pMmio2 = pMmio2->pNextR3)
879 {
880 PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
881 uint8_t const *pbPage = (uint8_t const *)pMmio2->RamRange.pvR3;
882 uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
883 uint32_t iPageLast = cPages;
884 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
885 {
886 uint8_t u8Type;
887 if (!fLiveSave)
888 u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
889 else
890 {
891 /* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
892 if ( !paLSPages[iPage].fDirty
893 && !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
894 {
895 if (paLSPages[iPage].fZero)
896 continue;
897
898 uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
899 RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
900 if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
901 continue;
902 }
903 u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
904 pVM->pgm.s.LiveSave.cSavedPages++;
905 }
906
907 if (iPage != 0 && iPage == iPageLast + 1)
908 rc = SSMR3PutU8(pSSM, u8Type);
909 else
910 {
911 SSMR3PutU8(pSSM, u8Type | PGM_STATE_REC_FLAG_ADDR);
912 SSMR3PutU8(pSSM, pMmio2->idSavedState);
913 rc = SSMR3PutU32(pSSM, iPage);
914 }
915 if (u8Type == PGM_STATE_REC_MMIO2_RAW)
916 rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
917 if (RT_FAILURE(rc))
918 break;
919 iPageLast = iPage;
920 }
921 }
922 pgmUnlock(pVM);
923 }
924 /*
925 * Reduce the rate after a little while since the current MMIO2 approach is
926 * a bit expensive.
927 * We position it two passes after the scan pass to avoid saving busy pages.
928 */
929 else if ( uPass <= 10
930 || (uPass & 3) == 2)
931 {
932 pgmLock(pVM);
933 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
934 pMmio2 && RT_SUCCESS(rc);
935 pMmio2 = pMmio2->pNextR3)
936 {
937 PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
938 uint8_t const *pbPage = (uint8_t const *)pMmio2->RamRange.pvR3;
939 uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
940 uint32_t iPageLast = cPages;
941 pgmUnlock(pVM);
942
943 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
944 {
945 /* Skip clean pages and pages which hasn't quiesced. */
946 if (!paLSPages[iPage].fDirty)
947 continue;
948 if (paLSPages[iPage].cUnchangedScans < 3)
949 continue;
950 if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
951 continue;
952
953 /* Save it. */
954 bool const fZero = paLSPages[iPage].fZero;
955 uint8_t abPage[PAGE_SIZE];
956 if (!fZero)
957 {
958 memcpy(abPage, pbPage, PAGE_SIZE);
959 RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
960 }
961
962 uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
963 if (iPage != 0 && iPage == iPageLast + 1)
964 rc = SSMR3PutU8(pSSM, u8Type);
965 else
966 {
967 SSMR3PutU8(pSSM, u8Type | PGM_STATE_REC_FLAG_ADDR);
968 SSMR3PutU8(pSSM, pMmio2->idSavedState);
969 rc = SSMR3PutU32(pSSM, iPage);
970 }
971 if (u8Type == PGM_STATE_REC_MMIO2_RAW)
972 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
973 if (RT_FAILURE(rc))
974 break;
975
976 /* Housekeeping. */
977 paLSPages[iPage].fDirty = false;
978 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
979 pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
980 if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
981 pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
982 pVM->pgm.s.LiveSave.cSavedPages++;
983 iPageLast = iPage;
984 }
985
986 pgmLock(pVM);
987 }
988 pgmUnlock(pVM);
989 }
990
991 return rc;
992}
993
994
995/**
996 * Cleans up MMIO2 pages after a live save.
997 *
998 * @param pVM The VM handle.
999 */
1000static void pgmR3DoneMmio2Pages(PVM pVM)
1001{
1002 /*
1003 * Free the tracking structures for the MMIO2 pages.
1004 * We do the freeing outside the lock in case the VM is running.
1005 */
1006 pgmLock(pVM);
1007 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
1008 {
1009 void *pvMmio2ToFree = pMmio2->paLSPages;
1010 if (pvMmio2ToFree)
1011 {
1012 pMmio2->paLSPages = NULL;
1013 pgmUnlock(pVM);
1014 MMR3HeapFree(pvMmio2ToFree);
1015 pgmLock(pVM);
1016 }
1017 }
1018 pgmUnlock(pVM);
1019}
1020
1021
1022/**
1023 * Prepares the RAM pages for a live save.
1024 *
1025 * @returns VBox status code.
1026 * @param pVM The VM handle.
1027 */
1028static int pgmR3PrepRamPages(PVM pVM)
1029{
1030
1031 /*
1032 * Try allocating tracking structures for the ram ranges.
1033 *
1034 * To avoid lock contention, we leave the lock every time we're allocating
1035 * a new array. This means we'll have to ditch the allocation and start
1036 * all over again if the RAM range list changes in-between.
1037 *
1038 * Note! pgmR3SaveDone will always be called and it is therefore responsible
1039 * for cleaning up.
1040 */
1041 PPGMRAMRANGE pCur;
1042 pgmLock(pVM);
1043 do
1044 {
1045 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1046 {
1047 if ( !pCur->paLSPages
1048 && !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1049 {
1050 uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1051 uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1052 pgmUnlock(pVM);
1053 PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1054 if (!paLSPages)
1055 return VERR_NO_MEMORY;
1056 pgmLock(pVM);
1057 if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1058 {
1059 pgmUnlock(pVM);
1060 MMR3HeapFree(paLSPages);
1061 pgmLock(pVM);
1062 break; /* try again */
1063 }
1064 pCur->paLSPages = paLSPages;
1065
1066 /*
1067 * Initialize the array.
1068 */
1069 uint32_t iPage = cPages;
1070 while (iPage-- > 0)
1071 {
1072 /** @todo yield critsect! (after moving this away from EMT0) */
1073 PCPGMPAGE pPage = &pCur->aPages[iPage];
1074 paLSPages[iPage].cDirtied = 0;
1075 paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1076 paLSPages[iPage].fWriteMonitored = 0;
1077 paLSPages[iPage].fWriteMonitoredJustNow = 0;
1078 paLSPages[iPage].u2Reserved = 0;
1079 switch (PGM_PAGE_GET_TYPE(pPage))
1080 {
1081 case PGMPAGETYPE_RAM:
1082 if ( PGM_PAGE_IS_ZERO(pPage)
1083 || PGM_PAGE_IS_BALLOONED(pPage))
1084 {
1085 paLSPages[iPage].fZero = 1;
1086 paLSPages[iPage].fShared = 0;
1087#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1088 paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1089#endif
1090 }
1091 else if (PGM_PAGE_IS_SHARED(pPage))
1092 {
1093 paLSPages[iPage].fZero = 0;
1094 paLSPages[iPage].fShared = 1;
1095#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1096 paLSPages[iPage].u32Crc = UINT32_MAX;
1097#endif
1098 }
1099 else
1100 {
1101 paLSPages[iPage].fZero = 0;
1102 paLSPages[iPage].fShared = 0;
1103#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1104 paLSPages[iPage].u32Crc = UINT32_MAX;
1105#endif
1106 }
1107 paLSPages[iPage].fIgnore = 0;
1108 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1109 break;
1110
1111 case PGMPAGETYPE_ROM_SHADOW:
1112 case PGMPAGETYPE_ROM:
1113 {
1114 paLSPages[iPage].fZero = 0;
1115 paLSPages[iPage].fShared = 0;
1116 paLSPages[iPage].fDirty = 0;
1117 paLSPages[iPage].fIgnore = 1;
1118#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1119 paLSPages[iPage].u32Crc = UINT32_MAX;
1120#endif
1121 pVM->pgm.s.LiveSave.cIgnoredPages++;
1122 break;
1123 }
1124
1125 default:
1126 AssertMsgFailed(("%R[pgmpage]", pPage));
1127 case PGMPAGETYPE_MMIO2:
1128 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1129 paLSPages[iPage].fZero = 0;
1130 paLSPages[iPage].fShared = 0;
1131 paLSPages[iPage].fDirty = 0;
1132 paLSPages[iPage].fIgnore = 1;
1133#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1134 paLSPages[iPage].u32Crc = UINT32_MAX;
1135#endif
1136 pVM->pgm.s.LiveSave.cIgnoredPages++;
1137 break;
1138
1139 case PGMPAGETYPE_MMIO:
1140 paLSPages[iPage].fZero = 0;
1141 paLSPages[iPage].fShared = 0;
1142 paLSPages[iPage].fDirty = 0;
1143 paLSPages[iPage].fIgnore = 1;
1144#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1145 paLSPages[iPage].u32Crc = UINT32_MAX;
1146#endif
1147 pVM->pgm.s.LiveSave.cIgnoredPages++;
1148 break;
1149 }
1150 }
1151 }
1152 }
1153 } while (pCur);
1154 pgmUnlock(pVM);
1155
1156 return VINF_SUCCESS;
1157}
1158
1159
1160/**
1161 * Saves the RAM configuration.
1162 *
1163 * @returns VBox status code.
1164 * @param pVM The VM handle.
1165 * @param pSSM The saved state handle.
1166 */
1167static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1168{
1169 uint32_t cbRamHole = 0;
1170 int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1171 AssertRCReturn(rc, rc);
1172
1173 uint64_t cbRam = 0;
1174 rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1175 AssertRCReturn(rc, rc);
1176
1177 SSMR3PutU32(pSSM, cbRamHole);
1178 return SSMR3PutU64(pSSM, cbRam);
1179}
1180
1181
1182/**
1183 * Loads and verifies the RAM configuration.
1184 *
1185 * @returns VBox status code.
1186 * @param pVM The VM handle.
1187 * @param pSSM The saved state handle.
1188 */
1189static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1190{
1191 uint32_t cbRamHoleCfg = 0;
1192 int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1193 AssertRCReturn(rc, rc);
1194
1195 uint64_t cbRamCfg = 0;
1196 rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1197 AssertRCReturn(rc, rc);
1198
1199 uint32_t cbRamHoleSaved;
1200 SSMR3GetU32(pSSM, &cbRamHoleSaved);
1201
1202 uint64_t cbRamSaved;
1203 rc = SSMR3GetU64(pSSM, &cbRamSaved);
1204 AssertRCReturn(rc, rc);
1205
1206 if ( cbRamHoleCfg != cbRamHoleSaved
1207 || cbRamCfg != cbRamSaved)
1208 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1209 cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1210 return VINF_SUCCESS;
1211}
1212
1213#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1214
1215/**
1216 * Calculates the CRC-32 for a RAM page and updates the live save page tracking
1217 * info with it.
1218 *
1219 * @param pVM The VM handle.
1220 * @param pCur The current RAM range.
1221 * @param paLSPages The current array of live save page tracking
1222 * structures.
1223 * @param iPage The page index.
1224 */
1225static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1226{
1227 RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1228 void const *pvPage;
1229 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1230 if (RT_SUCCESS(rc))
1231 paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1232 else
1233 paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1234}
1235
1236
1237/**
1238 * Verifies the CRC-32 for a page given it's raw bits.
1239 *
1240 * @param pvPage The page bits.
1241 * @param pCur The current RAM range.
1242 * @param paLSPages The current array of live save page tracking
1243 * structures.
1244 * @param iPage The page index.
1245 */
1246static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char *pszWhere)
1247{
1248 if (paLSPages[iPage].u32Crc != UINT32_MAX)
1249 {
1250 uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1251 Assert( ( !PGM_PAGE_IS_ZERO(&pCur->aPages[iPage])
1252 && !PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]))
1253 || u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1254 AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1255 ("%08x != %08x for %RGp %R[pgmpage] %s\n", paLSPages[iPage].u32Crc, u32Crc,
1256 pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage], pszWhere));
1257 }
1258}
1259
1260
1261/**
1262 * Verifies the CRC-32 for a RAM page.
1263 *
1264 * @param pVM The VM handle.
1265 * @param pCur The current RAM range.
1266 * @param paLSPages The current array of live save page tracking
1267 * structures.
1268 * @param iPage The page index.
1269 */
1270static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char *pszWhere)
1271{
1272 if (paLSPages[iPage].u32Crc != UINT32_MAX)
1273 {
1274 RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1275 void const *pvPage;
1276 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1277 if (RT_SUCCESS(rc))
1278 pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage, pszWhere);
1279 }
1280}
1281
1282#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1283
1284/**
1285 * Scan for RAM page modifications and reprotect them.
1286 *
1287 * @param pVM The VM handle.
1288 * @param fFinalPass Whether this is the final pass or not.
1289 */
1290static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1291{
1292 /*
1293 * The RAM.
1294 */
1295 RTGCPHYS GCPhysCur = 0;
1296 PPGMRAMRANGE pCur;
1297 pgmLock(pVM);
1298 do
1299 {
1300 uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1301 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1302 {
1303 if ( pCur->GCPhysLast > GCPhysCur
1304 && !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1305 {
1306 PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1307 uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1308 uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1309 GCPhysCur = 0;
1310 for (; iPage < cPages; iPage++)
1311 {
1312 /* Do yield first. */
1313 if ( !fFinalPass
1314#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1315 && (iPage & 0x7ff) == 0x100
1316#endif
1317 && PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1318 && pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1319 {
1320 GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1321 break; /* restart */
1322 }
1323
1324 /* Skip already ignored pages. */
1325 if (paLSPages[iPage].fIgnore)
1326 continue;
1327
1328 if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1329 {
1330 /*
1331 * A RAM page.
1332 */
1333 switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1334 {
1335 case PGM_PAGE_STATE_ALLOCATED:
1336 /** @todo Optimize this: Don't always re-enable write
1337 * monitoring if the page is known to be very busy. */
1338 if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1339 {
1340 Assert(paLSPages[iPage].fWriteMonitored);
1341 PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1342 Assert(pVM->pgm.s.cWrittenToPages > 0);
1343 pVM->pgm.s.cWrittenToPages--;
1344 }
1345 else
1346 {
1347 Assert(!paLSPages[iPage].fWriteMonitored);
1348 pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1349 }
1350
1351 if (!paLSPages[iPage].fDirty)
1352 {
1353 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1354 if (paLSPages[iPage].fZero)
1355 pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1356 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1357 if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1358 paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1359 }
1360
1361 PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1362 pVM->pgm.s.cMonitoredPages++;
1363 paLSPages[iPage].fWriteMonitored = 1;
1364 paLSPages[iPage].fWriteMonitoredJustNow = 1;
1365 paLSPages[iPage].fDirty = 1;
1366 paLSPages[iPage].fZero = 0;
1367 paLSPages[iPage].fShared = 0;
1368#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1369 paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1370#endif
1371 break;
1372
1373 case PGM_PAGE_STATE_WRITE_MONITORED:
1374 Assert(paLSPages[iPage].fWriteMonitored);
1375 if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1376 {
1377#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1378 if (paLSPages[iPage].fWriteMonitoredJustNow)
1379 pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1380 else
1381 pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "scan");
1382#endif
1383 paLSPages[iPage].fWriteMonitoredJustNow = 0;
1384 }
1385 else
1386 {
1387 paLSPages[iPage].fWriteMonitoredJustNow = 1;
1388#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1389 paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1390#endif
1391 if (!paLSPages[iPage].fDirty)
1392 {
1393 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1394 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1395 if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1396 paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1397 }
1398 }
1399 break;
1400
1401 case PGM_PAGE_STATE_ZERO:
1402 if (!paLSPages[iPage].fZero)
1403 {
1404 if (!paLSPages[iPage].fDirty)
1405 {
1406 paLSPages[iPage].fDirty = 1;
1407 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1408 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1409 }
1410 paLSPages[iPage].fZero = 1;
1411 paLSPages[iPage].fShared = 0;
1412#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1413 paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1414#endif
1415 }
1416 break;
1417
1418 case PGM_PAGE_STATE_BALLOONED:
1419 if (!paLSPages[iPage].fZero)
1420 {
1421 if (!paLSPages[iPage].fDirty)
1422 {
1423 paLSPages[iPage].fDirty = 1;
1424 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1425 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1426 }
1427 paLSPages[iPage].fZero = 1;
1428 paLSPages[iPage].fShared = 0;
1429#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1430 paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1431#endif
1432 }
1433 break;
1434
1435 case PGM_PAGE_STATE_SHARED:
1436 if (!paLSPages[iPage].fShared)
1437 {
1438 if (!paLSPages[iPage].fDirty)
1439 {
1440 paLSPages[iPage].fDirty = 1;
1441 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1442 if (paLSPages[iPage].fZero)
1443 pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1444 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1445 }
1446 paLSPages[iPage].fZero = 0;
1447 paLSPages[iPage].fShared = 1;
1448#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1449 pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1450#endif
1451 }
1452 break;
1453 }
1454 }
1455 else
1456 {
1457 /*
1458 * All other types => Ignore the page.
1459 */
1460 Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1461 paLSPages[iPage].fIgnore = 1;
1462 if (paLSPages[iPage].fWriteMonitored)
1463 {
1464 /** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1465 * pages! */
1466 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1467 {
1468 AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1469 PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1470 Assert(pVM->pgm.s.cMonitoredPages > 0);
1471 pVM->pgm.s.cMonitoredPages--;
1472 }
1473 if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1474 {
1475 PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1476 Assert(pVM->pgm.s.cWrittenToPages > 0);
1477 pVM->pgm.s.cWrittenToPages--;
1478 }
1479 pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1480 }
1481
1482 /** @todo the counting doesn't quite work out here. fix later? */
1483 if (paLSPages[iPage].fDirty)
1484 pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1485 else
1486 {
1487 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1488 if (paLSPages[iPage].fZero)
1489 pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1490 }
1491 pVM->pgm.s.LiveSave.cIgnoredPages++;
1492 }
1493 } /* for each page in range */
1494
1495 if (GCPhysCur != 0)
1496 break; /* Yield + ramrange change */
1497 GCPhysCur = pCur->GCPhysLast;
1498 }
1499 } /* for each range */
1500 } while (pCur);
1501 pgmUnlock(pVM);
1502}
1503
1504
1505/**
1506 * Save quiescent RAM pages.
1507 *
1508 * @returns VBox status code.
1509 * @param pVM The VM handle.
1510 * @param pSSM The SSM handle.
1511 * @param fLiveSave Whether it's a live save or not.
1512 * @param uPass The pass number.
1513 */
1514static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1515{
1516 /*
1517 * The RAM.
1518 */
1519 RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1520 RTGCPHYS GCPhysCur = 0;
1521 PPGMRAMRANGE pCur;
1522 bool fFTMDeltaSaveActive = FTMIsDeltaLoadSaveActive(pVM);
1523
1524 pgmLock(pVM);
1525 do
1526 {
1527 uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1528 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1529 {
1530 if ( pCur->GCPhysLast > GCPhysCur
1531 && !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1532 {
1533 PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1534 uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1535 uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1536 GCPhysCur = 0;
1537 for (; iPage < cPages; iPage++)
1538 {
1539 /* Do yield first. */
1540 if ( uPass != SSM_PASS_FINAL
1541 && (iPage & 0x7ff) == 0x100
1542 && PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1543 && pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1544 {
1545 GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1546 break; /* restart */
1547 }
1548
1549 PPGMPAGE pCurPage = &pCur->aPages[iPage];
1550
1551 /*
1552 * Only save pages that haven't changed since last scan and are dirty.
1553 */
1554 if ( uPass != SSM_PASS_FINAL
1555 && paLSPages)
1556 {
1557 if (!paLSPages[iPage].fDirty)
1558 continue;
1559 if (paLSPages[iPage].fWriteMonitoredJustNow)
1560 continue;
1561 if (paLSPages[iPage].fIgnore)
1562 continue;
1563 if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM) /* in case of recent remappings */
1564 continue;
1565 if ( PGM_PAGE_GET_STATE(pCurPage)
1566 != ( paLSPages[iPage].fZero
1567 ? PGM_PAGE_STATE_ZERO
1568 : paLSPages[iPage].fShared
1569 ? PGM_PAGE_STATE_SHARED
1570 : PGM_PAGE_STATE_WRITE_MONITORED))
1571 continue;
1572 if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1573 continue;
1574 }
1575 else
1576 {
1577 if ( paLSPages
1578 && !paLSPages[iPage].fDirty
1579 && !paLSPages[iPage].fIgnore)
1580 {
1581#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1582 if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1583 pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#1");
1584#endif
1585 continue;
1586 }
1587 if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1588 continue;
1589 }
1590
1591 /*
1592 * Do the saving outside the PGM critsect since SSM may block on I/O.
1593 */
1594 int rc;
1595 RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1596 bool fZero = PGM_PAGE_IS_ZERO(pCurPage) || PGM_PAGE_IS_BALLOONED(pCurPage);
1597 bool fSkipped = false;
1598
1599 if (!fZero)
1600 {
1601 /*
1602 * Copy the page and then save it outside the lock (since any
1603 * SSM call may block).
1604 */
1605 uint8_t abPage[PAGE_SIZE];
1606 void const *pvPage;
1607 rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pCurPage, GCPhys, &pvPage);
1608 if (RT_SUCCESS(rc))
1609 {
1610 memcpy(abPage, pvPage, PAGE_SIZE);
1611#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1612 if (paLSPages)
1613 pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage, "save#3");
1614#endif
1615 }
1616 pgmUnlock(pVM);
1617 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1618
1619 /* Try save some memory when restoring. */
1620 if (!ASMMemIsZeroPage(pvPage))
1621 {
1622 if (fFTMDeltaSaveActive)
1623 {
1624 if ( PGM_PAGE_IS_WRITTEN_TO(pCurPage)
1625 || PGM_PAGE_IS_FT_DIRTY(pCurPage))
1626 {
1627 if (GCPhys == GCPhysLast + PAGE_SIZE)
1628 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1629 else
1630 {
1631 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW | PGM_STATE_REC_FLAG_ADDR);
1632 SSMR3PutGCPhys(pSSM, GCPhys);
1633 }
1634 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1635 PGM_PAGE_CLEAR_WRITTEN_TO(pCurPage);
1636 PGM_PAGE_CLEAR_FT_DIRTY(pCurPage);
1637 }
1638 /* else nothing changed, so skip it. */
1639 else
1640 fSkipped = true;
1641 }
1642 else
1643 {
1644 if (GCPhys == GCPhysLast + PAGE_SIZE)
1645 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1646 else
1647 {
1648 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW | PGM_STATE_REC_FLAG_ADDR);
1649 SSMR3PutGCPhys(pSSM, GCPhys);
1650 }
1651 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1652 }
1653 }
1654 else
1655 {
1656 if (GCPhys == GCPhysLast + PAGE_SIZE)
1657 rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1658 else
1659 {
1660 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO | PGM_STATE_REC_FLAG_ADDR);
1661 rc = SSMR3PutGCPhys(pSSM, GCPhys);
1662 }
1663 }
1664 }
1665 else
1666 {
1667 /*
1668 * Dirty zero page.
1669 */
1670#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1671 if (paLSPages)
1672 pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#2");
1673#endif
1674 pgmUnlock(pVM);
1675
1676 if (GCPhys == GCPhysLast + PAGE_SIZE)
1677 rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1678 else
1679 {
1680 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO | PGM_STATE_REC_FLAG_ADDR);
1681 rc = SSMR3PutGCPhys(pSSM, GCPhys);
1682 }
1683 }
1684 if (RT_FAILURE(rc))
1685 return rc;
1686
1687 pgmLock(pVM);
1688 if (!fSkipped)
1689 GCPhysLast = GCPhys;
1690 if (paLSPages)
1691 {
1692 paLSPages[iPage].fDirty = 0;
1693 pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1694 if (fZero)
1695 pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1696 pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1697 pVM->pgm.s.LiveSave.cSavedPages++;
1698 }
1699 if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1700 {
1701 GCPhysCur = GCPhys | PAGE_OFFSET_MASK;
1702 break; /* restart */
1703 }
1704
1705 } /* for each page in range */
1706
1707 if (GCPhysCur != 0)
1708 break; /* Yield + ramrange change */
1709 GCPhysCur = pCur->GCPhysLast;
1710 }
1711 } /* for each range */
1712 } while (pCur);
1713
1714 pgmUnlock(pVM);
1715
1716 return VINF_SUCCESS;
1717}
1718
1719
1720/**
1721 * Cleans up RAM pages after a live save.
1722 *
1723 * @param pVM The VM handle.
1724 */
1725static void pgmR3DoneRamPages(PVM pVM)
1726{
1727 /*
1728 * Free the tracking arrays and disable write monitoring.
1729 *
1730 * Play nice with the PGM lock in case we're called while the VM is still
1731 * running. This means we have to delay the freeing since we wish to use
1732 * paLSPages as an indicator of which RAM ranges which we need to scan for
1733 * write monitored pages.
1734 */
1735 void *pvToFree = NULL;
1736 PPGMRAMRANGE pCur;
1737 uint32_t cMonitoredPages = 0;
1738 pgmLock(pVM);
1739 do
1740 {
1741 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1742 {
1743 if (pCur->paLSPages)
1744 {
1745 if (pvToFree)
1746 {
1747 uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1748 pgmUnlock(pVM);
1749 MMR3HeapFree(pvToFree);
1750 pvToFree = NULL;
1751 pgmLock(pVM);
1752 if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1753 break; /* start over again. */
1754 }
1755
1756 pvToFree = pCur->paLSPages;
1757 pCur->paLSPages = NULL;
1758
1759 uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1760 while (iPage--)
1761 {
1762 PPGMPAGE pPage = &pCur->aPages[iPage];
1763 PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1764 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1765 {
1766 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1767 cMonitoredPages++;
1768 }
1769 }
1770 }
1771 }
1772 } while (pCur);
1773
1774 Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1775 if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1776 pVM->pgm.s.cMonitoredPages = 0;
1777 else
1778 pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1779
1780 pgmUnlock(pVM);
1781
1782 MMR3HeapFree(pvToFree);
1783 pvToFree = NULL;
1784}
1785
1786
1787/**
1788 * Execute a live save pass.
1789 *
1790 * @returns VBox status code.
1791 *
1792 * @param pVM The VM handle.
1793 * @param pSSM The SSM handle.
1794 */
1795static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1796{
1797 int rc;
1798
1799 /*
1800 * Save the MMIO2 and ROM range IDs in pass 0.
1801 */
1802 if (uPass == 0)
1803 {
1804 rc = pgmR3SaveRamConfig(pVM, pSSM);
1805 if (RT_FAILURE(rc))
1806 return rc;
1807 rc = pgmR3SaveRomRanges(pVM, pSSM);
1808 if (RT_FAILURE(rc))
1809 return rc;
1810 rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1811 if (RT_FAILURE(rc))
1812 return rc;
1813 }
1814 /*
1815 * Reset the page-per-second estimate to avoid inflation by the initial
1816 * load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1817 */
1818 else if (uPass == 7)
1819 {
1820 pVM->pgm.s.LiveSave.cSavedPages = 0;
1821 pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1822 }
1823
1824 /*
1825 * Do the scanning.
1826 */
1827 pgmR3ScanRomPages(pVM);
1828 pgmR3ScanMmio2Pages(pVM, uPass);
1829 pgmR3ScanRamPages(pVM, false /*fFinalPass*/);
1830 pgmR3PoolClearAll(pVM, true /*fFlushRemTlb*/); /** @todo this could perhaps be optimized a bit. */
1831
1832 /*
1833 * Save the pages.
1834 */
1835 if (uPass == 0)
1836 rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /*fLiveSave*/);
1837 else
1838 rc = VINF_SUCCESS;
1839 if (RT_SUCCESS(rc))
1840 rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /*fLiveSave*/, false /*fFinalPass*/);
1841 if (RT_SUCCESS(rc))
1842 rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /*fLiveSave*/, uPass);
1843 if (RT_SUCCESS(rc))
1844 rc = pgmR3SaveRamPages( pVM, pSSM, true /*fLiveSave*/, uPass);
1845 SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes care of it.) */
1846
1847 return rc;
1848}
1849
1850
1851/**
1852 * Votes on whether the live save phase is done or not.
1853 *
1854 * @returns VBox status code.
1855 *
1856 * @param pVM The VM handle.
1857 * @param pSSM The SSM handle.
1858 * @param uPass The data pass.
1859 */
1860static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1861{
1862 /*
1863 * Update and calculate parameters used in the decision making.
1864 */
1865 const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1866
1867 /* update history. */
1868 pgmLock(pVM);
1869 uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1870 pgmUnlock(pVM);
1871 uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1872 + pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1873 + pVM->pgm.s.LiveSave.Ram.cDirtyPages
1874 + cWrittenToPages;
1875 uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1876 pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1877 pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1878
1879 /* calc shortterm average (4 passes). */
1880 AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1881 uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1882 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1883 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1884 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1885 uint32_t const cDirtyPagesShort = cTotal / 4;
1886 pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1887
1888 /* calc longterm average. */
1889 cTotal = 0;
1890 if (uPass < cHistoryEntries)
1891 for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1892 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1893 else
1894 for (i = 0; i < cHistoryEntries; i++)
1895 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1896 uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1897 pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1898
1899 /* estimate the speed */
1900 uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1901 uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1902 / ((long double)cNsElapsed / 1000000000.0) );
1903 pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1904
1905 /*
1906 * Try make a decision.
1907 */
1908 if ( cDirtyPagesShort <= cDirtyPagesLong
1909 && ( cDirtyNow <= cDirtyPagesShort
1910 || cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1911 )
1912 )
1913 {
1914 if (uPass > 10)
1915 {
1916 uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1917 uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1918 uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1919 if (cMsMaxDowntime < 32)
1920 cMsMaxDowntime = 32;
1921 if ( ( cMsLeftLong <= cMsMaxDowntime
1922 && cMsLeftShort < cMsMaxDowntime)
1923 || cMsLeftShort < cMsMaxDowntime / 2
1924 )
1925 {
1926 Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u|%ums cDirtyPagesLong=%u|%ums cMsMaxDowntime=%u\n",
1927 uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1928 return VINF_SUCCESS;
1929 }
1930 }
1931 else
1932 {
1933 if ( ( cDirtyPagesShort <= 128
1934 && cDirtyPagesLong <= 1024)
1935 || cDirtyPagesLong <= 256
1936 )
1937 {
1938 Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1939 return VINF_SUCCESS;
1940 }
1941 }
1942 }
1943
1944 /*
1945 * Come up with a completion percentage. Currently this is a simple
1946 * dirty page (long term) vs. total pages ratio + some pass trickery.
1947 */
1948 unsigned uPctDirty = (unsigned)( (long double)cDirtyPagesLong
1949 / (pVM->pgm.s.cAllPages - pVM->pgm.s.LiveSave.cIgnoredPages - pVM->pgm.s.cZeroPages) );
1950 if (uPctDirty <= 100)
1951 SSMR3HandleReportLivePercent(pSSM, RT_MIN(100 - uPctDirty, uPass * 2));
1952 else
1953 AssertMsgFailed(("uPctDirty=%u cDirtyPagesLong=%#x cAllPages=%#x cIgnoredPages=%#x cZeroPages=%#x\n",
1954 uPctDirty, cDirtyPagesLong, pVM->pgm.s.cAllPages, pVM->pgm.s.LiveSave.cIgnoredPages, pVM->pgm.s.cZeroPages));
1955
1956 return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1957}
1958
1959
1960/**
1961 * Prepare for a live save operation.
1962 *
1963 * This will attempt to allocate and initialize the tracking structures. It
1964 * will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1965 * pgmR3SaveDone will do the cleanups.
1966 *
1967 * @returns VBox status code.
1968 *
1969 * @param pVM The VM handle.
1970 * @param pSSM The SSM handle.
1971 */
1972static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1973{
1974 /*
1975 * Indicate that we will be using the write monitoring.
1976 */
1977 pgmLock(pVM);
1978 /** @todo find a way of mediating this when more users are added. */
1979 if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1980 {
1981 pgmUnlock(pVM);
1982 AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1983 }
1984 pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1985 pgmUnlock(pVM);
1986
1987 /*
1988 * Initialize the statistics.
1989 */
1990 pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1991 pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1992 pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1993 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1994 pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1995 pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1996 pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1997 pVM->pgm.s.LiveSave.fActive = true;
1998 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
1999 pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
2000 pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
2001 pVM->pgm.s.LiveSave.cSavedPages = 0;
2002 pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
2003 pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
2004
2005 /*
2006 * Per page type.
2007 */
2008 int rc = pgmR3PrepRomPages(pVM);
2009 if (RT_SUCCESS(rc))
2010 rc = pgmR3PrepMmio2Pages(pVM);
2011 if (RT_SUCCESS(rc))
2012 rc = pgmR3PrepRamPages(pVM);
2013 return rc;
2014}
2015
2016
2017/**
2018 * Execute state save operation.
2019 *
2020 * @returns VBox status code.
2021 * @param pVM VM Handle.
2022 * @param pSSM SSM operation handle.
2023 */
2024static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2025{
2026 int rc;
2027 unsigned i;
2028 PPGM pPGM = &pVM->pgm.s;
2029
2030 /*
2031 * Lock PGM and set the no-more-writes indicator.
2032 */
2033 pgmLock(pVM);
2034 pVM->pgm.s.fNoMorePhysWrites = true;
2035
2036 /*
2037 * Save basic data (required / unaffected by relocation).
2038 */
2039 bool const fMappingsFixed = pVM->pgm.s.fMappingsFixed;
2040 pVM->pgm.s.fMappingsFixed |= pVM->pgm.s.fMappingsFixedRestored;
2041 SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2042 pVM->pgm.s.fMappingsFixed = fMappingsFixed;
2043
2044 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2045 SSMR3PutStruct(pSSM, &pVM->aCpus[idCpu].pgm.s, &s_aPGMCpuFields[0]);
2046
2047 /*
2048 * The guest mappings.
2049 */
2050 i = 0;
2051 for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2052 {
2053 SSMR3PutU32( pSSM, i);
2054 SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2055 SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2056 SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2057 }
2058 rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2059
2060 /*
2061 * Save the (remainder of the) memory.
2062 */
2063 if (RT_SUCCESS(rc))
2064 {
2065 if (pVM->pgm.s.LiveSave.fActive)
2066 {
2067 pgmR3ScanRomPages(pVM);
2068 pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
2069 pgmR3ScanRamPages(pVM, true /*fFinalPass*/);
2070
2071 rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /*fLiveSave*/, true /*fFinalPass*/);
2072 if (RT_SUCCESS(rc))
2073 rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /*fLiveSave*/, SSM_PASS_FINAL);
2074 if (RT_SUCCESS(rc))
2075 rc = pgmR3SaveRamPages( pVM, pSSM, true /*fLiveSave*/, SSM_PASS_FINAL);
2076 }
2077 else
2078 {
2079 rc = pgmR3SaveRamConfig(pVM, pSSM);
2080 if (RT_SUCCESS(rc))
2081 rc = pgmR3SaveRomRanges(pVM, pSSM);
2082 if (RT_SUCCESS(rc))
2083 rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2084 if (RT_SUCCESS(rc))
2085 rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /*fLiveSave*/);
2086 if (RT_SUCCESS(rc))
2087 rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /*fLiveSave*/, true /*fFinalPass*/);
2088 if (RT_SUCCESS(rc))
2089 rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /*fLiveSave*/, SSM_PASS_FINAL);
2090 if (RT_SUCCESS(rc))
2091 rc = pgmR3SaveRamPages( pVM, pSSM, false /*fLiveSave*/, SSM_PASS_FINAL);
2092 }
2093 SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2094 }
2095
2096 pgmUnlock(pVM);
2097 return rc;
2098}
2099
2100
2101/**
2102 * Cleans up after an save state operation.
2103 *
2104 * @returns VBox status code.
2105 * @param pVM VM Handle.
2106 * @param pSSM SSM operation handle.
2107 */
2108static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2109{
2110 /*
2111 * Do per page type cleanups first.
2112 */
2113 if (pVM->pgm.s.LiveSave.fActive)
2114 {
2115 pgmR3DoneRomPages(pVM);
2116 pgmR3DoneMmio2Pages(pVM);
2117 pgmR3DoneRamPages(pVM);
2118 }
2119
2120 /*
2121 * Clear the live save indicator and disengage write monitoring.
2122 */
2123 pgmLock(pVM);
2124 pVM->pgm.s.LiveSave.fActive = false;
2125 /** @todo this is blindly assuming that we're the only user of write
2126 * monitoring. Fix this when more users are added. */
2127 pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2128 pgmUnlock(pVM);
2129
2130 return VINF_SUCCESS;
2131}
2132
2133
2134/**
2135 * Prepare state load operation.
2136 *
2137 * @returns VBox status code.
2138 * @param pVM VM Handle.
2139 * @param pSSM SSM operation handle.
2140 */
2141static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2142{
2143 /*
2144 * Call the reset function to make sure all the memory is cleared.
2145 */
2146 PGMR3Reset(pVM);
2147 pVM->pgm.s.LiveSave.fActive = false;
2148 NOREF(pSSM);
2149 return VINF_SUCCESS;
2150}
2151
2152
2153/**
2154 * Load an ignored page.
2155 *
2156 * @returns VBox status code.
2157 * @param pSSM The saved state handle.
2158 */
2159static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2160{
2161 uint8_t abPage[PAGE_SIZE];
2162 return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2163}
2164
2165
2166/**
2167 * Loads a page without any bits in the saved state, i.e. making sure it's
2168 * really zero.
2169 *
2170 * @returns VBox status code.
2171 * @param pVM The VM handle.
2172 * @param uType The page type or PGMPAGETYPE_INVALID (old saved
2173 * state).
2174 * @param pPage The guest page tracking structure.
2175 * @param GCPhys The page address.
2176 * @param pRam The ram range (logging).
2177 */
2178static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2179{
2180 if ( PGM_PAGE_GET_TYPE(pPage) != uType
2181 && uType != PGMPAGETYPE_INVALID)
2182 return VERR_SSM_UNEXPECTED_DATA;
2183
2184 /* I think this should be sufficient. */
2185 if ( !PGM_PAGE_IS_ZERO(pPage)
2186 && !PGM_PAGE_IS_BALLOONED(pPage))
2187 return VERR_SSM_UNEXPECTED_DATA;
2188
2189 NOREF(pVM);
2190 NOREF(GCPhys);
2191 NOREF(pRam);
2192 return VINF_SUCCESS;
2193}
2194
2195
2196/**
2197 * Loads a page from the saved state.
2198 *
2199 * @returns VBox status code.
2200 * @param pVM The VM handle.
2201 * @param pSSM The SSM handle.
2202 * @param uType The page type or PGMPAGETYEP_INVALID (old saved
2203 * state).
2204 * @param pPage The guest page tracking structure.
2205 * @param GCPhys The page address.
2206 * @param pRam The ram range (logging).
2207 */
2208static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2209{
2210 /*
2211 * Match up the type, dealing with MMIO2 aliases (dropped).
2212 */
2213 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2214 || uType == PGMPAGETYPE_INVALID,
2215 ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2216 VERR_SSM_UNEXPECTED_DATA);
2217
2218 /*
2219 * Load the page.
2220 */
2221 void *pvPage;
2222 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2223 if (RT_SUCCESS(rc))
2224 rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2225
2226 return rc;
2227}
2228
2229
2230/**
2231 * Loads a page (counter part to pgmR3SavePage).
2232 *
2233 * @returns VBox status code, fully bitched errors.
2234 * @param pVM The VM handle.
2235 * @param pSSM The SSM handle.
2236 * @param uType The page type.
2237 * @param pPage The page.
2238 * @param GCPhys The page address.
2239 * @param pRam The RAM range (for error messages).
2240 */
2241static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2242{
2243 uint8_t uState;
2244 int rc = SSMR3GetU8(pSSM, &uState);
2245 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2246 if (uState == 0 /* zero */)
2247 rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2248 else if (uState == 1)
2249 rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2250 else
2251 rc = VERR_INTERNAL_ERROR;
2252 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2253 pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2254 rc);
2255 return VINF_SUCCESS;
2256}
2257
2258
2259/**
2260 * Loads a shadowed ROM page.
2261 *
2262 * @returns VBox status code, errors are fully bitched.
2263 * @param pVM The VM handle.
2264 * @param pSSM The saved state handle.
2265 * @param pPage The page.
2266 * @param GCPhys The page address.
2267 * @param pRam The RAM range (for error messages).
2268 */
2269static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2270{
2271 /*
2272 * Load and set the protection first, then load the two pages, the first
2273 * one is the active the other is the passive.
2274 */
2275 PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2276 AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2277
2278 uint8_t uProt;
2279 int rc = SSMR3GetU8(pSSM, &uProt);
2280 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2281 PGMROMPROT enmProt = (PGMROMPROT)uProt;
2282 AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2283 && enmProt < PGMROMPROT_END,
2284 ("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2285 VERR_SSM_UNEXPECTED_DATA);
2286
2287 if (pRomPage->enmProt != enmProt)
2288 {
2289 rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2290 AssertLogRelRCReturn(rc, rc);
2291 AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2292 }
2293
2294 PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2295 PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2296 uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2297 uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2298
2299 /** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2300 * used down the line (will the 2nd page will be written to the first
2301 * one because of a false TLB hit since the TLB is using GCPhys and
2302 * doesn't check the HCPhys of the desired page). */
2303 rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2304 if (RT_SUCCESS(rc))
2305 {
2306 *pPageActive = *pPage;
2307 rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2308 }
2309 return rc;
2310}
2311
2312/**
2313 * Ram range flags and bits for older versions of the saved state.
2314 *
2315 * @returns VBox status code.
2316 *
2317 * @param pVM The VM handle
2318 * @param pSSM The SSM handle.
2319 * @param uVersion The saved state version.
2320 */
2321static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2322{
2323 PPGM pPGM = &pVM->pgm.s;
2324
2325 /*
2326 * Ram range flags and bits.
2327 */
2328 uint32_t i = 0;
2329 for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2330 {
2331 /* Check the sequence number / separator. */
2332 uint32_t u32Sep;
2333 int rc = SSMR3GetU32(pSSM, &u32Sep);
2334 if (RT_FAILURE(rc))
2335 return rc;
2336 if (u32Sep == ~0U)
2337 break;
2338 if (u32Sep != i)
2339 {
2340 AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2341 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2342 }
2343 AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2344
2345 /* Get the range details. */
2346 RTGCPHYS GCPhys;
2347 SSMR3GetGCPhys(pSSM, &GCPhys);
2348 RTGCPHYS GCPhysLast;
2349 SSMR3GetGCPhys(pSSM, &GCPhysLast);
2350 RTGCPHYS cb;
2351 SSMR3GetGCPhys(pSSM, &cb);
2352 uint8_t fHaveBits;
2353 rc = SSMR3GetU8(pSSM, &fHaveBits);
2354 if (RT_FAILURE(rc))
2355 return rc;
2356 if (fHaveBits & ~1)
2357 {
2358 AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2359 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2360 }
2361 size_t cchDesc = 0;
2362 char szDesc[256];
2363 szDesc[0] = '\0';
2364 if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2365 {
2366 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2367 if (RT_FAILURE(rc))
2368 return rc;
2369 /* Since we've modified the description strings in r45878, only compare
2370 them if the saved state is more recent. */
2371 if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2372 cchDesc = strlen(szDesc);
2373 }
2374
2375 /*
2376 * Match it up with the current range.
2377 *
2378 * Note there is a hack for dealing with the high BIOS mapping
2379 * in the old saved state format, this means we might not have
2380 * a 1:1 match on success.
2381 */
2382 if ( ( GCPhys != pRam->GCPhys
2383 || GCPhysLast != pRam->GCPhysLast
2384 || cb != pRam->cb
2385 || ( cchDesc
2386 && strcmp(szDesc, pRam->pszDesc)) )
2387 /* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2388 && ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2389 || GCPhys != UINT32_C(0xfff80000)
2390 || GCPhysLast != UINT32_C(0xffffffff)
2391 || pRam->GCPhysLast != GCPhysLast
2392 || pRam->GCPhys < GCPhys
2393 || !fHaveBits)
2394 )
2395 {
2396 LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2397 "State : %RGp-%RGp %RGp bytes %s %s\n",
2398 pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2399 GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2400 /*
2401 * If we're loading a state for debugging purpose, don't make a fuss if
2402 * the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2403 */
2404 if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2405 || GCPhys < 8 * _1M)
2406 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2407 N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2408 GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2409 pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2410
2411 AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2412 continue;
2413 }
2414
2415 uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2416 if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2417 {
2418 /*
2419 * Load the pages one by one.
2420 */
2421 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2422 {
2423 RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2424 PPGMPAGE pPage = &pRam->aPages[iPage];
2425 uint8_t uType;
2426 rc = SSMR3GetU8(pSSM, &uType);
2427 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2428 if (uType == PGMPAGETYPE_ROM_SHADOW)
2429 rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2430 else
2431 rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2432 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2433 }
2434 }
2435 else
2436 {
2437 /*
2438 * Old format.
2439 */
2440
2441 /* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2442 The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2443 uint32_t fFlags = 0;
2444 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2445 {
2446 uint16_t u16Flags;
2447 rc = SSMR3GetU16(pSSM, &u16Flags);
2448 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2449 fFlags |= u16Flags;
2450 }
2451
2452 /* Load the bits */
2453 if ( !fHaveBits
2454 && GCPhysLast < UINT32_C(0xe0000000))
2455 {
2456 /*
2457 * Dynamic chunks.
2458 */
2459 const uint32_t cPagesInChunk = (1*1024*1024) >> PAGE_SHIFT;
2460 AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2461 ("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2462 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2463
2464 for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2465 {
2466 uint8_t fPresent;
2467 rc = SSMR3GetU8(pSSM, &fPresent);
2468 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2469 AssertLogRelMsgReturn(fPresent == (uint8_t)true || fPresent == (uint8_t)false,
2470 ("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2471 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2472
2473 for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2474 {
2475 RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2476 PPGMPAGE pPage = &pRam->aPages[iPage];
2477 if (fPresent)
2478 {
2479 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2480 rc = pgmR3LoadPageToDevNullOld(pSSM);
2481 else
2482 rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2483 }
2484 else
2485 rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2486 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2487 }
2488 }
2489 }
2490 else if (pRam->pvR3)
2491 {
2492 /*
2493 * MMIO2.
2494 */
2495 AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /*MM_RAM_FLAGS_MMIO2*/,
2496 ("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2497 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2498 AssertLogRelMsgReturn(pRam->pvR3,
2499 ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2500 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2501
2502 rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2503 AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2504 }
2505 else if (GCPhysLast < UINT32_C(0xfff80000))
2506 {
2507 /*
2508 * PCI MMIO, no pages saved.
2509 */
2510 }
2511 else
2512 {
2513 /*
2514 * Load the 0xfff80000..0xffffffff BIOS range.
2515 * It starts with X reserved pages that we have to skip over since
2516 * the RAMRANGE create by the new code won't include those.
2517 */
2518 AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /*MM_RAM_FLAGS_MMIO2*/)
2519 && (fFlags & RT_BIT(0) /*MM_RAM_FLAGS_RESERVED*/),
2520 ("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2521 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2522 AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2523 ("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2524 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2525
2526 /* Skip wasted reserved pages before the ROM. */
2527 while (GCPhys < pRam->GCPhys)
2528 {
2529 rc = pgmR3LoadPageToDevNullOld(pSSM);
2530 GCPhys += PAGE_SIZE;
2531 }
2532
2533 /* Load the bios pages. */
2534 cPages = pRam->cb >> PAGE_SHIFT;
2535 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2536 {
2537 RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2538 PPGMPAGE pPage = &pRam->aPages[iPage];
2539
2540 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2541 ("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2542 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2543 rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2544 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2545 }
2546 }
2547 }
2548 }
2549
2550 return VINF_SUCCESS;
2551}
2552
2553
2554/**
2555 * Worker for pgmR3Load and pgmR3LoadLocked.
2556 *
2557 * @returns VBox status code.
2558 *
2559 * @param pVM The VM handle.
2560 * @param pSSM The SSM handle.
2561 * @param uVersion The saved state version.
2562 *
2563 * @todo This needs splitting up if more record types or code twists are
2564 * added...
2565 */
2566static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2567{
2568 /*
2569 * Process page records until we hit the terminator.
2570 */
2571 RTGCPHYS GCPhys = NIL_RTGCPHYS;
2572 PPGMRAMRANGE pRamHint = NULL;
2573 uint8_t id = UINT8_MAX;
2574 uint32_t iPage = UINT32_MAX - 10;
2575 PPGMROMRANGE pRom = NULL;
2576 PPGMMMIO2RANGE pMmio2 = NULL;
2577
2578 /*
2579 * We batch up pages that should be freed instead of calling GMM for
2580 * each and every one of them.
2581 */
2582 uint32_t cPendingPages = 0;
2583 PGMMFREEPAGESREQ pReq;
2584 int rc = GMMR3FreePagesPrepare(pVM, &pReq, 128 /* batch size */, GMMACCOUNT_BASE);
2585 AssertLogRelRCReturn(rc, rc);
2586
2587 for (;;)
2588 {
2589 /*
2590 * Get the record type and flags.
2591 */
2592 uint8_t u8;
2593 rc = SSMR3GetU8(pSSM, &u8);
2594 if (RT_FAILURE(rc))
2595 return rc;
2596 if (u8 == PGM_STATE_REC_END)
2597 {
2598 /*
2599 * Finish off any pages pending freeing.
2600 */
2601 if (cPendingPages)
2602 {
2603 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2604 AssertLogRelRCReturn(rc, rc);
2605 }
2606 GMMR3FreePagesCleanup(pReq);
2607 return VINF_SUCCESS;
2608 }
2609 AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2610 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2611 {
2612 /*
2613 * RAM page.
2614 */
2615 case PGM_STATE_REC_RAM_ZERO:
2616 case PGM_STATE_REC_RAM_RAW:
2617 {
2618 /*
2619 * Get the address and resolve it into a page descriptor.
2620 */
2621 if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2622 GCPhys += PAGE_SIZE;
2623 else
2624 {
2625 rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2626 if (RT_FAILURE(rc))
2627 return rc;
2628 }
2629 AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2630
2631 PPGMPAGE pPage;
2632 rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2633 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2634
2635 /*
2636 * Take action according to the record type.
2637 */
2638 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2639 {
2640 case PGM_STATE_REC_RAM_ZERO:
2641 {
2642 if ( PGM_PAGE_IS_ZERO(pPage)
2643 || PGM_PAGE_IS_BALLOONED(pPage))
2644 break;
2645 AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2646
2647 /* Free it only if it's not part of a previously allocated large page. */
2648 if (PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE)
2649 {
2650 /* Allocated before (prealloc), so free it now. */
2651 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys);
2652 AssertRC(rc);
2653 }
2654 break;
2655 }
2656
2657 case PGM_STATE_REC_RAM_RAW:
2658 {
2659 void *pvDstPage;
2660 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2661 AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2662 rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2663 if (RT_FAILURE(rc))
2664 return rc;
2665 break;
2666 }
2667
2668 default:
2669 AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2670 }
2671 id = UINT8_MAX;
2672 break;
2673 }
2674
2675 /*
2676 * MMIO2 page.
2677 */
2678 case PGM_STATE_REC_MMIO2_RAW:
2679 case PGM_STATE_REC_MMIO2_ZERO:
2680 {
2681 /*
2682 * Get the ID + page number and resolved that into a MMIO2 page.
2683 */
2684 if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2685 iPage++;
2686 else
2687 {
2688 SSMR3GetU8(pSSM, &id);
2689 rc = SSMR3GetU32(pSSM, &iPage);
2690 if (RT_FAILURE(rc))
2691 return rc;
2692 }
2693 if ( !pMmio2
2694 || pMmio2->idSavedState != id)
2695 {
2696 for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2697 if (pMmio2->idSavedState == id)
2698 break;
2699 AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2700 }
2701 AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2702 void *pvDstPage = (uint8_t *)pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2703
2704 /*
2705 * Load the page bits.
2706 */
2707 if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2708 ASMMemZeroPage(pvDstPage);
2709 else
2710 {
2711 rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2712 if (RT_FAILURE(rc))
2713 return rc;
2714 }
2715 GCPhys = NIL_RTGCPHYS;
2716 break;
2717 }
2718
2719 /*
2720 * ROM pages.
2721 */
2722 case PGM_STATE_REC_ROM_VIRGIN:
2723 case PGM_STATE_REC_ROM_SHW_RAW:
2724 case PGM_STATE_REC_ROM_SHW_ZERO:
2725 case PGM_STATE_REC_ROM_PROT:
2726 {
2727 /*
2728 * Get the ID + page number and resolved that into a ROM page descriptor.
2729 */
2730 if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2731 iPage++;
2732 else
2733 {
2734 SSMR3GetU8(pSSM, &id);
2735 rc = SSMR3GetU32(pSSM, &iPage);
2736 if (RT_FAILURE(rc))
2737 return rc;
2738 }
2739 if ( !pRom
2740 || pRom->idSavedState != id)
2741 {
2742 for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2743 if (pRom->idSavedState == id)
2744 break;
2745 AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2746 }
2747 AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2748 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2749 GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2750
2751 /*
2752 * Get and set the protection.
2753 */
2754 uint8_t u8Prot;
2755 rc = SSMR3GetU8(pSSM, &u8Prot);
2756 if (RT_FAILURE(rc))
2757 return rc;
2758 PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2759 AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2760
2761 if (enmProt != pRomPage->enmProt)
2762 {
2763 if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2764 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2765 N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2766 GCPhys, enmProt, pRom->pszDesc);
2767 rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2768 AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2769 AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2770 }
2771 if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2772 break; /* done */
2773
2774 /*
2775 * Get the right page descriptor.
2776 */
2777 PPGMPAGE pRealPage;
2778 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2779 {
2780 case PGM_STATE_REC_ROM_VIRGIN:
2781 if (!PGMROMPROT_IS_ROM(enmProt))
2782 pRealPage = &pRomPage->Virgin;
2783 else
2784 pRealPage = NULL;
2785 break;
2786
2787 case PGM_STATE_REC_ROM_SHW_RAW:
2788 case PGM_STATE_REC_ROM_SHW_ZERO:
2789 if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2790 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2791 N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2792 GCPhys, enmProt, pRom->pszDesc);
2793 if (PGMROMPROT_IS_ROM(enmProt))
2794 pRealPage = &pRomPage->Shadow;
2795 else
2796 pRealPage = NULL;
2797 break;
2798
2799 default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2800 }
2801 if (!pRealPage)
2802 {
2803 rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2804 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2805 }
2806
2807 /*
2808 * Make it writable and map it (if necessary).
2809 */
2810 void *pvDstPage = NULL;
2811 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2812 {
2813 case PGM_STATE_REC_ROM_SHW_ZERO:
2814 if ( PGM_PAGE_IS_ZERO(pRealPage)
2815 || PGM_PAGE_IS_BALLOONED(pRealPage))
2816 break;
2817 /** @todo implement zero page replacing. */
2818 /* fall thru */
2819 case PGM_STATE_REC_ROM_VIRGIN:
2820 case PGM_STATE_REC_ROM_SHW_RAW:
2821 {
2822 rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2823 AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2824 break;
2825 }
2826 }
2827
2828 /*
2829 * Load the bits.
2830 */
2831 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2832 {
2833 case PGM_STATE_REC_ROM_SHW_ZERO:
2834 if (pvDstPage)
2835 ASMMemZeroPage(pvDstPage);
2836 break;
2837
2838 case PGM_STATE_REC_ROM_VIRGIN:
2839 case PGM_STATE_REC_ROM_SHW_RAW:
2840 rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2841 if (RT_FAILURE(rc))
2842 return rc;
2843 break;
2844 }
2845 GCPhys = NIL_RTGCPHYS;
2846 break;
2847 }
2848
2849 /*
2850 * Unknown type.
2851 */
2852 default:
2853 AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2854 }
2855 } /* forever */
2856}
2857
2858
2859/**
2860 * Worker for pgmR3Load.
2861 *
2862 * @returns VBox status code.
2863 *
2864 * @param pVM The VM handle.
2865 * @param pSSM The SSM handle.
2866 * @param uVersion The saved state version.
2867 */
2868static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2869{
2870 PPGM pPGM = &pVM->pgm.s;
2871 int rc;
2872 uint32_t u32Sep;
2873
2874 /*
2875 * Load basic data (required / unaffected by relocation).
2876 */
2877 if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2878 {
2879 if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2880 rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2881 else
2882 rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFieldsPreBalloon[0]);
2883
2884 AssertLogRelRCReturn(rc, rc);
2885
2886 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2887 {
2888 rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2889 AssertLogRelRCReturn(rc, rc);
2890 }
2891 }
2892 else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2893 {
2894 AssertRelease(pVM->cCpus == 1);
2895
2896 PGMOLD pgmOld;
2897 rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2898 AssertLogRelRCReturn(rc, rc);
2899
2900 pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2901 pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2902 pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2903
2904 pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2905 pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2906 pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2907 }
2908 else
2909 {
2910 AssertRelease(pVM->cCpus == 1);
2911
2912 SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2913 SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2914 SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2915
2916 uint32_t cbRamSizeIgnored;
2917 rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2918 if (RT_FAILURE(rc))
2919 return rc;
2920 SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2921
2922 uint32_t u32 = 0;
2923 SSMR3GetUInt(pSSM, &u32);
2924 pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2925 SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2926 RTUINT uGuestMode;
2927 SSMR3GetUInt(pSSM, &uGuestMode);
2928 pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2929
2930 /* check separator. */
2931 SSMR3GetU32(pSSM, &u32Sep);
2932 if (RT_FAILURE(rc))
2933 return rc;
2934 if (u32Sep != (uint32_t)~0)
2935 {
2936 AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2937 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2938 }
2939 }
2940
2941 /*
2942 * The guest mappings - skipped now, see re-fixation in the caller.
2943 */
2944 uint32_t i = 0;
2945 for (;; i++)
2946 {
2947 rc = SSMR3GetU32(pSSM, &u32Sep); /* sequence number */
2948 if (RT_FAILURE(rc))
2949 return rc;
2950 if (u32Sep == ~0U)
2951 break;
2952 AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2953
2954 char szDesc[256];
2955 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2956 if (RT_FAILURE(rc))
2957 return rc;
2958 RTGCPTR GCPtrIgnore;
2959 SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
2960 rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
2961 if (RT_FAILURE(rc))
2962 return rc;
2963 }
2964
2965 /*
2966 * Load the RAM contents.
2967 */
2968 if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2969 {
2970 if (!pVM->pgm.s.LiveSave.fActive)
2971 {
2972 if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2973 {
2974 rc = pgmR3LoadRamConfig(pVM, pSSM);
2975 if (RT_FAILURE(rc))
2976 return rc;
2977 }
2978 rc = pgmR3LoadRomRanges(pVM, pSSM);
2979 if (RT_FAILURE(rc))
2980 return rc;
2981 rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2982 if (RT_FAILURE(rc))
2983 return rc;
2984 }
2985
2986 rc = pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2987 }
2988 else
2989 rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2990
2991 /* Refresh balloon accounting. */
2992 if (pVM->pgm.s.cBalloonedPages)
2993 {
2994 rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
2995 AssertRC(rc);
2996 }
2997 return rc;
2998}
2999
3000
3001/**
3002 * Execute state load operation.
3003 *
3004 * @returns VBox status code.
3005 * @param pVM VM Handle.
3006 * @param pSSM SSM operation handle.
3007 * @param uVersion Data layout version.
3008 * @param uPass The data pass.
3009 */
3010static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3011{
3012 int rc;
3013 PPGM pPGM = &pVM->pgm.s;
3014
3015 /*
3016 * Validate version.
3017 */
3018 if ( ( uPass != SSM_PASS_FINAL
3019 && uVersion != PGM_SAVED_STATE_VERSION
3020 && uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3021 && uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3022 || ( uVersion != PGM_SAVED_STATE_VERSION
3023 && uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3024 && uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
3025 && uVersion != PGM_SAVED_STATE_VERSION_3_0_0
3026 && uVersion != PGM_SAVED_STATE_VERSION_2_2_2
3027 && uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
3028 && uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3029 )
3030 {
3031 AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
3032 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3033 }
3034
3035 /*
3036 * Do the loading while owning the lock because a bunch of the functions
3037 * we're using requires this.
3038 */
3039 if (uPass != SSM_PASS_FINAL)
3040 {
3041 pgmLock(pVM);
3042 if (uPass != 0)
3043 rc = pgmR3LoadMemory(pVM, pSSM, uPass);
3044 else
3045 {
3046 pVM->pgm.s.LiveSave.fActive = true;
3047 if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3048 rc = pgmR3LoadRamConfig(pVM, pSSM);
3049 else
3050 rc = VINF_SUCCESS;
3051 if (RT_SUCCESS(rc))
3052 rc = pgmR3LoadRomRanges(pVM, pSSM);
3053 if (RT_SUCCESS(rc))
3054 rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3055 if (RT_SUCCESS(rc))
3056 rc = pgmR3LoadMemory(pVM, pSSM, uPass);
3057 }
3058 pgmUnlock(pVM);
3059 }
3060 else
3061 {
3062 pgmLock(pVM);
3063 rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
3064 pVM->pgm.s.LiveSave.fActive = false;
3065 pgmUnlock(pVM);
3066 if (RT_SUCCESS(rc))
3067 {
3068 /*
3069 * We require a full resync now.
3070 */
3071 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3072 {
3073 PVMCPU pVCpu = &pVM->aCpus[i];
3074 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3075 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3076 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3077 }
3078
3079 pgmR3HandlerPhysicalUpdateAll(pVM);
3080
3081 /*
3082 * Change the paging mode and restore PGMCPU::GCPhysCR3.
3083 * (The latter requires the CPUM state to be restored already.)
3084 */
3085 if (CPUMR3IsStateRestorePending(pVM))
3086 return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3087 N_("PGM was unexpectedly restored before CPUM"));
3088
3089 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3090 {
3091 PVMCPU pVCpu = &pVM->aCpus[i];
3092
3093 rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3094 AssertLogRelRCReturn(rc, rc);
3095
3096 /* Update pVM->pgm.s.GCPhysCR3. */
3097 Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS || FTMIsDeltaLoadSaveActive(pVM));
3098 RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3099 if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3100 || pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3101 || pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3102 || pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3103 GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3104 else
3105 GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3106 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3107
3108 /* Update the PSE, NX flags and validity masks. */
3109 pVCpu->pgm.s.fGst32BitPageSizeExtension = CPUMIsGuestPageSizeExtEnabled(pVCpu);
3110 PGMNotifyNxeChanged(pVCpu, CPUMIsGuestNXEnabled(pVCpu));
3111 }
3112
3113 /*
3114 * Try re-fixate the guest mappings.
3115 */
3116 pVM->pgm.s.fMappingsFixedRestored = false;
3117 if ( pVM->pgm.s.fMappingsFixed
3118 && pgmMapAreMappingsEnabled(&pVM->pgm.s))
3119 {
3120 RTGCPTR GCPtrFixed = pVM->pgm.s.GCPtrMappingFixed;
3121 uint32_t cbFixed = pVM->pgm.s.cbMappingFixed;
3122 pVM->pgm.s.fMappingsFixed = false;
3123
3124 uint32_t cbRequired;
3125 int rc2 = PGMR3MappingsSize(pVM, &cbRequired); AssertRC(rc2);
3126 if ( RT_SUCCESS(rc2)
3127 && cbRequired > cbFixed)
3128 rc2 = VERR_OUT_OF_RANGE;
3129 if (RT_SUCCESS(rc2))
3130 rc2 = pgmR3MappingsFixInternal(pVM, GCPtrFixed, cbFixed);
3131 if (RT_FAILURE(rc2))
3132 {
3133 LogRel(("PGM: Unable to re-fixate the guest mappings at %RGv-%RGv: rc=%Rrc (cbRequired=%#x)\n",
3134 GCPtrFixed, GCPtrFixed + cbFixed, rc2, cbRequired));
3135 pVM->pgm.s.fMappingsFixed = false;
3136 pVM->pgm.s.fMappingsFixedRestored = true;
3137 pVM->pgm.s.GCPtrMappingFixed = GCPtrFixed;
3138 pVM->pgm.s.cbMappingFixed = cbFixed;
3139 }
3140 }
3141 else
3142 {
3143 /* We used to set fixed + disabled while we only use disabled now,
3144 so wipe the state to avoid any confusion. */
3145 pVM->pgm.s.fMappingsFixed = false;
3146 pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
3147 pVM->pgm.s.cbMappingFixed = 0;
3148 }
3149
3150 /*
3151 * If we have floating mappings, do a CR3 sync now to make sure the HMA
3152 * doesn't conflict with guest code / data and thereby cause trouble
3153 * when restoring other components like PATM.
3154 */
3155 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3156 {
3157 PVMCPU pVCpu = &pVM->aCpus[0];
3158 rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
3159 if (RT_FAILURE(rc))
3160 return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3161 N_("PGMSyncCR3 failed unexpectedly with rc=%Rrc"), rc);
3162
3163 /* Make sure to re-sync before executing code. */
3164 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3165 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3166 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3167 }
3168 }
3169 }
3170
3171 return rc;
3172}
3173
3174
3175/**
3176 * Registers the saved state callbacks with SSM.
3177 *
3178 * @returns VBox status code.
3179 * @param pVM Pointer to VM structure.
3180 * @param cbRam The RAM size.
3181 */
3182int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3183{
3184 return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3185 pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3186 NULL, pgmR3SaveExec, pgmR3SaveDone,
3187 pgmR3LoadPrep, pgmR3Load, NULL);
3188}
3189
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