PGMSavedState.cpp@ 23539

Last change on this file since 23539 was 23539, checked in by vboxsync, 15 years ago
PGMSavedState: Added some sanity checks for write monitored pages using CRC-32.
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File size: 107.1 KB

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1	/* $Id: PGMSavedState.cpp 23539 2009-10-04 20:42:05Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/pgm.h>
28	#include <VBox/stam.h>
29	#include <VBox/ssm.h>
30	#include <VBox/pdm.h>
31	#include "PGMInternal.h"
32	#include <VBox/vm.h>
33
34	#include <VBox/param.h>
35	#include <VBox/err.h>
36
37	#include <iprt/asm.h>
38	#include <iprt/assert.h>
39	#include <iprt/crc32.h>
40	#include <iprt/mem.h>
41	#include <iprt/sha.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44
45
46	/*******************************************************************************
47	* Defined Constants And Macros *
48	*******************************************************************************/
49	/** Saved state data unit version. */
50	#ifdef VBOX_WITH_LIVE_MIGRATION
51	# define PGM_SAVED_STATE_VERSION 10
52	#else
53	# define PGM_SAVED_STATE_VERSION 9
54	#endif
55	/** Saved state data unit version for 3.0. (pre live migration) */
56	#define PGM_SAVED_STATE_VERSION_3_0_0 9
57	/** Saved state data unit version for 2.2.2 and later. */
58	#define PGM_SAVED_STATE_VERSION_2_2_2 8
59	/** Saved state data unit version for 2.2.0. */
60	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
61	/** Saved state data unit version. */
62	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
63
64
65	/** @name Sparse state record types
66	* @{ */
67	/** Zero page. No data. */
68	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
69	/** Raw page. */
70	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
71	/** Raw MMIO2 page. */
72	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
73	/** Zero MMIO2 page. */
74	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
75	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
76	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
77	/** Raw shadowed ROM page. The protection (8-bit) preceeds the raw bits. */
78	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
79	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
80	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
81	/** ROM protection (8-bit). */
82	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
83	/** The last record type. */
84	#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
85	/** End marker. */
86	#define PGM_STATE_REC_END UINT8_C(0xff)
87	/** Flag indicating that the data is preceeded by the page address.
88	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
89	* range ID and a 32-bit page index.
90	*/
91	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
92	/** @} */
93
94	/** The CRC-32 for a zero page. */
95	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
96	/** The CRC-32 for a zero half page. */
97	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
98
99
100	/*******************************************************************************
101	* Structures and Typedefs *
102	*******************************************************************************/
103	/** For loading old saved states. (pre-smp) */
104	typedef struct
105	{
106	/** If set no conflict checks are required. (boolean) */
107	bool fMappingsFixed;
108	/** Size of fixed mapping */
109	uint32_t cbMappingFixed;
110	/** Base address (GC) of fixed mapping */
111	RTGCPTR GCPtrMappingFixed;
112	/** A20 gate mask.
113	* Our current approach to A20 emulation is to let REM do it and don't bother
114	* anywhere else. The interesting Guests will be operating with it enabled anyway.
115	* But whould need arrise, we'll subject physical addresses to this mask. */
116	RTGCPHYS GCPhysA20Mask;
117	/** A20 gate state - boolean! */
118	bool fA20Enabled;
119	/** The guest paging mode. */
120	PGMMODE enmGuestMode;
121	} PGMOLD;
122
123
124	/*******************************************************************************
125	* Global Variables *
126	*******************************************************************************/
127	/** PGM fields to save/load. */
128	static const SSMFIELD s_aPGMFields[] =
129	{
130	SSMFIELD_ENTRY( PGM, fMappingsFixed),
131	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
132	SSMFIELD_ENTRY( PGM, cbMappingFixed),
133	SSMFIELD_ENTRY_TERM()
134	};
135
136	static const SSMFIELD s_aPGMCpuFields[] =
137	{
138	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
139	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
140	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
141	SSMFIELD_ENTRY_TERM()
142	};
143
144	static const SSMFIELD s_aPGMFields_Old[] =
145	{
146	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
147	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
148	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
149	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
150	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
151	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
152	SSMFIELD_ENTRY_TERM()
153	};
154
155
156	/**
157	* Find the ROM tracking structure for the given page.
158	*
159	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
160	* that it's a ROM page.
161	* @param pVM The VM handle.
162	* @param GCPhys The address of the ROM page.
163	*/
164	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
165	{
166	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
167	pRomRange;
168	pRomRange = pRomRange->CTX_SUFF(pNext))
169	{
170	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
171	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
172	return &pRomRange->aPages[off >> PAGE_SHIFT];
173	}
174	return NULL;
175	}
176
177
178	/**
179	* Prepares the ROM pages for a live save.
180	*
181	* @returns VBox status code.
182	* @param pVM The VM handle.
183	*/
184	static int pgmR3PrepRomPages(PVM pVM)
185	{
186	/*
187	* Initialize the live save tracking in the ROM page descriptors.
188	*/
189	pgmLock(pVM);
190	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
191	{
192	PPGMRAMRANGE pRamHint = NULL;;
193	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
194
195	for (uint32_t iPage = 0; iPage < cPages; iPage++)
196	{
197	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
198	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
199	pRom->aPages[iPage].LiveSave.fDirty = true;
200	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
201	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
202	{
203	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
204	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
205	else
206	{
207	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
208	PPGMPAGE pPage;
209	int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
210	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
211	if (RT_SUCCESS(rc))
212	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage);
213	else
214	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
215	}
216	}
217	}
218
219	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
220	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
221	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
222	}
223	pgmUnlock(pVM);
224
225	return VINF_SUCCESS;
226	}
227
228
229	/**
230	* Assigns IDs to the ROM ranges and saves them.
231	*
232	* @returns VBox status code.
233	* @param pVM The VM handle.
234	* @param pSSM Saved state handle.
235	*/
236	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
237	{
238	pgmLock(pVM);
239	uint8_t id = 1;
240	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
241	{
242	pRom->idSavedState = id;
243	SSMR3PutU8(pSSM, id);
244	SSMR3PutStrZ(pSSM, ""); /* device name */
245	SSMR3PutU32(pSSM, 0); /* device instance */
246	SSMR3PutU8(pSSM, 0); /* region */
247	SSMR3PutStrZ(pSSM, pRom->pszDesc);
248	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
249	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
250	if (RT_FAILURE(rc))
251	break;
252	}
253	pgmUnlock(pVM);
254	return SSMR3PutU8(pSSM, UINT8_MAX);
255	}
256
257
258	/**
259	* Loads the ROM range ID assignments.
260	*
261	* @returns VBox status code.
262	*
263	* @param pVM The VM handle.
264	* @param pSSM The saved state handle.
265	*/
266	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
267	{
268	Assert(PGMIsLockOwner(pVM));
269
270	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
271	pRom->idSavedState = UINT8_MAX;
272
273	for (;;)
274	{
275	/*
276	* Read the data.
277	*/
278	uint8_t id;
279	int rc = SSMR3GetU8(pSSM, &id);
280	if (RT_FAILURE(rc))
281	return rc;
282	if (id == UINT8_MAX)
283	{
284	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
285	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX, ("%s\n", pRom->pszDesc));
286	return VINF_SUCCESS; /* the end */
287	}
288	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
289
290	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szDeviceName)];
291	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
292	AssertLogRelRCReturn(rc, rc);
293
294	uint32_t uInstance;
295	SSMR3GetU32(pSSM, &uInstance);
296	uint8_t iRegion;
297	SSMR3GetU8(pSSM, &iRegion);
298
299	char szDesc[64];
300	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
301	AssertLogRelRCReturn(rc, rc);
302
303	RTGCPHYS GCPhys;
304	SSMR3GetGCPhys(pSSM, &GCPhys);
305	RTGCPHYS cb;
306	rc = SSMR3GetGCPhys(pSSM, &cb);
307	if (RT_FAILURE(rc))
308	return rc;
309	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
310	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
311
312	/*
313	* Locate a matching ROM range.
314	*/
315	AssertLogRelMsgReturn( uInstance == 0
316	&& iRegion == 0
317	&& szDevName[0] == '\0',
318	("GCPhys=%RGp %s\n", GCPhys, szDesc),
319	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
320	PPGMROMRANGE pRom;
321	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
322	{
323	if ( pRom->idSavedState == UINT8_MAX
324	&& !strcmp(pRom->pszDesc, szDesc))
325	{
326	pRom->idSavedState = id;
327	break;
328	}
329	}
330	AssertLogRelMsgReturn(pRom, ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_LOAD_CONFIG_MISMATCH);
331	} /* forever */
332	}
333
334
335	/**
336	* Scan ROM pages.
337	*
338	* @param pVM The VM handle.
339	*/
340	static void pgmR3ScanRomPages(PVM pVM)
341	{
342	/*
343	* The shadow ROMs.
344	*/
345	pgmLock(pVM);
346	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
347	{
348	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
349	{
350	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
351	for (uint32_t iPage = 0; iPage < cPages; iPage++)
352	{
353	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
354	if (pRomPage->LiveSave.fWrittenTo)
355	{
356	pRomPage->LiveSave.fWrittenTo = false;
357	if (!pRomPage->LiveSave.fDirty)
358	{
359	pRomPage->LiveSave.fDirty = true;
360	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
361	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
362	}
363	pRomPage->LiveSave.fDirtiedRecently = true;
364	}
365	else
366	pRomPage->LiveSave.fDirtiedRecently = false;
367	}
368	}
369	}
370	pgmUnlock(pVM);
371	}
372
373
374	/**
375	* Takes care of the virgin ROM pages in the first pass.
376	*
377	* This is an attempt at simplifying the handling of ROM pages a little bit.
378	* This ASSUMES that no new ROM ranges will be added and that they won't be
379	* relinked in any way.
380	*
381	* @param pVM The VM handle.
382	* @param pSSM The SSM handle.
383	* @param fLiveSave Whether we're in a live save or not.
384	*/
385	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
386	{
387	pgmLock(pVM);
388	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
389	{
390	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
391	for (uint32_t iPage = 0; iPage < cPages; iPage++)
392	{
393	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
394	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
395
396	/* Get the virgin page descriptor. */
397	PPGMPAGE pPage;
398	if (PGMROMPROT_IS_ROM(enmProt))
399	pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
400	else
401	pPage = &pRom->aPages[iPage].Virgin;
402
403	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
404	int rc = VINF_SUCCESS;
405	char abPage[PAGE_SIZE];
406	if (!PGM_PAGE_IS_ZERO(pPage))
407	{
408	void const *pvPage;
409	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
410	if (RT_SUCCESS(rc))
411	memcpy(abPage, pvPage, PAGE_SIZE);
412	}
413	else
414	ASMMemZeroPage(abPage);
415	pgmUnlock(pVM);
416	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
417
418	/* Save it. */
419	if (iPage > 0)
420	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
421	else
422	{
423	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
424	SSMR3PutU8(pSSM, pRom->idSavedState);
425	SSMR3PutU32(pSSM, iPage);
426	}
427	SSMR3PutU8(pSSM, (uint8_t)enmProt);
428	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
429	if (RT_FAILURE(rc))
430	return rc;
431
432	/* Update state. */
433	pgmLock(pVM);
434	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
435	if (fLiveSave)
436	{
437	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
438	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
439	}
440	}
441	}
442	pgmUnlock(pVM);
443	return VINF_SUCCESS;
444	}
445
446
447	/**
448	* Saves dirty pages in the shadowed ROM ranges.
449	*
450	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
451	*
452	* @returns VBox status code.
453	* @param pVM The VM handle.
454	* @param pSSM The SSM handle.
455	* @param fLiveSave Whether it's a live save or not.
456	* @param fFinalPass Whether this is the final pass or not.
457	*/
458	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
459	{
460	/*
461	* The Shadowed ROMs.
462	*
463	* ASSUMES that the ROM ranges are fixed.
464	* ASSUMES that all the ROM ranges are mapped.
465	*/
466	pgmLock(pVM);
467	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
468	{
469	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
470	{
471	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
472	uint32_t iPrevPage = cPages;
473	for (uint32_t iPage = 0; iPage < cPages; iPage++)
474	{
475	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
476	if ( !fLiveSave
477	\|\| ( pRomPage->LiveSave.fDirty
478	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
479	&& !pRomPage->LiveSave.fWrittenTo)
480	\|\| fFinalPass
481	)
482	)
483	)
484	{
485	uint8_t abPage[PAGE_SIZE];
486	PGMROMPROT enmProt = pRomPage->enmProt;
487	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
488	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
489	bool fZero = PGM_PAGE_IS_ZERO(pPage);
490	int rc = VINF_SUCCESS;
491	if (!fZero)
492	{
493	void const *pvPage;
494	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
495	if (RT_SUCCESS(rc))
496	memcpy(abPage, pvPage, PAGE_SIZE);
497	}
498	if (fLiveSave && RT_SUCCESS(rc))
499	{
500	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
501	pRomPage->LiveSave.fDirty = false;
502	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
503	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
504	}
505	pgmUnlock(pVM);
506	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
507
508	if (iPage - 1U == iPrevPage && iPage > 0)
509	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
510	else
511	{
512	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
513	SSMR3PutU8(pSSM, pRom->idSavedState);
514	SSMR3PutU32(pSSM, iPage);
515	}
516	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
517	if (!fZero)
518	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
519	if (RT_FAILURE(rc))
520	return rc;
521
522	pgmLock(pVM);
523	iPrevPage = iPage;
524	}
525	/*
526	* In the final pass, make sure the protection is in sync.
527	*/
528	else if ( fFinalPass
529	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
530	{
531	PGMROMPROT enmProt = pRomPage->enmProt;
532	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
533	pgmUnlock(pVM);
534
535	if (iPage - 1U == iPrevPage && iPage > 0)
536	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
537	else
538	{
539	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
540	SSMR3PutU8(pSSM, pRom->idSavedState);
541	SSMR3PutU32(pSSM, iPage);
542	}
543	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
544	if (RT_FAILURE(rc))
545	return rc;
546
547	pgmLock(pVM);
548	iPrevPage = iPage;
549	}
550	}
551	}
552	}
553	pgmUnlock(pVM);
554	return VINF_SUCCESS;
555	}
556
557
558	/**
559	* Cleans up ROM pages after a live save.
560	*
561	* @param pVM The VM handle.
562	*/
563	static void pgmR3DoneRomPages(PVM pVM)
564	{
565	NOREF(pVM);
566	}
567
568
569	/**
570	* Prepares the MMIO2 pages for a live save.
571	*
572	* @returns VBox status code.
573	* @param pVM The VM handle.
574	*/
575	static int pgmR3PrepMmio2Pages(PVM pVM)
576	{
577	/*
578	* Initialize the live save tracking in the MMIO2 ranges.
579	* ASSUME nothing changes here.
580	*/
581	pgmLock(pVM);
582	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
583	{
584	uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
585	pgmUnlock(pVM);
586
587	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
588	if (!paLSPages)
589	return VERR_NO_MEMORY;
590	for (uint32_t iPage = 0; iPage < cPages; iPage++)
591	{
592	/* Initialize it as a dirty zero page. */
593	paLSPages[iPage].fDirty = true;
594	paLSPages[iPage].cUnchangedScans = 0;
595	paLSPages[iPage].fZero = true;
596	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
597	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
598	}
599
600	pgmLock(pVM);
601	pMmio2->paLSPages = paLSPages;
602	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
603	}
604	pgmUnlock(pVM);
605	return VINF_SUCCESS;
606	}
607
608
609	/**
610	* Assigns IDs to the MMIO2 ranges and saves them.
611	*
612	* @returns VBox status code.
613	* @param pVM The VM handle.
614	* @param pSSM Saved state handle.
615	*/
616	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
617	{
618	pgmLock(pVM);
619	uint8_t id = 1;
620	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
621	{
622	pMmio2->idSavedState = id;
623	SSMR3PutU8(pSSM, id);
624	SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pDevReg->szDeviceName);
625	SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
626	SSMR3PutU8(pSSM, pMmio2->iRegion);
627	SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
628	int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
629	if (RT_FAILURE(rc))
630	break;
631	}
632	pgmUnlock(pVM);
633	return SSMR3PutU8(pSSM, UINT8_MAX);
634	}
635
636
637	/**
638	* Loads the MMIO2 range ID assignments.
639	*
640	* @returns VBox status code.
641	*
642	* @param pVM The VM handle.
643	* @param pSSM The saved state handle.
644	*/
645	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
646	{
647	Assert(PGMIsLockOwner(pVM));
648
649	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
650	pMmio2->idSavedState = UINT8_MAX;
651
652	for (;;)
653	{
654	/*
655	* Read the data.
656	*/
657	uint8_t id;
658	int rc = SSMR3GetU8(pSSM, &id);
659	if (RT_FAILURE(rc))
660	return rc;
661	if (id == UINT8_MAX)
662	{
663	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
664	AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
665	return VINF_SUCCESS; /* the end */
666	}
667	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
668
669	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szDeviceName)];
670	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
671	AssertLogRelRCReturn(rc, rc);
672
673	uint32_t uInstance;
674	SSMR3GetU32(pSSM, &uInstance);
675	uint8_t iRegion;
676	SSMR3GetU8(pSSM, &iRegion);
677
678	char szDesc[64];
679	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
680	AssertLogRelRCReturn(rc, rc);
681
682	RTGCPHYS cb;
683	rc = SSMR3GetGCPhys(pSSM, &cb);
684	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
685
686	/*
687	* Locate a matching MMIO2 range.
688	*/
689	PPGMMMIO2RANGE pMmio2;
690	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
691	{
692	if ( pMmio2->idSavedState == UINT8_MAX
693	&& pMmio2->iRegion == iRegion
694	&& pMmio2->pDevInsR3->iInstance == uInstance
695	&& !strcmp(pMmio2->pDevInsR3->pDevReg->szDeviceName, szDevName))
696	{
697	pMmio2->idSavedState = id;
698	break;
699	}
700	}
701	AssertLogRelMsgReturn(pMmio2, ("%s/%u/%u: %s\n", szDevName, uInstance, iRegion, szDesc), VERR_SSM_LOAD_CONFIG_MISMATCH);
702	} /* forever */
703	}
704
705
706	/**
707	* Scans one MMIO2 page.
708	*
709	* @returns True if changed, false if unchanged.
710	*
711	* @param pVM The VM handle
712	* @param pbPage The page bits.
713	* @param pLSPage The live save tracking structure for the page.
714	*
715	*/
716	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
717	{
718	/*
719	* Special handling of zero pages.
720	*/
721	if (pLSPage->fZero)
722	{
723	if (ASMMemIsZeroPage(pbPage))
724	{
725	/* Not modified. */
726	if (pLSPage->fDirty)
727	pLSPage->cUnchangedScans++;
728	return false;
729	}
730
731	pLSPage->fZero = false;
732	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
733	}
734	else
735	{
736	/*
737	* CRC the first half, if it doesn't match the page is dirty and
738	* we won't check the 2nd half (we'll do that next time).
739	*/
740	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
741	if (u32CrcH1 == pLSPage->u32CrcH1)
742	{
743	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
744	if (u32CrcH2 == pLSPage->u32CrcH2)
745	{
746	/* Probably not modified. */
747	if (pLSPage->fDirty)
748	pLSPage->cUnchangedScans++;
749	return false;
750	}
751
752	pLSPage->u32CrcH2 = u32CrcH2;
753	}
754	else
755	{
756	pLSPage->u32CrcH1 = u32CrcH1;
757	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
758	&& ASMMemIsZeroPage(pbPage))
759	{
760	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
761	pLSPage->fZero = true;
762	}
763	}
764	}
765
766	/* dirty page path */
767	pLSPage->cUnchangedScans = 0;
768	if (!pLSPage->fDirty)
769	{
770	pLSPage->fDirty = true;
771	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
772	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
773	}
774	return true;
775	}
776
777
778	/**
779	* Scan for MMIO2 page modifications.
780	*
781	* @param pVM The VM handle.
782	* @param uPass The pass number.
783	*/
784	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
785	{
786	/*
787	* Since this is a bit expensive we lower the scan rate after a little while.
788	*/
789	if ( ( (uPass & 3) != 0
790	&& uPass > 10)
791	\|\| uPass == SSM_PASS_FINAL)
792	return;
793
794	pgmLock(pVM); /* paranoia */
795	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
796	{
797	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
798	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
799	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
800	pgmUnlock(pVM);
801
802	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
803	{
804	uint8_t const pbPage = (uint8_t const )pMmio2->pvR3 + iPage * PAGE_SIZE;
805	pgmR3ScanMmio2Page(pVM,pbPage, &paLSPages[iPage]);
806	}
807
808	pgmLock(pVM);
809	}
810	pgmUnlock(pVM);
811
812	}
813
814
815	/**
816	* Save quiescent MMIO2 pages.
817	*
818	* @returns VBox status code.
819	* @param pVM The VM handle.
820	* @param pSSM The SSM handle.
821	* @param fLiveSave Whether it's a live save or not.
822	* @param uPass The pass number.
823	*/
824	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
825	{
826	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
827	* device that we wish to know about changes.) */
828
829	int rc = VINF_SUCCESS;
830	if (uPass == SSM_PASS_FINAL)
831	{
832	/*
833	* The mop up round.
834	*/
835	pgmLock(pVM);
836	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
837	pMmio2 && RT_SUCCESS(rc);
838	pMmio2 = pMmio2->pNextR3)
839	{
840	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
841	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
842	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
843	uint32_t iPageLast = cPages;
844	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
845	{
846	uint8_t u8Type;
847	if (!fLiveSave)
848	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
849	else
850	{
851	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
852	if ( !paLSPages[iPage].fDirty
853	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
854	{
855	if (paLSPages[iPage].fZero)
856	continue;
857
858	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
859	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
860	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
861	continue;
862	}
863	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
864	}
865
866	if (iPage != 0 && iPage == iPageLast + 1)
867	rc = SSMR3PutU8(pSSM, u8Type);
868	else
869	{
870	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
871	SSMR3PutU8(pSSM, pMmio2->idSavedState);
872	rc = SSMR3PutU32(pSSM, iPage);
873	}
874	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
875	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
876	if (RT_FAILURE(rc))
877	break;
878	iPageLast = iPage;
879	}
880	}
881	pgmUnlock(pVM);
882	}
883	/*
884	* Reduce the rate after a little while since the current MMIO2 approach is
885	* a bit expensive.
886	* We position it two passes after the scan pass to avoid saving busy pages.
887	*/
888	else if ( uPass <= 10
889	\|\| (uPass & 3) == 2)
890	{
891	pgmLock(pVM);
892	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
893	pMmio2 && RT_SUCCESS(rc);
894	pMmio2 = pMmio2->pNextR3)
895	{
896	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
897	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
898	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
899	uint32_t iPageLast = cPages;
900	pgmUnlock(pVM);
901
902	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
903	{
904	/* Skip clean pages and pages which hasn't quiesced. */
905	if (!paLSPages[iPage].fDirty)
906	continue;
907	if (paLSPages[iPage].cUnchangedScans < 3)
908	continue;
909	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
910	continue;
911
912	/* Save it. */
913	bool const fZero = paLSPages[iPage].fZero;
914	uint8_t abPage[PAGE_SIZE];
915	if (!fZero)
916	{
917	memcpy(abPage, pbPage, PAGE_SIZE);
918	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
919	}
920
921	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
922	if (iPage != 0 && iPage == iPageLast + 1)
923	rc = SSMR3PutU8(pSSM, u8Type);
924	else
925	{
926	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
927	SSMR3PutU8(pSSM, pMmio2->idSavedState);
928	rc = SSMR3PutU32(pSSM, iPage);
929	}
930	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
931	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
932	if (RT_FAILURE(rc))
933	break;
934
935	/* Housekeeping. */
936	paLSPages[iPage].fDirty = false;
937	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
938	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
939	iPageLast = iPage;
940	}
941
942	pgmLock(pVM);
943	}
944	pgmUnlock(pVM);
945	}
946
947	return rc;
948	}
949
950
951	/**
952	* Cleans up MMIO2 pages after a live save.
953	*
954	* @param pVM The VM handle.
955	*/
956	static void pgmR3DoneMmio2Pages(PVM pVM)
957	{
958	/*
959	* Free the tracking structures for the MMIO2 pages.
960	* We do the freeing outside the lock in case the VM is running.
961	*/
962	pgmLock(pVM);
963	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
964	{
965	void *pvMmio2ToFree = pMmio2->paLSPages;
966	if (pvMmio2ToFree)
967	{
968	pMmio2->paLSPages = NULL;
969	pgmUnlock(pVM);
970	MMR3HeapFree(pvMmio2ToFree);
971	pgmLock(pVM);
972	}
973	}
974	pgmUnlock(pVM);
975	}
976
977
978	/**
979	* Prepares the RAM pages for a live save.
980	*
981	* @returns VBox status code.
982	* @param pVM The VM handle.
983	*/
984	static int pgmR3PrepRamPages(PVM pVM)
985	{
986
987	/*
988	* Try allocating tracking structures for the ram ranges.
989	*
990	* To avoid lock contention, we leave the lock every time we're allocating
991	* a new array. This means we'll have to ditch the allocation and start
992	* all over again if the RAM range list changes in-between.
993	*
994	* Note! pgmR3SaveDone will always be called and it is therefore responsible
995	* for cleaning up.
996	*/
997	PPGMRAMRANGE pCur;
998	pgmLock(pVM);
999	do
1000	{
1001	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1002	{
1003	if ( !pCur->paLSPages
1004	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1005	{
1006	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1007	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1008	pgmUnlock(pVM);
1009	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1010	if (!paLSPages)
1011	return VERR_NO_MEMORY;
1012	pgmLock(pVM);
1013	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1014	{
1015	pgmUnlock(pVM);
1016	MMR3HeapFree(paLSPages);
1017	pgmLock(pVM);
1018	break; /* try again */
1019	}
1020	pCur->paLSPages = paLSPages;
1021
1022	/*
1023	* Initialize the array.
1024	*/
1025	uint32_t iPage = cPages;
1026	while (iPage-- > 0)
1027	{
1028	/** @todo yield critsect! (after moving this away from EMT0) */
1029	PCPGMPAGE pPage = &pCur->aPages[iPage];
1030	paLSPages[iPage].cDirtied = 0;
1031	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1032	paLSPages[iPage].fWriteMonitored = 0;
1033	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1034	paLSPages[iPage].u2Reserved = 0;
1035	switch (PGM_PAGE_GET_TYPE(pPage))
1036	{
1037	case PGMPAGETYPE_RAM:
1038	if (PGM_PAGE_IS_ZERO(pPage))
1039	{
1040	paLSPages[iPage].fZero = 1;
1041	paLSPages[iPage].fShared = 0;
1042	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1043	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1044	#endif
1045	}
1046	else if (PGM_PAGE_IS_SHARED(pPage))
1047	{
1048	paLSPages[iPage].fZero = 0;
1049	paLSPages[iPage].fShared = 1;
1050	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1051	paLSPages[iPage].u32Crc = UINT32_MAX;
1052	#endif
1053	}
1054	else
1055	{
1056	paLSPages[iPage].fZero = 0;
1057	paLSPages[iPage].fShared = 0;
1058	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1059	paLSPages[iPage].u32Crc = UINT32_MAX;
1060	#endif
1061	}
1062	paLSPages[iPage].fIgnore = 0;
1063	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1064	break;
1065
1066	case PGMPAGETYPE_ROM_SHADOW:
1067	case PGMPAGETYPE_ROM:
1068	{
1069	paLSPages[iPage].fZero = 0;
1070	paLSPages[iPage].fShared = 0;
1071	paLSPages[iPage].fDirty = 0;
1072	paLSPages[iPage].fIgnore = 1;
1073	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1074	paLSPages[iPage].u32Crc = UINT32_MAX;
1075	#endif
1076	pVM->pgm.s.LiveSave.cIgnoredPages++;
1077	break;
1078	}
1079
1080	default:
1081	AssertMsgFailed(("%R[pgmpage]", pPage));
1082	case PGMPAGETYPE_MMIO2:
1083	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1084	paLSPages[iPage].fZero = 0;
1085	paLSPages[iPage].fShared = 0;
1086	paLSPages[iPage].fDirty = 0;
1087	paLSPages[iPage].fIgnore = 1;
1088	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1089	paLSPages[iPage].u32Crc = UINT32_MAX;
1090	#endif
1091	pVM->pgm.s.LiveSave.cIgnoredPages++;
1092	break;
1093
1094	case PGMPAGETYPE_MMIO:
1095	paLSPages[iPage].fZero = 0;
1096	paLSPages[iPage].fShared = 0;
1097	paLSPages[iPage].fDirty = 0;
1098	paLSPages[iPage].fIgnore = 1;
1099	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1100	paLSPages[iPage].u32Crc = UINT32_MAX;
1101	#endif
1102	pVM->pgm.s.LiveSave.cIgnoredPages++;
1103	break;
1104	}
1105	}
1106	}
1107	}
1108	} while (pCur);
1109	pgmUnlock(pVM);
1110
1111	return VINF_SUCCESS;
1112	}
1113
1114	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1115
1116	/**
1117	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1118	* info with it.
1119	*
1120	* @param pVM The VM handle.
1121	* @param pCur The current RAM range.
1122	* @param paLSPages The current array of live save page tracking
1123	* structures.
1124	* @param iPage The page index.
1125	*/
1126	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1127	{
1128	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1129	void const *pvPage;
1130	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1131	if (RT_SUCCESS(rc))
1132	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1133	else
1134	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1135	}
1136
1137
1138	/**
1139	* Verifies the CRC-32 for a page given it's raw bits.
1140	*
1141	* @param pvPage The page bits.
1142	* @param pCur The current RAM range.
1143	* @param paLSPages The current array of live save page tracking
1144	* structures.
1145	* @param iPage The page index.
1146	*/
1147	static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1148	{
1149	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1150	{
1151	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1152	Assert(!PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) \|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1153	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1154	("%08x != %08x for %RGp %R[pgmpage]\n", paLSPages[iPage].u32Crc, u32Crc,
1155	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1156	}
1157	}
1158
1159
1160	/**
1161	* Verfies the CRC-32 for a RAM page.
1162	*
1163	* @param pVM The VM handle.
1164	* @param pCur The current RAM range.
1165	* @param paLSPages The current array of live save page tracking
1166	* structures.
1167	* @param iPage The page index.
1168	*/
1169	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1170	{
1171	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1172	{
1173	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1174	void const *pvPage;
1175	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1176	if (RT_SUCCESS(rc))
1177	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage);
1178	}
1179	}
1180
1181	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1182
1183	/**
1184	* Scan for RAM page modifications and reprotect them.
1185	*
1186	* @param pVM The VM handle.
1187	* @param fFinalPass Whether this is the final pass or not.
1188	*/
1189	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1190	{
1191	/*
1192	* The RAM.
1193	*/
1194	RTGCPHYS GCPhysCur = 0;
1195	PPGMRAMRANGE pCur;
1196	pgmLock(pVM);
1197	do
1198	{
1199	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1200	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1201	{
1202	if ( pCur->GCPhysLast > GCPhysCur
1203	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1204	{
1205	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1206	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1207	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1208	GCPhysCur = 0;
1209	for (; iPage < cPages; iPage++)
1210	{
1211	/* Do yield first. */
1212	if ( !fFinalPass
1213	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1214	&& (iPage & 0x7ff) == 0x100
1215	#endif
1216	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1217	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1218	{
1219	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1220	break; /* restart */
1221	}
1222
1223	/* Skip already ignored pages. */
1224	if (paLSPages[iPage].fIgnore)
1225	continue;
1226
1227	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1228	{
1229	/*
1230	* A RAM page.
1231	*/
1232	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1233	{
1234	case PGM_PAGE_STATE_ALLOCATED:
1235	/** @todo Optimize this: Don't always re-enable write
1236	* monitoring if the page is known to be very busy. */
1237	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1238	{
1239	Assert(paLSPages[iPage].fWriteMonitored);
1240	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1241	Assert(pVM->pgm.s.cWrittenToPages > 0);
1242	pVM->pgm.s.cWrittenToPages--;
1243	}
1244	else
1245	{
1246	Assert(!paLSPages[iPage].fWriteMonitored);
1247	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1248	if (paLSPages[iPage].fZero)
1249	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1250	}
1251
1252	if (!paLSPages[iPage].fDirty)
1253	{
1254	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1255	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1256	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1257	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1258	}
1259
1260	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1261	pVM->pgm.s.cMonitoredPages++;
1262	paLSPages[iPage].fWriteMonitored = 1;
1263	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1264	paLSPages[iPage].fDirty = 1;
1265	paLSPages[iPage].fZero = 0;
1266	paLSPages[iPage].fShared = 0;
1267	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1268	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1269	#endif
1270	break;
1271
1272	case PGM_PAGE_STATE_WRITE_MONITORED:
1273	Assert(paLSPages[iPage].fWriteMonitored);
1274	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1275	{
1276	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1277	if (paLSPages[iPage].fWriteMonitoredJustNow)
1278	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1279	else
1280	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1281	#endif
1282	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1283	}
1284	else
1285	{
1286	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1287	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1288	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1289	#endif
1290	if (!paLSPages[iPage].fDirty)
1291	{
1292	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1293	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1294	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1295	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1296	}
1297	}
1298	break;
1299
1300	case PGM_PAGE_STATE_ZERO:
1301	if (!paLSPages[iPage].fZero)
1302	{
1303	paLSPages[iPage].fZero = 1;
1304	paLSPages[iPage].fShared = 0;
1305	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1306	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1307	#endif
1308	if (!paLSPages[iPage].fDirty)
1309	{
1310	paLSPages[iPage].fDirty = 1;
1311	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1312	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1313	}
1314	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1315	}
1316	break;
1317
1318	case PGM_PAGE_STATE_SHARED:
1319	if (!paLSPages[iPage].fShared)
1320	{
1321	paLSPages[iPage].fZero = 0;
1322	paLSPages[iPage].fShared = 1;
1323	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1324	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1325	#endif
1326	if (!paLSPages[iPage].fDirty)
1327	{
1328	paLSPages[iPage].fDirty = 1;
1329	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1330	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1331	}
1332	}
1333	break;
1334	}
1335	}
1336	else
1337	{
1338	/*
1339	* All other types => Ignore the page.
1340	*/
1341	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1342	paLSPages[iPage].fIgnore = 1;
1343	if (paLSPages[iPage].fWriteMonitored)
1344	{
1345	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1346	* pages! */
1347	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1348	{
1349	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1350	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1351	Assert(pVM->pgm.s.cMonitoredPages > 0);
1352	pVM->pgm.s.cMonitoredPages--;
1353	}
1354	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1355	{
1356	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1357	Assert(pVM->pgm.s.cWrittenToPages > 0);
1358	pVM->pgm.s.cWrittenToPages--;
1359	}
1360	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1361	}
1362
1363	/** @todo the counting doesn't quite work out here. fix later? */
1364	if (paLSPages[iPage].fDirty)
1365	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1366	else
1367	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1368	pVM->pgm.s.LiveSave.cIgnoredPages++;
1369	}
1370	} /* for each page in range */
1371
1372	if (GCPhysCur != 0)
1373	break; /* Yield + ramrange change */
1374	GCPhysCur = pCur->GCPhysLast;
1375	}
1376	} /* for each range */
1377	} while (pCur);
1378	pgmUnlock(pVM);
1379	}
1380
1381
1382	/**
1383	* Save quiescent RAM pages.
1384	*
1385	* @returns VBox status code.
1386	* @param pVM The VM handle.
1387	* @param pSSM The SSM handle.
1388	* @param fLiveSave Whether it's a live save or not.
1389	* @param uPass The pass number.
1390	*/
1391	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1392	{
1393	/*
1394	* The RAM.
1395	*/
1396	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1397	RTGCPHYS GCPhysCur = 0;
1398	PPGMRAMRANGE pCur;
1399	pgmLock(pVM);
1400	do
1401	{
1402	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1403	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1404	{
1405	if ( pCur->GCPhysLast > GCPhysCur
1406	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1407	{
1408	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1409	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1410	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1411	GCPhysCur = 0;
1412	for (; iPage < cPages; iPage++)
1413	{
1414	/* Do yield first. */
1415	if ( uPass != SSM_PASS_FINAL
1416	&& (iPage & 0x7ff) == 0x100
1417	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1418	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1419	{
1420	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1421	break; /* restart */
1422	}
1423
1424	/*
1425	* Only save pages that hasn't changed since last scan and are dirty.
1426	*/
1427	if ( uPass != SSM_PASS_FINAL
1428	&& paLSPages)
1429	{
1430	if (!paLSPages[iPage].fDirty)
1431	continue;
1432	if (paLSPages[iPage].fWriteMonitoredJustNow)
1433	continue;
1434	if (paLSPages[iPage].fIgnore)
1435	continue;
1436	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM) /* in case of recent ramppings */
1437	continue;
1438	if ( PGM_PAGE_GET_STATE(&pCur->aPages[iPage])
1439	!= ( paLSPages[iPage].fZero
1440	? PGM_PAGE_STATE_ZERO
1441	: paLSPages[iPage].fShared
1442	? PGM_PAGE_STATE_SHARED
1443	: PGM_PAGE_STATE_WRITE_MONITORED))
1444	continue;
1445	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1446	continue;
1447	}
1448	else
1449	{
1450	if ( paLSPages
1451	&& !paLSPages[iPage].fDirty
1452	&& !paLSPages[iPage].fIgnore)
1453	{
1454	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1455	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1456	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1457	#endif
1458	continue;
1459	}
1460	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1461	continue;
1462	}
1463
1464	/*
1465	* Do the saving outside the PGM critsect since SSM may block on I/O.
1466	*/
1467	int rc;
1468	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1469	bool fZero = PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]);
1470
1471	if (!fZero)
1472	{
1473	/*
1474	* Copy the page and then save it outside the lock (since any
1475	* SSM call may block).
1476	*/
1477	uint8_t abPage[PAGE_SIZE];
1478	void const *pvPage;
1479	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1480	if (RT_SUCCESS(rc))
1481	{
1482	memcpy(abPage, pvPage, PAGE_SIZE);
1483	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1484	if (paLSPages)
1485	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage);
1486	#endif
1487	}
1488	pgmUnlock(pVM);
1489	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1490
1491	if (GCPhys == GCPhysLast + PAGE_SIZE)
1492	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1493	else
1494	{
1495	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1496	SSMR3PutGCPhys(pSSM, GCPhys);
1497	}
1498	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1499	}
1500	else
1501	{
1502	/*
1503	* Dirty zero page.
1504	*/
1505	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1506	if (paLSPages)
1507	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1508	#endif
1509	pgmUnlock(pVM);
1510
1511	if (GCPhys == GCPhysLast + PAGE_SIZE)
1512	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1513	else
1514	{
1515	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1516	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1517	}
1518	}
1519	if (RT_FAILURE(rc))
1520	return rc;
1521
1522	pgmLock(pVM);
1523	GCPhysLast = GCPhys;
1524	if (paLSPages)
1525	{
1526	paLSPages[iPage].fDirty = 0;
1527	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1528	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1529	if (fZero)
1530	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1531	}
1532	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1533	{
1534	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1535	break; /* restart */
1536	}
1537
1538	} /* for each page in range */
1539
1540	if (GCPhysCur != 0)
1541	break; /* Yield + ramrange change */
1542	GCPhysCur = pCur->GCPhysLast;
1543	}
1544	} /* for each range */
1545	} while (pCur);
1546	pgmUnlock(pVM);
1547
1548	return VINF_SUCCESS;
1549	}
1550
1551
1552	/**
1553	* Cleans up RAM pages after a live save.
1554	*
1555	* @param pVM The VM handle.
1556	*/
1557	static void pgmR3DoneRamPages(PVM pVM)
1558	{
1559	/*
1560	* Free the tracking arrays and disable write monitoring.
1561	*
1562	* Play nice with the PGM lock in case we're called while the VM is still
1563	* running. This means we have to delay the freeing since we wish to use
1564	* paLSPages as an indicator of which RAM ranges which we need to scan for
1565	* write monitored pages.
1566	*/
1567	void *pvToFree = NULL;
1568	PPGMRAMRANGE pCur;
1569	uint32_t cMonitoredPages = 0;
1570	pgmLock(pVM);
1571	do
1572	{
1573	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1574	{
1575	if (pCur->paLSPages)
1576	{
1577	if (pvToFree)
1578	{
1579	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1580	pgmUnlock(pVM);
1581	MMR3HeapFree(pvToFree);
1582	pvToFree = NULL;
1583	pgmLock(pVM);
1584	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1585	break; /* start over again. */
1586	}
1587
1588	pvToFree = pCur->paLSPages;
1589	pCur->paLSPages = NULL;
1590
1591	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1592	while (iPage--)
1593	{
1594	PPGMPAGE pPage = &pCur->aPages[iPage];
1595	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1596	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1597	{
1598	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1599	cMonitoredPages++;
1600	}
1601	}
1602	}
1603	}
1604	} while (pCur);
1605
1606	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1607	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1608	pVM->pgm.s.cMonitoredPages = 0;
1609	else
1610	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1611
1612	pgmUnlock(pVM);
1613
1614	MMR3HeapFree(pvToFree);
1615	pvToFree = NULL;
1616	}
1617
1618
1619	/**
1620	* Execute a live save pass.
1621	*
1622	* @returns VBox status code.
1623	*
1624	* @param pVM The VM handle.
1625	* @param pSSM The SSM handle.
1626	*/
1627	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1628	{
1629	int rc;
1630
1631	/*
1632	* Save the MMIO2 and ROM range IDs in pass 0.
1633	*/
1634	if (uPass == 0)
1635	{
1636	rc = pgmR3SaveRomRanges(pVM, pSSM);
1637	if (RT_FAILURE(rc))
1638	return rc;
1639	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1640	if (RT_FAILURE(rc))
1641	return rc;
1642	}
1643
1644	/*
1645	* Do the scanning.
1646	*/
1647	pgmR3ScanRomPages(pVM);
1648	pgmR3ScanMmio2Pages(pVM, uPass);
1649	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1650	pgmR3PoolClearAll(pVM); /** @todo this could perhaps be optimized a bit. */
1651
1652	/*
1653	* Save the pages.
1654	*/
1655	if (uPass == 0)
1656	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1657	else
1658	rc = VINF_SUCCESS;
1659	if (RT_SUCCESS(rc))
1660	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1661	if (RT_SUCCESS(rc))
1662	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1663	if (RT_SUCCESS(rc))
1664	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1665	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1666
1667	return rc;
1668	}
1669
1670	#include <iprt/stream.h>
1671
1672	/**
1673	* Votes on whether the live save phase is done or not.
1674	*
1675	* @returns VBox status code.
1676	*
1677	* @param pVM The VM handle.
1678	* @param pSSM The SSM handle.
1679	*/
1680	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM)
1681	{
1682	#if 1
1683	RTPrintf("# Rom[R/D/Z/M]=%03x/%03x/%03x/%03x Mmio2=%04x/%04x/%04x/%04x Ram=%06x/%06x/%06x/%06x Ignored=%03x\n",
1684	pVM->pgm.s.LiveSave.Rom.cReadyPages,
1685	pVM->pgm.s.LiveSave.Rom.cDirtyPages,
1686	pVM->pgm.s.LiveSave.Rom.cZeroPages,
1687	pVM->pgm.s.LiveSave.Rom.cMonitoredPages,
1688	pVM->pgm.s.LiveSave.Mmio2.cReadyPages,
1689	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages,
1690	pVM->pgm.s.LiveSave.Mmio2.cZeroPages,
1691	pVM->pgm.s.LiveSave.Mmio2.cMonitoredPages,
1692	pVM->pgm.s.LiveSave.Ram.cReadyPages,
1693	pVM->pgm.s.LiveSave.Ram.cDirtyPages,
1694	pVM->pgm.s.LiveSave.Ram.cZeroPages,
1695	pVM->pgm.s.LiveSave.Ram.cMonitoredPages,
1696	pVM->pgm.s.LiveSave.cIgnoredPages
1697	);
1698	static int s_iHack = 0;
1699	if ((++s_iHack % 42) == 0)
1700	return VINF_SUCCESS;
1701	RTThreadSleep(1000);
1702
1703	#else
1704	if ( pVM->pgm.s.LiveSave.Rom.cDirtyPages
1705	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1706	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1707	< 256) /* semi random numbers. */
1708	return VINF_SUCCESS;
1709	#endif
1710	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1711	}
1712
1713	#ifndef VBOX_WITH_LIVE_MIGRATION
1714
1715	/**
1716	* Save zero indicator + bits for the specified page.
1717	*
1718	* @returns VBox status code, errors are logged/asserted before returning.
1719	* @param pVM The VM handle.
1720	* @param pSSH The saved state handle.
1721	* @param pPage The page to save.
1722	* @param GCPhys The address of the page.
1723	* @param pRam The ram range (for error logging).
1724	*/
1725	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
1726	{
1727	int rc;
1728	if (PGM_PAGE_IS_ZERO(pPage))
1729	rc = SSMR3PutU8(pSSM, 0);
1730	else
1731	{
1732	void const *pvPage;
1733	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
1734	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
1735
1736	SSMR3PutU8(pSSM, 1);
1737	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
1738	}
1739	return rc;
1740	}
1741
1742
1743	/**
1744	* Save a shadowed ROM page.
1745	*
1746	* Format: Type, protection, and two pages with zero indicators.
1747	*
1748	* @returns VBox status code, errors are logged/asserted before returning.
1749	* @param pVM The VM handle.
1750	* @param pSSH The saved state handle.
1751	* @param pPage The page to save.
1752	* @param GCPhys The address of the page.
1753	* @param pRam The ram range (for error logging).
1754	*/
1755	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
1756	{
1757	/* Need to save both pages and the current state. */
1758	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
1759	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
1760
1761	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
1762	SSMR3PutU8(pSSM, pRomPage->enmProt);
1763
1764	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
1765	if (RT_SUCCESS(rc))
1766	{
1767	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
1768	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
1769	}
1770	return rc;
1771	}
1772
1773	#endif /* !VBOX_WITH_LIVE_MIGRATION */
1774
1775
1776	/**
1777	* Prepare for a live save operation.
1778	*
1779	* This will attempt to allocate and initialize the tracking structures. It
1780	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1781	* pgmR3SaveDone will do the cleanups.
1782	*
1783	* @returns VBox status code.
1784	*
1785	* @param pVM The VM handle.
1786	* @param pSSM The SSM handle.
1787	*/
1788	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1789	{
1790	/*
1791	* Indicate that we will be using the write monitoring.
1792	*/
1793	pgmLock(pVM);
1794	/** @todo find a way of mediating this when more users are added. */
1795	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1796	{
1797	pgmUnlock(pVM);
1798	AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1799	}
1800	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1801	pgmUnlock(pVM);
1802
1803	/*
1804	* Initialize the statistics.
1805	*/
1806	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1807	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1808	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1809	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1810	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1811	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1812	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1813	pVM->pgm.s.LiveSave.fActive = true;
1814
1815	/*
1816	* Per page type.
1817	*/
1818	int rc = pgmR3PrepRomPages(pVM);
1819	if (RT_SUCCESS(rc))
1820	rc = pgmR3PrepMmio2Pages(pVM);
1821	if (RT_SUCCESS(rc))
1822	rc = pgmR3PrepRamPages(pVM);
1823	return rc;
1824	}
1825
1826
1827	/**
1828	* Execute state save operation.
1829	*
1830	* @returns VBox status code.
1831	* @param pVM VM Handle.
1832	* @param pSSM SSM operation handle.
1833	*/
1834	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1835	{
1836	int rc;
1837	unsigned i;
1838	PPGM pPGM = &pVM->pgm.s;
1839
1840	/*
1841	* Lock PGM and set the no-more-writes indicator.
1842	*/
1843	pgmLock(pVM);
1844	pVM->pgm.s.fNoMorePhysWrites = true;
1845
1846	/*
1847	* Save basic data (required / unaffected by relocation).
1848	*/
1849	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
1850
1851	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1852	{
1853	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1854	SSMR3PutStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
1855	}
1856
1857	/*
1858	* The guest mappings.
1859	*/
1860	i = 0;
1861	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1862	{
1863	SSMR3PutU32( pSSM, i);
1864	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1865	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
1866	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1867	}
1868	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
1869
1870	#ifdef VBOX_WITH_LIVE_MIGRATION
1871	/*
1872	* Save the (remainder of the) memory.
1873	*/
1874	if (RT_SUCCESS(rc))
1875	{
1876	if (pVM->pgm.s.LiveSave.fActive)
1877	{
1878	pgmR3ScanRomPages(pVM);
1879	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
1880	pgmR3ScanRamPages(pVM, true /fFinalPass/);
1881
1882	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
1883	if (RT_SUCCESS(rc))
1884	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1885	if (RT_SUCCESS(rc))
1886	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1887	}
1888	else
1889	{
1890	rc = pgmR3SaveRomRanges(pVM, pSSM);
1891	if (RT_SUCCESS(rc))
1892	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1893	if (RT_SUCCESS(rc))
1894	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
1895	if (RT_SUCCESS(rc))
1896	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
1897	if (RT_SUCCESS(rc))
1898	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
1899	if (RT_SUCCESS(rc))
1900	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
1901	}
1902	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1903	}
1904
1905	#else /* !VBOX_WITH_LIVE_MIGRATION */
1906	/*
1907	* Ram ranges and the memory they describe.
1908	*/
1909	i = 0;
1910	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
1911	{
1912	/*
1913	* Save the ram range details.
1914	*/
1915	SSMR3PutU32(pSSM, i);
1916	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
1917	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
1918	SSMR3PutGCPhys(pSSM, pRam->cb);
1919	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
1920	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
1921
1922	/*
1923	* Iterate the pages, only two special case.
1924	*/
1925	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
1926	for (uint32_t iPage = 0; iPage < cPages; iPage++)
1927	{
1928	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1929	PPGMPAGE pPage = &pRam->aPages[iPage];
1930	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
1931
1932	if (uType == PGMPAGETYPE_ROM_SHADOW) /** @todo This isn't right, but it doesn't currently matter. */
1933	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
1934	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
1935	{
1936	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
1937	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
1938	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
1939	}
1940	else
1941	{
1942	SSMR3PutU8(pSSM, uType);
1943	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
1944	}
1945	if (RT_FAILURE(rc))
1946	break;
1947	}
1948	if (RT_FAILURE(rc))
1949	break;
1950	}
1951
1952	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
1953	#endif /* !VBOX_WITH_LIVE_MIGRATION */
1954
1955	pgmUnlock(pVM);
1956	return rc;
1957	}
1958
1959
1960	/**
1961	* Cleans up after an save state operation.
1962	*
1963	* @returns VBox status code.
1964	* @param pVM VM Handle.
1965	* @param pSSM SSM operation handle.
1966	*/
1967	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
1968	{
1969	/*
1970	* Do per page type cleanups first.
1971	*/
1972	if (pVM->pgm.s.LiveSave.fActive)
1973	{
1974	pgmR3DoneRomPages(pVM);
1975	pgmR3DoneMmio2Pages(pVM);
1976	pgmR3DoneRamPages(pVM);
1977	}
1978
1979	/*
1980	* Clear the live save indicator and disengage write monitoring.
1981	*/
1982	pgmLock(pVM);
1983	pVM->pgm.s.LiveSave.fActive = false;
1984	/** @todo this is blindly assuming that we're the only user of write
1985	* monitoring. Fix this when more users are added. */
1986	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
1987	pgmUnlock(pVM);
1988
1989	return VINF_SUCCESS;
1990	}
1991
1992
1993	/**
1994	* Prepare state load operation.
1995	*
1996	* @returns VBox status code.
1997	* @param pVM VM Handle.
1998	* @param pSSM SSM operation handle.
1999	*/
2000	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2001	{
2002	/*
2003	* Call the reset function to make sure all the memory is cleared.
2004	*/
2005	PGMR3Reset(pVM);
2006	pVM->pgm.s.LiveSave.fActive = false;
2007	NOREF(pSSM);
2008	return VINF_SUCCESS;
2009	}
2010
2011
2012	/**
2013	* Load an ignored page.
2014	*
2015	* @returns VBox status code.
2016	* @param pSSM The saved state handle.
2017	*/
2018	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2019	{
2020	uint8_t abPage[PAGE_SIZE];
2021	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2022	}
2023
2024
2025	/**
2026	* Loads a page without any bits in the saved state, i.e. making sure it's
2027	* really zero.
2028	*
2029	* @returns VBox status code.
2030	* @param pVM The VM handle.
2031	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2032	* state).
2033	* @param pPage The guest page tracking structure.
2034	* @param GCPhys The page address.
2035	* @param pRam The ram range (logging).
2036	*/
2037	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2038	{
2039	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2040	&& uType != PGMPAGETYPE_INVALID)
2041	return VERR_SSM_UNEXPECTED_DATA;
2042
2043	/* I think this should be sufficient. */
2044	if (!PGM_PAGE_IS_ZERO(pPage))
2045	return VERR_SSM_UNEXPECTED_DATA;
2046
2047	NOREF(pVM);
2048	NOREF(GCPhys);
2049	NOREF(pRam);
2050	return VINF_SUCCESS;
2051	}
2052
2053
2054	/**
2055	* Loads a page from the saved state.
2056	*
2057	* @returns VBox status code.
2058	* @param pVM The VM handle.
2059	* @param pSSM The SSM handle.
2060	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2061	* state).
2062	* @param pPage The guest page tracking structure.
2063	* @param GCPhys The page address.
2064	* @param pRam The ram range (logging).
2065	*/
2066	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2067	{
2068	/*
2069	* Match up the type, dealing with MMIO2 aliases (dropped).
2070	*/
2071	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2072	\|\| uType == PGMPAGETYPE_INVALID,
2073	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2074	VERR_SSM_UNEXPECTED_DATA);
2075
2076	/*
2077	* Load the page.
2078	*/
2079	void *pvPage;
2080	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2081	if (RT_SUCCESS(rc))
2082	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2083
2084	return rc;
2085	}
2086
2087
2088	/**
2089	* Loads a page (counter part to pgmR3SavePage).
2090	*
2091	* @returns VBox status code, fully bitched errors.
2092	* @param pVM The VM handle.
2093	* @param pSSM The SSM handle.
2094	* @param uType The page type.
2095	* @param pPage The page.
2096	* @param GCPhys The page address.
2097	* @param pRam The RAM range (for error messages).
2098	*/
2099	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2100	{
2101	uint8_t uState;
2102	int rc = SSMR3GetU8(pSSM, &uState);
2103	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2104	if (uState == 0 /* zero */)
2105	rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2106	else if (uState == 1)
2107	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2108	else
2109	rc = VERR_INTERNAL_ERROR;
2110	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2111	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2112	rc);
2113	return VINF_SUCCESS;
2114	}
2115
2116
2117	/**
2118	* Loads a shadowed ROM page.
2119	*
2120	* @returns VBox status code, errors are fully bitched.
2121	* @param pVM The VM handle.
2122	* @param pSSM The saved state handle.
2123	* @param pPage The page.
2124	* @param GCPhys The page address.
2125	* @param pRam The RAM range (for error messages).
2126	*/
2127	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2128	{
2129	/*
2130	* Load and set the protection first, then load the two pages, the first
2131	* one is the active the other is the passive.
2132	*/
2133	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2134	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2135
2136	uint8_t uProt;
2137	int rc = SSMR3GetU8(pSSM, &uProt);
2138	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2139	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2140	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2141	&& enmProt < PGMROMPROT_END,
2142	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2143	VERR_SSM_UNEXPECTED_DATA);
2144
2145	if (pRomPage->enmProt != enmProt)
2146	{
2147	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2148	AssertLogRelRCReturn(rc, rc);
2149	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2150	}
2151
2152	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2153	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2154	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2155	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2156
2157	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2158	* used down the line (will the 2nd page will be written to the first
2159	* one because of a false TLB hit since the TLB is using GCPhys and
2160	* doesn't check the HCPhys of the desired page). */
2161	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2162	if (RT_SUCCESS(rc))
2163	{
2164	pPageActive = pPage;
2165	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2166	}
2167	return rc;
2168	}
2169
2170	/**
2171	* Ram range flags and bits for older versions of the saved state.
2172	*
2173	* @returns VBox status code.
2174	*
2175	* @param pVM The VM handle
2176	* @param pSSM The SSM handle.
2177	* @param uVersion The saved state version.
2178	*/
2179	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2180	{
2181	PPGM pPGM = &pVM->pgm.s;
2182
2183	/*
2184	* Ram range flags and bits.
2185	*/
2186	uint32_t i = 0;
2187	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2188	{
2189	/* Check the seqence number / separator. */
2190	uint32_t u32Sep;
2191	int rc = SSMR3GetU32(pSSM, &u32Sep);
2192	if (RT_FAILURE(rc))
2193	return rc;
2194	if (u32Sep == ~0U)
2195	break;
2196	if (u32Sep != i)
2197	{
2198	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2199	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2200	}
2201	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2202
2203	/* Get the range details. */
2204	RTGCPHYS GCPhys;
2205	SSMR3GetGCPhys(pSSM, &GCPhys);
2206	RTGCPHYS GCPhysLast;
2207	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2208	RTGCPHYS cb;
2209	SSMR3GetGCPhys(pSSM, &cb);
2210	uint8_t fHaveBits;
2211	rc = SSMR3GetU8(pSSM, &fHaveBits);
2212	if (RT_FAILURE(rc))
2213	return rc;
2214	if (fHaveBits & ~1)
2215	{
2216	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2217	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2218	}
2219	size_t cchDesc = 0;
2220	char szDesc[256];
2221	szDesc[0] = '\0';
2222	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2223	{
2224	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2225	if (RT_FAILURE(rc))
2226	return rc;
2227	/* Since we've modified the description strings in r45878, only compare
2228	them if the saved state is more recent. */
2229	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2230	cchDesc = strlen(szDesc);
2231	}
2232
2233	/*
2234	* Match it up with the current range.
2235	*
2236	* Note there is a hack for dealing with the high BIOS mapping
2237	* in the old saved state format, this means we might not have
2238	* a 1:1 match on success.
2239	*/
2240	if ( ( GCPhys != pRam->GCPhys
2241	\|\| GCPhysLast != pRam->GCPhysLast
2242	\|\| cb != pRam->cb
2243	\|\| ( cchDesc
2244	&& strcmp(szDesc, pRam->pszDesc)) )
2245	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2246	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2247	\|\| GCPhys != UINT32_C(0xfff80000)
2248	\|\| GCPhysLast != UINT32_C(0xffffffff)
2249	\|\| pRam->GCPhysLast != GCPhysLast
2250	\|\| pRam->GCPhys < GCPhys
2251	\|\| !fHaveBits)
2252	)
2253	{
2254	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2255	"State : %RGp-%RGp %RGp bytes %s %s\n",
2256	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2257	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2258	/*
2259	* If we're loading a state for debugging purpose, don't make a fuss if
2260	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2261	*/
2262	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2263	\|\| GCPhys < 8 * _1M)
2264	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2265
2266	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2267	continue;
2268	}
2269
2270	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2271	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2272	{
2273	/*
2274	* Load the pages one by one.
2275	*/
2276	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2277	{
2278	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2279	PPGMPAGE pPage = &pRam->aPages[iPage];
2280	uint8_t uType;
2281	rc = SSMR3GetU8(pSSM, &uType);
2282	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2283	if (uType == PGMPAGETYPE_ROM_SHADOW)
2284	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2285	else
2286	rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2287	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2288	}
2289	}
2290	else
2291	{
2292	/*
2293	* Old format.
2294	*/
2295	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2296
2297	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2298	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2299	uint32_t fFlags = 0;
2300	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2301	{
2302	uint16_t u16Flags;
2303	rc = SSMR3GetU16(pSSM, &u16Flags);
2304	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2305	fFlags \|= u16Flags;
2306	}
2307
2308	/* Load the bits */
2309	if ( !fHaveBits
2310	&& GCPhysLast < UINT32_C(0xe0000000))
2311	{
2312	/*
2313	* Dynamic chunks.
2314	*/
2315	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2316	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2317	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2318	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2319
2320	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2321	{
2322	uint8_t fPresent;
2323	rc = SSMR3GetU8(pSSM, &fPresent);
2324	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2325	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2326	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2327	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2328
2329	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2330	{
2331	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2332	PPGMPAGE pPage = &pRam->aPages[iPage];
2333	if (fPresent)
2334	{
2335	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2336	rc = pgmR3LoadPageToDevNullOld(pSSM);
2337	else
2338	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2339	}
2340	else
2341	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2342	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2343	}
2344	}
2345	}
2346	else if (pRam->pvR3)
2347	{
2348	/*
2349	* MMIO2.
2350	*/
2351	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2352	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2353	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2354	AssertLogRelMsgReturn(pRam->pvR3,
2355	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2356	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2357
2358	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2359	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2360	}
2361	else if (GCPhysLast < UINT32_C(0xfff80000))
2362	{
2363	/*
2364	* PCI MMIO, no pages saved.
2365	*/
2366	}
2367	else
2368	{
2369	/*
2370	* Load the 0xfff80000..0xffffffff BIOS range.
2371	* It starts with X reserved pages that we have to skip over since
2372	* the RAMRANGE create by the new code won't include those.
2373	*/
2374	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2375	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2376	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2377	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2378	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2379	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2380	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2381
2382	/* Skip wasted reserved pages before the ROM. */
2383	while (GCPhys < pRam->GCPhys)
2384	{
2385	rc = pgmR3LoadPageToDevNullOld(pSSM);
2386	GCPhys += PAGE_SIZE;
2387	}
2388
2389	/* Load the bios pages. */
2390	cPages = pRam->cb >> PAGE_SHIFT;
2391	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2392	{
2393	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2394	PPGMPAGE pPage = &pRam->aPages[iPage];
2395
2396	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2397	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2398	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2399	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2400	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2401	}
2402	}
2403	}
2404	}
2405
2406	return VINF_SUCCESS;
2407	}
2408
2409
2410	/**
2411	* Worker for pgmR3Load and pgmR3LoadLocked.
2412	*
2413	* @returns VBox status code.
2414	*
2415	* @param pVM The VM handle.
2416	* @param pSSM The SSM handle.
2417	* @param uVersion The saved state version.
2418	*
2419	* @todo This needs splitting up if more record types or code twists are
2420	* added...
2421	*/
2422	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2423	{
2424	/*
2425	* Process page records until we hit the terminator.
2426	*/
2427	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2428	PPGMRAMRANGE pRamHint = NULL;
2429	uint8_t id = UINT8_MAX;
2430	uint32_t iPage = UINT32_MAX - 10;
2431	PPGMROMRANGE pRom = NULL;
2432	PPGMMMIO2RANGE pMmio2 = NULL;
2433	for (;;)
2434	{
2435	/*
2436	* Get the record type and flags.
2437	*/
2438	uint8_t u8;
2439	int rc = SSMR3GetU8(pSSM, &u8);
2440	if (RT_FAILURE(rc))
2441	return rc;
2442	if (u8 == PGM_STATE_REC_END)
2443	return VINF_SUCCESS;
2444	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2445	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2446	{
2447	/*
2448	* RAM page.
2449	*/
2450	case PGM_STATE_REC_RAM_ZERO:
2451	case PGM_STATE_REC_RAM_RAW:
2452	{
2453	/*
2454	* Get the address and resolve it into a page descriptor.
2455	*/
2456	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2457	GCPhys += PAGE_SIZE;
2458	else
2459	{
2460	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2461	if (RT_FAILURE(rc))
2462	return rc;
2463	}
2464	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2465
2466	PPGMPAGE pPage;
2467	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2468	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2469
2470	/*
2471	* Take action according to the record type.
2472	*/
2473	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2474	{
2475	case PGM_STATE_REC_RAM_ZERO:
2476	{
2477	if (PGM_PAGE_IS_ZERO(pPage))
2478	break;
2479	/** @todo implement zero page replacing. */
2480	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2481	void *pvDstPage;
2482	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2483	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2484	ASMMemZeroPage(pvDstPage);
2485	break;
2486	}
2487
2488	case PGM_STATE_REC_RAM_RAW:
2489	{
2490	void *pvDstPage;
2491	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2492	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2493	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2494	if (RT_FAILURE(rc))
2495	return rc;
2496	break;
2497	}
2498
2499	default:
2500	AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2501	}
2502	id = UINT8_MAX;
2503	break;
2504	}
2505
2506	/*
2507	* MMIO2 page.
2508	*/
2509	case PGM_STATE_REC_MMIO2_RAW:
2510	case PGM_STATE_REC_MMIO2_ZERO:
2511	{
2512	/*
2513	* Get the ID + page number and resolved that into a MMIO2 page.
2514	*/
2515	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2516	iPage++;
2517	else
2518	{
2519	SSMR3GetU8(pSSM, &id);
2520	rc = SSMR3GetU32(pSSM, &iPage);
2521	if (RT_FAILURE(rc))
2522	return rc;
2523	}
2524	if ( !pMmio2
2525	\|\| pMmio2->idSavedState != id)
2526	{
2527	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2528	if (pMmio2->idSavedState == id)
2529	break;
2530	AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2531	}
2532	AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2533	void pvDstPage = (uint8_t )pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2534
2535	/*
2536	* Load the page bits.
2537	*/
2538	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2539	ASMMemZeroPage(pvDstPage);
2540	else
2541	{
2542	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2543	if (RT_FAILURE(rc))
2544	return rc;
2545	}
2546	GCPhys = NIL_RTGCPHYS;
2547	break;
2548	}
2549
2550	/*
2551	* ROM pages.
2552	*/
2553	case PGM_STATE_REC_ROM_VIRGIN:
2554	case PGM_STATE_REC_ROM_SHW_RAW:
2555	case PGM_STATE_REC_ROM_SHW_ZERO:
2556	case PGM_STATE_REC_ROM_PROT:
2557	{
2558	/*
2559	* Get the ID + page number and resolved that into a ROM page descriptor.
2560	*/
2561	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2562	iPage++;
2563	else
2564	{
2565	SSMR3GetU8(pSSM, &id);
2566	rc = SSMR3GetU32(pSSM, &iPage);
2567	if (RT_FAILURE(rc))
2568	return rc;
2569	}
2570	if ( !pRom
2571	\|\| pRom->idSavedState != id)
2572	{
2573	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2574	if (pRom->idSavedState == id)
2575	break;
2576	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2577	}
2578	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2579	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2580	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2581
2582	/*
2583	* Get and set the protection.
2584	*/
2585	uint8_t u8Prot;
2586	rc = SSMR3GetU8(pSSM, &u8Prot);
2587	if (RT_FAILURE(rc))
2588	return rc;
2589	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2590	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2591
2592	if (enmProt != pRomPage->enmProt)
2593	{
2594	AssertLogRelMsgReturn(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED,
2595	("GCPhys=%RGp enmProt=%d %s\n", GCPhys, enmProt, pRom->pszDesc),
2596	VERR_SSM_LOAD_CONFIG_MISMATCH);
2597	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2598	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2599	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2600	}
2601	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2602	break; /* done */
2603
2604	/*
2605	* Get the right page descriptor.
2606	*/
2607	PPGMPAGE pRealPage;
2608	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2609	{
2610	case PGM_STATE_REC_ROM_VIRGIN:
2611	if (!PGMROMPROT_IS_ROM(enmProt))
2612	pRealPage = &pRomPage->Virgin;
2613	else
2614	pRealPage = NULL;
2615	break;
2616
2617	case PGM_STATE_REC_ROM_SHW_RAW:
2618	case PGM_STATE_REC_ROM_SHW_ZERO:
2619	AssertLogRelMsgReturn(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED,
2620	("GCPhys=%RGp enmProt=%d %s\n", GCPhys, enmProt, pRom->pszDesc),
2621	VERR_SSM_LOAD_CONFIG_MISMATCH);
2622	if (PGMROMPROT_IS_ROM(enmProt))
2623	pRealPage = &pRomPage->Shadow;
2624	else
2625	pRealPage = NULL;
2626	break;
2627
2628	default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2629	}
2630	if (!pRealPage)
2631	{
2632	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2633	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2634	}
2635
2636	/*
2637	* Make it writable and map it (if necessary).
2638	*/
2639	void *pvDstPage = NULL;
2640	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2641	{
2642	case PGM_STATE_REC_ROM_SHW_ZERO:
2643	if (PGM_PAGE_IS_ZERO(pRealPage))
2644	break;
2645	/** @todo implement zero page replacing. */
2646	/* fall thru */
2647	case PGM_STATE_REC_ROM_VIRGIN:
2648	case PGM_STATE_REC_ROM_SHW_RAW:
2649	{
2650	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2651	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2652	break;
2653	}
2654	}
2655
2656	/*
2657	* Load the bits.
2658	*/
2659	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2660	{
2661	case PGM_STATE_REC_ROM_SHW_ZERO:
2662	if (pvDstPage)
2663	ASMMemZeroPage(pvDstPage);
2664	break;
2665
2666	case PGM_STATE_REC_ROM_VIRGIN:
2667	case PGM_STATE_REC_ROM_SHW_RAW:
2668	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2669	if (RT_FAILURE(rc))
2670	return rc;
2671	break;
2672	}
2673	GCPhys = NIL_RTGCPHYS;
2674	break;
2675	}
2676
2677	/*
2678	* Unknown type.
2679	*/
2680	default:
2681	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2682	}
2683	} /* forever */
2684	}
2685
2686
2687	/**
2688	* Worker for pgmR3Load.
2689	*
2690	* @returns VBox status code.
2691	*
2692	* @param pVM The VM handle.
2693	* @param pSSM The SSM handle.
2694	* @param uVersion The saved state version.
2695	*/
2696	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2697	{
2698	PPGM pPGM = &pVM->pgm.s;
2699	int rc;
2700	uint32_t u32Sep;
2701
2702	/*
2703	* Load basic data (required / unaffected by relocation).
2704	*/
2705	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2706	{
2707	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2708	AssertLogRelRCReturn(rc, rc);
2709
2710	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2711	{
2712	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2713	AssertLogRelRCReturn(rc, rc);
2714	}
2715	}
2716	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2717	{
2718	AssertRelease(pVM->cCpus == 1);
2719
2720	PGMOLD pgmOld;
2721	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2722	AssertLogRelRCReturn(rc, rc);
2723
2724	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2725	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2726	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2727
2728	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2729	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2730	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2731	}
2732	else
2733	{
2734	AssertRelease(pVM->cCpus == 1);
2735
2736	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2737	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2738	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2739
2740	uint32_t cbRamSizeIgnored;
2741	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2742	if (RT_FAILURE(rc))
2743	return rc;
2744	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2745
2746	uint32_t u32 = 0;
2747	SSMR3GetUInt(pSSM, &u32);
2748	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2749	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2750	RTUINT uGuestMode;
2751	SSMR3GetUInt(pSSM, &uGuestMode);
2752	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2753
2754	/* check separator. */
2755	SSMR3GetU32(pSSM, &u32Sep);
2756	if (RT_FAILURE(rc))
2757	return rc;
2758	if (u32Sep != (uint32_t)~0)
2759	{
2760	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2761	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2762	}
2763	}
2764
2765	/*
2766	* The guest mappings.
2767	*/
2768	uint32_t i = 0;
2769	for (;; i++)
2770	{
2771	/* Check the seqence number / separator. */
2772	rc = SSMR3GetU32(pSSM, &u32Sep);
2773	if (RT_FAILURE(rc))
2774	return rc;
2775	if (u32Sep == ~0U)
2776	break;
2777	if (u32Sep != i)
2778	{
2779	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2780	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2781	}
2782
2783	/* get the mapping details. */
2784	char szDesc[256];
2785	szDesc[0] = '\0';
2786	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2787	if (RT_FAILURE(rc))
2788	return rc;
2789	RTGCPTR GCPtr;
2790	SSMR3GetGCPtr(pSSM, &GCPtr);
2791	RTGCPTR cPTs;
2792	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2793	if (RT_FAILURE(rc))
2794	return rc;
2795
2796	/* find matching range. */
2797	PPGMMAPPING pMapping;
2798	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2799	if ( pMapping->cPTs == cPTs
2800	&& !strcmp(pMapping->pszDesc, szDesc))
2801	break;
2802	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2803	cPTs, szDesc, GCPtr),
2804	VERR_SSM_LOAD_CONFIG_MISMATCH);
2805
2806	/* relocate it. */
2807	if (pMapping->GCPtr != GCPtr)
2808	{
2809	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2810	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2811	}
2812	else
2813	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2814	}
2815
2816	/*
2817	* Load the RAM contents.
2818	*/
2819	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2820	{
2821	if (!pVM->pgm.s.LiveSave.fActive)
2822	{
2823	rc = pgmR3LoadRomRanges(pVM, pSSM);
2824	if (RT_FAILURE(rc))
2825	return rc;
2826	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2827	if (RT_FAILURE(rc))
2828	return rc;
2829	}
2830
2831	return pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2832	}
2833	return pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2834	}
2835
2836
2837	/**
2838	* Execute state load operation.
2839	*
2840	* @returns VBox status code.
2841	* @param pVM VM Handle.
2842	* @param pSSM SSM operation handle.
2843	* @param uVersion Data layout version.
2844	* @param uPass The data pass.
2845	*/
2846	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2847	{
2848	int rc;
2849	PPGM pPGM = &pVM->pgm.s;
2850
2851	/*
2852	* Validate version.
2853	*/
2854	if ( ( uPass != SSM_PASS_FINAL
2855	&& uVersion != PGM_SAVED_STATE_VERSION)
2856	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
2857	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
2858	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
2859	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
2860	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2861	)
2862	{
2863	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
2864	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2865	}
2866
2867	/*
2868	* Do the loading while owning the lock because a bunch of the functions
2869	* we're using requires this.
2870	*/
2871	if (uPass != SSM_PASS_FINAL)
2872	{
2873	pgmLock(pVM);
2874	if (uPass != 0)
2875	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2876	else
2877	{
2878	pVM->pgm.s.LiveSave.fActive = true;
2879	rc = pgmR3LoadRomRanges(pVM, pSSM);
2880	if (RT_SUCCESS(rc))
2881	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2882	if (RT_SUCCESS(rc))
2883	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2884	}
2885	pgmUnlock(pVM);
2886	}
2887	else
2888	{
2889	pgmLock(pVM);
2890	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
2891	pVM->pgm.s.LiveSave.fActive = false;
2892	pgmUnlock(pVM);
2893	if (RT_SUCCESS(rc))
2894	{
2895	/*
2896	* We require a full resync now.
2897	*/
2898	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2899	{
2900	PVMCPU pVCpu = &pVM->aCpus[i];
2901	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2902	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2903
2904	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2905	}
2906
2907	pgmR3HandlerPhysicalUpdateAll(pVM);
2908
2909	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2910	{
2911	PVMCPU pVCpu = &pVM->aCpus[i];
2912
2913	/*
2914	* Change the paging mode.
2915	*/
2916	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
2917
2918	/* Restore pVM->pgm.s.GCPhysCR3. */
2919	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2920	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
2921	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
2922	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2923	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
2924	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2925	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2926	else
2927	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2928	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2929	}
2930	}
2931	}
2932
2933	return rc;
2934	}
2935
2936
2937	/**
2938	* Registers the saved state callbacks with SSM.
2939	*
2940	* @returns VBox status code.
2941	* @param pVM Pointer to VM structure.
2942	* @param cbRam The RAM size.
2943	*/
2944	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
2945	{
2946	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
2947	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
2948	NULL, pgmR3SaveExec, pgmR3SaveDone,
2949	pgmR3LoadPrep, pgmR3Load, NULL);
2950	}
2951

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source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 23539

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