PGMSavedState.cpp@ 23544

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1	/* $Id: PGMSavedState.cpp 23544 2009-10-04 21:24:43Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/pgm.h>
28	#include <VBox/stam.h>
29	#include <VBox/ssm.h>
30	#include <VBox/pdm.h>
31	#include "PGMInternal.h"
32	#include <VBox/vm.h>
33
34	#include <VBox/param.h>
35	#include <VBox/err.h>
36
37	#include <iprt/asm.h>
38	#include <iprt/assert.h>
39	#include <iprt/crc32.h>
40	#include <iprt/mem.h>
41	#include <iprt/sha.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44
45
46	/*******************************************************************************
47	* Defined Constants And Macros *
48	*******************************************************************************/
49	/** Saved state data unit version. */
50	#ifdef VBOX_WITH_LIVE_MIGRATION
51	# define PGM_SAVED_STATE_VERSION 10
52	#else
53	# define PGM_SAVED_STATE_VERSION 9
54	#endif
55	/** Saved state data unit version for 3.0. (pre live migration) */
56	#define PGM_SAVED_STATE_VERSION_3_0_0 9
57	/** Saved state data unit version for 2.2.2 and later. */
58	#define PGM_SAVED_STATE_VERSION_2_2_2 8
59	/** Saved state data unit version for 2.2.0. */
60	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
61	/** Saved state data unit version. */
62	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
63
64
65	/** @name Sparse state record types
66	* @{ */
67	/** Zero page. No data. */
68	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
69	/** Raw page. */
70	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
71	/** Raw MMIO2 page. */
72	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
73	/** Zero MMIO2 page. */
74	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
75	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
76	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
77	/** Raw shadowed ROM page. The protection (8-bit) preceeds the raw bits. */
78	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
79	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
80	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
81	/** ROM protection (8-bit). */
82	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
83	/** The last record type. */
84	#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
85	/** End marker. */
86	#define PGM_STATE_REC_END UINT8_C(0xff)
87	/** Flag indicating that the data is preceeded by the page address.
88	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
89	* range ID and a 32-bit page index.
90	*/
91	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
92	/** @} */
93
94	/** The CRC-32 for a zero page. */
95	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
96	/** The CRC-32 for a zero half page. */
97	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
98
99
100	/*******************************************************************************
101	* Structures and Typedefs *
102	*******************************************************************************/
103	/** For loading old saved states. (pre-smp) */
104	typedef struct
105	{
106	/** If set no conflict checks are required. (boolean) */
107	bool fMappingsFixed;
108	/** Size of fixed mapping */
109	uint32_t cbMappingFixed;
110	/** Base address (GC) of fixed mapping */
111	RTGCPTR GCPtrMappingFixed;
112	/** A20 gate mask.
113	* Our current approach to A20 emulation is to let REM do it and don't bother
114	* anywhere else. The interesting Guests will be operating with it enabled anyway.
115	* But whould need arrise, we'll subject physical addresses to this mask. */
116	RTGCPHYS GCPhysA20Mask;
117	/** A20 gate state - boolean! */
118	bool fA20Enabled;
119	/** The guest paging mode. */
120	PGMMODE enmGuestMode;
121	} PGMOLD;
122
123
124	/*******************************************************************************
125	* Global Variables *
126	*******************************************************************************/
127	/** PGM fields to save/load. */
128	static const SSMFIELD s_aPGMFields[] =
129	{
130	SSMFIELD_ENTRY( PGM, fMappingsFixed),
131	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
132	SSMFIELD_ENTRY( PGM, cbMappingFixed),
133	SSMFIELD_ENTRY_TERM()
134	};
135
136	static const SSMFIELD s_aPGMCpuFields[] =
137	{
138	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
139	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
140	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
141	SSMFIELD_ENTRY_TERM()
142	};
143
144	static const SSMFIELD s_aPGMFields_Old[] =
145	{
146	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
147	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
148	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
149	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
150	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
151	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
152	SSMFIELD_ENTRY_TERM()
153	};
154
155
156	/**
157	* Find the ROM tracking structure for the given page.
158	*
159	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
160	* that it's a ROM page.
161	* @param pVM The VM handle.
162	* @param GCPhys The address of the ROM page.
163	*/
164	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
165	{
166	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
167	pRomRange;
168	pRomRange = pRomRange->CTX_SUFF(pNext))
169	{
170	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
171	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
172	return &pRomRange->aPages[off >> PAGE_SHIFT];
173	}
174	return NULL;
175	}
176
177
178	/**
179	* Prepares the ROM pages for a live save.
180	*
181	* @returns VBox status code.
182	* @param pVM The VM handle.
183	*/
184	static int pgmR3PrepRomPages(PVM pVM)
185	{
186	/*
187	* Initialize the live save tracking in the ROM page descriptors.
188	*/
189	pgmLock(pVM);
190	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
191	{
192	PPGMRAMRANGE pRamHint = NULL;;
193	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
194
195	for (uint32_t iPage = 0; iPage < cPages; iPage++)
196	{
197	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
198	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
199	pRom->aPages[iPage].LiveSave.fDirty = true;
200	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
201	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
202	{
203	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
204	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
205	else
206	{
207	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
208	PPGMPAGE pPage;
209	int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
210	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
211	if (RT_SUCCESS(rc))
212	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage);
213	else
214	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
215	}
216	}
217	}
218
219	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
220	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
221	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
222	}
223	pgmUnlock(pVM);
224
225	return VINF_SUCCESS;
226	}
227
228
229	/**
230	* Assigns IDs to the ROM ranges and saves them.
231	*
232	* @returns VBox status code.
233	* @param pVM The VM handle.
234	* @param pSSM Saved state handle.
235	*/
236	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
237	{
238	pgmLock(pVM);
239	uint8_t id = 1;
240	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
241	{
242	pRom->idSavedState = id;
243	SSMR3PutU8(pSSM, id);
244	SSMR3PutStrZ(pSSM, ""); /* device name */
245	SSMR3PutU32(pSSM, 0); /* device instance */
246	SSMR3PutU8(pSSM, 0); /* region */
247	SSMR3PutStrZ(pSSM, pRom->pszDesc);
248	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
249	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
250	if (RT_FAILURE(rc))
251	break;
252	}
253	pgmUnlock(pVM);
254	return SSMR3PutU8(pSSM, UINT8_MAX);
255	}
256
257
258	/**
259	* Loads the ROM range ID assignments.
260	*
261	* @returns VBox status code.
262	*
263	* @param pVM The VM handle.
264	* @param pSSM The saved state handle.
265	*/
266	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
267	{
268	Assert(PGMIsLockOwner(pVM));
269
270	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
271	pRom->idSavedState = UINT8_MAX;
272
273	for (;;)
274	{
275	/*
276	* Read the data.
277	*/
278	uint8_t id;
279	int rc = SSMR3GetU8(pSSM, &id);
280	if (RT_FAILURE(rc))
281	return rc;
282	if (id == UINT8_MAX)
283	{
284	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
285	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX, ("%s\n", pRom->pszDesc));
286	return VINF_SUCCESS; /* the end */
287	}
288	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
289
290	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szDeviceName)];
291	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
292	AssertLogRelRCReturn(rc, rc);
293
294	uint32_t uInstance;
295	SSMR3GetU32(pSSM, &uInstance);
296	uint8_t iRegion;
297	SSMR3GetU8(pSSM, &iRegion);
298
299	char szDesc[64];
300	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
301	AssertLogRelRCReturn(rc, rc);
302
303	RTGCPHYS GCPhys;
304	SSMR3GetGCPhys(pSSM, &GCPhys);
305	RTGCPHYS cb;
306	rc = SSMR3GetGCPhys(pSSM, &cb);
307	if (RT_FAILURE(rc))
308	return rc;
309	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
310	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
311
312	/*
313	* Locate a matching ROM range.
314	*/
315	AssertLogRelMsgReturn( uInstance == 0
316	&& iRegion == 0
317	&& szDevName[0] == '\0',
318	("GCPhys=%RGp %s\n", GCPhys, szDesc),
319	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
320	PPGMROMRANGE pRom;
321	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
322	{
323	if ( pRom->idSavedState == UINT8_MAX
324	&& !strcmp(pRom->pszDesc, szDesc))
325	{
326	pRom->idSavedState = id;
327	break;
328	}
329	}
330	AssertLogRelMsgReturn(pRom, ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_LOAD_CONFIG_MISMATCH);
331	} /* forever */
332	}
333
334
335	/**
336	* Scan ROM pages.
337	*
338	* @param pVM The VM handle.
339	*/
340	static void pgmR3ScanRomPages(PVM pVM)
341	{
342	/*
343	* The shadow ROMs.
344	*/
345	pgmLock(pVM);
346	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
347	{
348	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
349	{
350	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
351	for (uint32_t iPage = 0; iPage < cPages; iPage++)
352	{
353	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
354	if (pRomPage->LiveSave.fWrittenTo)
355	{
356	pRomPage->LiveSave.fWrittenTo = false;
357	if (!pRomPage->LiveSave.fDirty)
358	{
359	pRomPage->LiveSave.fDirty = true;
360	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
361	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
362	}
363	pRomPage->LiveSave.fDirtiedRecently = true;
364	}
365	else
366	pRomPage->LiveSave.fDirtiedRecently = false;
367	}
368	}
369	}
370	pgmUnlock(pVM);
371	}
372
373
374	/**
375	* Takes care of the virgin ROM pages in the first pass.
376	*
377	* This is an attempt at simplifying the handling of ROM pages a little bit.
378	* This ASSUMES that no new ROM ranges will be added and that they won't be
379	* relinked in any way.
380	*
381	* @param pVM The VM handle.
382	* @param pSSM The SSM handle.
383	* @param fLiveSave Whether we're in a live save or not.
384	*/
385	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
386	{
387	pgmLock(pVM);
388	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
389	{
390	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
391	for (uint32_t iPage = 0; iPage < cPages; iPage++)
392	{
393	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
394	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
395
396	/* Get the virgin page descriptor. */
397	PPGMPAGE pPage;
398	if (PGMROMPROT_IS_ROM(enmProt))
399	pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
400	else
401	pPage = &pRom->aPages[iPage].Virgin;
402
403	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
404	int rc = VINF_SUCCESS;
405	char abPage[PAGE_SIZE];
406	if (!PGM_PAGE_IS_ZERO(pPage))
407	{
408	void const *pvPage;
409	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
410	if (RT_SUCCESS(rc))
411	memcpy(abPage, pvPage, PAGE_SIZE);
412	}
413	else
414	ASMMemZeroPage(abPage);
415	pgmUnlock(pVM);
416	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
417
418	/* Save it. */
419	if (iPage > 0)
420	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
421	else
422	{
423	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
424	SSMR3PutU8(pSSM, pRom->idSavedState);
425	SSMR3PutU32(pSSM, iPage);
426	}
427	SSMR3PutU8(pSSM, (uint8_t)enmProt);
428	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
429	if (RT_FAILURE(rc))
430	return rc;
431
432	/* Update state. */
433	pgmLock(pVM);
434	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
435	if (fLiveSave)
436	{
437	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
438	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
439	}
440	}
441	}
442	pgmUnlock(pVM);
443	return VINF_SUCCESS;
444	}
445
446
447	/**
448	* Saves dirty pages in the shadowed ROM ranges.
449	*
450	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
451	*
452	* @returns VBox status code.
453	* @param pVM The VM handle.
454	* @param pSSM The SSM handle.
455	* @param fLiveSave Whether it's a live save or not.
456	* @param fFinalPass Whether this is the final pass or not.
457	*/
458	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
459	{
460	/*
461	* The Shadowed ROMs.
462	*
463	* ASSUMES that the ROM ranges are fixed.
464	* ASSUMES that all the ROM ranges are mapped.
465	*/
466	pgmLock(pVM);
467	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
468	{
469	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
470	{
471	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
472	uint32_t iPrevPage = cPages;
473	for (uint32_t iPage = 0; iPage < cPages; iPage++)
474	{
475	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
476	if ( !fLiveSave
477	\|\| ( pRomPage->LiveSave.fDirty
478	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
479	&& !pRomPage->LiveSave.fWrittenTo)
480	\|\| fFinalPass
481	)
482	)
483	)
484	{
485	uint8_t abPage[PAGE_SIZE];
486	PGMROMPROT enmProt = pRomPage->enmProt;
487	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
488	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
489	bool fZero = PGM_PAGE_IS_ZERO(pPage);
490	int rc = VINF_SUCCESS;
491	if (!fZero)
492	{
493	void const *pvPage;
494	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
495	if (RT_SUCCESS(rc))
496	memcpy(abPage, pvPage, PAGE_SIZE);
497	}
498	if (fLiveSave && RT_SUCCESS(rc))
499	{
500	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
501	pRomPage->LiveSave.fDirty = false;
502	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
503	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
504	}
505	pgmUnlock(pVM);
506	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
507
508	if (iPage - 1U == iPrevPage && iPage > 0)
509	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
510	else
511	{
512	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
513	SSMR3PutU8(pSSM, pRom->idSavedState);
514	SSMR3PutU32(pSSM, iPage);
515	}
516	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
517	if (!fZero)
518	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
519	if (RT_FAILURE(rc))
520	return rc;
521
522	pgmLock(pVM);
523	iPrevPage = iPage;
524	}
525	/*
526	* In the final pass, make sure the protection is in sync.
527	*/
528	else if ( fFinalPass
529	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
530	{
531	PGMROMPROT enmProt = pRomPage->enmProt;
532	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
533	pgmUnlock(pVM);
534
535	if (iPage - 1U == iPrevPage && iPage > 0)
536	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
537	else
538	{
539	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
540	SSMR3PutU8(pSSM, pRom->idSavedState);
541	SSMR3PutU32(pSSM, iPage);
542	}
543	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
544	if (RT_FAILURE(rc))
545	return rc;
546
547	pgmLock(pVM);
548	iPrevPage = iPage;
549	}
550	}
551	}
552	}
553	pgmUnlock(pVM);
554	return VINF_SUCCESS;
555	}
556
557
558	/**
559	* Cleans up ROM pages after a live save.
560	*
561	* @param pVM The VM handle.
562	*/
563	static void pgmR3DoneRomPages(PVM pVM)
564	{
565	NOREF(pVM);
566	}
567
568
569	/**
570	* Prepares the MMIO2 pages for a live save.
571	*
572	* @returns VBox status code.
573	* @param pVM The VM handle.
574	*/
575	static int pgmR3PrepMmio2Pages(PVM pVM)
576	{
577	/*
578	* Initialize the live save tracking in the MMIO2 ranges.
579	* ASSUME nothing changes here.
580	*/
581	pgmLock(pVM);
582	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
583	{
584	uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
585	pgmUnlock(pVM);
586
587	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
588	if (!paLSPages)
589	return VERR_NO_MEMORY;
590	for (uint32_t iPage = 0; iPage < cPages; iPage++)
591	{
592	/* Initialize it as a dirty zero page. */
593	paLSPages[iPage].fDirty = true;
594	paLSPages[iPage].cUnchangedScans = 0;
595	paLSPages[iPage].fZero = true;
596	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
597	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
598	}
599
600	pgmLock(pVM);
601	pMmio2->paLSPages = paLSPages;
602	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
603	}
604	pgmUnlock(pVM);
605	return VINF_SUCCESS;
606	}
607
608
609	/**
610	* Assigns IDs to the MMIO2 ranges and saves them.
611	*
612	* @returns VBox status code.
613	* @param pVM The VM handle.
614	* @param pSSM Saved state handle.
615	*/
616	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
617	{
618	pgmLock(pVM);
619	uint8_t id = 1;
620	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
621	{
622	pMmio2->idSavedState = id;
623	SSMR3PutU8(pSSM, id);
624	SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pDevReg->szDeviceName);
625	SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
626	SSMR3PutU8(pSSM, pMmio2->iRegion);
627	SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
628	int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
629	if (RT_FAILURE(rc))
630	break;
631	}
632	pgmUnlock(pVM);
633	return SSMR3PutU8(pSSM, UINT8_MAX);
634	}
635
636
637	/**
638	* Loads the MMIO2 range ID assignments.
639	*
640	* @returns VBox status code.
641	*
642	* @param pVM The VM handle.
643	* @param pSSM The saved state handle.
644	*/
645	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
646	{
647	Assert(PGMIsLockOwner(pVM));
648
649	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
650	pMmio2->idSavedState = UINT8_MAX;
651
652	for (;;)
653	{
654	/*
655	* Read the data.
656	*/
657	uint8_t id;
658	int rc = SSMR3GetU8(pSSM, &id);
659	if (RT_FAILURE(rc))
660	return rc;
661	if (id == UINT8_MAX)
662	{
663	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
664	AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
665	return VINF_SUCCESS; /* the end */
666	}
667	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
668
669	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szDeviceName)];
670	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
671	AssertLogRelRCReturn(rc, rc);
672
673	uint32_t uInstance;
674	SSMR3GetU32(pSSM, &uInstance);
675	uint8_t iRegion;
676	SSMR3GetU8(pSSM, &iRegion);
677
678	char szDesc[64];
679	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
680	AssertLogRelRCReturn(rc, rc);
681
682	RTGCPHYS cb;
683	rc = SSMR3GetGCPhys(pSSM, &cb);
684	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
685
686	/*
687	* Locate a matching MMIO2 range.
688	*/
689	PPGMMMIO2RANGE pMmio2;
690	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
691	{
692	if ( pMmio2->idSavedState == UINT8_MAX
693	&& pMmio2->iRegion == iRegion
694	&& pMmio2->pDevInsR3->iInstance == uInstance
695	&& !strcmp(pMmio2->pDevInsR3->pDevReg->szDeviceName, szDevName))
696	{
697	pMmio2->idSavedState = id;
698	break;
699	}
700	}
701	AssertLogRelMsgReturn(pMmio2, ("%s/%u/%u: %s\n", szDevName, uInstance, iRegion, szDesc), VERR_SSM_LOAD_CONFIG_MISMATCH);
702	} /* forever */
703	}
704
705
706	/**
707	* Scans one MMIO2 page.
708	*
709	* @returns True if changed, false if unchanged.
710	*
711	* @param pVM The VM handle
712	* @param pbPage The page bits.
713	* @param pLSPage The live save tracking structure for the page.
714	*
715	*/
716	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
717	{
718	/*
719	* Special handling of zero pages.
720	*/
721	bool const fZero = pLSPage->fZero;
722	if (fZero)
723	{
724	if (ASMMemIsZeroPage(pbPage))
725	{
726	/* Not modified. */
727	if (pLSPage->fDirty)
728	pLSPage->cUnchangedScans++;
729	return false;
730	}
731
732	pLSPage->fZero = false;
733	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
734	}
735	else
736	{
737	/*
738	* CRC the first half, if it doesn't match the page is dirty and
739	* we won't check the 2nd half (we'll do that next time).
740	*/
741	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
742	if (u32CrcH1 == pLSPage->u32CrcH1)
743	{
744	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
745	if (u32CrcH2 == pLSPage->u32CrcH2)
746	{
747	/* Probably not modified. */
748	if (pLSPage->fDirty)
749	pLSPage->cUnchangedScans++;
750	return false;
751	}
752
753	pLSPage->u32CrcH2 = u32CrcH2;
754	}
755	else
756	{
757	pLSPage->u32CrcH1 = u32CrcH1;
758	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
759	&& ASMMemIsZeroPage(pbPage))
760	{
761	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
762	pLSPage->fZero = true;
763	}
764	}
765	}
766
767	/* dirty page path */
768	pLSPage->cUnchangedScans = 0;
769	if (!pLSPage->fDirty)
770	{
771	pLSPage->fDirty = true;
772	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
773	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
774	if (fZero)
775	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
776	}
777	return true;
778	}
779
780
781	/**
782	* Scan for MMIO2 page modifications.
783	*
784	* @param pVM The VM handle.
785	* @param uPass The pass number.
786	*/
787	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
788	{
789	/*
790	* Since this is a bit expensive we lower the scan rate after a little while.
791	*/
792	if ( ( (uPass & 3) != 0
793	&& uPass > 10)
794	\|\| uPass == SSM_PASS_FINAL)
795	return;
796
797	pgmLock(pVM); /* paranoia */
798	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
799	{
800	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
801	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
802	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
803	pgmUnlock(pVM);
804
805	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
806	{
807	uint8_t const pbPage = (uint8_t const )pMmio2->pvR3 + iPage * PAGE_SIZE;
808	pgmR3ScanMmio2Page(pVM,pbPage, &paLSPages[iPage]);
809	}
810
811	pgmLock(pVM);
812	}
813	pgmUnlock(pVM);
814
815	}
816
817
818	/**
819	* Save quiescent MMIO2 pages.
820	*
821	* @returns VBox status code.
822	* @param pVM The VM handle.
823	* @param pSSM The SSM handle.
824	* @param fLiveSave Whether it's a live save or not.
825	* @param uPass The pass number.
826	*/
827	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
828	{
829	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
830	* device that we wish to know about changes.) */
831
832	int rc = VINF_SUCCESS;
833	if (uPass == SSM_PASS_FINAL)
834	{
835	/*
836	* The mop up round.
837	*/
838	pgmLock(pVM);
839	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
840	pMmio2 && RT_SUCCESS(rc);
841	pMmio2 = pMmio2->pNextR3)
842	{
843	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
844	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
845	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
846	uint32_t iPageLast = cPages;
847	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
848	{
849	uint8_t u8Type;
850	if (!fLiveSave)
851	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
852	else
853	{
854	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
855	if ( !paLSPages[iPage].fDirty
856	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
857	{
858	if (paLSPages[iPage].fZero)
859	continue;
860
861	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
862	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
863	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
864	continue;
865	}
866	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
867	}
868
869	if (iPage != 0 && iPage == iPageLast + 1)
870	rc = SSMR3PutU8(pSSM, u8Type);
871	else
872	{
873	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
874	SSMR3PutU8(pSSM, pMmio2->idSavedState);
875	rc = SSMR3PutU32(pSSM, iPage);
876	}
877	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
878	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
879	if (RT_FAILURE(rc))
880	break;
881	iPageLast = iPage;
882	}
883	}
884	pgmUnlock(pVM);
885	}
886	/*
887	* Reduce the rate after a little while since the current MMIO2 approach is
888	* a bit expensive.
889	* We position it two passes after the scan pass to avoid saving busy pages.
890	*/
891	else if ( uPass <= 10
892	\|\| (uPass & 3) == 2)
893	{
894	pgmLock(pVM);
895	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
896	pMmio2 && RT_SUCCESS(rc);
897	pMmio2 = pMmio2->pNextR3)
898	{
899	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
900	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
901	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
902	uint32_t iPageLast = cPages;
903	pgmUnlock(pVM);
904
905	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
906	{
907	/* Skip clean pages and pages which hasn't quiesced. */
908	if (!paLSPages[iPage].fDirty)
909	continue;
910	if (paLSPages[iPage].cUnchangedScans < 3)
911	continue;
912	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
913	continue;
914
915	/* Save it. */
916	bool const fZero = paLSPages[iPage].fZero;
917	uint8_t abPage[PAGE_SIZE];
918	if (!fZero)
919	{
920	memcpy(abPage, pbPage, PAGE_SIZE);
921	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
922	}
923
924	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
925	if (iPage != 0 && iPage == iPageLast + 1)
926	rc = SSMR3PutU8(pSSM, u8Type);
927	else
928	{
929	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
930	SSMR3PutU8(pSSM, pMmio2->idSavedState);
931	rc = SSMR3PutU32(pSSM, iPage);
932	}
933	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
934	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
935	if (RT_FAILURE(rc))
936	break;
937
938	/* Housekeeping. */
939	paLSPages[iPage].fDirty = false;
940	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
941	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
942	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
943	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
944	iPageLast = iPage;
945	}
946
947	pgmLock(pVM);
948	}
949	pgmUnlock(pVM);
950	}
951
952	return rc;
953	}
954
955
956	/**
957	* Cleans up MMIO2 pages after a live save.
958	*
959	* @param pVM The VM handle.
960	*/
961	static void pgmR3DoneMmio2Pages(PVM pVM)
962	{
963	/*
964	* Free the tracking structures for the MMIO2 pages.
965	* We do the freeing outside the lock in case the VM is running.
966	*/
967	pgmLock(pVM);
968	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
969	{
970	void *pvMmio2ToFree = pMmio2->paLSPages;
971	if (pvMmio2ToFree)
972	{
973	pMmio2->paLSPages = NULL;
974	pgmUnlock(pVM);
975	MMR3HeapFree(pvMmio2ToFree);
976	pgmLock(pVM);
977	}
978	}
979	pgmUnlock(pVM);
980	}
981
982
983	/**
984	* Prepares the RAM pages for a live save.
985	*
986	* @returns VBox status code.
987	* @param pVM The VM handle.
988	*/
989	static int pgmR3PrepRamPages(PVM pVM)
990	{
991
992	/*
993	* Try allocating tracking structures for the ram ranges.
994	*
995	* To avoid lock contention, we leave the lock every time we're allocating
996	* a new array. This means we'll have to ditch the allocation and start
997	* all over again if the RAM range list changes in-between.
998	*
999	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1000	* for cleaning up.
1001	*/
1002	PPGMRAMRANGE pCur;
1003	pgmLock(pVM);
1004	do
1005	{
1006	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1007	{
1008	if ( !pCur->paLSPages
1009	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1010	{
1011	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1012	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1013	pgmUnlock(pVM);
1014	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1015	if (!paLSPages)
1016	return VERR_NO_MEMORY;
1017	pgmLock(pVM);
1018	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1019	{
1020	pgmUnlock(pVM);
1021	MMR3HeapFree(paLSPages);
1022	pgmLock(pVM);
1023	break; /* try again */
1024	}
1025	pCur->paLSPages = paLSPages;
1026
1027	/*
1028	* Initialize the array.
1029	*/
1030	uint32_t iPage = cPages;
1031	while (iPage-- > 0)
1032	{
1033	/** @todo yield critsect! (after moving this away from EMT0) */
1034	PCPGMPAGE pPage = &pCur->aPages[iPage];
1035	paLSPages[iPage].cDirtied = 0;
1036	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1037	paLSPages[iPage].fWriteMonitored = 0;
1038	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1039	paLSPages[iPage].u2Reserved = 0;
1040	switch (PGM_PAGE_GET_TYPE(pPage))
1041	{
1042	case PGMPAGETYPE_RAM:
1043	if (PGM_PAGE_IS_ZERO(pPage))
1044	{
1045	paLSPages[iPage].fZero = 1;
1046	paLSPages[iPage].fShared = 0;
1047	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1048	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1049	#endif
1050	}
1051	else if (PGM_PAGE_IS_SHARED(pPage))
1052	{
1053	paLSPages[iPage].fZero = 0;
1054	paLSPages[iPage].fShared = 1;
1055	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1056	paLSPages[iPage].u32Crc = UINT32_MAX;
1057	#endif
1058	}
1059	else
1060	{
1061	paLSPages[iPage].fZero = 0;
1062	paLSPages[iPage].fShared = 0;
1063	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1064	paLSPages[iPage].u32Crc = UINT32_MAX;
1065	#endif
1066	}
1067	paLSPages[iPage].fIgnore = 0;
1068	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1069	break;
1070
1071	case PGMPAGETYPE_ROM_SHADOW:
1072	case PGMPAGETYPE_ROM:
1073	{
1074	paLSPages[iPage].fZero = 0;
1075	paLSPages[iPage].fShared = 0;
1076	paLSPages[iPage].fDirty = 0;
1077	paLSPages[iPage].fIgnore = 1;
1078	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1079	paLSPages[iPage].u32Crc = UINT32_MAX;
1080	#endif
1081	pVM->pgm.s.LiveSave.cIgnoredPages++;
1082	break;
1083	}
1084
1085	default:
1086	AssertMsgFailed(("%R[pgmpage]", pPage));
1087	case PGMPAGETYPE_MMIO2:
1088	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1089	paLSPages[iPage].fZero = 0;
1090	paLSPages[iPage].fShared = 0;
1091	paLSPages[iPage].fDirty = 0;
1092	paLSPages[iPage].fIgnore = 1;
1093	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1094	paLSPages[iPage].u32Crc = UINT32_MAX;
1095	#endif
1096	pVM->pgm.s.LiveSave.cIgnoredPages++;
1097	break;
1098
1099	case PGMPAGETYPE_MMIO:
1100	paLSPages[iPage].fZero = 0;
1101	paLSPages[iPage].fShared = 0;
1102	paLSPages[iPage].fDirty = 0;
1103	paLSPages[iPage].fIgnore = 1;
1104	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1105	paLSPages[iPage].u32Crc = UINT32_MAX;
1106	#endif
1107	pVM->pgm.s.LiveSave.cIgnoredPages++;
1108	break;
1109	}
1110	}
1111	}
1112	}
1113	} while (pCur);
1114	pgmUnlock(pVM);
1115
1116	return VINF_SUCCESS;
1117	}
1118
1119	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1120
1121	/**
1122	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1123	* info with it.
1124	*
1125	* @param pVM The VM handle.
1126	* @param pCur The current RAM range.
1127	* @param paLSPages The current array of live save page tracking
1128	* structures.
1129	* @param iPage The page index.
1130	*/
1131	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1132	{
1133	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1134	void const *pvPage;
1135	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1136	if (RT_SUCCESS(rc))
1137	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1138	else
1139	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1140	}
1141
1142
1143	/**
1144	* Verifies the CRC-32 for a page given it's raw bits.
1145	*
1146	* @param pvPage The page bits.
1147	* @param pCur The current RAM range.
1148	* @param paLSPages The current array of live save page tracking
1149	* structures.
1150	* @param iPage The page index.
1151	*/
1152	static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1153	{
1154	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1155	{
1156	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1157	Assert(!PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) \|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1158	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1159	("%08x != %08x for %RGp %R[pgmpage]\n", paLSPages[iPage].u32Crc, u32Crc,
1160	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1161	}
1162	}
1163
1164
1165	/**
1166	* Verfies the CRC-32 for a RAM page.
1167	*
1168	* @param pVM The VM handle.
1169	* @param pCur The current RAM range.
1170	* @param paLSPages The current array of live save page tracking
1171	* structures.
1172	* @param iPage The page index.
1173	*/
1174	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1175	{
1176	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1177	{
1178	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1179	void const *pvPage;
1180	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1181	if (RT_SUCCESS(rc))
1182	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage);
1183	}
1184	}
1185
1186	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1187
1188	/**
1189	* Scan for RAM page modifications and reprotect them.
1190	*
1191	* @param pVM The VM handle.
1192	* @param fFinalPass Whether this is the final pass or not.
1193	*/
1194	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1195	{
1196	/*
1197	* The RAM.
1198	*/
1199	RTGCPHYS GCPhysCur = 0;
1200	PPGMRAMRANGE pCur;
1201	pgmLock(pVM);
1202	do
1203	{
1204	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1205	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1206	{
1207	if ( pCur->GCPhysLast > GCPhysCur
1208	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1209	{
1210	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1211	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1212	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1213	GCPhysCur = 0;
1214	for (; iPage < cPages; iPage++)
1215	{
1216	/* Do yield first. */
1217	if ( !fFinalPass
1218	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1219	&& (iPage & 0x7ff) == 0x100
1220	#endif
1221	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1222	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1223	{
1224	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1225	break; /* restart */
1226	}
1227
1228	/* Skip already ignored pages. */
1229	if (paLSPages[iPage].fIgnore)
1230	continue;
1231
1232	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1233	{
1234	/*
1235	* A RAM page.
1236	*/
1237	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1238	{
1239	case PGM_PAGE_STATE_ALLOCATED:
1240	/** @todo Optimize this: Don't always re-enable write
1241	* monitoring if the page is known to be very busy. */
1242	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1243	{
1244	Assert(paLSPages[iPage].fWriteMonitored);
1245	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1246	Assert(pVM->pgm.s.cWrittenToPages > 0);
1247	pVM->pgm.s.cWrittenToPages--;
1248	}
1249	else
1250	{
1251	Assert(!paLSPages[iPage].fWriteMonitored);
1252	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1253	}
1254
1255	if (!paLSPages[iPage].fDirty)
1256	{
1257	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1258	if (paLSPages[iPage].fZero)
1259	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1260	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1261	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1262	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1263	}
1264
1265	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1266	pVM->pgm.s.cMonitoredPages++;
1267	paLSPages[iPage].fWriteMonitored = 1;
1268	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1269	paLSPages[iPage].fDirty = 1;
1270	paLSPages[iPage].fZero = 0;
1271	paLSPages[iPage].fShared = 0;
1272	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1273	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1274	#endif
1275	break;
1276
1277	case PGM_PAGE_STATE_WRITE_MONITORED:
1278	Assert(paLSPages[iPage].fWriteMonitored);
1279	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1280	{
1281	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1282	if (paLSPages[iPage].fWriteMonitoredJustNow)
1283	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1284	else
1285	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1286	#endif
1287	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1288	}
1289	else
1290	{
1291	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1292	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1293	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1294	#endif
1295	if (!paLSPages[iPage].fDirty)
1296	{
1297	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1298	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1299	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1300	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1301	}
1302	}
1303	break;
1304
1305	case PGM_PAGE_STATE_ZERO:
1306	if (!paLSPages[iPage].fZero)
1307	{
1308	if (!paLSPages[iPage].fDirty)
1309	{
1310	paLSPages[iPage].fDirty = 1;
1311	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1312	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1313	}
1314	paLSPages[iPage].fZero = 1;
1315	paLSPages[iPage].fShared = 0;
1316	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1317	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1318	#endif
1319	}
1320	break;
1321
1322	case PGM_PAGE_STATE_SHARED:
1323	if (!paLSPages[iPage].fShared)
1324	{
1325	if (!paLSPages[iPage].fDirty)
1326	{
1327	paLSPages[iPage].fDirty = 1;
1328	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1329	if (paLSPages[iPage].fZero)
1330	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1331	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1332	}
1333	paLSPages[iPage].fZero = 0;
1334	paLSPages[iPage].fShared = 1;
1335	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1336	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1337	#endif
1338	}
1339	break;
1340	}
1341	}
1342	else
1343	{
1344	/*
1345	* All other types => Ignore the page.
1346	*/
1347	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1348	paLSPages[iPage].fIgnore = 1;
1349	if (paLSPages[iPage].fWriteMonitored)
1350	{
1351	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1352	* pages! */
1353	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1354	{
1355	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1356	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1357	Assert(pVM->pgm.s.cMonitoredPages > 0);
1358	pVM->pgm.s.cMonitoredPages--;
1359	}
1360	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1361	{
1362	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1363	Assert(pVM->pgm.s.cWrittenToPages > 0);
1364	pVM->pgm.s.cWrittenToPages--;
1365	}
1366	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1367	}
1368
1369	/** @todo the counting doesn't quite work out here. fix later? */
1370	if (paLSPages[iPage].fDirty)
1371	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1372	else
1373	{
1374	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1375	if (paLSPages[iPage].fZero)
1376	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1377	}
1378	pVM->pgm.s.LiveSave.cIgnoredPages++;
1379	}
1380	} /* for each page in range */
1381
1382	if (GCPhysCur != 0)
1383	break; /* Yield + ramrange change */
1384	GCPhysCur = pCur->GCPhysLast;
1385	}
1386	} /* for each range */
1387	} while (pCur);
1388	pgmUnlock(pVM);
1389	}
1390
1391
1392	/**
1393	* Save quiescent RAM pages.
1394	*
1395	* @returns VBox status code.
1396	* @param pVM The VM handle.
1397	* @param pSSM The SSM handle.
1398	* @param fLiveSave Whether it's a live save or not.
1399	* @param uPass The pass number.
1400	*/
1401	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1402	{
1403	/*
1404	* The RAM.
1405	*/
1406	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1407	RTGCPHYS GCPhysCur = 0;
1408	PPGMRAMRANGE pCur;
1409	pgmLock(pVM);
1410	do
1411	{
1412	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1413	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1414	{
1415	if ( pCur->GCPhysLast > GCPhysCur
1416	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1417	{
1418	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1419	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1420	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1421	GCPhysCur = 0;
1422	for (; iPage < cPages; iPage++)
1423	{
1424	/* Do yield first. */
1425	if ( uPass != SSM_PASS_FINAL
1426	&& (iPage & 0x7ff) == 0x100
1427	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1428	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1429	{
1430	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1431	break; /* restart */
1432	}
1433
1434	/*
1435	* Only save pages that hasn't changed since last scan and are dirty.
1436	*/
1437	if ( uPass != SSM_PASS_FINAL
1438	&& paLSPages)
1439	{
1440	if (!paLSPages[iPage].fDirty)
1441	continue;
1442	if (paLSPages[iPage].fWriteMonitoredJustNow)
1443	continue;
1444	if (paLSPages[iPage].fIgnore)
1445	continue;
1446	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM) /* in case of recent ramppings */
1447	continue;
1448	if ( PGM_PAGE_GET_STATE(&pCur->aPages[iPage])
1449	!= ( paLSPages[iPage].fZero
1450	? PGM_PAGE_STATE_ZERO
1451	: paLSPages[iPage].fShared
1452	? PGM_PAGE_STATE_SHARED
1453	: PGM_PAGE_STATE_WRITE_MONITORED))
1454	continue;
1455	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1456	continue;
1457	}
1458	else
1459	{
1460	if ( paLSPages
1461	&& !paLSPages[iPage].fDirty
1462	&& !paLSPages[iPage].fIgnore)
1463	{
1464	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1465	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1466	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1467	#endif
1468	continue;
1469	}
1470	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1471	continue;
1472	}
1473
1474	/*
1475	* Do the saving outside the PGM critsect since SSM may block on I/O.
1476	*/
1477	int rc;
1478	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1479	bool fZero = PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]);
1480
1481	if (!fZero)
1482	{
1483	/*
1484	* Copy the page and then save it outside the lock (since any
1485	* SSM call may block).
1486	*/
1487	uint8_t abPage[PAGE_SIZE];
1488	void const *pvPage;
1489	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1490	if (RT_SUCCESS(rc))
1491	{
1492	memcpy(abPage, pvPage, PAGE_SIZE);
1493	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1494	if (paLSPages)
1495	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage);
1496	#endif
1497	}
1498	pgmUnlock(pVM);
1499	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1500
1501	if (GCPhys == GCPhysLast + PAGE_SIZE)
1502	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1503	else
1504	{
1505	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1506	SSMR3PutGCPhys(pSSM, GCPhys);
1507	}
1508	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1509	}
1510	else
1511	{
1512	/*
1513	* Dirty zero page.
1514	*/
1515	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1516	if (paLSPages)
1517	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1518	#endif
1519	pgmUnlock(pVM);
1520
1521	if (GCPhys == GCPhysLast + PAGE_SIZE)
1522	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1523	else
1524	{
1525	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1526	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1527	}
1528	}
1529	if (RT_FAILURE(rc))
1530	return rc;
1531
1532	pgmLock(pVM);
1533	GCPhysLast = GCPhys;
1534	if (paLSPages)
1535	{
1536	paLSPages[iPage].fDirty = 0;
1537	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1538	if (fZero)
1539	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1540	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1541	}
1542	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1543	{
1544	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1545	break; /* restart */
1546	}
1547
1548	} /* for each page in range */
1549
1550	if (GCPhysCur != 0)
1551	break; /* Yield + ramrange change */
1552	GCPhysCur = pCur->GCPhysLast;
1553	}
1554	} /* for each range */
1555	} while (pCur);
1556	pgmUnlock(pVM);
1557
1558	return VINF_SUCCESS;
1559	}
1560
1561
1562	/**
1563	* Cleans up RAM pages after a live save.
1564	*
1565	* @param pVM The VM handle.
1566	*/
1567	static void pgmR3DoneRamPages(PVM pVM)
1568	{
1569	/*
1570	* Free the tracking arrays and disable write monitoring.
1571	*
1572	* Play nice with the PGM lock in case we're called while the VM is still
1573	* running. This means we have to delay the freeing since we wish to use
1574	* paLSPages as an indicator of which RAM ranges which we need to scan for
1575	* write monitored pages.
1576	*/
1577	void *pvToFree = NULL;
1578	PPGMRAMRANGE pCur;
1579	uint32_t cMonitoredPages = 0;
1580	pgmLock(pVM);
1581	do
1582	{
1583	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1584	{
1585	if (pCur->paLSPages)
1586	{
1587	if (pvToFree)
1588	{
1589	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1590	pgmUnlock(pVM);
1591	MMR3HeapFree(pvToFree);
1592	pvToFree = NULL;
1593	pgmLock(pVM);
1594	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1595	break; /* start over again. */
1596	}
1597
1598	pvToFree = pCur->paLSPages;
1599	pCur->paLSPages = NULL;
1600
1601	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1602	while (iPage--)
1603	{
1604	PPGMPAGE pPage = &pCur->aPages[iPage];
1605	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1606	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1607	{
1608	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1609	cMonitoredPages++;
1610	}
1611	}
1612	}
1613	}
1614	} while (pCur);
1615
1616	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1617	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1618	pVM->pgm.s.cMonitoredPages = 0;
1619	else
1620	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1621
1622	pgmUnlock(pVM);
1623
1624	MMR3HeapFree(pvToFree);
1625	pvToFree = NULL;
1626	}
1627
1628
1629	/**
1630	* Execute a live save pass.
1631	*
1632	* @returns VBox status code.
1633	*
1634	* @param pVM The VM handle.
1635	* @param pSSM The SSM handle.
1636	*/
1637	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1638	{
1639	int rc;
1640
1641	/*
1642	* Save the MMIO2 and ROM range IDs in pass 0.
1643	*/
1644	if (uPass == 0)
1645	{
1646	rc = pgmR3SaveRomRanges(pVM, pSSM);
1647	if (RT_FAILURE(rc))
1648	return rc;
1649	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1650	if (RT_FAILURE(rc))
1651	return rc;
1652	}
1653
1654	/*
1655	* Do the scanning.
1656	*/
1657	pgmR3ScanRomPages(pVM);
1658	pgmR3ScanMmio2Pages(pVM, uPass);
1659	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1660	pgmR3PoolClearAll(pVM); /** @todo this could perhaps be optimized a bit. */
1661
1662	/*
1663	* Save the pages.
1664	*/
1665	if (uPass == 0)
1666	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1667	else
1668	rc = VINF_SUCCESS;
1669	if (RT_SUCCESS(rc))
1670	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1671	if (RT_SUCCESS(rc))
1672	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1673	if (RT_SUCCESS(rc))
1674	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1675	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1676
1677	return rc;
1678	}
1679
1680	//#include <iprt/stream.h>
1681
1682	/**
1683	* Votes on whether the live save phase is done or not.
1684	*
1685	* @returns VBox status code.
1686	*
1687	* @param pVM The VM handle.
1688	* @param pSSM The SSM handle.
1689	*/
1690	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM)
1691	{
1692	#if 0
1693	RTPrintf("# Rom[R/D/Z/M]=%03x/%03x/%03x/%03x Mmio2=%04x/%04x/%04x/%04x Ram=%06x/%06x/%06x/%06x Ignored=%03x\n",
1694	pVM->pgm.s.LiveSave.Rom.cReadyPages,
1695	pVM->pgm.s.LiveSave.Rom.cDirtyPages,
1696	pVM->pgm.s.LiveSave.Rom.cZeroPages,
1697	pVM->pgm.s.LiveSave.Rom.cMonitoredPages,
1698	pVM->pgm.s.LiveSave.Mmio2.cReadyPages,
1699	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages,
1700	pVM->pgm.s.LiveSave.Mmio2.cZeroPages,
1701	pVM->pgm.s.LiveSave.Mmio2.cMonitoredPages,
1702	pVM->pgm.s.LiveSave.Ram.cReadyPages,
1703	pVM->pgm.s.LiveSave.Ram.cDirtyPages,
1704	pVM->pgm.s.LiveSave.Ram.cZeroPages,
1705	pVM->pgm.s.LiveSave.Ram.cMonitoredPages,
1706	pVM->pgm.s.LiveSave.cIgnoredPages
1707	);
1708	static int s_iHack = 0;
1709	if ((++s_iHack % 42) == 0)
1710	return VINF_SUCCESS;
1711	RTThreadSleep(1000);
1712
1713	#else
1714	if ( pVM->pgm.s.LiveSave.Rom.cDirtyPages
1715	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1716	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1717	< 256) /* semi random numbers. */
1718	return VINF_SUCCESS;
1719	#endif
1720	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1721	}
1722
1723	#ifndef VBOX_WITH_LIVE_MIGRATION
1724
1725	/**
1726	* Save zero indicator + bits for the specified page.
1727	*
1728	* @returns VBox status code, errors are logged/asserted before returning.
1729	* @param pVM The VM handle.
1730	* @param pSSH The saved state handle.
1731	* @param pPage The page to save.
1732	* @param GCPhys The address of the page.
1733	* @param pRam The ram range (for error logging).
1734	*/
1735	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
1736	{
1737	int rc;
1738	if (PGM_PAGE_IS_ZERO(pPage))
1739	rc = SSMR3PutU8(pSSM, 0);
1740	else
1741	{
1742	void const *pvPage;
1743	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
1744	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
1745
1746	SSMR3PutU8(pSSM, 1);
1747	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
1748	}
1749	return rc;
1750	}
1751
1752
1753	/**
1754	* Save a shadowed ROM page.
1755	*
1756	* Format: Type, protection, and two pages with zero indicators.
1757	*
1758	* @returns VBox status code, errors are logged/asserted before returning.
1759	* @param pVM The VM handle.
1760	* @param pSSH The saved state handle.
1761	* @param pPage The page to save.
1762	* @param GCPhys The address of the page.
1763	* @param pRam The ram range (for error logging).
1764	*/
1765	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
1766	{
1767	/* Need to save both pages and the current state. */
1768	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
1769	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
1770
1771	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
1772	SSMR3PutU8(pSSM, pRomPage->enmProt);
1773
1774	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
1775	if (RT_SUCCESS(rc))
1776	{
1777	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
1778	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
1779	}
1780	return rc;
1781	}
1782
1783	#endif /* !VBOX_WITH_LIVE_MIGRATION */
1784
1785
1786	/**
1787	* Prepare for a live save operation.
1788	*
1789	* This will attempt to allocate and initialize the tracking structures. It
1790	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1791	* pgmR3SaveDone will do the cleanups.
1792	*
1793	* @returns VBox status code.
1794	*
1795	* @param pVM The VM handle.
1796	* @param pSSM The SSM handle.
1797	*/
1798	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1799	{
1800	/*
1801	* Indicate that we will be using the write monitoring.
1802	*/
1803	pgmLock(pVM);
1804	/** @todo find a way of mediating this when more users are added. */
1805	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1806	{
1807	pgmUnlock(pVM);
1808	AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1809	}
1810	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1811	pgmUnlock(pVM);
1812
1813	/*
1814	* Initialize the statistics.
1815	*/
1816	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1817	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1818	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1819	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1820	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1821	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1822	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1823	pVM->pgm.s.LiveSave.fActive = true;
1824
1825	/*
1826	* Per page type.
1827	*/
1828	int rc = pgmR3PrepRomPages(pVM);
1829	if (RT_SUCCESS(rc))
1830	rc = pgmR3PrepMmio2Pages(pVM);
1831	if (RT_SUCCESS(rc))
1832	rc = pgmR3PrepRamPages(pVM);
1833	return rc;
1834	}
1835
1836
1837	/**
1838	* Execute state save operation.
1839	*
1840	* @returns VBox status code.
1841	* @param pVM VM Handle.
1842	* @param pSSM SSM operation handle.
1843	*/
1844	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1845	{
1846	int rc;
1847	unsigned i;
1848	PPGM pPGM = &pVM->pgm.s;
1849
1850	/*
1851	* Lock PGM and set the no-more-writes indicator.
1852	*/
1853	pgmLock(pVM);
1854	pVM->pgm.s.fNoMorePhysWrites = true;
1855
1856	/*
1857	* Save basic data (required / unaffected by relocation).
1858	*/
1859	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
1860
1861	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1862	{
1863	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1864	SSMR3PutStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
1865	}
1866
1867	/*
1868	* The guest mappings.
1869	*/
1870	i = 0;
1871	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1872	{
1873	SSMR3PutU32( pSSM, i);
1874	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1875	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
1876	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1877	}
1878	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
1879
1880	#ifdef VBOX_WITH_LIVE_MIGRATION
1881	/*
1882	* Save the (remainder of the) memory.
1883	*/
1884	if (RT_SUCCESS(rc))
1885	{
1886	if (pVM->pgm.s.LiveSave.fActive)
1887	{
1888	pgmR3ScanRomPages(pVM);
1889	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
1890	pgmR3ScanRamPages(pVM, true /fFinalPass/);
1891
1892	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
1893	if (RT_SUCCESS(rc))
1894	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1895	if (RT_SUCCESS(rc))
1896	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1897	}
1898	else
1899	{
1900	rc = pgmR3SaveRomRanges(pVM, pSSM);
1901	if (RT_SUCCESS(rc))
1902	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1903	if (RT_SUCCESS(rc))
1904	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
1905	if (RT_SUCCESS(rc))
1906	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
1907	if (RT_SUCCESS(rc))
1908	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
1909	if (RT_SUCCESS(rc))
1910	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
1911	}
1912	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1913	}
1914
1915	#else /* !VBOX_WITH_LIVE_MIGRATION */
1916	/*
1917	* Ram ranges and the memory they describe.
1918	*/
1919	i = 0;
1920	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
1921	{
1922	/*
1923	* Save the ram range details.
1924	*/
1925	SSMR3PutU32(pSSM, i);
1926	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
1927	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
1928	SSMR3PutGCPhys(pSSM, pRam->cb);
1929	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
1930	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
1931
1932	/*
1933	* Iterate the pages, only two special case.
1934	*/
1935	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
1936	for (uint32_t iPage = 0; iPage < cPages; iPage++)
1937	{
1938	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1939	PPGMPAGE pPage = &pRam->aPages[iPage];
1940	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
1941
1942	if (uType == PGMPAGETYPE_ROM_SHADOW) /** @todo This isn't right, but it doesn't currently matter. */
1943	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
1944	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
1945	{
1946	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
1947	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
1948	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
1949	}
1950	else
1951	{
1952	SSMR3PutU8(pSSM, uType);
1953	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
1954	}
1955	if (RT_FAILURE(rc))
1956	break;
1957	}
1958	if (RT_FAILURE(rc))
1959	break;
1960	}
1961
1962	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
1963	#endif /* !VBOX_WITH_LIVE_MIGRATION */
1964
1965	pgmUnlock(pVM);
1966	return rc;
1967	}
1968
1969
1970	/**
1971	* Cleans up after an save state operation.
1972	*
1973	* @returns VBox status code.
1974	* @param pVM VM Handle.
1975	* @param pSSM SSM operation handle.
1976	*/
1977	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
1978	{
1979	/*
1980	* Do per page type cleanups first.
1981	*/
1982	if (pVM->pgm.s.LiveSave.fActive)
1983	{
1984	pgmR3DoneRomPages(pVM);
1985	pgmR3DoneMmio2Pages(pVM);
1986	pgmR3DoneRamPages(pVM);
1987	}
1988
1989	/*
1990	* Clear the live save indicator and disengage write monitoring.
1991	*/
1992	pgmLock(pVM);
1993	pVM->pgm.s.LiveSave.fActive = false;
1994	/** @todo this is blindly assuming that we're the only user of write
1995	* monitoring. Fix this when more users are added. */
1996	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
1997	pgmUnlock(pVM);
1998
1999	return VINF_SUCCESS;
2000	}
2001
2002
2003	/**
2004	* Prepare state load operation.
2005	*
2006	* @returns VBox status code.
2007	* @param pVM VM Handle.
2008	* @param pSSM SSM operation handle.
2009	*/
2010	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2011	{
2012	/*
2013	* Call the reset function to make sure all the memory is cleared.
2014	*/
2015	PGMR3Reset(pVM);
2016	pVM->pgm.s.LiveSave.fActive = false;
2017	NOREF(pSSM);
2018	return VINF_SUCCESS;
2019	}
2020
2021
2022	/**
2023	* Load an ignored page.
2024	*
2025	* @returns VBox status code.
2026	* @param pSSM The saved state handle.
2027	*/
2028	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2029	{
2030	uint8_t abPage[PAGE_SIZE];
2031	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2032	}
2033
2034
2035	/**
2036	* Loads a page without any bits in the saved state, i.e. making sure it's
2037	* really zero.
2038	*
2039	* @returns VBox status code.
2040	* @param pVM The VM handle.
2041	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2042	* state).
2043	* @param pPage The guest page tracking structure.
2044	* @param GCPhys The page address.
2045	* @param pRam The ram range (logging).
2046	*/
2047	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2048	{
2049	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2050	&& uType != PGMPAGETYPE_INVALID)
2051	return VERR_SSM_UNEXPECTED_DATA;
2052
2053	/* I think this should be sufficient. */
2054	if (!PGM_PAGE_IS_ZERO(pPage))
2055	return VERR_SSM_UNEXPECTED_DATA;
2056
2057	NOREF(pVM);
2058	NOREF(GCPhys);
2059	NOREF(pRam);
2060	return VINF_SUCCESS;
2061	}
2062
2063
2064	/**
2065	* Loads a page from the saved state.
2066	*
2067	* @returns VBox status code.
2068	* @param pVM The VM handle.
2069	* @param pSSM The SSM handle.
2070	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2071	* state).
2072	* @param pPage The guest page tracking structure.
2073	* @param GCPhys The page address.
2074	* @param pRam The ram range (logging).
2075	*/
2076	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2077	{
2078	/*
2079	* Match up the type, dealing with MMIO2 aliases (dropped).
2080	*/
2081	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2082	\|\| uType == PGMPAGETYPE_INVALID,
2083	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2084	VERR_SSM_UNEXPECTED_DATA);
2085
2086	/*
2087	* Load the page.
2088	*/
2089	void *pvPage;
2090	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2091	if (RT_SUCCESS(rc))
2092	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2093
2094	return rc;
2095	}
2096
2097
2098	/**
2099	* Loads a page (counter part to pgmR3SavePage).
2100	*
2101	* @returns VBox status code, fully bitched errors.
2102	* @param pVM The VM handle.
2103	* @param pSSM The SSM handle.
2104	* @param uType The page type.
2105	* @param pPage The page.
2106	* @param GCPhys The page address.
2107	* @param pRam The RAM range (for error messages).
2108	*/
2109	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2110	{
2111	uint8_t uState;
2112	int rc = SSMR3GetU8(pSSM, &uState);
2113	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2114	if (uState == 0 /* zero */)
2115	rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2116	else if (uState == 1)
2117	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2118	else
2119	rc = VERR_INTERNAL_ERROR;
2120	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2121	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2122	rc);
2123	return VINF_SUCCESS;
2124	}
2125
2126
2127	/**
2128	* Loads a shadowed ROM page.
2129	*
2130	* @returns VBox status code, errors are fully bitched.
2131	* @param pVM The VM handle.
2132	* @param pSSM The saved state handle.
2133	* @param pPage The page.
2134	* @param GCPhys The page address.
2135	* @param pRam The RAM range (for error messages).
2136	*/
2137	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2138	{
2139	/*
2140	* Load and set the protection first, then load the two pages, the first
2141	* one is the active the other is the passive.
2142	*/
2143	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2144	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2145
2146	uint8_t uProt;
2147	int rc = SSMR3GetU8(pSSM, &uProt);
2148	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2149	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2150	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2151	&& enmProt < PGMROMPROT_END,
2152	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2153	VERR_SSM_UNEXPECTED_DATA);
2154
2155	if (pRomPage->enmProt != enmProt)
2156	{
2157	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2158	AssertLogRelRCReturn(rc, rc);
2159	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2160	}
2161
2162	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2163	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2164	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2165	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2166
2167	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2168	* used down the line (will the 2nd page will be written to the first
2169	* one because of a false TLB hit since the TLB is using GCPhys and
2170	* doesn't check the HCPhys of the desired page). */
2171	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2172	if (RT_SUCCESS(rc))
2173	{
2174	pPageActive = pPage;
2175	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2176	}
2177	return rc;
2178	}
2179
2180	/**
2181	* Ram range flags and bits for older versions of the saved state.
2182	*
2183	* @returns VBox status code.
2184	*
2185	* @param pVM The VM handle
2186	* @param pSSM The SSM handle.
2187	* @param uVersion The saved state version.
2188	*/
2189	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2190	{
2191	PPGM pPGM = &pVM->pgm.s;
2192
2193	/*
2194	* Ram range flags and bits.
2195	*/
2196	uint32_t i = 0;
2197	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2198	{
2199	/* Check the seqence number / separator. */
2200	uint32_t u32Sep;
2201	int rc = SSMR3GetU32(pSSM, &u32Sep);
2202	if (RT_FAILURE(rc))
2203	return rc;
2204	if (u32Sep == ~0U)
2205	break;
2206	if (u32Sep != i)
2207	{
2208	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2209	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2210	}
2211	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2212
2213	/* Get the range details. */
2214	RTGCPHYS GCPhys;
2215	SSMR3GetGCPhys(pSSM, &GCPhys);
2216	RTGCPHYS GCPhysLast;
2217	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2218	RTGCPHYS cb;
2219	SSMR3GetGCPhys(pSSM, &cb);
2220	uint8_t fHaveBits;
2221	rc = SSMR3GetU8(pSSM, &fHaveBits);
2222	if (RT_FAILURE(rc))
2223	return rc;
2224	if (fHaveBits & ~1)
2225	{
2226	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2227	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2228	}
2229	size_t cchDesc = 0;
2230	char szDesc[256];
2231	szDesc[0] = '\0';
2232	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2233	{
2234	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2235	if (RT_FAILURE(rc))
2236	return rc;
2237	/* Since we've modified the description strings in r45878, only compare
2238	them if the saved state is more recent. */
2239	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2240	cchDesc = strlen(szDesc);
2241	}
2242
2243	/*
2244	* Match it up with the current range.
2245	*
2246	* Note there is a hack for dealing with the high BIOS mapping
2247	* in the old saved state format, this means we might not have
2248	* a 1:1 match on success.
2249	*/
2250	if ( ( GCPhys != pRam->GCPhys
2251	\|\| GCPhysLast != pRam->GCPhysLast
2252	\|\| cb != pRam->cb
2253	\|\| ( cchDesc
2254	&& strcmp(szDesc, pRam->pszDesc)) )
2255	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2256	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2257	\|\| GCPhys != UINT32_C(0xfff80000)
2258	\|\| GCPhysLast != UINT32_C(0xffffffff)
2259	\|\| pRam->GCPhysLast != GCPhysLast
2260	\|\| pRam->GCPhys < GCPhys
2261	\|\| !fHaveBits)
2262	)
2263	{
2264	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2265	"State : %RGp-%RGp %RGp bytes %s %s\n",
2266	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2267	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2268	/*
2269	* If we're loading a state for debugging purpose, don't make a fuss if
2270	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2271	*/
2272	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2273	\|\| GCPhys < 8 * _1M)
2274	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2275
2276	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2277	continue;
2278	}
2279
2280	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2281	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2282	{
2283	/*
2284	* Load the pages one by one.
2285	*/
2286	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2287	{
2288	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2289	PPGMPAGE pPage = &pRam->aPages[iPage];
2290	uint8_t uType;
2291	rc = SSMR3GetU8(pSSM, &uType);
2292	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2293	if (uType == PGMPAGETYPE_ROM_SHADOW)
2294	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2295	else
2296	rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2297	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2298	}
2299	}
2300	else
2301	{
2302	/*
2303	* Old format.
2304	*/
2305	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2306
2307	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2308	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2309	uint32_t fFlags = 0;
2310	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2311	{
2312	uint16_t u16Flags;
2313	rc = SSMR3GetU16(pSSM, &u16Flags);
2314	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2315	fFlags \|= u16Flags;
2316	}
2317
2318	/* Load the bits */
2319	if ( !fHaveBits
2320	&& GCPhysLast < UINT32_C(0xe0000000))
2321	{
2322	/*
2323	* Dynamic chunks.
2324	*/
2325	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2326	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2327	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2328	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2329
2330	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2331	{
2332	uint8_t fPresent;
2333	rc = SSMR3GetU8(pSSM, &fPresent);
2334	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2335	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2336	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2337	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2338
2339	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2340	{
2341	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2342	PPGMPAGE pPage = &pRam->aPages[iPage];
2343	if (fPresent)
2344	{
2345	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2346	rc = pgmR3LoadPageToDevNullOld(pSSM);
2347	else
2348	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2349	}
2350	else
2351	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2352	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2353	}
2354	}
2355	}
2356	else if (pRam->pvR3)
2357	{
2358	/*
2359	* MMIO2.
2360	*/
2361	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2362	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2363	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2364	AssertLogRelMsgReturn(pRam->pvR3,
2365	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2366	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2367
2368	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2369	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2370	}
2371	else if (GCPhysLast < UINT32_C(0xfff80000))
2372	{
2373	/*
2374	* PCI MMIO, no pages saved.
2375	*/
2376	}
2377	else
2378	{
2379	/*
2380	* Load the 0xfff80000..0xffffffff BIOS range.
2381	* It starts with X reserved pages that we have to skip over since
2382	* the RAMRANGE create by the new code won't include those.
2383	*/
2384	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2385	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2386	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2387	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2388	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2389	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2390	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2391
2392	/* Skip wasted reserved pages before the ROM. */
2393	while (GCPhys < pRam->GCPhys)
2394	{
2395	rc = pgmR3LoadPageToDevNullOld(pSSM);
2396	GCPhys += PAGE_SIZE;
2397	}
2398
2399	/* Load the bios pages. */
2400	cPages = pRam->cb >> PAGE_SHIFT;
2401	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2402	{
2403	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2404	PPGMPAGE pPage = &pRam->aPages[iPage];
2405
2406	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2407	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2408	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2409	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2410	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2411	}
2412	}
2413	}
2414	}
2415
2416	return VINF_SUCCESS;
2417	}
2418
2419
2420	/**
2421	* Worker for pgmR3Load and pgmR3LoadLocked.
2422	*
2423	* @returns VBox status code.
2424	*
2425	* @param pVM The VM handle.
2426	* @param pSSM The SSM handle.
2427	* @param uVersion The saved state version.
2428	*
2429	* @todo This needs splitting up if more record types or code twists are
2430	* added...
2431	*/
2432	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2433	{
2434	/*
2435	* Process page records until we hit the terminator.
2436	*/
2437	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2438	PPGMRAMRANGE pRamHint = NULL;
2439	uint8_t id = UINT8_MAX;
2440	uint32_t iPage = UINT32_MAX - 10;
2441	PPGMROMRANGE pRom = NULL;
2442	PPGMMMIO2RANGE pMmio2 = NULL;
2443	for (;;)
2444	{
2445	/*
2446	* Get the record type and flags.
2447	*/
2448	uint8_t u8;
2449	int rc = SSMR3GetU8(pSSM, &u8);
2450	if (RT_FAILURE(rc))
2451	return rc;
2452	if (u8 == PGM_STATE_REC_END)
2453	return VINF_SUCCESS;
2454	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2455	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2456	{
2457	/*
2458	* RAM page.
2459	*/
2460	case PGM_STATE_REC_RAM_ZERO:
2461	case PGM_STATE_REC_RAM_RAW:
2462	{
2463	/*
2464	* Get the address and resolve it into a page descriptor.
2465	*/
2466	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2467	GCPhys += PAGE_SIZE;
2468	else
2469	{
2470	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2471	if (RT_FAILURE(rc))
2472	return rc;
2473	}
2474	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2475
2476	PPGMPAGE pPage;
2477	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2478	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2479
2480	/*
2481	* Take action according to the record type.
2482	*/
2483	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2484	{
2485	case PGM_STATE_REC_RAM_ZERO:
2486	{
2487	if (PGM_PAGE_IS_ZERO(pPage))
2488	break;
2489	/** @todo implement zero page replacing. */
2490	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2491	void *pvDstPage;
2492	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2493	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2494	ASMMemZeroPage(pvDstPage);
2495	break;
2496	}
2497
2498	case PGM_STATE_REC_RAM_RAW:
2499	{
2500	void *pvDstPage;
2501	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2502	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2503	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2504	if (RT_FAILURE(rc))
2505	return rc;
2506	break;
2507	}
2508
2509	default:
2510	AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2511	}
2512	id = UINT8_MAX;
2513	break;
2514	}
2515
2516	/*
2517	* MMIO2 page.
2518	*/
2519	case PGM_STATE_REC_MMIO2_RAW:
2520	case PGM_STATE_REC_MMIO2_ZERO:
2521	{
2522	/*
2523	* Get the ID + page number and resolved that into a MMIO2 page.
2524	*/
2525	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2526	iPage++;
2527	else
2528	{
2529	SSMR3GetU8(pSSM, &id);
2530	rc = SSMR3GetU32(pSSM, &iPage);
2531	if (RT_FAILURE(rc))
2532	return rc;
2533	}
2534	if ( !pMmio2
2535	\|\| pMmio2->idSavedState != id)
2536	{
2537	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2538	if (pMmio2->idSavedState == id)
2539	break;
2540	AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2541	}
2542	AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2543	void pvDstPage = (uint8_t )pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2544
2545	/*
2546	* Load the page bits.
2547	*/
2548	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2549	ASMMemZeroPage(pvDstPage);
2550	else
2551	{
2552	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2553	if (RT_FAILURE(rc))
2554	return rc;
2555	}
2556	GCPhys = NIL_RTGCPHYS;
2557	break;
2558	}
2559
2560	/*
2561	* ROM pages.
2562	*/
2563	case PGM_STATE_REC_ROM_VIRGIN:
2564	case PGM_STATE_REC_ROM_SHW_RAW:
2565	case PGM_STATE_REC_ROM_SHW_ZERO:
2566	case PGM_STATE_REC_ROM_PROT:
2567	{
2568	/*
2569	* Get the ID + page number and resolved that into a ROM page descriptor.
2570	*/
2571	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2572	iPage++;
2573	else
2574	{
2575	SSMR3GetU8(pSSM, &id);
2576	rc = SSMR3GetU32(pSSM, &iPage);
2577	if (RT_FAILURE(rc))
2578	return rc;
2579	}
2580	if ( !pRom
2581	\|\| pRom->idSavedState != id)
2582	{
2583	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2584	if (pRom->idSavedState == id)
2585	break;
2586	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2587	}
2588	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2589	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2590	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2591
2592	/*
2593	* Get and set the protection.
2594	*/
2595	uint8_t u8Prot;
2596	rc = SSMR3GetU8(pSSM, &u8Prot);
2597	if (RT_FAILURE(rc))
2598	return rc;
2599	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2600	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2601
2602	if (enmProt != pRomPage->enmProt)
2603	{
2604	AssertLogRelMsgReturn(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED,
2605	("GCPhys=%RGp enmProt=%d %s\n", GCPhys, enmProt, pRom->pszDesc),
2606	VERR_SSM_LOAD_CONFIG_MISMATCH);
2607	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2608	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2609	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2610	}
2611	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2612	break; /* done */
2613
2614	/*
2615	* Get the right page descriptor.
2616	*/
2617	PPGMPAGE pRealPage;
2618	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2619	{
2620	case PGM_STATE_REC_ROM_VIRGIN:
2621	if (!PGMROMPROT_IS_ROM(enmProt))
2622	pRealPage = &pRomPage->Virgin;
2623	else
2624	pRealPage = NULL;
2625	break;
2626
2627	case PGM_STATE_REC_ROM_SHW_RAW:
2628	case PGM_STATE_REC_ROM_SHW_ZERO:
2629	AssertLogRelMsgReturn(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED,
2630	("GCPhys=%RGp enmProt=%d %s\n", GCPhys, enmProt, pRom->pszDesc),
2631	VERR_SSM_LOAD_CONFIG_MISMATCH);
2632	if (PGMROMPROT_IS_ROM(enmProt))
2633	pRealPage = &pRomPage->Shadow;
2634	else
2635	pRealPage = NULL;
2636	break;
2637
2638	default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2639	}
2640	if (!pRealPage)
2641	{
2642	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2643	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2644	}
2645
2646	/*
2647	* Make it writable and map it (if necessary).
2648	*/
2649	void *pvDstPage = NULL;
2650	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2651	{
2652	case PGM_STATE_REC_ROM_SHW_ZERO:
2653	if (PGM_PAGE_IS_ZERO(pRealPage))
2654	break;
2655	/** @todo implement zero page replacing. */
2656	/* fall thru */
2657	case PGM_STATE_REC_ROM_VIRGIN:
2658	case PGM_STATE_REC_ROM_SHW_RAW:
2659	{
2660	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2661	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2662	break;
2663	}
2664	}
2665
2666	/*
2667	* Load the bits.
2668	*/
2669	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2670	{
2671	case PGM_STATE_REC_ROM_SHW_ZERO:
2672	if (pvDstPage)
2673	ASMMemZeroPage(pvDstPage);
2674	break;
2675
2676	case PGM_STATE_REC_ROM_VIRGIN:
2677	case PGM_STATE_REC_ROM_SHW_RAW:
2678	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2679	if (RT_FAILURE(rc))
2680	return rc;
2681	break;
2682	}
2683	GCPhys = NIL_RTGCPHYS;
2684	break;
2685	}
2686
2687	/*
2688	* Unknown type.
2689	*/
2690	default:
2691	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2692	}
2693	} /* forever */
2694	}
2695
2696
2697	/**
2698	* Worker for pgmR3Load.
2699	*
2700	* @returns VBox status code.
2701	*
2702	* @param pVM The VM handle.
2703	* @param pSSM The SSM handle.
2704	* @param uVersion The saved state version.
2705	*/
2706	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2707	{
2708	PPGM pPGM = &pVM->pgm.s;
2709	int rc;
2710	uint32_t u32Sep;
2711
2712	/*
2713	* Load basic data (required / unaffected by relocation).
2714	*/
2715	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2716	{
2717	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2718	AssertLogRelRCReturn(rc, rc);
2719
2720	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2721	{
2722	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2723	AssertLogRelRCReturn(rc, rc);
2724	}
2725	}
2726	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2727	{
2728	AssertRelease(pVM->cCpus == 1);
2729
2730	PGMOLD pgmOld;
2731	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2732	AssertLogRelRCReturn(rc, rc);
2733
2734	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2735	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2736	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2737
2738	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2739	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2740	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2741	}
2742	else
2743	{
2744	AssertRelease(pVM->cCpus == 1);
2745
2746	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2747	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2748	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2749
2750	uint32_t cbRamSizeIgnored;
2751	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2752	if (RT_FAILURE(rc))
2753	return rc;
2754	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2755
2756	uint32_t u32 = 0;
2757	SSMR3GetUInt(pSSM, &u32);
2758	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2759	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2760	RTUINT uGuestMode;
2761	SSMR3GetUInt(pSSM, &uGuestMode);
2762	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2763
2764	/* check separator. */
2765	SSMR3GetU32(pSSM, &u32Sep);
2766	if (RT_FAILURE(rc))
2767	return rc;
2768	if (u32Sep != (uint32_t)~0)
2769	{
2770	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2771	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2772	}
2773	}
2774
2775	/*
2776	* The guest mappings.
2777	*/
2778	uint32_t i = 0;
2779	for (;; i++)
2780	{
2781	/* Check the seqence number / separator. */
2782	rc = SSMR3GetU32(pSSM, &u32Sep);
2783	if (RT_FAILURE(rc))
2784	return rc;
2785	if (u32Sep == ~0U)
2786	break;
2787	if (u32Sep != i)
2788	{
2789	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2790	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2791	}
2792
2793	/* get the mapping details. */
2794	char szDesc[256];
2795	szDesc[0] = '\0';
2796	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2797	if (RT_FAILURE(rc))
2798	return rc;
2799	RTGCPTR GCPtr;
2800	SSMR3GetGCPtr(pSSM, &GCPtr);
2801	RTGCPTR cPTs;
2802	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2803	if (RT_FAILURE(rc))
2804	return rc;
2805
2806	/* find matching range. */
2807	PPGMMAPPING pMapping;
2808	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2809	if ( pMapping->cPTs == cPTs
2810	&& !strcmp(pMapping->pszDesc, szDesc))
2811	break;
2812	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2813	cPTs, szDesc, GCPtr),
2814	VERR_SSM_LOAD_CONFIG_MISMATCH);
2815
2816	/* relocate it. */
2817	if (pMapping->GCPtr != GCPtr)
2818	{
2819	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2820	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2821	}
2822	else
2823	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2824	}
2825
2826	/*
2827	* Load the RAM contents.
2828	*/
2829	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2830	{
2831	if (!pVM->pgm.s.LiveSave.fActive)
2832	{
2833	rc = pgmR3LoadRomRanges(pVM, pSSM);
2834	if (RT_FAILURE(rc))
2835	return rc;
2836	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2837	if (RT_FAILURE(rc))
2838	return rc;
2839	}
2840
2841	return pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2842	}
2843	return pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2844	}
2845
2846
2847	/**
2848	* Execute state load operation.
2849	*
2850	* @returns VBox status code.
2851	* @param pVM VM Handle.
2852	* @param pSSM SSM operation handle.
2853	* @param uVersion Data layout version.
2854	* @param uPass The data pass.
2855	*/
2856	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2857	{
2858	int rc;
2859	PPGM pPGM = &pVM->pgm.s;
2860
2861	/*
2862	* Validate version.
2863	*/
2864	if ( ( uPass != SSM_PASS_FINAL
2865	&& uVersion != PGM_SAVED_STATE_VERSION)
2866	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
2867	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
2868	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
2869	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
2870	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2871	)
2872	{
2873	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
2874	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2875	}
2876
2877	/*
2878	* Do the loading while owning the lock because a bunch of the functions
2879	* we're using requires this.
2880	*/
2881	if (uPass != SSM_PASS_FINAL)
2882	{
2883	pgmLock(pVM);
2884	if (uPass != 0)
2885	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2886	else
2887	{
2888	pVM->pgm.s.LiveSave.fActive = true;
2889	rc = pgmR3LoadRomRanges(pVM, pSSM);
2890	if (RT_SUCCESS(rc))
2891	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2892	if (RT_SUCCESS(rc))
2893	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2894	}
2895	pgmUnlock(pVM);
2896	}
2897	else
2898	{
2899	pgmLock(pVM);
2900	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
2901	pVM->pgm.s.LiveSave.fActive = false;
2902	pgmUnlock(pVM);
2903	if (RT_SUCCESS(rc))
2904	{
2905	/*
2906	* We require a full resync now.
2907	*/
2908	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2909	{
2910	PVMCPU pVCpu = &pVM->aCpus[i];
2911	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2912	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2913
2914	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2915	}
2916
2917	pgmR3HandlerPhysicalUpdateAll(pVM);
2918
2919	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2920	{
2921	PVMCPU pVCpu = &pVM->aCpus[i];
2922
2923	/*
2924	* Change the paging mode.
2925	*/
2926	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
2927
2928	/* Restore pVM->pgm.s.GCPhysCR3. */
2929	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2930	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
2931	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
2932	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2933	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
2934	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2935	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2936	else
2937	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2938	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2939	}
2940	}
2941	}
2942
2943	return rc;
2944	}
2945
2946
2947	/**
2948	* Registers the saved state callbacks with SSM.
2949	*
2950	* @returns VBox status code.
2951	* @param pVM Pointer to VM structure.
2952	* @param cbRam The RAM size.
2953	*/
2954	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
2955	{
2956	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
2957	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
2958	NULL, pgmR3SaveExec, pgmR3SaveDone,
2959	pgmR3LoadPrep, pgmR3Load, NULL);
2960	}
2961

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source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 23544

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