PGMSavedState.cpp@ 27436

Last change on this file since 27436 was 27197, checked in by vboxsync, 15 years ago
Refresh the balloon a bit later during state restore.
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File size: 113.7 KB

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1	/* $Id: PGMSavedState.cpp 27197 2010-03-09 09:43:50Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/pgm.h>
28	#include <VBox/stam.h>
29	#include <VBox/ssm.h>
30	#include <VBox/pdmdrv.h>
31	#include <VBox/pdmdev.h>
32	#include "PGMInternal.h"
33	#include <VBox/vm.h>
34	#include "PGMInline.h"
35
36	#include <VBox/param.h>
37	#include <VBox/err.h>
38
39	#include <iprt/asm.h>
40	#include <iprt/assert.h>
41	#include <iprt/crc32.h>
42	#include <iprt/mem.h>
43	#include <iprt/sha.h>
44	#include <iprt/string.h>
45	#include <iprt/thread.h>
46
47
48	/*******************************************************************************
49	* Defined Constants And Macros *
50	*******************************************************************************/
51	/** Saved state data unit version.
52	* @todo remove the guest mappings from the saved state at next version change! */
53	#define PGM_SAVED_STATE_VERSION 12
54	/** Saved state before the balloon change. */
55	#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
56	/** Saved state data unit version used during 3.1 development, misses the RAM
57	* config. */
58	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
59	/** Saved state data unit version for 3.0 (pre teleportation). */
60	#define PGM_SAVED_STATE_VERSION_3_0_0 9
61	/** Saved state data unit version for 2.2.2 and later. */
62	#define PGM_SAVED_STATE_VERSION_2_2_2 8
63	/** Saved state data unit version for 2.2.0. */
64	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
65	/** Saved state data unit version. */
66	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
67
68
69	/** @name Sparse state record types
70	* @{ */
71	/** Zero page. No data. */
72	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
73	/** Raw page. */
74	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
75	/** Raw MMIO2 page. */
76	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
77	/** Zero MMIO2 page. */
78	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
79	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
80	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
81	/** Raw shadowed ROM page. The protection (8-bit) preceeds the raw bits. */
82	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
83	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
84	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
85	/** ROM protection (8-bit). */
86	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
87	/** The last record type. */
88	#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
89	/** End marker. */
90	#define PGM_STATE_REC_END UINT8_C(0xff)
91	/** Flag indicating that the data is preceeded by the page address.
92	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
93	* range ID and a 32-bit page index.
94	*/
95	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
96	/** @} */
97
98	/** The CRC-32 for a zero page. */
99	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
100	/** The CRC-32 for a zero half page. */
101	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
102
103
104	/*******************************************************************************
105	* Structures and Typedefs *
106	*******************************************************************************/
107	/** For loading old saved states. (pre-smp) */
108	typedef struct
109	{
110	/** If set no conflict checks are required. (boolean) */
111	bool fMappingsFixed;
112	/** Size of fixed mapping */
113	uint32_t cbMappingFixed;
114	/** Base address (GC) of fixed mapping */
115	RTGCPTR GCPtrMappingFixed;
116	/** A20 gate mask.
117	* Our current approach to A20 emulation is to let REM do it and don't bother
118	* anywhere else. The interesting guests will be operating with it enabled anyway.
119	* But should the need arise, we'll subject physical addresses to this mask. */
120	RTGCPHYS GCPhysA20Mask;
121	/** A20 gate state - boolean! */
122	bool fA20Enabled;
123	/** The guest paging mode. */
124	PGMMODE enmGuestMode;
125	} PGMOLD;
126
127
128	/*******************************************************************************
129	* Global Variables *
130	*******************************************************************************/
131	/** PGM fields to save/load. */
132
133	static const SSMFIELD s_aPGMFields[] =
134	{
135	SSMFIELD_ENTRY( PGM, fMappingsFixed),
136	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
137	SSMFIELD_ENTRY( PGM, cbMappingFixed),
138	SSMFIELD_ENTRY( PGM, cBalloonedPages),
139	SSMFIELD_ENTRY_TERM()
140	};
141
142	static const SSMFIELD s_aPGMFieldsPreBalloon[] =
143	{
144	SSMFIELD_ENTRY( PGM, fMappingsFixed),
145	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
146	SSMFIELD_ENTRY( PGM, cbMappingFixed),
147	SSMFIELD_ENTRY_TERM()
148	};
149
150	static const SSMFIELD s_aPGMCpuFields[] =
151	{
152	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
153	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
154	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
155	SSMFIELD_ENTRY_TERM()
156	};
157
158	static const SSMFIELD s_aPGMFields_Old[] =
159	{
160	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
161	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
162	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
163	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
164	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
165	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
166	SSMFIELD_ENTRY_TERM()
167	};
168
169
170	/**
171	* Find the ROM tracking structure for the given page.
172	*
173	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
174	* that it's a ROM page.
175	* @param pVM The VM handle.
176	* @param GCPhys The address of the ROM page.
177	*/
178	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
179	{
180	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
181	pRomRange;
182	pRomRange = pRomRange->CTX_SUFF(pNext))
183	{
184	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
185	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
186	return &pRomRange->aPages[off >> PAGE_SHIFT];
187	}
188	return NULL;
189	}
190
191
192	/**
193	* Prepares the ROM pages for a live save.
194	*
195	* @returns VBox status code.
196	* @param pVM The VM handle.
197	*/
198	static int pgmR3PrepRomPages(PVM pVM)
199	{
200	/*
201	* Initialize the live save tracking in the ROM page descriptors.
202	*/
203	pgmLock(pVM);
204	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
205	{
206	PPGMRAMRANGE pRamHint = NULL;;
207	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
208
209	for (uint32_t iPage = 0; iPage < cPages; iPage++)
210	{
211	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
212	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
213	pRom->aPages[iPage].LiveSave.fDirty = true;
214	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
215	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
216	{
217	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
218	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
219	else
220	{
221	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
222	PPGMPAGE pPage;
223	int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
224	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
225	if (RT_SUCCESS(rc))
226	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage);
227	else
228	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
229	}
230	}
231	}
232
233	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
234	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
235	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
236	}
237	pgmUnlock(pVM);
238
239	return VINF_SUCCESS;
240	}
241
242
243	/**
244	* Assigns IDs to the ROM ranges and saves them.
245	*
246	* @returns VBox status code.
247	* @param pVM The VM handle.
248	* @param pSSM Saved state handle.
249	*/
250	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
251	{
252	pgmLock(pVM);
253	uint8_t id = 1;
254	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
255	{
256	pRom->idSavedState = id;
257	SSMR3PutU8(pSSM, id);
258	SSMR3PutStrZ(pSSM, ""); /* device name */
259	SSMR3PutU32(pSSM, 0); /* device instance */
260	SSMR3PutU8(pSSM, 0); /* region */
261	SSMR3PutStrZ(pSSM, pRom->pszDesc);
262	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
263	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
264	if (RT_FAILURE(rc))
265	break;
266	}
267	pgmUnlock(pVM);
268	return SSMR3PutU8(pSSM, UINT8_MAX);
269	}
270
271
272	/**
273	* Loads the ROM range ID assignments.
274	*
275	* @returns VBox status code.
276	*
277	* @param pVM The VM handle.
278	* @param pSSM The saved state handle.
279	*/
280	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
281	{
282	Assert(PGMIsLockOwner(pVM));
283
284	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
285	pRom->idSavedState = UINT8_MAX;
286
287	for (;;)
288	{
289	/*
290	* Read the data.
291	*/
292	uint8_t id;
293	int rc = SSMR3GetU8(pSSM, &id);
294	if (RT_FAILURE(rc))
295	return rc;
296	if (id == UINT8_MAX)
297	{
298	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
299	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX, ("%s\n", pRom->pszDesc));
300	return VINF_SUCCESS; /* the end */
301	}
302	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
303
304	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
305	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
306	AssertLogRelRCReturn(rc, rc);
307
308	uint32_t uInstance;
309	SSMR3GetU32(pSSM, &uInstance);
310	uint8_t iRegion;
311	SSMR3GetU8(pSSM, &iRegion);
312
313	char szDesc[64];
314	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
315	AssertLogRelRCReturn(rc, rc);
316
317	RTGCPHYS GCPhys;
318	SSMR3GetGCPhys(pSSM, &GCPhys);
319	RTGCPHYS cb;
320	rc = SSMR3GetGCPhys(pSSM, &cb);
321	if (RT_FAILURE(rc))
322	return rc;
323	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
324	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
325
326	/*
327	* Locate a matching ROM range.
328	*/
329	AssertLogRelMsgReturn( uInstance == 0
330	&& iRegion == 0
331	&& szDevName[0] == '\0',
332	("GCPhys=%RGp %s\n", GCPhys, szDesc),
333	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
334	PPGMROMRANGE pRom;
335	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
336	{
337	if ( pRom->idSavedState == UINT8_MAX
338	&& !strcmp(pRom->pszDesc, szDesc))
339	{
340	pRom->idSavedState = id;
341	break;
342	}
343	}
344	if (!pRom)
345	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
346	} /* forever */
347	}
348
349
350	/**
351	* Scan ROM pages.
352	*
353	* @param pVM The VM handle.
354	*/
355	static void pgmR3ScanRomPages(PVM pVM)
356	{
357	/*
358	* The shadow ROMs.
359	*/
360	pgmLock(pVM);
361	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
362	{
363	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
364	{
365	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
366	for (uint32_t iPage = 0; iPage < cPages; iPage++)
367	{
368	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
369	if (pRomPage->LiveSave.fWrittenTo)
370	{
371	pRomPage->LiveSave.fWrittenTo = false;
372	if (!pRomPage->LiveSave.fDirty)
373	{
374	pRomPage->LiveSave.fDirty = true;
375	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
376	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
377	}
378	pRomPage->LiveSave.fDirtiedRecently = true;
379	}
380	else
381	pRomPage->LiveSave.fDirtiedRecently = false;
382	}
383	}
384	}
385	pgmUnlock(pVM);
386	}
387
388
389	/**
390	* Takes care of the virgin ROM pages in the first pass.
391	*
392	* This is an attempt at simplifying the handling of ROM pages a little bit.
393	* This ASSUMES that no new ROM ranges will be added and that they won't be
394	* relinked in any way.
395	*
396	* @param pVM The VM handle.
397	* @param pSSM The SSM handle.
398	* @param fLiveSave Whether we're in a live save or not.
399	*/
400	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
401	{
402	pgmLock(pVM);
403	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
404	{
405	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
406	for (uint32_t iPage = 0; iPage < cPages; iPage++)
407	{
408	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
409	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
410
411	/* Get the virgin page descriptor. */
412	PPGMPAGE pPage;
413	if (PGMROMPROT_IS_ROM(enmProt))
414	pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
415	else
416	pPage = &pRom->aPages[iPage].Virgin;
417
418	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
419	int rc = VINF_SUCCESS;
420	char abPage[PAGE_SIZE];
421	if (!PGM_PAGE_IS_ZERO(pPage))
422	{
423	void const *pvPage;
424	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
425	if (RT_SUCCESS(rc))
426	memcpy(abPage, pvPage, PAGE_SIZE);
427	}
428	else
429	ASMMemZeroPage(abPage);
430	pgmUnlock(pVM);
431	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
432
433	/* Save it. */
434	if (iPage > 0)
435	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
436	else
437	{
438	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
439	SSMR3PutU8(pSSM, pRom->idSavedState);
440	SSMR3PutU32(pSSM, iPage);
441	}
442	SSMR3PutU8(pSSM, (uint8_t)enmProt);
443	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
444	if (RT_FAILURE(rc))
445	return rc;
446
447	/* Update state. */
448	pgmLock(pVM);
449	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
450	if (fLiveSave)
451	{
452	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
453	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
454	pVM->pgm.s.LiveSave.cSavedPages++;
455	}
456	}
457	}
458	pgmUnlock(pVM);
459	return VINF_SUCCESS;
460	}
461
462
463	/**
464	* Saves dirty pages in the shadowed ROM ranges.
465	*
466	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
467	*
468	* @returns VBox status code.
469	* @param pVM The VM handle.
470	* @param pSSM The SSM handle.
471	* @param fLiveSave Whether it's a live save or not.
472	* @param fFinalPass Whether this is the final pass or not.
473	*/
474	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
475	{
476	/*
477	* The Shadowed ROMs.
478	*
479	* ASSUMES that the ROM ranges are fixed.
480	* ASSUMES that all the ROM ranges are mapped.
481	*/
482	pgmLock(pVM);
483	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
484	{
485	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
486	{
487	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
488	uint32_t iPrevPage = cPages;
489	for (uint32_t iPage = 0; iPage < cPages; iPage++)
490	{
491	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
492	if ( !fLiveSave
493	\|\| ( pRomPage->LiveSave.fDirty
494	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
495	&& !pRomPage->LiveSave.fWrittenTo)
496	\|\| fFinalPass
497	)
498	)
499	)
500	{
501	uint8_t abPage[PAGE_SIZE];
502	PGMROMPROT enmProt = pRomPage->enmProt;
503	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
504	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
505	bool fZero = PGM_PAGE_IS_ZERO(pPage);
506	int rc = VINF_SUCCESS;
507	if (!fZero)
508	{
509	void const *pvPage;
510	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
511	if (RT_SUCCESS(rc))
512	memcpy(abPage, pvPage, PAGE_SIZE);
513	}
514	if (fLiveSave && RT_SUCCESS(rc))
515	{
516	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
517	pRomPage->LiveSave.fDirty = false;
518	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
519	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
520	pVM->pgm.s.LiveSave.cSavedPages++;
521	}
522	pgmUnlock(pVM);
523	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
524
525	if (iPage - 1U == iPrevPage && iPage > 0)
526	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
527	else
528	{
529	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
530	SSMR3PutU8(pSSM, pRom->idSavedState);
531	SSMR3PutU32(pSSM, iPage);
532	}
533	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
534	if (!fZero)
535	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
536	if (RT_FAILURE(rc))
537	return rc;
538
539	pgmLock(pVM);
540	iPrevPage = iPage;
541	}
542	/*
543	* In the final pass, make sure the protection is in sync.
544	*/
545	else if ( fFinalPass
546	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
547	{
548	PGMROMPROT enmProt = pRomPage->enmProt;
549	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
550	pgmUnlock(pVM);
551
552	if (iPage - 1U == iPrevPage && iPage > 0)
553	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
554	else
555	{
556	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
557	SSMR3PutU8(pSSM, pRom->idSavedState);
558	SSMR3PutU32(pSSM, iPage);
559	}
560	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
561	if (RT_FAILURE(rc))
562	return rc;
563
564	pgmLock(pVM);
565	iPrevPage = iPage;
566	}
567	}
568	}
569	}
570	pgmUnlock(pVM);
571	return VINF_SUCCESS;
572	}
573
574
575	/**
576	* Cleans up ROM pages after a live save.
577	*
578	* @param pVM The VM handle.
579	*/
580	static void pgmR3DoneRomPages(PVM pVM)
581	{
582	NOREF(pVM);
583	}
584
585
586	/**
587	* Prepares the MMIO2 pages for a live save.
588	*
589	* @returns VBox status code.
590	* @param pVM The VM handle.
591	*/
592	static int pgmR3PrepMmio2Pages(PVM pVM)
593	{
594	/*
595	* Initialize the live save tracking in the MMIO2 ranges.
596	* ASSUME nothing changes here.
597	*/
598	pgmLock(pVM);
599	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
600	{
601	uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
602	pgmUnlock(pVM);
603
604	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
605	if (!paLSPages)
606	return VERR_NO_MEMORY;
607	for (uint32_t iPage = 0; iPage < cPages; iPage++)
608	{
609	/* Initialize it as a dirty zero page. */
610	paLSPages[iPage].fDirty = true;
611	paLSPages[iPage].cUnchangedScans = 0;
612	paLSPages[iPage].fZero = true;
613	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
614	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
615	}
616
617	pgmLock(pVM);
618	pMmio2->paLSPages = paLSPages;
619	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
620	}
621	pgmUnlock(pVM);
622	return VINF_SUCCESS;
623	}
624
625
626	/**
627	* Assigns IDs to the MMIO2 ranges and saves them.
628	*
629	* @returns VBox status code.
630	* @param pVM The VM handle.
631	* @param pSSM Saved state handle.
632	*/
633	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
634	{
635	pgmLock(pVM);
636	uint8_t id = 1;
637	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
638	{
639	pMmio2->idSavedState = id;
640	SSMR3PutU8(pSSM, id);
641	SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pReg->szName);
642	SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
643	SSMR3PutU8(pSSM, pMmio2->iRegion);
644	SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
645	int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
646	if (RT_FAILURE(rc))
647	break;
648	}
649	pgmUnlock(pVM);
650	return SSMR3PutU8(pSSM, UINT8_MAX);
651	}
652
653
654	/**
655	* Loads the MMIO2 range ID assignments.
656	*
657	* @returns VBox status code.
658	*
659	* @param pVM The VM handle.
660	* @param pSSM The saved state handle.
661	*/
662	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
663	{
664	Assert(PGMIsLockOwner(pVM));
665
666	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
667	pMmio2->idSavedState = UINT8_MAX;
668
669	for (;;)
670	{
671	/*
672	* Read the data.
673	*/
674	uint8_t id;
675	int rc = SSMR3GetU8(pSSM, &id);
676	if (RT_FAILURE(rc))
677	return rc;
678	if (id == UINT8_MAX)
679	{
680	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
681	AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
682	return VINF_SUCCESS; /* the end */
683	}
684	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
685
686	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
687	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
688	AssertLogRelRCReturn(rc, rc);
689
690	uint32_t uInstance;
691	SSMR3GetU32(pSSM, &uInstance);
692	uint8_t iRegion;
693	SSMR3GetU8(pSSM, &iRegion);
694
695	char szDesc[64];
696	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
697	AssertLogRelRCReturn(rc, rc);
698
699	RTGCPHYS cb;
700	rc = SSMR3GetGCPhys(pSSM, &cb);
701	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
702
703	/*
704	* Locate a matching MMIO2 range.
705	*/
706	PPGMMMIO2RANGE pMmio2;
707	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
708	{
709	if ( pMmio2->idSavedState == UINT8_MAX
710	&& pMmio2->iRegion == iRegion
711	&& pMmio2->pDevInsR3->iInstance == uInstance
712	&& !strcmp(pMmio2->pDevInsR3->pReg->szName, szDevName))
713	{
714	pMmio2->idSavedState = id;
715	break;
716	}
717	}
718	if (!pMmio2)
719	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
720	szDesc, szDevName, uInstance, iRegion);
721
722	/*
723	* Validate the configuration, the size of the MMIO2 region should be
724	* the same.
725	*/
726	if (cb != pMmio2->RamRange.cb)
727	{
728	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
729	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
730	if (cb > pMmio2->RamRange.cb) /* bad idea? */
731	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
732	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
733	}
734	} /* forever */
735	}
736
737
738	/**
739	* Scans one MMIO2 page.
740	*
741	* @returns True if changed, false if unchanged.
742	*
743	* @param pVM The VM handle
744	* @param pbPage The page bits.
745	* @param pLSPage The live save tracking structure for the page.
746	*
747	*/
748	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
749	{
750	/*
751	* Special handling of zero pages.
752	*/
753	bool const fZero = pLSPage->fZero;
754	if (fZero)
755	{
756	if (ASMMemIsZeroPage(pbPage))
757	{
758	/* Not modified. */
759	if (pLSPage->fDirty)
760	pLSPage->cUnchangedScans++;
761	return false;
762	}
763
764	pLSPage->fZero = false;
765	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
766	}
767	else
768	{
769	/*
770	* CRC the first half, if it doesn't match the page is dirty and
771	* we won't check the 2nd half (we'll do that next time).
772	*/
773	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
774	if (u32CrcH1 == pLSPage->u32CrcH1)
775	{
776	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
777	if (u32CrcH2 == pLSPage->u32CrcH2)
778	{
779	/* Probably not modified. */
780	if (pLSPage->fDirty)
781	pLSPage->cUnchangedScans++;
782	return false;
783	}
784
785	pLSPage->u32CrcH2 = u32CrcH2;
786	}
787	else
788	{
789	pLSPage->u32CrcH1 = u32CrcH1;
790	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
791	&& ASMMemIsZeroPage(pbPage))
792	{
793	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
794	pLSPage->fZero = true;
795	}
796	}
797	}
798
799	/* dirty page path */
800	pLSPage->cUnchangedScans = 0;
801	if (!pLSPage->fDirty)
802	{
803	pLSPage->fDirty = true;
804	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
805	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
806	if (fZero)
807	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
808	}
809	return true;
810	}
811
812
813	/**
814	* Scan for MMIO2 page modifications.
815	*
816	* @param pVM The VM handle.
817	* @param uPass The pass number.
818	*/
819	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
820	{
821	/*
822	* Since this is a bit expensive we lower the scan rate after a little while.
823	*/
824	if ( ( (uPass & 3) != 0
825	&& uPass > 10)
826	\|\| uPass == SSM_PASS_FINAL)
827	return;
828
829	pgmLock(pVM); /* paranoia */
830	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
831	{
832	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
833	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
834	pgmUnlock(pVM);
835
836	for (uint32_t iPage = 0; iPage < cPages; iPage++)
837	{
838	uint8_t const pbPage = (uint8_t const )pMmio2->pvR3 + iPage * PAGE_SIZE;
839	pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
840	}
841
842	pgmLock(pVM);
843	}
844	pgmUnlock(pVM);
845
846	}
847
848
849	/**
850	* Save quiescent MMIO2 pages.
851	*
852	* @returns VBox status code.
853	* @param pVM The VM handle.
854	* @param pSSM The SSM handle.
855	* @param fLiveSave Whether it's a live save or not.
856	* @param uPass The pass number.
857	*/
858	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
859	{
860	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
861	* device that we wish to know about changes.) */
862
863	int rc = VINF_SUCCESS;
864	if (uPass == SSM_PASS_FINAL)
865	{
866	/*
867	* The mop up round.
868	*/
869	pgmLock(pVM);
870	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
871	pMmio2 && RT_SUCCESS(rc);
872	pMmio2 = pMmio2->pNextR3)
873	{
874	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
875	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
876	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
877	uint32_t iPageLast = cPages;
878	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
879	{
880	uint8_t u8Type;
881	if (!fLiveSave)
882	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
883	else
884	{
885	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
886	if ( !paLSPages[iPage].fDirty
887	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
888	{
889	if (paLSPages[iPage].fZero)
890	continue;
891
892	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
893	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
894	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
895	continue;
896	}
897	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
898	pVM->pgm.s.LiveSave.cSavedPages++;
899	}
900
901	if (iPage != 0 && iPage == iPageLast + 1)
902	rc = SSMR3PutU8(pSSM, u8Type);
903	else
904	{
905	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
906	SSMR3PutU8(pSSM, pMmio2->idSavedState);
907	rc = SSMR3PutU32(pSSM, iPage);
908	}
909	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
910	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
911	if (RT_FAILURE(rc))
912	break;
913	iPageLast = iPage;
914	}
915	}
916	pgmUnlock(pVM);
917	}
918	/*
919	* Reduce the rate after a little while since the current MMIO2 approach is
920	* a bit expensive.
921	* We position it two passes after the scan pass to avoid saving busy pages.
922	*/
923	else if ( uPass <= 10
924	\|\| (uPass & 3) == 2)
925	{
926	pgmLock(pVM);
927	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
928	pMmio2 && RT_SUCCESS(rc);
929	pMmio2 = pMmio2->pNextR3)
930	{
931	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
932	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
933	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
934	uint32_t iPageLast = cPages;
935	pgmUnlock(pVM);
936
937	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
938	{
939	/* Skip clean pages and pages which hasn't quiesced. */
940	if (!paLSPages[iPage].fDirty)
941	continue;
942	if (paLSPages[iPage].cUnchangedScans < 3)
943	continue;
944	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
945	continue;
946
947	/* Save it. */
948	bool const fZero = paLSPages[iPage].fZero;
949	uint8_t abPage[PAGE_SIZE];
950	if (!fZero)
951	{
952	memcpy(abPage, pbPage, PAGE_SIZE);
953	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
954	}
955
956	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
957	if (iPage != 0 && iPage == iPageLast + 1)
958	rc = SSMR3PutU8(pSSM, u8Type);
959	else
960	{
961	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
962	SSMR3PutU8(pSSM, pMmio2->idSavedState);
963	rc = SSMR3PutU32(pSSM, iPage);
964	}
965	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
966	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
967	if (RT_FAILURE(rc))
968	break;
969
970	/* Housekeeping. */
971	paLSPages[iPage].fDirty = false;
972	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
973	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
974	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
975	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
976	pVM->pgm.s.LiveSave.cSavedPages++;
977	iPageLast = iPage;
978	}
979
980	pgmLock(pVM);
981	}
982	pgmUnlock(pVM);
983	}
984
985	return rc;
986	}
987
988
989	/**
990	* Cleans up MMIO2 pages after a live save.
991	*
992	* @param pVM The VM handle.
993	*/
994	static void pgmR3DoneMmio2Pages(PVM pVM)
995	{
996	/*
997	* Free the tracking structures for the MMIO2 pages.
998	* We do the freeing outside the lock in case the VM is running.
999	*/
1000	pgmLock(pVM);
1001	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
1002	{
1003	void *pvMmio2ToFree = pMmio2->paLSPages;
1004	if (pvMmio2ToFree)
1005	{
1006	pMmio2->paLSPages = NULL;
1007	pgmUnlock(pVM);
1008	MMR3HeapFree(pvMmio2ToFree);
1009	pgmLock(pVM);
1010	}
1011	}
1012	pgmUnlock(pVM);
1013	}
1014
1015
1016	/**
1017	* Prepares the RAM pages for a live save.
1018	*
1019	* @returns VBox status code.
1020	* @param pVM The VM handle.
1021	*/
1022	static int pgmR3PrepRamPages(PVM pVM)
1023	{
1024
1025	/*
1026	* Try allocating tracking structures for the ram ranges.
1027	*
1028	* To avoid lock contention, we leave the lock every time we're allocating
1029	* a new array. This means we'll have to ditch the allocation and start
1030	* all over again if the RAM range list changes in-between.
1031	*
1032	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1033	* for cleaning up.
1034	*/
1035	PPGMRAMRANGE pCur;
1036	pgmLock(pVM);
1037	do
1038	{
1039	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1040	{
1041	if ( !pCur->paLSPages
1042	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1043	{
1044	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1045	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1046	pgmUnlock(pVM);
1047	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1048	if (!paLSPages)
1049	return VERR_NO_MEMORY;
1050	pgmLock(pVM);
1051	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1052	{
1053	pgmUnlock(pVM);
1054	MMR3HeapFree(paLSPages);
1055	pgmLock(pVM);
1056	break; /* try again */
1057	}
1058	pCur->paLSPages = paLSPages;
1059
1060	/*
1061	* Initialize the array.
1062	*/
1063	uint32_t iPage = cPages;
1064	while (iPage-- > 0)
1065	{
1066	/** @todo yield critsect! (after moving this away from EMT0) */
1067	PCPGMPAGE pPage = &pCur->aPages[iPage];
1068	paLSPages[iPage].cDirtied = 0;
1069	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1070	paLSPages[iPage].fWriteMonitored = 0;
1071	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1072	paLSPages[iPage].u2Reserved = 0;
1073	switch (PGM_PAGE_GET_TYPE(pPage))
1074	{
1075	case PGMPAGETYPE_RAM:
1076	if (PGM_PAGE_IS_ZERO(pPage))
1077	{
1078	paLSPages[iPage].fZero = 1;
1079	paLSPages[iPage].fShared = 0;
1080	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1081	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1082	#endif
1083	}
1084	else if (PGM_PAGE_IS_SHARED(pPage))
1085	{
1086	paLSPages[iPage].fZero = 0;
1087	paLSPages[iPage].fShared = 1;
1088	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1089	paLSPages[iPage].u32Crc = UINT32_MAX;
1090	#endif
1091	}
1092	else
1093	{
1094	paLSPages[iPage].fZero = 0;
1095	paLSPages[iPage].fShared = 0;
1096	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1097	paLSPages[iPage].u32Crc = UINT32_MAX;
1098	#endif
1099	}
1100	paLSPages[iPage].fIgnore = 0;
1101	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1102	break;
1103
1104	case PGMPAGETYPE_ROM_SHADOW:
1105	case PGMPAGETYPE_ROM:
1106	{
1107	paLSPages[iPage].fZero = 0;
1108	paLSPages[iPage].fShared = 0;
1109	paLSPages[iPage].fDirty = 0;
1110	paLSPages[iPage].fIgnore = 1;
1111	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1112	paLSPages[iPage].u32Crc = UINT32_MAX;
1113	#endif
1114	pVM->pgm.s.LiveSave.cIgnoredPages++;
1115	break;
1116	}
1117
1118	default:
1119	AssertMsgFailed(("%R[pgmpage]", pPage));
1120	case PGMPAGETYPE_MMIO2:
1121	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1122	paLSPages[iPage].fZero = 0;
1123	paLSPages[iPage].fShared = 0;
1124	paLSPages[iPage].fDirty = 0;
1125	paLSPages[iPage].fIgnore = 1;
1126	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1127	paLSPages[iPage].u32Crc = UINT32_MAX;
1128	#endif
1129	pVM->pgm.s.LiveSave.cIgnoredPages++;
1130	break;
1131
1132	case PGMPAGETYPE_MMIO:
1133	paLSPages[iPage].fZero = 0;
1134	paLSPages[iPage].fShared = 0;
1135	paLSPages[iPage].fDirty = 0;
1136	paLSPages[iPage].fIgnore = 1;
1137	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1138	paLSPages[iPage].u32Crc = UINT32_MAX;
1139	#endif
1140	pVM->pgm.s.LiveSave.cIgnoredPages++;
1141	break;
1142	}
1143	}
1144	}
1145	}
1146	} while (pCur);
1147	pgmUnlock(pVM);
1148
1149	return VINF_SUCCESS;
1150	}
1151
1152
1153	/**
1154	* Saves the RAM configuration.
1155	*
1156	* @returns VBox status code.
1157	* @param pVM The VM handle.
1158	* @param pSSM The saved state handle.
1159	*/
1160	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1161	{
1162	uint32_t cbRamHole = 0;
1163	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1164	AssertRCReturn(rc, rc);
1165
1166	uint64_t cbRam = 0;
1167	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1168	AssertRCReturn(rc, rc);
1169
1170	SSMR3PutU32(pSSM, cbRamHole);
1171	return SSMR3PutU64(pSSM, cbRam);
1172	}
1173
1174
1175	/**
1176	* Loads and verifies the RAM configuration.
1177	*
1178	* @returns VBox status code.
1179	* @param pVM The VM handle.
1180	* @param pSSM The saved state handle.
1181	*/
1182	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1183	{
1184	uint32_t cbRamHoleCfg = 0;
1185	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1186	AssertRCReturn(rc, rc);
1187
1188	uint64_t cbRamCfg = 0;
1189	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1190	AssertRCReturn(rc, rc);
1191
1192	uint32_t cbRamHoleSaved;
1193	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1194
1195	uint64_t cbRamSaved;
1196	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1197	AssertRCReturn(rc, rc);
1198
1199	if ( cbRamHoleCfg != cbRamHoleSaved
1200	\|\| cbRamCfg != cbRamSaved)
1201	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1202	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1203	return VINF_SUCCESS;
1204	}
1205
1206	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1207
1208	/**
1209	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1210	* info with it.
1211	*
1212	* @param pVM The VM handle.
1213	* @param pCur The current RAM range.
1214	* @param paLSPages The current array of live save page tracking
1215	* structures.
1216	* @param iPage The page index.
1217	*/
1218	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1219	{
1220	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1221	void const *pvPage;
1222	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1223	if (RT_SUCCESS(rc))
1224	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1225	else
1226	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1227	}
1228
1229
1230	/**
1231	* Verifies the CRC-32 for a page given it's raw bits.
1232	*
1233	* @param pvPage The page bits.
1234	* @param pCur The current RAM range.
1235	* @param paLSPages The current array of live save page tracking
1236	* structures.
1237	* @param iPage The page index.
1238	*/
1239	static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1240	{
1241	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1242	{
1243	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1244	Assert(!PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) \|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1245	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1246	("%08x != %08x for %RGp %R[pgmpage]\n", paLSPages[iPage].u32Crc, u32Crc,
1247	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1248	}
1249	}
1250
1251
1252	/**
1253	* Verfies the CRC-32 for a RAM page.
1254	*
1255	* @param pVM The VM handle.
1256	* @param pCur The current RAM range.
1257	* @param paLSPages The current array of live save page tracking
1258	* structures.
1259	* @param iPage The page index.
1260	*/
1261	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1262	{
1263	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1264	{
1265	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1266	void const *pvPage;
1267	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1268	if (RT_SUCCESS(rc))
1269	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage);
1270	}
1271	}
1272
1273	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1274
1275	/**
1276	* Scan for RAM page modifications and reprotect them.
1277	*
1278	* @param pVM The VM handle.
1279	* @param fFinalPass Whether this is the final pass or not.
1280	*/
1281	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1282	{
1283	/*
1284	* The RAM.
1285	*/
1286	RTGCPHYS GCPhysCur = 0;
1287	PPGMRAMRANGE pCur;
1288	pgmLock(pVM);
1289	do
1290	{
1291	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1292	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1293	{
1294	if ( pCur->GCPhysLast > GCPhysCur
1295	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1296	{
1297	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1298	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1299	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1300	GCPhysCur = 0;
1301	for (; iPage < cPages; iPage++)
1302	{
1303	/* Do yield first. */
1304	if ( !fFinalPass
1305	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1306	&& (iPage & 0x7ff) == 0x100
1307	#endif
1308	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1309	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1310	{
1311	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1312	break; /* restart */
1313	}
1314
1315	/* Skip already ignored pages. */
1316	if (paLSPages[iPage].fIgnore)
1317	continue;
1318
1319	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1320	{
1321	/*
1322	* A RAM page.
1323	*/
1324	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1325	{
1326	case PGM_PAGE_STATE_ALLOCATED:
1327	/** @todo Optimize this: Don't always re-enable write
1328	* monitoring if the page is known to be very busy. */
1329	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1330	{
1331	Assert(paLSPages[iPage].fWriteMonitored);
1332	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1333	Assert(pVM->pgm.s.cWrittenToPages > 0);
1334	pVM->pgm.s.cWrittenToPages--;
1335	}
1336	else
1337	{
1338	Assert(!paLSPages[iPage].fWriteMonitored);
1339	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1340	}
1341
1342	if (!paLSPages[iPage].fDirty)
1343	{
1344	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1345	if (paLSPages[iPage].fZero)
1346	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1347	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1348	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1349	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1350	}
1351
1352	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1353	pVM->pgm.s.cMonitoredPages++;
1354	paLSPages[iPage].fWriteMonitored = 1;
1355	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1356	paLSPages[iPage].fDirty = 1;
1357	paLSPages[iPage].fZero = 0;
1358	paLSPages[iPage].fShared = 0;
1359	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1360	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1361	#endif
1362	break;
1363
1364	case PGM_PAGE_STATE_WRITE_MONITORED:
1365	Assert(paLSPages[iPage].fWriteMonitored);
1366	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1367	{
1368	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1369	if (paLSPages[iPage].fWriteMonitoredJustNow)
1370	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1371	else
1372	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1373	#endif
1374	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1375	}
1376	else
1377	{
1378	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1379	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1380	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1381	#endif
1382	if (!paLSPages[iPage].fDirty)
1383	{
1384	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1385	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1386	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1387	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1388	}
1389	}
1390	break;
1391
1392	case PGM_PAGE_STATE_ZERO:
1393	if (!paLSPages[iPage].fZero)
1394	{
1395	if (!paLSPages[iPage].fDirty)
1396	{
1397	paLSPages[iPage].fDirty = 1;
1398	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1399	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1400	}
1401	paLSPages[iPage].fZero = 1;
1402	paLSPages[iPage].fShared = 0;
1403	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1404	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1405	#endif
1406	}
1407	break;
1408
1409	case PGM_PAGE_STATE_SHARED:
1410	if (!paLSPages[iPage].fShared)
1411	{
1412	if (!paLSPages[iPage].fDirty)
1413	{
1414	paLSPages[iPage].fDirty = 1;
1415	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1416	if (paLSPages[iPage].fZero)
1417	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1418	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1419	}
1420	paLSPages[iPage].fZero = 0;
1421	paLSPages[iPage].fShared = 1;
1422	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1423	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1424	#endif
1425	}
1426	break;
1427	}
1428	}
1429	else
1430	{
1431	/*
1432	* All other types => Ignore the page.
1433	*/
1434	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1435	paLSPages[iPage].fIgnore = 1;
1436	if (paLSPages[iPage].fWriteMonitored)
1437	{
1438	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1439	* pages! */
1440	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1441	{
1442	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1443	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1444	Assert(pVM->pgm.s.cMonitoredPages > 0);
1445	pVM->pgm.s.cMonitoredPages--;
1446	}
1447	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1448	{
1449	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1450	Assert(pVM->pgm.s.cWrittenToPages > 0);
1451	pVM->pgm.s.cWrittenToPages--;
1452	}
1453	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1454	}
1455
1456	/** @todo the counting doesn't quite work out here. fix later? */
1457	if (paLSPages[iPage].fDirty)
1458	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1459	else
1460	{
1461	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1462	if (paLSPages[iPage].fZero)
1463	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1464	}
1465	pVM->pgm.s.LiveSave.cIgnoredPages++;
1466	}
1467	} /* for each page in range */
1468
1469	if (GCPhysCur != 0)
1470	break; /* Yield + ramrange change */
1471	GCPhysCur = pCur->GCPhysLast;
1472	}
1473	} /* for each range */
1474	} while (pCur);
1475	pgmUnlock(pVM);
1476	}
1477
1478
1479	/**
1480	* Save quiescent RAM pages.
1481	*
1482	* @returns VBox status code.
1483	* @param pVM The VM handle.
1484	* @param pSSM The SSM handle.
1485	* @param fLiveSave Whether it's a live save or not.
1486	* @param uPass The pass number.
1487	*/
1488	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1489	{
1490	/*
1491	* The RAM.
1492	*/
1493	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1494	RTGCPHYS GCPhysCur = 0;
1495	PPGMRAMRANGE pCur;
1496	pgmLock(pVM);
1497	do
1498	{
1499	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1500	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1501	{
1502	if ( pCur->GCPhysLast > GCPhysCur
1503	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1504	{
1505	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1506	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1507	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1508	GCPhysCur = 0;
1509	for (; iPage < cPages; iPage++)
1510	{
1511	/* Do yield first. */
1512	if ( uPass != SSM_PASS_FINAL
1513	&& (iPage & 0x7ff) == 0x100
1514	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1515	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1516	{
1517	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1518	break; /* restart */
1519	}
1520
1521	/*
1522	* Only save pages that hasn't changed since last scan and are dirty.
1523	*/
1524	if ( uPass != SSM_PASS_FINAL
1525	&& paLSPages)
1526	{
1527	if (!paLSPages[iPage].fDirty)
1528	continue;
1529	if (paLSPages[iPage].fWriteMonitoredJustNow)
1530	continue;
1531	if (paLSPages[iPage].fIgnore)
1532	continue;
1533	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM) /* in case of recent ramppings */
1534	continue;
1535	if ( PGM_PAGE_GET_STATE(&pCur->aPages[iPage])
1536	!= ( paLSPages[iPage].fZero
1537	? PGM_PAGE_STATE_ZERO
1538	: paLSPages[iPage].fShared
1539	? PGM_PAGE_STATE_SHARED
1540	: PGM_PAGE_STATE_WRITE_MONITORED))
1541	continue;
1542	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1543	continue;
1544	}
1545	else
1546	{
1547	if ( paLSPages
1548	&& !paLSPages[iPage].fDirty
1549	&& !paLSPages[iPage].fIgnore)
1550	{
1551	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1552	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1553	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1554	#endif
1555	continue;
1556	}
1557	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1558	continue;
1559	}
1560
1561	/*
1562	* Do the saving outside the PGM critsect since SSM may block on I/O.
1563	*/
1564	int rc;
1565	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1566	bool fZero = PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]);
1567
1568	if (!fZero)
1569	{
1570	/*
1571	* Copy the page and then save it outside the lock (since any
1572	* SSM call may block).
1573	*/
1574	uint8_t abPage[PAGE_SIZE];
1575	void const *pvPage;
1576	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1577	if (RT_SUCCESS(rc))
1578	{
1579	memcpy(abPage, pvPage, PAGE_SIZE);
1580	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1581	if (paLSPages)
1582	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage);
1583	#endif
1584	}
1585	pgmUnlock(pVM);
1586	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1587
1588	if (GCPhys == GCPhysLast + PAGE_SIZE)
1589	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1590	else
1591	{
1592	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1593	SSMR3PutGCPhys(pSSM, GCPhys);
1594	}
1595	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1596	}
1597	else
1598	{
1599	/*
1600	* Dirty zero page.
1601	*/
1602	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1603	if (paLSPages)
1604	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1605	#endif
1606	pgmUnlock(pVM);
1607
1608	if (GCPhys == GCPhysLast + PAGE_SIZE)
1609	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1610	else
1611	{
1612	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1613	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1614	}
1615	}
1616	if (RT_FAILURE(rc))
1617	return rc;
1618
1619	pgmLock(pVM);
1620	GCPhysLast = GCPhys;
1621	if (paLSPages)
1622	{
1623	paLSPages[iPage].fDirty = 0;
1624	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1625	if (fZero)
1626	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1627	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1628	pVM->pgm.s.LiveSave.cSavedPages++;
1629	}
1630	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1631	{
1632	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1633	break; /* restart */
1634	}
1635
1636	} /* for each page in range */
1637
1638	if (GCPhysCur != 0)
1639	break; /* Yield + ramrange change */
1640	GCPhysCur = pCur->GCPhysLast;
1641	}
1642	} /* for each range */
1643	} while (pCur);
1644	pgmUnlock(pVM);
1645
1646	return VINF_SUCCESS;
1647	}
1648
1649
1650	/**
1651	* Cleans up RAM pages after a live save.
1652	*
1653	* @param pVM The VM handle.
1654	*/
1655	static void pgmR3DoneRamPages(PVM pVM)
1656	{
1657	/*
1658	* Free the tracking arrays and disable write monitoring.
1659	*
1660	* Play nice with the PGM lock in case we're called while the VM is still
1661	* running. This means we have to delay the freeing since we wish to use
1662	* paLSPages as an indicator of which RAM ranges which we need to scan for
1663	* write monitored pages.
1664	*/
1665	void *pvToFree = NULL;
1666	PPGMRAMRANGE pCur;
1667	uint32_t cMonitoredPages = 0;
1668	pgmLock(pVM);
1669	do
1670	{
1671	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1672	{
1673	if (pCur->paLSPages)
1674	{
1675	if (pvToFree)
1676	{
1677	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1678	pgmUnlock(pVM);
1679	MMR3HeapFree(pvToFree);
1680	pvToFree = NULL;
1681	pgmLock(pVM);
1682	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1683	break; /* start over again. */
1684	}
1685
1686	pvToFree = pCur->paLSPages;
1687	pCur->paLSPages = NULL;
1688
1689	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1690	while (iPage--)
1691	{
1692	PPGMPAGE pPage = &pCur->aPages[iPage];
1693	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1694	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1695	{
1696	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1697	cMonitoredPages++;
1698	}
1699	}
1700	}
1701	}
1702	} while (pCur);
1703
1704	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1705	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1706	pVM->pgm.s.cMonitoredPages = 0;
1707	else
1708	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1709
1710	pgmUnlock(pVM);
1711
1712	MMR3HeapFree(pvToFree);
1713	pvToFree = NULL;
1714	}
1715
1716
1717	/**
1718	* Execute a live save pass.
1719	*
1720	* @returns VBox status code.
1721	*
1722	* @param pVM The VM handle.
1723	* @param pSSM The SSM handle.
1724	*/
1725	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1726	{
1727	int rc;
1728
1729	/*
1730	* Save the MMIO2 and ROM range IDs in pass 0.
1731	*/
1732	if (uPass == 0)
1733	{
1734	rc = pgmR3SaveRamConfig(pVM, pSSM);
1735	if (RT_FAILURE(rc))
1736	return rc;
1737	rc = pgmR3SaveRomRanges(pVM, pSSM);
1738	if (RT_FAILURE(rc))
1739	return rc;
1740	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1741	if (RT_FAILURE(rc))
1742	return rc;
1743	}
1744	/*
1745	* Reset the page-per-second estimate to avoid inflation by the initial
1746	* load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1747	*/
1748	else if (uPass == 7)
1749	{
1750	pVM->pgm.s.LiveSave.cSavedPages = 0;
1751	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1752	}
1753
1754	/*
1755	* Do the scanning.
1756	*/
1757	pgmR3ScanRomPages(pVM);
1758	pgmR3ScanMmio2Pages(pVM, uPass);
1759	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1760	pgmR3PoolClearAll(pVM); /** @todo this could perhaps be optimized a bit. */
1761
1762	/*
1763	* Save the pages.
1764	*/
1765	if (uPass == 0)
1766	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1767	else
1768	rc = VINF_SUCCESS;
1769	if (RT_SUCCESS(rc))
1770	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1771	if (RT_SUCCESS(rc))
1772	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1773	if (RT_SUCCESS(rc))
1774	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1775	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1776
1777	return rc;
1778	}
1779
1780
1781	/**
1782	* Votes on whether the live save phase is done or not.
1783	*
1784	* @returns VBox status code.
1785	*
1786	* @param pVM The VM handle.
1787	* @param pSSM The SSM handle.
1788	* @param uPass The data pass.
1789	*/
1790	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1791	{
1792	/*
1793	* Update and calculate parameters used in the decision making.
1794	*/
1795	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1796
1797	/* update history. */
1798	pgmLock(pVM);
1799	uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1800	pgmUnlock(pVM);
1801	uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1802	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1803	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1804	+ cWrittenToPages;
1805	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1806	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1807	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1808
1809	/* calc shortterm average (4 passes). */
1810	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1811	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1812	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1813	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1814	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1815	uint32_t const cDirtyPagesShort = cTotal / 4;
1816	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1817
1818	/* calc longterm average. */
1819	cTotal = 0;
1820	if (uPass < cHistoryEntries)
1821	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1822	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1823	else
1824	for (i = 0; i < cHistoryEntries; i++)
1825	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1826	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1827	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1828
1829	/* estimate the speed */
1830	uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1831	uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1832	/ ((long double)cNsElapsed / 1000000000.0) );
1833	pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1834
1835	/*
1836	* Try make a decision.
1837	*/
1838	if ( cDirtyPagesShort <= cDirtyPagesLong
1839	&& ( cDirtyNow <= cDirtyPagesShort
1840	\|\| cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1841	)
1842	)
1843	{
1844	if (uPass > 10)
1845	{
1846	uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1847	uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1848	uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1849	if (cMsMaxDowntime < 32)
1850	cMsMaxDowntime = 32;
1851	if ( ( cMsLeftLong <= cMsMaxDowntime
1852	&& cMsLeftShort < cMsMaxDowntime)
1853	\|\| cMsLeftShort < cMsMaxDowntime / 2
1854	)
1855	{
1856	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u\|%ums cDirtyPagesLong=%u\|%ums cMsMaxDowntime=%u\n",
1857	uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1858	return VINF_SUCCESS;
1859	}
1860	}
1861	else
1862	{
1863	if ( ( cDirtyPagesShort <= 128
1864	&& cDirtyPagesLong <= 1024)
1865	\|\| cDirtyPagesLong <= 256
1866	)
1867	{
1868	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1869	return VINF_SUCCESS;
1870	}
1871	}
1872	}
1873	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1874	}
1875
1876
1877	/**
1878	* Prepare for a live save operation.
1879	*
1880	* This will attempt to allocate and initialize the tracking structures. It
1881	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1882	* pgmR3SaveDone will do the cleanups.
1883	*
1884	* @returns VBox status code.
1885	*
1886	* @param pVM The VM handle.
1887	* @param pSSM The SSM handle.
1888	*/
1889	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1890	{
1891	/*
1892	* Indicate that we will be using the write monitoring.
1893	*/
1894	pgmLock(pVM);
1895	/** @todo find a way of mediating this when more users are added. */
1896	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1897	{
1898	pgmUnlock(pVM);
1899	AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1900	}
1901	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1902	pgmUnlock(pVM);
1903
1904	/*
1905	* Initialize the statistics.
1906	*/
1907	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1908	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1909	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1910	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1911	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1912	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1913	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1914	pVM->pgm.s.LiveSave.fActive = true;
1915	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
1916	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
1917	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
1918	pVM->pgm.s.LiveSave.cSavedPages = 0;
1919	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1920	pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
1921
1922	/*
1923	* Per page type.
1924	*/
1925	int rc = pgmR3PrepRomPages(pVM);
1926	if (RT_SUCCESS(rc))
1927	rc = pgmR3PrepMmio2Pages(pVM);
1928	if (RT_SUCCESS(rc))
1929	rc = pgmR3PrepRamPages(pVM);
1930	return rc;
1931	}
1932
1933
1934	/**
1935	* Execute state save operation.
1936	*
1937	* @returns VBox status code.
1938	* @param pVM VM Handle.
1939	* @param pSSM SSM operation handle.
1940	*/
1941	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1942	{
1943	int rc;
1944	unsigned i;
1945	PPGM pPGM = &pVM->pgm.s;
1946
1947	/*
1948	* Lock PGM and set the no-more-writes indicator.
1949	*/
1950	pgmLock(pVM);
1951	pVM->pgm.s.fNoMorePhysWrites = true;
1952
1953	/*
1954	* Save basic data (required / unaffected by relocation).
1955	*/
1956	bool const fMappingsFixed = pVM->pgm.s.fMappingsFixed;
1957	pVM->pgm.s.fMappingsFixed \|= pVM->pgm.s.fMappingsFixedRestored;
1958	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
1959	pVM->pgm.s.fMappingsFixed = fMappingsFixed;
1960
1961	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1962	SSMR3PutStruct(pSSM, &pVM->aCpus[idCpu].pgm.s, &s_aPGMCpuFields[0]);
1963
1964	/*
1965	* The guest mappings.
1966	*/
1967	i = 0;
1968	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1969	{
1970	SSMR3PutU32( pSSM, i);
1971	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1972	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
1973	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1974	}
1975	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
1976
1977	/*
1978	* Save the (remainder of the) memory.
1979	*/
1980	if (RT_SUCCESS(rc))
1981	{
1982	if (pVM->pgm.s.LiveSave.fActive)
1983	{
1984	pgmR3ScanRomPages(pVM);
1985	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
1986	pgmR3ScanRamPages(pVM, true /fFinalPass/);
1987
1988	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
1989	if (RT_SUCCESS(rc))
1990	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1991	if (RT_SUCCESS(rc))
1992	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1993	}
1994	else
1995	{
1996	rc = pgmR3SaveRamConfig(pVM, pSSM);
1997	if (RT_SUCCESS(rc))
1998	rc = pgmR3SaveRomRanges(pVM, pSSM);
1999	if (RT_SUCCESS(rc))
2000	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2001	if (RT_SUCCESS(rc))
2002	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
2003	if (RT_SUCCESS(rc))
2004	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
2005	if (RT_SUCCESS(rc))
2006	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2007	if (RT_SUCCESS(rc))
2008	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2009	}
2010	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2011	}
2012
2013	pgmUnlock(pVM);
2014	return rc;
2015	}
2016
2017
2018	/**
2019	* Cleans up after an save state operation.
2020	*
2021	* @returns VBox status code.
2022	* @param pVM VM Handle.
2023	* @param pSSM SSM operation handle.
2024	*/
2025	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2026	{
2027	/*
2028	* Do per page type cleanups first.
2029	*/
2030	if (pVM->pgm.s.LiveSave.fActive)
2031	{
2032	pgmR3DoneRomPages(pVM);
2033	pgmR3DoneMmio2Pages(pVM);
2034	pgmR3DoneRamPages(pVM);
2035	}
2036
2037	/*
2038	* Clear the live save indicator and disengage write monitoring.
2039	*/
2040	pgmLock(pVM);
2041	pVM->pgm.s.LiveSave.fActive = false;
2042	/** @todo this is blindly assuming that we're the only user of write
2043	* monitoring. Fix this when more users are added. */
2044	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2045	pgmUnlock(pVM);
2046
2047	return VINF_SUCCESS;
2048	}
2049
2050
2051	/**
2052	* Prepare state load operation.
2053	*
2054	* @returns VBox status code.
2055	* @param pVM VM Handle.
2056	* @param pSSM SSM operation handle.
2057	*/
2058	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2059	{
2060	/*
2061	* Call the reset function to make sure all the memory is cleared.
2062	*/
2063	PGMR3Reset(pVM);
2064	pVM->pgm.s.LiveSave.fActive = false;
2065	NOREF(pSSM);
2066	return VINF_SUCCESS;
2067	}
2068
2069
2070	/**
2071	* Load an ignored page.
2072	*
2073	* @returns VBox status code.
2074	* @param pSSM The saved state handle.
2075	*/
2076	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2077	{
2078	uint8_t abPage[PAGE_SIZE];
2079	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2080	}
2081
2082
2083	/**
2084	* Loads a page without any bits in the saved state, i.e. making sure it's
2085	* really zero.
2086	*
2087	* @returns VBox status code.
2088	* @param pVM The VM handle.
2089	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2090	* state).
2091	* @param pPage The guest page tracking structure.
2092	* @param GCPhys The page address.
2093	* @param pRam The ram range (logging).
2094	*/
2095	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2096	{
2097	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2098	&& uType != PGMPAGETYPE_INVALID)
2099	return VERR_SSM_UNEXPECTED_DATA;
2100
2101	/* I think this should be sufficient. */
2102	if (!PGM_PAGE_IS_ZERO(pPage))
2103	return VERR_SSM_UNEXPECTED_DATA;
2104
2105	NOREF(pVM);
2106	NOREF(GCPhys);
2107	NOREF(pRam);
2108	return VINF_SUCCESS;
2109	}
2110
2111
2112	/**
2113	* Loads a page from the saved state.
2114	*
2115	* @returns VBox status code.
2116	* @param pVM The VM handle.
2117	* @param pSSM The SSM handle.
2118	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2119	* state).
2120	* @param pPage The guest page tracking structure.
2121	* @param GCPhys The page address.
2122	* @param pRam The ram range (logging).
2123	*/
2124	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2125	{
2126	/*
2127	* Match up the type, dealing with MMIO2 aliases (dropped).
2128	*/
2129	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2130	\|\| uType == PGMPAGETYPE_INVALID,
2131	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2132	VERR_SSM_UNEXPECTED_DATA);
2133
2134	/*
2135	* Load the page.
2136	*/
2137	void *pvPage;
2138	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2139	if (RT_SUCCESS(rc))
2140	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2141
2142	return rc;
2143	}
2144
2145
2146	/**
2147	* Loads a page (counter part to pgmR3SavePage).
2148	*
2149	* @returns VBox status code, fully bitched errors.
2150	* @param pVM The VM handle.
2151	* @param pSSM The SSM handle.
2152	* @param uType The page type.
2153	* @param pPage The page.
2154	* @param GCPhys The page address.
2155	* @param pRam The RAM range (for error messages).
2156	*/
2157	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2158	{
2159	uint8_t uState;
2160	int rc = SSMR3GetU8(pSSM, &uState);
2161	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2162	if (uState == 0 /* zero */)
2163	rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2164	else if (uState == 1)
2165	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2166	else
2167	rc = VERR_INTERNAL_ERROR;
2168	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2169	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2170	rc);
2171	return VINF_SUCCESS;
2172	}
2173
2174
2175	/**
2176	* Loads a shadowed ROM page.
2177	*
2178	* @returns VBox status code, errors are fully bitched.
2179	* @param pVM The VM handle.
2180	* @param pSSM The saved state handle.
2181	* @param pPage The page.
2182	* @param GCPhys The page address.
2183	* @param pRam The RAM range (for error messages).
2184	*/
2185	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2186	{
2187	/*
2188	* Load and set the protection first, then load the two pages, the first
2189	* one is the active the other is the passive.
2190	*/
2191	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2192	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2193
2194	uint8_t uProt;
2195	int rc = SSMR3GetU8(pSSM, &uProt);
2196	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2197	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2198	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2199	&& enmProt < PGMROMPROT_END,
2200	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2201	VERR_SSM_UNEXPECTED_DATA);
2202
2203	if (pRomPage->enmProt != enmProt)
2204	{
2205	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2206	AssertLogRelRCReturn(rc, rc);
2207	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2208	}
2209
2210	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2211	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2212	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2213	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2214
2215	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2216	* used down the line (will the 2nd page will be written to the first
2217	* one because of a false TLB hit since the TLB is using GCPhys and
2218	* doesn't check the HCPhys of the desired page). */
2219	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2220	if (RT_SUCCESS(rc))
2221	{
2222	pPageActive = pPage;
2223	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2224	}
2225	return rc;
2226	}
2227
2228	/**
2229	* Ram range flags and bits for older versions of the saved state.
2230	*
2231	* @returns VBox status code.
2232	*
2233	* @param pVM The VM handle
2234	* @param pSSM The SSM handle.
2235	* @param uVersion The saved state version.
2236	*/
2237	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2238	{
2239	PPGM pPGM = &pVM->pgm.s;
2240
2241	/*
2242	* Ram range flags and bits.
2243	*/
2244	uint32_t i = 0;
2245	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2246	{
2247	/* Check the seqence number / separator. */
2248	uint32_t u32Sep;
2249	int rc = SSMR3GetU32(pSSM, &u32Sep);
2250	if (RT_FAILURE(rc))
2251	return rc;
2252	if (u32Sep == ~0U)
2253	break;
2254	if (u32Sep != i)
2255	{
2256	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2257	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2258	}
2259	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2260
2261	/* Get the range details. */
2262	RTGCPHYS GCPhys;
2263	SSMR3GetGCPhys(pSSM, &GCPhys);
2264	RTGCPHYS GCPhysLast;
2265	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2266	RTGCPHYS cb;
2267	SSMR3GetGCPhys(pSSM, &cb);
2268	uint8_t fHaveBits;
2269	rc = SSMR3GetU8(pSSM, &fHaveBits);
2270	if (RT_FAILURE(rc))
2271	return rc;
2272	if (fHaveBits & ~1)
2273	{
2274	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2275	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2276	}
2277	size_t cchDesc = 0;
2278	char szDesc[256];
2279	szDesc[0] = '\0';
2280	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2281	{
2282	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2283	if (RT_FAILURE(rc))
2284	return rc;
2285	/* Since we've modified the description strings in r45878, only compare
2286	them if the saved state is more recent. */
2287	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2288	cchDesc = strlen(szDesc);
2289	}
2290
2291	/*
2292	* Match it up with the current range.
2293	*
2294	* Note there is a hack for dealing with the high BIOS mapping
2295	* in the old saved state format, this means we might not have
2296	* a 1:1 match on success.
2297	*/
2298	if ( ( GCPhys != pRam->GCPhys
2299	\|\| GCPhysLast != pRam->GCPhysLast
2300	\|\| cb != pRam->cb
2301	\|\| ( cchDesc
2302	&& strcmp(szDesc, pRam->pszDesc)) )
2303	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2304	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2305	\|\| GCPhys != UINT32_C(0xfff80000)
2306	\|\| GCPhysLast != UINT32_C(0xffffffff)
2307	\|\| pRam->GCPhysLast != GCPhysLast
2308	\|\| pRam->GCPhys < GCPhys
2309	\|\| !fHaveBits)
2310	)
2311	{
2312	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2313	"State : %RGp-%RGp %RGp bytes %s %s\n",
2314	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2315	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2316	/*
2317	* If we're loading a state for debugging purpose, don't make a fuss if
2318	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2319	*/
2320	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2321	\|\| GCPhys < 8 * _1M)
2322	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2323	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2324	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2325	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2326
2327	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2328	continue;
2329	}
2330
2331	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2332	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2333	{
2334	/*
2335	* Load the pages one by one.
2336	*/
2337	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2338	{
2339	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2340	PPGMPAGE pPage = &pRam->aPages[iPage];
2341	uint8_t uType;
2342	rc = SSMR3GetU8(pSSM, &uType);
2343	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2344	if (uType == PGMPAGETYPE_ROM_SHADOW)
2345	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2346	else
2347	rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2348	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2349	}
2350	}
2351	else
2352	{
2353	/*
2354	* Old format.
2355	*/
2356
2357	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2358	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2359	uint32_t fFlags = 0;
2360	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2361	{
2362	uint16_t u16Flags;
2363	rc = SSMR3GetU16(pSSM, &u16Flags);
2364	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2365	fFlags \|= u16Flags;
2366	}
2367
2368	/* Load the bits */
2369	if ( !fHaveBits
2370	&& GCPhysLast < UINT32_C(0xe0000000))
2371	{
2372	/*
2373	* Dynamic chunks.
2374	*/
2375	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2376	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2377	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2378	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2379
2380	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2381	{
2382	uint8_t fPresent;
2383	rc = SSMR3GetU8(pSSM, &fPresent);
2384	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2385	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2386	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2387	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2388
2389	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2390	{
2391	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2392	PPGMPAGE pPage = &pRam->aPages[iPage];
2393	if (fPresent)
2394	{
2395	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2396	rc = pgmR3LoadPageToDevNullOld(pSSM);
2397	else
2398	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2399	}
2400	else
2401	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2402	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2403	}
2404	}
2405	}
2406	else if (pRam->pvR3)
2407	{
2408	/*
2409	* MMIO2.
2410	*/
2411	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2412	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2413	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2414	AssertLogRelMsgReturn(pRam->pvR3,
2415	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2416	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2417
2418	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2419	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2420	}
2421	else if (GCPhysLast < UINT32_C(0xfff80000))
2422	{
2423	/*
2424	* PCI MMIO, no pages saved.
2425	*/
2426	}
2427	else
2428	{
2429	/*
2430	* Load the 0xfff80000..0xffffffff BIOS range.
2431	* It starts with X reserved pages that we have to skip over since
2432	* the RAMRANGE create by the new code won't include those.
2433	*/
2434	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2435	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2436	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2437	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2438	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2439	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2440	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2441
2442	/* Skip wasted reserved pages before the ROM. */
2443	while (GCPhys < pRam->GCPhys)
2444	{
2445	rc = pgmR3LoadPageToDevNullOld(pSSM);
2446	GCPhys += PAGE_SIZE;
2447	}
2448
2449	/* Load the bios pages. */
2450	cPages = pRam->cb >> PAGE_SHIFT;
2451	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2452	{
2453	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2454	PPGMPAGE pPage = &pRam->aPages[iPage];
2455
2456	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2457	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2458	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2459	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2460	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2461	}
2462	}
2463	}
2464	}
2465
2466	return VINF_SUCCESS;
2467	}
2468
2469
2470	/**
2471	* Worker for pgmR3Load and pgmR3LoadLocked.
2472	*
2473	* @returns VBox status code.
2474	*
2475	* @param pVM The VM handle.
2476	* @param pSSM The SSM handle.
2477	* @param uVersion The saved state version.
2478	*
2479	* @todo This needs splitting up if more record types or code twists are
2480	* added...
2481	*/
2482	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2483	{
2484	/*
2485	* Process page records until we hit the terminator.
2486	*/
2487	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2488	PPGMRAMRANGE pRamHint = NULL;
2489	uint8_t id = UINT8_MAX;
2490	uint32_t iPage = UINT32_MAX - 10;
2491	PPGMROMRANGE pRom = NULL;
2492	PPGMMMIO2RANGE pMmio2 = NULL;
2493	for (;;)
2494	{
2495	/*
2496	* Get the record type and flags.
2497	*/
2498	uint8_t u8;
2499	int rc = SSMR3GetU8(pSSM, &u8);
2500	if (RT_FAILURE(rc))
2501	return rc;
2502	if (u8 == PGM_STATE_REC_END)
2503	return VINF_SUCCESS;
2504	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2505	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2506	{
2507	/*
2508	* RAM page.
2509	*/
2510	case PGM_STATE_REC_RAM_ZERO:
2511	case PGM_STATE_REC_RAM_RAW:
2512	{
2513	/*
2514	* Get the address and resolve it into a page descriptor.
2515	*/
2516	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2517	GCPhys += PAGE_SIZE;
2518	else
2519	{
2520	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2521	if (RT_FAILURE(rc))
2522	return rc;
2523	}
2524	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2525
2526	PPGMPAGE pPage;
2527	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2528	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2529
2530	/*
2531	* Take action according to the record type.
2532	*/
2533	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2534	{
2535	case PGM_STATE_REC_RAM_ZERO:
2536	{
2537	if (PGM_PAGE_IS_ZERO(pPage))
2538	break;
2539	/** @todo implement zero page replacing. */
2540	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2541	void *pvDstPage;
2542	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2543	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2544	ASMMemZeroPage(pvDstPage);
2545	break;
2546	}
2547
2548	case PGM_STATE_REC_RAM_RAW:
2549	{
2550	void *pvDstPage;
2551	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2552	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2553	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2554	if (RT_FAILURE(rc))
2555	return rc;
2556	break;
2557	}
2558
2559	default:
2560	AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2561	}
2562	id = UINT8_MAX;
2563	break;
2564	}
2565
2566	/*
2567	* MMIO2 page.
2568	*/
2569	case PGM_STATE_REC_MMIO2_RAW:
2570	case PGM_STATE_REC_MMIO2_ZERO:
2571	{
2572	/*
2573	* Get the ID + page number and resolved that into a MMIO2 page.
2574	*/
2575	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2576	iPage++;
2577	else
2578	{
2579	SSMR3GetU8(pSSM, &id);
2580	rc = SSMR3GetU32(pSSM, &iPage);
2581	if (RT_FAILURE(rc))
2582	return rc;
2583	}
2584	if ( !pMmio2
2585	\|\| pMmio2->idSavedState != id)
2586	{
2587	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2588	if (pMmio2->idSavedState == id)
2589	break;
2590	AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2591	}
2592	AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2593	void pvDstPage = (uint8_t )pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2594
2595	/*
2596	* Load the page bits.
2597	*/
2598	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2599	ASMMemZeroPage(pvDstPage);
2600	else
2601	{
2602	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2603	if (RT_FAILURE(rc))
2604	return rc;
2605	}
2606	GCPhys = NIL_RTGCPHYS;
2607	break;
2608	}
2609
2610	/*
2611	* ROM pages.
2612	*/
2613	case PGM_STATE_REC_ROM_VIRGIN:
2614	case PGM_STATE_REC_ROM_SHW_RAW:
2615	case PGM_STATE_REC_ROM_SHW_ZERO:
2616	case PGM_STATE_REC_ROM_PROT:
2617	{
2618	/*
2619	* Get the ID + page number and resolved that into a ROM page descriptor.
2620	*/
2621	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2622	iPage++;
2623	else
2624	{
2625	SSMR3GetU8(pSSM, &id);
2626	rc = SSMR3GetU32(pSSM, &iPage);
2627	if (RT_FAILURE(rc))
2628	return rc;
2629	}
2630	if ( !pRom
2631	\|\| pRom->idSavedState != id)
2632	{
2633	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2634	if (pRom->idSavedState == id)
2635	break;
2636	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2637	}
2638	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2639	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2640	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2641
2642	/*
2643	* Get and set the protection.
2644	*/
2645	uint8_t u8Prot;
2646	rc = SSMR3GetU8(pSSM, &u8Prot);
2647	if (RT_FAILURE(rc))
2648	return rc;
2649	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2650	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2651
2652	if (enmProt != pRomPage->enmProt)
2653	{
2654	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2655	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2656	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2657	GCPhys, enmProt, pRom->pszDesc);
2658	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2659	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2660	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2661	}
2662	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2663	break; /* done */
2664
2665	/*
2666	* Get the right page descriptor.
2667	*/
2668	PPGMPAGE pRealPage;
2669	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2670	{
2671	case PGM_STATE_REC_ROM_VIRGIN:
2672	if (!PGMROMPROT_IS_ROM(enmProt))
2673	pRealPage = &pRomPage->Virgin;
2674	else
2675	pRealPage = NULL;
2676	break;
2677
2678	case PGM_STATE_REC_ROM_SHW_RAW:
2679	case PGM_STATE_REC_ROM_SHW_ZERO:
2680	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2681	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2682	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2683	GCPhys, enmProt, pRom->pszDesc);
2684	if (PGMROMPROT_IS_ROM(enmProt))
2685	pRealPage = &pRomPage->Shadow;
2686	else
2687	pRealPage = NULL;
2688	break;
2689
2690	default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2691	}
2692	if (!pRealPage)
2693	{
2694	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2695	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2696	}
2697
2698	/*
2699	* Make it writable and map it (if necessary).
2700	*/
2701	void *pvDstPage = NULL;
2702	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2703	{
2704	case PGM_STATE_REC_ROM_SHW_ZERO:
2705	if (PGM_PAGE_IS_ZERO(pRealPage))
2706	break;
2707	/** @todo implement zero page replacing. */
2708	/* fall thru */
2709	case PGM_STATE_REC_ROM_VIRGIN:
2710	case PGM_STATE_REC_ROM_SHW_RAW:
2711	{
2712	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2713	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2714	break;
2715	}
2716	}
2717
2718	/*
2719	* Load the bits.
2720	*/
2721	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2722	{
2723	case PGM_STATE_REC_ROM_SHW_ZERO:
2724	if (pvDstPage)
2725	ASMMemZeroPage(pvDstPage);
2726	break;
2727
2728	case PGM_STATE_REC_ROM_VIRGIN:
2729	case PGM_STATE_REC_ROM_SHW_RAW:
2730	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2731	if (RT_FAILURE(rc))
2732	return rc;
2733	break;
2734	}
2735	GCPhys = NIL_RTGCPHYS;
2736	break;
2737	}
2738
2739	/*
2740	* Unknown type.
2741	*/
2742	default:
2743	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2744	}
2745	} /* forever */
2746	}
2747
2748
2749	/**
2750	* Worker for pgmR3Load.
2751	*
2752	* @returns VBox status code.
2753	*
2754	* @param pVM The VM handle.
2755	* @param pSSM The SSM handle.
2756	* @param uVersion The saved state version.
2757	*/
2758	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2759	{
2760	PPGM pPGM = &pVM->pgm.s;
2761	int rc;
2762	uint32_t u32Sep;
2763
2764	/*
2765	* Load basic data (required / unaffected by relocation).
2766	*/
2767	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2768	{
2769	if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2770	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2771	else
2772	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFieldsPreBalloon[0]);
2773
2774	AssertLogRelRCReturn(rc, rc);
2775
2776	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2777	{
2778	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2779	AssertLogRelRCReturn(rc, rc);
2780	}
2781	}
2782	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2783	{
2784	AssertRelease(pVM->cCpus == 1);
2785
2786	PGMOLD pgmOld;
2787	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2788	AssertLogRelRCReturn(rc, rc);
2789
2790	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2791	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2792	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2793
2794	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2795	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2796	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2797	}
2798	else
2799	{
2800	AssertRelease(pVM->cCpus == 1);
2801
2802	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2803	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2804	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2805
2806	uint32_t cbRamSizeIgnored;
2807	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2808	if (RT_FAILURE(rc))
2809	return rc;
2810	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2811
2812	uint32_t u32 = 0;
2813	SSMR3GetUInt(pSSM, &u32);
2814	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2815	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2816	RTUINT uGuestMode;
2817	SSMR3GetUInt(pSSM, &uGuestMode);
2818	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2819
2820	/* check separator. */
2821	SSMR3GetU32(pSSM, &u32Sep);
2822	if (RT_FAILURE(rc))
2823	return rc;
2824	if (u32Sep != (uint32_t)~0)
2825	{
2826	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2827	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2828	}
2829	}
2830
2831	/*
2832	* The guest mappings - skipped now, see re-fixation in the caller.
2833	*/
2834	uint32_t i = 0;
2835	for (;; i++)
2836	{
2837	rc = SSMR3GetU32(pSSM, &u32Sep); /* seqence number */
2838	if (RT_FAILURE(rc))
2839	return rc;
2840	if (u32Sep == ~0U)
2841	break;
2842	AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2843
2844	char szDesc[256];
2845	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2846	if (RT_FAILURE(rc))
2847	return rc;
2848	RTGCPTR GCPtrIgnore;
2849	SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
2850	rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
2851	if (RT_FAILURE(rc))
2852	return rc;
2853	}
2854
2855	/*
2856	* Load the RAM contents.
2857	*/
2858	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2859	{
2860	if (!pVM->pgm.s.LiveSave.fActive)
2861	{
2862	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2863	{
2864	rc = pgmR3LoadRamConfig(pVM, pSSM);
2865	if (RT_FAILURE(rc))
2866	return rc;
2867	}
2868	rc = pgmR3LoadRomRanges(pVM, pSSM);
2869	if (RT_FAILURE(rc))
2870	return rc;
2871	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2872	if (RT_FAILURE(rc))
2873	return rc;
2874	}
2875
2876	rc = pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2877	}
2878	else
2879	rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2880
2881	/* Refresh balloon accounting. */
2882	if (pVM->pgm.s.cBalloonedPages)
2883	{
2884	rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
2885	AssertRC(rc);
2886	}
2887	return rc;
2888	}
2889
2890
2891	/**
2892	* Execute state load operation.
2893	*
2894	* @returns VBox status code.
2895	* @param pVM VM Handle.
2896	* @param pSSM SSM operation handle.
2897	* @param uVersion Data layout version.
2898	* @param uPass The data pass.
2899	*/
2900	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2901	{
2902	int rc;
2903	PPGM pPGM = &pVM->pgm.s;
2904
2905	/*
2906	* Validate version.
2907	*/
2908	if ( ( uPass != SSM_PASS_FINAL
2909	&& uVersion != PGM_SAVED_STATE_VERSION
2910	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
2911	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2912	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
2913	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
2914	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
2915	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
2916	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
2917	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
2918	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2919	)
2920	{
2921	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
2922	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2923	}
2924
2925	/*
2926	* Do the loading while owning the lock because a bunch of the functions
2927	* we're using requires this.
2928	*/
2929	if (uPass != SSM_PASS_FINAL)
2930	{
2931	pgmLock(pVM);
2932	if (uPass != 0)
2933	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2934	else
2935	{
2936	pVM->pgm.s.LiveSave.fActive = true;
2937	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2938	rc = pgmR3LoadRamConfig(pVM, pSSM);
2939	else
2940	rc = VINF_SUCCESS;
2941	if (RT_SUCCESS(rc))
2942	rc = pgmR3LoadRomRanges(pVM, pSSM);
2943	if (RT_SUCCESS(rc))
2944	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2945	if (RT_SUCCESS(rc))
2946	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2947	}
2948	pgmUnlock(pVM);
2949	}
2950	else
2951	{
2952	pgmLock(pVM);
2953	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
2954	pVM->pgm.s.LiveSave.fActive = false;
2955	pgmUnlock(pVM);
2956	if (RT_SUCCESS(rc))
2957	{
2958	/*
2959	* We require a full resync now.
2960	*/
2961	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2962	{
2963	PVMCPU pVCpu = &pVM->aCpus[i];
2964	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2965	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2966	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2967	}
2968
2969	pgmR3HandlerPhysicalUpdateAll(pVM);
2970
2971	/*
2972	* Change the paging mode and restore PGMCPU::GCPhysCR3.
2973	* (The latter requires the CPUM state to be restored already.)
2974	*/
2975	if (CPUMR3IsStateRestorePending(pVM))
2976	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
2977	N_("PGM was unexpectedly restored before CPUM"));
2978
2979	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2980	{
2981	PVMCPU pVCpu = &pVM->aCpus[i];
2982
2983	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
2984	AssertLogRelRCReturn(rc, rc);
2985
2986	/* Restore pVM->pgm.s.GCPhysCR3. */
2987	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2988	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
2989	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
2990	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2991	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
2992	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2993	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2994	else
2995	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2996	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2997	}
2998
2999	/*
3000	* Try re-fixate the guest mappings.
3001	*/
3002	pVM->pgm.s.fMappingsFixedRestored = false;
3003	if ( pVM->pgm.s.fMappingsFixed
3004	&& pgmMapAreMappingsEnabled(&pVM->pgm.s))
3005	{
3006	RTGCPTR GCPtrFixed = pVM->pgm.s.GCPtrMappingFixed;
3007	uint32_t cbFixed = pVM->pgm.s.cbMappingFixed;
3008	pVM->pgm.s.fMappingsFixed = false;
3009
3010	uint32_t cbRequired;
3011	int rc2 = PGMR3MappingsSize(pVM, &cbRequired); AssertRC(rc2);
3012	if ( RT_SUCCESS(rc2)
3013	&& cbRequired > cbFixed)
3014	rc2 = VERR_OUT_OF_RANGE;
3015	if (RT_SUCCESS(rc2))
3016	rc2 = pgmR3MappingsFixInternal(pVM, GCPtrFixed, cbFixed);
3017	if (RT_FAILURE(rc2))
3018	{
3019	LogRel(("PGM: Unable to re-fixate the guest mappings at %RGv-%RGv: rc=%Rrc (cbRequired=%#x)\n",
3020	GCPtrFixed, GCPtrFixed + cbFixed, rc2, cbRequired));
3021	pVM->pgm.s.fMappingsFixed = false;
3022	pVM->pgm.s.fMappingsFixedRestored = true;
3023	pVM->pgm.s.GCPtrMappingFixed = GCPtrFixed;
3024	pVM->pgm.s.cbMappingFixed = cbFixed;
3025	}
3026	}
3027	else
3028	{
3029	/* We used to set fixed + disabled while we only use disabled now,
3030	so wipe the state to avoid any confusion. */
3031	pVM->pgm.s.fMappingsFixed = false;
3032	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
3033	pVM->pgm.s.cbMappingFixed = 0;
3034	}
3035
3036	/*
3037	* If we have floating mappings, do a CR3 sync now to make sure the HMA
3038	* doesn't conflict with guest code / data and thereby cause trouble
3039	* when restoring other components like PATM.
3040	*/
3041	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3042	{
3043	PVMCPU pVCpu = &pVM->aCpus[0];
3044	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
3045	if (RT_FAILURE(rc))
3046	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3047	N_("PGMSyncCR3 failed unexpectedly with rc=%Rrc"), rc);
3048
3049	/* Make sure to re-sync before executing code. */
3050	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3051	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3052	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3053	}
3054	}
3055	}
3056
3057	return rc;
3058	}
3059
3060
3061	/**
3062	* Registers the saved state callbacks with SSM.
3063	*
3064	* @returns VBox status code.
3065	* @param pVM Pointer to VM structure.
3066	* @param cbRam The RAM size.
3067	*/
3068	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3069	{
3070	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3071	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3072	NULL, pgmR3SaveExec, pgmR3SaveDone,
3073	pgmR3LoadPrep, pgmR3Load, NULL);
3074	}
3075

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source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 27436

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