PGMSavedState.cpp@ 27549

Last change on this file since 27549 was 27543, checked in by vboxsync, 15 years ago
Balloon updates; make ballooned pages as such
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1	/* $Id: PGMSavedState.cpp 27543 2010-03-19 15:47:14Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/pgm.h>
28	#include <VBox/stam.h>
29	#include <VBox/ssm.h>
30	#include <VBox/pdmdrv.h>
31	#include <VBox/pdmdev.h>
32	#include "PGMInternal.h"
33	#include <VBox/vm.h>
34	#include "PGMInline.h"
35
36	#include <VBox/param.h>
37	#include <VBox/err.h>
38
39	#include <iprt/asm.h>
40	#include <iprt/assert.h>
41	#include <iprt/crc32.h>
42	#include <iprt/mem.h>
43	#include <iprt/sha.h>
44	#include <iprt/string.h>
45	#include <iprt/thread.h>
46
47
48	/*******************************************************************************
49	* Defined Constants And Macros *
50	*******************************************************************************/
51	/** Saved state data unit version.
52	* @todo remove the guest mappings from the saved state at next version change! */
53	#define PGM_SAVED_STATE_VERSION 12
54	/** Saved state before the balloon change. */
55	#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
56	/** Saved state data unit version used during 3.1 development, misses the RAM
57	* config. */
58	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
59	/** Saved state data unit version for 3.0 (pre teleportation). */
60	#define PGM_SAVED_STATE_VERSION_3_0_0 9
61	/** Saved state data unit version for 2.2.2 and later. */
62	#define PGM_SAVED_STATE_VERSION_2_2_2 8
63	/** Saved state data unit version for 2.2.0. */
64	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
65	/** Saved state data unit version. */
66	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
67
68
69	/** @name Sparse state record types
70	* @{ */
71	/** Zero page. No data. */
72	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
73	/** Raw page. */
74	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
75	/** Raw MMIO2 page. */
76	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
77	/** Zero MMIO2 page. */
78	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
79	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
80	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
81	/** Raw shadowed ROM page. The protection (8-bit) preceeds the raw bits. */
82	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
83	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
84	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
85	/** ROM protection (8-bit). */
86	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
87	/** The last record type. */
88	#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
89	/** End marker. */
90	#define PGM_STATE_REC_END UINT8_C(0xff)
91	/** Flag indicating that the data is preceeded by the page address.
92	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
93	* range ID and a 32-bit page index.
94	*/
95	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
96	/** @} */
97
98	/** The CRC-32 for a zero page. */
99	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
100	/** The CRC-32 for a zero half page. */
101	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
102
103
104	/*******************************************************************************
105	* Structures and Typedefs *
106	*******************************************************************************/
107	/** For loading old saved states. (pre-smp) */
108	typedef struct
109	{
110	/** If set no conflict checks are required. (boolean) */
111	bool fMappingsFixed;
112	/** Size of fixed mapping */
113	uint32_t cbMappingFixed;
114	/** Base address (GC) of fixed mapping */
115	RTGCPTR GCPtrMappingFixed;
116	/** A20 gate mask.
117	* Our current approach to A20 emulation is to let REM do it and don't bother
118	* anywhere else. The interesting guests will be operating with it enabled anyway.
119	* But should the need arise, we'll subject physical addresses to this mask. */
120	RTGCPHYS GCPhysA20Mask;
121	/** A20 gate state - boolean! */
122	bool fA20Enabled;
123	/** The guest paging mode. */
124	PGMMODE enmGuestMode;
125	} PGMOLD;
126
127
128	/*******************************************************************************
129	* Global Variables *
130	*******************************************************************************/
131	/** PGM fields to save/load. */
132
133	static const SSMFIELD s_aPGMFields[] =
134	{
135	SSMFIELD_ENTRY( PGM, fMappingsFixed),
136	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
137	SSMFIELD_ENTRY( PGM, cbMappingFixed),
138	SSMFIELD_ENTRY( PGM, cBalloonedPages),
139	SSMFIELD_ENTRY_TERM()
140	};
141
142	static const SSMFIELD s_aPGMFieldsPreBalloon[] =
143	{
144	SSMFIELD_ENTRY( PGM, fMappingsFixed),
145	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
146	SSMFIELD_ENTRY( PGM, cbMappingFixed),
147	SSMFIELD_ENTRY_TERM()
148	};
149
150	static const SSMFIELD s_aPGMCpuFields[] =
151	{
152	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
153	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
154	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
155	SSMFIELD_ENTRY_TERM()
156	};
157
158	static const SSMFIELD s_aPGMFields_Old[] =
159	{
160	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
161	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
162	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
163	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
164	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
165	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
166	SSMFIELD_ENTRY_TERM()
167	};
168
169
170	/**
171	* Find the ROM tracking structure for the given page.
172	*
173	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
174	* that it's a ROM page.
175	* @param pVM The VM handle.
176	* @param GCPhys The address of the ROM page.
177	*/
178	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
179	{
180	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
181	pRomRange;
182	pRomRange = pRomRange->CTX_SUFF(pNext))
183	{
184	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
185	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
186	return &pRomRange->aPages[off >> PAGE_SHIFT];
187	}
188	return NULL;
189	}
190
191
192	/**
193	* Prepares the ROM pages for a live save.
194	*
195	* @returns VBox status code.
196	* @param pVM The VM handle.
197	*/
198	static int pgmR3PrepRomPages(PVM pVM)
199	{
200	/*
201	* Initialize the live save tracking in the ROM page descriptors.
202	*/
203	pgmLock(pVM);
204	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
205	{
206	PPGMRAMRANGE pRamHint = NULL;;
207	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
208
209	for (uint32_t iPage = 0; iPage < cPages; iPage++)
210	{
211	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
212	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
213	pRom->aPages[iPage].LiveSave.fDirty = true;
214	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
215	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
216	{
217	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
218	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
219	else
220	{
221	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
222	PPGMPAGE pPage;
223	int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
224	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
225	if (RT_SUCCESS(rc))
226	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage) && !PGM_PAGE_IS_BALLOONED(pPage);
227	else
228	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
229	}
230	}
231	}
232
233	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
234	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
235	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
236	}
237	pgmUnlock(pVM);
238
239	return VINF_SUCCESS;
240	}
241
242
243	/**
244	* Assigns IDs to the ROM ranges and saves them.
245	*
246	* @returns VBox status code.
247	* @param pVM The VM handle.
248	* @param pSSM Saved state handle.
249	*/
250	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
251	{
252	pgmLock(pVM);
253	uint8_t id = 1;
254	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
255	{
256	pRom->idSavedState = id;
257	SSMR3PutU8(pSSM, id);
258	SSMR3PutStrZ(pSSM, ""); /* device name */
259	SSMR3PutU32(pSSM, 0); /* device instance */
260	SSMR3PutU8(pSSM, 0); /* region */
261	SSMR3PutStrZ(pSSM, pRom->pszDesc);
262	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
263	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
264	if (RT_FAILURE(rc))
265	break;
266	}
267	pgmUnlock(pVM);
268	return SSMR3PutU8(pSSM, UINT8_MAX);
269	}
270
271
272	/**
273	* Loads the ROM range ID assignments.
274	*
275	* @returns VBox status code.
276	*
277	* @param pVM The VM handle.
278	* @param pSSM The saved state handle.
279	*/
280	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
281	{
282	Assert(PGMIsLockOwner(pVM));
283
284	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
285	pRom->idSavedState = UINT8_MAX;
286
287	for (;;)
288	{
289	/*
290	* Read the data.
291	*/
292	uint8_t id;
293	int rc = SSMR3GetU8(pSSM, &id);
294	if (RT_FAILURE(rc))
295	return rc;
296	if (id == UINT8_MAX)
297	{
298	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
299	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX, ("%s\n", pRom->pszDesc));
300	return VINF_SUCCESS; /* the end */
301	}
302	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
303
304	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
305	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
306	AssertLogRelRCReturn(rc, rc);
307
308	uint32_t uInstance;
309	SSMR3GetU32(pSSM, &uInstance);
310	uint8_t iRegion;
311	SSMR3GetU8(pSSM, &iRegion);
312
313	char szDesc[64];
314	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
315	AssertLogRelRCReturn(rc, rc);
316
317	RTGCPHYS GCPhys;
318	SSMR3GetGCPhys(pSSM, &GCPhys);
319	RTGCPHYS cb;
320	rc = SSMR3GetGCPhys(pSSM, &cb);
321	if (RT_FAILURE(rc))
322	return rc;
323	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
324	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
325
326	/*
327	* Locate a matching ROM range.
328	*/
329	AssertLogRelMsgReturn( uInstance == 0
330	&& iRegion == 0
331	&& szDevName[0] == '\0',
332	("GCPhys=%RGp %s\n", GCPhys, szDesc),
333	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
334	PPGMROMRANGE pRom;
335	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
336	{
337	if ( pRom->idSavedState == UINT8_MAX
338	&& !strcmp(pRom->pszDesc, szDesc))
339	{
340	pRom->idSavedState = id;
341	break;
342	}
343	}
344	if (!pRom)
345	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
346	} /* forever */
347	}
348
349
350	/**
351	* Scan ROM pages.
352	*
353	* @param pVM The VM handle.
354	*/
355	static void pgmR3ScanRomPages(PVM pVM)
356	{
357	/*
358	* The shadow ROMs.
359	*/
360	pgmLock(pVM);
361	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
362	{
363	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
364	{
365	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
366	for (uint32_t iPage = 0; iPage < cPages; iPage++)
367	{
368	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
369	if (pRomPage->LiveSave.fWrittenTo)
370	{
371	pRomPage->LiveSave.fWrittenTo = false;
372	if (!pRomPage->LiveSave.fDirty)
373	{
374	pRomPage->LiveSave.fDirty = true;
375	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
376	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
377	}
378	pRomPage->LiveSave.fDirtiedRecently = true;
379	}
380	else
381	pRomPage->LiveSave.fDirtiedRecently = false;
382	}
383	}
384	}
385	pgmUnlock(pVM);
386	}
387
388
389	/**
390	* Takes care of the virgin ROM pages in the first pass.
391	*
392	* This is an attempt at simplifying the handling of ROM pages a little bit.
393	* This ASSUMES that no new ROM ranges will be added and that they won't be
394	* relinked in any way.
395	*
396	* @param pVM The VM handle.
397	* @param pSSM The SSM handle.
398	* @param fLiveSave Whether we're in a live save or not.
399	*/
400	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
401	{
402	pgmLock(pVM);
403	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
404	{
405	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
406	for (uint32_t iPage = 0; iPage < cPages; iPage++)
407	{
408	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
409	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
410
411	/* Get the virgin page descriptor. */
412	PPGMPAGE pPage;
413	if (PGMROMPROT_IS_ROM(enmProt))
414	pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
415	else
416	pPage = &pRom->aPages[iPage].Virgin;
417
418	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
419	int rc = VINF_SUCCESS;
420	char abPage[PAGE_SIZE];
421	if ( !PGM_PAGE_IS_ZERO(pPage)
422	&& !PGM_PAGE_IS_BALLOONED(pPage))
423	{
424	void const *pvPage;
425	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
426	if (RT_SUCCESS(rc))
427	memcpy(abPage, pvPage, PAGE_SIZE);
428	}
429	else
430	ASMMemZeroPage(abPage);
431	pgmUnlock(pVM);
432	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
433
434	/* Save it. */
435	if (iPage > 0)
436	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
437	else
438	{
439	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
440	SSMR3PutU8(pSSM, pRom->idSavedState);
441	SSMR3PutU32(pSSM, iPage);
442	}
443	SSMR3PutU8(pSSM, (uint8_t)enmProt);
444	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
445	if (RT_FAILURE(rc))
446	return rc;
447
448	/* Update state. */
449	pgmLock(pVM);
450	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
451	if (fLiveSave)
452	{
453	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
454	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
455	pVM->pgm.s.LiveSave.cSavedPages++;
456	}
457	}
458	}
459	pgmUnlock(pVM);
460	return VINF_SUCCESS;
461	}
462
463
464	/**
465	* Saves dirty pages in the shadowed ROM ranges.
466	*
467	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
468	*
469	* @returns VBox status code.
470	* @param pVM The VM handle.
471	* @param pSSM The SSM handle.
472	* @param fLiveSave Whether it's a live save or not.
473	* @param fFinalPass Whether this is the final pass or not.
474	*/
475	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
476	{
477	/*
478	* The Shadowed ROMs.
479	*
480	* ASSUMES that the ROM ranges are fixed.
481	* ASSUMES that all the ROM ranges are mapped.
482	*/
483	pgmLock(pVM);
484	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
485	{
486	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
487	{
488	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
489	uint32_t iPrevPage = cPages;
490	for (uint32_t iPage = 0; iPage < cPages; iPage++)
491	{
492	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
493	if ( !fLiveSave
494	\|\| ( pRomPage->LiveSave.fDirty
495	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
496	&& !pRomPage->LiveSave.fWrittenTo)
497	\|\| fFinalPass
498	)
499	)
500	)
501	{
502	uint8_t abPage[PAGE_SIZE];
503	PGMROMPROT enmProt = pRomPage->enmProt;
504	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
505	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
506	bool fZero = PGM_PAGE_IS_ZERO(pPage) \|\| PGM_PAGE_IS_BALLOONED(pPage);
507	int rc = VINF_SUCCESS;
508	if (!fZero)
509	{
510	void const *pvPage;
511	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
512	if (RT_SUCCESS(rc))
513	memcpy(abPage, pvPage, PAGE_SIZE);
514	}
515	if (fLiveSave && RT_SUCCESS(rc))
516	{
517	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
518	pRomPage->LiveSave.fDirty = false;
519	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
520	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
521	pVM->pgm.s.LiveSave.cSavedPages++;
522	}
523	pgmUnlock(pVM);
524	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
525
526	if (iPage - 1U == iPrevPage && iPage > 0)
527	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
528	else
529	{
530	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
531	SSMR3PutU8(pSSM, pRom->idSavedState);
532	SSMR3PutU32(pSSM, iPage);
533	}
534	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
535	if (!fZero)
536	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
537	if (RT_FAILURE(rc))
538	return rc;
539
540	pgmLock(pVM);
541	iPrevPage = iPage;
542	}
543	/*
544	* In the final pass, make sure the protection is in sync.
545	*/
546	else if ( fFinalPass
547	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
548	{
549	PGMROMPROT enmProt = pRomPage->enmProt;
550	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
551	pgmUnlock(pVM);
552
553	if (iPage - 1U == iPrevPage && iPage > 0)
554	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
555	else
556	{
557	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
558	SSMR3PutU8(pSSM, pRom->idSavedState);
559	SSMR3PutU32(pSSM, iPage);
560	}
561	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
562	if (RT_FAILURE(rc))
563	return rc;
564
565	pgmLock(pVM);
566	iPrevPage = iPage;
567	}
568	}
569	}
570	}
571	pgmUnlock(pVM);
572	return VINF_SUCCESS;
573	}
574
575
576	/**
577	* Cleans up ROM pages after a live save.
578	*
579	* @param pVM The VM handle.
580	*/
581	static void pgmR3DoneRomPages(PVM pVM)
582	{
583	NOREF(pVM);
584	}
585
586
587	/**
588	* Prepares the MMIO2 pages for a live save.
589	*
590	* @returns VBox status code.
591	* @param pVM The VM handle.
592	*/
593	static int pgmR3PrepMmio2Pages(PVM pVM)
594	{
595	/*
596	* Initialize the live save tracking in the MMIO2 ranges.
597	* ASSUME nothing changes here.
598	*/
599	pgmLock(pVM);
600	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
601	{
602	uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
603	pgmUnlock(pVM);
604
605	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
606	if (!paLSPages)
607	return VERR_NO_MEMORY;
608	for (uint32_t iPage = 0; iPage < cPages; iPage++)
609	{
610	/* Initialize it as a dirty zero page. */
611	paLSPages[iPage].fDirty = true;
612	paLSPages[iPage].cUnchangedScans = 0;
613	paLSPages[iPage].fZero = true;
614	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
615	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
616	}
617
618	pgmLock(pVM);
619	pMmio2->paLSPages = paLSPages;
620	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
621	}
622	pgmUnlock(pVM);
623	return VINF_SUCCESS;
624	}
625
626
627	/**
628	* Assigns IDs to the MMIO2 ranges and saves them.
629	*
630	* @returns VBox status code.
631	* @param pVM The VM handle.
632	* @param pSSM Saved state handle.
633	*/
634	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
635	{
636	pgmLock(pVM);
637	uint8_t id = 1;
638	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
639	{
640	pMmio2->idSavedState = id;
641	SSMR3PutU8(pSSM, id);
642	SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pReg->szName);
643	SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
644	SSMR3PutU8(pSSM, pMmio2->iRegion);
645	SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
646	int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
647	if (RT_FAILURE(rc))
648	break;
649	}
650	pgmUnlock(pVM);
651	return SSMR3PutU8(pSSM, UINT8_MAX);
652	}
653
654
655	/**
656	* Loads the MMIO2 range ID assignments.
657	*
658	* @returns VBox status code.
659	*
660	* @param pVM The VM handle.
661	* @param pSSM The saved state handle.
662	*/
663	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
664	{
665	Assert(PGMIsLockOwner(pVM));
666
667	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
668	pMmio2->idSavedState = UINT8_MAX;
669
670	for (;;)
671	{
672	/*
673	* Read the data.
674	*/
675	uint8_t id;
676	int rc = SSMR3GetU8(pSSM, &id);
677	if (RT_FAILURE(rc))
678	return rc;
679	if (id == UINT8_MAX)
680	{
681	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
682	AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
683	return VINF_SUCCESS; /* the end */
684	}
685	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
686
687	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
688	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
689	AssertLogRelRCReturn(rc, rc);
690
691	uint32_t uInstance;
692	SSMR3GetU32(pSSM, &uInstance);
693	uint8_t iRegion;
694	SSMR3GetU8(pSSM, &iRegion);
695
696	char szDesc[64];
697	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
698	AssertLogRelRCReturn(rc, rc);
699
700	RTGCPHYS cb;
701	rc = SSMR3GetGCPhys(pSSM, &cb);
702	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
703
704	/*
705	* Locate a matching MMIO2 range.
706	*/
707	PPGMMMIO2RANGE pMmio2;
708	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
709	{
710	if ( pMmio2->idSavedState == UINT8_MAX
711	&& pMmio2->iRegion == iRegion
712	&& pMmio2->pDevInsR3->iInstance == uInstance
713	&& !strcmp(pMmio2->pDevInsR3->pReg->szName, szDevName))
714	{
715	pMmio2->idSavedState = id;
716	break;
717	}
718	}
719	if (!pMmio2)
720	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
721	szDesc, szDevName, uInstance, iRegion);
722
723	/*
724	* Validate the configuration, the size of the MMIO2 region should be
725	* the same.
726	*/
727	if (cb != pMmio2->RamRange.cb)
728	{
729	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
730	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
731	if (cb > pMmio2->RamRange.cb) /* bad idea? */
732	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
733	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
734	}
735	} /* forever */
736	}
737
738
739	/**
740	* Scans one MMIO2 page.
741	*
742	* @returns True if changed, false if unchanged.
743	*
744	* @param pVM The VM handle
745	* @param pbPage The page bits.
746	* @param pLSPage The live save tracking structure for the page.
747	*
748	*/
749	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
750	{
751	/*
752	* Special handling of zero pages.
753	*/
754	bool const fZero = pLSPage->fZero;
755	if (fZero)
756	{
757	if (ASMMemIsZeroPage(pbPage))
758	{
759	/* Not modified. */
760	if (pLSPage->fDirty)
761	pLSPage->cUnchangedScans++;
762	return false;
763	}
764
765	pLSPage->fZero = false;
766	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
767	}
768	else
769	{
770	/*
771	* CRC the first half, if it doesn't match the page is dirty and
772	* we won't check the 2nd half (we'll do that next time).
773	*/
774	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
775	if (u32CrcH1 == pLSPage->u32CrcH1)
776	{
777	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
778	if (u32CrcH2 == pLSPage->u32CrcH2)
779	{
780	/* Probably not modified. */
781	if (pLSPage->fDirty)
782	pLSPage->cUnchangedScans++;
783	return false;
784	}
785
786	pLSPage->u32CrcH2 = u32CrcH2;
787	}
788	else
789	{
790	pLSPage->u32CrcH1 = u32CrcH1;
791	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
792	&& ASMMemIsZeroPage(pbPage))
793	{
794	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
795	pLSPage->fZero = true;
796	}
797	}
798	}
799
800	/* dirty page path */
801	pLSPage->cUnchangedScans = 0;
802	if (!pLSPage->fDirty)
803	{
804	pLSPage->fDirty = true;
805	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
806	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
807	if (fZero)
808	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
809	}
810	return true;
811	}
812
813
814	/**
815	* Scan for MMIO2 page modifications.
816	*
817	* @param pVM The VM handle.
818	* @param uPass The pass number.
819	*/
820	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
821	{
822	/*
823	* Since this is a bit expensive we lower the scan rate after a little while.
824	*/
825	if ( ( (uPass & 3) != 0
826	&& uPass > 10)
827	\|\| uPass == SSM_PASS_FINAL)
828	return;
829
830	pgmLock(pVM); /* paranoia */
831	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
832	{
833	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
834	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
835	pgmUnlock(pVM);
836
837	for (uint32_t iPage = 0; iPage < cPages; iPage++)
838	{
839	uint8_t const pbPage = (uint8_t const )pMmio2->pvR3 + iPage * PAGE_SIZE;
840	pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
841	}
842
843	pgmLock(pVM);
844	}
845	pgmUnlock(pVM);
846
847	}
848
849
850	/**
851	* Save quiescent MMIO2 pages.
852	*
853	* @returns VBox status code.
854	* @param pVM The VM handle.
855	* @param pSSM The SSM handle.
856	* @param fLiveSave Whether it's a live save or not.
857	* @param uPass The pass number.
858	*/
859	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
860	{
861	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
862	* device that we wish to know about changes.) */
863
864	int rc = VINF_SUCCESS;
865	if (uPass == SSM_PASS_FINAL)
866	{
867	/*
868	* The mop up round.
869	*/
870	pgmLock(pVM);
871	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
872	pMmio2 && RT_SUCCESS(rc);
873	pMmio2 = pMmio2->pNextR3)
874	{
875	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
876	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
877	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
878	uint32_t iPageLast = cPages;
879	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
880	{
881	uint8_t u8Type;
882	if (!fLiveSave)
883	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
884	else
885	{
886	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
887	if ( !paLSPages[iPage].fDirty
888	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
889	{
890	if (paLSPages[iPage].fZero)
891	continue;
892
893	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
894	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
895	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
896	continue;
897	}
898	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
899	pVM->pgm.s.LiveSave.cSavedPages++;
900	}
901
902	if (iPage != 0 && iPage == iPageLast + 1)
903	rc = SSMR3PutU8(pSSM, u8Type);
904	else
905	{
906	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
907	SSMR3PutU8(pSSM, pMmio2->idSavedState);
908	rc = SSMR3PutU32(pSSM, iPage);
909	}
910	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
911	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
912	if (RT_FAILURE(rc))
913	break;
914	iPageLast = iPage;
915	}
916	}
917	pgmUnlock(pVM);
918	}
919	/*
920	* Reduce the rate after a little while since the current MMIO2 approach is
921	* a bit expensive.
922	* We position it two passes after the scan pass to avoid saving busy pages.
923	*/
924	else if ( uPass <= 10
925	\|\| (uPass & 3) == 2)
926	{
927	pgmLock(pVM);
928	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
929	pMmio2 && RT_SUCCESS(rc);
930	pMmio2 = pMmio2->pNextR3)
931	{
932	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
933	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
934	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
935	uint32_t iPageLast = cPages;
936	pgmUnlock(pVM);
937
938	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
939	{
940	/* Skip clean pages and pages which hasn't quiesced. */
941	if (!paLSPages[iPage].fDirty)
942	continue;
943	if (paLSPages[iPage].cUnchangedScans < 3)
944	continue;
945	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
946	continue;
947
948	/* Save it. */
949	bool const fZero = paLSPages[iPage].fZero;
950	uint8_t abPage[PAGE_SIZE];
951	if (!fZero)
952	{
953	memcpy(abPage, pbPage, PAGE_SIZE);
954	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
955	}
956
957	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
958	if (iPage != 0 && iPage == iPageLast + 1)
959	rc = SSMR3PutU8(pSSM, u8Type);
960	else
961	{
962	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
963	SSMR3PutU8(pSSM, pMmio2->idSavedState);
964	rc = SSMR3PutU32(pSSM, iPage);
965	}
966	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
967	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
968	if (RT_FAILURE(rc))
969	break;
970
971	/* Housekeeping. */
972	paLSPages[iPage].fDirty = false;
973	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
974	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
975	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
976	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
977	pVM->pgm.s.LiveSave.cSavedPages++;
978	iPageLast = iPage;
979	}
980
981	pgmLock(pVM);
982	}
983	pgmUnlock(pVM);
984	}
985
986	return rc;
987	}
988
989
990	/**
991	* Cleans up MMIO2 pages after a live save.
992	*
993	* @param pVM The VM handle.
994	*/
995	static void pgmR3DoneMmio2Pages(PVM pVM)
996	{
997	/*
998	* Free the tracking structures for the MMIO2 pages.
999	* We do the freeing outside the lock in case the VM is running.
1000	*/
1001	pgmLock(pVM);
1002	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
1003	{
1004	void *pvMmio2ToFree = pMmio2->paLSPages;
1005	if (pvMmio2ToFree)
1006	{
1007	pMmio2->paLSPages = NULL;
1008	pgmUnlock(pVM);
1009	MMR3HeapFree(pvMmio2ToFree);
1010	pgmLock(pVM);
1011	}
1012	}
1013	pgmUnlock(pVM);
1014	}
1015
1016
1017	/**
1018	* Prepares the RAM pages for a live save.
1019	*
1020	* @returns VBox status code.
1021	* @param pVM The VM handle.
1022	*/
1023	static int pgmR3PrepRamPages(PVM pVM)
1024	{
1025
1026	/*
1027	* Try allocating tracking structures for the ram ranges.
1028	*
1029	* To avoid lock contention, we leave the lock every time we're allocating
1030	* a new array. This means we'll have to ditch the allocation and start
1031	* all over again if the RAM range list changes in-between.
1032	*
1033	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1034	* for cleaning up.
1035	*/
1036	PPGMRAMRANGE pCur;
1037	pgmLock(pVM);
1038	do
1039	{
1040	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1041	{
1042	if ( !pCur->paLSPages
1043	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1044	{
1045	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1046	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1047	pgmUnlock(pVM);
1048	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1049	if (!paLSPages)
1050	return VERR_NO_MEMORY;
1051	pgmLock(pVM);
1052	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1053	{
1054	pgmUnlock(pVM);
1055	MMR3HeapFree(paLSPages);
1056	pgmLock(pVM);
1057	break; /* try again */
1058	}
1059	pCur->paLSPages = paLSPages;
1060
1061	/*
1062	* Initialize the array.
1063	*/
1064	uint32_t iPage = cPages;
1065	while (iPage-- > 0)
1066	{
1067	/** @todo yield critsect! (after moving this away from EMT0) */
1068	PCPGMPAGE pPage = &pCur->aPages[iPage];
1069	paLSPages[iPage].cDirtied = 0;
1070	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1071	paLSPages[iPage].fWriteMonitored = 0;
1072	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1073	paLSPages[iPage].u2Reserved = 0;
1074	switch (PGM_PAGE_GET_TYPE(pPage))
1075	{
1076	case PGMPAGETYPE_RAM:
1077	if ( PGM_PAGE_IS_ZERO(pPage)
1078	\|\| PGM_PAGE_IS_BALLOONED(pPage))
1079	{
1080	paLSPages[iPage].fZero = 1;
1081	paLSPages[iPage].fShared = 0;
1082	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1083	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1084	#endif
1085	}
1086	else if (PGM_PAGE_IS_SHARED(pPage))
1087	{
1088	paLSPages[iPage].fZero = 0;
1089	paLSPages[iPage].fShared = 1;
1090	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1091	paLSPages[iPage].u32Crc = UINT32_MAX;
1092	#endif
1093	}
1094	else
1095	{
1096	paLSPages[iPage].fZero = 0;
1097	paLSPages[iPage].fShared = 0;
1098	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1099	paLSPages[iPage].u32Crc = UINT32_MAX;
1100	#endif
1101	}
1102	paLSPages[iPage].fIgnore = 0;
1103	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1104	break;
1105
1106	case PGMPAGETYPE_ROM_SHADOW:
1107	case PGMPAGETYPE_ROM:
1108	{
1109	paLSPages[iPage].fZero = 0;
1110	paLSPages[iPage].fShared = 0;
1111	paLSPages[iPage].fDirty = 0;
1112	paLSPages[iPage].fIgnore = 1;
1113	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1114	paLSPages[iPage].u32Crc = UINT32_MAX;
1115	#endif
1116	pVM->pgm.s.LiveSave.cIgnoredPages++;
1117	break;
1118	}
1119
1120	default:
1121	AssertMsgFailed(("%R[pgmpage]", pPage));
1122	case PGMPAGETYPE_MMIO2:
1123	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1124	paLSPages[iPage].fZero = 0;
1125	paLSPages[iPage].fShared = 0;
1126	paLSPages[iPage].fDirty = 0;
1127	paLSPages[iPage].fIgnore = 1;
1128	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1129	paLSPages[iPage].u32Crc = UINT32_MAX;
1130	#endif
1131	pVM->pgm.s.LiveSave.cIgnoredPages++;
1132	break;
1133
1134	case PGMPAGETYPE_MMIO:
1135	paLSPages[iPage].fZero = 0;
1136	paLSPages[iPage].fShared = 0;
1137	paLSPages[iPage].fDirty = 0;
1138	paLSPages[iPage].fIgnore = 1;
1139	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1140	paLSPages[iPage].u32Crc = UINT32_MAX;
1141	#endif
1142	pVM->pgm.s.LiveSave.cIgnoredPages++;
1143	break;
1144	}
1145	}
1146	}
1147	}
1148	} while (pCur);
1149	pgmUnlock(pVM);
1150
1151	return VINF_SUCCESS;
1152	}
1153
1154
1155	/**
1156	* Saves the RAM configuration.
1157	*
1158	* @returns VBox status code.
1159	* @param pVM The VM handle.
1160	* @param pSSM The saved state handle.
1161	*/
1162	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1163	{
1164	uint32_t cbRamHole = 0;
1165	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1166	AssertRCReturn(rc, rc);
1167
1168	uint64_t cbRam = 0;
1169	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1170	AssertRCReturn(rc, rc);
1171
1172	SSMR3PutU32(pSSM, cbRamHole);
1173	return SSMR3PutU64(pSSM, cbRam);
1174	}
1175
1176
1177	/**
1178	* Loads and verifies the RAM configuration.
1179	*
1180	* @returns VBox status code.
1181	* @param pVM The VM handle.
1182	* @param pSSM The saved state handle.
1183	*/
1184	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1185	{
1186	uint32_t cbRamHoleCfg = 0;
1187	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1188	AssertRCReturn(rc, rc);
1189
1190	uint64_t cbRamCfg = 0;
1191	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1192	AssertRCReturn(rc, rc);
1193
1194	uint32_t cbRamHoleSaved;
1195	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1196
1197	uint64_t cbRamSaved;
1198	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1199	AssertRCReturn(rc, rc);
1200
1201	if ( cbRamHoleCfg != cbRamHoleSaved
1202	\|\| cbRamCfg != cbRamSaved)
1203	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1204	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1205	return VINF_SUCCESS;
1206	}
1207
1208	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1209
1210	/**
1211	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1212	* info with it.
1213	*
1214	* @param pVM The VM handle.
1215	* @param pCur The current RAM range.
1216	* @param paLSPages The current array of live save page tracking
1217	* structures.
1218	* @param iPage The page index.
1219	*/
1220	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1221	{
1222	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1223	void const *pvPage;
1224	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1225	if (RT_SUCCESS(rc))
1226	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1227	else
1228	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1229	}
1230
1231
1232	/**
1233	* Verifies the CRC-32 for a page given it's raw bits.
1234	*
1235	* @param pvPage The page bits.
1236	* @param pCur The current RAM range.
1237	* @param paLSPages The current array of live save page tracking
1238	* structures.
1239	* @param iPage The page index.
1240	*/
1241	static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1242	{
1243	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1244	{
1245	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1246	Assert((!PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) && !PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage])) \|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1247	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1248	("%08x != %08x for %RGp %R[pgmpage]\n", paLSPages[iPage].u32Crc, u32Crc,
1249	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1250	}
1251	}
1252
1253
1254	/**
1255	* Verfies the CRC-32 for a RAM page.
1256	*
1257	* @param pVM The VM handle.
1258	* @param pCur The current RAM range.
1259	* @param paLSPages The current array of live save page tracking
1260	* structures.
1261	* @param iPage The page index.
1262	*/
1263	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1264	{
1265	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1266	{
1267	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1268	void const *pvPage;
1269	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1270	if (RT_SUCCESS(rc))
1271	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage);
1272	}
1273	}
1274
1275	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1276
1277	/**
1278	* Scan for RAM page modifications and reprotect them.
1279	*
1280	* @param pVM The VM handle.
1281	* @param fFinalPass Whether this is the final pass or not.
1282	*/
1283	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1284	{
1285	/*
1286	* The RAM.
1287	*/
1288	RTGCPHYS GCPhysCur = 0;
1289	PPGMRAMRANGE pCur;
1290	pgmLock(pVM);
1291	do
1292	{
1293	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1294	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1295	{
1296	if ( pCur->GCPhysLast > GCPhysCur
1297	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1298	{
1299	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1300	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1301	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1302	GCPhysCur = 0;
1303	for (; iPage < cPages; iPage++)
1304	{
1305	/* Do yield first. */
1306	if ( !fFinalPass
1307	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1308	&& (iPage & 0x7ff) == 0x100
1309	#endif
1310	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1311	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1312	{
1313	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1314	break; /* restart */
1315	}
1316
1317	/* Skip already ignored pages. */
1318	if (paLSPages[iPage].fIgnore)
1319	continue;
1320
1321	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1322	{
1323	/*
1324	* A RAM page.
1325	*/
1326	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1327	{
1328	case PGM_PAGE_STATE_ALLOCATED:
1329	/** @todo Optimize this: Don't always re-enable write
1330	* monitoring if the page is known to be very busy. */
1331	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1332	{
1333	Assert(paLSPages[iPage].fWriteMonitored);
1334	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1335	Assert(pVM->pgm.s.cWrittenToPages > 0);
1336	pVM->pgm.s.cWrittenToPages--;
1337	}
1338	else
1339	{
1340	Assert(!paLSPages[iPage].fWriteMonitored);
1341	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1342	}
1343
1344	if (!paLSPages[iPage].fDirty)
1345	{
1346	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1347	if (paLSPages[iPage].fZero)
1348	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1349	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1350	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1351	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1352	}
1353
1354	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1355	pVM->pgm.s.cMonitoredPages++;
1356	paLSPages[iPage].fWriteMonitored = 1;
1357	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1358	paLSPages[iPage].fDirty = 1;
1359	paLSPages[iPage].fZero = 0;
1360	paLSPages[iPage].fShared = 0;
1361	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1362	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1363	#endif
1364	break;
1365
1366	case PGM_PAGE_STATE_WRITE_MONITORED:
1367	Assert(paLSPages[iPage].fWriteMonitored);
1368	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1369	{
1370	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1371	if (paLSPages[iPage].fWriteMonitoredJustNow)
1372	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1373	else
1374	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1375	#endif
1376	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1377	}
1378	else
1379	{
1380	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1381	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1382	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1383	#endif
1384	if (!paLSPages[iPage].fDirty)
1385	{
1386	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1387	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1388	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1389	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1390	}
1391	}
1392	break;
1393
1394	case PGM_PAGE_STATE_ZERO:
1395	if (!paLSPages[iPage].fZero)
1396	{
1397	if (!paLSPages[iPage].fDirty)
1398	{
1399	paLSPages[iPage].fDirty = 1;
1400	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1401	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1402	}
1403	paLSPages[iPage].fZero = 1;
1404	paLSPages[iPage].fShared = 0;
1405	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1406	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1407	#endif
1408	}
1409	break;
1410
1411	case PGM_PAGE_STATE_BALLOONED:
1412	if (!paLSPages[iPage].fZero)
1413	{
1414	if (!paLSPages[iPage].fDirty)
1415	{
1416	paLSPages[iPage].fDirty = 1;
1417	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1418	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1419	}
1420	paLSPages[iPage].fZero = 1;
1421	paLSPages[iPage].fShared = 0;
1422	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1423	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1424	#endif
1425	}
1426	break;
1427
1428	case PGM_PAGE_STATE_SHARED:
1429	if (!paLSPages[iPage].fShared)
1430	{
1431	if (!paLSPages[iPage].fDirty)
1432	{
1433	paLSPages[iPage].fDirty = 1;
1434	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1435	if (paLSPages[iPage].fZero)
1436	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1437	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1438	}
1439	paLSPages[iPage].fZero = 0;
1440	paLSPages[iPage].fShared = 1;
1441	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1442	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1443	#endif
1444	}
1445	break;
1446	}
1447	}
1448	else
1449	{
1450	/*
1451	* All other types => Ignore the page.
1452	*/
1453	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1454	paLSPages[iPage].fIgnore = 1;
1455	if (paLSPages[iPage].fWriteMonitored)
1456	{
1457	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1458	* pages! */
1459	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1460	{
1461	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1462	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1463	Assert(pVM->pgm.s.cMonitoredPages > 0);
1464	pVM->pgm.s.cMonitoredPages--;
1465	}
1466	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1467	{
1468	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1469	Assert(pVM->pgm.s.cWrittenToPages > 0);
1470	pVM->pgm.s.cWrittenToPages--;
1471	}
1472	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1473	}
1474
1475	/** @todo the counting doesn't quite work out here. fix later? */
1476	if (paLSPages[iPage].fDirty)
1477	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1478	else
1479	{
1480	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1481	if (paLSPages[iPage].fZero)
1482	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1483	}
1484	pVM->pgm.s.LiveSave.cIgnoredPages++;
1485	}
1486	} /* for each page in range */
1487
1488	if (GCPhysCur != 0)
1489	break; /* Yield + ramrange change */
1490	GCPhysCur = pCur->GCPhysLast;
1491	}
1492	} /* for each range */
1493	} while (pCur);
1494	pgmUnlock(pVM);
1495	}
1496
1497
1498	/**
1499	* Save quiescent RAM pages.
1500	*
1501	* @returns VBox status code.
1502	* @param pVM The VM handle.
1503	* @param pSSM The SSM handle.
1504	* @param fLiveSave Whether it's a live save or not.
1505	* @param uPass The pass number.
1506	*/
1507	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1508	{
1509	/*
1510	* The RAM.
1511	*/
1512	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1513	RTGCPHYS GCPhysCur = 0;
1514	PPGMRAMRANGE pCur;
1515	pgmLock(pVM);
1516	do
1517	{
1518	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1519	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1520	{
1521	if ( pCur->GCPhysLast > GCPhysCur
1522	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1523	{
1524	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1525	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1526	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1527	GCPhysCur = 0;
1528	for (; iPage < cPages; iPage++)
1529	{
1530	/* Do yield first. */
1531	if ( uPass != SSM_PASS_FINAL
1532	&& (iPage & 0x7ff) == 0x100
1533	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1534	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1535	{
1536	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1537	break; /* restart */
1538	}
1539
1540	/*
1541	* Only save pages that haven't changed since last scan and are dirty.
1542	*/
1543	if ( uPass != SSM_PASS_FINAL
1544	&& paLSPages)
1545	{
1546	if (!paLSPages[iPage].fDirty)
1547	continue;
1548	if (paLSPages[iPage].fWriteMonitoredJustNow)
1549	continue;
1550	if (paLSPages[iPage].fIgnore)
1551	continue;
1552	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM) /* in case of recent ramppings */
1553	continue;
1554	if ( PGM_PAGE_GET_STATE(&pCur->aPages[iPage])
1555	!= ( paLSPages[iPage].fZero
1556	? PGM_PAGE_STATE_ZERO
1557	: paLSPages[iPage].fShared
1558	? PGM_PAGE_STATE_SHARED
1559	: PGM_PAGE_STATE_WRITE_MONITORED))
1560	continue;
1561	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1562	continue;
1563	}
1564	else
1565	{
1566	if ( paLSPages
1567	&& !paLSPages[iPage].fDirty
1568	&& !paLSPages[iPage].fIgnore)
1569	{
1570	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1571	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1572	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1573	#endif
1574	continue;
1575	}
1576	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1577	continue;
1578	}
1579
1580	/*
1581	* Do the saving outside the PGM critsect since SSM may block on I/O.
1582	*/
1583	int rc;
1584	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1585	bool fZero = PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) \|\| PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]);
1586
1587	if (!fZero)
1588	{
1589	/*
1590	* Copy the page and then save it outside the lock (since any
1591	* SSM call may block).
1592	*/
1593	uint8_t abPage[PAGE_SIZE];
1594	void const *pvPage;
1595	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1596	if (RT_SUCCESS(rc))
1597	{
1598	memcpy(abPage, pvPage, PAGE_SIZE);
1599	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1600	if (paLSPages)
1601	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage);
1602	#endif
1603	}
1604	pgmUnlock(pVM);
1605	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1606
1607	if (GCPhys == GCPhysLast + PAGE_SIZE)
1608	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1609	else
1610	{
1611	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1612	SSMR3PutGCPhys(pSSM, GCPhys);
1613	}
1614	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1615	}
1616	else
1617	{
1618	/*
1619	* Dirty zero page.
1620	*/
1621	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1622	if (paLSPages)
1623	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1624	#endif
1625	pgmUnlock(pVM);
1626
1627	if (GCPhys == GCPhysLast + PAGE_SIZE)
1628	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1629	else
1630	{
1631	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1632	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1633	}
1634	}
1635	if (RT_FAILURE(rc))
1636	return rc;
1637
1638	pgmLock(pVM);
1639	GCPhysLast = GCPhys;
1640	if (paLSPages)
1641	{
1642	paLSPages[iPage].fDirty = 0;
1643	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1644	if (fZero)
1645	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1646	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1647	pVM->pgm.s.LiveSave.cSavedPages++;
1648	}
1649	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1650	{
1651	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1652	break; /* restart */
1653	}
1654
1655	} /* for each page in range */
1656
1657	if (GCPhysCur != 0)
1658	break; /* Yield + ramrange change */
1659	GCPhysCur = pCur->GCPhysLast;
1660	}
1661	} /* for each range */
1662	} while (pCur);
1663	pgmUnlock(pVM);
1664
1665	return VINF_SUCCESS;
1666	}
1667
1668
1669	/**
1670	* Cleans up RAM pages after a live save.
1671	*
1672	* @param pVM The VM handle.
1673	*/
1674	static void pgmR3DoneRamPages(PVM pVM)
1675	{
1676	/*
1677	* Free the tracking arrays and disable write monitoring.
1678	*
1679	* Play nice with the PGM lock in case we're called while the VM is still
1680	* running. This means we have to delay the freeing since we wish to use
1681	* paLSPages as an indicator of which RAM ranges which we need to scan for
1682	* write monitored pages.
1683	*/
1684	void *pvToFree = NULL;
1685	PPGMRAMRANGE pCur;
1686	uint32_t cMonitoredPages = 0;
1687	pgmLock(pVM);
1688	do
1689	{
1690	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1691	{
1692	if (pCur->paLSPages)
1693	{
1694	if (pvToFree)
1695	{
1696	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1697	pgmUnlock(pVM);
1698	MMR3HeapFree(pvToFree);
1699	pvToFree = NULL;
1700	pgmLock(pVM);
1701	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1702	break; /* start over again. */
1703	}
1704
1705	pvToFree = pCur->paLSPages;
1706	pCur->paLSPages = NULL;
1707
1708	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1709	while (iPage--)
1710	{
1711	PPGMPAGE pPage = &pCur->aPages[iPage];
1712	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1713	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1714	{
1715	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1716	cMonitoredPages++;
1717	}
1718	}
1719	}
1720	}
1721	} while (pCur);
1722
1723	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1724	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1725	pVM->pgm.s.cMonitoredPages = 0;
1726	else
1727	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1728
1729	pgmUnlock(pVM);
1730
1731	MMR3HeapFree(pvToFree);
1732	pvToFree = NULL;
1733	}
1734
1735
1736	/**
1737	* Execute a live save pass.
1738	*
1739	* @returns VBox status code.
1740	*
1741	* @param pVM The VM handle.
1742	* @param pSSM The SSM handle.
1743	*/
1744	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1745	{
1746	int rc;
1747
1748	/*
1749	* Save the MMIO2 and ROM range IDs in pass 0.
1750	*/
1751	if (uPass == 0)
1752	{
1753	rc = pgmR3SaveRamConfig(pVM, pSSM);
1754	if (RT_FAILURE(rc))
1755	return rc;
1756	rc = pgmR3SaveRomRanges(pVM, pSSM);
1757	if (RT_FAILURE(rc))
1758	return rc;
1759	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1760	if (RT_FAILURE(rc))
1761	return rc;
1762	}
1763	/*
1764	* Reset the page-per-second estimate to avoid inflation by the initial
1765	* load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1766	*/
1767	else if (uPass == 7)
1768	{
1769	pVM->pgm.s.LiveSave.cSavedPages = 0;
1770	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1771	}
1772
1773	/*
1774	* Do the scanning.
1775	*/
1776	pgmR3ScanRomPages(pVM);
1777	pgmR3ScanMmio2Pages(pVM, uPass);
1778	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1779	pgmR3PoolClearAll(pVM); /** @todo this could perhaps be optimized a bit. */
1780
1781	/*
1782	* Save the pages.
1783	*/
1784	if (uPass == 0)
1785	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1786	else
1787	rc = VINF_SUCCESS;
1788	if (RT_SUCCESS(rc))
1789	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1790	if (RT_SUCCESS(rc))
1791	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1792	if (RT_SUCCESS(rc))
1793	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1794	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1795
1796	return rc;
1797	}
1798
1799
1800	/**
1801	* Votes on whether the live save phase is done or not.
1802	*
1803	* @returns VBox status code.
1804	*
1805	* @param pVM The VM handle.
1806	* @param pSSM The SSM handle.
1807	* @param uPass The data pass.
1808	*/
1809	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1810	{
1811	/*
1812	* Update and calculate parameters used in the decision making.
1813	*/
1814	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1815
1816	/* update history. */
1817	pgmLock(pVM);
1818	uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1819	pgmUnlock(pVM);
1820	uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1821	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1822	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1823	+ cWrittenToPages;
1824	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1825	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1826	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1827
1828	/* calc shortterm average (4 passes). */
1829	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1830	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1831	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1832	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1833	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1834	uint32_t const cDirtyPagesShort = cTotal / 4;
1835	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1836
1837	/* calc longterm average. */
1838	cTotal = 0;
1839	if (uPass < cHistoryEntries)
1840	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1841	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1842	else
1843	for (i = 0; i < cHistoryEntries; i++)
1844	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1845	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1846	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1847
1848	/* estimate the speed */
1849	uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1850	uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1851	/ ((long double)cNsElapsed / 1000000000.0) );
1852	pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1853
1854	/*
1855	* Try make a decision.
1856	*/
1857	if ( cDirtyPagesShort <= cDirtyPagesLong
1858	&& ( cDirtyNow <= cDirtyPagesShort
1859	\|\| cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1860	)
1861	)
1862	{
1863	if (uPass > 10)
1864	{
1865	uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1866	uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1867	uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1868	if (cMsMaxDowntime < 32)
1869	cMsMaxDowntime = 32;
1870	if ( ( cMsLeftLong <= cMsMaxDowntime
1871	&& cMsLeftShort < cMsMaxDowntime)
1872	\|\| cMsLeftShort < cMsMaxDowntime / 2
1873	)
1874	{
1875	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u\|%ums cDirtyPagesLong=%u\|%ums cMsMaxDowntime=%u\n",
1876	uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1877	return VINF_SUCCESS;
1878	}
1879	}
1880	else
1881	{
1882	if ( ( cDirtyPagesShort <= 128
1883	&& cDirtyPagesLong <= 1024)
1884	\|\| cDirtyPagesLong <= 256
1885	)
1886	{
1887	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1888	return VINF_SUCCESS;
1889	}
1890	}
1891	}
1892	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1893	}
1894
1895
1896	/**
1897	* Prepare for a live save operation.
1898	*
1899	* This will attempt to allocate and initialize the tracking structures. It
1900	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1901	* pgmR3SaveDone will do the cleanups.
1902	*
1903	* @returns VBox status code.
1904	*
1905	* @param pVM The VM handle.
1906	* @param pSSM The SSM handle.
1907	*/
1908	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1909	{
1910	/*
1911	* Indicate that we will be using the write monitoring.
1912	*/
1913	pgmLock(pVM);
1914	/** @todo find a way of mediating this when more users are added. */
1915	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1916	{
1917	pgmUnlock(pVM);
1918	AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1919	}
1920	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1921	pgmUnlock(pVM);
1922
1923	/*
1924	* Initialize the statistics.
1925	*/
1926	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1927	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1928	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1929	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1930	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1931	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1932	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1933	pVM->pgm.s.LiveSave.fActive = true;
1934	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
1935	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
1936	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
1937	pVM->pgm.s.LiveSave.cSavedPages = 0;
1938	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1939	pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
1940
1941	/*
1942	* Per page type.
1943	*/
1944	int rc = pgmR3PrepRomPages(pVM);
1945	if (RT_SUCCESS(rc))
1946	rc = pgmR3PrepMmio2Pages(pVM);
1947	if (RT_SUCCESS(rc))
1948	rc = pgmR3PrepRamPages(pVM);
1949	return rc;
1950	}
1951
1952
1953	/**
1954	* Execute state save operation.
1955	*
1956	* @returns VBox status code.
1957	* @param pVM VM Handle.
1958	* @param pSSM SSM operation handle.
1959	*/
1960	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1961	{
1962	int rc;
1963	unsigned i;
1964	PPGM pPGM = &pVM->pgm.s;
1965
1966	/*
1967	* Lock PGM and set the no-more-writes indicator.
1968	*/
1969	pgmLock(pVM);
1970	pVM->pgm.s.fNoMorePhysWrites = true;
1971
1972	/*
1973	* Save basic data (required / unaffected by relocation).
1974	*/
1975	bool const fMappingsFixed = pVM->pgm.s.fMappingsFixed;
1976	pVM->pgm.s.fMappingsFixed \|= pVM->pgm.s.fMappingsFixedRestored;
1977	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
1978	pVM->pgm.s.fMappingsFixed = fMappingsFixed;
1979
1980	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1981	SSMR3PutStruct(pSSM, &pVM->aCpus[idCpu].pgm.s, &s_aPGMCpuFields[0]);
1982
1983	/*
1984	* The guest mappings.
1985	*/
1986	i = 0;
1987	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1988	{
1989	SSMR3PutU32( pSSM, i);
1990	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1991	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
1992	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1993	}
1994	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
1995
1996	/*
1997	* Save the (remainder of the) memory.
1998	*/
1999	if (RT_SUCCESS(rc))
2000	{
2001	if (pVM->pgm.s.LiveSave.fActive)
2002	{
2003	pgmR3ScanRomPages(pVM);
2004	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
2005	pgmR3ScanRamPages(pVM, true /fFinalPass/);
2006
2007	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
2008	if (RT_SUCCESS(rc))
2009	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2010	if (RT_SUCCESS(rc))
2011	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2012	}
2013	else
2014	{
2015	rc = pgmR3SaveRamConfig(pVM, pSSM);
2016	if (RT_SUCCESS(rc))
2017	rc = pgmR3SaveRomRanges(pVM, pSSM);
2018	if (RT_SUCCESS(rc))
2019	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2020	if (RT_SUCCESS(rc))
2021	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
2022	if (RT_SUCCESS(rc))
2023	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
2024	if (RT_SUCCESS(rc))
2025	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2026	if (RT_SUCCESS(rc))
2027	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2028	}
2029	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2030	}
2031
2032	pgmUnlock(pVM);
2033	return rc;
2034	}
2035
2036
2037	/**
2038	* Cleans up after an save state operation.
2039	*
2040	* @returns VBox status code.
2041	* @param pVM VM Handle.
2042	* @param pSSM SSM operation handle.
2043	*/
2044	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2045	{
2046	/*
2047	* Do per page type cleanups first.
2048	*/
2049	if (pVM->pgm.s.LiveSave.fActive)
2050	{
2051	pgmR3DoneRomPages(pVM);
2052	pgmR3DoneMmio2Pages(pVM);
2053	pgmR3DoneRamPages(pVM);
2054	}
2055
2056	/*
2057	* Clear the live save indicator and disengage write monitoring.
2058	*/
2059	pgmLock(pVM);
2060	pVM->pgm.s.LiveSave.fActive = false;
2061	/** @todo this is blindly assuming that we're the only user of write
2062	* monitoring. Fix this when more users are added. */
2063	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2064	pgmUnlock(pVM);
2065
2066	return VINF_SUCCESS;
2067	}
2068
2069
2070	/**
2071	* Prepare state load operation.
2072	*
2073	* @returns VBox status code.
2074	* @param pVM VM Handle.
2075	* @param pSSM SSM operation handle.
2076	*/
2077	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2078	{
2079	/*
2080	* Call the reset function to make sure all the memory is cleared.
2081	*/
2082	PGMR3Reset(pVM);
2083	pVM->pgm.s.LiveSave.fActive = false;
2084	NOREF(pSSM);
2085	return VINF_SUCCESS;
2086	}
2087
2088
2089	/**
2090	* Load an ignored page.
2091	*
2092	* @returns VBox status code.
2093	* @param pSSM The saved state handle.
2094	*/
2095	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2096	{
2097	uint8_t abPage[PAGE_SIZE];
2098	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2099	}
2100
2101
2102	/**
2103	* Loads a page without any bits in the saved state, i.e. making sure it's
2104	* really zero.
2105	*
2106	* @returns VBox status code.
2107	* @param pVM The VM handle.
2108	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2109	* state).
2110	* @param pPage The guest page tracking structure.
2111	* @param GCPhys The page address.
2112	* @param pRam The ram range (logging).
2113	*/
2114	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2115	{
2116	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2117	&& uType != PGMPAGETYPE_INVALID)
2118	return VERR_SSM_UNEXPECTED_DATA;
2119
2120	/* I think this should be sufficient. */
2121	if ( !PGM_PAGE_IS_ZERO(pPage)
2122	&& !PGM_PAGE_IS_BALLOONED(pPage))
2123	return VERR_SSM_UNEXPECTED_DATA;
2124
2125	NOREF(pVM);
2126	NOREF(GCPhys);
2127	NOREF(pRam);
2128	return VINF_SUCCESS;
2129	}
2130
2131
2132	/**
2133	* Loads a page from the saved state.
2134	*
2135	* @returns VBox status code.
2136	* @param pVM The VM handle.
2137	* @param pSSM The SSM handle.
2138	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2139	* state).
2140	* @param pPage The guest page tracking structure.
2141	* @param GCPhys The page address.
2142	* @param pRam The ram range (logging).
2143	*/
2144	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2145	{
2146	/*
2147	* Match up the type, dealing with MMIO2 aliases (dropped).
2148	*/
2149	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2150	\|\| uType == PGMPAGETYPE_INVALID,
2151	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2152	VERR_SSM_UNEXPECTED_DATA);
2153
2154	/*
2155	* Load the page.
2156	*/
2157	void *pvPage;
2158	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2159	if (RT_SUCCESS(rc))
2160	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2161
2162	return rc;
2163	}
2164
2165
2166	/**
2167	* Loads a page (counter part to pgmR3SavePage).
2168	*
2169	* @returns VBox status code, fully bitched errors.
2170	* @param pVM The VM handle.
2171	* @param pSSM The SSM handle.
2172	* @param uType The page type.
2173	* @param pPage The page.
2174	* @param GCPhys The page address.
2175	* @param pRam The RAM range (for error messages).
2176	*/
2177	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2178	{
2179	uint8_t uState;
2180	int rc = SSMR3GetU8(pSSM, &uState);
2181	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2182	if (uState == 0 /* zero */)
2183	rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2184	else if (uState == 1)
2185	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2186	else
2187	rc = VERR_INTERNAL_ERROR;
2188	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2189	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2190	rc);
2191	return VINF_SUCCESS;
2192	}
2193
2194
2195	/**
2196	* Loads a shadowed ROM page.
2197	*
2198	* @returns VBox status code, errors are fully bitched.
2199	* @param pVM The VM handle.
2200	* @param pSSM The saved state handle.
2201	* @param pPage The page.
2202	* @param GCPhys The page address.
2203	* @param pRam The RAM range (for error messages).
2204	*/
2205	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2206	{
2207	/*
2208	* Load and set the protection first, then load the two pages, the first
2209	* one is the active the other is the passive.
2210	*/
2211	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2212	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2213
2214	uint8_t uProt;
2215	int rc = SSMR3GetU8(pSSM, &uProt);
2216	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2217	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2218	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2219	&& enmProt < PGMROMPROT_END,
2220	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2221	VERR_SSM_UNEXPECTED_DATA);
2222
2223	if (pRomPage->enmProt != enmProt)
2224	{
2225	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2226	AssertLogRelRCReturn(rc, rc);
2227	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2228	}
2229
2230	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2231	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2232	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2233	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2234
2235	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2236	* used down the line (will the 2nd page will be written to the first
2237	* one because of a false TLB hit since the TLB is using GCPhys and
2238	* doesn't check the HCPhys of the desired page). */
2239	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2240	if (RT_SUCCESS(rc))
2241	{
2242	pPageActive = pPage;
2243	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2244	}
2245	return rc;
2246	}
2247
2248	/**
2249	* Ram range flags and bits for older versions of the saved state.
2250	*
2251	* @returns VBox status code.
2252	*
2253	* @param pVM The VM handle
2254	* @param pSSM The SSM handle.
2255	* @param uVersion The saved state version.
2256	*/
2257	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2258	{
2259	PPGM pPGM = &pVM->pgm.s;
2260
2261	/*
2262	* Ram range flags and bits.
2263	*/
2264	uint32_t i = 0;
2265	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2266	{
2267	/* Check the seqence number / separator. */
2268	uint32_t u32Sep;
2269	int rc = SSMR3GetU32(pSSM, &u32Sep);
2270	if (RT_FAILURE(rc))
2271	return rc;
2272	if (u32Sep == ~0U)
2273	break;
2274	if (u32Sep != i)
2275	{
2276	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2277	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2278	}
2279	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2280
2281	/* Get the range details. */
2282	RTGCPHYS GCPhys;
2283	SSMR3GetGCPhys(pSSM, &GCPhys);
2284	RTGCPHYS GCPhysLast;
2285	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2286	RTGCPHYS cb;
2287	SSMR3GetGCPhys(pSSM, &cb);
2288	uint8_t fHaveBits;
2289	rc = SSMR3GetU8(pSSM, &fHaveBits);
2290	if (RT_FAILURE(rc))
2291	return rc;
2292	if (fHaveBits & ~1)
2293	{
2294	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2295	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2296	}
2297	size_t cchDesc = 0;
2298	char szDesc[256];
2299	szDesc[0] = '\0';
2300	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2301	{
2302	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2303	if (RT_FAILURE(rc))
2304	return rc;
2305	/* Since we've modified the description strings in r45878, only compare
2306	them if the saved state is more recent. */
2307	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2308	cchDesc = strlen(szDesc);
2309	}
2310
2311	/*
2312	* Match it up with the current range.
2313	*
2314	* Note there is a hack for dealing with the high BIOS mapping
2315	* in the old saved state format, this means we might not have
2316	* a 1:1 match on success.
2317	*/
2318	if ( ( GCPhys != pRam->GCPhys
2319	\|\| GCPhysLast != pRam->GCPhysLast
2320	\|\| cb != pRam->cb
2321	\|\| ( cchDesc
2322	&& strcmp(szDesc, pRam->pszDesc)) )
2323	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2324	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2325	\|\| GCPhys != UINT32_C(0xfff80000)
2326	\|\| GCPhysLast != UINT32_C(0xffffffff)
2327	\|\| pRam->GCPhysLast != GCPhysLast
2328	\|\| pRam->GCPhys < GCPhys
2329	\|\| !fHaveBits)
2330	)
2331	{
2332	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2333	"State : %RGp-%RGp %RGp bytes %s %s\n",
2334	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2335	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2336	/*
2337	* If we're loading a state for debugging purpose, don't make a fuss if
2338	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2339	*/
2340	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2341	\|\| GCPhys < 8 * _1M)
2342	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2343	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2344	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2345	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2346
2347	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2348	continue;
2349	}
2350
2351	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2352	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2353	{
2354	/*
2355	* Load the pages one by one.
2356	*/
2357	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2358	{
2359	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2360	PPGMPAGE pPage = &pRam->aPages[iPage];
2361	uint8_t uType;
2362	rc = SSMR3GetU8(pSSM, &uType);
2363	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2364	if (uType == PGMPAGETYPE_ROM_SHADOW)
2365	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2366	else
2367	rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2368	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2369	}
2370	}
2371	else
2372	{
2373	/*
2374	* Old format.
2375	*/
2376
2377	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2378	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2379	uint32_t fFlags = 0;
2380	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2381	{
2382	uint16_t u16Flags;
2383	rc = SSMR3GetU16(pSSM, &u16Flags);
2384	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2385	fFlags \|= u16Flags;
2386	}
2387
2388	/* Load the bits */
2389	if ( !fHaveBits
2390	&& GCPhysLast < UINT32_C(0xe0000000))
2391	{
2392	/*
2393	* Dynamic chunks.
2394	*/
2395	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2396	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2397	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2398	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2399
2400	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2401	{
2402	uint8_t fPresent;
2403	rc = SSMR3GetU8(pSSM, &fPresent);
2404	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2405	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2406	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2407	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2408
2409	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2410	{
2411	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2412	PPGMPAGE pPage = &pRam->aPages[iPage];
2413	if (fPresent)
2414	{
2415	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2416	rc = pgmR3LoadPageToDevNullOld(pSSM);
2417	else
2418	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2419	}
2420	else
2421	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2422	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2423	}
2424	}
2425	}
2426	else if (pRam->pvR3)
2427	{
2428	/*
2429	* MMIO2.
2430	*/
2431	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2432	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2433	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2434	AssertLogRelMsgReturn(pRam->pvR3,
2435	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2436	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2437
2438	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2439	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2440	}
2441	else if (GCPhysLast < UINT32_C(0xfff80000))
2442	{
2443	/*
2444	* PCI MMIO, no pages saved.
2445	*/
2446	}
2447	else
2448	{
2449	/*
2450	* Load the 0xfff80000..0xffffffff BIOS range.
2451	* It starts with X reserved pages that we have to skip over since
2452	* the RAMRANGE create by the new code won't include those.
2453	*/
2454	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2455	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2456	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2457	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2458	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2459	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2460	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2461
2462	/* Skip wasted reserved pages before the ROM. */
2463	while (GCPhys < pRam->GCPhys)
2464	{
2465	rc = pgmR3LoadPageToDevNullOld(pSSM);
2466	GCPhys += PAGE_SIZE;
2467	}
2468
2469	/* Load the bios pages. */
2470	cPages = pRam->cb >> PAGE_SHIFT;
2471	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2472	{
2473	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2474	PPGMPAGE pPage = &pRam->aPages[iPage];
2475
2476	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2477	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2478	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2479	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2480	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2481	}
2482	}
2483	}
2484	}
2485
2486	return VINF_SUCCESS;
2487	}
2488
2489
2490	/**
2491	* Worker for pgmR3Load and pgmR3LoadLocked.
2492	*
2493	* @returns VBox status code.
2494	*
2495	* @param pVM The VM handle.
2496	* @param pSSM The SSM handle.
2497	* @param uVersion The saved state version.
2498	*
2499	* @todo This needs splitting up if more record types or code twists are
2500	* added...
2501	*/
2502	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2503	{
2504	/*
2505	* Process page records until we hit the terminator.
2506	*/
2507	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2508	PPGMRAMRANGE pRamHint = NULL;
2509	uint8_t id = UINT8_MAX;
2510	uint32_t iPage = UINT32_MAX - 10;
2511	PPGMROMRANGE pRom = NULL;
2512	PPGMMMIO2RANGE pMmio2 = NULL;
2513	for (;;)
2514	{
2515	/*
2516	* Get the record type and flags.
2517	*/
2518	uint8_t u8;
2519	int rc = SSMR3GetU8(pSSM, &u8);
2520	if (RT_FAILURE(rc))
2521	return rc;
2522	if (u8 == PGM_STATE_REC_END)
2523	return VINF_SUCCESS;
2524	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2525	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2526	{
2527	/*
2528	* RAM page.
2529	*/
2530	case PGM_STATE_REC_RAM_ZERO:
2531	case PGM_STATE_REC_RAM_RAW:
2532	{
2533	/*
2534	* Get the address and resolve it into a page descriptor.
2535	*/
2536	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2537	GCPhys += PAGE_SIZE;
2538	else
2539	{
2540	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2541	if (RT_FAILURE(rc))
2542	return rc;
2543	}
2544	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2545
2546	PPGMPAGE pPage;
2547	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2548	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2549
2550	/*
2551	* Take action according to the record type.
2552	*/
2553	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2554	{
2555	case PGM_STATE_REC_RAM_ZERO:
2556	{
2557	if ( PGM_PAGE_IS_ZERO(pPage)
2558	\|\| PGM_PAGE_IS_BALLOONED(pPage))
2559	break;
2560	/** @todo implement zero page replacing. */
2561	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2562	void *pvDstPage;
2563	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2564	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2565	ASMMemZeroPage(pvDstPage);
2566	break;
2567	}
2568
2569	case PGM_STATE_REC_RAM_RAW:
2570	{
2571	void *pvDstPage;
2572	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2573	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2574	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2575	if (RT_FAILURE(rc))
2576	return rc;
2577	break;
2578	}
2579
2580	default:
2581	AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2582	}
2583	id = UINT8_MAX;
2584	break;
2585	}
2586
2587	/*
2588	* MMIO2 page.
2589	*/
2590	case PGM_STATE_REC_MMIO2_RAW:
2591	case PGM_STATE_REC_MMIO2_ZERO:
2592	{
2593	/*
2594	* Get the ID + page number and resolved that into a MMIO2 page.
2595	*/
2596	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2597	iPage++;
2598	else
2599	{
2600	SSMR3GetU8(pSSM, &id);
2601	rc = SSMR3GetU32(pSSM, &iPage);
2602	if (RT_FAILURE(rc))
2603	return rc;
2604	}
2605	if ( !pMmio2
2606	\|\| pMmio2->idSavedState != id)
2607	{
2608	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2609	if (pMmio2->idSavedState == id)
2610	break;
2611	AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2612	}
2613	AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2614	void pvDstPage = (uint8_t )pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2615
2616	/*
2617	* Load the page bits.
2618	*/
2619	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2620	ASMMemZeroPage(pvDstPage);
2621	else
2622	{
2623	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2624	if (RT_FAILURE(rc))
2625	return rc;
2626	}
2627	GCPhys = NIL_RTGCPHYS;
2628	break;
2629	}
2630
2631	/*
2632	* ROM pages.
2633	*/
2634	case PGM_STATE_REC_ROM_VIRGIN:
2635	case PGM_STATE_REC_ROM_SHW_RAW:
2636	case PGM_STATE_REC_ROM_SHW_ZERO:
2637	case PGM_STATE_REC_ROM_PROT:
2638	{
2639	/*
2640	* Get the ID + page number and resolved that into a ROM page descriptor.
2641	*/
2642	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2643	iPage++;
2644	else
2645	{
2646	SSMR3GetU8(pSSM, &id);
2647	rc = SSMR3GetU32(pSSM, &iPage);
2648	if (RT_FAILURE(rc))
2649	return rc;
2650	}
2651	if ( !pRom
2652	\|\| pRom->idSavedState != id)
2653	{
2654	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2655	if (pRom->idSavedState == id)
2656	break;
2657	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2658	}
2659	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2660	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2661	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2662
2663	/*
2664	* Get and set the protection.
2665	*/
2666	uint8_t u8Prot;
2667	rc = SSMR3GetU8(pSSM, &u8Prot);
2668	if (RT_FAILURE(rc))
2669	return rc;
2670	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2671	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2672
2673	if (enmProt != pRomPage->enmProt)
2674	{
2675	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2676	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2677	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2678	GCPhys, enmProt, pRom->pszDesc);
2679	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2680	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2681	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2682	}
2683	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2684	break; /* done */
2685
2686	/*
2687	* Get the right page descriptor.
2688	*/
2689	PPGMPAGE pRealPage;
2690	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2691	{
2692	case PGM_STATE_REC_ROM_VIRGIN:
2693	if (!PGMROMPROT_IS_ROM(enmProt))
2694	pRealPage = &pRomPage->Virgin;
2695	else
2696	pRealPage = NULL;
2697	break;
2698
2699	case PGM_STATE_REC_ROM_SHW_RAW:
2700	case PGM_STATE_REC_ROM_SHW_ZERO:
2701	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2702	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2703	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2704	GCPhys, enmProt, pRom->pszDesc);
2705	if (PGMROMPROT_IS_ROM(enmProt))
2706	pRealPage = &pRomPage->Shadow;
2707	else
2708	pRealPage = NULL;
2709	break;
2710
2711	default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2712	}
2713	if (!pRealPage)
2714	{
2715	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2716	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2717	}
2718
2719	/*
2720	* Make it writable and map it (if necessary).
2721	*/
2722	void *pvDstPage = NULL;
2723	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2724	{
2725	case PGM_STATE_REC_ROM_SHW_ZERO:
2726	if ( PGM_PAGE_IS_ZERO(pRealPage)
2727	\|\| PGM_PAGE_IS_BALLOONED(pRealPage))
2728	break;
2729	/** @todo implement zero page replacing. */
2730	/* fall thru */
2731	case PGM_STATE_REC_ROM_VIRGIN:
2732	case PGM_STATE_REC_ROM_SHW_RAW:
2733	{
2734	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2735	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2736	break;
2737	}
2738	}
2739
2740	/*
2741	* Load the bits.
2742	*/
2743	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2744	{
2745	case PGM_STATE_REC_ROM_SHW_ZERO:
2746	if (pvDstPage)
2747	ASMMemZeroPage(pvDstPage);
2748	break;
2749
2750	case PGM_STATE_REC_ROM_VIRGIN:
2751	case PGM_STATE_REC_ROM_SHW_RAW:
2752	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2753	if (RT_FAILURE(rc))
2754	return rc;
2755	break;
2756	}
2757	GCPhys = NIL_RTGCPHYS;
2758	break;
2759	}
2760
2761	/*
2762	* Unknown type.
2763	*/
2764	default:
2765	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2766	}
2767	} /* forever */
2768	}
2769
2770
2771	/**
2772	* Worker for pgmR3Load.
2773	*
2774	* @returns VBox status code.
2775	*
2776	* @param pVM The VM handle.
2777	* @param pSSM The SSM handle.
2778	* @param uVersion The saved state version.
2779	*/
2780	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2781	{
2782	PPGM pPGM = &pVM->pgm.s;
2783	int rc;
2784	uint32_t u32Sep;
2785
2786	/*
2787	* Load basic data (required / unaffected by relocation).
2788	*/
2789	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2790	{
2791	if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2792	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2793	else
2794	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFieldsPreBalloon[0]);
2795
2796	AssertLogRelRCReturn(rc, rc);
2797
2798	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2799	{
2800	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2801	AssertLogRelRCReturn(rc, rc);
2802	}
2803	}
2804	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2805	{
2806	AssertRelease(pVM->cCpus == 1);
2807
2808	PGMOLD pgmOld;
2809	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2810	AssertLogRelRCReturn(rc, rc);
2811
2812	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2813	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2814	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2815
2816	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2817	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2818	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2819	}
2820	else
2821	{
2822	AssertRelease(pVM->cCpus == 1);
2823
2824	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2825	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2826	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2827
2828	uint32_t cbRamSizeIgnored;
2829	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2830	if (RT_FAILURE(rc))
2831	return rc;
2832	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2833
2834	uint32_t u32 = 0;
2835	SSMR3GetUInt(pSSM, &u32);
2836	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2837	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2838	RTUINT uGuestMode;
2839	SSMR3GetUInt(pSSM, &uGuestMode);
2840	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2841
2842	/* check separator. */
2843	SSMR3GetU32(pSSM, &u32Sep);
2844	if (RT_FAILURE(rc))
2845	return rc;
2846	if (u32Sep != (uint32_t)~0)
2847	{
2848	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2849	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2850	}
2851	}
2852
2853	/*
2854	* The guest mappings - skipped now, see re-fixation in the caller.
2855	*/
2856	uint32_t i = 0;
2857	for (;; i++)
2858	{
2859	rc = SSMR3GetU32(pSSM, &u32Sep); /* seqence number */
2860	if (RT_FAILURE(rc))
2861	return rc;
2862	if (u32Sep == ~0U)
2863	break;
2864	AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2865
2866	char szDesc[256];
2867	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2868	if (RT_FAILURE(rc))
2869	return rc;
2870	RTGCPTR GCPtrIgnore;
2871	SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
2872	rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
2873	if (RT_FAILURE(rc))
2874	return rc;
2875	}
2876
2877	/*
2878	* Load the RAM contents.
2879	*/
2880	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2881	{
2882	if (!pVM->pgm.s.LiveSave.fActive)
2883	{
2884	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2885	{
2886	rc = pgmR3LoadRamConfig(pVM, pSSM);
2887	if (RT_FAILURE(rc))
2888	return rc;
2889	}
2890	rc = pgmR3LoadRomRanges(pVM, pSSM);
2891	if (RT_FAILURE(rc))
2892	return rc;
2893	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2894	if (RT_FAILURE(rc))
2895	return rc;
2896	}
2897
2898	rc = pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2899	}
2900	else
2901	rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2902
2903	/* Refresh balloon accounting. */
2904	if (pVM->pgm.s.cBalloonedPages)
2905	{
2906	rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
2907	AssertRC(rc);
2908	}
2909	return rc;
2910	}
2911
2912
2913	/**
2914	* Execute state load operation.
2915	*
2916	* @returns VBox status code.
2917	* @param pVM VM Handle.
2918	* @param pSSM SSM operation handle.
2919	* @param uVersion Data layout version.
2920	* @param uPass The data pass.
2921	*/
2922	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2923	{
2924	int rc;
2925	PPGM pPGM = &pVM->pgm.s;
2926
2927	/*
2928	* Validate version.
2929	*/
2930	if ( ( uPass != SSM_PASS_FINAL
2931	&& uVersion != PGM_SAVED_STATE_VERSION
2932	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
2933	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2934	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
2935	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
2936	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
2937	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
2938	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
2939	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
2940	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2941	)
2942	{
2943	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
2944	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2945	}
2946
2947	/*
2948	* Do the loading while owning the lock because a bunch of the functions
2949	* we're using requires this.
2950	*/
2951	if (uPass != SSM_PASS_FINAL)
2952	{
2953	pgmLock(pVM);
2954	if (uPass != 0)
2955	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2956	else
2957	{
2958	pVM->pgm.s.LiveSave.fActive = true;
2959	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2960	rc = pgmR3LoadRamConfig(pVM, pSSM);
2961	else
2962	rc = VINF_SUCCESS;
2963	if (RT_SUCCESS(rc))
2964	rc = pgmR3LoadRomRanges(pVM, pSSM);
2965	if (RT_SUCCESS(rc))
2966	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2967	if (RT_SUCCESS(rc))
2968	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2969	}
2970	pgmUnlock(pVM);
2971	}
2972	else
2973	{
2974	pgmLock(pVM);
2975	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
2976	pVM->pgm.s.LiveSave.fActive = false;
2977	pgmUnlock(pVM);
2978	if (RT_SUCCESS(rc))
2979	{
2980	/*
2981	* We require a full resync now.
2982	*/
2983	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2984	{
2985	PVMCPU pVCpu = &pVM->aCpus[i];
2986	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2987	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2988	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2989	}
2990
2991	pgmR3HandlerPhysicalUpdateAll(pVM);
2992
2993	/*
2994	* Change the paging mode and restore PGMCPU::GCPhysCR3.
2995	* (The latter requires the CPUM state to be restored already.)
2996	*/
2997	if (CPUMR3IsStateRestorePending(pVM))
2998	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
2999	N_("PGM was unexpectedly restored before CPUM"));
3000
3001	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3002	{
3003	PVMCPU pVCpu = &pVM->aCpus[i];
3004
3005	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3006	AssertLogRelRCReturn(rc, rc);
3007
3008	/* Restore pVM->pgm.s.GCPhysCR3. */
3009	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3010	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3011	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3012	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3013	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3014	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3015	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3016	else
3017	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3018	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3019	}
3020
3021	/*
3022	* Try re-fixate the guest mappings.
3023	*/
3024	pVM->pgm.s.fMappingsFixedRestored = false;
3025	if ( pVM->pgm.s.fMappingsFixed
3026	&& pgmMapAreMappingsEnabled(&pVM->pgm.s))
3027	{
3028	RTGCPTR GCPtrFixed = pVM->pgm.s.GCPtrMappingFixed;
3029	uint32_t cbFixed = pVM->pgm.s.cbMappingFixed;
3030	pVM->pgm.s.fMappingsFixed = false;
3031
3032	uint32_t cbRequired;
3033	int rc2 = PGMR3MappingsSize(pVM, &cbRequired); AssertRC(rc2);
3034	if ( RT_SUCCESS(rc2)
3035	&& cbRequired > cbFixed)
3036	rc2 = VERR_OUT_OF_RANGE;
3037	if (RT_SUCCESS(rc2))
3038	rc2 = pgmR3MappingsFixInternal(pVM, GCPtrFixed, cbFixed);
3039	if (RT_FAILURE(rc2))
3040	{
3041	LogRel(("PGM: Unable to re-fixate the guest mappings at %RGv-%RGv: rc=%Rrc (cbRequired=%#x)\n",
3042	GCPtrFixed, GCPtrFixed + cbFixed, rc2, cbRequired));
3043	pVM->pgm.s.fMappingsFixed = false;
3044	pVM->pgm.s.fMappingsFixedRestored = true;
3045	pVM->pgm.s.GCPtrMappingFixed = GCPtrFixed;
3046	pVM->pgm.s.cbMappingFixed = cbFixed;
3047	}
3048	}
3049	else
3050	{
3051	/* We used to set fixed + disabled while we only use disabled now,
3052	so wipe the state to avoid any confusion. */
3053	pVM->pgm.s.fMappingsFixed = false;
3054	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
3055	pVM->pgm.s.cbMappingFixed = 0;
3056	}
3057
3058	/*
3059	* If we have floating mappings, do a CR3 sync now to make sure the HMA
3060	* doesn't conflict with guest code / data and thereby cause trouble
3061	* when restoring other components like PATM.
3062	*/
3063	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3064	{
3065	PVMCPU pVCpu = &pVM->aCpus[0];
3066	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
3067	if (RT_FAILURE(rc))
3068	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3069	N_("PGMSyncCR3 failed unexpectedly with rc=%Rrc"), rc);
3070
3071	/* Make sure to re-sync before executing code. */
3072	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3073	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3074	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3075	}
3076	}
3077	}
3078
3079	return rc;
3080	}
3081
3082
3083	/**
3084	* Registers the saved state callbacks with SSM.
3085	*
3086	* @returns VBox status code.
3087	* @param pVM Pointer to VM structure.
3088	* @param cbRam The RAM size.
3089	*/
3090	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3091	{
3092	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3093	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3094	NULL, pgmR3SaveExec, pgmR3SaveDone,
3095	pgmR3LoadPrep, pgmR3Load, NULL);
3096	}
3097

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source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 27549

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