VirtualBox

source: vbox/trunk/src/VBox/VMM/SELM.cpp@ 17522

Last change on this file since 17522 was 17107, checked in by vboxsync, 16 years ago

SELM: todo for optimizating the REM case...
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 95.9 KB
Line 
1/* $Id: SELM.cpp 17107 2009-02-25 00:50:49Z vboxsync $ */
2/** @file
3 * SELM - The Selector Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_selm SELM - The Selector Manager
23 *
24 * SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
25 * of a few hyper selector for the raw-mode context. In the hardware assisted
26 * virtualization mode its only task is to decode entries in the guest GDT or
27 * LDT once in a while.
28 *
29 * @see grp_selm
30 *
31 *
32 * @section seg_selm_shadowing Shadowing
33 *
34 * SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
35 * work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
36 * The idea is to do it in a more on-demand fashion when we get time. There
37 * also a whole bunch of issues with the current synchronization of all three
38 * tables, see notes and todos in the code.
39 *
40 * When the guest makes changes to the GDT we will try update the shadow copy
41 * without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
42 *
43 * When the guest make LDT changes we'll trigger a full resync of the LDT
44 * (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
45 *
46 * The TSS shadowing is limited to the fields we need to care about, namely SS0
47 * and ESP0. The Patch Manager makes use of these. We monitor updates to the
48 * guest TSS and will try keep our SS0 and ESP0 copies up to date this way
49 * rather than go the SELMR3SyncTSS() route.
50 *
51 * When in raw-mode SELM also injects a few extra GDT selectors which are used
52 * by the raw-mode (hyper) context. These start their life at the high end of
53 * the table and will be relocated when the guest tries to make use of them...
54 * Well, that was that idea at least, only the code isn't quite there yet which
55 * is why we have trouble with guests which actually have a full sized GDT.
56 *
57 * So, the summary of the current GDT, LDT and TSS shadowing is that there is a
58 * lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
59 *
60 */
61
62/*******************************************************************************
63* Header Files *
64*******************************************************************************/
65#define LOG_GROUP LOG_GROUP_SELM
66#include <VBox/selm.h>
67#include <VBox/cpum.h>
68#include <VBox/stam.h>
69#include <VBox/mm.h>
70#include <VBox/ssm.h>
71#include <VBox/pgm.h>
72#include <VBox/trpm.h>
73#include <VBox/dbgf.h>
74#include "SELMInternal.h"
75#include <VBox/vm.h>
76#include <VBox/err.h>
77#include <VBox/param.h>
78
79#include <iprt/assert.h>
80#include <VBox/log.h>
81#include <iprt/asm.h>
82#include <iprt/string.h>
83#include <iprt/thread.h>
84#include <iprt/string.h>
85
86
87/**
88 * Enable or disable tracking of Guest's GDT/LDT/TSS.
89 * @{
90 */
91#define SELM_TRACK_GUEST_GDT_CHANGES
92#define SELM_TRACK_GUEST_LDT_CHANGES
93#define SELM_TRACK_GUEST_TSS_CHANGES
94/** @} */
95
96/**
97 * Enable or disable tracking of Shadow GDT/LDT/TSS.
98 * @{
99 */
100#define SELM_TRACK_SHADOW_GDT_CHANGES
101#define SELM_TRACK_SHADOW_LDT_CHANGES
102#define SELM_TRACK_SHADOW_TSS_CHANGES
103/** @} */
104
105
106/** SELM saved state version. */
107#define SELM_SAVED_STATE_VERSION 5
108
109
110/*******************************************************************************
111* Internal Functions *
112*******************************************************************************/
113static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
114static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
115static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
116static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
117static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
118static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
119static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
120static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
121static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
122static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
123//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
124//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125
126
127
128/**
129 * Initializes the SELM.
130 *
131 * @returns VBox status code.
132 * @param pVM The VM to operate on.
133 */
134VMMR3DECL(int) SELMR3Init(PVM pVM)
135{
136 LogFlow(("SELMR3Init\n"));
137
138 /*
139 * Assert alignment and sizes.
140 * (The TSS block requires contiguous back.)
141 */
142 AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
143 AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
144#if 0 /* doesn't work */
145 AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
146 AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
147#endif
148 AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
149 AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
150 AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
151
152 /*
153 * Init the structure.
154 */
155 pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
156 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
157 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
158 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
159 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
160 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
161
162 /*
163 * Allocate GDT table.
164 */
165 int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
166 PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
167 AssertRCReturn(rc, rc);
168
169 /*
170 * Allocate LDT area.
171 */
172 rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
173 AssertRCReturn(rc, rc);
174
175 /*
176 * Init Guest's and Shadow GDT, LDT, TSS changes control variables.
177 */
178 pVM->selm.s.cbEffGuestGdtLimit = 0;
179 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
180 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
181 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
182
183 pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
184 pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
185 pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
186 pVM->selm.s.GCSelTss = RTSEL_MAX;
187
188 pVM->selm.s.fDisableMonitoring = false;
189 pVM->selm.s.fSyncTSSRing0Stack = false;
190
191 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
192 * for I/O operations. */
193 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
194 /* bit set to 1 means no redirection */
195 memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
196
197 /*
198 * Register the saved state data unit.
199 */
200 rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
201 NULL, selmR3Save, NULL,
202 NULL, selmR3Load, selmR3LoadDone);
203 if (RT_FAILURE(rc))
204 return rc;
205
206 /*
207 * Statistics.
208 */
209 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
210 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
211 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
212 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
213 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
214 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
215 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
216 STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
217 STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
218
219 STAM_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
220 STAM_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
221
222 /*
223 * Default action when entering raw mode for the first time
224 */
225 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
226 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
227 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
228
229 /*
230 * Register info handlers.
231 */
232 DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
233 DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
234 DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
235 DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
236 //DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
237 //DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
238
239 return rc;
240}
241
242
243/**
244 * Finalizes HMA page attributes.
245 *
246 * @returns VBox status code.
247 * @param pVM The VM handle.
248 */
249VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
250{
251 /** @cfgm{/DoubleFault,bool,false}
252 * Enables catching of double faults in the raw-mode context VMM code. This can
253 * be used when the tripple faults or hangs occure and one suspect an unhandled
254 * double fault. This is not enabled by default because it means making the
255 * hyper selectors writeable for all supervisor code, including the guest's.
256 * The double fault is a task switch and thus requires write access to the GDT
257 * of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
258 * 8 TSS for the back link.
259 */
260 bool f;
261#if defined(DEBUG_bird)
262 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
263#else
264 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
265#endif
266 AssertLogRelRCReturn(rc, rc);
267 if (f)
268 {
269 PX86DESC paGdt = pVM->selm.s.paGdtR3;
270 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
271 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
272 AssertRC(rc);
273 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
274 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
275 AssertRC(rc);
276 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
277 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
278 AssertRC(rc);
279 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
280 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
281 AssertRC(rc);
282 }
283 return VINF_SUCCESS;
284}
285
286
287/**
288 * Setup the hypervisor GDT selectors in our shadow table
289 *
290 * @param pVM The VM handle.
291 */
292static void selmR3SetupHyperGDTSelectors(PVM pVM)
293{
294 PX86DESC paGdt = pVM->selm.s.paGdtR3;
295
296 /*
297 * Set up global code and data descriptors for use in the guest context.
298 * Both are wide open (base 0, limit 4GB)
299 */
300 PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
301 pDesc->Gen.u16LimitLow = 0xffff;
302 pDesc->Gen.u4LimitHigh = 0xf;
303 pDesc->Gen.u16BaseLow = 0;
304 pDesc->Gen.u8BaseHigh1 = 0;
305 pDesc->Gen.u8BaseHigh2 = 0;
306 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
307 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
308 pDesc->Gen.u2Dpl = 0; /* supervisor */
309 pDesc->Gen.u1Present = 1;
310 pDesc->Gen.u1Available = 0;
311 pDesc->Gen.u1Long = 0;
312 pDesc->Gen.u1DefBig = 1; /* def 32 bit */
313 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
314
315 /* data */
316 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
317 pDesc->Gen.u16LimitLow = 0xffff;
318 pDesc->Gen.u4LimitHigh = 0xf;
319 pDesc->Gen.u16BaseLow = 0;
320 pDesc->Gen.u8BaseHigh1 = 0;
321 pDesc->Gen.u8BaseHigh2 = 0;
322 pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
323 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
324 pDesc->Gen.u2Dpl = 0; /* supervisor */
325 pDesc->Gen.u1Present = 1;
326 pDesc->Gen.u1Available = 0;
327 pDesc->Gen.u1Long = 0;
328 pDesc->Gen.u1DefBig = 1; /* big */
329 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
330
331 /* 64-bit mode code (& data?) */
332 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
333 pDesc->Gen.u16LimitLow = 0xffff;
334 pDesc->Gen.u4LimitHigh = 0xf;
335 pDesc->Gen.u16BaseLow = 0;
336 pDesc->Gen.u8BaseHigh1 = 0;
337 pDesc->Gen.u8BaseHigh2 = 0;
338 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
339 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
340 pDesc->Gen.u2Dpl = 0; /* supervisor */
341 pDesc->Gen.u1Present = 1;
342 pDesc->Gen.u1Available = 0;
343 pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
344 pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
345 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
346
347 /*
348 * TSS descriptor
349 */
350 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
351 RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
352 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
353 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
354 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
355 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
356 pDesc->Gen.u4LimitHigh = 0;
357 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
358 pDesc->Gen.u1DescType = 0; /* system */
359 pDesc->Gen.u2Dpl = 0; /* supervisor */
360 pDesc->Gen.u1Present = 1;
361 pDesc->Gen.u1Available = 0;
362 pDesc->Gen.u1Long = 0;
363 pDesc->Gen.u1DefBig = 0;
364 pDesc->Gen.u1Granularity = 0; /* byte limit */
365
366 /*
367 * TSS descriptor for trap 08
368 */
369 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
370 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
371 pDesc->Gen.u4LimitHigh = 0;
372 RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
373 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
374 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
375 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
376 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
377 pDesc->Gen.u1DescType = 0; /* system */
378 pDesc->Gen.u2Dpl = 0; /* supervisor */
379 pDesc->Gen.u1Present = 1;
380 pDesc->Gen.u1Available = 0;
381 pDesc->Gen.u1Long = 0;
382 pDesc->Gen.u1DefBig = 0;
383 pDesc->Gen.u1Granularity = 0; /* byte limit */
384}
385
386/**
387 * Applies relocations to data and code managed by this
388 * component. This function will be called at init and
389 * whenever the VMM need to relocate it self inside the GC.
390 *
391 * @param pVM The VM.
392 */
393VMMR3DECL(void) SELMR3Relocate(PVM pVM)
394{
395 PX86DESC paGdt = pVM->selm.s.paGdtR3;
396 LogFlow(("SELMR3Relocate\n"));
397
398 /*
399 * Update GDTR and selector.
400 */
401 CPUMSetHyperGDTR(pVM, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
402
403 /** @todo selector relocations should be a seperate operation? */
404 CPUMSetHyperCS(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
405 CPUMSetHyperDS(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
406 CPUMSetHyperES(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
407 CPUMSetHyperSS(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
408 CPUMSetHyperTR(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
409
410 selmR3SetupHyperGDTSelectors(pVM);
411
412/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
413/** @todo PGM knows the proper CR3 values these days, not CPUM. */
414 /*
415 * Update the TSSes.
416 */
417 /* Current TSS */
418 pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVM);
419 pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
420 pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVM);
421 pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
422 pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
423 pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
424 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
425
426 /* trap 08 */
427 pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM); /* this should give use better survival chances. */
428 pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
429 pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
430 pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVM) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
431 pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
432 pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
433 pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
434 pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
435 pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
436 pVM->selm.s.TssTrap08.fs = 0;
437 pVM->selm.s.TssTrap08.gs = 0;
438 pVM->selm.s.TssTrap08.selLdt = 0;
439 pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
440 pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
441 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
442 pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
443 pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
444 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
445 pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
446 pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
447 /* TRPM will be updating the eip */
448
449 if (!pVM->selm.s.fDisableMonitoring)
450 {
451 /*
452 * Update shadow GDT/LDT/TSS write access handlers.
453 */
454 int rc;
455#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
456 if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
457 {
458 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
459 AssertRC(rc);
460 }
461 pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
462 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
463 pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
464 0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
465 AssertRC(rc);
466#endif
467#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
468 if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
469 {
470 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
471 AssertRC(rc);
472 }
473 pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
474 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
475 pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
476 0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
477 AssertRC(rc);
478#endif
479
480 /*
481 * Update the GC LDT region handler and address.
482 */
483#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
484 if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
485 {
486 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
487 AssertRC(rc);
488 }
489#endif
490 pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
491#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
492 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
493 pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
494 0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
495 AssertRC(rc);
496#endif
497 }
498}
499
500
501/**
502 * Notification callback which is called whenever there is a chance that a CR3
503 * value might have changed.
504 * This is called by PGM.
505 *
506 * @param pVM The VM handle
507 */
508VMMR3DECL(void) SELMR3PagingModeChanged(PVM pVM)
509{
510 pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVM);
511 pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM);
512}
513
514
515/**
516 * Terminates the SELM.
517 *
518 * Termination means cleaning up and freeing all resources,
519 * the VM it self is at this point powered off or suspended.
520 *
521 * @returns VBox status code.
522 * @param pVM The VM to operate on.
523 */
524VMMR3DECL(int) SELMR3Term(PVM pVM)
525{
526 return 0;
527}
528
529
530/**
531 * The VM is being reset.
532 *
533 * For the SELM component this means that any GDT/LDT/TSS monitors
534 * needs to be removed.
535 *
536 * @param pVM VM handle.
537 */
538VMMR3DECL(void) SELMR3Reset(PVM pVM)
539{
540 LogFlow(("SELMR3Reset:\n"));
541 VM_ASSERT_EMT(pVM);
542
543 /*
544 * Uninstall guest GDT/LDT/TSS write access handlers.
545 */
546 int rc;
547#ifdef SELM_TRACK_GUEST_GDT_CHANGES
548 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
549 {
550 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
551 AssertRC(rc);
552 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
553 pVM->selm.s.GuestGdtr.cbGdt = 0;
554 }
555 pVM->selm.s.fGDTRangeRegistered = false;
556#endif
557#ifdef SELM_TRACK_GUEST_LDT_CHANGES
558 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
559 {
560 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
561 AssertRC(rc);
562 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
563 }
564#endif
565#ifdef SELM_TRACK_GUEST_TSS_CHANGES
566 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
567 {
568 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
569 AssertRC(rc);
570 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
571 pVM->selm.s.GCSelTss = RTSEL_MAX;
572 }
573#endif
574
575 /*
576 * Re-initialize other members.
577 */
578 pVM->selm.s.cbLdtLimit = 0;
579 pVM->selm.s.offLdtHyper = 0;
580 pVM->selm.s.cbMonitoredGuestTss = 0;
581
582 pVM->selm.s.fSyncTSSRing0Stack = false;
583
584 /*
585 * Default action when entering raw mode for the first time
586 */
587 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
588 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
589 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
590}
591
592/**
593 * Disable GDT/LDT/TSS monitoring and syncing
594 *
595 * @param pVM The VM to operate on.
596 */
597VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
598{
599 /*
600 * Uninstall guest GDT/LDT/TSS write access handlers.
601 */
602 int rc;
603#ifdef SELM_TRACK_GUEST_GDT_CHANGES
604 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
605 {
606 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
607 AssertRC(rc);
608 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
609 pVM->selm.s.GuestGdtr.cbGdt = 0;
610 }
611 pVM->selm.s.fGDTRangeRegistered = false;
612#endif
613#ifdef SELM_TRACK_GUEST_LDT_CHANGES
614 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
615 {
616 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
617 AssertRC(rc);
618 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
619 }
620#endif
621#ifdef SELM_TRACK_GUEST_TSS_CHANGES
622 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
623 {
624 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
625 AssertRC(rc);
626 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
627 pVM->selm.s.GCSelTss = RTSEL_MAX;
628 }
629#endif
630
631 /*
632 * Unregister shadow GDT/LDT/TSS write access handlers.
633 */
634#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
635 if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
636 {
637 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
638 AssertRC(rc);
639 pVM->selm.s.paGdtRC = NIL_RTRCPTR;
640 }
641#endif
642#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
643 if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
644 {
645 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
646 AssertRC(rc);
647 pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
648 }
649#endif
650#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
651 if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
652 {
653 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
654 AssertRC(rc);
655 pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
656 }
657#endif
658
659 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
660 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
661 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
662
663 pVM->selm.s.fDisableMonitoring = true;
664}
665
666
667/**
668 * Execute state save operation.
669 *
670 * @returns VBox status code.
671 * @param pVM VM Handle.
672 * @param pSSM SSM operation handle.
673 */
674static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
675{
676 LogFlow(("selmR3Save:\n"));
677
678 /*
679 * Save the basic bits - fortunately all the other things can be resynced on load.
680 */
681 PSELM pSelm = &pVM->selm.s;
682
683 SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
684 SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
685 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
686 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
687 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
688 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
689 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
690 return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
691}
692
693
694/**
695 * Execute state load operation.
696 *
697 * @returns VBox status code.
698 * @param pVM VM Handle.
699 * @param pSSM SSM operation handle.
700 * @param u32Version Data layout version.
701 */
702static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
703{
704 LogFlow(("selmR3Load:\n"));
705
706 /*
707 * Validate version.
708 */
709 if (u32Version != SELM_SAVED_STATE_VERSION)
710 {
711 AssertMsgFailed(("selmR3Load: Invalid version u32Version=%d!\n", u32Version));
712 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
713 }
714
715 /*
716 * Do a reset.
717 */
718 SELMR3Reset(pVM);
719
720 /* Get the monitoring flag. */
721 SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
722
723 /* Get the TSS state flag. */
724 SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
725
726 /*
727 * Get the selectors.
728 */
729 RTSEL SelCS;
730 SSMR3GetSel(pSSM, &SelCS);
731 RTSEL SelDS;
732 SSMR3GetSel(pSSM, &SelDS);
733 RTSEL SelCS64;
734 SSMR3GetSel(pSSM, &SelCS64);
735 RTSEL SelDS64;
736 SSMR3GetSel(pSSM, &SelDS64);
737 RTSEL SelTSS;
738 SSMR3GetSel(pSSM, &SelTSS);
739 RTSEL SelTSSTrap08;
740 SSMR3GetSel(pSSM, &SelTSSTrap08);
741
742 /* Copy the selectors; they will be checked during relocation. */
743 PSELM pSelm = &pVM->selm.s;
744 pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
745 pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
746 pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
747 pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
748 pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
749
750 return VINF_SUCCESS;
751}
752
753
754/**
755 * Sync the GDT, LDT and TSS after loading the state.
756 *
757 * Just to play save, we set the FFs to force syncing before
758 * executing GC code.
759 *
760 * @returns VBox status code.
761 * @param pVM VM Handle.
762 * @param pSSM SSM operation handle.
763 */
764static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
765{
766 LogFlow(("selmR3LoadDone:\n"));
767
768 /*
769 * Don't do anything if it's a load failure.
770 */
771 int rc = SSMR3HandleGetStatus(pSSM);
772 if (RT_FAILURE(rc))
773 return VINF_SUCCESS;
774
775 /*
776 * Do the syncing if we're in protected mode.
777 */
778 if (PGMGetGuestMode(pVM) != PGMMODE_REAL)
779 {
780 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
781 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
782 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
783 SELMR3UpdateFromCPUM(pVM);
784 }
785
786 /*
787 * Flag everything for resync on next raw mode entry.
788 */
789 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
790 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
791 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
792
793 return VINF_SUCCESS;
794}
795
796
797/**
798 * Updates the Guest GDT & LDT virtualization based on current CPU state.
799 *
800 * @returns VBox status code.
801 * @param pVM The VM to operate on.
802 */
803VMMR3DECL(int) SELMR3UpdateFromCPUM(PVM pVM)
804{
805 int rc = VINF_SUCCESS;
806
807 if (pVM->selm.s.fDisableMonitoring)
808 {
809 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
810 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
811 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
812
813 return VINF_SUCCESS;
814 }
815
816 STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
817
818 /*
819 * GDT sync
820 */
821 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_GDT))
822 {
823 /*
824 * Always assume the best
825 */
826 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
827
828 /* If the GDT was changed, then make sure the LDT is checked too */
829 /** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
830 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
831 /* Same goes for the TSS selector */
832 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
833
834 /*
835 * Get the GDTR and check if there is anything to do (there usually is).
836 */
837 VBOXGDTR GDTR;
838 CPUMGetGuestGDTR(pVM, &GDTR);
839 if (GDTR.cbGdt < sizeof(X86DESC))
840 {
841 Log(("No GDT entries...\n"));
842 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
843 return VINF_SUCCESS;
844 }
845
846 /*
847 * Read the Guest GDT.
848 * ASSUMES that the entire GDT is in memory.
849 */
850 RTUINT cbEffLimit = GDTR.cbGdt;
851 PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
852 rc = PGMPhysSimpleReadGCPtr(pVM, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
853 if (RT_FAILURE(rc))
854 {
855 /*
856 * Read it page by page.
857 *
858 * Keep track of the last valid page and delay memsets and
859 * adjust cbEffLimit to reflect the effective size. The latter
860 * is something we do in the belief that the guest will probably
861 * never actually commit the last page, thus allowing us to keep
862 * our selectors in the high end of the GDT.
863 */
864 RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
865 RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
866 uint8_t *pu8Dst = (uint8_t *)&pVM->selm.s.paGdtR3[1];
867 uint8_t *pu8DstInvalid = pu8Dst;
868
869 while (cbLeft)
870 {
871 RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
872 cb = RT_MIN(cb, cbLeft);
873 rc = PGMPhysSimpleReadGCPtr(pVM, pu8Dst, GCPtrSrc, cb);
874 if (RT_SUCCESS(rc))
875 {
876 if (pu8DstInvalid != pu8Dst)
877 memset(pu8DstInvalid, 0, pu8Dst - pu8DstInvalid);
878 GCPtrSrc += cb;
879 pu8Dst += cb;
880 pu8DstInvalid = pu8Dst;
881 }
882 else if ( rc == VERR_PAGE_NOT_PRESENT
883 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
884 {
885 GCPtrSrc += cb;
886 pu8Dst += cb;
887 }
888 else
889 {
890 AssertReleaseMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
891 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
892 return VERR_NOT_IMPLEMENTED;
893 }
894 cbLeft -= cb;
895 }
896
897 /* any invalid pages at the end? */
898 if (pu8DstInvalid != pu8Dst)
899 {
900 cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
901 /* If any GDTEs was invalidated, zero them. */
902 if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
903 memset(pu8DstInvalid + cbEffLimit + 1, 0, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
904 }
905
906 /* keep track of the effective limit. */
907 if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
908 {
909 Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
910 pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
911 pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
912 }
913 }
914
915 /*
916 * Check if the Guest GDT intrudes on our GDT entries.
917 */
918 /** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
919 RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
920 if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
921 {
922 PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
923 PX86DESC pGDTE = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
924 int iGDT = 0;
925
926 Log(("Internal SELM GDT conflict: use non-present entries\n"));
927 STAM_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
928 while (pGDTE > pGDTEStart)
929 {
930 /* We can reuse non-present entries */
931 if (!pGDTE->Gen.u1Present)
932 {
933 aHyperSel[iGDT] = ((uintptr_t)pGDTE - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
934 aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
935 Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
936 iGDT++;
937 if (iGDT >= SELM_HYPER_SEL_MAX)
938 break;
939 }
940
941 pGDTE--;
942 }
943 if (iGDT != SELM_HYPER_SEL_MAX)
944 {
945 AssertReleaseMsgFailed(("Internal SELM GDT conflict.\n"));
946 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
947 return VERR_NOT_IMPLEMENTED;
948 }
949 }
950 else
951 {
952 aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
953 aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
954 aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
955 aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
956 aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
957 }
958
959 /*
960 * Work thru the copied GDT entries adjusting them for correct virtualization.
961 */
962 PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
963 while (pGDTE < pGDTEEnd)
964 {
965 if (pGDTE->Gen.u1Present)
966 {
967 /*
968 * Code and data selectors are generally 1:1, with the
969 * 'little' adjustment we do for DPL 0 selectors.
970 */
971 if (pGDTE->Gen.u1DescType)
972 {
973 /*
974 * Hack for A-bit against Trap E on read-only GDT.
975 */
976 /** @todo Fix this by loading ds and cs before turning off WP. */
977 pGDTE->Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
978
979 /*
980 * All DPL 0 code and data segments are squeezed into DPL 1.
981 *
982 * We're skipping conforming segments here because those
983 * cannot give us any trouble.
984 */
985 if ( pGDTE->Gen.u2Dpl == 0
986 && (pGDTE->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
987 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
988 pGDTE->Gen.u2Dpl = 1;
989 }
990 else
991 {
992 /*
993 * System type selectors are marked not present.
994 * Recompiler or special handling is required for these.
995 */
996 /** @todo what about interrupt gates and rawr0? */
997 pGDTE->Gen.u1Present = 0;
998 }
999 }
1000
1001 /* Next GDT entry. */
1002 pGDTE++;
1003 }
1004
1005 /*
1006 * Check if our hypervisor selectors were changed.
1007 */
1008 if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
1009 || aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
1010 || aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
1011 || aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
1012 || aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
1013 {
1014 /* Reinitialize our hypervisor GDTs */
1015 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
1016 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
1017 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
1018 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
1019 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1020
1021 STAM_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
1022
1023 /*
1024 * Do the relocation callbacks to let everyone update their hyper selector dependencies.
1025 * (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
1026 */
1027 VMR3Relocate(pVM, 0);
1028 }
1029 else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
1030 /* We overwrote all entries above, so we have to save them again. */
1031 selmR3SetupHyperGDTSelectors(pVM);
1032
1033 /*
1034 * Adjust the cached GDT limit.
1035 * Any GDT entries which have been removed must be cleared.
1036 */
1037 if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1038 {
1039 if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1040 memset(pGDTE, 0, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1041#ifndef SELM_TRACK_GUEST_GDT_CHANGES
1042 pVM->selm.s.GuestGdtr.cbGdt = GDTR.cbGdt;
1043#endif
1044 }
1045
1046#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1047 /*
1048 * Check if Guest's GDTR is changed.
1049 */
1050 if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1051 || GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1052 {
1053 Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1054
1055 /*
1056 * [Re]Register write virtual handler for guest's GDT.
1057 */
1058 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1059 {
1060 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1061 AssertRC(rc);
1062 }
1063
1064 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1065 0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0, "Guest GDT write access handler");
1066 if (RT_FAILURE(rc))
1067 return rc;
1068
1069 /* Update saved Guest GDTR. */
1070 pVM->selm.s.GuestGdtr = GDTR;
1071 pVM->selm.s.fGDTRangeRegistered = true;
1072 }
1073#endif
1074 }
1075
1076 /*
1077 * TSS sync
1078 */
1079 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
1080 {
1081 SELMR3SyncTSS(pVM);
1082 }
1083
1084 /*
1085 * LDT sync
1086 */
1087 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_LDT))
1088 {
1089 /*
1090 * Always assume the best
1091 */
1092 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
1093
1094 /*
1095 * LDT handling is done similarly to the GDT handling with a shadow
1096 * array. However, since the LDT is expected to be swappable (at least
1097 * some ancient OSes makes it swappable) it must be floating and
1098 * synced on a per-page basis.
1099 *
1100 * Eventually we will change this to be fully on demand. Meaning that
1101 * we will only sync pages containing LDT selectors actually used and
1102 * let the #PF handler lazily sync pages as they are used.
1103 * (This applies to GDT too, when we start making OS/2 fast.)
1104 */
1105
1106 /*
1107 * First, determin the current LDT selector.
1108 */
1109 RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
1110 if ((SelLdt & X86_SEL_MASK) == 0)
1111 {
1112 /* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1113 CPUMSetHyperLDTR(pVM, 0);
1114#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1115 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1116 {
1117 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1118 AssertRC(rc);
1119 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1120 }
1121#endif
1122 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1123 return VINF_SUCCESS;
1124 }
1125
1126 /*
1127 * Get the LDT selector.
1128 */
1129 PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1130 RTGCPTR GCPtrLdt = X86DESC_BASE(*pDesc);
1131 unsigned cbLdt = X86DESC_LIMIT(*pDesc);
1132 if (pDesc->Gen.u1Granularity)
1133 cbLdt = (cbLdt << PAGE_SHIFT) | PAGE_OFFSET_MASK;
1134
1135 /*
1136 * Validate it.
1137 */
1138 if ( !cbLdt
1139 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1140 || pDesc->Gen.u1DescType
1141 || pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1142 {
1143 AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1144
1145 /* cbLdt > 0:
1146 * This is quite impossible, so we do as most people do when faced with
1147 * the impossible, we simply ignore it.
1148 */
1149 CPUMSetHyperLDTR(pVM, 0);
1150#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1151 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1152 {
1153 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1154 AssertRC(rc);
1155 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1156 }
1157#endif
1158 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1159 return VINF_SUCCESS;
1160 }
1161 /** @todo check what intel does about odd limits. */
1162 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1163
1164 /*
1165 * Use the cached guest ldt address if the descriptor has already been modified (see below)
1166 * (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1167 */
1168 if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1169 GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1170
1171
1172#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1173 /** @todo Handle only present LDT segments. */
1174 // if (pDesc->Gen.u1Present)
1175 {
1176 /*
1177 * Check if Guest's LDT address/limit is changed.
1178 */
1179 if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1180 || cbLdt != pVM->selm.s.cbLdtLimit)
1181 {
1182 Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1183 pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1184
1185 /*
1186 * [Re]Register write virtual handler for guest's GDT.
1187 * In the event of LDT overlapping something, don't install it just assume it's being updated.
1188 */
1189 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1190 {
1191 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1192 AssertRC(rc);
1193 }
1194#ifdef DEBUG
1195 if (pDesc->Gen.u1Present)
1196 Log(("LDT selector marked not present!!\n"));
1197#endif
1198 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1199 0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1200 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1201 {
1202 /** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1203 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1204 Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1205 GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1206 }
1207 else if (RT_SUCCESS(rc))
1208 pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1209 else
1210 {
1211 CPUMSetHyperLDTR(pVM, 0);
1212 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1213 return rc;
1214 }
1215
1216 pVM->selm.s.cbLdtLimit = cbLdt;
1217 }
1218 }
1219#else
1220 pVM->selm.s.cbLdtLimit = cbLdt;
1221#endif
1222
1223 /*
1224 * Calc Shadow LDT base.
1225 */
1226 unsigned off;
1227 pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1228 RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1229 PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1230
1231 /*
1232 * Enable the LDT selector in the shadow GDT.
1233 */
1234 pDesc->Gen.u1Present = 1;
1235 pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1236 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1237 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1238 pDesc->Gen.u1Available = 0;
1239 pDesc->Gen.u1Long = 0;
1240 if (cbLdt > 0xffff)
1241 {
1242 cbLdt = 0xffff;
1243 pDesc->Gen.u4LimitHigh = 0;
1244 pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1245 }
1246
1247 /*
1248 * Set Hyper LDTR and notify TRPM.
1249 */
1250 CPUMSetHyperLDTR(pVM, SelLdt);
1251
1252 /*
1253 * Loop synchronising the LDT page by page.
1254 */
1255 /** @todo investigate how intel handle various operations on half present cross page entries. */
1256 off = GCPtrLdt & (sizeof(X86DESC) - 1);
1257 AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1258
1259 /* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1260 unsigned cbLeft = cbLdt + 1;
1261 PX86DESC pLDTE = pShadowLDT;
1262 while (cbLeft)
1263 {
1264 /*
1265 * Read a chunk.
1266 */
1267 unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1268 if (cbChunk > cbLeft)
1269 cbChunk = cbLeft;
1270 rc = PGMPhysSimpleReadGCPtr(pVM, pShadowLDT, GCPtrLdt, cbChunk);
1271 if (RT_SUCCESS(rc))
1272 {
1273 /*
1274 * Mark page
1275 */
1276 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D);
1277 AssertRC(rc);
1278
1279 /*
1280 * Loop thru the available LDT entries.
1281 * Figure out where to start and end and the potential cross pageness of
1282 * things adds a little complexity. pLDTE is updated there and not in the
1283 * 'next' part of the loop. The pLDTEEnd is inclusive.
1284 */
1285 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1286 if (pLDTE + 1 < pShadowLDT)
1287 pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1288 while (pLDTE <= pLDTEEnd)
1289 {
1290 if (pLDTE->Gen.u1Present)
1291 {
1292 /*
1293 * Code and data selectors are generally 1:1, with the
1294 * 'little' adjustment we do for DPL 0 selectors.
1295 */
1296 if (pLDTE->Gen.u1DescType)
1297 {
1298 /*
1299 * Hack for A-bit against Trap E on read-only GDT.
1300 */
1301 /** @todo Fix this by loading ds and cs before turning off WP. */
1302 if (!(pLDTE->Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1303 pLDTE->Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1304
1305 /*
1306 * All DPL 0 code and data segments are squeezed into DPL 1.
1307 *
1308 * We're skipping conforming segments here because those
1309 * cannot give us any trouble.
1310 */
1311 if ( pLDTE->Gen.u2Dpl == 0
1312 && (pLDTE->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
1313 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
1314 pLDTE->Gen.u2Dpl = 1;
1315 }
1316 else
1317 {
1318 /*
1319 * System type selectors are marked not present.
1320 * Recompiler or special handling is required for these.
1321 */
1322 /** @todo what about interrupt gates and rawr0? */
1323 pLDTE->Gen.u1Present = 0;
1324 }
1325 }
1326
1327 /* Next LDT entry. */
1328 pLDTE++;
1329 }
1330 }
1331 else
1332 {
1333 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1334 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1335 AssertRC(rc);
1336 }
1337
1338 /*
1339 * Advance to the next page.
1340 */
1341 cbLeft -= cbChunk;
1342 GCPtrShadowLDT += cbChunk;
1343 pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1344 GCPtrLdt += cbChunk;
1345 }
1346 }
1347
1348 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1349 return VINF_SUCCESS;
1350}
1351
1352
1353/**
1354 * \#PF Handler callback for virtual access handler ranges.
1355 *
1356 * Important to realize that a physical page in a range can have aliases, and
1357 * for ALL and WRITE handlers these will also trigger.
1358 *
1359 * @returns VINF_SUCCESS if the handler have carried out the operation.
1360 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1361 * @param pVM VM Handle.
1362 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1363 * @param pvPtr The HC mapping of that address.
1364 * @param pvBuf What the guest is reading/writing.
1365 * @param cbBuf How much it's reading/writing.
1366 * @param enmAccessType The access type.
1367 * @param pvUser User argument.
1368 */
1369static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1370{
1371 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1372 Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1373 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
1374
1375 return VINF_PGM_HANDLER_DO_DEFAULT;
1376}
1377
1378
1379/**
1380 * \#PF Handler callback for virtual access handler ranges.
1381 *
1382 * Important to realize that a physical page in a range can have aliases, and
1383 * for ALL and WRITE handlers these will also trigger.
1384 *
1385 * @returns VINF_SUCCESS if the handler have carried out the operation.
1386 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1387 * @param pVM VM Handle.
1388 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1389 * @param pvPtr The HC mapping of that address.
1390 * @param pvBuf What the guest is reading/writing.
1391 * @param cbBuf How much it's reading/writing.
1392 * @param enmAccessType The access type.
1393 * @param pvUser User argument.
1394 */
1395static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1396{
1397 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1398 Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1399 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
1400 return VINF_PGM_HANDLER_DO_DEFAULT;
1401}
1402
1403
1404/**
1405 * \#PF Handler callback for virtual access handler ranges.
1406 *
1407 * Important to realize that a physical page in a range can have aliases, and
1408 * for ALL and WRITE handlers these will also trigger.
1409 *
1410 * @returns VINF_SUCCESS if the handler have carried out the operation.
1411 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1412 * @param pVM VM Handle.
1413 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1414 * @param pvPtr The HC mapping of that address.
1415 * @param pvBuf What the guest is reading/writing.
1416 * @param cbBuf How much it's reading/writing.
1417 * @param enmAccessType The access type.
1418 * @param pvUser User argument.
1419 */
1420static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1421{
1422 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1423 Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1424
1425 /** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1426 * reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1427 * should probably also deregister the virtual handler if TR.base/size
1428 * changes while we're in REM. */
1429
1430 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
1431
1432 return VINF_PGM_HANDLER_DO_DEFAULT;
1433}
1434
1435
1436/**
1437 * Synchronize the shadowed fields in the TSS.
1438 *
1439 * At present we're shadowing the ring-0 stack selector & pointer, and the
1440 * interrupt redirection bitmap (if present). We take the lazy approach wrt to
1441 * REM and this function is called both if REM made any changes to the TSS or
1442 * loaded TR.
1443 *
1444 * @returns VBox status code.
1445 * @param pVM The VM to operate on.
1446 */
1447VMMR3DECL(int) SELMR3SyncTSS(PVM pVM)
1448{
1449 int rc;
1450
1451 if (pVM->selm.s.fDisableMonitoring)
1452 {
1453 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
1454 return VINF_SUCCESS;
1455 }
1456
1457 STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1458 Assert(VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS));
1459
1460 /*
1461 * Get TR and extract and store the basic info.
1462 *
1463 * Note! The TSS limit is not checked by the LTR code, so we
1464 * have to be a bit careful with it. We make sure cbTss
1465 * won't be zero if TR is valid and if it's NULL we'll
1466 * make sure cbTss is 0.
1467 */
1468 CPUMSELREGHID trHid;
1469 RTSEL SelTss = CPUMGetGuestTR(pVM, &trHid);
1470 RTGCPTR GCPtrTss = trHid.u64Base;
1471 uint32_t cbTss = trHid.u32Limit;
1472 Assert( (SelTss & X86_SEL_MASK)
1473 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1474 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1475 if (SelTss & X86_SEL_MASK)
1476 {
1477 Assert(!(SelTss & X86_SEL_LDT));
1478 Assert(trHid.Attr.n.u1DescType == 0);
1479 Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1480 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1481 if (!++cbTss)
1482 cbTss = UINT32_MAX;
1483 }
1484 else
1485 {
1486 Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1487 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1488 cbTss = 0; /* the reset case. */
1489 }
1490 pVM->selm.s.cbGuestTss = cbTss;
1491 pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1492 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1493
1494 /*
1495 * Figure out the size of what need to monitor.
1496 */
1497 /* We're not interested in any 16-bit TSSes. */
1498 uint32_t cbMonitoredTss = cbTss;
1499 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1500 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1501 cbMonitoredTss = 0;
1502
1503 pVM->selm.s.offGuestIoBitmap = 0;
1504 bool fNoRing1Stack = true;
1505 if (cbMonitoredTss)
1506 {
1507 /*
1508 * 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1509 * If VME is enabled we also want to keep an eye on the interrupt
1510 * redirection bitmap.
1511 */
1512 VBOXTSS Tss;
1513 uint32_t cr4 = CPUMGetGuestCR4(pVM);
1514 rc = PGMPhysSimpleReadGCPtr(pVM, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1515 if ( !(cr4 & X86_CR4_VME)
1516 || ( VBOX_SUCCESS(rc)
1517 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1518 && Tss.offIoBitmap > cbTss) /* beyond the end */ /** @todo not sure how the partial case is handled; probably not allowed. */
1519 )
1520 /* No interrupt redirection bitmap, just ESP0 and SS0. */
1521 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1522 else if (RT_SUCCESS(rc))
1523 {
1524 /*
1525 * Everything up to and including the interrupt redirection bitmap. Unfortunately
1526 * this can be quite a large chunk. We use to skip it earlier and just hope it
1527 * was kind of static...
1528 *
1529 * Update the virtual interrupt redirection bitmap while we're here.
1530 * (It is located in the 32 bytes before TR:offIoBitmap.)
1531 */
1532 cbMonitoredTss = Tss.offIoBitmap;
1533 pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1534
1535 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1536 rc = PGMPhysSimpleReadGCPtr(pVM, &pVM->selm.s.Tss.IntRedirBitmap,
1537 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1538 AssertRC(rc);
1539 /** @todo memset the bitmap on failure? */
1540 Log2(("Redirection bitmap:\n"));
1541 Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1542 }
1543 else
1544 {
1545 cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1546 pVM->selm.s.offGuestIoBitmap = 0;
1547 /** @todo memset the bitmap? */
1548 }
1549
1550 /*
1551 * Update the ring 0 stack selector and base address.
1552 */
1553 if (RT_SUCCESS(rc))
1554 {
1555#ifdef LOG_ENABLED
1556 if (LogIsEnabled())
1557 {
1558 uint32_t ssr0, espr0;
1559 SELMGetRing1Stack(pVM, &ssr0, &espr0);
1560 if ((ssr0 & ~1) != Tss.ss0 || espr0 != Tss.esp0)
1561 {
1562 RTGCPHYS GCPhys = NIL_RTGCPHYS;
1563 rc = PGMGstGetPage(pVM, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1564 Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%VGp)\n",
1565 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1566 AssertMsg(ssr0 != Tss.ss0,
1567 ("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%VGp)\n",
1568 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1569 }
1570 Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1571 }
1572#endif /* LOG_ENABLED */
1573 AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1574
1575 /* Update our TSS structure for the guest's ring 1 stack */
1576 selmSetRing1Stack(pVM, Tss.ss0 | 1, Tss.esp0);
1577 pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1578 }
1579 }
1580
1581 /*
1582 * Flush the ring-1 stack and the direct syscall dispatching if we
1583 * cannot obtain SS0:ESP0.
1584 */
1585 if (fNoRing1Stack)
1586 {
1587 selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1588 pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1589
1590 /** @todo handle these dependencies better! */
1591 TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1592 TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1593 }
1594
1595 /*
1596 * Check for monitor changes and apply them.
1597 */
1598 if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1599 || cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1600 {
1601 Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1602 GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1603
1604 /* Release the old range first. */
1605 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1606 {
1607 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1608 AssertRC(rc);
1609 }
1610
1611 /* Register the write handler if TS != 0. */
1612 if (cbMonitoredTss != 0)
1613 {
1614 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1615 0, selmR3GuestTSSWriteHandler,
1616 "selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1617 if (RT_FAILURE(rc))
1618 {
1619 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1620 return rc;
1621 }
1622
1623 /* Update saved Guest TSS info. */
1624 pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1625 pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1626 pVM->selm.s.GCSelTss = SelTss;
1627 }
1628 else
1629 {
1630 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1631 pVM->selm.s.cbMonitoredGuestTss = 0;
1632 pVM->selm.s.GCSelTss = 0;
1633 }
1634 }
1635
1636 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
1637
1638 STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1639 return VINF_SUCCESS;
1640}
1641
1642
1643/**
1644 * Compares the Guest GDT and LDT with the shadow tables.
1645 * This is a VBOX_STRICT only function.
1646 *
1647 * @returns VBox status code.
1648 * @param pVM The VM Handle.
1649 */
1650VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1651{
1652#ifdef VBOX_STRICT
1653 /*
1654 * Get GDTR and check for conflict.
1655 */
1656 VBOXGDTR GDTR;
1657 CPUMGetGuestGDTR(pVM, &GDTR);
1658 if (GDTR.cbGdt == 0)
1659 return VINF_SUCCESS;
1660
1661 if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1662 Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1663
1664 if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1665 Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1666
1667 /*
1668 * Loop thru the GDT checking each entry.
1669 */
1670 RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1671 PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1672 PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1673 while (pGDTE < pGDTEEnd)
1674 {
1675 X86DESC GDTEGuest;
1676 int rc = PGMPhysSimpleReadGCPtr(pVM, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1677 if (RT_SUCCESS(rc))
1678 {
1679 if (pGDTE->Gen.u1DescType || pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1680 {
1681 if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1682 || pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1683 || pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1684 || pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1685 || pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1686 || pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1687 || pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1688 {
1689 unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1690 SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1691 SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1692 }
1693 }
1694 }
1695
1696 /* Advance to the next descriptor. */
1697 GCPtrGDTEGuest += sizeof(X86DESC);
1698 pGDTE++;
1699 }
1700
1701
1702 /*
1703 * LDT?
1704 */
1705 RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
1706 if ((SelLdt & X86_SEL_MASK) == 0)
1707 return VINF_SUCCESS;
1708 if (SelLdt > GDTR.cbGdt)
1709 {
1710 Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1711 return VERR_INTERNAL_ERROR;
1712 }
1713 X86DESC LDTDesc;
1714 int rc = PGMPhysSimpleReadGCPtr(pVM, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1715 if (RT_FAILURE(rc))
1716 {
1717 Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1718 return rc;
1719 }
1720 RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(LDTDesc);
1721 unsigned cbLdt = X86DESC_LIMIT(LDTDesc);
1722 if (LDTDesc.Gen.u1Granularity)
1723 cbLdt = (cbLdt << PAGE_SHIFT) | PAGE_OFFSET_MASK;
1724
1725 /*
1726 * Validate it.
1727 */
1728 if (!cbLdt)
1729 return VINF_SUCCESS;
1730 /** @todo check what intel does about odd limits. */
1731 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1732 if ( LDTDesc.Gen.u1DescType
1733 || LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1734 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1735 {
1736 Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1737 return VERR_INTERNAL_ERROR;
1738 }
1739
1740 /*
1741 * Loop thru the LDT checking each entry.
1742 */
1743 unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1744 PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1745 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1746 while (pLDTE < pLDTEEnd)
1747 {
1748 X86DESC LDTEGuest;
1749 int rc = PGMPhysSimpleReadGCPtr(pVM, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1750 if (RT_SUCCESS(rc))
1751 {
1752 if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1753 || pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1754 || pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1755 || pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1756 || pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1757 || pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1758 || pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1759 {
1760 unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1761 SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1762 SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1763 }
1764 }
1765
1766 /* Advance to the next descriptor. */
1767 GCPtrLDTEGuest += sizeof(X86DESC);
1768 pLDTE++;
1769 }
1770
1771#else /* !VBOX_STRICT */
1772 NOREF(pVM);
1773#endif /* !VBOX_STRICT */
1774
1775 return VINF_SUCCESS;
1776}
1777
1778
1779/**
1780 * Validates the RawR0 TSS values against the one in the Guest TSS.
1781 *
1782 * @returns true if it matches.
1783 * @returns false and assertions on mismatch..
1784 * @param pVM VM Handle.
1785 */
1786VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1787{
1788#ifdef VBOX_STRICT
1789 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
1790 return true;
1791
1792 /*
1793 * Get TR and extract the basic info.
1794 */
1795 CPUMSELREGHID trHid;
1796 RTSEL SelTss = CPUMGetGuestTR(pVM, &trHid);
1797 RTGCPTR GCPtrTss = trHid.u64Base;
1798 uint32_t cbTss = trHid.u32Limit;
1799 Assert( (SelTss & X86_SEL_MASK)
1800 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1801 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1802 if (SelTss & X86_SEL_MASK)
1803 {
1804 AssertReturn(!(SelTss & X86_SEL_LDT), false);
1805 AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1806 AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1807 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1808 false);
1809 if (!++cbTss)
1810 cbTss = UINT32_MAX;
1811 }
1812 else
1813 {
1814 AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1815 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */),
1816 false);
1817 cbTss = 0; /* the reset case. */
1818 }
1819 AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1820 AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1821 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1822 ("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1823 false);
1824 AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1825 || (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1826 ("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1827 false);
1828 AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1829 || (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1830 ("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1831 false);
1832
1833
1834 /*
1835 * Figure out the size of what need to monitor.
1836 */
1837 bool fNoRing1Stack = true;
1838 /* We're not interested in any 16-bit TSSes. */
1839 uint32_t cbMonitoredTss = cbTss;
1840 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1841 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1842 cbMonitoredTss = 0;
1843 if (cbMonitoredTss)
1844 {
1845 VBOXTSS Tss;
1846 uint32_t cr4 = CPUMGetGuestCR4(pVM);
1847 int rc = PGMPhysSimpleReadGCPtr(pVM, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1848 AssertReturn( rc == VINF_SUCCESS
1849 /* Happends early in XP boot during page table switching. */
1850 || ( (rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT)
1851 && !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF)),
1852 false);
1853 if ( !(cr4 & X86_CR4_VME)
1854 || ( VBOX_SUCCESS(rc)
1855 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1856 && Tss.offIoBitmap > cbTss)
1857 )
1858 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1859 else if (RT_SUCCESS(rc))
1860 {
1861 cbMonitoredTss = Tss.offIoBitmap;
1862 AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1863 ("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1864 false);
1865
1866 /* check the bitmap */
1867 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1868 rc = PGMPhysSimpleReadGCPtr(pVM, &Tss.IntRedirBitmap,
1869 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1870 AssertRCReturn(rc, false);
1871 AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
1872 ("offIoBitmap=%#x cbTss=%#x\n"
1873 " Guest: %.32Rhxs\n"
1874 "Shadow: %.32Rhxs\n",
1875 Tss.offIoBitmap, cbTss,
1876 &Tss.IntRedirBitmap[0],
1877 &pVM->selm.s.Tss.IntRedirBitmap[0]),
1878 false);
1879 }
1880 else
1881 cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1882
1883 /*
1884 * Check SS0 and ESP0.
1885 */
1886 if ( !pVM->selm.s.fSyncTSSRing0Stack
1887 && RT_SUCCESS(rc))
1888 {
1889 if ( Tss.esp0 != pVM->selm.s.Tss.esp1
1890 || Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
1891 {
1892 RTGCPHYS GCPhys;
1893 rc = PGMGstGetPage(pVM, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1894 AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
1895 (pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
1896 Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
1897 return false;
1898 }
1899 }
1900 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1901 }
1902 else
1903 {
1904 AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
1905 AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
1906 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1907 }
1908
1909
1910
1911 return true;
1912
1913#else /* !VBOX_STRICT */
1914 NOREF(pVM);
1915 return true;
1916#endif /* !VBOX_STRICT */
1917}
1918
1919
1920/**
1921 * Returns flat address and limit of LDT by LDT selector from guest GDTR.
1922 *
1923 * Fully validate selector.
1924 *
1925 * @returns VBox status.
1926 * @param pVM VM Handle.
1927 * @param SelLdt LDT selector.
1928 * @param ppvLdt Where to store the flat address of LDT.
1929 * @param pcbLimit Where to store LDT limit.
1930 */
1931VMMDECL(int) SELMGetLDTFromSel(PVM pVM, RTSEL SelLdt, PRTGCPTR ppvLdt, unsigned *pcbLimit)
1932{
1933 /* Get guest GDTR. */
1934 VBOXGDTR GDTR;
1935 CPUMGetGuestGDTR(pVM, &GDTR);
1936
1937 /* Check selector TI and GDT limit. */
1938 if ( SelLdt & X86_SEL_LDT
1939 || (SelLdt > GDTR.cbGdt))
1940 return VERR_INVALID_SELECTOR;
1941
1942 /* Read descriptor from GC. */
1943 X86DESC Desc;
1944 int rc = PGMPhysSimpleReadGCPtr(pVM, (void *)&Desc, (RTGCPTR)(GDTR.pGdt + (SelLdt & X86_SEL_MASK)), sizeof(Desc));
1945 if (RT_FAILURE(rc))
1946 {
1947 /* fatal */
1948 AssertMsgFailed(("Can't read LDT descriptor for selector=%04X\n", SelLdt));
1949 return VERR_SELECTOR_NOT_PRESENT;
1950 }
1951
1952 /* Check if LDT descriptor is not present. */
1953 if (Desc.Gen.u1Present == 0)
1954 return VERR_SELECTOR_NOT_PRESENT;
1955
1956 /* Check LDT descriptor type. */
1957 if ( Desc.Gen.u1DescType == 1
1958 || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1959 return VERR_INVALID_SELECTOR;
1960
1961 /* LDT descriptor is ok. */
1962 if (ppvLdt)
1963 {
1964 *ppvLdt = (RTGCPTR)X86DESC_BASE(Desc);
1965 *pcbLimit = X86DESC_LIMIT(Desc);
1966 }
1967 return VINF_SUCCESS;
1968}
1969
1970
1971/**
1972 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
1973 *
1974 * See SELMR3GetSelectorInfo for details.
1975 *
1976 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
1977 *
1978 * @param pVM VM handle.
1979 * @param Sel The selector to get info about.
1980 * @param pSelInfo Where to store the information.
1981 */
1982static int selmR3GetSelectorInfo64(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
1983{
1984 pSelInfo->fHyper = false;
1985
1986 /*
1987 * Read it from the guest descriptor table.
1988 */
1989 X86DESC64 Desc;
1990 VBOXGDTR Gdtr;
1991 RTGCPTR GCPtrDesc;
1992 CPUMGetGuestGDTR(pVM, &Gdtr);
1993 if (!(Sel & X86_SEL_LDT))
1994 {
1995 /* GDT */
1996 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
1997 return VERR_INVALID_SELECTOR;
1998 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
1999 }
2000 else
2001 {
2002 /*
2003 * LDT - must locate the LDT first...
2004 */
2005 RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
2006 if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */
2007 || (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2008 return VERR_INVALID_SELECTOR;
2009 GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2010 int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
2011 if (RT_FAILURE(rc))
2012 return rc;
2013
2014 /* validate the LDT descriptor. */
2015 if (Desc.Gen.u1Present == 0)
2016 return VERR_SELECTOR_NOT_PRESENT;
2017 if ( Desc.Gen.u1DescType == 1
2018 || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2019 return VERR_INVALID_SELECTOR;
2020
2021 unsigned cbLimit = X86DESC_LIMIT(Desc);
2022 if (Desc.Gen.u1Granularity)
2023 cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2024 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2025 return VERR_INVALID_SELECTOR;
2026
2027 /* calc the descriptor location. */
2028 GCPtrDesc = X86DESC64_BASE(Desc);
2029 GCPtrDesc += (Sel & X86_SEL_MASK);
2030 }
2031
2032 /* read the descriptor. */
2033 int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
2034 if (RT_FAILURE(rc))
2035 return rc;
2036
2037 /*
2038 * Extract the base and limit
2039 */
2040 pSelInfo->Sel = Sel;
2041 pSelInfo->Raw64 = Desc;
2042 pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2043 if (Desc.Gen.u1Granularity)
2044 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2045 pSelInfo->GCPtrBase = X86DESC64_BASE(Desc);
2046 pSelInfo->fRealMode = false;
2047
2048 return VINF_SUCCESS;
2049}
2050
2051
2052/**
2053 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2054 *
2055 * See SELMR3GetSelectorInfo for details.
2056 *
2057 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
2058 *
2059 * @param pVM VM handle.
2060 * @param Sel The selector to get info about.
2061 * @param pSelInfo Where to store the information.
2062 */
2063static int selmR3GetSelectorInfo32(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
2064{
2065 /*
2066 * Read the descriptor entry
2067 */
2068 X86DESC Desc;
2069 if ( !(Sel & X86_SEL_LDT)
2070 && ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2071 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2072 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2073 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2074 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK))
2075 )
2076 {
2077 /*
2078 * Hypervisor descriptor.
2079 */
2080 pSelInfo->fHyper = true;
2081 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2082 }
2083 else if (CPUMIsGuestInProtectedMode(pVM))
2084 {
2085 /*
2086 * Read it from the guest descriptor table.
2087 */
2088 pSelInfo->fHyper = false;
2089
2090 VBOXGDTR Gdtr;
2091 RTGCPTR GCPtrDesc;
2092 CPUMGetGuestGDTR(pVM, &Gdtr);
2093 if (!(Sel & X86_SEL_LDT))
2094 {
2095 /* GDT */
2096 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2097 return VERR_INVALID_SELECTOR;
2098 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2099 }
2100 else
2101 {
2102 /*
2103 * LDT - must locate the LDT first...
2104 */
2105 RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
2106 if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */
2107 || (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2108 return VERR_INVALID_SELECTOR;
2109 GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2110 int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
2111 if (RT_FAILURE(rc))
2112 return rc;
2113
2114 /* validate the LDT descriptor. */
2115 if (Desc.Gen.u1Present == 0)
2116 return VERR_SELECTOR_NOT_PRESENT;
2117 if ( Desc.Gen.u1DescType == 1
2118 || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2119 return VERR_INVALID_SELECTOR;
2120
2121 unsigned cbLimit = X86DESC_LIMIT(Desc);
2122 if (Desc.Gen.u1Granularity)
2123 cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2124 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2125 return VERR_INVALID_SELECTOR;
2126
2127 /* calc the descriptor location. */
2128 GCPtrDesc = X86DESC_BASE(Desc);
2129 GCPtrDesc += (Sel & X86_SEL_MASK);
2130 }
2131
2132 /* read the descriptor. */
2133 int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
2134 if (RT_FAILURE(rc))
2135 return rc;
2136 }
2137 else
2138 {
2139 /*
2140 * We're in real mode.
2141 */
2142 pSelInfo->Sel = Sel;
2143 pSelInfo->GCPtrBase = Sel << 4;
2144 pSelInfo->cbLimit = 0xffff;
2145 pSelInfo->fHyper = false;
2146 pSelInfo->fRealMode = true;
2147 memset(&pSelInfo->Raw, 0, sizeof(pSelInfo->Raw));
2148 return VINF_SUCCESS;
2149 }
2150
2151 /*
2152 * Extract the base and limit
2153 */
2154 pSelInfo->Sel = Sel;
2155 pSelInfo->Raw = Desc;
2156 pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2157 if (Desc.Gen.u1Granularity)
2158 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2159 pSelInfo->GCPtrBase = X86DESC_BASE(Desc);
2160 pSelInfo->fRealMode = false;
2161
2162 return VINF_SUCCESS;
2163}
2164
2165
2166/**
2167 * Gets information about a selector.
2168 * Intended for the debugger mostly and will prefer the guest
2169 * descriptor tables over the shadow ones.
2170 *
2171 * @returns VINF_SUCCESS on success.
2172 * @returns VERR_INVALID_SELECTOR if the selector isn't fully inside the descriptor table.
2173 * @returns VERR_SELECTOR_NOT_PRESENT if the selector wasn't present.
2174 * @returns VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the pagetable or page
2175 * backing the selector table wasn't present.
2176 * @returns Other VBox status code on other errors.
2177 *
2178 * @param pVM VM handle.
2179 * @param Sel The selector to get info about.
2180 * @param pSelInfo Where to store the information.
2181 */
2182VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
2183{
2184 AssertPtr(pSelInfo);
2185 if (CPUMIsGuestInLongMode(pVM))
2186 return selmR3GetSelectorInfo64(pVM, Sel, pSelInfo);
2187 return selmR3GetSelectorInfo32(pVM, Sel, pSelInfo);
2188}
2189
2190
2191/**
2192 * Gets information about a selector from the shadow tables.
2193 *
2194 * This is intended to be faster than the SELMR3GetSelectorInfo() method, but requires
2195 * that the caller ensures that the shadow tables are up to date.
2196 *
2197 * @returns VINF_SUCCESS on success.
2198 * @returns VERR_INVALID_SELECTOR if the selector isn't fully inside the descriptor table.
2199 * @returns VERR_SELECTOR_NOT_PRESENT if the selector wasn't present.
2200 * @returns VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the pagetable or page
2201 * backing the selector table wasn't present.
2202 * @returns Other VBox status code on other errors.
2203 *
2204 * @param pVM VM handle.
2205 * @param Sel The selector to get info about.
2206 * @param pSelInfo Where to store the information.
2207 */
2208VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
2209{
2210 Assert(pSelInfo);
2211
2212 /*
2213 * Read the descriptor entry
2214 */
2215 X86DESC Desc;
2216 if (!(Sel & X86_SEL_LDT))
2217 {
2218 /*
2219 * Global descriptor.
2220 */
2221 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2222 pSelInfo->fHyper = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2223 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2224 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2225 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2226 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK);
2227 /** @todo check that the GDT offset is valid. */
2228 }
2229 else
2230 {
2231 /*
2232 * Local Descriptor.
2233 */
2234 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2235 Desc = paLDT[Sel >> X86_SEL_SHIFT];
2236 /** @todo check if the LDT page is actually available. */
2237 /** @todo check that the LDT offset is valid. */
2238 pSelInfo->fHyper = false;
2239 }
2240
2241 /*
2242 * Extract the base and limit
2243 */
2244 pSelInfo->Sel = Sel;
2245 pSelInfo->Raw = Desc;
2246 pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2247 if (Desc.Gen.u1Granularity)
2248 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2249 pSelInfo->GCPtrBase = X86DESC_BASE(Desc);
2250 pSelInfo->fRealMode = false;
2251
2252 return VINF_SUCCESS;
2253}
2254
2255
2256/**
2257 * Formats a descriptor.
2258 *
2259 * @param Desc Descriptor to format.
2260 * @param Sel Selector number.
2261 * @param pszOutput Output buffer.
2262 * @param cchOutput Size of output buffer.
2263 */
2264static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2265{
2266 /*
2267 * Make variable description string.
2268 */
2269 static struct
2270 {
2271 unsigned cch;
2272 const char *psz;
2273 } const aTypes[32] =
2274 {
2275#define STRENTRY(str) { sizeof(str) - 1, str }
2276 /* system */
2277 STRENTRY("Reserved0 "), /* 0x00 */
2278 STRENTRY("TSS16Avail "), /* 0x01 */
2279 STRENTRY("LDT "), /* 0x02 */
2280 STRENTRY("TSS16Busy "), /* 0x03 */
2281 STRENTRY("Call16 "), /* 0x04 */
2282 STRENTRY("Task "), /* 0x05 */
2283 STRENTRY("Int16 "), /* 0x06 */
2284 STRENTRY("Trap16 "), /* 0x07 */
2285 STRENTRY("Reserved8 "), /* 0x08 */
2286 STRENTRY("TSS32Avail "), /* 0x09 */
2287 STRENTRY("ReservedA "), /* 0x0a */
2288 STRENTRY("TSS32Busy "), /* 0x0b */
2289 STRENTRY("Call32 "), /* 0x0c */
2290 STRENTRY("ReservedD "), /* 0x0d */
2291 STRENTRY("Int32 "), /* 0x0e */
2292 STRENTRY("Trap32 "), /* 0x0f */
2293 /* non system */
2294 STRENTRY("DataRO "), /* 0x10 */
2295 STRENTRY("DataRO Accessed "), /* 0x11 */
2296 STRENTRY("DataRW "), /* 0x12 */
2297 STRENTRY("DataRW Accessed "), /* 0x13 */
2298 STRENTRY("DataDownRO "), /* 0x14 */
2299 STRENTRY("DataDownRO Accessed "), /* 0x15 */
2300 STRENTRY("DataDownRW "), /* 0x16 */
2301 STRENTRY("DataDownRW Accessed "), /* 0x17 */
2302 STRENTRY("CodeEO "), /* 0x18 */
2303 STRENTRY("CodeEO Accessed "), /* 0x19 */
2304 STRENTRY("CodeER "), /* 0x1a */
2305 STRENTRY("CodeER Accessed "), /* 0x1b */
2306 STRENTRY("CodeConfEO "), /* 0x1c */
2307 STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2308 STRENTRY("CodeConfER "), /* 0x1e */
2309 STRENTRY("CodeConfER Accessed ") /* 0x1f */
2310#undef SYSENTRY
2311 };
2312#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2313 char szMsg[128];
2314 char *psz = &szMsg[0];
2315 unsigned i = Desc.Gen.u1DescType << 4 | Desc.Gen.u4Type;
2316 memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2317 psz += aTypes[i].cch;
2318
2319 if (Desc.Gen.u1Present)
2320 ADD_STR(psz, "Present ");
2321 else
2322 ADD_STR(psz, "Not-Present ");
2323 if (Desc.Gen.u1Granularity)
2324 ADD_STR(psz, "Page ");
2325 if (Desc.Gen.u1DefBig)
2326 ADD_STR(psz, "32-bit ");
2327 else
2328 ADD_STR(psz, "16-bit ");
2329#undef ADD_STR
2330 *psz = '\0';
2331
2332 /*
2333 * Limit and Base and format the output.
2334 */
2335 uint32_t u32Limit = X86DESC_LIMIT(Desc);
2336 if (Desc.Gen.u1Granularity)
2337 u32Limit = u32Limit << PAGE_SHIFT | PAGE_OFFSET_MASK;
2338 uint32_t u32Base = X86DESC_BASE(Desc);
2339
2340 RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2341 Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2342}
2343
2344
2345/**
2346 * Dumps a descriptor.
2347 *
2348 * @param Desc Descriptor to dump.
2349 * @param Sel Selector number.
2350 * @param pszMsg Message to prepend the log entry with.
2351 */
2352VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2353{
2354 char szOutput[128];
2355 selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2356 Log(("%s: %s\n", pszMsg, szOutput));
2357 NOREF(szOutput[0]);
2358}
2359
2360
2361/**
2362 * Display the shadow gdt.
2363 *
2364 * @param pVM VM Handle.
2365 * @param pHlp The info helpers.
2366 * @param pszArgs Arguments, ignored.
2367 */
2368static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2369{
2370 pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2371 for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2372 {
2373 if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2374 {
2375 char szOutput[128];
2376 selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2377 const char *psz = "";
2378 if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2379 psz = " HyperCS";
2380 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2381 psz = " HyperDS";
2382 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2383 psz = " HyperCS64";
2384 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2385 psz = " HyperTSS";
2386 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2387 psz = " HyperTSSTrap08";
2388 pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2389 }
2390 }
2391}
2392
2393
2394/**
2395 * Display the guest gdt.
2396 *
2397 * @param pVM VM Handle.
2398 * @param pHlp The info helpers.
2399 * @param pszArgs Arguments, ignored.
2400 */
2401static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2402{
2403 VBOXGDTR GDTR;
2404 CPUMGetGuestGDTR(pVM, &GDTR);
2405 RTGCPTR GCPtrGDT = GDTR.pGdt;
2406 unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2407
2408 pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2409 for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2410 {
2411 X86DESC GDTE;
2412 int rc = PGMPhysSimpleReadGCPtr(pVM, &GDTE, GCPtrGDT, sizeof(GDTE));
2413 if (RT_SUCCESS(rc))
2414 {
2415 if (GDTE.Gen.u1Present)
2416 {
2417 char szOutput[128];
2418 selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2419 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2420 }
2421 }
2422 else if (rc == VERR_PAGE_NOT_PRESENT)
2423 {
2424 if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2425 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2426 }
2427 else
2428 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2429 }
2430}
2431
2432
2433/**
2434 * Display the shadow ldt.
2435 *
2436 * @param pVM VM Handle.
2437 * @param pHlp The info helpers.
2438 * @param pszArgs Arguments, ignored.
2439 */
2440static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2441{
2442 unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2443 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2444 pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2445 for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2446 {
2447 if (paLDT[iLDT].Gen.u1Present)
2448 {
2449 char szOutput[128];
2450 selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2451 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2452 }
2453 }
2454}
2455
2456
2457/**
2458 * Display the guest ldt.
2459 *
2460 * @param pVM VM Handle.
2461 * @param pHlp The info helpers.
2462 * @param pszArgs Arguments, ignored.
2463 */
2464static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2465{
2466 RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
2467 if (!(SelLdt & X86_SEL_MASK))
2468 {
2469 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2470 return;
2471 }
2472
2473 RTGCPTR GCPtrLdt;
2474 unsigned cbLdt;
2475 int rc = SELMGetLDTFromSel(pVM, SelLdt, &GCPtrLdt, &cbLdt);
2476 if (RT_FAILURE(rc))
2477 {
2478 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): rc=%Rrc\n", SelLdt, rc);
2479 return;
2480 }
2481
2482 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RGv limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2483 unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2484 for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2485 {
2486 X86DESC LdtE;
2487 int rc = PGMPhysSimpleReadGCPtr(pVM, &LdtE, GCPtrLdt, sizeof(LdtE));
2488 if (RT_SUCCESS(rc))
2489 {
2490 if (LdtE.Gen.u1Present)
2491 {
2492 char szOutput[128];
2493 selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2494 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2495 }
2496 }
2497 else if (rc == VERR_PAGE_NOT_PRESENT)
2498 {
2499 if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2500 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, GCPtrLdt);
2501 }
2502 else
2503 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, rc, GCPtrLdt);
2504 }
2505}
2506
2507
2508/**
2509 * Dumps the hypervisor GDT
2510 *
2511 * @param pVM VM handle.
2512 */
2513VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2514{
2515 DBGFR3Info(pVM, "gdt", NULL, NULL);
2516}
2517
2518
2519/**
2520 * Dumps the hypervisor LDT
2521 *
2522 * @param pVM VM handle.
2523 */
2524VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2525{
2526 DBGFR3Info(pVM, "ldt", NULL, NULL);
2527}
2528
2529
2530/**
2531 * Dumps the guest GDT
2532 *
2533 * @param pVM VM handle.
2534 */
2535VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2536{
2537 DBGFR3Info(pVM, "gdtguest", NULL, NULL);
2538}
2539
2540
2541/**
2542 * Dumps the guest LDT
2543 *
2544 * @param pVM VM handle.
2545 */
2546VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2547{
2548 DBGFR3Info(pVM, "ldtguest", NULL, NULL);
2549}
2550
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette