VirtualBox

source: vbox/trunk/src/VBox/VMM/SELM.cpp@ 18746

Last change on this file since 18746 was 17616, checked in by vboxsync, 16 years ago

Inform SELM about shadow CR3 changes.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 95.5 KB
Line 
1/* $Id: SELM.cpp 17616 2009-03-10 11:08:39Z vboxsync $ */
2/** @file
3 * SELM - The Selector Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_selm SELM - The Selector Manager
23 *
24 * SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
25 * of a few hyper selector for the raw-mode context. In the hardware assisted
26 * virtualization mode its only task is to decode entries in the guest GDT or
27 * LDT once in a while.
28 *
29 * @see grp_selm
30 *
31 *
32 * @section seg_selm_shadowing Shadowing
33 *
34 * SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
35 * work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
36 * The idea is to do it in a more on-demand fashion when we get time. There
37 * also a whole bunch of issues with the current synchronization of all three
38 * tables, see notes and todos in the code.
39 *
40 * When the guest makes changes to the GDT we will try update the shadow copy
41 * without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
42 *
43 * When the guest make LDT changes we'll trigger a full resync of the LDT
44 * (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
45 *
46 * The TSS shadowing is limited to the fields we need to care about, namely SS0
47 * and ESP0. The Patch Manager makes use of these. We monitor updates to the
48 * guest TSS and will try keep our SS0 and ESP0 copies up to date this way
49 * rather than go the SELMR3SyncTSS() route.
50 *
51 * When in raw-mode SELM also injects a few extra GDT selectors which are used
52 * by the raw-mode (hyper) context. These start their life at the high end of
53 * the table and will be relocated when the guest tries to make use of them...
54 * Well, that was that idea at least, only the code isn't quite there yet which
55 * is why we have trouble with guests which actually have a full sized GDT.
56 *
57 * So, the summary of the current GDT, LDT and TSS shadowing is that there is a
58 * lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
59 *
60 */
61
62/*******************************************************************************
63* Header Files *
64*******************************************************************************/
65#define LOG_GROUP LOG_GROUP_SELM
66#include <VBox/selm.h>
67#include <VBox/cpum.h>
68#include <VBox/stam.h>
69#include <VBox/mm.h>
70#include <VBox/ssm.h>
71#include <VBox/pgm.h>
72#include <VBox/trpm.h>
73#include <VBox/dbgf.h>
74#include "SELMInternal.h"
75#include <VBox/vm.h>
76#include <VBox/err.h>
77#include <VBox/param.h>
78
79#include <iprt/assert.h>
80#include <VBox/log.h>
81#include <iprt/asm.h>
82#include <iprt/string.h>
83#include <iprt/thread.h>
84#include <iprt/string.h>
85
86
87/**
88 * Enable or disable tracking of Guest's GDT/LDT/TSS.
89 * @{
90 */
91#define SELM_TRACK_GUEST_GDT_CHANGES
92#define SELM_TRACK_GUEST_LDT_CHANGES
93#define SELM_TRACK_GUEST_TSS_CHANGES
94/** @} */
95
96/**
97 * Enable or disable tracking of Shadow GDT/LDT/TSS.
98 * @{
99 */
100#define SELM_TRACK_SHADOW_GDT_CHANGES
101#define SELM_TRACK_SHADOW_LDT_CHANGES
102#define SELM_TRACK_SHADOW_TSS_CHANGES
103/** @} */
104
105
106/** SELM saved state version. */
107#define SELM_SAVED_STATE_VERSION 5
108
109
110/*******************************************************************************
111* Internal Functions *
112*******************************************************************************/
113static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
114static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
115static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
116static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
117static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
118static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
119static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
120static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
121static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
122static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
123//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
124//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125
126
127
128/**
129 * Initializes the SELM.
130 *
131 * @returns VBox status code.
132 * @param pVM The VM to operate on.
133 */
134VMMR3DECL(int) SELMR3Init(PVM pVM)
135{
136 LogFlow(("SELMR3Init\n"));
137
138 /*
139 * Assert alignment and sizes.
140 * (The TSS block requires contiguous back.)
141 */
142 AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
143 AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
144#if 0 /* doesn't work */
145 AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
146 AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
147#endif
148 AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
149 AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
150 AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
151
152 /*
153 * Init the structure.
154 */
155 pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
156 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
157 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
158 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
159 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
160 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
161
162 /*
163 * Allocate GDT table.
164 */
165 int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
166 PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
167 AssertRCReturn(rc, rc);
168
169 /*
170 * Allocate LDT area.
171 */
172 rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
173 AssertRCReturn(rc, rc);
174
175 /*
176 * Init Guest's and Shadow GDT, LDT, TSS changes control variables.
177 */
178 pVM->selm.s.cbEffGuestGdtLimit = 0;
179 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
180 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
181 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
182
183 pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
184 pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
185 pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
186 pVM->selm.s.GCSelTss = RTSEL_MAX;
187
188 pVM->selm.s.fDisableMonitoring = false;
189 pVM->selm.s.fSyncTSSRing0Stack = false;
190
191 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
192 * for I/O operations. */
193 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
194 /* bit set to 1 means no redirection */
195 memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
196
197 /*
198 * Register the saved state data unit.
199 */
200 rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
201 NULL, selmR3Save, NULL,
202 NULL, selmR3Load, selmR3LoadDone);
203 if (RT_FAILURE(rc))
204 return rc;
205
206 /*
207 * Statistics.
208 */
209 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
210 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
211 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
212 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
213 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
214 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
215 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
216 STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
217 STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
218
219 STAM_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
220 STAM_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
221
222 /*
223 * Default action when entering raw mode for the first time
224 */
225 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
226 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
227 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
228
229 /*
230 * Register info handlers.
231 */
232 DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
233 DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
234 DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
235 DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
236 //DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
237 //DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
238
239 return rc;
240}
241
242
243/**
244 * Finalizes HMA page attributes.
245 *
246 * @returns VBox status code.
247 * @param pVM The VM handle.
248 */
249VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
250{
251 /** @cfgm{/DoubleFault,bool,false}
252 * Enables catching of double faults in the raw-mode context VMM code. This can
253 * be used when the tripple faults or hangs occure and one suspect an unhandled
254 * double fault. This is not enabled by default because it means making the
255 * hyper selectors writeable for all supervisor code, including the guest's.
256 * The double fault is a task switch and thus requires write access to the GDT
257 * of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
258 * 8 TSS for the back link.
259 */
260 bool f;
261#if defined(DEBUG_bird)
262 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
263#else
264 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
265#endif
266 AssertLogRelRCReturn(rc, rc);
267 if (f)
268 {
269 PX86DESC paGdt = pVM->selm.s.paGdtR3;
270 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
271 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
272 AssertRC(rc);
273 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
274 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
275 AssertRC(rc);
276 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
277 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
278 AssertRC(rc);
279 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
280 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
281 AssertRC(rc);
282 }
283 return VINF_SUCCESS;
284}
285
286
287/**
288 * Setup the hypervisor GDT selectors in our shadow table
289 *
290 * @param pVM The VM handle.
291 */
292static void selmR3SetupHyperGDTSelectors(PVM pVM)
293{
294 PX86DESC paGdt = pVM->selm.s.paGdtR3;
295
296 /*
297 * Set up global code and data descriptors for use in the guest context.
298 * Both are wide open (base 0, limit 4GB)
299 */
300 PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
301 pDesc->Gen.u16LimitLow = 0xffff;
302 pDesc->Gen.u4LimitHigh = 0xf;
303 pDesc->Gen.u16BaseLow = 0;
304 pDesc->Gen.u8BaseHigh1 = 0;
305 pDesc->Gen.u8BaseHigh2 = 0;
306 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
307 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
308 pDesc->Gen.u2Dpl = 0; /* supervisor */
309 pDesc->Gen.u1Present = 1;
310 pDesc->Gen.u1Available = 0;
311 pDesc->Gen.u1Long = 0;
312 pDesc->Gen.u1DefBig = 1; /* def 32 bit */
313 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
314
315 /* data */
316 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
317 pDesc->Gen.u16LimitLow = 0xffff;
318 pDesc->Gen.u4LimitHigh = 0xf;
319 pDesc->Gen.u16BaseLow = 0;
320 pDesc->Gen.u8BaseHigh1 = 0;
321 pDesc->Gen.u8BaseHigh2 = 0;
322 pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
323 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
324 pDesc->Gen.u2Dpl = 0; /* supervisor */
325 pDesc->Gen.u1Present = 1;
326 pDesc->Gen.u1Available = 0;
327 pDesc->Gen.u1Long = 0;
328 pDesc->Gen.u1DefBig = 1; /* big */
329 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
330
331 /* 64-bit mode code (& data?) */
332 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
333 pDesc->Gen.u16LimitLow = 0xffff;
334 pDesc->Gen.u4LimitHigh = 0xf;
335 pDesc->Gen.u16BaseLow = 0;
336 pDesc->Gen.u8BaseHigh1 = 0;
337 pDesc->Gen.u8BaseHigh2 = 0;
338 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
339 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
340 pDesc->Gen.u2Dpl = 0; /* supervisor */
341 pDesc->Gen.u1Present = 1;
342 pDesc->Gen.u1Available = 0;
343 pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
344 pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
345 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
346
347 /*
348 * TSS descriptor
349 */
350 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
351 RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
352 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
353 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
354 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
355 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
356 pDesc->Gen.u4LimitHigh = 0;
357 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
358 pDesc->Gen.u1DescType = 0; /* system */
359 pDesc->Gen.u2Dpl = 0; /* supervisor */
360 pDesc->Gen.u1Present = 1;
361 pDesc->Gen.u1Available = 0;
362 pDesc->Gen.u1Long = 0;
363 pDesc->Gen.u1DefBig = 0;
364 pDesc->Gen.u1Granularity = 0; /* byte limit */
365
366 /*
367 * TSS descriptor for trap 08
368 */
369 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
370 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
371 pDesc->Gen.u4LimitHigh = 0;
372 RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
373 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
374 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
375 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
376 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
377 pDesc->Gen.u1DescType = 0; /* system */
378 pDesc->Gen.u2Dpl = 0; /* supervisor */
379 pDesc->Gen.u1Present = 1;
380 pDesc->Gen.u1Available = 0;
381 pDesc->Gen.u1Long = 0;
382 pDesc->Gen.u1DefBig = 0;
383 pDesc->Gen.u1Granularity = 0; /* byte limit */
384}
385
386/**
387 * Applies relocations to data and code managed by this
388 * component. This function will be called at init and
389 * whenever the VMM need to relocate it self inside the GC.
390 *
391 * @param pVM The VM.
392 */
393VMMR3DECL(void) SELMR3Relocate(PVM pVM)
394{
395 PX86DESC paGdt = pVM->selm.s.paGdtR3;
396 LogFlow(("SELMR3Relocate\n"));
397
398 /*
399 * Update GDTR and selector.
400 */
401 CPUMSetHyperGDTR(pVM, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
402
403 /** @todo selector relocations should be a seperate operation? */
404 CPUMSetHyperCS(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
405 CPUMSetHyperDS(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
406 CPUMSetHyperES(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
407 CPUMSetHyperSS(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
408 CPUMSetHyperTR(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
409
410 selmR3SetupHyperGDTSelectors(pVM);
411
412/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
413/** @todo PGM knows the proper CR3 values these days, not CPUM. */
414 /*
415 * Update the TSSes.
416 */
417 /* Current TSS */
418 pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVM);
419 pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
420 pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVM);
421 pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
422 pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
423 pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
424 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
425
426 /* trap 08 */
427 pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM); /* this should give use better survival chances. */
428 pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
429 pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
430 pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVM) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
431 pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
432 pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
433 pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
434 pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
435 pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
436 pVM->selm.s.TssTrap08.fs = 0;
437 pVM->selm.s.TssTrap08.gs = 0;
438 pVM->selm.s.TssTrap08.selLdt = 0;
439 pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
440 pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
441 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
442 pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
443 pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
444 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
445 pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
446 pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
447 /* TRPM will be updating the eip */
448
449 if (!pVM->selm.s.fDisableMonitoring)
450 {
451 /*
452 * Update shadow GDT/LDT/TSS write access handlers.
453 */
454 int rc;
455#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
456 if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
457 {
458 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
459 AssertRC(rc);
460 }
461 pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
462 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
463 pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
464 0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
465 AssertRC(rc);
466#endif
467#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
468 if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
469 {
470 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
471 AssertRC(rc);
472 }
473 pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
474 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
475 pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
476 0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
477 AssertRC(rc);
478#endif
479
480 /*
481 * Update the GC LDT region handler and address.
482 */
483#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
484 if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
485 {
486 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
487 AssertRC(rc);
488 }
489#endif
490 pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
491#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
492 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
493 pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
494 0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
495 AssertRC(rc);
496#endif
497 }
498}
499
500
501/**
502 * Terminates the SELM.
503 *
504 * Termination means cleaning up and freeing all resources,
505 * the VM it self is at this point powered off or suspended.
506 *
507 * @returns VBox status code.
508 * @param pVM The VM to operate on.
509 */
510VMMR3DECL(int) SELMR3Term(PVM pVM)
511{
512 return 0;
513}
514
515
516/**
517 * The VM is being reset.
518 *
519 * For the SELM component this means that any GDT/LDT/TSS monitors
520 * needs to be removed.
521 *
522 * @param pVM VM handle.
523 */
524VMMR3DECL(void) SELMR3Reset(PVM pVM)
525{
526 LogFlow(("SELMR3Reset:\n"));
527 VM_ASSERT_EMT(pVM);
528
529 /*
530 * Uninstall guest GDT/LDT/TSS write access handlers.
531 */
532 int rc;
533#ifdef SELM_TRACK_GUEST_GDT_CHANGES
534 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
535 {
536 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
537 AssertRC(rc);
538 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
539 pVM->selm.s.GuestGdtr.cbGdt = 0;
540 }
541 pVM->selm.s.fGDTRangeRegistered = false;
542#endif
543#ifdef SELM_TRACK_GUEST_LDT_CHANGES
544 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
545 {
546 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
547 AssertRC(rc);
548 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
549 }
550#endif
551#ifdef SELM_TRACK_GUEST_TSS_CHANGES
552 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
553 {
554 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
555 AssertRC(rc);
556 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
557 pVM->selm.s.GCSelTss = RTSEL_MAX;
558 }
559#endif
560
561 /*
562 * Re-initialize other members.
563 */
564 pVM->selm.s.cbLdtLimit = 0;
565 pVM->selm.s.offLdtHyper = 0;
566 pVM->selm.s.cbMonitoredGuestTss = 0;
567
568 pVM->selm.s.fSyncTSSRing0Stack = false;
569
570 /*
571 * Default action when entering raw mode for the first time
572 */
573 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
574 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
575 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
576}
577
578/**
579 * Disable GDT/LDT/TSS monitoring and syncing
580 *
581 * @param pVM The VM to operate on.
582 */
583VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
584{
585 /*
586 * Uninstall guest GDT/LDT/TSS write access handlers.
587 */
588 int rc;
589#ifdef SELM_TRACK_GUEST_GDT_CHANGES
590 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
591 {
592 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
593 AssertRC(rc);
594 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
595 pVM->selm.s.GuestGdtr.cbGdt = 0;
596 }
597 pVM->selm.s.fGDTRangeRegistered = false;
598#endif
599#ifdef SELM_TRACK_GUEST_LDT_CHANGES
600 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
601 {
602 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
603 AssertRC(rc);
604 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
605 }
606#endif
607#ifdef SELM_TRACK_GUEST_TSS_CHANGES
608 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
609 {
610 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
611 AssertRC(rc);
612 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
613 pVM->selm.s.GCSelTss = RTSEL_MAX;
614 }
615#endif
616
617 /*
618 * Unregister shadow GDT/LDT/TSS write access handlers.
619 */
620#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
621 if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
622 {
623 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
624 AssertRC(rc);
625 pVM->selm.s.paGdtRC = NIL_RTRCPTR;
626 }
627#endif
628#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
629 if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
630 {
631 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
632 AssertRC(rc);
633 pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
634 }
635#endif
636#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
637 if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
638 {
639 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
640 AssertRC(rc);
641 pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
642 }
643#endif
644
645 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
646 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
647 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
648
649 pVM->selm.s.fDisableMonitoring = true;
650}
651
652
653/**
654 * Execute state save operation.
655 *
656 * @returns VBox status code.
657 * @param pVM VM Handle.
658 * @param pSSM SSM operation handle.
659 */
660static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
661{
662 LogFlow(("selmR3Save:\n"));
663
664 /*
665 * Save the basic bits - fortunately all the other things can be resynced on load.
666 */
667 PSELM pSelm = &pVM->selm.s;
668
669 SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
670 SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
671 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
672 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
673 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
674 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
675 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
676 return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
677}
678
679
680/**
681 * Execute state load operation.
682 *
683 * @returns VBox status code.
684 * @param pVM VM Handle.
685 * @param pSSM SSM operation handle.
686 * @param u32Version Data layout version.
687 */
688static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
689{
690 LogFlow(("selmR3Load:\n"));
691
692 /*
693 * Validate version.
694 */
695 if (u32Version != SELM_SAVED_STATE_VERSION)
696 {
697 AssertMsgFailed(("selmR3Load: Invalid version u32Version=%d!\n", u32Version));
698 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
699 }
700
701 /*
702 * Do a reset.
703 */
704 SELMR3Reset(pVM);
705
706 /* Get the monitoring flag. */
707 SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
708
709 /* Get the TSS state flag. */
710 SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
711
712 /*
713 * Get the selectors.
714 */
715 RTSEL SelCS;
716 SSMR3GetSel(pSSM, &SelCS);
717 RTSEL SelDS;
718 SSMR3GetSel(pSSM, &SelDS);
719 RTSEL SelCS64;
720 SSMR3GetSel(pSSM, &SelCS64);
721 RTSEL SelDS64;
722 SSMR3GetSel(pSSM, &SelDS64);
723 RTSEL SelTSS;
724 SSMR3GetSel(pSSM, &SelTSS);
725 RTSEL SelTSSTrap08;
726 SSMR3GetSel(pSSM, &SelTSSTrap08);
727
728 /* Copy the selectors; they will be checked during relocation. */
729 PSELM pSelm = &pVM->selm.s;
730 pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
731 pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
732 pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
733 pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
734 pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
735
736 return VINF_SUCCESS;
737}
738
739
740/**
741 * Sync the GDT, LDT and TSS after loading the state.
742 *
743 * Just to play save, we set the FFs to force syncing before
744 * executing GC code.
745 *
746 * @returns VBox status code.
747 * @param pVM VM Handle.
748 * @param pSSM SSM operation handle.
749 */
750static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
751{
752 LogFlow(("selmR3LoadDone:\n"));
753
754 /*
755 * Don't do anything if it's a load failure.
756 */
757 int rc = SSMR3HandleGetStatus(pSSM);
758 if (RT_FAILURE(rc))
759 return VINF_SUCCESS;
760
761 /*
762 * Do the syncing if we're in protected mode.
763 */
764 if (PGMGetGuestMode(pVM) != PGMMODE_REAL)
765 {
766 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
767 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
768 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
769 SELMR3UpdateFromCPUM(pVM);
770 }
771
772 /*
773 * Flag everything for resync on next raw mode entry.
774 */
775 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
776 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
777 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
778
779 return VINF_SUCCESS;
780}
781
782
783/**
784 * Updates the Guest GDT & LDT virtualization based on current CPU state.
785 *
786 * @returns VBox status code.
787 * @param pVM The VM to operate on.
788 */
789VMMR3DECL(int) SELMR3UpdateFromCPUM(PVM pVM)
790{
791 int rc = VINF_SUCCESS;
792
793 if (pVM->selm.s.fDisableMonitoring)
794 {
795 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
796 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
797 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
798
799 return VINF_SUCCESS;
800 }
801
802 STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
803
804 /*
805 * GDT sync
806 */
807 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_GDT))
808 {
809 /*
810 * Always assume the best
811 */
812 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
813
814 /* If the GDT was changed, then make sure the LDT is checked too */
815 /** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
816 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
817 /* Same goes for the TSS selector */
818 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
819
820 /*
821 * Get the GDTR and check if there is anything to do (there usually is).
822 */
823 VBOXGDTR GDTR;
824 CPUMGetGuestGDTR(pVM, &GDTR);
825 if (GDTR.cbGdt < sizeof(X86DESC))
826 {
827 Log(("No GDT entries...\n"));
828 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
829 return VINF_SUCCESS;
830 }
831
832 /*
833 * Read the Guest GDT.
834 * ASSUMES that the entire GDT is in memory.
835 */
836 RTUINT cbEffLimit = GDTR.cbGdt;
837 PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
838 rc = PGMPhysSimpleReadGCPtr(pVM, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
839 if (RT_FAILURE(rc))
840 {
841 /*
842 * Read it page by page.
843 *
844 * Keep track of the last valid page and delay memsets and
845 * adjust cbEffLimit to reflect the effective size. The latter
846 * is something we do in the belief that the guest will probably
847 * never actually commit the last page, thus allowing us to keep
848 * our selectors in the high end of the GDT.
849 */
850 RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
851 RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
852 uint8_t *pu8Dst = (uint8_t *)&pVM->selm.s.paGdtR3[1];
853 uint8_t *pu8DstInvalid = pu8Dst;
854
855 while (cbLeft)
856 {
857 RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
858 cb = RT_MIN(cb, cbLeft);
859 rc = PGMPhysSimpleReadGCPtr(pVM, pu8Dst, GCPtrSrc, cb);
860 if (RT_SUCCESS(rc))
861 {
862 if (pu8DstInvalid != pu8Dst)
863 memset(pu8DstInvalid, 0, pu8Dst - pu8DstInvalid);
864 GCPtrSrc += cb;
865 pu8Dst += cb;
866 pu8DstInvalid = pu8Dst;
867 }
868 else if ( rc == VERR_PAGE_NOT_PRESENT
869 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
870 {
871 GCPtrSrc += cb;
872 pu8Dst += cb;
873 }
874 else
875 {
876 AssertReleaseMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
877 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
878 return VERR_NOT_IMPLEMENTED;
879 }
880 cbLeft -= cb;
881 }
882
883 /* any invalid pages at the end? */
884 if (pu8DstInvalid != pu8Dst)
885 {
886 cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
887 /* If any GDTEs was invalidated, zero them. */
888 if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
889 memset(pu8DstInvalid + cbEffLimit + 1, 0, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
890 }
891
892 /* keep track of the effective limit. */
893 if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
894 {
895 Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
896 pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
897 pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
898 }
899 }
900
901 /*
902 * Check if the Guest GDT intrudes on our GDT entries.
903 */
904 /** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
905 RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
906 if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
907 {
908 PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
909 PX86DESC pGDTE = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
910 int iGDT = 0;
911
912 Log(("Internal SELM GDT conflict: use non-present entries\n"));
913 STAM_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
914 while (pGDTE > pGDTEStart)
915 {
916 /* We can reuse non-present entries */
917 if (!pGDTE->Gen.u1Present)
918 {
919 aHyperSel[iGDT] = ((uintptr_t)pGDTE - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
920 aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
921 Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
922 iGDT++;
923 if (iGDT >= SELM_HYPER_SEL_MAX)
924 break;
925 }
926
927 pGDTE--;
928 }
929 if (iGDT != SELM_HYPER_SEL_MAX)
930 {
931 AssertReleaseMsgFailed(("Internal SELM GDT conflict.\n"));
932 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
933 return VERR_NOT_IMPLEMENTED;
934 }
935 }
936 else
937 {
938 aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
939 aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
940 aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
941 aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
942 aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
943 }
944
945 /*
946 * Work thru the copied GDT entries adjusting them for correct virtualization.
947 */
948 PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
949 while (pGDTE < pGDTEEnd)
950 {
951 if (pGDTE->Gen.u1Present)
952 {
953 /*
954 * Code and data selectors are generally 1:1, with the
955 * 'little' adjustment we do for DPL 0 selectors.
956 */
957 if (pGDTE->Gen.u1DescType)
958 {
959 /*
960 * Hack for A-bit against Trap E on read-only GDT.
961 */
962 /** @todo Fix this by loading ds and cs before turning off WP. */
963 pGDTE->Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
964
965 /*
966 * All DPL 0 code and data segments are squeezed into DPL 1.
967 *
968 * We're skipping conforming segments here because those
969 * cannot give us any trouble.
970 */
971 if ( pGDTE->Gen.u2Dpl == 0
972 && (pGDTE->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
973 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
974 pGDTE->Gen.u2Dpl = 1;
975 }
976 else
977 {
978 /*
979 * System type selectors are marked not present.
980 * Recompiler or special handling is required for these.
981 */
982 /** @todo what about interrupt gates and rawr0? */
983 pGDTE->Gen.u1Present = 0;
984 }
985 }
986
987 /* Next GDT entry. */
988 pGDTE++;
989 }
990
991 /*
992 * Check if our hypervisor selectors were changed.
993 */
994 if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
995 || aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
996 || aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
997 || aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
998 || aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
999 {
1000 /* Reinitialize our hypervisor GDTs */
1001 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
1002 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
1003 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
1004 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
1005 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1006
1007 STAM_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
1008
1009 /*
1010 * Do the relocation callbacks to let everyone update their hyper selector dependencies.
1011 * (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
1012 */
1013 VMR3Relocate(pVM, 0);
1014 }
1015 else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
1016 /* We overwrote all entries above, so we have to save them again. */
1017 selmR3SetupHyperGDTSelectors(pVM);
1018
1019 /*
1020 * Adjust the cached GDT limit.
1021 * Any GDT entries which have been removed must be cleared.
1022 */
1023 if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1024 {
1025 if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1026 memset(pGDTE, 0, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1027#ifndef SELM_TRACK_GUEST_GDT_CHANGES
1028 pVM->selm.s.GuestGdtr.cbGdt = GDTR.cbGdt;
1029#endif
1030 }
1031
1032#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1033 /*
1034 * Check if Guest's GDTR is changed.
1035 */
1036 if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1037 || GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1038 {
1039 Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1040
1041 /*
1042 * [Re]Register write virtual handler for guest's GDT.
1043 */
1044 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1045 {
1046 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1047 AssertRC(rc);
1048 }
1049
1050 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1051 0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0, "Guest GDT write access handler");
1052 if (RT_FAILURE(rc))
1053 return rc;
1054
1055 /* Update saved Guest GDTR. */
1056 pVM->selm.s.GuestGdtr = GDTR;
1057 pVM->selm.s.fGDTRangeRegistered = true;
1058 }
1059#endif
1060 }
1061
1062 /*
1063 * TSS sync
1064 */
1065 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
1066 {
1067 SELMR3SyncTSS(pVM);
1068 }
1069
1070 /*
1071 * LDT sync
1072 */
1073 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_LDT))
1074 {
1075 /*
1076 * Always assume the best
1077 */
1078 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
1079
1080 /*
1081 * LDT handling is done similarly to the GDT handling with a shadow
1082 * array. However, since the LDT is expected to be swappable (at least
1083 * some ancient OSes makes it swappable) it must be floating and
1084 * synced on a per-page basis.
1085 *
1086 * Eventually we will change this to be fully on demand. Meaning that
1087 * we will only sync pages containing LDT selectors actually used and
1088 * let the #PF handler lazily sync pages as they are used.
1089 * (This applies to GDT too, when we start making OS/2 fast.)
1090 */
1091
1092 /*
1093 * First, determin the current LDT selector.
1094 */
1095 RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
1096 if ((SelLdt & X86_SEL_MASK) == 0)
1097 {
1098 /* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1099 CPUMSetHyperLDTR(pVM, 0);
1100#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1101 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1102 {
1103 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1104 AssertRC(rc);
1105 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1106 }
1107#endif
1108 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1109 return VINF_SUCCESS;
1110 }
1111
1112 /*
1113 * Get the LDT selector.
1114 */
1115 PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1116 RTGCPTR GCPtrLdt = X86DESC_BASE(*pDesc);
1117 unsigned cbLdt = X86DESC_LIMIT(*pDesc);
1118 if (pDesc->Gen.u1Granularity)
1119 cbLdt = (cbLdt << PAGE_SHIFT) | PAGE_OFFSET_MASK;
1120
1121 /*
1122 * Validate it.
1123 */
1124 if ( !cbLdt
1125 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1126 || pDesc->Gen.u1DescType
1127 || pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1128 {
1129 AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1130
1131 /* cbLdt > 0:
1132 * This is quite impossible, so we do as most people do when faced with
1133 * the impossible, we simply ignore it.
1134 */
1135 CPUMSetHyperLDTR(pVM, 0);
1136#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1137 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1138 {
1139 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1140 AssertRC(rc);
1141 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1142 }
1143#endif
1144 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1145 return VINF_SUCCESS;
1146 }
1147 /** @todo check what intel does about odd limits. */
1148 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1149
1150 /*
1151 * Use the cached guest ldt address if the descriptor has already been modified (see below)
1152 * (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1153 */
1154 if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1155 GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1156
1157
1158#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1159 /** @todo Handle only present LDT segments. */
1160 // if (pDesc->Gen.u1Present)
1161 {
1162 /*
1163 * Check if Guest's LDT address/limit is changed.
1164 */
1165 if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1166 || cbLdt != pVM->selm.s.cbLdtLimit)
1167 {
1168 Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1169 pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1170
1171 /*
1172 * [Re]Register write virtual handler for guest's GDT.
1173 * In the event of LDT overlapping something, don't install it just assume it's being updated.
1174 */
1175 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1176 {
1177 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1178 AssertRC(rc);
1179 }
1180#ifdef DEBUG
1181 if (pDesc->Gen.u1Present)
1182 Log(("LDT selector marked not present!!\n"));
1183#endif
1184 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1185 0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1186 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1187 {
1188 /** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1189 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1190 Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1191 GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1192 }
1193 else if (RT_SUCCESS(rc))
1194 pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1195 else
1196 {
1197 CPUMSetHyperLDTR(pVM, 0);
1198 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1199 return rc;
1200 }
1201
1202 pVM->selm.s.cbLdtLimit = cbLdt;
1203 }
1204 }
1205#else
1206 pVM->selm.s.cbLdtLimit = cbLdt;
1207#endif
1208
1209 /*
1210 * Calc Shadow LDT base.
1211 */
1212 unsigned off;
1213 pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1214 RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1215 PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1216
1217 /*
1218 * Enable the LDT selector in the shadow GDT.
1219 */
1220 pDesc->Gen.u1Present = 1;
1221 pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1222 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1223 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1224 pDesc->Gen.u1Available = 0;
1225 pDesc->Gen.u1Long = 0;
1226 if (cbLdt > 0xffff)
1227 {
1228 cbLdt = 0xffff;
1229 pDesc->Gen.u4LimitHigh = 0;
1230 pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1231 }
1232
1233 /*
1234 * Set Hyper LDTR and notify TRPM.
1235 */
1236 CPUMSetHyperLDTR(pVM, SelLdt);
1237
1238 /*
1239 * Loop synchronising the LDT page by page.
1240 */
1241 /** @todo investigate how intel handle various operations on half present cross page entries. */
1242 off = GCPtrLdt & (sizeof(X86DESC) - 1);
1243 AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1244
1245 /* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1246 unsigned cbLeft = cbLdt + 1;
1247 PX86DESC pLDTE = pShadowLDT;
1248 while (cbLeft)
1249 {
1250 /*
1251 * Read a chunk.
1252 */
1253 unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1254 if (cbChunk > cbLeft)
1255 cbChunk = cbLeft;
1256 rc = PGMPhysSimpleReadGCPtr(pVM, pShadowLDT, GCPtrLdt, cbChunk);
1257 if (RT_SUCCESS(rc))
1258 {
1259 /*
1260 * Mark page
1261 */
1262 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D);
1263 AssertRC(rc);
1264
1265 /*
1266 * Loop thru the available LDT entries.
1267 * Figure out where to start and end and the potential cross pageness of
1268 * things adds a little complexity. pLDTE is updated there and not in the
1269 * 'next' part of the loop. The pLDTEEnd is inclusive.
1270 */
1271 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1272 if (pLDTE + 1 < pShadowLDT)
1273 pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1274 while (pLDTE <= pLDTEEnd)
1275 {
1276 if (pLDTE->Gen.u1Present)
1277 {
1278 /*
1279 * Code and data selectors are generally 1:1, with the
1280 * 'little' adjustment we do for DPL 0 selectors.
1281 */
1282 if (pLDTE->Gen.u1DescType)
1283 {
1284 /*
1285 * Hack for A-bit against Trap E on read-only GDT.
1286 */
1287 /** @todo Fix this by loading ds and cs before turning off WP. */
1288 if (!(pLDTE->Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1289 pLDTE->Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1290
1291 /*
1292 * All DPL 0 code and data segments are squeezed into DPL 1.
1293 *
1294 * We're skipping conforming segments here because those
1295 * cannot give us any trouble.
1296 */
1297 if ( pLDTE->Gen.u2Dpl == 0
1298 && (pLDTE->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
1299 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
1300 pLDTE->Gen.u2Dpl = 1;
1301 }
1302 else
1303 {
1304 /*
1305 * System type selectors are marked not present.
1306 * Recompiler or special handling is required for these.
1307 */
1308 /** @todo what about interrupt gates and rawr0? */
1309 pLDTE->Gen.u1Present = 0;
1310 }
1311 }
1312
1313 /* Next LDT entry. */
1314 pLDTE++;
1315 }
1316 }
1317 else
1318 {
1319 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1320 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1321 AssertRC(rc);
1322 }
1323
1324 /*
1325 * Advance to the next page.
1326 */
1327 cbLeft -= cbChunk;
1328 GCPtrShadowLDT += cbChunk;
1329 pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1330 GCPtrLdt += cbChunk;
1331 }
1332 }
1333
1334 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1335 return VINF_SUCCESS;
1336}
1337
1338
1339/**
1340 * \#PF Handler callback for virtual access handler ranges.
1341 *
1342 * Important to realize that a physical page in a range can have aliases, and
1343 * for ALL and WRITE handlers these will also trigger.
1344 *
1345 * @returns VINF_SUCCESS if the handler have carried out the operation.
1346 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1347 * @param pVM VM Handle.
1348 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1349 * @param pvPtr The HC mapping of that address.
1350 * @param pvBuf What the guest is reading/writing.
1351 * @param cbBuf How much it's reading/writing.
1352 * @param enmAccessType The access type.
1353 * @param pvUser User argument.
1354 */
1355static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1356{
1357 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1358 Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1359 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
1360
1361 return VINF_PGM_HANDLER_DO_DEFAULT;
1362}
1363
1364
1365/**
1366 * \#PF Handler callback for virtual access handler ranges.
1367 *
1368 * Important to realize that a physical page in a range can have aliases, and
1369 * for ALL and WRITE handlers these will also trigger.
1370 *
1371 * @returns VINF_SUCCESS if the handler have carried out the operation.
1372 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1373 * @param pVM VM Handle.
1374 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1375 * @param pvPtr The HC mapping of that address.
1376 * @param pvBuf What the guest is reading/writing.
1377 * @param cbBuf How much it's reading/writing.
1378 * @param enmAccessType The access type.
1379 * @param pvUser User argument.
1380 */
1381static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1382{
1383 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1384 Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1385 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
1386 return VINF_PGM_HANDLER_DO_DEFAULT;
1387}
1388
1389
1390/**
1391 * \#PF Handler callback for virtual access handler ranges.
1392 *
1393 * Important to realize that a physical page in a range can have aliases, and
1394 * for ALL and WRITE handlers these will also trigger.
1395 *
1396 * @returns VINF_SUCCESS if the handler have carried out the operation.
1397 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1398 * @param pVM VM Handle.
1399 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1400 * @param pvPtr The HC mapping of that address.
1401 * @param pvBuf What the guest is reading/writing.
1402 * @param cbBuf How much it's reading/writing.
1403 * @param enmAccessType The access type.
1404 * @param pvUser User argument.
1405 */
1406static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1407{
1408 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1409 Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1410
1411 /** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1412 * reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1413 * should probably also deregister the virtual handler if TR.base/size
1414 * changes while we're in REM. */
1415
1416 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
1417
1418 return VINF_PGM_HANDLER_DO_DEFAULT;
1419}
1420
1421
1422/**
1423 * Synchronize the shadowed fields in the TSS.
1424 *
1425 * At present we're shadowing the ring-0 stack selector & pointer, and the
1426 * interrupt redirection bitmap (if present). We take the lazy approach wrt to
1427 * REM and this function is called both if REM made any changes to the TSS or
1428 * loaded TR.
1429 *
1430 * @returns VBox status code.
1431 * @param pVM The VM to operate on.
1432 */
1433VMMR3DECL(int) SELMR3SyncTSS(PVM pVM)
1434{
1435 int rc;
1436
1437 if (pVM->selm.s.fDisableMonitoring)
1438 {
1439 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
1440 return VINF_SUCCESS;
1441 }
1442
1443 STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1444 Assert(VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS));
1445
1446 /*
1447 * Get TR and extract and store the basic info.
1448 *
1449 * Note! The TSS limit is not checked by the LTR code, so we
1450 * have to be a bit careful with it. We make sure cbTss
1451 * won't be zero if TR is valid and if it's NULL we'll
1452 * make sure cbTss is 0.
1453 */
1454 CPUMSELREGHID trHid;
1455 RTSEL SelTss = CPUMGetGuestTR(pVM, &trHid);
1456 RTGCPTR GCPtrTss = trHid.u64Base;
1457 uint32_t cbTss = trHid.u32Limit;
1458 Assert( (SelTss & X86_SEL_MASK)
1459 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1460 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1461 if (SelTss & X86_SEL_MASK)
1462 {
1463 Assert(!(SelTss & X86_SEL_LDT));
1464 Assert(trHid.Attr.n.u1DescType == 0);
1465 Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1466 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1467 if (!++cbTss)
1468 cbTss = UINT32_MAX;
1469 }
1470 else
1471 {
1472 Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1473 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1474 cbTss = 0; /* the reset case. */
1475 }
1476 pVM->selm.s.cbGuestTss = cbTss;
1477 pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1478 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1479
1480 /*
1481 * Figure out the size of what need to monitor.
1482 */
1483 /* We're not interested in any 16-bit TSSes. */
1484 uint32_t cbMonitoredTss = cbTss;
1485 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1486 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1487 cbMonitoredTss = 0;
1488
1489 pVM->selm.s.offGuestIoBitmap = 0;
1490 bool fNoRing1Stack = true;
1491 if (cbMonitoredTss)
1492 {
1493 /*
1494 * 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1495 * If VME is enabled we also want to keep an eye on the interrupt
1496 * redirection bitmap.
1497 */
1498 VBOXTSS Tss;
1499 uint32_t cr4 = CPUMGetGuestCR4(pVM);
1500 rc = PGMPhysSimpleReadGCPtr(pVM, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1501 if ( !(cr4 & X86_CR4_VME)
1502 || ( VBOX_SUCCESS(rc)
1503 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1504 && Tss.offIoBitmap > cbTss) /* beyond the end */ /** @todo not sure how the partial case is handled; probably not allowed. */
1505 )
1506 /* No interrupt redirection bitmap, just ESP0 and SS0. */
1507 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1508 else if (RT_SUCCESS(rc))
1509 {
1510 /*
1511 * Everything up to and including the interrupt redirection bitmap. Unfortunately
1512 * this can be quite a large chunk. We use to skip it earlier and just hope it
1513 * was kind of static...
1514 *
1515 * Update the virtual interrupt redirection bitmap while we're here.
1516 * (It is located in the 32 bytes before TR:offIoBitmap.)
1517 */
1518 cbMonitoredTss = Tss.offIoBitmap;
1519 pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1520
1521 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1522 rc = PGMPhysSimpleReadGCPtr(pVM, &pVM->selm.s.Tss.IntRedirBitmap,
1523 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1524 AssertRC(rc);
1525 /** @todo memset the bitmap on failure? */
1526 Log2(("Redirection bitmap:\n"));
1527 Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1528 }
1529 else
1530 {
1531 cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1532 pVM->selm.s.offGuestIoBitmap = 0;
1533 /** @todo memset the bitmap? */
1534 }
1535
1536 /*
1537 * Update the ring 0 stack selector and base address.
1538 */
1539 if (RT_SUCCESS(rc))
1540 {
1541#ifdef LOG_ENABLED
1542 if (LogIsEnabled())
1543 {
1544 uint32_t ssr0, espr0;
1545 SELMGetRing1Stack(pVM, &ssr0, &espr0);
1546 if ((ssr0 & ~1) != Tss.ss0 || espr0 != Tss.esp0)
1547 {
1548 RTGCPHYS GCPhys = NIL_RTGCPHYS;
1549 rc = PGMGstGetPage(pVM, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1550 Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%VGp)\n",
1551 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1552 AssertMsg(ssr0 != Tss.ss0,
1553 ("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%VGp)\n",
1554 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1555 }
1556 Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1557 }
1558#endif /* LOG_ENABLED */
1559 AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1560
1561 /* Update our TSS structure for the guest's ring 1 stack */
1562 selmSetRing1Stack(pVM, Tss.ss0 | 1, Tss.esp0);
1563 pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1564 }
1565 }
1566
1567 /*
1568 * Flush the ring-1 stack and the direct syscall dispatching if we
1569 * cannot obtain SS0:ESP0.
1570 */
1571 if (fNoRing1Stack)
1572 {
1573 selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1574 pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1575
1576 /** @todo handle these dependencies better! */
1577 TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1578 TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1579 }
1580
1581 /*
1582 * Check for monitor changes and apply them.
1583 */
1584 if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1585 || cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1586 {
1587 Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1588 GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1589
1590 /* Release the old range first. */
1591 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1592 {
1593 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1594 AssertRC(rc);
1595 }
1596
1597 /* Register the write handler if TS != 0. */
1598 if (cbMonitoredTss != 0)
1599 {
1600 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1601 0, selmR3GuestTSSWriteHandler,
1602 "selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1603 if (RT_FAILURE(rc))
1604 {
1605 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1606 return rc;
1607 }
1608
1609 /* Update saved Guest TSS info. */
1610 pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1611 pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1612 pVM->selm.s.GCSelTss = SelTss;
1613 }
1614 else
1615 {
1616 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1617 pVM->selm.s.cbMonitoredGuestTss = 0;
1618 pVM->selm.s.GCSelTss = 0;
1619 }
1620 }
1621
1622 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
1623
1624 STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1625 return VINF_SUCCESS;
1626}
1627
1628
1629/**
1630 * Compares the Guest GDT and LDT with the shadow tables.
1631 * This is a VBOX_STRICT only function.
1632 *
1633 * @returns VBox status code.
1634 * @param pVM The VM Handle.
1635 */
1636VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1637{
1638#ifdef VBOX_STRICT
1639 /*
1640 * Get GDTR and check for conflict.
1641 */
1642 VBOXGDTR GDTR;
1643 CPUMGetGuestGDTR(pVM, &GDTR);
1644 if (GDTR.cbGdt == 0)
1645 return VINF_SUCCESS;
1646
1647 if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1648 Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1649
1650 if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1651 Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1652
1653 /*
1654 * Loop thru the GDT checking each entry.
1655 */
1656 RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1657 PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1658 PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1659 while (pGDTE < pGDTEEnd)
1660 {
1661 X86DESC GDTEGuest;
1662 int rc = PGMPhysSimpleReadGCPtr(pVM, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1663 if (RT_SUCCESS(rc))
1664 {
1665 if (pGDTE->Gen.u1DescType || pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1666 {
1667 if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1668 || pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1669 || pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1670 || pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1671 || pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1672 || pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1673 || pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1674 {
1675 unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1676 SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1677 SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1678 }
1679 }
1680 }
1681
1682 /* Advance to the next descriptor. */
1683 GCPtrGDTEGuest += sizeof(X86DESC);
1684 pGDTE++;
1685 }
1686
1687
1688 /*
1689 * LDT?
1690 */
1691 RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
1692 if ((SelLdt & X86_SEL_MASK) == 0)
1693 return VINF_SUCCESS;
1694 if (SelLdt > GDTR.cbGdt)
1695 {
1696 Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1697 return VERR_INTERNAL_ERROR;
1698 }
1699 X86DESC LDTDesc;
1700 int rc = PGMPhysSimpleReadGCPtr(pVM, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1701 if (RT_FAILURE(rc))
1702 {
1703 Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1704 return rc;
1705 }
1706 RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(LDTDesc);
1707 unsigned cbLdt = X86DESC_LIMIT(LDTDesc);
1708 if (LDTDesc.Gen.u1Granularity)
1709 cbLdt = (cbLdt << PAGE_SHIFT) | PAGE_OFFSET_MASK;
1710
1711 /*
1712 * Validate it.
1713 */
1714 if (!cbLdt)
1715 return VINF_SUCCESS;
1716 /** @todo check what intel does about odd limits. */
1717 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1718 if ( LDTDesc.Gen.u1DescType
1719 || LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1720 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1721 {
1722 Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1723 return VERR_INTERNAL_ERROR;
1724 }
1725
1726 /*
1727 * Loop thru the LDT checking each entry.
1728 */
1729 unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1730 PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1731 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1732 while (pLDTE < pLDTEEnd)
1733 {
1734 X86DESC LDTEGuest;
1735 int rc = PGMPhysSimpleReadGCPtr(pVM, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1736 if (RT_SUCCESS(rc))
1737 {
1738 if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1739 || pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1740 || pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1741 || pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1742 || pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1743 || pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1744 || pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1745 {
1746 unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1747 SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1748 SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1749 }
1750 }
1751
1752 /* Advance to the next descriptor. */
1753 GCPtrLDTEGuest += sizeof(X86DESC);
1754 pLDTE++;
1755 }
1756
1757#else /* !VBOX_STRICT */
1758 NOREF(pVM);
1759#endif /* !VBOX_STRICT */
1760
1761 return VINF_SUCCESS;
1762}
1763
1764
1765/**
1766 * Validates the RawR0 TSS values against the one in the Guest TSS.
1767 *
1768 * @returns true if it matches.
1769 * @returns false and assertions on mismatch..
1770 * @param pVM VM Handle.
1771 */
1772VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1773{
1774#ifdef VBOX_STRICT
1775 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
1776 return true;
1777
1778 /*
1779 * Get TR and extract the basic info.
1780 */
1781 CPUMSELREGHID trHid;
1782 RTSEL SelTss = CPUMGetGuestTR(pVM, &trHid);
1783 RTGCPTR GCPtrTss = trHid.u64Base;
1784 uint32_t cbTss = trHid.u32Limit;
1785 Assert( (SelTss & X86_SEL_MASK)
1786 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1787 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1788 if (SelTss & X86_SEL_MASK)
1789 {
1790 AssertReturn(!(SelTss & X86_SEL_LDT), false);
1791 AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1792 AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1793 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1794 false);
1795 if (!++cbTss)
1796 cbTss = UINT32_MAX;
1797 }
1798 else
1799 {
1800 AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1801 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */),
1802 false);
1803 cbTss = 0; /* the reset case. */
1804 }
1805 AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1806 AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1807 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1808 ("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1809 false);
1810 AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1811 || (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1812 ("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1813 false);
1814 AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1815 || (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1816 ("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1817 false);
1818
1819
1820 /*
1821 * Figure out the size of what need to monitor.
1822 */
1823 bool fNoRing1Stack = true;
1824 /* We're not interested in any 16-bit TSSes. */
1825 uint32_t cbMonitoredTss = cbTss;
1826 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1827 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1828 cbMonitoredTss = 0;
1829 if (cbMonitoredTss)
1830 {
1831 VBOXTSS Tss;
1832 uint32_t cr4 = CPUMGetGuestCR4(pVM);
1833 int rc = PGMPhysSimpleReadGCPtr(pVM, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1834 AssertReturn( rc == VINF_SUCCESS
1835 /* Happends early in XP boot during page table switching. */
1836 || ( (rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT)
1837 && !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF)),
1838 false);
1839 if ( !(cr4 & X86_CR4_VME)
1840 || ( VBOX_SUCCESS(rc)
1841 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1842 && Tss.offIoBitmap > cbTss)
1843 )
1844 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1845 else if (RT_SUCCESS(rc))
1846 {
1847 cbMonitoredTss = Tss.offIoBitmap;
1848 AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1849 ("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1850 false);
1851
1852 /* check the bitmap */
1853 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1854 rc = PGMPhysSimpleReadGCPtr(pVM, &Tss.IntRedirBitmap,
1855 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1856 AssertRCReturn(rc, false);
1857 AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
1858 ("offIoBitmap=%#x cbTss=%#x\n"
1859 " Guest: %.32Rhxs\n"
1860 "Shadow: %.32Rhxs\n",
1861 Tss.offIoBitmap, cbTss,
1862 &Tss.IntRedirBitmap[0],
1863 &pVM->selm.s.Tss.IntRedirBitmap[0]),
1864 false);
1865 }
1866 else
1867 cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1868
1869 /*
1870 * Check SS0 and ESP0.
1871 */
1872 if ( !pVM->selm.s.fSyncTSSRing0Stack
1873 && RT_SUCCESS(rc))
1874 {
1875 if ( Tss.esp0 != pVM->selm.s.Tss.esp1
1876 || Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
1877 {
1878 RTGCPHYS GCPhys;
1879 rc = PGMGstGetPage(pVM, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1880 AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
1881 (pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
1882 Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
1883 return false;
1884 }
1885 }
1886 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1887 }
1888 else
1889 {
1890 AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
1891 AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
1892 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1893 }
1894
1895
1896
1897 return true;
1898
1899#else /* !VBOX_STRICT */
1900 NOREF(pVM);
1901 return true;
1902#endif /* !VBOX_STRICT */
1903}
1904
1905
1906/**
1907 * Returns flat address and limit of LDT by LDT selector from guest GDTR.
1908 *
1909 * Fully validate selector.
1910 *
1911 * @returns VBox status.
1912 * @param pVM VM Handle.
1913 * @param SelLdt LDT selector.
1914 * @param ppvLdt Where to store the flat address of LDT.
1915 * @param pcbLimit Where to store LDT limit.
1916 */
1917VMMDECL(int) SELMGetLDTFromSel(PVM pVM, RTSEL SelLdt, PRTGCPTR ppvLdt, unsigned *pcbLimit)
1918{
1919 /* Get guest GDTR. */
1920 VBOXGDTR GDTR;
1921 CPUMGetGuestGDTR(pVM, &GDTR);
1922
1923 /* Check selector TI and GDT limit. */
1924 if ( SelLdt & X86_SEL_LDT
1925 || (SelLdt > GDTR.cbGdt))
1926 return VERR_INVALID_SELECTOR;
1927
1928 /* Read descriptor from GC. */
1929 X86DESC Desc;
1930 int rc = PGMPhysSimpleReadGCPtr(pVM, (void *)&Desc, (RTGCPTR)(GDTR.pGdt + (SelLdt & X86_SEL_MASK)), sizeof(Desc));
1931 if (RT_FAILURE(rc))
1932 {
1933 /* fatal */
1934 AssertMsgFailed(("Can't read LDT descriptor for selector=%04X\n", SelLdt));
1935 return VERR_SELECTOR_NOT_PRESENT;
1936 }
1937
1938 /* Check if LDT descriptor is not present. */
1939 if (Desc.Gen.u1Present == 0)
1940 return VERR_SELECTOR_NOT_PRESENT;
1941
1942 /* Check LDT descriptor type. */
1943 if ( Desc.Gen.u1DescType == 1
1944 || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1945 return VERR_INVALID_SELECTOR;
1946
1947 /* LDT descriptor is ok. */
1948 if (ppvLdt)
1949 {
1950 *ppvLdt = (RTGCPTR)X86DESC_BASE(Desc);
1951 *pcbLimit = X86DESC_LIMIT(Desc);
1952 }
1953 return VINF_SUCCESS;
1954}
1955
1956
1957/**
1958 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
1959 *
1960 * See SELMR3GetSelectorInfo for details.
1961 *
1962 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
1963 *
1964 * @param pVM VM handle.
1965 * @param Sel The selector to get info about.
1966 * @param pSelInfo Where to store the information.
1967 */
1968static int selmR3GetSelectorInfo64(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
1969{
1970 pSelInfo->fHyper = false;
1971
1972 /*
1973 * Read it from the guest descriptor table.
1974 */
1975 X86DESC64 Desc;
1976 VBOXGDTR Gdtr;
1977 RTGCPTR GCPtrDesc;
1978 CPUMGetGuestGDTR(pVM, &Gdtr);
1979 if (!(Sel & X86_SEL_LDT))
1980 {
1981 /* GDT */
1982 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
1983 return VERR_INVALID_SELECTOR;
1984 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
1985 }
1986 else
1987 {
1988 /*
1989 * LDT - must locate the LDT first...
1990 */
1991 RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
1992 if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */
1993 || (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
1994 return VERR_INVALID_SELECTOR;
1995 GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
1996 int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
1997 if (RT_FAILURE(rc))
1998 return rc;
1999
2000 /* validate the LDT descriptor. */
2001 if (Desc.Gen.u1Present == 0)
2002 return VERR_SELECTOR_NOT_PRESENT;
2003 if ( Desc.Gen.u1DescType == 1
2004 || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2005 return VERR_INVALID_SELECTOR;
2006
2007 unsigned cbLimit = X86DESC_LIMIT(Desc);
2008 if (Desc.Gen.u1Granularity)
2009 cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2010 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2011 return VERR_INVALID_SELECTOR;
2012
2013 /* calc the descriptor location. */
2014 GCPtrDesc = X86DESC64_BASE(Desc);
2015 GCPtrDesc += (Sel & X86_SEL_MASK);
2016 }
2017
2018 /* read the descriptor. */
2019 int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
2020 if (RT_FAILURE(rc))
2021 return rc;
2022
2023 /*
2024 * Extract the base and limit
2025 */
2026 pSelInfo->Sel = Sel;
2027 pSelInfo->Raw64 = Desc;
2028 pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2029 if (Desc.Gen.u1Granularity)
2030 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2031 pSelInfo->GCPtrBase = X86DESC64_BASE(Desc);
2032 pSelInfo->fRealMode = false;
2033
2034 return VINF_SUCCESS;
2035}
2036
2037
2038/**
2039 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2040 *
2041 * See SELMR3GetSelectorInfo for details.
2042 *
2043 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
2044 *
2045 * @param pVM VM handle.
2046 * @param Sel The selector to get info about.
2047 * @param pSelInfo Where to store the information.
2048 */
2049static int selmR3GetSelectorInfo32(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
2050{
2051 /*
2052 * Read the descriptor entry
2053 */
2054 X86DESC Desc;
2055 if ( !(Sel & X86_SEL_LDT)
2056 && ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2057 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2058 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2059 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2060 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK))
2061 )
2062 {
2063 /*
2064 * Hypervisor descriptor.
2065 */
2066 pSelInfo->fHyper = true;
2067 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2068 }
2069 else if (CPUMIsGuestInProtectedMode(pVM))
2070 {
2071 /*
2072 * Read it from the guest descriptor table.
2073 */
2074 pSelInfo->fHyper = false;
2075
2076 VBOXGDTR Gdtr;
2077 RTGCPTR GCPtrDesc;
2078 CPUMGetGuestGDTR(pVM, &Gdtr);
2079 if (!(Sel & X86_SEL_LDT))
2080 {
2081 /* GDT */
2082 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2083 return VERR_INVALID_SELECTOR;
2084 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2085 }
2086 else
2087 {
2088 /*
2089 * LDT - must locate the LDT first...
2090 */
2091 RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
2092 if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */
2093 || (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2094 return VERR_INVALID_SELECTOR;
2095 GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2096 int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
2097 if (RT_FAILURE(rc))
2098 return rc;
2099
2100 /* validate the LDT descriptor. */
2101 if (Desc.Gen.u1Present == 0)
2102 return VERR_SELECTOR_NOT_PRESENT;
2103 if ( Desc.Gen.u1DescType == 1
2104 || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2105 return VERR_INVALID_SELECTOR;
2106
2107 unsigned cbLimit = X86DESC_LIMIT(Desc);
2108 if (Desc.Gen.u1Granularity)
2109 cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2110 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2111 return VERR_INVALID_SELECTOR;
2112
2113 /* calc the descriptor location. */
2114 GCPtrDesc = X86DESC_BASE(Desc);
2115 GCPtrDesc += (Sel & X86_SEL_MASK);
2116 }
2117
2118 /* read the descriptor. */
2119 int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
2120 if (RT_FAILURE(rc))
2121 return rc;
2122 }
2123 else
2124 {
2125 /*
2126 * We're in real mode.
2127 */
2128 pSelInfo->Sel = Sel;
2129 pSelInfo->GCPtrBase = Sel << 4;
2130 pSelInfo->cbLimit = 0xffff;
2131 pSelInfo->fHyper = false;
2132 pSelInfo->fRealMode = true;
2133 memset(&pSelInfo->Raw, 0, sizeof(pSelInfo->Raw));
2134 return VINF_SUCCESS;
2135 }
2136
2137 /*
2138 * Extract the base and limit
2139 */
2140 pSelInfo->Sel = Sel;
2141 pSelInfo->Raw = Desc;
2142 pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2143 if (Desc.Gen.u1Granularity)
2144 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2145 pSelInfo->GCPtrBase = X86DESC_BASE(Desc);
2146 pSelInfo->fRealMode = false;
2147
2148 return VINF_SUCCESS;
2149}
2150
2151
2152/**
2153 * Gets information about a selector.
2154 * Intended for the debugger mostly and will prefer the guest
2155 * descriptor tables over the shadow ones.
2156 *
2157 * @returns VINF_SUCCESS on success.
2158 * @returns VERR_INVALID_SELECTOR if the selector isn't fully inside the descriptor table.
2159 * @returns VERR_SELECTOR_NOT_PRESENT if the selector wasn't present.
2160 * @returns VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the pagetable or page
2161 * backing the selector table wasn't present.
2162 * @returns Other VBox status code on other errors.
2163 *
2164 * @param pVM VM handle.
2165 * @param Sel The selector to get info about.
2166 * @param pSelInfo Where to store the information.
2167 */
2168VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
2169{
2170 AssertPtr(pSelInfo);
2171 if (CPUMIsGuestInLongMode(pVM))
2172 return selmR3GetSelectorInfo64(pVM, Sel, pSelInfo);
2173 return selmR3GetSelectorInfo32(pVM, Sel, pSelInfo);
2174}
2175
2176
2177/**
2178 * Gets information about a selector from the shadow tables.
2179 *
2180 * This is intended to be faster than the SELMR3GetSelectorInfo() method, but requires
2181 * that the caller ensures that the shadow tables are up to date.
2182 *
2183 * @returns VINF_SUCCESS on success.
2184 * @returns VERR_INVALID_SELECTOR if the selector isn't fully inside the descriptor table.
2185 * @returns VERR_SELECTOR_NOT_PRESENT if the selector wasn't present.
2186 * @returns VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the pagetable or page
2187 * backing the selector table wasn't present.
2188 * @returns Other VBox status code on other errors.
2189 *
2190 * @param pVM VM handle.
2191 * @param Sel The selector to get info about.
2192 * @param pSelInfo Where to store the information.
2193 */
2194VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
2195{
2196 Assert(pSelInfo);
2197
2198 /*
2199 * Read the descriptor entry
2200 */
2201 X86DESC Desc;
2202 if (!(Sel & X86_SEL_LDT))
2203 {
2204 /*
2205 * Global descriptor.
2206 */
2207 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2208 pSelInfo->fHyper = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2209 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2210 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2211 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2212 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK);
2213 /** @todo check that the GDT offset is valid. */
2214 }
2215 else
2216 {
2217 /*
2218 * Local Descriptor.
2219 */
2220 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2221 Desc = paLDT[Sel >> X86_SEL_SHIFT];
2222 /** @todo check if the LDT page is actually available. */
2223 /** @todo check that the LDT offset is valid. */
2224 pSelInfo->fHyper = false;
2225 }
2226
2227 /*
2228 * Extract the base and limit
2229 */
2230 pSelInfo->Sel = Sel;
2231 pSelInfo->Raw = Desc;
2232 pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2233 if (Desc.Gen.u1Granularity)
2234 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2235 pSelInfo->GCPtrBase = X86DESC_BASE(Desc);
2236 pSelInfo->fRealMode = false;
2237
2238 return VINF_SUCCESS;
2239}
2240
2241
2242/**
2243 * Formats a descriptor.
2244 *
2245 * @param Desc Descriptor to format.
2246 * @param Sel Selector number.
2247 * @param pszOutput Output buffer.
2248 * @param cchOutput Size of output buffer.
2249 */
2250static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2251{
2252 /*
2253 * Make variable description string.
2254 */
2255 static struct
2256 {
2257 unsigned cch;
2258 const char *psz;
2259 } const aTypes[32] =
2260 {
2261#define STRENTRY(str) { sizeof(str) - 1, str }
2262 /* system */
2263 STRENTRY("Reserved0 "), /* 0x00 */
2264 STRENTRY("TSS16Avail "), /* 0x01 */
2265 STRENTRY("LDT "), /* 0x02 */
2266 STRENTRY("TSS16Busy "), /* 0x03 */
2267 STRENTRY("Call16 "), /* 0x04 */
2268 STRENTRY("Task "), /* 0x05 */
2269 STRENTRY("Int16 "), /* 0x06 */
2270 STRENTRY("Trap16 "), /* 0x07 */
2271 STRENTRY("Reserved8 "), /* 0x08 */
2272 STRENTRY("TSS32Avail "), /* 0x09 */
2273 STRENTRY("ReservedA "), /* 0x0a */
2274 STRENTRY("TSS32Busy "), /* 0x0b */
2275 STRENTRY("Call32 "), /* 0x0c */
2276 STRENTRY("ReservedD "), /* 0x0d */
2277 STRENTRY("Int32 "), /* 0x0e */
2278 STRENTRY("Trap32 "), /* 0x0f */
2279 /* non system */
2280 STRENTRY("DataRO "), /* 0x10 */
2281 STRENTRY("DataRO Accessed "), /* 0x11 */
2282 STRENTRY("DataRW "), /* 0x12 */
2283 STRENTRY("DataRW Accessed "), /* 0x13 */
2284 STRENTRY("DataDownRO "), /* 0x14 */
2285 STRENTRY("DataDownRO Accessed "), /* 0x15 */
2286 STRENTRY("DataDownRW "), /* 0x16 */
2287 STRENTRY("DataDownRW Accessed "), /* 0x17 */
2288 STRENTRY("CodeEO "), /* 0x18 */
2289 STRENTRY("CodeEO Accessed "), /* 0x19 */
2290 STRENTRY("CodeER "), /* 0x1a */
2291 STRENTRY("CodeER Accessed "), /* 0x1b */
2292 STRENTRY("CodeConfEO "), /* 0x1c */
2293 STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2294 STRENTRY("CodeConfER "), /* 0x1e */
2295 STRENTRY("CodeConfER Accessed ") /* 0x1f */
2296#undef SYSENTRY
2297 };
2298#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2299 char szMsg[128];
2300 char *psz = &szMsg[0];
2301 unsigned i = Desc.Gen.u1DescType << 4 | Desc.Gen.u4Type;
2302 memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2303 psz += aTypes[i].cch;
2304
2305 if (Desc.Gen.u1Present)
2306 ADD_STR(psz, "Present ");
2307 else
2308 ADD_STR(psz, "Not-Present ");
2309 if (Desc.Gen.u1Granularity)
2310 ADD_STR(psz, "Page ");
2311 if (Desc.Gen.u1DefBig)
2312 ADD_STR(psz, "32-bit ");
2313 else
2314 ADD_STR(psz, "16-bit ");
2315#undef ADD_STR
2316 *psz = '\0';
2317
2318 /*
2319 * Limit and Base and format the output.
2320 */
2321 uint32_t u32Limit = X86DESC_LIMIT(Desc);
2322 if (Desc.Gen.u1Granularity)
2323 u32Limit = u32Limit << PAGE_SHIFT | PAGE_OFFSET_MASK;
2324 uint32_t u32Base = X86DESC_BASE(Desc);
2325
2326 RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2327 Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2328}
2329
2330
2331/**
2332 * Dumps a descriptor.
2333 *
2334 * @param Desc Descriptor to dump.
2335 * @param Sel Selector number.
2336 * @param pszMsg Message to prepend the log entry with.
2337 */
2338VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2339{
2340 char szOutput[128];
2341 selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2342 Log(("%s: %s\n", pszMsg, szOutput));
2343 NOREF(szOutput[0]);
2344}
2345
2346
2347/**
2348 * Display the shadow gdt.
2349 *
2350 * @param pVM VM Handle.
2351 * @param pHlp The info helpers.
2352 * @param pszArgs Arguments, ignored.
2353 */
2354static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2355{
2356 pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2357 for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2358 {
2359 if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2360 {
2361 char szOutput[128];
2362 selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2363 const char *psz = "";
2364 if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2365 psz = " HyperCS";
2366 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2367 psz = " HyperDS";
2368 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2369 psz = " HyperCS64";
2370 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2371 psz = " HyperTSS";
2372 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2373 psz = " HyperTSSTrap08";
2374 pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2375 }
2376 }
2377}
2378
2379
2380/**
2381 * Display the guest gdt.
2382 *
2383 * @param pVM VM Handle.
2384 * @param pHlp The info helpers.
2385 * @param pszArgs Arguments, ignored.
2386 */
2387static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2388{
2389 VBOXGDTR GDTR;
2390 CPUMGetGuestGDTR(pVM, &GDTR);
2391 RTGCPTR GCPtrGDT = GDTR.pGdt;
2392 unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2393
2394 pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2395 for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2396 {
2397 X86DESC GDTE;
2398 int rc = PGMPhysSimpleReadGCPtr(pVM, &GDTE, GCPtrGDT, sizeof(GDTE));
2399 if (RT_SUCCESS(rc))
2400 {
2401 if (GDTE.Gen.u1Present)
2402 {
2403 char szOutput[128];
2404 selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2405 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2406 }
2407 }
2408 else if (rc == VERR_PAGE_NOT_PRESENT)
2409 {
2410 if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2411 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2412 }
2413 else
2414 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2415 }
2416}
2417
2418
2419/**
2420 * Display the shadow ldt.
2421 *
2422 * @param pVM VM Handle.
2423 * @param pHlp The info helpers.
2424 * @param pszArgs Arguments, ignored.
2425 */
2426static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2427{
2428 unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2429 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2430 pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2431 for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2432 {
2433 if (paLDT[iLDT].Gen.u1Present)
2434 {
2435 char szOutput[128];
2436 selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2437 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2438 }
2439 }
2440}
2441
2442
2443/**
2444 * Display the guest ldt.
2445 *
2446 * @param pVM VM Handle.
2447 * @param pHlp The info helpers.
2448 * @param pszArgs Arguments, ignored.
2449 */
2450static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2451{
2452 RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
2453 if (!(SelLdt & X86_SEL_MASK))
2454 {
2455 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2456 return;
2457 }
2458
2459 RTGCPTR GCPtrLdt;
2460 unsigned cbLdt;
2461 int rc = SELMGetLDTFromSel(pVM, SelLdt, &GCPtrLdt, &cbLdt);
2462 if (RT_FAILURE(rc))
2463 {
2464 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): rc=%Rrc\n", SelLdt, rc);
2465 return;
2466 }
2467
2468 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RGv limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2469 unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2470 for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2471 {
2472 X86DESC LdtE;
2473 int rc = PGMPhysSimpleReadGCPtr(pVM, &LdtE, GCPtrLdt, sizeof(LdtE));
2474 if (RT_SUCCESS(rc))
2475 {
2476 if (LdtE.Gen.u1Present)
2477 {
2478 char szOutput[128];
2479 selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2480 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2481 }
2482 }
2483 else if (rc == VERR_PAGE_NOT_PRESENT)
2484 {
2485 if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2486 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, GCPtrLdt);
2487 }
2488 else
2489 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, rc, GCPtrLdt);
2490 }
2491}
2492
2493
2494/**
2495 * Dumps the hypervisor GDT
2496 *
2497 * @param pVM VM handle.
2498 */
2499VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2500{
2501 DBGFR3Info(pVM, "gdt", NULL, NULL);
2502}
2503
2504
2505/**
2506 * Dumps the hypervisor LDT
2507 *
2508 * @param pVM VM handle.
2509 */
2510VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2511{
2512 DBGFR3Info(pVM, "ldt", NULL, NULL);
2513}
2514
2515
2516/**
2517 * Dumps the guest GDT
2518 *
2519 * @param pVM VM handle.
2520 */
2521VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2522{
2523 DBGFR3Info(pVM, "gdtguest", NULL, NULL);
2524}
2525
2526
2527/**
2528 * Dumps the guest LDT
2529 *
2530 * @param pVM VM handle.
2531 */
2532VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2533{
2534 DBGFR3Info(pVM, "ldtguest", NULL, NULL);
2535}
2536
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette