SELM.cpp@ 17073

Last change on this file since 17073 was 17035, checked in by vboxsync, 16 years ago
VMM,REM: Brushed up the TR/TSS shadowing. We're now relying on the hidden TR registers in SELM and CPUM/REM will make sure these are always in sync. Joined CPUMGetGuestTRHid and CPUMGetGuestTR. Kicked out sync_tr (unused now) and SELMGCGetRing1Stack.
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File size: 94.1 KB

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1	/* $Id: SELM.cpp 17035 2009-02-23 22:26:39Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_selm SELM - The Selector Manager
23	*
24	* SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
25	* of a few hyper selector for the raw-mode context. In the hardware assisted
26	* virtualization mode its only task is to decode entries in the guest GDT or
27	* LDT once in a while.
28	*
29	* @see grp_selm
30	*
31	*
32	* @section seg_selm_shadowing Shadowing
33	*
34	* SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
35	* work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
36	* The idea is to do it in a more on-demand fashion when we get time. There
37	* also a whole bunch of issues with the current synchronization of all three
38	* tables, see notes and todos in the code.
39	*
40	* When the guest makes changes to the GDT we will try update the shadow copy
41	* without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
42	*
43	* When the guest make LDT changes we'll trigger a full resync of the LDT
44	* (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
45	*
46	* The TSS shadowing is limited to the fields we need to care about, namely SS0
47	* and ESP0. The Patch Manager makes use of these. We monitor updates to the
48	* guest TSS and will try keep our SS0 and ESP0 copies up to date this way
49	* rather than go the SELMR3SyncTSS() route.
50	*
51	* When in raw-mode SELM also injects a few extra GDT selectors which are used
52	* by the raw-mode (hyper) context. These start their life at the high end of
53	* the table and will be relocated when the guest tries to make use of them...
54	* Well, that was that idea at least, only the code isn't quite there yet which
55	* is why we have trouble with guests which actually have a full sized GDT.
56	*
57	* So, the summary of the current GDT, LDT and TSS shadowing is that there is a
58	* lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
59	*
60	*/
61
62	/*******************************************************************************
63	* Header Files *
64	*******************************************************************************/
65	#define LOG_GROUP LOG_GROUP_SELM
66	#include <VBox/selm.h>
67	#include <VBox/cpum.h>
68	#include <VBox/stam.h>
69	#include <VBox/mm.h>
70	#include <VBox/ssm.h>
71	#include <VBox/pgm.h>
72	#include <VBox/trpm.h>
73	#include <VBox/dbgf.h>
74	#include "SELMInternal.h"
75	#include <VBox/vm.h>
76	#include <VBox/err.h>
77	#include <VBox/param.h>
78
79	#include <iprt/assert.h>
80	#include <VBox/log.h>
81	#include <iprt/asm.h>
82	#include <iprt/string.h>
83	#include <iprt/thread.h>
84	#include <iprt/string.h>
85
86
87	/**
88	* Enable or disable tracking of Guest's GDT/LDT/TSS.
89	* @{
90	*/
91	#define SELM_TRACK_GUEST_GDT_CHANGES
92	#define SELM_TRACK_GUEST_LDT_CHANGES
93	#define SELM_TRACK_GUEST_TSS_CHANGES
94	/** @} */
95
96	/**
97	* Enable or disable tracking of Shadow GDT/LDT/TSS.
98	* @{
99	*/
100	#define SELM_TRACK_SHADOW_GDT_CHANGES
101	#define SELM_TRACK_SHADOW_LDT_CHANGES
102	#define SELM_TRACK_SHADOW_TSS_CHANGES
103	/** @} */
104
105
106	/** SELM saved state version. */
107	#define SELM_SAVED_STATE_VERSION 5
108
109
110	/*******************************************************************************
111	* Internal Functions *
112	*******************************************************************************/
113	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
114	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
115	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
116	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
117	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
118	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
119	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
120	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
121	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
122	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
123	//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
124	//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125
126
127
128	/**
129	* Initializes the SELM.
130	*
131	* @returns VBox status code.
132	* @param pVM The VM to operate on.
133	*/
134	VMMR3DECL(int) SELMR3Init(PVM pVM)
135	{
136	LogFlow(("SELMR3Init\n"));
137
138	/*
139	* Assert alignment and sizes.
140	* (The TSS block requires contiguous back.)
141	*/
142	AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
143	AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
144	#if 0 /* doesn't work */
145	AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
146	AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
147	#endif
148	AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
149	AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
150	AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
151
152	/*
153	* Init the structure.
154	*/
155	pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
156	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
157	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
158	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
159	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
160	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
161
162	/*
163	* Allocate GDT table.
164	*/
165	int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
166	PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
167	AssertRCReturn(rc, rc);
168
169	/*
170	* Allocate LDT area.
171	*/
172	rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
173	AssertRCReturn(rc, rc);
174
175	/*
176	* Init Guest's and Shadow GDT, LDT, TSS changes control variables.
177	*/
178	pVM->selm.s.cbEffGuestGdtLimit = 0;
179	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
180	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
181	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
182
183	pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
184	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
185	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
186	pVM->selm.s.GCSelTss = RTSEL_MAX;
187
188	pVM->selm.s.fDisableMonitoring = false;
189	pVM->selm.s.fSyncTSSRing0Stack = false;
190
191	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
192	* for I/O operations. */
193	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
194	/* bit set to 1 means no redirection */
195	memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
196
197	/*
198	* Register the saved state data unit.
199	*/
200	rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
201	NULL, selmR3Save, NULL,
202	NULL, selmR3Load, selmR3LoadDone);
203	if (RT_FAILURE(rc))
204	return rc;
205
206	/*
207	* Statistics.
208	*/
209	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
210	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
211	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
212	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
213	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
214	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
215	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
216	STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
217	STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
218
219	STAM_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
220	STAM_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
221
222	/*
223	* Default action when entering raw mode for the first time
224	*/
225	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
226	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
227	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
228
229	/*
230	* Register info handlers.
231	*/
232	DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
233	DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
234	DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
235	DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
236	//DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
237	//DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
238
239	return rc;
240	}
241
242
243	/**
244	* Finalizes HMA page attributes.
245	*
246	* @returns VBox status code.
247	* @param pVM The VM handle.
248	*/
249	VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
250	{
251	/** @cfgm{/DoubleFault,bool,false}
252	* Enables catching of double faults in the raw-mode context VMM code. This can
253	* be used when the tripple faults or hangs occure and one suspect an unhandled
254	* double fault. This is not enabled by default because it means making the
255	* hyper selectors writeable for all supervisor code, including the guest's.
256	* The double fault is a task switch and thus requires write access to the GDT
257	* of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
258	* 8 TSS for the back link.
259	*/
260	bool f;
261	#if defined(DEBUG_bird)
262	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
263	#else
264	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
265	#endif
266	AssertLogRelRCReturn(rc, rc);
267	if (f)
268	{
269	PX86DESC paGdt = pVM->selm.s.paGdtR3;
270	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
271	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
272	AssertRC(rc);
273	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
274	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
275	AssertRC(rc);
276	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
277	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
278	AssertRC(rc);
279	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
280	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
281	AssertRC(rc);
282	}
283	return VINF_SUCCESS;
284	}
285
286
287	/**
288	* Setup the hypervisor GDT selectors in our shadow table
289	*
290	* @param pVM The VM handle.
291	*/
292	static void selmR3SetupHyperGDTSelectors(PVM pVM)
293	{
294	PX86DESC paGdt = pVM->selm.s.paGdtR3;
295
296	/*
297	* Set up global code and data descriptors for use in the guest context.
298	* Both are wide open (base 0, limit 4GB)
299	*/
300	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
301	pDesc->Gen.u16LimitLow = 0xffff;
302	pDesc->Gen.u4LimitHigh = 0xf;
303	pDesc->Gen.u16BaseLow = 0;
304	pDesc->Gen.u8BaseHigh1 = 0;
305	pDesc->Gen.u8BaseHigh2 = 0;
306	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
307	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
308	pDesc->Gen.u2Dpl = 0; /* supervisor */
309	pDesc->Gen.u1Present = 1;
310	pDesc->Gen.u1Available = 0;
311	pDesc->Gen.u1Long = 0;
312	pDesc->Gen.u1DefBig = 1; /* def 32 bit */
313	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
314
315	/* data */
316	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
317	pDesc->Gen.u16LimitLow = 0xffff;
318	pDesc->Gen.u4LimitHigh = 0xf;
319	pDesc->Gen.u16BaseLow = 0;
320	pDesc->Gen.u8BaseHigh1 = 0;
321	pDesc->Gen.u8BaseHigh2 = 0;
322	pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
323	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
324	pDesc->Gen.u2Dpl = 0; /* supervisor */
325	pDesc->Gen.u1Present = 1;
326	pDesc->Gen.u1Available = 0;
327	pDesc->Gen.u1Long = 0;
328	pDesc->Gen.u1DefBig = 1; /* big */
329	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
330
331	/* 64-bit mode code (& data?) */
332	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
333	pDesc->Gen.u16LimitLow = 0xffff;
334	pDesc->Gen.u4LimitHigh = 0xf;
335	pDesc->Gen.u16BaseLow = 0;
336	pDesc->Gen.u8BaseHigh1 = 0;
337	pDesc->Gen.u8BaseHigh2 = 0;
338	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
339	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
340	pDesc->Gen.u2Dpl = 0; /* supervisor */
341	pDesc->Gen.u1Present = 1;
342	pDesc->Gen.u1Available = 0;
343	pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
344	pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
345	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
346
347	/*
348	* TSS descriptor
349	*/
350	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
351	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
352	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
353	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
354	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
355	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
356	pDesc->Gen.u4LimitHigh = 0;
357	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
358	pDesc->Gen.u1DescType = 0; /* system */
359	pDesc->Gen.u2Dpl = 0; /* supervisor */
360	pDesc->Gen.u1Present = 1;
361	pDesc->Gen.u1Available = 0;
362	pDesc->Gen.u1Long = 0;
363	pDesc->Gen.u1DefBig = 0;
364	pDesc->Gen.u1Granularity = 0; /* byte limit */
365
366	/*
367	* TSS descriptor for trap 08
368	*/
369	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
370	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
371	pDesc->Gen.u4LimitHigh = 0;
372	RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
373	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
374	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
375	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
376	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
377	pDesc->Gen.u1DescType = 0; /* system */
378	pDesc->Gen.u2Dpl = 0; /* supervisor */
379	pDesc->Gen.u1Present = 1;
380	pDesc->Gen.u1Available = 0;
381	pDesc->Gen.u1Long = 0;
382	pDesc->Gen.u1DefBig = 0;
383	pDesc->Gen.u1Granularity = 0; /* byte limit */
384	}
385
386	/**
387	* Applies relocations to data and code managed by this
388	* component. This function will be called at init and
389	* whenever the VMM need to relocate it self inside the GC.
390	*
391	* @param pVM The VM.
392	*/
393	VMMR3DECL(void) SELMR3Relocate(PVM pVM)
394	{
395	PX86DESC paGdt = pVM->selm.s.paGdtR3;
396	LogFlow(("SELMR3Relocate\n"));
397
398	/*
399	* Update GDTR and selector.
400	*/
401	CPUMSetHyperGDTR(pVM, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
402
403	/** @todo selector relocations should be a seperate operation? */
404	CPUMSetHyperCS(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
405	CPUMSetHyperDS(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
406	CPUMSetHyperES(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
407	CPUMSetHyperSS(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
408	CPUMSetHyperTR(pVM, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
409
410	selmR3SetupHyperGDTSelectors(pVM);
411
412	/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
413	/** @todo PGM knows the proper CR3 values these days, not CPUM. */
414	/*
415	* Update the TSSes.
416	*/
417	/* Current TSS */
418	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVM);
419	pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
420	pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVM);
421	pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
422	pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
423	pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
424	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
425
426	/* trap 08 */
427	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM); /* this should give use better survival chances. */
428	pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
429	pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
430	pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVM) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
431	pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
432	pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
433	pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
434	pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
435	pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
436	pVM->selm.s.TssTrap08.fs = 0;
437	pVM->selm.s.TssTrap08.gs = 0;
438	pVM->selm.s.TssTrap08.selLdt = 0;
439	pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
440	pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
441	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
442	pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
443	pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
444	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
445	pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
446	pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
447	/* TRPM will be updating the eip */
448
449	if (!pVM->selm.s.fDisableMonitoring)
450	{
451	/*
452	* Update shadow GDT/LDT/TSS write access handlers.
453	*/
454	int rc;
455	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
456	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
457	{
458	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
459	AssertRC(rc);
460	}
461	pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
462	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
463	pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
464	0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
465	AssertRC(rc);
466	#endif
467	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
468	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
469	{
470	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
471	AssertRC(rc);
472	}
473	pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
474	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
475	pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
476	0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
477	AssertRC(rc);
478	#endif
479
480	/*
481	* Update the GC LDT region handler and address.
482	*/
483	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
484	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
485	{
486	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
487	AssertRC(rc);
488	}
489	#endif
490	pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
491	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
492	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
493	pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
494	0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
495	AssertRC(rc);
496	#endif
497	}
498	}
499
500
501	/**
502	* Notification callback which is called whenever there is a chance that a CR3
503	* value might have changed.
504	* This is called by PGM.
505	*
506	* @param pVM The VM handle
507	*/
508	VMMR3DECL(void) SELMR3PagingModeChanged(PVM pVM)
509	{
510	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVM);
511	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM);
512	}
513
514
515	/**
516	* Terminates the SELM.
517	*
518	* Termination means cleaning up and freeing all resources,
519	* the VM it self is at this point powered off or suspended.
520	*
521	* @returns VBox status code.
522	* @param pVM The VM to operate on.
523	*/
524	VMMR3DECL(int) SELMR3Term(PVM pVM)
525	{
526	return 0;
527	}
528
529
530	/**
531	* The VM is being reset.
532	*
533	* For the SELM component this means that any GDT/LDT/TSS monitors
534	* needs to be removed.
535	*
536	* @param pVM VM handle.
537	*/
538	VMMR3DECL(void) SELMR3Reset(PVM pVM)
539	{
540	LogFlow(("SELMR3Reset:\n"));
541	VM_ASSERT_EMT(pVM);
542
543	/*
544	* Uninstall guest GDT/LDT/TSS write access handlers.
545	*/
546	int rc;
547	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
548	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
549	{
550	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
551	AssertRC(rc);
552	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
553	pVM->selm.s.GuestGdtr.cbGdt = 0;
554	}
555	pVM->selm.s.fGDTRangeRegistered = false;
556	#endif
557	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
558	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
559	{
560	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
561	AssertRC(rc);
562	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
563	}
564	#endif
565	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
566	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
567	{
568	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
569	AssertRC(rc);
570	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
571	pVM->selm.s.GCSelTss = RTSEL_MAX;
572	}
573	#endif
574
575	/*
576	* Re-initialize other members.
577	*/
578	pVM->selm.s.cbLdtLimit = 0;
579	pVM->selm.s.offLdtHyper = 0;
580	pVM->selm.s.cbMonitoredGuestTss = 0;
581
582	pVM->selm.s.fSyncTSSRing0Stack = false;
583
584	/*
585	* Default action when entering raw mode for the first time
586	*/
587	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
588	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
589	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
590	}
591
592	/**
593	* Disable GDT/LDT/TSS monitoring and syncing
594	*
595	* @param pVM The VM to operate on.
596	*/
597	VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
598	{
599	/*
600	* Uninstall guest GDT/LDT/TSS write access handlers.
601	*/
602	int rc;
603	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
604	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
605	{
606	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
607	AssertRC(rc);
608	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
609	pVM->selm.s.GuestGdtr.cbGdt = 0;
610	}
611	pVM->selm.s.fGDTRangeRegistered = false;
612	#endif
613	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
614	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
615	{
616	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
617	AssertRC(rc);
618	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
619	}
620	#endif
621	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
622	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
623	{
624	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
625	AssertRC(rc);
626	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
627	pVM->selm.s.GCSelTss = RTSEL_MAX;
628	}
629	#endif
630
631	/*
632	* Unregister shadow GDT/LDT/TSS write access handlers.
633	*/
634	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
635	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
636	{
637	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
638	AssertRC(rc);
639	pVM->selm.s.paGdtRC = NIL_RTRCPTR;
640	}
641	#endif
642	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
643	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
644	{
645	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
646	AssertRC(rc);
647	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
648	}
649	#endif
650	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
651	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
652	{
653	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
654	AssertRC(rc);
655	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
656	}
657	#endif
658
659	VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
660	VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
661	VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
662
663	pVM->selm.s.fDisableMonitoring = true;
664	}
665
666
667	/**
668	* Execute state save operation.
669	*
670	* @returns VBox status code.
671	* @param pVM VM Handle.
672	* @param pSSM SSM operation handle.
673	*/
674	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
675	{
676	LogFlow(("selmR3Save:\n"));
677
678	/*
679	* Save the basic bits - fortunately all the other things can be resynced on load.
680	*/
681	PSELM pSelm = &pVM->selm.s;
682
683	SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
684	SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
685	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
686	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
687	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
688	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
689	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
690	return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
691	}
692
693
694	/**
695	* Execute state load operation.
696	*
697	* @returns VBox status code.
698	* @param pVM VM Handle.
699	* @param pSSM SSM operation handle.
700	* @param u32Version Data layout version.
701	*/
702	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
703	{
704	LogFlow(("selmR3Load:\n"));
705
706	/*
707	* Validate version.
708	*/
709	if (u32Version != SELM_SAVED_STATE_VERSION)
710	{
711	AssertMsgFailed(("selmR3Load: Invalid version u32Version=%d!\n", u32Version));
712	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
713	}
714
715	/*
716	* Do a reset.
717	*/
718	SELMR3Reset(pVM);
719
720	/* Get the monitoring flag. */
721	SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
722
723	/* Get the TSS state flag. */
724	SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
725
726	/*
727	* Get the selectors.
728	*/
729	RTSEL SelCS;
730	SSMR3GetSel(pSSM, &SelCS);
731	RTSEL SelDS;
732	SSMR3GetSel(pSSM, &SelDS);
733	RTSEL SelCS64;
734	SSMR3GetSel(pSSM, &SelCS64);
735	RTSEL SelDS64;
736	SSMR3GetSel(pSSM, &SelDS64);
737	RTSEL SelTSS;
738	SSMR3GetSel(pSSM, &SelTSS);
739	RTSEL SelTSSTrap08;
740	SSMR3GetSel(pSSM, &SelTSSTrap08);
741
742	/* Copy the selectors; they will be checked during relocation. */
743	PSELM pSelm = &pVM->selm.s;
744	pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
745	pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
746	pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
747	pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
748	pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
749
750	return VINF_SUCCESS;
751	}
752
753
754	/**
755	* Sync the GDT, LDT and TSS after loading the state.
756	*
757	* Just to play save, we set the FFs to force syncing before
758	* executing GC code.
759	*
760	* @returns VBox status code.
761	* @param pVM VM Handle.
762	* @param pSSM SSM operation handle.
763	*/
764	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
765	{
766	LogFlow(("selmR3LoadDone:\n"));
767
768	/*
769	* Don't do anything if it's a load failure.
770	*/
771	int rc = SSMR3HandleGetStatus(pSSM);
772	if (RT_FAILURE(rc))
773	return VINF_SUCCESS;
774
775	/*
776	* Do the syncing if we're in protected mode.
777	*/
778	if (PGMGetGuestMode(pVM) != PGMMODE_REAL)
779	{
780	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
781	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
782	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
783	SELMR3UpdateFromCPUM(pVM);
784	}
785
786	/*
787	* Flag everything for resync on next raw mode entry.
788	*/
789	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
790	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
791	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
792
793	return VINF_SUCCESS;
794	}
795
796
797	/**
798	* Updates the Guest GDT & LDT virtualization based on current CPU state.
799	*
800	* @returns VBox status code.
801	* @param pVM The VM to operate on.
802	*/
803	VMMR3DECL(int) SELMR3UpdateFromCPUM(PVM pVM)
804	{
805	int rc = VINF_SUCCESS;
806
807	if (pVM->selm.s.fDisableMonitoring)
808	{
809	VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
810	VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
811	VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
812
813	return VINF_SUCCESS;
814	}
815
816	STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
817
818	/*
819	* GDT sync
820	*/
821	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_GDT))
822	{
823	/*
824	* Always assume the best
825	*/
826	VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
827
828	/* If the GDT was changed, then make sure the LDT is checked too */
829	/** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
830	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
831	/* Same goes for the TSS selector */
832	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
833
834	/*
835	* Get the GDTR and check if there is anything to do (there usually is).
836	*/
837	VBOXGDTR GDTR;
838	CPUMGetGuestGDTR(pVM, &GDTR);
839	if (GDTR.cbGdt < sizeof(X86DESC))
840	{
841	Log(("No GDT entries...\n"));
842	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
843	return VINF_SUCCESS;
844	}
845
846	/*
847	* Read the Guest GDT.
848	* ASSUMES that the entire GDT is in memory.
849	*/
850	RTUINT cbEffLimit = GDTR.cbGdt;
851	PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
852	rc = PGMPhysSimpleReadGCPtr(pVM, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
853	if (RT_FAILURE(rc))
854	{
855	/*
856	* Read it page by page.
857	*
858	* Keep track of the last valid page and delay memsets and
859	* adjust cbEffLimit to reflect the effective size. The latter
860	* is something we do in the belief that the guest will probably
861	* never actually commit the last page, thus allowing us to keep
862	* our selectors in the high end of the GDT.
863	*/
864	RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
865	RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
866	uint8_t pu8Dst = (uint8_t )&pVM->selm.s.paGdtR3[1];
867	uint8_t *pu8DstInvalid = pu8Dst;
868
869	while (cbLeft)
870	{
871	RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
872	cb = RT_MIN(cb, cbLeft);
873	rc = PGMPhysSimpleReadGCPtr(pVM, pu8Dst, GCPtrSrc, cb);
874	if (RT_SUCCESS(rc))
875	{
876	if (pu8DstInvalid != pu8Dst)
877	memset(pu8DstInvalid, 0, pu8Dst - pu8DstInvalid);
878	GCPtrSrc += cb;
879	pu8Dst += cb;
880	pu8DstInvalid = pu8Dst;
881	}
882	else if ( rc == VERR_PAGE_NOT_PRESENT
883	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
884	{
885	GCPtrSrc += cb;
886	pu8Dst += cb;
887	}
888	else
889	{
890	AssertReleaseMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
891	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
892	return VERR_NOT_IMPLEMENTED;
893	}
894	cbLeft -= cb;
895	}
896
897	/* any invalid pages at the end? */
898	if (pu8DstInvalid != pu8Dst)
899	{
900	cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
901	/* If any GDTEs was invalidated, zero them. */
902	if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
903	memset(pu8DstInvalid + cbEffLimit + 1, 0, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
904	}
905
906	/* keep track of the effective limit. */
907	if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
908	{
909	Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
910	pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
911	pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
912	}
913	}
914
915	/*
916	* Check if the Guest GDT intrudes on our GDT entries.
917	*/
918	/** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
919	RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
920	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
921	{
922	PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
923	PX86DESC pGDTE = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
924	int iGDT = 0;
925
926	Log(("Internal SELM GDT conflict: use non-present entries\n"));
927	STAM_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
928	while (pGDTE > pGDTEStart)
929	{
930	/* We can reuse non-present entries */
931	if (!pGDTE->Gen.u1Present)
932	{
933	aHyperSel[iGDT] = ((uintptr_t)pGDTE - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
934	aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
935	Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
936	iGDT++;
937	if (iGDT >= SELM_HYPER_SEL_MAX)
938	break;
939	}
940
941	pGDTE--;
942	}
943	if (iGDT != SELM_HYPER_SEL_MAX)
944	{
945	AssertReleaseMsgFailed(("Internal SELM GDT conflict.\n"));
946	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
947	return VERR_NOT_IMPLEMENTED;
948	}
949	}
950	else
951	{
952	aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
953	aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
954	aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
955	aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
956	aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
957	}
958
959	/*
960	* Work thru the copied GDT entries adjusting them for correct virtualization.
961	*/
962	PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
963	while (pGDTE < pGDTEEnd)
964	{
965	if (pGDTE->Gen.u1Present)
966	{
967	/*
968	* Code and data selectors are generally 1:1, with the
969	* 'little' adjustment we do for DPL 0 selectors.
970	*/
971	if (pGDTE->Gen.u1DescType)
972	{
973	/*
974	* Hack for A-bit against Trap E on read-only GDT.
975	*/
976	/** @todo Fix this by loading ds and cs before turning off WP. */
977	pGDTE->Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
978
979	/*
980	* All DPL 0 code and data segments are squeezed into DPL 1.
981	*
982	* We're skipping conforming segments here because those
983	* cannot give us any trouble.
984	*/
985	if ( pGDTE->Gen.u2Dpl == 0
986	&& (pGDTE->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
987	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF) )
988	pGDTE->Gen.u2Dpl = 1;
989	}
990	else
991	{
992	/*
993	* System type selectors are marked not present.
994	* Recompiler or special handling is required for these.
995	*/
996	/** @todo what about interrupt gates and rawr0? */
997	pGDTE->Gen.u1Present = 0;
998	}
999	}
1000
1001	/* Next GDT entry. */
1002	pGDTE++;
1003	}
1004
1005	/*
1006	* Check if our hypervisor selectors were changed.
1007	*/
1008	if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
1009	\|\| aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
1010	\|\| aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
1011	\|\| aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
1012	\|\| aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
1013	{
1014	/* Reinitialize our hypervisor GDTs */
1015	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
1016	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
1017	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
1018	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
1019	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1020
1021	STAM_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
1022
1023	/*
1024	* Do the relocation callbacks to let everyone update their hyper selector dependencies.
1025	* (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
1026	*/
1027	VMR3Relocate(pVM, 0);
1028	}
1029	else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
1030	/* We overwrote all entries above, so we have to save them again. */
1031	selmR3SetupHyperGDTSelectors(pVM);
1032
1033	/*
1034	* Adjust the cached GDT limit.
1035	* Any GDT entries which have been removed must be cleared.
1036	*/
1037	if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1038	{
1039	if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1040	memset(pGDTE, 0, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1041	#ifndef SELM_TRACK_GUEST_GDT_CHANGES
1042	pVM->selm.s.GuestGdtr.cbGdt = GDTR.cbGdt;
1043	#endif
1044	}
1045
1046	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1047	/*
1048	* Check if Guest's GDTR is changed.
1049	*/
1050	if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1051	\|\| GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1052	{
1053	Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1054
1055	/*
1056	* [Re]Register write virtual handler for guest's GDT.
1057	*/
1058	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1059	{
1060	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1061	AssertRC(rc);
1062	}
1063
1064	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1065	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0, "Guest GDT write access handler");
1066	if (RT_FAILURE(rc))
1067	return rc;
1068
1069	/* Update saved Guest GDTR. */
1070	pVM->selm.s.GuestGdtr = GDTR;
1071	pVM->selm.s.fGDTRangeRegistered = true;
1072	}
1073	#endif
1074	}
1075
1076	/*
1077	* TSS sync
1078	*/
1079	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
1080	{
1081	SELMR3SyncTSS(pVM);
1082	}
1083
1084	/*
1085	* LDT sync
1086	*/
1087	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_LDT))
1088	{
1089	/*
1090	* Always assume the best
1091	*/
1092	VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
1093
1094	/*
1095	* LDT handling is done similarly to the GDT handling with a shadow
1096	* array. However, since the LDT is expected to be swappable (at least
1097	* some ancient OSes makes it swappable) it must be floating and
1098	* synced on a per-page basis.
1099	*
1100	* Eventually we will change this to be fully on demand. Meaning that
1101	* we will only sync pages containing LDT selectors actually used and
1102	* let the #PF handler lazily sync pages as they are used.
1103	* (This applies to GDT too, when we start making OS/2 fast.)
1104	*/
1105
1106	/*
1107	* First, determin the current LDT selector.
1108	*/
1109	RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
1110	if ((SelLdt & X86_SEL_MASK) == 0)
1111	{
1112	/* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1113	CPUMSetHyperLDTR(pVM, 0);
1114	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1115	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1116	{
1117	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1118	AssertRC(rc);
1119	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1120	}
1121	#endif
1122	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1123	return VINF_SUCCESS;
1124	}
1125
1126	/*
1127	* Get the LDT selector.
1128	*/
1129	PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1130	RTGCPTR GCPtrLdt = X86DESC_BASE(*pDesc);
1131	unsigned cbLdt = X86DESC_LIMIT(*pDesc);
1132	if (pDesc->Gen.u1Granularity)
1133	cbLdt = (cbLdt << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
1134
1135	/*
1136	* Validate it.
1137	*/
1138	if ( !cbLdt
1139	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1140	\|\| pDesc->Gen.u1DescType
1141	\|\| pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1142	{
1143	AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1144
1145	/* cbLdt > 0:
1146	* This is quite impossible, so we do as most people do when faced with
1147	* the impossible, we simply ignore it.
1148	*/
1149	CPUMSetHyperLDTR(pVM, 0);
1150	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1151	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1152	{
1153	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1154	AssertRC(rc);
1155	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1156	}
1157	#endif
1158	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1159	return VINF_SUCCESS;
1160	}
1161	/** @todo check what intel does about odd limits. */
1162	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1163
1164	/*
1165	* Use the cached guest ldt address if the descriptor has already been modified (see below)
1166	* (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1167	*/
1168	if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1169	GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1170
1171
1172	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1173	/** @todo Handle only present LDT segments. */
1174	// if (pDesc->Gen.u1Present)
1175	{
1176	/*
1177	* Check if Guest's LDT address/limit is changed.
1178	*/
1179	if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1180	\|\| cbLdt != pVM->selm.s.cbLdtLimit)
1181	{
1182	Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1183	pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1184
1185	/*
1186	* [Re]Register write virtual handler for guest's GDT.
1187	* In the event of LDT overlapping something, don't install it just assume it's being updated.
1188	*/
1189	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1190	{
1191	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1192	AssertRC(rc);
1193	}
1194	#ifdef DEBUG
1195	if (pDesc->Gen.u1Present)
1196	Log(("LDT selector marked not present!!\n"));
1197	#endif
1198	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1199	0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1200	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1201	{
1202	/** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1203	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1204	Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1205	GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1206	}
1207	else if (RT_SUCCESS(rc))
1208	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1209	else
1210	{
1211	CPUMSetHyperLDTR(pVM, 0);
1212	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1213	return rc;
1214	}
1215
1216	pVM->selm.s.cbLdtLimit = cbLdt;
1217	}
1218	}
1219	#else
1220	pVM->selm.s.cbLdtLimit = cbLdt;
1221	#endif
1222
1223	/*
1224	* Calc Shadow LDT base.
1225	*/
1226	unsigned off;
1227	pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1228	RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1229	PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1230
1231	/*
1232	* Enable the LDT selector in the shadow GDT.
1233	*/
1234	pDesc->Gen.u1Present = 1;
1235	pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1236	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1237	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1238	pDesc->Gen.u1Available = 0;
1239	pDesc->Gen.u1Long = 0;
1240	if (cbLdt > 0xffff)
1241	{
1242	cbLdt = 0xffff;
1243	pDesc->Gen.u4LimitHigh = 0;
1244	pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1245	}
1246
1247	/*
1248	* Set Hyper LDTR and notify TRPM.
1249	*/
1250	CPUMSetHyperLDTR(pVM, SelLdt);
1251
1252	/*
1253	* Loop synchronising the LDT page by page.
1254	*/
1255	/** @todo investigate how intel handle various operations on half present cross page entries. */
1256	off = GCPtrLdt & (sizeof(X86DESC) - 1);
1257	AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1258
1259	/* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1260	unsigned cbLeft = cbLdt + 1;
1261	PX86DESC pLDTE = pShadowLDT;
1262	while (cbLeft)
1263	{
1264	/*
1265	* Read a chunk.
1266	*/
1267	unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1268	if (cbChunk > cbLeft)
1269	cbChunk = cbLeft;
1270	rc = PGMPhysSimpleReadGCPtr(pVM, pShadowLDT, GCPtrLdt, cbChunk);
1271	if (RT_SUCCESS(rc))
1272	{
1273	/*
1274	* Mark page
1275	*/
1276	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
1277	AssertRC(rc);
1278
1279	/*
1280	* Loop thru the available LDT entries.
1281	* Figure out where to start and end and the potential cross pageness of
1282	* things adds a little complexity. pLDTE is updated there and not in the
1283	* 'next' part of the loop. The pLDTEEnd is inclusive.
1284	*/
1285	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1286	if (pLDTE + 1 < pShadowLDT)
1287	pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1288	while (pLDTE <= pLDTEEnd)
1289	{
1290	if (pLDTE->Gen.u1Present)
1291	{
1292	/*
1293	* Code and data selectors are generally 1:1, with the
1294	* 'little' adjustment we do for DPL 0 selectors.
1295	*/
1296	if (pLDTE->Gen.u1DescType)
1297	{
1298	/*
1299	* Hack for A-bit against Trap E on read-only GDT.
1300	*/
1301	/** @todo Fix this by loading ds and cs before turning off WP. */
1302	if (!(pLDTE->Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1303	pLDTE->Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
1304
1305	/*
1306	* All DPL 0 code and data segments are squeezed into DPL 1.
1307	*
1308	* We're skipping conforming segments here because those
1309	* cannot give us any trouble.
1310	*/
1311	if ( pLDTE->Gen.u2Dpl == 0
1312	&& (pLDTE->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
1313	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF) )
1314	pLDTE->Gen.u2Dpl = 1;
1315	}
1316	else
1317	{
1318	/*
1319	* System type selectors are marked not present.
1320	* Recompiler or special handling is required for these.
1321	*/
1322	/** @todo what about interrupt gates and rawr0? */
1323	pLDTE->Gen.u1Present = 0;
1324	}
1325	}
1326
1327	/* Next LDT entry. */
1328	pLDTE++;
1329	}
1330	}
1331	else
1332	{
1333	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1334	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1335	AssertRC(rc);
1336	}
1337
1338	/*
1339	* Advance to the next page.
1340	*/
1341	cbLeft -= cbChunk;
1342	GCPtrShadowLDT += cbChunk;
1343	pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1344	GCPtrLdt += cbChunk;
1345	}
1346	}
1347
1348	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1349	return VINF_SUCCESS;
1350	}
1351
1352
1353	/**
1354	* \#PF Handler callback for virtual access handler ranges.
1355	*
1356	* Important to realize that a physical page in a range can have aliases, and
1357	* for ALL and WRITE handlers these will also trigger.
1358	*
1359	* @returns VINF_SUCCESS if the handler have carried out the operation.
1360	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1361	* @param pVM VM Handle.
1362	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1363	* @param pvPtr The HC mapping of that address.
1364	* @param pvBuf What the guest is reading/writing.
1365	* @param cbBuf How much it's reading/writing.
1366	* @param enmAccessType The access type.
1367	* @param pvUser User argument.
1368	*/
1369	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1370	{
1371	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1372	Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1373	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
1374
1375	return VINF_PGM_HANDLER_DO_DEFAULT;
1376	}
1377
1378
1379	/**
1380	* \#PF Handler callback for virtual access handler ranges.
1381	*
1382	* Important to realize that a physical page in a range can have aliases, and
1383	* for ALL and WRITE handlers these will also trigger.
1384	*
1385	* @returns VINF_SUCCESS if the handler have carried out the operation.
1386	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1387	* @param pVM VM Handle.
1388	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1389	* @param pvPtr The HC mapping of that address.
1390	* @param pvBuf What the guest is reading/writing.
1391	* @param cbBuf How much it's reading/writing.
1392	* @param enmAccessType The access type.
1393	* @param pvUser User argument.
1394	*/
1395	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1396	{
1397	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1398	Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1399	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
1400	return VINF_PGM_HANDLER_DO_DEFAULT;
1401	}
1402
1403
1404	/**
1405	* \#PF Handler callback for virtual access handler ranges.
1406	*
1407	* Important to realize that a physical page in a range can have aliases, and
1408	* for ALL and WRITE handlers these will also trigger.
1409	*
1410	* @returns VINF_SUCCESS if the handler have carried out the operation.
1411	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1412	* @param pVM VM Handle.
1413	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1414	* @param pvPtr The HC mapping of that address.
1415	* @param pvBuf What the guest is reading/writing.
1416	* @param cbBuf How much it's reading/writing.
1417	* @param enmAccessType The access type.
1418	* @param pvUser User argument.
1419	*/
1420	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1421	{
1422	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1423	Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1424
1425	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
1426
1427	return VINF_PGM_HANDLER_DO_DEFAULT;
1428	}
1429
1430
1431	/**
1432	* Synchronize the shadowed fields in the TSS.
1433	*
1434	* At present we're shadowing the ring-0 stack selector & pointer, and the
1435	* interrupt redirection bitmap (if present). We take the lazy approach wrt to
1436	* REM and this function is called both if REM made any changes to the TSS or
1437	* loaded TR.
1438	*
1439	* @returns VBox status code.
1440	* @param pVM The VM to operate on.
1441	*/
1442	VMMR3DECL(int) SELMR3SyncTSS(PVM pVM)
1443	{
1444	int rc;
1445
1446	if (pVM->selm.s.fDisableMonitoring)
1447	{
1448	VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
1449	return VINF_SUCCESS;
1450	}
1451
1452	STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1453	Assert(VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS));
1454
1455	/*
1456	* Get TR and extract and store the basic info.
1457	*
1458	* Note! The TSS limit is not checked by the LTR code, so we
1459	* have to be a bit careful with it. We make sure cbTss
1460	* won't be zero if TR is valid and if it's NULL we'll
1461	* make sure cbTss is 0.
1462	*/
1463	CPUMSELREGHID trHid;
1464	RTSEL SelTss = CPUMGetGuestTR(pVM, &trHid);
1465	RTGCPTR GCPtrTss = trHid.u64Base;
1466	uint32_t cbTss = trHid.u32Limit;
1467	Assert( (SelTss & X86_SEL_MASK)
1468	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1469	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1470	if (SelTss & X86_SEL_MASK)
1471	{
1472	Assert(!(SelTss & X86_SEL_LDT));
1473	Assert(trHid.Attr.n.u1DescType == 0);
1474	Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1475	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1476	if (++cbTss)
1477	cbTss = UINT32_MAX;
1478	}
1479	else
1480	{
1481	Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1482	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1483	cbTss = 0; /* the reset case. */
1484	}
1485	pVM->selm.s.cbGuestTss = cbTss;
1486	pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1487	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1488
1489	/*
1490	* Presently we monitor the TSS and the interrupt redirection bitmap if it's present.
1491	* We're assuming the guest is playing nice and that the bits we're monitoring won't
1492	* cross page boundraries. (The TSS core must be on a single page, while the bitmap
1493	* probably doesn't need to be.)
1494	*/
1495	uint32_t cbMonitoredTss = cbTss > sizeof(VBOXTSS) ? sizeof(VBOXTSS) : cbTss;
1496
1497	/*
1498	* We're also completely uninterested in a 16-bit TSS.
1499	*/
1500	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1501	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1502	cbMonitoredTss = 0;
1503	AssertMsg((GCPtrTss >> PAGE_SHIFT) == ((GCPtrTss + cbMonitoredTss - 1) >> PAGE_SHIFT) \|\| !cbMonitoredTss,
1504	("GCPtrTss=%RGv cbMonitoredTss=%#x - We assume everything is inside one page!\n", GCPtrTss, cbMonitoredTss));
1505
1506	/*
1507	* Check for monitor changes and apply them.
1508	*/
1509	if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1510	\|\| cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1511	{
1512	Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1513	GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1514
1515	/* Release the old range first. */
1516	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1517	{
1518	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1519	AssertRC(rc);
1520	}
1521
1522	/* Register the write handler if TS != 0. */
1523	if (cbMonitoredTss != 0)
1524	{
1525	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1526	0, selmR3GuestTSSWriteHandler,
1527	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1528	if (RT_FAILURE(rc))
1529	{
1530	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1531	return rc;
1532	}
1533
1534	/* Update saved Guest TSS info. */
1535	pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1536	pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1537	pVM->selm.s.GCSelTss = SelTss;
1538	}
1539	else
1540	{
1541	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1542	pVM->selm.s.cbMonitoredGuestTss = 0;
1543	pVM->selm.s.GCSelTss = 0;
1544	}
1545	}
1546
1547	/*
1548	* Update the ring 0 stack selector and base address.
1549	* (Reading up to and including offIoBitmap to save effort in the VME case.)
1550	*/
1551	bool fNoRing1Stack = true;
1552	if (cbMonitoredTss)
1553	{
1554	VBOXTSS Tss;
1555	rc = PGMPhysSimpleReadGCPtr(pVM, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, offIoBitmap) + sizeof(Tss.offIoBitmap));
1556	if (RT_SUCCESS(rc))
1557	{
1558	#ifdef LOG_ENABLED
1559	if (LogIsEnabled())
1560	{
1561	uint32_t ssr0, espr0;
1562	SELMGetRing1Stack(pVM, &ssr0, &espr0);
1563	if ((ssr0 & ~1) != Tss.ss0 \|\| espr0 != Tss.esp0)
1564	{
1565	RTGCPHYS GCPhys = NIL_RTGCPHYS;
1566	rc = PGMGstGetPage(pVM, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1567	Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%VGp)\n",
1568	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1569	AssertMsg(ssr0 != Tss.ss0,
1570	("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%VGp)\n",
1571	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1572	}
1573	Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1574	}
1575	#endif /* LOG_ENABLED */
1576	AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1577
1578
1579	/* Update our TSS structure for the guest's ring 1 stack */
1580	selmSetRing1Stack(pVM, Tss.ss0 \| 1, Tss.esp0);
1581	pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1582
1583	/*
1584	* Should we sync the virtual interrupt redirection bitmap as well?
1585	*/
1586	if (CPUMGetGuestCR4(pVM) & X86_CR4_VME)
1587	{
1588	/* Make sure the io bitmap offset is valid; anything less than sizeof(VBOXTSS) means there's none. */
1589	if (Tss.offIoBitmap < RT_OFFSETOF(VBOXTSS, IntRedirBitmap) + sizeof(Tss.IntRedirBitmap))
1590	{
1591	Log(("Invalid io bitmap offset detected (%x)!\n", Tss.offIoBitmap));
1592	Tss.offIoBitmap = RT_OFFSETOF(VBOXTSS, IntRedirBitmap) + sizeof(Tss.IntRedirBitmap);
1593	}
1594
1595	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1596
1597	/** @todo not sure how the partial case is handled; probably not allowed */
1598	if (offRedirBitmap + sizeof(Tss.IntRedirBitmap) <= pVM->selm.s.cbGuestTss)
1599	{
1600	rc = PGMPhysSimpleReadGCPtr(pVM, &pVM->selm.s.Tss.IntRedirBitmap, GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1601	AssertRC(rc);
1602	Log2(("Redirection bitmap:\n"));
1603	Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1604	}
1605	}
1606	}
1607	}
1608
1609	/*
1610	* Flush the ring-1 stack and the direct syscall dispatching if we cannot obtain SS0:ESP0.
1611	*/
1612	if (fNoRing1Stack)
1613	{
1614	selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1615	pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1616
1617	/** @todo handle these dependencies better! */
1618	TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1619	TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1620	}
1621
1622	VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
1623
1624	STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1625	return VINF_SUCCESS;
1626	}
1627
1628
1629	/**
1630	* Compares the Guest GDT and LDT with the shadow tables.
1631	* This is a VBOX_STRICT only function.
1632	*
1633	* @returns VBox status code.
1634	* @param pVM The VM Handle.
1635	*/
1636	VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1637	{
1638	#ifdef VBOX_STRICT
1639	/*
1640	* Get GDTR and check for conflict.
1641	*/
1642	VBOXGDTR GDTR;
1643	CPUMGetGuestGDTR(pVM, &GDTR);
1644	if (GDTR.cbGdt == 0)
1645	return VINF_SUCCESS;
1646
1647	if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1648	Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1649
1650	if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1651	Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1652
1653	/*
1654	* Loop thru the GDT checking each entry.
1655	*/
1656	RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1657	PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1658	PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1659	while (pGDTE < pGDTEEnd)
1660	{
1661	X86DESC GDTEGuest;
1662	int rc = PGMPhysSimpleReadGCPtr(pVM, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1663	if (RT_SUCCESS(rc))
1664	{
1665	if (pGDTE->Gen.u1DescType \|\| pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1666	{
1667	if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1668	\|\| pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1669	\|\| pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1670	\|\| pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1671	\|\| pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1672	\|\| pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1673	\|\| pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1674	{
1675	unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1676	SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1677	SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1678	}
1679	}
1680	}
1681
1682	/* Advance to the next descriptor. */
1683	GCPtrGDTEGuest += sizeof(X86DESC);
1684	pGDTE++;
1685	}
1686
1687
1688	/*
1689	* LDT?
1690	*/
1691	RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
1692	if ((SelLdt & X86_SEL_MASK) == 0)
1693	return VINF_SUCCESS;
1694	if (SelLdt > GDTR.cbGdt)
1695	{
1696	Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1697	return VERR_INTERNAL_ERROR;
1698	}
1699	X86DESC LDTDesc;
1700	int rc = PGMPhysSimpleReadGCPtr(pVM, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1701	if (RT_FAILURE(rc))
1702	{
1703	Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1704	return rc;
1705	}
1706	RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(LDTDesc);
1707	unsigned cbLdt = X86DESC_LIMIT(LDTDesc);
1708	if (LDTDesc.Gen.u1Granularity)
1709	cbLdt = (cbLdt << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
1710
1711	/*
1712	* Validate it.
1713	*/
1714	if (!cbLdt)
1715	return VINF_SUCCESS;
1716	/** @todo check what intel does about odd limits. */
1717	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1718	if ( LDTDesc.Gen.u1DescType
1719	\|\| LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1720	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1721	{
1722	Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1723	return VERR_INTERNAL_ERROR;
1724	}
1725
1726	/*
1727	* Loop thru the LDT checking each entry.
1728	*/
1729	unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1730	PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1731	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1732	while (pLDTE < pLDTEEnd)
1733	{
1734	X86DESC LDTEGuest;
1735	int rc = PGMPhysSimpleReadGCPtr(pVM, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1736	if (RT_SUCCESS(rc))
1737	{
1738	if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1739	\|\| pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1740	\|\| pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1741	\|\| pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1742	\|\| pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1743	\|\| pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1744	\|\| pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1745	{
1746	unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1747	SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1748	SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1749	}
1750	}
1751
1752	/* Advance to the next descriptor. */
1753	GCPtrLDTEGuest += sizeof(X86DESC);
1754	pLDTE++;
1755	}
1756
1757	#else /* !VBOX_STRICT */
1758	NOREF(pVM);
1759	#endif /* !VBOX_STRICT */
1760
1761	return VINF_SUCCESS;
1762	}
1763
1764
1765	/**
1766	* Validates the RawR0 TSS values against the one in the Guest TSS.
1767	*
1768	* @returns true if it matches.
1769	* @returns false and assertions on mismatch..
1770	* @param pVM VM Handle.
1771	*/
1772	VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1773	{
1774	#ifdef VBOX_STRICT
1775	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
1776	return true;
1777
1778	/*
1779	* Get TR and extract the basic info.
1780	*/
1781	CPUMSELREGHID trHid;
1782	RTSEL SelTss = CPUMGetGuestTR(pVM, &trHid);
1783	RTGCPTR GCPtrTss = trHid.u64Base;
1784	uint32_t cbTss = trHid.u32Limit;
1785	Assert( (SelTss & X86_SEL_MASK)
1786	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1787	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1788	if (SelTss & X86_SEL_MASK)
1789	{
1790	AssertReturn(!(SelTss & X86_SEL_LDT), false);
1791	AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1792	AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1793	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1794	false);
1795	if (++cbTss)
1796	cbTss = UINT32_MAX;
1797	}
1798	else
1799	{
1800	AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1801	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */),
1802	false);
1803	cbTss = 0; /* the reset case. */
1804	}
1805	AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1806	AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1807	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1808	("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1809	false);
1810	AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1811	\|\| (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1812	("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1813	false);
1814	AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1815	\|\| (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1816	("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1817	false);
1818
1819	/*
1820	* Cap the TSS size, see SELMR3SyncTSS for details.
1821	*/
1822	uint32_t cbMonitoredTss = cbTss > sizeof(VBOXTSS) ? sizeof(VBOXTSS) : cbTss;
1823	AssertMsg((GCPtrTss >> PAGE_SHIFT) == ((GCPtrTss + cbMonitoredTss - 1) >> PAGE_SHIFT) \|\| !cbMonitoredTss,
1824	("GCPtrTss=%RGv cbMonitoredTss=%#x - We assume everything is inside one page!\n", GCPtrTss, cbMonitoredTss));
1825	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1826
1827	/*
1828	* Check SS0 and ESP0.
1829	*/
1830	if ( cbMonitoredTss
1831	&& !pVM->selm.s.fSyncTSSRing0Stack)
1832	{
1833	RTGCPTR GCPtrGuestTSS = pVM->selm.s.GCPtrGuestTss;
1834	uint32_t ESPR0;
1835	int rc = PGMPhysSimpleReadGCPtr(pVM, &ESPR0, GCPtrGuestTSS + RT_OFFSETOF(VBOXTSS, esp0), sizeof(ESPR0));
1836	if (RT_SUCCESS(rc))
1837	{
1838	RTSEL SelSS0;
1839	rc = PGMPhysSimpleReadGCPtr(pVM, &SelSS0, GCPtrGuestTSS + RT_OFFSETOF(VBOXTSS, ss0), sizeof(SelSS0));
1840	AssertRCReturn(rc, false);
1841
1842	if ( ESPR0 != pVM->selm.s.Tss.esp1
1843	\|\| SelSS0 != (pVM->selm.s.Tss.ss1 & ~1))
1844	{
1845	RTGCPHYS GCPhys;
1846	rc = PGMGstGetPage(pVM, GCPtrGuestTSS, NULL, &GCPhys); AssertRC(rc);
1847	AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
1848	(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1, SelSS0, ESPR0, GCPtrGuestTSS, GCPhys));
1849	return false;
1850	}
1851	}
1852	else
1853	/* Happens during early Windows XP boot when it is switching page tables. */
1854	AssertReturn(rc == VINF_SUCCESS \|\| ((rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT) && !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF)),
1855	false);
1856	}
1857	else if (!cbMonitoredTss)
1858	{
1859	AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
1860	AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
1861	}
1862	return true;
1863
1864	#else /* !VBOX_STRICT */
1865	NOREF(pVM);
1866	return true;
1867	#endif /* !VBOX_STRICT */
1868	}
1869
1870
1871	/**
1872	* Returns flat address and limit of LDT by LDT selector from guest GDTR.
1873	*
1874	* Fully validate selector.
1875	*
1876	* @returns VBox status.
1877	* @param pVM VM Handle.
1878	* @param SelLdt LDT selector.
1879	* @param ppvLdt Where to store the flat address of LDT.
1880	* @param pcbLimit Where to store LDT limit.
1881	*/
1882	VMMDECL(int) SELMGetLDTFromSel(PVM pVM, RTSEL SelLdt, PRTGCPTR ppvLdt, unsigned *pcbLimit)
1883	{
1884	/* Get guest GDTR. */
1885	VBOXGDTR GDTR;
1886	CPUMGetGuestGDTR(pVM, &GDTR);
1887
1888	/* Check selector TI and GDT limit. */
1889	if ( SelLdt & X86_SEL_LDT
1890	\|\| (SelLdt > GDTR.cbGdt))
1891	return VERR_INVALID_SELECTOR;
1892
1893	/* Read descriptor from GC. */
1894	X86DESC Desc;
1895	int rc = PGMPhysSimpleReadGCPtr(pVM, (void *)&Desc, (RTGCPTR)(GDTR.pGdt + (SelLdt & X86_SEL_MASK)), sizeof(Desc));
1896	if (RT_FAILURE(rc))
1897	{
1898	/* fatal */
1899	AssertMsgFailed(("Can't read LDT descriptor for selector=%04X\n", SelLdt));
1900	return VERR_SELECTOR_NOT_PRESENT;
1901	}
1902
1903	/* Check if LDT descriptor is not present. */
1904	if (Desc.Gen.u1Present == 0)
1905	return VERR_SELECTOR_NOT_PRESENT;
1906
1907	/* Check LDT descriptor type. */
1908	if ( Desc.Gen.u1DescType == 1
1909	\|\| Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1910	return VERR_INVALID_SELECTOR;
1911
1912	/* LDT descriptor is ok. */
1913	if (ppvLdt)
1914	{
1915	*ppvLdt = (RTGCPTR)X86DESC_BASE(Desc);
1916	*pcbLimit = X86DESC_LIMIT(Desc);
1917	}
1918	return VINF_SUCCESS;
1919	}
1920
1921
1922	/**
1923	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
1924	*
1925	* See SELMR3GetSelectorInfo for details.
1926	*
1927	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
1928	*
1929	* @param pVM VM handle.
1930	* @param Sel The selector to get info about.
1931	* @param pSelInfo Where to store the information.
1932	*/
1933	static int selmR3GetSelectorInfo64(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
1934	{
1935	pSelInfo->fHyper = false;
1936
1937	/*
1938	* Read it from the guest descriptor table.
1939	*/
1940	X86DESC64 Desc;
1941	VBOXGDTR Gdtr;
1942	RTGCPTR GCPtrDesc;
1943	CPUMGetGuestGDTR(pVM, &Gdtr);
1944	if (!(Sel & X86_SEL_LDT))
1945	{
1946	/* GDT */
1947	if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
1948	return VERR_INVALID_SELECTOR;
1949	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
1950	}
1951	else
1952	{
1953	/*
1954	* LDT - must locate the LDT first...
1955	*/
1956	RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
1957	if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */
1958	\|\| (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
1959	return VERR_INVALID_SELECTOR;
1960	GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
1961	int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
1962	if (RT_FAILURE(rc))
1963	return rc;
1964
1965	/* validate the LDT descriptor. */
1966	if (Desc.Gen.u1Present == 0)
1967	return VERR_SELECTOR_NOT_PRESENT;
1968	if ( Desc.Gen.u1DescType == 1
1969	\|\| Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1970	return VERR_INVALID_SELECTOR;
1971
1972	unsigned cbLimit = X86DESC_LIMIT(Desc);
1973	if (Desc.Gen.u1Granularity)
1974	cbLimit = (cbLimit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
1975	if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
1976	return VERR_INVALID_SELECTOR;
1977
1978	/* calc the descriptor location. */
1979	GCPtrDesc = X86DESC64_BASE(Desc);
1980	GCPtrDesc += (Sel & X86_SEL_MASK);
1981	}
1982
1983	/* read the descriptor. */
1984	int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
1985	if (RT_FAILURE(rc))
1986	return rc;
1987
1988	/*
1989	* Extract the base and limit
1990	*/
1991	pSelInfo->Sel = Sel;
1992	pSelInfo->Raw64 = Desc;
1993	pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
1994	if (Desc.Gen.u1Granularity)
1995	pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
1996	pSelInfo->GCPtrBase = X86DESC64_BASE(Desc);
1997	pSelInfo->fRealMode = false;
1998
1999	return VINF_SUCCESS;
2000	}
2001
2002
2003	/**
2004	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2005	*
2006	* See SELMR3GetSelectorInfo for details.
2007	*
2008	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2009	*
2010	* @param pVM VM handle.
2011	* @param Sel The selector to get info about.
2012	* @param pSelInfo Where to store the information.
2013	*/
2014	static int selmR3GetSelectorInfo32(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
2015	{
2016	/*
2017	* Read the descriptor entry
2018	*/
2019	X86DESC Desc;
2020	if ( !(Sel & X86_SEL_LDT)
2021	&& ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2022	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2023	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2024	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2025	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK))
2026	)
2027	{
2028	/*
2029	* Hypervisor descriptor.
2030	*/
2031	pSelInfo->fHyper = true;
2032	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2033	}
2034	else if (CPUMIsGuestInProtectedMode(pVM))
2035	{
2036	/*
2037	* Read it from the guest descriptor table.
2038	*/
2039	pSelInfo->fHyper = false;
2040
2041	VBOXGDTR Gdtr;
2042	RTGCPTR GCPtrDesc;
2043	CPUMGetGuestGDTR(pVM, &Gdtr);
2044	if (!(Sel & X86_SEL_LDT))
2045	{
2046	/* GDT */
2047	if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2048	return VERR_INVALID_SELECTOR;
2049	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2050	}
2051	else
2052	{
2053	/*
2054	* LDT - must locate the LDT first...
2055	*/
2056	RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
2057	if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */
2058	\|\| (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2059	return VERR_INVALID_SELECTOR;
2060	GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2061	int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
2062	if (RT_FAILURE(rc))
2063	return rc;
2064
2065	/* validate the LDT descriptor. */
2066	if (Desc.Gen.u1Present == 0)
2067	return VERR_SELECTOR_NOT_PRESENT;
2068	if ( Desc.Gen.u1DescType == 1
2069	\|\| Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2070	return VERR_INVALID_SELECTOR;
2071
2072	unsigned cbLimit = X86DESC_LIMIT(Desc);
2073	if (Desc.Gen.u1Granularity)
2074	cbLimit = (cbLimit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
2075	if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2076	return VERR_INVALID_SELECTOR;
2077
2078	/* calc the descriptor location. */
2079	GCPtrDesc = X86DESC_BASE(Desc);
2080	GCPtrDesc += (Sel & X86_SEL_MASK);
2081	}
2082
2083	/* read the descriptor. */
2084	int rc = PGMPhysSimpleReadGCPtr(pVM, &Desc, GCPtrDesc, sizeof(Desc));
2085	if (RT_FAILURE(rc))
2086	return rc;
2087	}
2088	else
2089	{
2090	/*
2091	* We're in real mode.
2092	*/
2093	pSelInfo->Sel = Sel;
2094	pSelInfo->GCPtrBase = Sel << 4;
2095	pSelInfo->cbLimit = 0xffff;
2096	pSelInfo->fHyper = false;
2097	pSelInfo->fRealMode = true;
2098	memset(&pSelInfo->Raw, 0, sizeof(pSelInfo->Raw));
2099	return VINF_SUCCESS;
2100	}
2101
2102	/*
2103	* Extract the base and limit
2104	*/
2105	pSelInfo->Sel = Sel;
2106	pSelInfo->Raw = Desc;
2107	pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2108	if (Desc.Gen.u1Granularity)
2109	pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
2110	pSelInfo->GCPtrBase = X86DESC_BASE(Desc);
2111	pSelInfo->fRealMode = false;
2112
2113	return VINF_SUCCESS;
2114	}
2115
2116
2117	/**
2118	* Gets information about a selector.
2119	* Intended for the debugger mostly and will prefer the guest
2120	* descriptor tables over the shadow ones.
2121	*
2122	* @returns VINF_SUCCESS on success.
2123	* @returns VERR_INVALID_SELECTOR if the selector isn't fully inside the descriptor table.
2124	* @returns VERR_SELECTOR_NOT_PRESENT if the selector wasn't present.
2125	* @returns VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the pagetable or page
2126	* backing the selector table wasn't present.
2127	* @returns Other VBox status code on other errors.
2128	*
2129	* @param pVM VM handle.
2130	* @param Sel The selector to get info about.
2131	* @param pSelInfo Where to store the information.
2132	*/
2133	VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
2134	{
2135	AssertPtr(pSelInfo);
2136	if (CPUMIsGuestInLongMode(pVM))
2137	return selmR3GetSelectorInfo64(pVM, Sel, pSelInfo);
2138	return selmR3GetSelectorInfo32(pVM, Sel, pSelInfo);
2139	}
2140
2141
2142	/**
2143	* Gets information about a selector from the shadow tables.
2144	*
2145	* This is intended to be faster than the SELMR3GetSelectorInfo() method, but requires
2146	* that the caller ensures that the shadow tables are up to date.
2147	*
2148	* @returns VINF_SUCCESS on success.
2149	* @returns VERR_INVALID_SELECTOR if the selector isn't fully inside the descriptor table.
2150	* @returns VERR_SELECTOR_NOT_PRESENT if the selector wasn't present.
2151	* @returns VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the pagetable or page
2152	* backing the selector table wasn't present.
2153	* @returns Other VBox status code on other errors.
2154	*
2155	* @param pVM VM handle.
2156	* @param Sel The selector to get info about.
2157	* @param pSelInfo Where to store the information.
2158	*/
2159	VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
2160	{
2161	Assert(pSelInfo);
2162
2163	/*
2164	* Read the descriptor entry
2165	*/
2166	X86DESC Desc;
2167	if (!(Sel & X86_SEL_LDT))
2168	{
2169	/*
2170	* Global descriptor.
2171	*/
2172	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2173	pSelInfo->fHyper = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2174	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2175	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2176	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2177	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK);
2178	/** @todo check that the GDT offset is valid. */
2179	}
2180	else
2181	{
2182	/*
2183	* Local Descriptor.
2184	*/
2185	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2186	Desc = paLDT[Sel >> X86_SEL_SHIFT];
2187	/** @todo check if the LDT page is actually available. */
2188	/** @todo check that the LDT offset is valid. */
2189	pSelInfo->fHyper = false;
2190	}
2191
2192	/*
2193	* Extract the base and limit
2194	*/
2195	pSelInfo->Sel = Sel;
2196	pSelInfo->Raw = Desc;
2197	pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2198	if (Desc.Gen.u1Granularity)
2199	pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
2200	pSelInfo->GCPtrBase = X86DESC_BASE(Desc);
2201	pSelInfo->fRealMode = false;
2202
2203	return VINF_SUCCESS;
2204	}
2205
2206
2207	/**
2208	* Formats a descriptor.
2209	*
2210	* @param Desc Descriptor to format.
2211	* @param Sel Selector number.
2212	* @param pszOutput Output buffer.
2213	* @param cchOutput Size of output buffer.
2214	*/
2215	static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2216	{
2217	/*
2218	* Make variable description string.
2219	*/
2220	static struct
2221	{
2222	unsigned cch;
2223	const char *psz;
2224	} const aTypes[32] =
2225	{
2226	#define STRENTRY(str) { sizeof(str) - 1, str }
2227	/* system */
2228	STRENTRY("Reserved0 "), /* 0x00 */
2229	STRENTRY("TSS16Avail "), /* 0x01 */
2230	STRENTRY("LDT "), /* 0x02 */
2231	STRENTRY("TSS16Busy "), /* 0x03 */
2232	STRENTRY("Call16 "), /* 0x04 */
2233	STRENTRY("Task "), /* 0x05 */
2234	STRENTRY("Int16 "), /* 0x06 */
2235	STRENTRY("Trap16 "), /* 0x07 */
2236	STRENTRY("Reserved8 "), /* 0x08 */
2237	STRENTRY("TSS32Avail "), /* 0x09 */
2238	STRENTRY("ReservedA "), /* 0x0a */
2239	STRENTRY("TSS32Busy "), /* 0x0b */
2240	STRENTRY("Call32 "), /* 0x0c */
2241	STRENTRY("ReservedD "), /* 0x0d */
2242	STRENTRY("Int32 "), /* 0x0e */
2243	STRENTRY("Trap32 "), /* 0x0f */
2244	/* non system */
2245	STRENTRY("DataRO "), /* 0x10 */
2246	STRENTRY("DataRO Accessed "), /* 0x11 */
2247	STRENTRY("DataRW "), /* 0x12 */
2248	STRENTRY("DataRW Accessed "), /* 0x13 */
2249	STRENTRY("DataDownRO "), /* 0x14 */
2250	STRENTRY("DataDownRO Accessed "), /* 0x15 */
2251	STRENTRY("DataDownRW "), /* 0x16 */
2252	STRENTRY("DataDownRW Accessed "), /* 0x17 */
2253	STRENTRY("CodeEO "), /* 0x18 */
2254	STRENTRY("CodeEO Accessed "), /* 0x19 */
2255	STRENTRY("CodeER "), /* 0x1a */
2256	STRENTRY("CodeER Accessed "), /* 0x1b */
2257	STRENTRY("CodeConfEO "), /* 0x1c */
2258	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2259	STRENTRY("CodeConfER "), /* 0x1e */
2260	STRENTRY("CodeConfER Accessed ") /* 0x1f */
2261	#undef SYSENTRY
2262	};
2263	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2264	char szMsg[128];
2265	char *psz = &szMsg[0];
2266	unsigned i = Desc.Gen.u1DescType << 4 \| Desc.Gen.u4Type;
2267	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2268	psz += aTypes[i].cch;
2269
2270	if (Desc.Gen.u1Present)
2271	ADD_STR(psz, "Present ");
2272	else
2273	ADD_STR(psz, "Not-Present ");
2274	if (Desc.Gen.u1Granularity)
2275	ADD_STR(psz, "Page ");
2276	if (Desc.Gen.u1DefBig)
2277	ADD_STR(psz, "32-bit ");
2278	else
2279	ADD_STR(psz, "16-bit ");
2280	#undef ADD_STR
2281	*psz = '\0';
2282
2283	/*
2284	* Limit and Base and format the output.
2285	*/
2286	uint32_t u32Limit = X86DESC_LIMIT(Desc);
2287	if (Desc.Gen.u1Granularity)
2288	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
2289	uint32_t u32Base = X86DESC_BASE(Desc);
2290
2291	RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2292	Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2293	}
2294
2295
2296	/**
2297	* Dumps a descriptor.
2298	*
2299	* @param Desc Descriptor to dump.
2300	* @param Sel Selector number.
2301	* @param pszMsg Message to prepend the log entry with.
2302	*/
2303	VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2304	{
2305	char szOutput[128];
2306	selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2307	Log(("%s: %s\n", pszMsg, szOutput));
2308	NOREF(szOutput[0]);
2309	}
2310
2311
2312	/**
2313	* Display the shadow gdt.
2314	*
2315	* @param pVM VM Handle.
2316	* @param pHlp The info helpers.
2317	* @param pszArgs Arguments, ignored.
2318	*/
2319	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2320	{
2321	pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2322	for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2323	{
2324	if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2325	{
2326	char szOutput[128];
2327	selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2328	const char *psz = "";
2329	if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2330	psz = " HyperCS";
2331	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2332	psz = " HyperDS";
2333	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2334	psz = " HyperCS64";
2335	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2336	psz = " HyperTSS";
2337	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2338	psz = " HyperTSSTrap08";
2339	pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2340	}
2341	}
2342	}
2343
2344
2345	/**
2346	* Display the guest gdt.
2347	*
2348	* @param pVM VM Handle.
2349	* @param pHlp The info helpers.
2350	* @param pszArgs Arguments, ignored.
2351	*/
2352	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2353	{
2354	VBOXGDTR GDTR;
2355	CPUMGetGuestGDTR(pVM, &GDTR);
2356	RTGCPTR GCPtrGDT = GDTR.pGdt;
2357	unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2358
2359	pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2360	for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2361	{
2362	X86DESC GDTE;
2363	int rc = PGMPhysSimpleReadGCPtr(pVM, &GDTE, GCPtrGDT, sizeof(GDTE));
2364	if (RT_SUCCESS(rc))
2365	{
2366	if (GDTE.Gen.u1Present)
2367	{
2368	char szOutput[128];
2369	selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2370	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2371	}
2372	}
2373	else if (rc == VERR_PAGE_NOT_PRESENT)
2374	{
2375	if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2376	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2377	}
2378	else
2379	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2380	}
2381	}
2382
2383
2384	/**
2385	* Display the shadow ldt.
2386	*
2387	* @param pVM VM Handle.
2388	* @param pHlp The info helpers.
2389	* @param pszArgs Arguments, ignored.
2390	*/
2391	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2392	{
2393	unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2394	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2395	pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2396	for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2397	{
2398	if (paLDT[iLDT].Gen.u1Present)
2399	{
2400	char szOutput[128];
2401	selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2402	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2403	}
2404	}
2405	}
2406
2407
2408	/**
2409	* Display the guest ldt.
2410	*
2411	* @param pVM VM Handle.
2412	* @param pHlp The info helpers.
2413	* @param pszArgs Arguments, ignored.
2414	*/
2415	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2416	{
2417	RTSEL SelLdt = CPUMGetGuestLDTR(pVM);
2418	if (!(SelLdt & X86_SEL_MASK))
2419	{
2420	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2421	return;
2422	}
2423
2424	RTGCPTR GCPtrLdt;
2425	unsigned cbLdt;
2426	int rc = SELMGetLDTFromSel(pVM, SelLdt, &GCPtrLdt, &cbLdt);
2427	if (RT_FAILURE(rc))
2428	{
2429	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): rc=%Rrc\n", SelLdt, rc);
2430	return;
2431	}
2432
2433	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RGv limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2434	unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2435	for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2436	{
2437	X86DESC LdtE;
2438	int rc = PGMPhysSimpleReadGCPtr(pVM, &LdtE, GCPtrLdt, sizeof(LdtE));
2439	if (RT_SUCCESS(rc))
2440	{
2441	if (LdtE.Gen.u1Present)
2442	{
2443	char szOutput[128];
2444	selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2445	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2446	}
2447	}
2448	else if (rc == VERR_PAGE_NOT_PRESENT)
2449	{
2450	if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2451	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, GCPtrLdt);
2452	}
2453	else
2454	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, rc, GCPtrLdt);
2455	}
2456	}
2457
2458
2459	/**
2460	* Dumps the hypervisor GDT
2461	*
2462	* @param pVM VM handle.
2463	*/
2464	VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2465	{
2466	DBGFR3Info(pVM, "gdt", NULL, NULL);
2467	}
2468
2469
2470	/**
2471	* Dumps the hypervisor LDT
2472	*
2473	* @param pVM VM handle.
2474	*/
2475	VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2476	{
2477	DBGFR3Info(pVM, "ldt", NULL, NULL);
2478	}
2479
2480
2481	/**
2482	* Dumps the guest GDT
2483	*
2484	* @param pVM VM handle.
2485	*/
2486	VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2487	{
2488	DBGFR3Info(pVM, "gdtguest", NULL, NULL);
2489	}
2490
2491
2492	/**
2493	* Dumps the guest LDT
2494	*
2495	* @param pVM VM handle.
2496	*/
2497	VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2498	{
2499	DBGFR3Info(pVM, "ldtguest", NULL, NULL);
2500	}
2501

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source: vbox/trunk/src/VBox/VMM/SELM.cpp@ 17073

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