1 | /* $Id: SELM.cpp 30647 2010-07-06 08:09:01Z vboxsync $ */
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2 | /** @file
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3 | * SELM - The Selector Manager.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2007 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 | /** @page pg_selm SELM - The Selector Manager
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19 | *
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20 | * SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
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21 | * of a few hyper selector for the raw-mode context. In the hardware assisted
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22 | * virtualization mode its only task is to decode entries in the guest GDT or
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23 | * LDT once in a while.
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24 | *
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25 | * @see grp_selm
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26 | *
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27 | *
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28 | * @section seg_selm_shadowing Shadowing
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29 | *
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30 | * SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
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31 | * work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
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32 | * The idea is to do it in a more on-demand fashion when we get time. There
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33 | * also a whole bunch of issues with the current synchronization of all three
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34 | * tables, see notes and todos in the code.
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35 | *
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36 | * When the guest makes changes to the GDT we will try update the shadow copy
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37 | * without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
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38 | *
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39 | * When the guest make LDT changes we'll trigger a full resync of the LDT
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40 | * (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
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41 | *
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42 | * The TSS shadowing is limited to the fields we need to care about, namely SS0
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43 | * and ESP0. The Patch Manager makes use of these. We monitor updates to the
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44 | * guest TSS and will try keep our SS0 and ESP0 copies up to date this way
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45 | * rather than go the SELMR3SyncTSS() route.
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46 | *
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47 | * When in raw-mode SELM also injects a few extra GDT selectors which are used
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48 | * by the raw-mode (hyper) context. These start their life at the high end of
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49 | * the table and will be relocated when the guest tries to make use of them...
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50 | * Well, that was that idea at least, only the code isn't quite there yet which
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51 | * is why we have trouble with guests which actually have a full sized GDT.
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52 | *
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53 | * So, the summary of the current GDT, LDT and TSS shadowing is that there is a
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54 | * lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
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55 | *
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56 | */
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57 |
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58 | /*******************************************************************************
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59 | * Header Files *
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60 | *******************************************************************************/
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61 | #define LOG_GROUP LOG_GROUP_SELM
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62 | #include <VBox/selm.h>
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63 | #include <VBox/cpum.h>
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64 | #include <VBox/stam.h>
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65 | #include <VBox/mm.h>
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66 | #include <VBox/ssm.h>
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67 | #include <VBox/pgm.h>
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68 | #include <VBox/trpm.h>
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69 | #include <VBox/dbgf.h>
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70 | #include "SELMInternal.h"
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71 | #include <VBox/vm.h>
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72 | #include <VBox/err.h>
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73 | #include <VBox/param.h>
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74 |
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75 | #include <iprt/assert.h>
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76 | #include <VBox/log.h>
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77 | #include <iprt/asm.h>
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78 | #include <iprt/string.h>
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79 | #include <iprt/thread.h>
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80 | #include <iprt/string.h>
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81 |
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82 |
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83 | /**
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84 | * Enable or disable tracking of Guest's GDT/LDT/TSS.
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85 | * @{
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86 | */
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87 | #define SELM_TRACK_GUEST_GDT_CHANGES
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88 | #define SELM_TRACK_GUEST_LDT_CHANGES
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89 | #define SELM_TRACK_GUEST_TSS_CHANGES
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90 | /** @} */
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91 |
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92 | /**
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93 | * Enable or disable tracking of Shadow GDT/LDT/TSS.
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94 | * @{
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95 | */
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96 | #define SELM_TRACK_SHADOW_GDT_CHANGES
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97 | #define SELM_TRACK_SHADOW_LDT_CHANGES
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98 | #define SELM_TRACK_SHADOW_TSS_CHANGES
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99 | /** @} */
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100 |
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101 |
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102 | /** SELM saved state version. */
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103 | #define SELM_SAVED_STATE_VERSION 5
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104 |
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105 |
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106 | /*******************************************************************************
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107 | * Internal Functions *
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108 | *******************************************************************************/
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109 | static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
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110 | static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
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111 | static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
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112 | static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
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113 | static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
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114 | static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
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115 | static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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116 | static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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117 | static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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118 | static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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119 | //static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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120 | //static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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121 |
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122 |
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123 |
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124 | /**
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125 | * Initializes the SELM.
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126 | *
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127 | * @returns VBox status code.
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128 | * @param pVM The VM to operate on.
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129 | */
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130 | VMMR3DECL(int) SELMR3Init(PVM pVM)
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131 | {
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132 | LogFlow(("SELMR3Init\n"));
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133 |
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134 | /*
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135 | * Assert alignment and sizes.
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136 | * (The TSS block requires contiguous back.)
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137 | */
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138 | AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
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139 | AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
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140 | #if 0 /* doesn't work */
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141 | AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
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142 | AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
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143 | #endif
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144 | AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
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145 | AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
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146 | AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
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147 |
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148 | /*
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149 | * Init the structure.
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150 | */
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151 | pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
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152 | pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
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153 | pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
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154 | pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
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155 | pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
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156 | pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
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157 |
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158 | /*
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159 | * Allocate GDT table.
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160 | */
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161 | int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
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162 | PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
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163 | AssertRCReturn(rc, rc);
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164 |
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165 | /*
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166 | * Allocate LDT area.
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167 | */
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168 | rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
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169 | AssertRCReturn(rc, rc);
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170 |
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171 | /*
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172 | * Init Guest's and Shadow GDT, LDT, TSS changes control variables.
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173 | */
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174 | pVM->selm.s.cbEffGuestGdtLimit = 0;
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175 | pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
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176 | pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
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177 | pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
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178 |
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179 | pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
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180 | pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
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181 | pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
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182 | pVM->selm.s.GCSelTss = RTSEL_MAX;
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183 |
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184 | pVM->selm.s.fDisableMonitoring = false;
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185 | pVM->selm.s.fSyncTSSRing0Stack = false;
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186 |
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187 | /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
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188 | * for I/O operations. */
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189 | pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
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190 | /* bit set to 1 means no redirection */
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191 | memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
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192 |
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193 | /*
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194 | * Register the saved state data unit.
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195 | */
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196 | rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
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197 | NULL, NULL, NULL,
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198 | NULL, selmR3Save, NULL,
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199 | NULL, selmR3Load, selmR3LoadDone);
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200 | if (RT_FAILURE(rc))
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201 | return rc;
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202 |
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203 | /*
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204 | * Statistics.
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205 | */
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206 | STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
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207 | STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
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208 | STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
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209 | STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
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210 | STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
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211 | STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
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212 | STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
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213 | STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
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214 | STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
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215 |
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216 | STAM_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
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217 | STAM_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
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218 |
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219 | /*
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220 | * Default action when entering raw mode for the first time
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221 | */
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222 | PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
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223 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
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224 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
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225 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
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226 |
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227 | /*
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228 | * Register info handlers.
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229 | */
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230 | DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
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231 | DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
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232 | DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
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233 | DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
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234 | //DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
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235 | //DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
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236 |
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237 | return rc;
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238 | }
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239 |
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240 |
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241 | /**
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242 | * Finalizes HMA page attributes.
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243 | *
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244 | * @returns VBox status code.
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245 | * @param pVM The VM handle.
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246 | */
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247 | VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
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248 | {
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249 | /** @cfgm{/DoubleFault,bool,false}
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250 | * Enables catching of double faults in the raw-mode context VMM code. This can
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251 | * be used when the tripple faults or hangs occure and one suspect an unhandled
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252 | * double fault. This is not enabled by default because it means making the
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253 | * hyper selectors writeable for all supervisor code, including the guest's.
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254 | * The double fault is a task switch and thus requires write access to the GDT
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255 | * of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
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256 | * 8 TSS for the back link.
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257 | */
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258 | bool f;
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259 | #if defined(DEBUG_bird)
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260 | int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
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261 | #else
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262 | int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
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263 | #endif
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264 | AssertLogRelRCReturn(rc, rc);
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265 | if (f)
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266 | {
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267 | PX86DESC paGdt = pVM->selm.s.paGdtR3;
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268 | rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
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269 | X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
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270 | AssertRC(rc);
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271 | rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
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272 | X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
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273 | AssertRC(rc);
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274 | rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
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275 | X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
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276 | AssertRC(rc);
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277 | rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
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278 | X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
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279 | AssertRC(rc);
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280 | }
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281 | return VINF_SUCCESS;
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282 | }
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283 |
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284 |
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285 | /**
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286 | * Setup the hypervisor GDT selectors in our shadow table
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287 | *
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288 | * @param pVM The VM handle.
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289 | */
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290 | static void selmR3SetupHyperGDTSelectors(PVM pVM)
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291 | {
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292 | PX86DESC paGdt = pVM->selm.s.paGdtR3;
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293 |
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294 | /*
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295 | * Set up global code and data descriptors for use in the guest context.
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296 | * Both are wide open (base 0, limit 4GB)
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297 | */
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298 | PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
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299 | pDesc->Gen.u16LimitLow = 0xffff;
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300 | pDesc->Gen.u4LimitHigh = 0xf;
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301 | pDesc->Gen.u16BaseLow = 0;
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302 | pDesc->Gen.u8BaseHigh1 = 0;
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303 | pDesc->Gen.u8BaseHigh2 = 0;
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304 | pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
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305 | pDesc->Gen.u1DescType = 1; /* not system, but code/data */
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306 | pDesc->Gen.u2Dpl = 0; /* supervisor */
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307 | pDesc->Gen.u1Present = 1;
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308 | pDesc->Gen.u1Available = 0;
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309 | pDesc->Gen.u1Long = 0;
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310 | pDesc->Gen.u1DefBig = 1; /* def 32 bit */
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311 | pDesc->Gen.u1Granularity = 1; /* 4KB limit */
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312 |
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313 | /* data */
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314 | pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
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315 | pDesc->Gen.u16LimitLow = 0xffff;
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316 | pDesc->Gen.u4LimitHigh = 0xf;
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317 | pDesc->Gen.u16BaseLow = 0;
|
---|
318 | pDesc->Gen.u8BaseHigh1 = 0;
|
---|
319 | pDesc->Gen.u8BaseHigh2 = 0;
|
---|
320 | pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
|
---|
321 | pDesc->Gen.u1DescType = 1; /* not system, but code/data */
|
---|
322 | pDesc->Gen.u2Dpl = 0; /* supervisor */
|
---|
323 | pDesc->Gen.u1Present = 1;
|
---|
324 | pDesc->Gen.u1Available = 0;
|
---|
325 | pDesc->Gen.u1Long = 0;
|
---|
326 | pDesc->Gen.u1DefBig = 1; /* big */
|
---|
327 | pDesc->Gen.u1Granularity = 1; /* 4KB limit */
|
---|
328 |
|
---|
329 | /* 64-bit mode code (& data?) */
|
---|
330 | pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
|
---|
331 | pDesc->Gen.u16LimitLow = 0xffff;
|
---|
332 | pDesc->Gen.u4LimitHigh = 0xf;
|
---|
333 | pDesc->Gen.u16BaseLow = 0;
|
---|
334 | pDesc->Gen.u8BaseHigh1 = 0;
|
---|
335 | pDesc->Gen.u8BaseHigh2 = 0;
|
---|
336 | pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
|
---|
337 | pDesc->Gen.u1DescType = 1; /* not system, but code/data */
|
---|
338 | pDesc->Gen.u2Dpl = 0; /* supervisor */
|
---|
339 | pDesc->Gen.u1Present = 1;
|
---|
340 | pDesc->Gen.u1Available = 0;
|
---|
341 | pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
|
---|
342 | pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
|
---|
343 | pDesc->Gen.u1Granularity = 1; /* 4KB limit */
|
---|
344 |
|
---|
345 | /*
|
---|
346 | * TSS descriptor
|
---|
347 | */
|
---|
348 | pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
|
---|
349 | RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
|
---|
350 | pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
|
---|
351 | pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
|
---|
352 | pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
|
---|
353 | pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
|
---|
354 | pDesc->Gen.u4LimitHigh = 0;
|
---|
355 | pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
|
---|
356 | pDesc->Gen.u1DescType = 0; /* system */
|
---|
357 | pDesc->Gen.u2Dpl = 0; /* supervisor */
|
---|
358 | pDesc->Gen.u1Present = 1;
|
---|
359 | pDesc->Gen.u1Available = 0;
|
---|
360 | pDesc->Gen.u1Long = 0;
|
---|
361 | pDesc->Gen.u1DefBig = 0;
|
---|
362 | pDesc->Gen.u1Granularity = 0; /* byte limit */
|
---|
363 |
|
---|
364 | /*
|
---|
365 | * TSS descriptor for trap 08
|
---|
366 | */
|
---|
367 | pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
|
---|
368 | pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
|
---|
369 | pDesc->Gen.u4LimitHigh = 0;
|
---|
370 | RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
|
---|
371 | pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
|
---|
372 | pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
|
---|
373 | pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
|
---|
374 | pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
|
---|
375 | pDesc->Gen.u1DescType = 0; /* system */
|
---|
376 | pDesc->Gen.u2Dpl = 0; /* supervisor */
|
---|
377 | pDesc->Gen.u1Present = 1;
|
---|
378 | pDesc->Gen.u1Available = 0;
|
---|
379 | pDesc->Gen.u1Long = 0;
|
---|
380 | pDesc->Gen.u1DefBig = 0;
|
---|
381 | pDesc->Gen.u1Granularity = 0; /* byte limit */
|
---|
382 | }
|
---|
383 |
|
---|
384 | /**
|
---|
385 | * Applies relocations to data and code managed by this
|
---|
386 | * component. This function will be called at init and
|
---|
387 | * whenever the VMM need to relocate it self inside the GC.
|
---|
388 | *
|
---|
389 | * @param pVM The VM.
|
---|
390 | */
|
---|
391 | VMMR3DECL(void) SELMR3Relocate(PVM pVM)
|
---|
392 | {
|
---|
393 | PX86DESC paGdt = pVM->selm.s.paGdtR3;
|
---|
394 | LogFlow(("SELMR3Relocate\n"));
|
---|
395 |
|
---|
396 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
397 | {
|
---|
398 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
399 |
|
---|
400 | /*
|
---|
401 | * Update GDTR and selector.
|
---|
402 | */
|
---|
403 | CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
|
---|
404 |
|
---|
405 | /** @todo selector relocations should be a seperate operation? */
|
---|
406 | CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
|
---|
407 | CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
|
---|
408 | CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
|
---|
409 | CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
|
---|
410 | CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
|
---|
411 | }
|
---|
412 |
|
---|
413 | selmR3SetupHyperGDTSelectors(pVM);
|
---|
414 |
|
---|
415 | /** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
|
---|
416 | /** @todo PGM knows the proper CR3 values these days, not CPUM. */
|
---|
417 | /*
|
---|
418 | * Update the TSSes.
|
---|
419 | */
|
---|
420 | /* Only applies to raw mode which supports only 1 VCPU */
|
---|
421 | PVMCPU pVCpu = &pVM->aCpus[0];
|
---|
422 |
|
---|
423 | /* Current TSS */
|
---|
424 | pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
|
---|
425 | pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
|
---|
426 | pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
|
---|
427 | pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
|
---|
428 | pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
|
---|
429 | pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
|
---|
430 | pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
|
---|
431 |
|
---|
432 | /* trap 08 */
|
---|
433 | pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
|
---|
434 | pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
|
---|
435 | pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
|
---|
436 | pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
|
---|
437 | pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
|
---|
438 | pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
|
---|
439 | pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
|
---|
440 | pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
|
---|
441 | pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
|
---|
442 | pVM->selm.s.TssTrap08.fs = 0;
|
---|
443 | pVM->selm.s.TssTrap08.gs = 0;
|
---|
444 | pVM->selm.s.TssTrap08.selLdt = 0;
|
---|
445 | pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
|
---|
446 | pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
|
---|
447 | pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
|
---|
448 | pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
|
---|
449 | pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
|
---|
450 | pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
|
---|
451 | pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
|
---|
452 | pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
|
---|
453 | /* TRPM will be updating the eip */
|
---|
454 |
|
---|
455 | if (!pVM->selm.s.fDisableMonitoring)
|
---|
456 | {
|
---|
457 | /*
|
---|
458 | * Update shadow GDT/LDT/TSS write access handlers.
|
---|
459 | */
|
---|
460 | int rc;
|
---|
461 | #ifdef SELM_TRACK_SHADOW_GDT_CHANGES
|
---|
462 | if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
|
---|
463 | {
|
---|
464 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
|
---|
465 | AssertRC(rc);
|
---|
466 | }
|
---|
467 | pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
|
---|
468 | rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
|
---|
469 | pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
|
---|
470 | 0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
|
---|
471 | AssertRC(rc);
|
---|
472 | #endif
|
---|
473 | #ifdef SELM_TRACK_SHADOW_TSS_CHANGES
|
---|
474 | if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
|
---|
475 | {
|
---|
476 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
|
---|
477 | AssertRC(rc);
|
---|
478 | }
|
---|
479 | pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
|
---|
480 | rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
|
---|
481 | pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
|
---|
482 | 0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
|
---|
483 | AssertRC(rc);
|
---|
484 | #endif
|
---|
485 |
|
---|
486 | /*
|
---|
487 | * Update the GC LDT region handler and address.
|
---|
488 | */
|
---|
489 | #ifdef SELM_TRACK_SHADOW_LDT_CHANGES
|
---|
490 | if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
|
---|
491 | {
|
---|
492 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
|
---|
493 | AssertRC(rc);
|
---|
494 | }
|
---|
495 | #endif
|
---|
496 | pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
|
---|
497 | #ifdef SELM_TRACK_SHADOW_LDT_CHANGES
|
---|
498 | rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
|
---|
499 | pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
|
---|
500 | 0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
|
---|
501 | AssertRC(rc);
|
---|
502 | #endif
|
---|
503 | }
|
---|
504 | }
|
---|
505 |
|
---|
506 |
|
---|
507 | /**
|
---|
508 | * Terminates the SELM.
|
---|
509 | *
|
---|
510 | * Termination means cleaning up and freeing all resources,
|
---|
511 | * the VM it self is at this point powered off or suspended.
|
---|
512 | *
|
---|
513 | * @returns VBox status code.
|
---|
514 | * @param pVM The VM to operate on.
|
---|
515 | */
|
---|
516 | VMMR3DECL(int) SELMR3Term(PVM pVM)
|
---|
517 | {
|
---|
518 | return 0;
|
---|
519 | }
|
---|
520 |
|
---|
521 |
|
---|
522 | /**
|
---|
523 | * The VM is being reset.
|
---|
524 | *
|
---|
525 | * For the SELM component this means that any GDT/LDT/TSS monitors
|
---|
526 | * needs to be removed.
|
---|
527 | *
|
---|
528 | * @param pVM VM handle.
|
---|
529 | */
|
---|
530 | VMMR3DECL(void) SELMR3Reset(PVM pVM)
|
---|
531 | {
|
---|
532 | LogFlow(("SELMR3Reset:\n"));
|
---|
533 | VM_ASSERT_EMT(pVM);
|
---|
534 |
|
---|
535 | /*
|
---|
536 | * Uninstall guest GDT/LDT/TSS write access handlers.
|
---|
537 | */
|
---|
538 | int rc;
|
---|
539 | #ifdef SELM_TRACK_GUEST_GDT_CHANGES
|
---|
540 | if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
|
---|
541 | {
|
---|
542 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
|
---|
543 | AssertRC(rc);
|
---|
544 | pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
|
---|
545 | pVM->selm.s.GuestGdtr.cbGdt = 0;
|
---|
546 | }
|
---|
547 | pVM->selm.s.fGDTRangeRegistered = false;
|
---|
548 | #endif
|
---|
549 | #ifdef SELM_TRACK_GUEST_LDT_CHANGES
|
---|
550 | if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
|
---|
551 | {
|
---|
552 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
|
---|
553 | AssertRC(rc);
|
---|
554 | pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
|
---|
555 | }
|
---|
556 | #endif
|
---|
557 | #ifdef SELM_TRACK_GUEST_TSS_CHANGES
|
---|
558 | if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
|
---|
559 | {
|
---|
560 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
|
---|
561 | AssertRC(rc);
|
---|
562 | pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
|
---|
563 | pVM->selm.s.GCSelTss = RTSEL_MAX;
|
---|
564 | }
|
---|
565 | #endif
|
---|
566 |
|
---|
567 | /*
|
---|
568 | * Re-initialize other members.
|
---|
569 | */
|
---|
570 | pVM->selm.s.cbLdtLimit = 0;
|
---|
571 | pVM->selm.s.offLdtHyper = 0;
|
---|
572 | pVM->selm.s.cbMonitoredGuestTss = 0;
|
---|
573 |
|
---|
574 | pVM->selm.s.fSyncTSSRing0Stack = false;
|
---|
575 |
|
---|
576 | /*
|
---|
577 | * Default action when entering raw mode for the first time
|
---|
578 | */
|
---|
579 | PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
|
---|
580 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
|
---|
581 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
|
---|
582 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
|
---|
583 | }
|
---|
584 |
|
---|
585 | /**
|
---|
586 | * Disable GDT/LDT/TSS monitoring and syncing
|
---|
587 | *
|
---|
588 | * @param pVM The VM to operate on.
|
---|
589 | */
|
---|
590 | VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
|
---|
591 | {
|
---|
592 | /*
|
---|
593 | * Uninstall guest GDT/LDT/TSS write access handlers.
|
---|
594 | */
|
---|
595 | int rc;
|
---|
596 | #ifdef SELM_TRACK_GUEST_GDT_CHANGES
|
---|
597 | if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
|
---|
598 | {
|
---|
599 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
|
---|
600 | AssertRC(rc);
|
---|
601 | pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
|
---|
602 | pVM->selm.s.GuestGdtr.cbGdt = 0;
|
---|
603 | }
|
---|
604 | pVM->selm.s.fGDTRangeRegistered = false;
|
---|
605 | #endif
|
---|
606 | #ifdef SELM_TRACK_GUEST_LDT_CHANGES
|
---|
607 | if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
|
---|
608 | {
|
---|
609 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
|
---|
610 | AssertRC(rc);
|
---|
611 | pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
|
---|
612 | }
|
---|
613 | #endif
|
---|
614 | #ifdef SELM_TRACK_GUEST_TSS_CHANGES
|
---|
615 | if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
|
---|
616 | {
|
---|
617 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
|
---|
618 | AssertRC(rc);
|
---|
619 | pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
|
---|
620 | pVM->selm.s.GCSelTss = RTSEL_MAX;
|
---|
621 | }
|
---|
622 | #endif
|
---|
623 |
|
---|
624 | /*
|
---|
625 | * Unregister shadow GDT/LDT/TSS write access handlers.
|
---|
626 | */
|
---|
627 | #ifdef SELM_TRACK_SHADOW_GDT_CHANGES
|
---|
628 | if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
|
---|
629 | {
|
---|
630 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
|
---|
631 | AssertRC(rc);
|
---|
632 | pVM->selm.s.paGdtRC = NIL_RTRCPTR;
|
---|
633 | }
|
---|
634 | #endif
|
---|
635 | #ifdef SELM_TRACK_SHADOW_TSS_CHANGES
|
---|
636 | if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
|
---|
637 | {
|
---|
638 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
|
---|
639 | AssertRC(rc);
|
---|
640 | pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
|
---|
641 | }
|
---|
642 | #endif
|
---|
643 | #ifdef SELM_TRACK_SHADOW_LDT_CHANGES
|
---|
644 | if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
|
---|
645 | {
|
---|
646 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
|
---|
647 | AssertRC(rc);
|
---|
648 | pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
|
---|
649 | }
|
---|
650 | #endif
|
---|
651 |
|
---|
652 | PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
|
---|
653 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
|
---|
654 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
|
---|
655 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
|
---|
656 |
|
---|
657 | pVM->selm.s.fDisableMonitoring = true;
|
---|
658 | }
|
---|
659 |
|
---|
660 |
|
---|
661 | /**
|
---|
662 | * Execute state save operation.
|
---|
663 | *
|
---|
664 | * @returns VBox status code.
|
---|
665 | * @param pVM VM Handle.
|
---|
666 | * @param pSSM SSM operation handle.
|
---|
667 | */
|
---|
668 | static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
|
---|
669 | {
|
---|
670 | LogFlow(("selmR3Save:\n"));
|
---|
671 |
|
---|
672 | /*
|
---|
673 | * Save the basic bits - fortunately all the other things can be resynced on load.
|
---|
674 | */
|
---|
675 | PSELM pSelm = &pVM->selm.s;
|
---|
676 |
|
---|
677 | SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
|
---|
678 | SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
|
---|
679 | SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
|
---|
680 | SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
|
---|
681 | SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
|
---|
682 | SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
|
---|
683 | SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
|
---|
684 | return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
|
---|
685 | }
|
---|
686 |
|
---|
687 |
|
---|
688 | /**
|
---|
689 | * Execute state load operation.
|
---|
690 | *
|
---|
691 | * @returns VBox status code.
|
---|
692 | * @param pVM VM Handle.
|
---|
693 | * @param pSSM SSM operation handle.
|
---|
694 | * @param uVersion Data layout version.
|
---|
695 | * @param uPass The data pass.
|
---|
696 | */
|
---|
697 | static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
698 | {
|
---|
699 | LogFlow(("selmR3Load:\n"));
|
---|
700 | Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
|
---|
701 |
|
---|
702 | /*
|
---|
703 | * Validate version.
|
---|
704 | */
|
---|
705 | if (uVersion != SELM_SAVED_STATE_VERSION)
|
---|
706 | {
|
---|
707 | AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
|
---|
708 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
709 | }
|
---|
710 |
|
---|
711 | /*
|
---|
712 | * Do a reset.
|
---|
713 | */
|
---|
714 | SELMR3Reset(pVM);
|
---|
715 |
|
---|
716 | /* Get the monitoring flag. */
|
---|
717 | SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
|
---|
718 |
|
---|
719 | /* Get the TSS state flag. */
|
---|
720 | SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
|
---|
721 |
|
---|
722 | /*
|
---|
723 | * Get the selectors.
|
---|
724 | */
|
---|
725 | RTSEL SelCS;
|
---|
726 | SSMR3GetSel(pSSM, &SelCS);
|
---|
727 | RTSEL SelDS;
|
---|
728 | SSMR3GetSel(pSSM, &SelDS);
|
---|
729 | RTSEL SelCS64;
|
---|
730 | SSMR3GetSel(pSSM, &SelCS64);
|
---|
731 | RTSEL SelDS64;
|
---|
732 | SSMR3GetSel(pSSM, &SelDS64);
|
---|
733 | RTSEL SelTSS;
|
---|
734 | SSMR3GetSel(pSSM, &SelTSS);
|
---|
735 | RTSEL SelTSSTrap08;
|
---|
736 | SSMR3GetSel(pSSM, &SelTSSTrap08);
|
---|
737 |
|
---|
738 | /* Copy the selectors; they will be checked during relocation. */
|
---|
739 | PSELM pSelm = &pVM->selm.s;
|
---|
740 | pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
|
---|
741 | pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
|
---|
742 | pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
|
---|
743 | pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
|
---|
744 | pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
|
---|
745 |
|
---|
746 | return VINF_SUCCESS;
|
---|
747 | }
|
---|
748 |
|
---|
749 |
|
---|
750 | /**
|
---|
751 | * Sync the GDT, LDT and TSS after loading the state.
|
---|
752 | *
|
---|
753 | * Just to play save, we set the FFs to force syncing before
|
---|
754 | * executing GC code.
|
---|
755 | *
|
---|
756 | * @returns VBox status code.
|
---|
757 | * @param pVM VM Handle.
|
---|
758 | * @param pSSM SSM operation handle.
|
---|
759 | */
|
---|
760 | static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
|
---|
761 | {
|
---|
762 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
763 |
|
---|
764 | LogFlow(("selmR3LoadDone:\n"));
|
---|
765 |
|
---|
766 | /*
|
---|
767 | * Don't do anything if it's a load failure.
|
---|
768 | */
|
---|
769 | int rc = SSMR3HandleGetStatus(pSSM);
|
---|
770 | if (RT_FAILURE(rc))
|
---|
771 | return VINF_SUCCESS;
|
---|
772 |
|
---|
773 | /*
|
---|
774 | * Do the syncing if we're in protected mode.
|
---|
775 | */
|
---|
776 | if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
|
---|
777 | {
|
---|
778 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
|
---|
779 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
|
---|
780 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
|
---|
781 | SELMR3UpdateFromCPUM(pVM, pVCpu);
|
---|
782 | }
|
---|
783 |
|
---|
784 | /*
|
---|
785 | * Flag everything for resync on next raw mode entry.
|
---|
786 | */
|
---|
787 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
|
---|
788 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
|
---|
789 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
|
---|
790 |
|
---|
791 | return VINF_SUCCESS;
|
---|
792 | }
|
---|
793 |
|
---|
794 |
|
---|
795 | /**
|
---|
796 | * Updates the Guest GDT & LDT virtualization based on current CPU state.
|
---|
797 | *
|
---|
798 | * @returns VBox status code.
|
---|
799 | * @param pVM The VM to operate on.
|
---|
800 | * @param pVCpu The VMCPU to operate on.
|
---|
801 | */
|
---|
802 | VMMR3DECL(int) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
|
---|
803 | {
|
---|
804 | int rc = VINF_SUCCESS;
|
---|
805 |
|
---|
806 | if (pVM->selm.s.fDisableMonitoring)
|
---|
807 | {
|
---|
808 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
|
---|
809 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
|
---|
810 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
|
---|
811 |
|
---|
812 | return VINF_SUCCESS;
|
---|
813 | }
|
---|
814 |
|
---|
815 | STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
|
---|
816 |
|
---|
817 | /*
|
---|
818 | * GDT sync
|
---|
819 | */
|
---|
820 | if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
|
---|
821 | {
|
---|
822 | /*
|
---|
823 | * Always assume the best
|
---|
824 | */
|
---|
825 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
|
---|
826 |
|
---|
827 | /* If the GDT was changed, then make sure the LDT is checked too */
|
---|
828 | /** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
|
---|
829 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
|
---|
830 | /* Same goes for the TSS selector */
|
---|
831 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
|
---|
832 |
|
---|
833 | /*
|
---|
834 | * Get the GDTR and check if there is anything to do (there usually is).
|
---|
835 | */
|
---|
836 | VBOXGDTR GDTR;
|
---|
837 | CPUMGetGuestGDTR(pVCpu, &GDTR);
|
---|
838 | if (GDTR.cbGdt < sizeof(X86DESC))
|
---|
839 | {
|
---|
840 | Log(("No GDT entries...\n"));
|
---|
841 | STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
|
---|
842 | return VINF_SUCCESS;
|
---|
843 | }
|
---|
844 |
|
---|
845 | /*
|
---|
846 | * Read the Guest GDT.
|
---|
847 | * ASSUMES that the entire GDT is in memory.
|
---|
848 | */
|
---|
849 | RTUINT cbEffLimit = GDTR.cbGdt;
|
---|
850 | PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
|
---|
851 | rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
|
---|
852 | if (RT_FAILURE(rc))
|
---|
853 | {
|
---|
854 | /*
|
---|
855 | * Read it page by page.
|
---|
856 | *
|
---|
857 | * Keep track of the last valid page and delay memsets and
|
---|
858 | * adjust cbEffLimit to reflect the effective size. The latter
|
---|
859 | * is something we do in the belief that the guest will probably
|
---|
860 | * never actually commit the last page, thus allowing us to keep
|
---|
861 | * our selectors in the high end of the GDT.
|
---|
862 | */
|
---|
863 | RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
|
---|
864 | RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
|
---|
865 | uint8_t *pu8Dst = (uint8_t *)&pVM->selm.s.paGdtR3[1];
|
---|
866 | uint8_t *pu8DstInvalid = pu8Dst;
|
---|
867 |
|
---|
868 | while (cbLeft)
|
---|
869 | {
|
---|
870 | RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
|
---|
871 | cb = RT_MIN(cb, cbLeft);
|
---|
872 | rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
|
---|
873 | if (RT_SUCCESS(rc))
|
---|
874 | {
|
---|
875 | if (pu8DstInvalid != pu8Dst)
|
---|
876 | memset(pu8DstInvalid, 0, pu8Dst - pu8DstInvalid);
|
---|
877 | GCPtrSrc += cb;
|
---|
878 | pu8Dst += cb;
|
---|
879 | pu8DstInvalid = pu8Dst;
|
---|
880 | }
|
---|
881 | else if ( rc == VERR_PAGE_NOT_PRESENT
|
---|
882 | || rc == VERR_PAGE_TABLE_NOT_PRESENT)
|
---|
883 | {
|
---|
884 | GCPtrSrc += cb;
|
---|
885 | pu8Dst += cb;
|
---|
886 | }
|
---|
887 | else
|
---|
888 | {
|
---|
889 | AssertReleaseMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
|
---|
890 | STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
|
---|
891 | return VERR_NOT_IMPLEMENTED;
|
---|
892 | }
|
---|
893 | cbLeft -= cb;
|
---|
894 | }
|
---|
895 |
|
---|
896 | /* any invalid pages at the end? */
|
---|
897 | if (pu8DstInvalid != pu8Dst)
|
---|
898 | {
|
---|
899 | cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
|
---|
900 | /* If any GDTEs was invalidated, zero them. */
|
---|
901 | if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
|
---|
902 | memset(pu8DstInvalid + cbEffLimit + 1, 0, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
|
---|
903 | }
|
---|
904 |
|
---|
905 | /* keep track of the effective limit. */
|
---|
906 | if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
|
---|
907 | {
|
---|
908 | Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
|
---|
909 | pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
|
---|
910 | pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
|
---|
911 | }
|
---|
912 | }
|
---|
913 |
|
---|
914 | /*
|
---|
915 | * Check if the Guest GDT intrudes on our GDT entries.
|
---|
916 | */
|
---|
917 | /** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
|
---|
918 | RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
|
---|
919 | if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
|
---|
920 | {
|
---|
921 | PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
|
---|
922 | PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
|
---|
923 | int iGDT = 0;
|
---|
924 |
|
---|
925 | Log(("Internal SELM GDT conflict: use non-present entries\n"));
|
---|
926 | STAM_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
|
---|
927 | while (pGDTECur > pGDTEStart)
|
---|
928 | {
|
---|
929 | /* We can reuse non-present entries */
|
---|
930 | if (!pGDTECur->Gen.u1Present)
|
---|
931 | {
|
---|
932 | aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
|
---|
933 | aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
|
---|
934 | Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
|
---|
935 | iGDT++;
|
---|
936 | if (iGDT >= SELM_HYPER_SEL_MAX)
|
---|
937 | break;
|
---|
938 | }
|
---|
939 |
|
---|
940 | pGDTECur--;
|
---|
941 | }
|
---|
942 | if (iGDT != SELM_HYPER_SEL_MAX)
|
---|
943 | {
|
---|
944 | AssertReleaseMsgFailed(("Internal SELM GDT conflict.\n"));
|
---|
945 | STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
|
---|
946 | return VERR_NOT_IMPLEMENTED;
|
---|
947 | }
|
---|
948 | }
|
---|
949 | else
|
---|
950 | {
|
---|
951 | aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
|
---|
952 | aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
|
---|
953 | aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
|
---|
954 | aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
|
---|
955 | aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
|
---|
956 | }
|
---|
957 |
|
---|
958 | /*
|
---|
959 | * Work thru the copied GDT entries adjusting them for correct virtualization.
|
---|
960 | */
|
---|
961 | PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
|
---|
962 | while (pGDTE < pGDTEEnd)
|
---|
963 | {
|
---|
964 | if (pGDTE->Gen.u1Present)
|
---|
965 | {
|
---|
966 | /*
|
---|
967 | * Code and data selectors are generally 1:1, with the
|
---|
968 | * 'little' adjustment we do for DPL 0 selectors.
|
---|
969 | */
|
---|
970 | if (pGDTE->Gen.u1DescType)
|
---|
971 | {
|
---|
972 | /*
|
---|
973 | * Hack for A-bit against Trap E on read-only GDT.
|
---|
974 | */
|
---|
975 | /** @todo Fix this by loading ds and cs before turning off WP. */
|
---|
976 | pGDTE->Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
|
---|
977 |
|
---|
978 | /*
|
---|
979 | * All DPL 0 code and data segments are squeezed into DPL 1.
|
---|
980 | *
|
---|
981 | * We're skipping conforming segments here because those
|
---|
982 | * cannot give us any trouble.
|
---|
983 | */
|
---|
984 | if ( pGDTE->Gen.u2Dpl == 0
|
---|
985 | && (pGDTE->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
|
---|
986 | != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
|
---|
987 | pGDTE->Gen.u2Dpl = 1;
|
---|
988 | }
|
---|
989 | else
|
---|
990 | {
|
---|
991 | /*
|
---|
992 | * System type selectors are marked not present.
|
---|
993 | * Recompiler or special handling is required for these.
|
---|
994 | */
|
---|
995 | /** @todo what about interrupt gates and rawr0? */
|
---|
996 | pGDTE->Gen.u1Present = 0;
|
---|
997 | }
|
---|
998 | }
|
---|
999 |
|
---|
1000 | /* Next GDT entry. */
|
---|
1001 | pGDTE++;
|
---|
1002 | }
|
---|
1003 |
|
---|
1004 | /*
|
---|
1005 | * Check if our hypervisor selectors were changed.
|
---|
1006 | */
|
---|
1007 | if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
|
---|
1008 | || aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
|
---|
1009 | || aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
|
---|
1010 | || aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
|
---|
1011 | || aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
|
---|
1012 | {
|
---|
1013 | /* Reinitialize our hypervisor GDTs */
|
---|
1014 | pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
|
---|
1015 | pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
|
---|
1016 | pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
|
---|
1017 | pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
|
---|
1018 | pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
|
---|
1019 |
|
---|
1020 | STAM_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
|
---|
1021 |
|
---|
1022 | /*
|
---|
1023 | * Do the relocation callbacks to let everyone update their hyper selector dependencies.
|
---|
1024 | * (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
|
---|
1025 | */
|
---|
1026 | VMR3Relocate(pVM, 0);
|
---|
1027 | }
|
---|
1028 | else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
|
---|
1029 | /* We overwrote all entries above, so we have to save them again. */
|
---|
1030 | selmR3SetupHyperGDTSelectors(pVM);
|
---|
1031 |
|
---|
1032 | /*
|
---|
1033 | * Adjust the cached GDT limit.
|
---|
1034 | * Any GDT entries which have been removed must be cleared.
|
---|
1035 | */
|
---|
1036 | if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
|
---|
1037 | {
|
---|
1038 | if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
|
---|
1039 | memset(pGDTE, 0, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
|
---|
1040 | #ifndef SELM_TRACK_GUEST_GDT_CHANGES
|
---|
1041 | pVM->selm.s.GuestGdtr.cbGdt = GDTR.cbGdt;
|
---|
1042 | #endif
|
---|
1043 | }
|
---|
1044 |
|
---|
1045 | #ifdef SELM_TRACK_GUEST_GDT_CHANGES
|
---|
1046 | /*
|
---|
1047 | * Check if Guest's GDTR is changed.
|
---|
1048 | */
|
---|
1049 | if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
|
---|
1050 | || GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
|
---|
1051 | {
|
---|
1052 | Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
|
---|
1053 |
|
---|
1054 | /*
|
---|
1055 | * [Re]Register write virtual handler for guest's GDT.
|
---|
1056 | */
|
---|
1057 | if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
|
---|
1058 | {
|
---|
1059 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
|
---|
1060 | AssertRC(rc);
|
---|
1061 | }
|
---|
1062 |
|
---|
1063 | rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
|
---|
1064 | 0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0, "Guest GDT write access handler");
|
---|
1065 | if (RT_FAILURE(rc))
|
---|
1066 | return rc;
|
---|
1067 |
|
---|
1068 | /* Update saved Guest GDTR. */
|
---|
1069 | pVM->selm.s.GuestGdtr = GDTR;
|
---|
1070 | pVM->selm.s.fGDTRangeRegistered = true;
|
---|
1071 | }
|
---|
1072 | #endif
|
---|
1073 | }
|
---|
1074 |
|
---|
1075 | /*
|
---|
1076 | * TSS sync
|
---|
1077 | */
|
---|
1078 | if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
|
---|
1079 | {
|
---|
1080 | SELMR3SyncTSS(pVM, pVCpu);
|
---|
1081 | }
|
---|
1082 |
|
---|
1083 | /*
|
---|
1084 | * LDT sync
|
---|
1085 | */
|
---|
1086 | if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
|
---|
1087 | {
|
---|
1088 | /*
|
---|
1089 | * Always assume the best
|
---|
1090 | */
|
---|
1091 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
|
---|
1092 |
|
---|
1093 | /*
|
---|
1094 | * LDT handling is done similarly to the GDT handling with a shadow
|
---|
1095 | * array. However, since the LDT is expected to be swappable (at least
|
---|
1096 | * some ancient OSes makes it swappable) it must be floating and
|
---|
1097 | * synced on a per-page basis.
|
---|
1098 | *
|
---|
1099 | * Eventually we will change this to be fully on demand. Meaning that
|
---|
1100 | * we will only sync pages containing LDT selectors actually used and
|
---|
1101 | * let the #PF handler lazily sync pages as they are used.
|
---|
1102 | * (This applies to GDT too, when we start making OS/2 fast.)
|
---|
1103 | */
|
---|
1104 |
|
---|
1105 | /*
|
---|
1106 | * First, determin the current LDT selector.
|
---|
1107 | */
|
---|
1108 | RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
|
---|
1109 | if ((SelLdt & X86_SEL_MASK) == 0)
|
---|
1110 | {
|
---|
1111 | /* ldtr = 0 - update hyper LDTR and deregister any active handler. */
|
---|
1112 | CPUMSetHyperLDTR(pVCpu, 0);
|
---|
1113 | #ifdef SELM_TRACK_GUEST_LDT_CHANGES
|
---|
1114 | if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
|
---|
1115 | {
|
---|
1116 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
|
---|
1117 | AssertRC(rc);
|
---|
1118 | pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
|
---|
1119 | }
|
---|
1120 | #endif
|
---|
1121 | STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
|
---|
1122 | return VINF_SUCCESS;
|
---|
1123 | }
|
---|
1124 |
|
---|
1125 | /*
|
---|
1126 | * Get the LDT selector.
|
---|
1127 | */
|
---|
1128 | PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
|
---|
1129 | RTGCPTR GCPtrLdt = X86DESC_BASE(*pDesc);
|
---|
1130 | unsigned cbLdt = X86DESC_LIMIT(*pDesc);
|
---|
1131 | if (pDesc->Gen.u1Granularity)
|
---|
1132 | cbLdt = (cbLdt << PAGE_SHIFT) | PAGE_OFFSET_MASK;
|
---|
1133 |
|
---|
1134 | /*
|
---|
1135 | * Validate it.
|
---|
1136 | */
|
---|
1137 | if ( !cbLdt
|
---|
1138 | || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
|
---|
1139 | || pDesc->Gen.u1DescType
|
---|
1140 | || pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
|
---|
1141 | {
|
---|
1142 | AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
|
---|
1143 |
|
---|
1144 | /* cbLdt > 0:
|
---|
1145 | * This is quite impossible, so we do as most people do when faced with
|
---|
1146 | * the impossible, we simply ignore it.
|
---|
1147 | */
|
---|
1148 | CPUMSetHyperLDTR(pVCpu, 0);
|
---|
1149 | #ifdef SELM_TRACK_GUEST_LDT_CHANGES
|
---|
1150 | if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
|
---|
1151 | {
|
---|
1152 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
|
---|
1153 | AssertRC(rc);
|
---|
1154 | pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
|
---|
1155 | }
|
---|
1156 | #endif
|
---|
1157 | STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
|
---|
1158 | return VINF_SUCCESS;
|
---|
1159 | }
|
---|
1160 | /** @todo check what intel does about odd limits. */
|
---|
1161 | AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
|
---|
1162 |
|
---|
1163 | /*
|
---|
1164 | * Use the cached guest ldt address if the descriptor has already been modified (see below)
|
---|
1165 | * (this is necessary due to redundant LDT updates; see todo above at GDT sync)
|
---|
1166 | */
|
---|
1167 | if (MMHyperIsInsideArea(pVM, GCPtrLdt))
|
---|
1168 | GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
|
---|
1169 |
|
---|
1170 |
|
---|
1171 | #ifdef SELM_TRACK_GUEST_LDT_CHANGES
|
---|
1172 | /** @todo Handle only present LDT segments. */
|
---|
1173 | // if (pDesc->Gen.u1Present)
|
---|
1174 | {
|
---|
1175 | /*
|
---|
1176 | * Check if Guest's LDT address/limit is changed.
|
---|
1177 | */
|
---|
1178 | if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
|
---|
1179 | || cbLdt != pVM->selm.s.cbLdtLimit)
|
---|
1180 | {
|
---|
1181 | Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
|
---|
1182 | pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
|
---|
1183 |
|
---|
1184 | /*
|
---|
1185 | * [Re]Register write virtual handler for guest's GDT.
|
---|
1186 | * In the event of LDT overlapping something, don't install it just assume it's being updated.
|
---|
1187 | */
|
---|
1188 | if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
|
---|
1189 | {
|
---|
1190 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
|
---|
1191 | AssertRC(rc);
|
---|
1192 | }
|
---|
1193 | #ifdef DEBUG
|
---|
1194 | if (pDesc->Gen.u1Present)
|
---|
1195 | Log(("LDT selector marked not present!!\n"));
|
---|
1196 | #endif
|
---|
1197 | rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
|
---|
1198 | 0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
|
---|
1199 | if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
|
---|
1200 | {
|
---|
1201 | /** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
|
---|
1202 | pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
|
---|
1203 | Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
|
---|
1204 | GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
|
---|
1205 | }
|
---|
1206 | else if (RT_SUCCESS(rc))
|
---|
1207 | pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
|
---|
1208 | else
|
---|
1209 | {
|
---|
1210 | CPUMSetHyperLDTR(pVCpu, 0);
|
---|
1211 | STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
|
---|
1212 | return rc;
|
---|
1213 | }
|
---|
1214 |
|
---|
1215 | pVM->selm.s.cbLdtLimit = cbLdt;
|
---|
1216 | }
|
---|
1217 | }
|
---|
1218 | #else
|
---|
1219 | pVM->selm.s.cbLdtLimit = cbLdt;
|
---|
1220 | #endif
|
---|
1221 |
|
---|
1222 | /*
|
---|
1223 | * Calc Shadow LDT base.
|
---|
1224 | */
|
---|
1225 | unsigned off;
|
---|
1226 | pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
|
---|
1227 | RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
|
---|
1228 | PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
|
---|
1229 |
|
---|
1230 | /*
|
---|
1231 | * Enable the LDT selector in the shadow GDT.
|
---|
1232 | */
|
---|
1233 | pDesc->Gen.u1Present = 1;
|
---|
1234 | pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
|
---|
1235 | pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
|
---|
1236 | pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
|
---|
1237 | pDesc->Gen.u1Available = 0;
|
---|
1238 | pDesc->Gen.u1Long = 0;
|
---|
1239 | if (cbLdt > 0xffff)
|
---|
1240 | {
|
---|
1241 | cbLdt = 0xffff;
|
---|
1242 | pDesc->Gen.u4LimitHigh = 0;
|
---|
1243 | pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
|
---|
1244 | }
|
---|
1245 |
|
---|
1246 | /*
|
---|
1247 | * Set Hyper LDTR and notify TRPM.
|
---|
1248 | */
|
---|
1249 | CPUMSetHyperLDTR(pVCpu, SelLdt);
|
---|
1250 |
|
---|
1251 | /*
|
---|
1252 | * Loop synchronising the LDT page by page.
|
---|
1253 | */
|
---|
1254 | /** @todo investigate how intel handle various operations on half present cross page entries. */
|
---|
1255 | off = GCPtrLdt & (sizeof(X86DESC) - 1);
|
---|
1256 | AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
|
---|
1257 |
|
---|
1258 | /* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
|
---|
1259 | unsigned cbLeft = cbLdt + 1;
|
---|
1260 | PX86DESC pLDTE = pShadowLDT;
|
---|
1261 | while (cbLeft)
|
---|
1262 | {
|
---|
1263 | /*
|
---|
1264 | * Read a chunk.
|
---|
1265 | */
|
---|
1266 | unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
|
---|
1267 | if (cbChunk > cbLeft)
|
---|
1268 | cbChunk = cbLeft;
|
---|
1269 | rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
|
---|
1270 | if (RT_SUCCESS(rc))
|
---|
1271 | {
|
---|
1272 | /*
|
---|
1273 | * Mark page
|
---|
1274 | */
|
---|
1275 | rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D);
|
---|
1276 | AssertRC(rc);
|
---|
1277 |
|
---|
1278 | /*
|
---|
1279 | * Loop thru the available LDT entries.
|
---|
1280 | * Figure out where to start and end and the potential cross pageness of
|
---|
1281 | * things adds a little complexity. pLDTE is updated there and not in the
|
---|
1282 | * 'next' part of the loop. The pLDTEEnd is inclusive.
|
---|
1283 | */
|
---|
1284 | PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
|
---|
1285 | if (pLDTE + 1 < pShadowLDT)
|
---|
1286 | pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
|
---|
1287 | while (pLDTE <= pLDTEEnd)
|
---|
1288 | {
|
---|
1289 | if (pLDTE->Gen.u1Present)
|
---|
1290 | {
|
---|
1291 | /*
|
---|
1292 | * Code and data selectors are generally 1:1, with the
|
---|
1293 | * 'little' adjustment we do for DPL 0 selectors.
|
---|
1294 | */
|
---|
1295 | if (pLDTE->Gen.u1DescType)
|
---|
1296 | {
|
---|
1297 | /*
|
---|
1298 | * Hack for A-bit against Trap E on read-only GDT.
|
---|
1299 | */
|
---|
1300 | /** @todo Fix this by loading ds and cs before turning off WP. */
|
---|
1301 | if (!(pLDTE->Gen.u4Type & X86_SEL_TYPE_ACCESSED))
|
---|
1302 | pLDTE->Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
|
---|
1303 |
|
---|
1304 | /*
|
---|
1305 | * All DPL 0 code and data segments are squeezed into DPL 1.
|
---|
1306 | *
|
---|
1307 | * We're skipping conforming segments here because those
|
---|
1308 | * cannot give us any trouble.
|
---|
1309 | */
|
---|
1310 | if ( pLDTE->Gen.u2Dpl == 0
|
---|
1311 | && (pLDTE->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
|
---|
1312 | != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
|
---|
1313 | pLDTE->Gen.u2Dpl = 1;
|
---|
1314 | }
|
---|
1315 | else
|
---|
1316 | {
|
---|
1317 | /*
|
---|
1318 | * System type selectors are marked not present.
|
---|
1319 | * Recompiler or special handling is required for these.
|
---|
1320 | */
|
---|
1321 | /** @todo what about interrupt gates and rawr0? */
|
---|
1322 | pLDTE->Gen.u1Present = 0;
|
---|
1323 | }
|
---|
1324 | }
|
---|
1325 |
|
---|
1326 | /* Next LDT entry. */
|
---|
1327 | pLDTE++;
|
---|
1328 | }
|
---|
1329 | }
|
---|
1330 | else
|
---|
1331 | {
|
---|
1332 | AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
|
---|
1333 | rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
|
---|
1334 | AssertRC(rc);
|
---|
1335 | }
|
---|
1336 |
|
---|
1337 | /*
|
---|
1338 | * Advance to the next page.
|
---|
1339 | */
|
---|
1340 | cbLeft -= cbChunk;
|
---|
1341 | GCPtrShadowLDT += cbChunk;
|
---|
1342 | pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
|
---|
1343 | GCPtrLdt += cbChunk;
|
---|
1344 | }
|
---|
1345 | }
|
---|
1346 |
|
---|
1347 | STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
|
---|
1348 | return VINF_SUCCESS;
|
---|
1349 | }
|
---|
1350 |
|
---|
1351 |
|
---|
1352 | /**
|
---|
1353 | * \#PF Handler callback for virtual access handler ranges.
|
---|
1354 | *
|
---|
1355 | * Important to realize that a physical page in a range can have aliases, and
|
---|
1356 | * for ALL and WRITE handlers these will also trigger.
|
---|
1357 | *
|
---|
1358 | * @returns VINF_SUCCESS if the handler have carried out the operation.
|
---|
1359 | * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
|
---|
1360 | * @param pVM VM Handle.
|
---|
1361 | * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
|
---|
1362 | * @param pvPtr The HC mapping of that address.
|
---|
1363 | * @param pvBuf What the guest is reading/writing.
|
---|
1364 | * @param cbBuf How much it's reading/writing.
|
---|
1365 | * @param enmAccessType The access type.
|
---|
1366 | * @param pvUser User argument.
|
---|
1367 | */
|
---|
1368 | static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
|
---|
1369 | {
|
---|
1370 | Assert(enmAccessType == PGMACCESSTYPE_WRITE);
|
---|
1371 | Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
|
---|
1372 |
|
---|
1373 | VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_GDT);
|
---|
1374 | return VINF_PGM_HANDLER_DO_DEFAULT;
|
---|
1375 | }
|
---|
1376 |
|
---|
1377 |
|
---|
1378 | /**
|
---|
1379 | * \#PF Handler callback for virtual access handler ranges.
|
---|
1380 | *
|
---|
1381 | * Important to realize that a physical page in a range can have aliases, and
|
---|
1382 | * for ALL and WRITE handlers these will also trigger.
|
---|
1383 | *
|
---|
1384 | * @returns VINF_SUCCESS if the handler have carried out the operation.
|
---|
1385 | * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
|
---|
1386 | * @param pVM VM Handle.
|
---|
1387 | * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
|
---|
1388 | * @param pvPtr The HC mapping of that address.
|
---|
1389 | * @param pvBuf What the guest is reading/writing.
|
---|
1390 | * @param cbBuf How much it's reading/writing.
|
---|
1391 | * @param enmAccessType The access type.
|
---|
1392 | * @param pvUser User argument.
|
---|
1393 | */
|
---|
1394 | static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
|
---|
1395 | {
|
---|
1396 | Assert(enmAccessType == PGMACCESSTYPE_WRITE);
|
---|
1397 | Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
|
---|
1398 | VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_LDT);
|
---|
1399 | return VINF_PGM_HANDLER_DO_DEFAULT;
|
---|
1400 | }
|
---|
1401 |
|
---|
1402 |
|
---|
1403 | /**
|
---|
1404 | * \#PF Handler callback for virtual access handler ranges.
|
---|
1405 | *
|
---|
1406 | * Important to realize that a physical page in a range can have aliases, and
|
---|
1407 | * for ALL and WRITE handlers these will also trigger.
|
---|
1408 | *
|
---|
1409 | * @returns VINF_SUCCESS if the handler have carried out the operation.
|
---|
1410 | * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
|
---|
1411 | * @param pVM VM Handle.
|
---|
1412 | * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
|
---|
1413 | * @param pvPtr The HC mapping of that address.
|
---|
1414 | * @param pvBuf What the guest is reading/writing.
|
---|
1415 | * @param cbBuf How much it's reading/writing.
|
---|
1416 | * @param enmAccessType The access type.
|
---|
1417 | * @param pvUser User argument.
|
---|
1418 | */
|
---|
1419 | static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
|
---|
1420 | {
|
---|
1421 | Assert(enmAccessType == PGMACCESSTYPE_WRITE);
|
---|
1422 | Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
|
---|
1423 |
|
---|
1424 | /** @todo This can be optimized by checking for the ESP0 offset and tracking TR
|
---|
1425 | * reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
|
---|
1426 | * should probably also deregister the virtual handler if TR.base/size
|
---|
1427 | * changes while we're in REM. */
|
---|
1428 |
|
---|
1429 | VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_TSS);
|
---|
1430 |
|
---|
1431 | return VINF_PGM_HANDLER_DO_DEFAULT;
|
---|
1432 | }
|
---|
1433 |
|
---|
1434 |
|
---|
1435 | /**
|
---|
1436 | * Synchronize the shadowed fields in the TSS.
|
---|
1437 | *
|
---|
1438 | * At present we're shadowing the ring-0 stack selector & pointer, and the
|
---|
1439 | * interrupt redirection bitmap (if present). We take the lazy approach wrt to
|
---|
1440 | * REM and this function is called both if REM made any changes to the TSS or
|
---|
1441 | * loaded TR.
|
---|
1442 | *
|
---|
1443 | * @returns VBox status code.
|
---|
1444 | * @param pVM The VM to operate on.
|
---|
1445 | * @param pVCpu The VMCPU to operate on.
|
---|
1446 | */
|
---|
1447 | VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
|
---|
1448 | {
|
---|
1449 | int rc;
|
---|
1450 |
|
---|
1451 | if (pVM->selm.s.fDisableMonitoring)
|
---|
1452 | {
|
---|
1453 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
|
---|
1454 | return VINF_SUCCESS;
|
---|
1455 | }
|
---|
1456 |
|
---|
1457 | STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
|
---|
1458 | Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
|
---|
1459 |
|
---|
1460 | /*
|
---|
1461 | * Get TR and extract and store the basic info.
|
---|
1462 | *
|
---|
1463 | * Note! The TSS limit is not checked by the LTR code, so we
|
---|
1464 | * have to be a bit careful with it. We make sure cbTss
|
---|
1465 | * won't be zero if TR is valid and if it's NULL we'll
|
---|
1466 | * make sure cbTss is 0.
|
---|
1467 | */
|
---|
1468 | CPUMSELREGHID trHid;
|
---|
1469 | RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
|
---|
1470 | RTGCPTR GCPtrTss = trHid.u64Base;
|
---|
1471 | uint32_t cbTss = trHid.u32Limit;
|
---|
1472 | Assert( (SelTss & X86_SEL_MASK)
|
---|
1473 | || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
|
---|
1474 | || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
|
---|
1475 | if (SelTss & X86_SEL_MASK)
|
---|
1476 | {
|
---|
1477 | Assert(!(SelTss & X86_SEL_LDT));
|
---|
1478 | Assert(trHid.Attr.n.u1DescType == 0);
|
---|
1479 | Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
|
---|
1480 | || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
|
---|
1481 | if (!++cbTss)
|
---|
1482 | cbTss = UINT32_MAX;
|
---|
1483 | }
|
---|
1484 | else
|
---|
1485 | {
|
---|
1486 | Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
|
---|
1487 | || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
|
---|
1488 | cbTss = 0; /* the reset case. */
|
---|
1489 | }
|
---|
1490 | pVM->selm.s.cbGuestTss = cbTss;
|
---|
1491 | pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
|
---|
1492 | || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
|
---|
1493 |
|
---|
1494 | /*
|
---|
1495 | * Figure out the size of what need to monitor.
|
---|
1496 | */
|
---|
1497 | /* We're not interested in any 16-bit TSSes. */
|
---|
1498 | uint32_t cbMonitoredTss = cbTss;
|
---|
1499 | if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
|
---|
1500 | && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
|
---|
1501 | cbMonitoredTss = 0;
|
---|
1502 |
|
---|
1503 | pVM->selm.s.offGuestIoBitmap = 0;
|
---|
1504 | bool fNoRing1Stack = true;
|
---|
1505 | if (cbMonitoredTss)
|
---|
1506 | {
|
---|
1507 | /*
|
---|
1508 | * 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
|
---|
1509 | * If VME is enabled we also want to keep an eye on the interrupt
|
---|
1510 | * redirection bitmap.
|
---|
1511 | */
|
---|
1512 | VBOXTSS Tss;
|
---|
1513 | uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
|
---|
1514 | rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
|
---|
1515 | if ( !(cr4 & X86_CR4_VME)
|
---|
1516 | || ( RT_SUCCESS(rc)
|
---|
1517 | && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
|
---|
1518 | && Tss.offIoBitmap > cbTss) /* beyond the end */ /** @todo not sure how the partial case is handled; probably not allowed. */
|
---|
1519 | )
|
---|
1520 | /* No interrupt redirection bitmap, just ESP0 and SS0. */
|
---|
1521 | cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
|
---|
1522 | else if (RT_SUCCESS(rc))
|
---|
1523 | {
|
---|
1524 | /*
|
---|
1525 | * Everything up to and including the interrupt redirection bitmap. Unfortunately
|
---|
1526 | * this can be quite a large chunk. We use to skip it earlier and just hope it
|
---|
1527 | * was kind of static...
|
---|
1528 | *
|
---|
1529 | * Update the virtual interrupt redirection bitmap while we're here.
|
---|
1530 | * (It is located in the 32 bytes before TR:offIoBitmap.)
|
---|
1531 | */
|
---|
1532 | cbMonitoredTss = Tss.offIoBitmap;
|
---|
1533 | pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
|
---|
1534 |
|
---|
1535 | uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
|
---|
1536 | rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
|
---|
1537 | GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
|
---|
1538 | AssertRC(rc);
|
---|
1539 | /** @todo memset the bitmap on failure? */
|
---|
1540 | Log2(("Redirection bitmap:\n"));
|
---|
1541 | Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
|
---|
1542 | }
|
---|
1543 | else
|
---|
1544 | {
|
---|
1545 | cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
|
---|
1546 | pVM->selm.s.offGuestIoBitmap = 0;
|
---|
1547 | /** @todo memset the bitmap? */
|
---|
1548 | }
|
---|
1549 |
|
---|
1550 | /*
|
---|
1551 | * Update the ring 0 stack selector and base address.
|
---|
1552 | */
|
---|
1553 | if (RT_SUCCESS(rc))
|
---|
1554 | {
|
---|
1555 | #ifdef LOG_ENABLED
|
---|
1556 | if (LogIsEnabled())
|
---|
1557 | {
|
---|
1558 | uint32_t ssr0, espr0;
|
---|
1559 | SELMGetRing1Stack(pVM, &ssr0, &espr0);
|
---|
1560 | if ((ssr0 & ~1) != Tss.ss0 || espr0 != Tss.esp0)
|
---|
1561 | {
|
---|
1562 | RTGCPHYS GCPhys = NIL_RTGCPHYS;
|
---|
1563 | rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
|
---|
1564 | Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
|
---|
1565 | Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
|
---|
1566 | AssertMsg(ssr0 != Tss.ss0,
|
---|
1567 | ("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
|
---|
1568 | Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
|
---|
1569 | }
|
---|
1570 | Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
|
---|
1571 | }
|
---|
1572 | #endif /* LOG_ENABLED */
|
---|
1573 | AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
|
---|
1574 |
|
---|
1575 | /* Update our TSS structure for the guest's ring 1 stack */
|
---|
1576 | selmSetRing1Stack(pVM, Tss.ss0 | 1, Tss.esp0);
|
---|
1577 | pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
|
---|
1578 | }
|
---|
1579 | }
|
---|
1580 |
|
---|
1581 | /*
|
---|
1582 | * Flush the ring-1 stack and the direct syscall dispatching if we
|
---|
1583 | * cannot obtain SS0:ESP0.
|
---|
1584 | */
|
---|
1585 | if (fNoRing1Stack)
|
---|
1586 | {
|
---|
1587 | selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
|
---|
1588 | pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
|
---|
1589 |
|
---|
1590 | /** @todo handle these dependencies better! */
|
---|
1591 | TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
|
---|
1592 | TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
|
---|
1593 | }
|
---|
1594 |
|
---|
1595 | /*
|
---|
1596 | * Check for monitor changes and apply them.
|
---|
1597 | */
|
---|
1598 | if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
|
---|
1599 | || cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
|
---|
1600 | {
|
---|
1601 | Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
|
---|
1602 | GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
|
---|
1603 |
|
---|
1604 | /* Release the old range first. */
|
---|
1605 | if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
|
---|
1606 | {
|
---|
1607 | rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
|
---|
1608 | AssertRC(rc);
|
---|
1609 | }
|
---|
1610 |
|
---|
1611 | /* Register the write handler if TS != 0. */
|
---|
1612 | if (cbMonitoredTss != 0)
|
---|
1613 | {
|
---|
1614 | rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
|
---|
1615 | 0, selmR3GuestTSSWriteHandler,
|
---|
1616 | "selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
|
---|
1617 | if (RT_FAILURE(rc))
|
---|
1618 | {
|
---|
1619 | STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
|
---|
1620 | return rc;
|
---|
1621 | }
|
---|
1622 |
|
---|
1623 | /* Update saved Guest TSS info. */
|
---|
1624 | pVM->selm.s.GCPtrGuestTss = GCPtrTss;
|
---|
1625 | pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
|
---|
1626 | pVM->selm.s.GCSelTss = SelTss;
|
---|
1627 | }
|
---|
1628 | else
|
---|
1629 | {
|
---|
1630 | pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
|
---|
1631 | pVM->selm.s.cbMonitoredGuestTss = 0;
|
---|
1632 | pVM->selm.s.GCSelTss = 0;
|
---|
1633 | }
|
---|
1634 | }
|
---|
1635 |
|
---|
1636 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
|
---|
1637 |
|
---|
1638 | STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
|
---|
1639 | return VINF_SUCCESS;
|
---|
1640 | }
|
---|
1641 |
|
---|
1642 |
|
---|
1643 | /**
|
---|
1644 | * Compares the Guest GDT and LDT with the shadow tables.
|
---|
1645 | * This is a VBOX_STRICT only function.
|
---|
1646 | *
|
---|
1647 | * @returns VBox status code.
|
---|
1648 | * @param pVM The VM Handle.
|
---|
1649 | */
|
---|
1650 | VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
|
---|
1651 | {
|
---|
1652 | #ifdef VBOX_STRICT
|
---|
1653 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
1654 |
|
---|
1655 | /*
|
---|
1656 | * Get GDTR and check for conflict.
|
---|
1657 | */
|
---|
1658 | VBOXGDTR GDTR;
|
---|
1659 | CPUMGetGuestGDTR(pVCpu, &GDTR);
|
---|
1660 | if (GDTR.cbGdt == 0)
|
---|
1661 | return VINF_SUCCESS;
|
---|
1662 |
|
---|
1663 | if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
|
---|
1664 | Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
|
---|
1665 |
|
---|
1666 | if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
|
---|
1667 | Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
|
---|
1668 |
|
---|
1669 | /*
|
---|
1670 | * Loop thru the GDT checking each entry.
|
---|
1671 | */
|
---|
1672 | RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
|
---|
1673 | PX86DESC pGDTE = pVM->selm.s.paGdtR3;
|
---|
1674 | PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
|
---|
1675 | while (pGDTE < pGDTEEnd)
|
---|
1676 | {
|
---|
1677 | X86DESC GDTEGuest;
|
---|
1678 | int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
|
---|
1679 | if (RT_SUCCESS(rc))
|
---|
1680 | {
|
---|
1681 | if (pGDTE->Gen.u1DescType || pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
|
---|
1682 | {
|
---|
1683 | if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
|
---|
1684 | || pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
|
---|
1685 | || pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
|
---|
1686 | || pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
|
---|
1687 | || pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
|
---|
1688 | || pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
|
---|
1689 | || pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
|
---|
1690 | {
|
---|
1691 | unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
|
---|
1692 | SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
|
---|
1693 | SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
|
---|
1694 | }
|
---|
1695 | }
|
---|
1696 | }
|
---|
1697 |
|
---|
1698 | /* Advance to the next descriptor. */
|
---|
1699 | GCPtrGDTEGuest += sizeof(X86DESC);
|
---|
1700 | pGDTE++;
|
---|
1701 | }
|
---|
1702 |
|
---|
1703 |
|
---|
1704 | /*
|
---|
1705 | * LDT?
|
---|
1706 | */
|
---|
1707 | RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
|
---|
1708 | if ((SelLdt & X86_SEL_MASK) == 0)
|
---|
1709 | return VINF_SUCCESS;
|
---|
1710 | if (SelLdt > GDTR.cbGdt)
|
---|
1711 | {
|
---|
1712 | Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
|
---|
1713 | return VERR_INTERNAL_ERROR;
|
---|
1714 | }
|
---|
1715 | X86DESC LDTDesc;
|
---|
1716 | int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
|
---|
1717 | if (RT_FAILURE(rc))
|
---|
1718 | {
|
---|
1719 | Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
|
---|
1720 | return rc;
|
---|
1721 | }
|
---|
1722 | RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(LDTDesc);
|
---|
1723 | unsigned cbLdt = X86DESC_LIMIT(LDTDesc);
|
---|
1724 | if (LDTDesc.Gen.u1Granularity)
|
---|
1725 | cbLdt = (cbLdt << PAGE_SHIFT) | PAGE_OFFSET_MASK;
|
---|
1726 |
|
---|
1727 | /*
|
---|
1728 | * Validate it.
|
---|
1729 | */
|
---|
1730 | if (!cbLdt)
|
---|
1731 | return VINF_SUCCESS;
|
---|
1732 | /** @todo check what intel does about odd limits. */
|
---|
1733 | AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
|
---|
1734 | if ( LDTDesc.Gen.u1DescType
|
---|
1735 | || LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
|
---|
1736 | || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
|
---|
1737 | {
|
---|
1738 | Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
|
---|
1739 | return VERR_INTERNAL_ERROR;
|
---|
1740 | }
|
---|
1741 |
|
---|
1742 | /*
|
---|
1743 | * Loop thru the LDT checking each entry.
|
---|
1744 | */
|
---|
1745 | unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
|
---|
1746 | PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
|
---|
1747 | PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
|
---|
1748 | while (pLDTE < pLDTEEnd)
|
---|
1749 | {
|
---|
1750 | X86DESC LDTEGuest;
|
---|
1751 | rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
|
---|
1752 | if (RT_SUCCESS(rc))
|
---|
1753 | {
|
---|
1754 | if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
|
---|
1755 | || pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
|
---|
1756 | || pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
|
---|
1757 | || pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
|
---|
1758 | || pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
|
---|
1759 | || pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
|
---|
1760 | || pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
|
---|
1761 | {
|
---|
1762 | unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
|
---|
1763 | SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
|
---|
1764 | SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
|
---|
1765 | }
|
---|
1766 | }
|
---|
1767 |
|
---|
1768 | /* Advance to the next descriptor. */
|
---|
1769 | GCPtrLDTEGuest += sizeof(X86DESC);
|
---|
1770 | pLDTE++;
|
---|
1771 | }
|
---|
1772 |
|
---|
1773 | #else /* !VBOX_STRICT */
|
---|
1774 | NOREF(pVM);
|
---|
1775 | #endif /* !VBOX_STRICT */
|
---|
1776 |
|
---|
1777 | return VINF_SUCCESS;
|
---|
1778 | }
|
---|
1779 |
|
---|
1780 |
|
---|
1781 | /**
|
---|
1782 | * Validates the RawR0 TSS values against the one in the Guest TSS.
|
---|
1783 | *
|
---|
1784 | * @returns true if it matches.
|
---|
1785 | * @returns false and assertions on mismatch..
|
---|
1786 | * @param pVM VM Handle.
|
---|
1787 | */
|
---|
1788 | VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
|
---|
1789 | {
|
---|
1790 | #ifdef VBOX_STRICT
|
---|
1791 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
1792 |
|
---|
1793 | if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
|
---|
1794 | return true;
|
---|
1795 |
|
---|
1796 | /*
|
---|
1797 | * Get TR and extract the basic info.
|
---|
1798 | */
|
---|
1799 | CPUMSELREGHID trHid;
|
---|
1800 | RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
|
---|
1801 | RTGCPTR GCPtrTss = trHid.u64Base;
|
---|
1802 | uint32_t cbTss = trHid.u32Limit;
|
---|
1803 | Assert( (SelTss & X86_SEL_MASK)
|
---|
1804 | || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
|
---|
1805 | || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
|
---|
1806 | if (SelTss & X86_SEL_MASK)
|
---|
1807 | {
|
---|
1808 | AssertReturn(!(SelTss & X86_SEL_LDT), false);
|
---|
1809 | AssertReturn(trHid.Attr.n.u1DescType == 0, false);
|
---|
1810 | AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
|
---|
1811 | || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
|
---|
1812 | false);
|
---|
1813 | if (!++cbTss)
|
---|
1814 | cbTss = UINT32_MAX;
|
---|
1815 | }
|
---|
1816 | else
|
---|
1817 | {
|
---|
1818 | AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
|
---|
1819 | || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */),
|
---|
1820 | false);
|
---|
1821 | cbTss = 0; /* the reset case. */
|
---|
1822 | }
|
---|
1823 | AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
|
---|
1824 | AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
|
---|
1825 | || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
|
---|
1826 | ("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
|
---|
1827 | false);
|
---|
1828 | AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
|
---|
1829 | || (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
|
---|
1830 | ("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
|
---|
1831 | false);
|
---|
1832 | AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
|
---|
1833 | || (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
|
---|
1834 | ("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
|
---|
1835 | false);
|
---|
1836 |
|
---|
1837 |
|
---|
1838 | /*
|
---|
1839 | * Figure out the size of what need to monitor.
|
---|
1840 | */
|
---|
1841 | bool fNoRing1Stack = true;
|
---|
1842 | /* We're not interested in any 16-bit TSSes. */
|
---|
1843 | uint32_t cbMonitoredTss = cbTss;
|
---|
1844 | if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
|
---|
1845 | && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
|
---|
1846 | cbMonitoredTss = 0;
|
---|
1847 | if (cbMonitoredTss)
|
---|
1848 | {
|
---|
1849 | VBOXTSS Tss;
|
---|
1850 | uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
|
---|
1851 | int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
|
---|
1852 | AssertReturn( rc == VINF_SUCCESS
|
---|
1853 | /* Happends early in XP boot during page table switching. */
|
---|
1854 | || ( (rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT)
|
---|
1855 | && !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
|
---|
1856 | false);
|
---|
1857 | if ( !(cr4 & X86_CR4_VME)
|
---|
1858 | || ( RT_SUCCESS(rc)
|
---|
1859 | && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
|
---|
1860 | && Tss.offIoBitmap > cbTss)
|
---|
1861 | )
|
---|
1862 | cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
|
---|
1863 | else if (RT_SUCCESS(rc))
|
---|
1864 | {
|
---|
1865 | cbMonitoredTss = Tss.offIoBitmap;
|
---|
1866 | AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
|
---|
1867 | ("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
|
---|
1868 | false);
|
---|
1869 |
|
---|
1870 | /* check the bitmap */
|
---|
1871 | uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
|
---|
1872 | rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
|
---|
1873 | GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
|
---|
1874 | AssertRCReturn(rc, false);
|
---|
1875 | AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
|
---|
1876 | ("offIoBitmap=%#x cbTss=%#x\n"
|
---|
1877 | " Guest: %.32Rhxs\n"
|
---|
1878 | "Shadow: %.32Rhxs\n",
|
---|
1879 | Tss.offIoBitmap, cbTss,
|
---|
1880 | &Tss.IntRedirBitmap[0],
|
---|
1881 | &pVM->selm.s.Tss.IntRedirBitmap[0]),
|
---|
1882 | false);
|
---|
1883 | }
|
---|
1884 | else
|
---|
1885 | cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
|
---|
1886 |
|
---|
1887 | /*
|
---|
1888 | * Check SS0 and ESP0.
|
---|
1889 | */
|
---|
1890 | if ( !pVM->selm.s.fSyncTSSRing0Stack
|
---|
1891 | && RT_SUCCESS(rc))
|
---|
1892 | {
|
---|
1893 | if ( Tss.esp0 != pVM->selm.s.Tss.esp1
|
---|
1894 | || Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
|
---|
1895 | {
|
---|
1896 | RTGCPHYS GCPhys;
|
---|
1897 | rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
|
---|
1898 | AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
|
---|
1899 | (pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
|
---|
1900 | Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
|
---|
1901 | return false;
|
---|
1902 | }
|
---|
1903 | }
|
---|
1904 | AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
|
---|
1905 | }
|
---|
1906 | else
|
---|
1907 | {
|
---|
1908 | AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
|
---|
1909 | AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
|
---|
1910 | AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
|
---|
1911 | }
|
---|
1912 |
|
---|
1913 |
|
---|
1914 |
|
---|
1915 | return true;
|
---|
1916 |
|
---|
1917 | #else /* !VBOX_STRICT */
|
---|
1918 | NOREF(pVM);
|
---|
1919 | return true;
|
---|
1920 | #endif /* !VBOX_STRICT */
|
---|
1921 | }
|
---|
1922 |
|
---|
1923 |
|
---|
1924 | /**
|
---|
1925 | * Returns flat address and limit of LDT by LDT selector from guest GDTR.
|
---|
1926 | *
|
---|
1927 | * Fully validate selector.
|
---|
1928 | *
|
---|
1929 | * @returns VBox status.
|
---|
1930 | * @param pVM VM Handle.
|
---|
1931 | * @param SelLdt LDT selector.
|
---|
1932 | * @param ppvLdt Where to store the flat address of LDT.
|
---|
1933 | * @param pcbLimit Where to store LDT limit.
|
---|
1934 | */
|
---|
1935 | VMMDECL(int) SELMGetLDTFromSel(PVM pVM, RTSEL SelLdt, PRTGCPTR ppvLdt, unsigned *pcbLimit)
|
---|
1936 | {
|
---|
1937 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
1938 |
|
---|
1939 | /* Get guest GDTR. */
|
---|
1940 | VBOXGDTR GDTR;
|
---|
1941 | CPUMGetGuestGDTR(pVCpu, &GDTR);
|
---|
1942 |
|
---|
1943 | /* Check selector TI and GDT limit. */
|
---|
1944 | if ( (SelLdt & X86_SEL_LDT)
|
---|
1945 | || SelLdt > GDTR.cbGdt)
|
---|
1946 | return VERR_INVALID_SELECTOR;
|
---|
1947 |
|
---|
1948 | /* Read descriptor from GC. */
|
---|
1949 | X86DESC Desc;
|
---|
1950 | int rc = PGMPhysSimpleReadGCPtr(pVCpu, (void *)&Desc, (RTGCPTR)(GDTR.pGdt + (SelLdt & X86_SEL_MASK)), sizeof(Desc));
|
---|
1951 | if (RT_FAILURE(rc))
|
---|
1952 | {
|
---|
1953 | /* fatal */
|
---|
1954 | Log(("Can't read LDT descriptor for selector=%04X\n", SelLdt));
|
---|
1955 | return VERR_SELECTOR_NOT_PRESENT;
|
---|
1956 | }
|
---|
1957 |
|
---|
1958 | /* Check if LDT descriptor is not present. */
|
---|
1959 | if (Desc.Gen.u1Present == 0)
|
---|
1960 | return VERR_SELECTOR_NOT_PRESENT;
|
---|
1961 |
|
---|
1962 | /* Check LDT descriptor type. */
|
---|
1963 | if ( Desc.Gen.u1DescType == 1
|
---|
1964 | || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
|
---|
1965 | return VERR_INVALID_SELECTOR;
|
---|
1966 |
|
---|
1967 | /* LDT descriptor is ok. */
|
---|
1968 | if (ppvLdt)
|
---|
1969 | {
|
---|
1970 | *ppvLdt = (RTGCPTR)X86DESC_BASE(Desc);
|
---|
1971 | *pcbLimit = X86DESC_LIMIT(Desc);
|
---|
1972 | }
|
---|
1973 | return VINF_SUCCESS;
|
---|
1974 | }
|
---|
1975 |
|
---|
1976 |
|
---|
1977 | /**
|
---|
1978 | * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
|
---|
1979 | *
|
---|
1980 | * See SELMR3GetSelectorInfo for details.
|
---|
1981 | *
|
---|
1982 | * @returns VBox status code, see SELMR3GetSelectorInfo for details.
|
---|
1983 | *
|
---|
1984 | * @param pVM VM handle.
|
---|
1985 | * @param pVCpu VMCPU handle.
|
---|
1986 | * @param Sel The selector to get info about.
|
---|
1987 | * @param pSelInfo Where to store the information.
|
---|
1988 | */
|
---|
1989 | static int selmR3GetSelectorInfo64(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
|
---|
1990 | {
|
---|
1991 | /*
|
---|
1992 | * Read it from the guest descriptor table.
|
---|
1993 | */
|
---|
1994 | X86DESC64 Desc;
|
---|
1995 | VBOXGDTR Gdtr;
|
---|
1996 | RTGCPTR GCPtrDesc;
|
---|
1997 | CPUMGetGuestGDTR(pVCpu, &Gdtr);
|
---|
1998 | if (!(Sel & X86_SEL_LDT))
|
---|
1999 | {
|
---|
2000 | /* GDT */
|
---|
2001 | if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
|
---|
2002 | return VERR_INVALID_SELECTOR;
|
---|
2003 | GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
|
---|
2004 | }
|
---|
2005 | else
|
---|
2006 | {
|
---|
2007 | /*
|
---|
2008 | * LDT - must locate the LDT first.
|
---|
2009 | */
|
---|
2010 | RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
|
---|
2011 | if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */ /** @todo r=bird: No, I don't think so */
|
---|
2012 | || (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
|
---|
2013 | return VERR_INVALID_SELECTOR;
|
---|
2014 | GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
|
---|
2015 | int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
|
---|
2016 | if (RT_FAILURE(rc))
|
---|
2017 | return rc;
|
---|
2018 |
|
---|
2019 | /* validate the LDT descriptor. */
|
---|
2020 | if (Desc.Gen.u1Present == 0)
|
---|
2021 | return VERR_SELECTOR_NOT_PRESENT;
|
---|
2022 | if ( Desc.Gen.u1DescType == 1
|
---|
2023 | || Desc.Gen.u4Type != AMD64_SEL_TYPE_SYS_LDT)
|
---|
2024 | return VERR_INVALID_SELECTOR;
|
---|
2025 |
|
---|
2026 | uint32_t cbLimit = X86DESC_LIMIT(Desc);
|
---|
2027 | if (Desc.Gen.u1Granularity)
|
---|
2028 | cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
|
---|
2029 | if ((uint32_t)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
|
---|
2030 | return VERR_INVALID_SELECTOR;
|
---|
2031 |
|
---|
2032 | /* calc the descriptor location. */
|
---|
2033 | GCPtrDesc = X86DESC64_BASE(Desc);
|
---|
2034 | GCPtrDesc += (Sel & X86_SEL_MASK);
|
---|
2035 | }
|
---|
2036 |
|
---|
2037 | /* read the descriptor. */
|
---|
2038 | int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
|
---|
2039 | if (RT_FAILURE(rc))
|
---|
2040 | {
|
---|
2041 | rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
|
---|
2042 | if (RT_FAILURE(rc))
|
---|
2043 | return rc;
|
---|
2044 | Desc.au64[1] = 0;
|
---|
2045 | }
|
---|
2046 |
|
---|
2047 | /*
|
---|
2048 | * Extract the base and limit
|
---|
2049 | * (We ignore the present bit here, which is probably a bit silly...)
|
---|
2050 | */
|
---|
2051 | pSelInfo->Sel = Sel;
|
---|
2052 | pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
|
---|
2053 | pSelInfo->u.Raw64 = Desc;
|
---|
2054 | if (Desc.Gen.u1DescType)
|
---|
2055 | {
|
---|
2056 | /*
|
---|
2057 | * 64-bit code selectors are wide open, it's not possible to detect
|
---|
2058 | * 64-bit data or stack selectors without also dragging in assumptions
|
---|
2059 | * about current CS (i.e. that's we're executing in 64-bit mode). So,
|
---|
2060 | * the selinfo user needs to deal with this in the context the info is
|
---|
2061 | * used unfortunately.
|
---|
2062 | */
|
---|
2063 | if ( Desc.Gen.u1Long
|
---|
2064 | && !Desc.Gen.u1DefBig
|
---|
2065 | && (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
|
---|
2066 | {
|
---|
2067 | /* Note! We ignore the segment limit hacks that was added by AMD. */
|
---|
2068 | pSelInfo->GCPtrBase = 0;
|
---|
2069 | pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
|
---|
2070 | }
|
---|
2071 | else
|
---|
2072 | {
|
---|
2073 | pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
|
---|
2074 | if (Desc.Gen.u1Granularity)
|
---|
2075 | pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
|
---|
2076 | pSelInfo->GCPtrBase = X86DESC_BASE(Desc);
|
---|
2077 | }
|
---|
2078 | pSelInfo->SelGate = 0;
|
---|
2079 | }
|
---|
2080 | else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
|
---|
2081 | || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
|
---|
2082 | || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
|
---|
2083 | {
|
---|
2084 | /* Note. LDT descriptors are weird in long mode, we ignore the footnote
|
---|
2085 | in the AMD manual here as a simplification. */
|
---|
2086 | pSelInfo->GCPtrBase = X86DESC64_BASE(Desc);
|
---|
2087 | pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
|
---|
2088 | if (Desc.Gen.u1Granularity)
|
---|
2089 | pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
|
---|
2090 | pSelInfo->SelGate = 0;
|
---|
2091 | }
|
---|
2092 | else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
|
---|
2093 | || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
|
---|
2094 | || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
|
---|
2095 | {
|
---|
2096 | pSelInfo->cbLimit = X86DESC64_BASE(Desc);
|
---|
2097 | pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
|
---|
2098 | | ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
|
---|
2099 | | ((uint64_t)Desc.Gate.u32OffsetTop << 32);
|
---|
2100 | pSelInfo->SelGate = Desc.Gate.u16Sel;
|
---|
2101 | pSelInfo->fFlags |= DBGFSELINFO_FLAGS_GATE;
|
---|
2102 | }
|
---|
2103 | else
|
---|
2104 | {
|
---|
2105 | pSelInfo->cbLimit = 0;
|
---|
2106 | pSelInfo->GCPtrBase = 0;
|
---|
2107 | pSelInfo->SelGate = 0;
|
---|
2108 | pSelInfo->fFlags |= DBGFSELINFO_FLAGS_INVALID;
|
---|
2109 | }
|
---|
2110 | if (!Desc.Gen.u1Present)
|
---|
2111 | pSelInfo->fFlags |= DBGFSELINFO_FLAGS_NOT_PRESENT;
|
---|
2112 |
|
---|
2113 | return VINF_SUCCESS;
|
---|
2114 | }
|
---|
2115 |
|
---|
2116 |
|
---|
2117 | /**
|
---|
2118 | * Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
|
---|
2119 | * interprets a legacy descriptor table entry and fills in the selector info
|
---|
2120 | * structure from it.
|
---|
2121 | *
|
---|
2122 | * @param pSelInfo Where to store the selector info. Only the fFlags and
|
---|
2123 | * Sel members have been initialized.
|
---|
2124 | * @param pDesc The legacy descriptor to parse.
|
---|
2125 | */
|
---|
2126 | DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
|
---|
2127 | {
|
---|
2128 | pSelInfo->u.Raw64.au64[1] = 0;
|
---|
2129 | pSelInfo->u.Raw = *pDesc;
|
---|
2130 | if ( pDesc->Gen.u1DescType
|
---|
2131 | || !(pDesc->Gen.u4Type & 4))
|
---|
2132 | {
|
---|
2133 | pSelInfo->cbLimit = X86DESC_LIMIT(*pDesc);
|
---|
2134 | if (pDesc->Gen.u1Granularity)
|
---|
2135 | pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
|
---|
2136 | pSelInfo->GCPtrBase = X86DESC_BASE(*pDesc);
|
---|
2137 | pSelInfo->SelGate = 0;
|
---|
2138 | }
|
---|
2139 | else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
|
---|
2140 | {
|
---|
2141 | pSelInfo->cbLimit = 0;
|
---|
2142 | if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
|
---|
2143 | pSelInfo->GCPtrBase = 0;
|
---|
2144 | else
|
---|
2145 | pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
|
---|
2146 | | (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
|
---|
2147 | pSelInfo->SelGate = pDesc->Gate.u16Sel;
|
---|
2148 | pSelInfo->fFlags |= DBGFSELINFO_FLAGS_GATE;
|
---|
2149 | }
|
---|
2150 | else
|
---|
2151 | {
|
---|
2152 | pSelInfo->cbLimit = 0;
|
---|
2153 | pSelInfo->GCPtrBase = 0;
|
---|
2154 | pSelInfo->SelGate = 0;
|
---|
2155 | pSelInfo->fFlags |= DBGFSELINFO_FLAGS_INVALID;
|
---|
2156 | }
|
---|
2157 | if (!pDesc->Gen.u1Present)
|
---|
2158 | pSelInfo->fFlags |= DBGFSELINFO_FLAGS_NOT_PRESENT;
|
---|
2159 | }
|
---|
2160 |
|
---|
2161 |
|
---|
2162 | /**
|
---|
2163 | * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
|
---|
2164 | *
|
---|
2165 | * See SELMR3GetSelectorInfo for details.
|
---|
2166 | *
|
---|
2167 | * @returns VBox status code, see SELMR3GetSelectorInfo for details.
|
---|
2168 | *
|
---|
2169 | * @param pVM VM handle.
|
---|
2170 | * @param pVCpu VMCPU handle.
|
---|
2171 | * @param Sel The selector to get info about.
|
---|
2172 | * @param pSelInfo Where to store the information.
|
---|
2173 | */
|
---|
2174 | static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
|
---|
2175 | {
|
---|
2176 | /*
|
---|
2177 | * Read the descriptor entry
|
---|
2178 | */
|
---|
2179 | pSelInfo->fFlags = 0;
|
---|
2180 | X86DESC Desc;
|
---|
2181 | if ( !(Sel & X86_SEL_LDT)
|
---|
2182 | && ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
|
---|
2183 | || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
|
---|
2184 | || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
|
---|
2185 | || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
|
---|
2186 | || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK))
|
---|
2187 | )
|
---|
2188 | {
|
---|
2189 | /*
|
---|
2190 | * Hypervisor descriptor.
|
---|
2191 | */
|
---|
2192 | pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
|
---|
2193 | if (CPUMIsGuestInProtectedMode(pVCpu))
|
---|
2194 | pSelInfo->fFlags |= DBGFSELINFO_FLAGS_PROT_MODE;
|
---|
2195 | else
|
---|
2196 | pSelInfo->fFlags |= DBGFSELINFO_FLAGS_REAL_MODE;
|
---|
2197 |
|
---|
2198 | Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
|
---|
2199 | }
|
---|
2200 | else if (CPUMIsGuestInProtectedMode(pVCpu))
|
---|
2201 | {
|
---|
2202 | /*
|
---|
2203 | * Read it from the guest descriptor table.
|
---|
2204 | */
|
---|
2205 | pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
|
---|
2206 |
|
---|
2207 | VBOXGDTR Gdtr;
|
---|
2208 | RTGCPTR GCPtrDesc;
|
---|
2209 | CPUMGetGuestGDTR(pVCpu, &Gdtr);
|
---|
2210 | if (!(Sel & X86_SEL_LDT))
|
---|
2211 | {
|
---|
2212 | /* GDT */
|
---|
2213 | if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
|
---|
2214 | return VERR_INVALID_SELECTOR;
|
---|
2215 | GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
|
---|
2216 | }
|
---|
2217 | else
|
---|
2218 | {
|
---|
2219 | /*
|
---|
2220 | * LDT - must locate the LDT first...
|
---|
2221 | */
|
---|
2222 | RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
|
---|
2223 | if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */ /** @todo r=bird: No, I don't think so */
|
---|
2224 | || (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
|
---|
2225 | return VERR_INVALID_SELECTOR;
|
---|
2226 | GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
|
---|
2227 | int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
|
---|
2228 | if (RT_FAILURE(rc))
|
---|
2229 | return rc;
|
---|
2230 |
|
---|
2231 | /* validate the LDT descriptor. */
|
---|
2232 | if (Desc.Gen.u1Present == 0)
|
---|
2233 | return VERR_SELECTOR_NOT_PRESENT;
|
---|
2234 | if ( Desc.Gen.u1DescType == 1
|
---|
2235 | || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
|
---|
2236 | return VERR_INVALID_SELECTOR;
|
---|
2237 |
|
---|
2238 | unsigned cbLimit = X86DESC_LIMIT(Desc);
|
---|
2239 | if (Desc.Gen.u1Granularity)
|
---|
2240 | cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
|
---|
2241 | if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
|
---|
2242 | return VERR_INVALID_SELECTOR;
|
---|
2243 |
|
---|
2244 | /* calc the descriptor location. */
|
---|
2245 | GCPtrDesc = X86DESC_BASE(Desc);
|
---|
2246 | GCPtrDesc += (Sel & X86_SEL_MASK);
|
---|
2247 | }
|
---|
2248 |
|
---|
2249 | /* read the descriptor. */
|
---|
2250 | int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
|
---|
2251 | if (RT_FAILURE(rc))
|
---|
2252 | return rc;
|
---|
2253 | }
|
---|
2254 | else
|
---|
2255 | {
|
---|
2256 | /*
|
---|
2257 | * We're in real mode.
|
---|
2258 | */
|
---|
2259 | pSelInfo->Sel = Sel;
|
---|
2260 | pSelInfo->GCPtrBase = Sel << 4;
|
---|
2261 | pSelInfo->cbLimit = 0xffff;
|
---|
2262 | pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
|
---|
2263 | pSelInfo->u.Raw64.au64[0] = 0;
|
---|
2264 | pSelInfo->u.Raw64.au64[1] = 0;
|
---|
2265 | pSelInfo->SelGate = 0;
|
---|
2266 | return VINF_SUCCESS;
|
---|
2267 | }
|
---|
2268 |
|
---|
2269 | /*
|
---|
2270 | * Extract the base and limit or sel:offset for gates.
|
---|
2271 | */
|
---|
2272 | pSelInfo->Sel = Sel;
|
---|
2273 | selmR3SelInfoFromDesc32(pSelInfo, &Desc);
|
---|
2274 |
|
---|
2275 | return VINF_SUCCESS;
|
---|
2276 | }
|
---|
2277 |
|
---|
2278 |
|
---|
2279 | /**
|
---|
2280 | * Gets information about a selector.
|
---|
2281 | *
|
---|
2282 | * Intended for the debugger mostly and will prefer the guest descriptor tables
|
---|
2283 | * over the shadow ones.
|
---|
2284 | *
|
---|
2285 | * @retval VINF_SUCCESS on success.
|
---|
2286 | * @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
|
---|
2287 | * descriptor table.
|
---|
2288 | * @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
|
---|
2289 | * is not returned if the selector itself isn't present, you have to
|
---|
2290 | * check that for yourself (see DBGFSELINFO::fFlags).
|
---|
2291 | * @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
|
---|
2292 | * pagetable or page backing the selector table wasn't present.
|
---|
2293 | * @returns Other VBox status code on other errors.
|
---|
2294 | *
|
---|
2295 | * @param pVM VM handle.
|
---|
2296 | * @param pVCpu The virtual CPU handle.
|
---|
2297 | * @param Sel The selector to get info about.
|
---|
2298 | * @param pSelInfo Where to store the information.
|
---|
2299 | */
|
---|
2300 | VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
|
---|
2301 | {
|
---|
2302 | AssertPtr(pSelInfo);
|
---|
2303 | if (CPUMIsGuestInLongMode(pVCpu))
|
---|
2304 | return selmR3GetSelectorInfo64(pVM, pVCpu, Sel, pSelInfo);
|
---|
2305 | return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
|
---|
2306 | }
|
---|
2307 |
|
---|
2308 |
|
---|
2309 | /**
|
---|
2310 | * Gets information about a selector from the shadow tables.
|
---|
2311 | *
|
---|
2312 | * This is intended to be faster than the SELMR3GetSelectorInfo() method, but
|
---|
2313 | * requires that the caller ensures that the shadow tables are up to date.
|
---|
2314 | *
|
---|
2315 | * @retval VINF_SUCCESS on success.
|
---|
2316 | * @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
|
---|
2317 | * descriptor table.
|
---|
2318 | * @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
|
---|
2319 | * is not returned if the selector itself isn't present, you have to
|
---|
2320 | * check that for yourself (see DBGFSELINFO::fFlags).
|
---|
2321 | * @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
|
---|
2322 | * pagetable or page backing the selector table wasn't present.
|
---|
2323 | * @returns Other VBox status code on other errors.
|
---|
2324 | *
|
---|
2325 | * @param pVM VM handle.
|
---|
2326 | * @param Sel The selector to get info about.
|
---|
2327 | * @param pSelInfo Where to store the information.
|
---|
2328 | *
|
---|
2329 | * @remarks Don't use this when in hardware assisted virtualization mode.
|
---|
2330 | */
|
---|
2331 | VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
|
---|
2332 | {
|
---|
2333 | Assert(pSelInfo);
|
---|
2334 |
|
---|
2335 | /*
|
---|
2336 | * Read the descriptor entry
|
---|
2337 | */
|
---|
2338 | X86DESC Desc;
|
---|
2339 | if (!(Sel & X86_SEL_LDT))
|
---|
2340 | {
|
---|
2341 | /*
|
---|
2342 | * Global descriptor.
|
---|
2343 | */
|
---|
2344 | Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
|
---|
2345 | pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
|
---|
2346 | || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
|
---|
2347 | || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
|
---|
2348 | || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
|
---|
2349 | || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK)
|
---|
2350 | ? DBGFSELINFO_FLAGS_HYPER
|
---|
2351 | : 0;
|
---|
2352 | /** @todo check that the GDT offset is valid. */
|
---|
2353 | }
|
---|
2354 | else
|
---|
2355 | {
|
---|
2356 | /*
|
---|
2357 | * Local Descriptor.
|
---|
2358 | */
|
---|
2359 | PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
|
---|
2360 | Desc = paLDT[Sel >> X86_SEL_SHIFT];
|
---|
2361 | /** @todo check if the LDT page is actually available. */
|
---|
2362 | /** @todo check that the LDT offset is valid. */
|
---|
2363 | pSelInfo->fFlags = 0;
|
---|
2364 | }
|
---|
2365 | if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
|
---|
2366 | pSelInfo->fFlags |= DBGFSELINFO_FLAGS_PROT_MODE;
|
---|
2367 | else
|
---|
2368 | pSelInfo->fFlags |= DBGFSELINFO_FLAGS_REAL_MODE;
|
---|
2369 |
|
---|
2370 | /*
|
---|
2371 | * Extract the base and limit or sel:offset for gates.
|
---|
2372 | */
|
---|
2373 | pSelInfo->Sel = Sel;
|
---|
2374 | selmR3SelInfoFromDesc32(pSelInfo, &Desc);
|
---|
2375 |
|
---|
2376 | return VINF_SUCCESS;
|
---|
2377 | }
|
---|
2378 |
|
---|
2379 |
|
---|
2380 | /**
|
---|
2381 | * Formats a descriptor.
|
---|
2382 | *
|
---|
2383 | * @param Desc Descriptor to format.
|
---|
2384 | * @param Sel Selector number.
|
---|
2385 | * @param pszOutput Output buffer.
|
---|
2386 | * @param cchOutput Size of output buffer.
|
---|
2387 | */
|
---|
2388 | static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
|
---|
2389 | {
|
---|
2390 | /*
|
---|
2391 | * Make variable description string.
|
---|
2392 | */
|
---|
2393 | static struct
|
---|
2394 | {
|
---|
2395 | unsigned cch;
|
---|
2396 | const char *psz;
|
---|
2397 | } const aTypes[32] =
|
---|
2398 | {
|
---|
2399 | #define STRENTRY(str) { sizeof(str) - 1, str }
|
---|
2400 | /* system */
|
---|
2401 | STRENTRY("Reserved0 "), /* 0x00 */
|
---|
2402 | STRENTRY("TSS16Avail "), /* 0x01 */
|
---|
2403 | STRENTRY("LDT "), /* 0x02 */
|
---|
2404 | STRENTRY("TSS16Busy "), /* 0x03 */
|
---|
2405 | STRENTRY("Call16 "), /* 0x04 */
|
---|
2406 | STRENTRY("Task "), /* 0x05 */
|
---|
2407 | STRENTRY("Int16 "), /* 0x06 */
|
---|
2408 | STRENTRY("Trap16 "), /* 0x07 */
|
---|
2409 | STRENTRY("Reserved8 "), /* 0x08 */
|
---|
2410 | STRENTRY("TSS32Avail "), /* 0x09 */
|
---|
2411 | STRENTRY("ReservedA "), /* 0x0a */
|
---|
2412 | STRENTRY("TSS32Busy "), /* 0x0b */
|
---|
2413 | STRENTRY("Call32 "), /* 0x0c */
|
---|
2414 | STRENTRY("ReservedD "), /* 0x0d */
|
---|
2415 | STRENTRY("Int32 "), /* 0x0e */
|
---|
2416 | STRENTRY("Trap32 "), /* 0x0f */
|
---|
2417 | /* non system */
|
---|
2418 | STRENTRY("DataRO "), /* 0x10 */
|
---|
2419 | STRENTRY("DataRO Accessed "), /* 0x11 */
|
---|
2420 | STRENTRY("DataRW "), /* 0x12 */
|
---|
2421 | STRENTRY("DataRW Accessed "), /* 0x13 */
|
---|
2422 | STRENTRY("DataDownRO "), /* 0x14 */
|
---|
2423 | STRENTRY("DataDownRO Accessed "), /* 0x15 */
|
---|
2424 | STRENTRY("DataDownRW "), /* 0x16 */
|
---|
2425 | STRENTRY("DataDownRW Accessed "), /* 0x17 */
|
---|
2426 | STRENTRY("CodeEO "), /* 0x18 */
|
---|
2427 | STRENTRY("CodeEO Accessed "), /* 0x19 */
|
---|
2428 | STRENTRY("CodeER "), /* 0x1a */
|
---|
2429 | STRENTRY("CodeER Accessed "), /* 0x1b */
|
---|
2430 | STRENTRY("CodeConfEO "), /* 0x1c */
|
---|
2431 | STRENTRY("CodeConfEO Accessed "), /* 0x1d */
|
---|
2432 | STRENTRY("CodeConfER "), /* 0x1e */
|
---|
2433 | STRENTRY("CodeConfER Accessed ") /* 0x1f */
|
---|
2434 | #undef SYSENTRY
|
---|
2435 | };
|
---|
2436 | #define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
|
---|
2437 | char szMsg[128];
|
---|
2438 | char *psz = &szMsg[0];
|
---|
2439 | unsigned i = Desc.Gen.u1DescType << 4 | Desc.Gen.u4Type;
|
---|
2440 | memcpy(psz, aTypes[i].psz, aTypes[i].cch);
|
---|
2441 | psz += aTypes[i].cch;
|
---|
2442 |
|
---|
2443 | if (Desc.Gen.u1Present)
|
---|
2444 | ADD_STR(psz, "Present ");
|
---|
2445 | else
|
---|
2446 | ADD_STR(psz, "Not-Present ");
|
---|
2447 | if (Desc.Gen.u1Granularity)
|
---|
2448 | ADD_STR(psz, "Page ");
|
---|
2449 | if (Desc.Gen.u1DefBig)
|
---|
2450 | ADD_STR(psz, "32-bit ");
|
---|
2451 | else
|
---|
2452 | ADD_STR(psz, "16-bit ");
|
---|
2453 | #undef ADD_STR
|
---|
2454 | *psz = '\0';
|
---|
2455 |
|
---|
2456 | /*
|
---|
2457 | * Limit and Base and format the output.
|
---|
2458 | */
|
---|
2459 | uint32_t u32Limit = X86DESC_LIMIT(Desc);
|
---|
2460 | if (Desc.Gen.u1Granularity)
|
---|
2461 | u32Limit = u32Limit << PAGE_SHIFT | PAGE_OFFSET_MASK;
|
---|
2462 | uint32_t u32Base = X86DESC_BASE(Desc);
|
---|
2463 |
|
---|
2464 | RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
|
---|
2465 | Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
|
---|
2466 | }
|
---|
2467 |
|
---|
2468 |
|
---|
2469 | /**
|
---|
2470 | * Dumps a descriptor.
|
---|
2471 | *
|
---|
2472 | * @param Desc Descriptor to dump.
|
---|
2473 | * @param Sel Selector number.
|
---|
2474 | * @param pszMsg Message to prepend the log entry with.
|
---|
2475 | */
|
---|
2476 | VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
|
---|
2477 | {
|
---|
2478 | char szOutput[128];
|
---|
2479 | selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
|
---|
2480 | Log(("%s: %s\n", pszMsg, szOutput));
|
---|
2481 | NOREF(szOutput[0]);
|
---|
2482 | }
|
---|
2483 |
|
---|
2484 |
|
---|
2485 | /**
|
---|
2486 | * Display the shadow gdt.
|
---|
2487 | *
|
---|
2488 | * @param pVM VM Handle.
|
---|
2489 | * @param pHlp The info helpers.
|
---|
2490 | * @param pszArgs Arguments, ignored.
|
---|
2491 | */
|
---|
2492 | static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
2493 | {
|
---|
2494 | pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
|
---|
2495 | for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
|
---|
2496 | {
|
---|
2497 | if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
|
---|
2498 | {
|
---|
2499 | char szOutput[128];
|
---|
2500 | selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
|
---|
2501 | const char *psz = "";
|
---|
2502 | if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
|
---|
2503 | psz = " HyperCS";
|
---|
2504 | else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
|
---|
2505 | psz = " HyperDS";
|
---|
2506 | else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
|
---|
2507 | psz = " HyperCS64";
|
---|
2508 | else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
|
---|
2509 | psz = " HyperTSS";
|
---|
2510 | else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
|
---|
2511 | psz = " HyperTSSTrap08";
|
---|
2512 | pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
|
---|
2513 | }
|
---|
2514 | }
|
---|
2515 | }
|
---|
2516 |
|
---|
2517 |
|
---|
2518 | /**
|
---|
2519 | * Display the guest gdt.
|
---|
2520 | *
|
---|
2521 | * @param pVM VM Handle.
|
---|
2522 | * @param pHlp The info helpers.
|
---|
2523 | * @param pszArgs Arguments, ignored.
|
---|
2524 | */
|
---|
2525 | static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
2526 | {
|
---|
2527 | /** @todo SMP support! */
|
---|
2528 | PVMCPU pVCpu = &pVM->aCpus[0];
|
---|
2529 |
|
---|
2530 | VBOXGDTR GDTR;
|
---|
2531 | CPUMGetGuestGDTR(pVCpu, &GDTR);
|
---|
2532 | RTGCPTR GCPtrGDT = GDTR.pGdt;
|
---|
2533 | unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
|
---|
2534 |
|
---|
2535 | pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
|
---|
2536 | for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
|
---|
2537 | {
|
---|
2538 | X86DESC GDTE;
|
---|
2539 | int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
|
---|
2540 | if (RT_SUCCESS(rc))
|
---|
2541 | {
|
---|
2542 | if (GDTE.Gen.u1Present)
|
---|
2543 | {
|
---|
2544 | char szOutput[128];
|
---|
2545 | selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
|
---|
2546 | pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
|
---|
2547 | }
|
---|
2548 | }
|
---|
2549 | else if (rc == VERR_PAGE_NOT_PRESENT)
|
---|
2550 | {
|
---|
2551 | if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
|
---|
2552 | pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
|
---|
2553 | }
|
---|
2554 | else
|
---|
2555 | pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
|
---|
2556 | }
|
---|
2557 | }
|
---|
2558 |
|
---|
2559 |
|
---|
2560 | /**
|
---|
2561 | * Display the shadow ldt.
|
---|
2562 | *
|
---|
2563 | * @param pVM VM Handle.
|
---|
2564 | * @param pHlp The info helpers.
|
---|
2565 | * @param pszArgs Arguments, ignored.
|
---|
2566 | */
|
---|
2567 | static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
2568 | {
|
---|
2569 | unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
|
---|
2570 | PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
|
---|
2571 | pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
|
---|
2572 | for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
|
---|
2573 | {
|
---|
2574 | if (paLDT[iLDT].Gen.u1Present)
|
---|
2575 | {
|
---|
2576 | char szOutput[128];
|
---|
2577 | selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
|
---|
2578 | pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
|
---|
2579 | }
|
---|
2580 | }
|
---|
2581 | }
|
---|
2582 |
|
---|
2583 |
|
---|
2584 | /**
|
---|
2585 | * Display the guest ldt.
|
---|
2586 | *
|
---|
2587 | * @param pVM VM Handle.
|
---|
2588 | * @param pHlp The info helpers.
|
---|
2589 | * @param pszArgs Arguments, ignored.
|
---|
2590 | */
|
---|
2591 | static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
2592 | {
|
---|
2593 | /** @todo SMP support! */
|
---|
2594 | PVMCPU pVCpu = &pVM->aCpus[0];
|
---|
2595 |
|
---|
2596 | RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
|
---|
2597 | if (!(SelLdt & X86_SEL_MASK))
|
---|
2598 | {
|
---|
2599 | pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
|
---|
2600 | return;
|
---|
2601 | }
|
---|
2602 |
|
---|
2603 | RTGCPTR GCPtrLdt;
|
---|
2604 | unsigned cbLdt;
|
---|
2605 | int rc = SELMGetLDTFromSel(pVM, SelLdt, &GCPtrLdt, &cbLdt);
|
---|
2606 | if (RT_FAILURE(rc))
|
---|
2607 | {
|
---|
2608 | pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): rc=%Rrc\n", SelLdt, rc);
|
---|
2609 | return;
|
---|
2610 | }
|
---|
2611 |
|
---|
2612 | pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RGv limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
|
---|
2613 | unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
|
---|
2614 | for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
|
---|
2615 | {
|
---|
2616 | X86DESC LdtE;
|
---|
2617 | rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
|
---|
2618 | if (RT_SUCCESS(rc))
|
---|
2619 | {
|
---|
2620 | if (LdtE.Gen.u1Present)
|
---|
2621 | {
|
---|
2622 | char szOutput[128];
|
---|
2623 | selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
|
---|
2624 | pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
|
---|
2625 | }
|
---|
2626 | }
|
---|
2627 | else if (rc == VERR_PAGE_NOT_PRESENT)
|
---|
2628 | {
|
---|
2629 | if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
|
---|
2630 | pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, GCPtrLdt);
|
---|
2631 | }
|
---|
2632 | else
|
---|
2633 | pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, rc, GCPtrLdt);
|
---|
2634 | }
|
---|
2635 | }
|
---|
2636 |
|
---|
2637 |
|
---|
2638 | /**
|
---|
2639 | * Dumps the hypervisor GDT
|
---|
2640 | *
|
---|
2641 | * @param pVM VM handle.
|
---|
2642 | */
|
---|
2643 | VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
|
---|
2644 | {
|
---|
2645 | DBGFR3Info(pVM, "gdt", NULL, NULL);
|
---|
2646 | }
|
---|
2647 |
|
---|
2648 |
|
---|
2649 | /**
|
---|
2650 | * Dumps the hypervisor LDT
|
---|
2651 | *
|
---|
2652 | * @param pVM VM handle.
|
---|
2653 | */
|
---|
2654 | VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
|
---|
2655 | {
|
---|
2656 | DBGFR3Info(pVM, "ldt", NULL, NULL);
|
---|
2657 | }
|
---|
2658 |
|
---|
2659 |
|
---|
2660 | /**
|
---|
2661 | * Dumps the guest GDT
|
---|
2662 | *
|
---|
2663 | * @param pVM VM handle.
|
---|
2664 | */
|
---|
2665 | VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
|
---|
2666 | {
|
---|
2667 | DBGFR3Info(pVM, "gdtguest", NULL, NULL);
|
---|
2668 | }
|
---|
2669 |
|
---|
2670 |
|
---|
2671 | /**
|
---|
2672 | * Dumps the guest LDT
|
---|
2673 | *
|
---|
2674 | * @param pVM VM handle.
|
---|
2675 | */
|
---|
2676 | VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
|
---|
2677 | {
|
---|
2678 | DBGFR3Info(pVM, "ldtguest", NULL, NULL);
|
---|
2679 | }
|
---|
2680 |
|
---|