TRPM.cpp@ 31816

Last change on this file since 31816 was 30493, checked in by vboxsync, 14 years ago
Demoted some PGM apis to internal only.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 75.9 KB

Line
1	/* $Id: TRPM.cpp 30493 2010-06-29 11:59:47Z vboxsync $ */
2	/** @file
3	* TRPM - The Trap Monitor.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_trpm TRPM - The Trap Monitor
19	*
20	* The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21	* the VMM. It plays a major role in raw-mode execution and a lesser one in the
22	* hardware assisted mode.
23	*
24	* Note first, the following will use trap as a collective term for faults,
25	* aborts and traps.
26	*
27	* @see grp_trpm
28	*
29	*
30	* @section sec_trpm_rc Raw-Mode Context
31	*
32	* When executing in the raw-mode context, TRPM will be managing the IDT and
33	* processing all traps and interrupts. It will also monitor the guest IDT
34	* because CSAM wishes to know about changes to it (trap/interrupt/syscall
35	* handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36	* considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37	*
38	* External interrupts will be forwarded to the host context by the quickest
39	* possible route where they will be reasserted. The other events will be
40	* categorized into virtualization traps, genuine guest traps and hypervisor
41	* traps. The latter group may be recoverable depending on when they happen and
42	* whether there is a handler for it, otherwise it will cause a guru meditation.
43	*
44	* TRPM disgishishes the between the first two (virt and guest traps) and the
45	* latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46	* it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47	* dispatcher tables, one ad-hoc for one time traps registered via
48	* TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49	* The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50	*
51	* The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52	* part), will call up the other VMM sub-systems depending on what it things
53	* happens. The two most busy traps are page faults (\#PF) and general
54	* protection fault/trap (\#GP).
55	*
56	* Before resuming guest code after having taken a virtualization trap or
57	* injected a guest trap, TRPM will check for pending forced action and
58	* every now and again let TM check for timed out timers. This allows code that
59	* is being executed as part of virtualization traps to signal ring-3 exits,
60	* page table resyncs and similar without necessarily using the status code. It
61	* also make sure we're more responsive to timers and requests from other
62	* threads (necessarily running on some different core/cpu in most cases).
63	*
64	*
65	* @section sec_trpm_all All Contexts
66	*
67	* TRPM will also dispatch / inject interrupts and traps to the guest, both when
68	* in raw-mode and when in hardware assisted mode. See TRPMInject().
69	*
70	*/
71
72	/*******************************************************************************
73	* Header Files *
74	*******************************************************************************/
75	#define LOG_GROUP LOG_GROUP_TRPM
76	#include <VBox/trpm.h>
77	#include <VBox/cpum.h>
78	#include <VBox/selm.h>
79	#include <VBox/ssm.h>
80	#include <VBox/pdmapi.h>
81	#include <VBox/pgm.h>
82	#include <include/internal/pgm.h>
83	#include <VBox/dbgf.h>
84	#include <VBox/mm.h>
85	#include <VBox/stam.h>
86	#include <VBox/csam.h>
87	#include <VBox/patm.h>
88	#include "TRPMInternal.h"
89	#include <VBox/vm.h>
90	#include <VBox/em.h>
91	#include <VBox/rem.h>
92	#include <VBox/hwaccm.h>
93
94	#include <VBox/err.h>
95	#include <VBox/param.h>
96	#include <VBox/log.h>
97	#include <iprt/assert.h>
98	#include <iprt/asm.h>
99	#include <iprt/string.h>
100	#include <iprt/alloc.h>
101
102
103	/*******************************************************************************
104	* Structures and Typedefs *
105	*******************************************************************************/
106	/**
107	* Trap handler function.
108	* @todo need to specialize this as we go along.
109	*/
110	typedef enum TRPMHANDLER
111	{
112	/** Generic Interrupt handler. */
113	TRPM_HANDLER_INT = 0,
114	/** Generic Trap handler. */
115	TRPM_HANDLER_TRAP,
116	/** Trap 8 (\#DF) handler. */
117	TRPM_HANDLER_TRAP_08,
118	/** Trap 12 (\#MC) handler. */
119	TRPM_HANDLER_TRAP_12,
120	/** Max. */
121	TRPM_HANDLER_MAX
122	} TRPMHANDLER, *PTRPMHANDLER;
123
124
125	/*******************************************************************************
126	* Global Variables *
127	*******************************************************************************/
128	/** Preinitialized IDT.
129	* The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
130	* will use to pick the right address. The u16SegSel is always VMM CS.
131	*/
132	static VBOXIDTE_GENERIC g_aIdt[256] =
133	{
134	/* special trap handler - still, this is an interrupt gate not a trap gate... */
135	#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
136	/* generic trap handler. */
137	#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
138	/* special interrupt handler. */
139	#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
140	/* generic interrupt handler. */
141	#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
142	/* special task gate IDT entry (for critical exceptions like #DF). */
143	#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
144	/* draft, fixme later when the handler is written. */
145	#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
146
147	/* N - M M - T - C - D i */
148	/* o - n o - y - o - e p */
149	/* - e n - p - d - s t */
150	/* - i - e - e - c . */
151	/* - c - - - r */
152	/* ============================================================= */
153	IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
154	IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
155	#ifdef VBOX_WITH_NMI
156	IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
157	#else
158	IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
159	#endif
160	IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
161	IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
162	IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
163	IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
164	IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
165	IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
166	IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
167	IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
168	IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
169	IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
170	IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
171	IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
172	IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
173	IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
174	IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
175	IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
176	IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
177	IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
178	IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
179	IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
180	IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
181	IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
182	IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
183	IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
184	IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
185	IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
186	IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
187	IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
188	IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
189	IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
190	IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
191	IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
192	IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
193	IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
194	IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
195	IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
196	IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
197	IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
198	IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
199	IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
200	IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
201	IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
202	IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
203	IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
204	IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
205	IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
206	IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
207	IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
208	IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
209	IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
210	IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
211	IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
212	IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
213	IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
214	IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
215	IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
216	IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
217	IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
218	IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
219	IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
220	IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
221	IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
222	IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
223	IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
224	IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
225	IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
226	IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
227	IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
228	IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
229	IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
230	IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
231	IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
232	IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
233	IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
234	IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
235	IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
236	IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
237	IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
238	IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
239	IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
240	IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
241	IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
242	IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
243	IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
244	IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
245	IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
246	IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
247	IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
248	IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
249	IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
250	IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
251	IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
252	IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
253	IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
254	IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
255	IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
256	IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
257	IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
258	IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
259	IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
260	IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
261	IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
262	IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
263	IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
264	IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
265	IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
266	IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
267	IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
268	IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
269	IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
270	IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
271	IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
272	IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
273	IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
274	IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
275	IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
276	IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
277	IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
278	IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
279	IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
280	IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
281	IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
282	IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
283	IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
284	IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
285	IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
286	IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
287	IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
288	IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
289	IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
290	IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
291	IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
292	IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
293	IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
294	IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
295	IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
296	IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
297	IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
298	IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
299	IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
300	IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
301	IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
302	IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
303	IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
304	IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
305	IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
306	IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
307	IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
308	IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
309	IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
310	IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
311	IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
312	IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
313	IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
314	IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
315	IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
316	IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
317	IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
318	IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
319	IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
320	IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
321	IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
322	IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
323	IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
324	IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
325	IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
326	IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
327	IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
328	IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
329	IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
330	IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
331	IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
332	IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
333	IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
334	IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
335	IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
336	IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
337	IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
338	IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
339	IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
340	IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
341	IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
342	IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
343	IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
344	IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
345	IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
346	IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
347	IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
348	IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
349	IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
350	IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
351	IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
352	IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
353	IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
354	IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
355	IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
356	IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
357	IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
358	IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
359	IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
360	IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
361	IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
362	IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
363	IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
364	IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
365	IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
366	IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
367	IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
368	IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
369	IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
370	IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
371	IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
372	IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
373	IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
374	IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
375	IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
376	IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
377	IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
378	IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
379	IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
380	IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
381	IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
382	IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
383	IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
384	IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
385	IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
386	IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
387	IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
388	IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
389	IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
390	IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
391	IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
392	IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
393	IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
394	IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
395	IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
396	IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
397	IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
398	IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
399	IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
400	IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
401	IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
402	IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
403	IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
404	IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
405	IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
406	IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
407	IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
408	IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
409	IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
410	IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
411	IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
412	IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
413	#undef IDTE_TRAP
414	#undef IDTE_TRAP_GEN
415	#undef IDTE_INT
416	#undef IDTE_INT_GEN
417	#undef IDTE_TASK
418	#undef IDTE_UNUSED
419	#undef IDTE_RESERVED
420	};
421
422
423	/** Enable or disable tracking of Guest's IDT. */
424	#define TRPM_TRACK_GUEST_IDT_CHANGES
425
426	/** Enable or disable tracking of Shadow IDT. */
427	#define TRPM_TRACK_SHADOW_IDT_CHANGES
428
429	/** TRPM saved state version. */
430	#define TRPM_SAVED_STATE_VERSION 9
431	#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
432
433
434	/*******************************************************************************
435	* Internal Functions *
436	*******************************************************************************/
437	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
438	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
439	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
440
441
442	/**
443	* Initializes the Trap Manager
444	*
445	* @returns VBox status code.
446	* @param pVM The VM to operate on.
447	*/
448	VMMR3DECL(int) TRPMR3Init(PVM pVM)
449	{
450	LogFlow(("TRPMR3Init\n"));
451
452	/*
453	* Assert sizes and alignments.
454	*/
455	AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
456	AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
457	AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
458	AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
459
460	/*
461	* Initialize members.
462	*/
463	pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
464	pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
465
466	for (VMCPUID i = 0; i < pVM->cCpus; i++)
467	{
468	PVMCPU pVCpu = &pVM->aCpus[i];
469
470	pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
471	pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
472	pVCpu->trpm.s.uActiveVector = ~0;
473	}
474
475	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
476	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
477	pVM->trpm.s.fDisableMonitoring = false;
478	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
479
480	/*
481	* Read the configuration (if any).
482	*/
483	PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
484	if (pTRPMNode)
485	{
486	bool f;
487	int rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
488	if (RT_SUCCESS(rc))
489	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
490	}
491
492	/* write config summary to log */
493	if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
494	LogRel(("TRPM: Dropping Guest IDT Monitoring.\n"));
495
496	/*
497	* Initialize the IDT.
498	* The handler addresses will be set in the TRPMR3Relocate() function.
499	*/
500	Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
501	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
502
503	/*
504	* Register the saved state data unit.
505	*/
506	int rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
507	NULL, NULL, NULL,
508	NULL, trpmR3Save, NULL,
509	NULL, trpmR3Load, NULL);
510	if (RT_FAILURE(rc))
511	return rc;
512
513	/*
514	* Statistics.
515	*/
516	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
517	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
518	STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
519
520	/* traps */
521	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
522	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
523	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
524	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
525	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
526	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
527	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
528	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
529	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
530	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
531	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
532	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segemnt not present.");
533	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
534	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
535	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
536	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
537	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
538	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
539	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
540	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
541
542	#ifdef VBOX_WITH_STATISTICS
543	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 255, 8, MM_TAG_STAM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
544	AssertRCReturn(rc, rc);
545	pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
546	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
547	for (unsigned i = 0; i < 255; i++)
548	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
549	i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
550	#endif
551
552	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
553	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
554	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
555	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
556	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
557	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
558
559	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
560	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
561
562	/*
563	* Default action when entering raw mode for the first time
564	*/
565	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
566	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
567	return 0;
568	}
569
570
571	/**
572	* Applies relocations to data and code managed by this component.
573	*
574	* This function will be called at init and whenever the VMM need
575	* to relocate itself inside the GC.
576	*
577	* @param pVM The VM handle.
578	* @param offDelta Relocation delta relative to old location.
579	*/
580	VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
581	{
582	/* Only applies to raw mode which supports only 1 VCPU. */
583	PVMCPU pVCpu = &pVM->aCpus[0];
584
585	LogFlow(("TRPMR3Relocate\n"));
586	/*
587	* Get the trap handler addresses.
588	*
589	* If VMMGC.gc is screwed, so are we. We'll assert here since it elsewise
590	* would make init order impossible if we should assert the presence of these
591	* exports in TRPMR3Init().
592	*/
593	RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
594	RT_ZERO(aRCPtrs);
595	int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
596	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
597
598	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
599	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMGC.gc!\n"));
600
601	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
602	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMGC.gc!\n"));
603
604	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
605	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMGC.gc!\n"));
606
607	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
608
609	/*
610	* Iterate the idt and set the addresses.
611	*/
612	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
613	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
614	for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
615	{
616	if ( pIdte->Gen.u1Present
617	&& !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
618	)
619	{
620	Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
621	RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
622	switch (pIdteTemplate->u16OffsetLow)
623	{
624	/*
625	* Generic handlers have different entrypoints for each possible
626	* vector number. These entrypoints makes a sort of an array with
627	* 8 byte entries where the vector number is the index.
628	* See TRPMGCHandlersA.asm for details.
629	*/
630	case TRPM_HANDLER_INT:
631	case TRPM_HANDLER_TRAP:
632	Offset += i * 8;
633	break;
634	case TRPM_HANDLER_TRAP_12:
635	break;
636	case TRPM_HANDLER_TRAP_08:
637	/* Handle #DF Task Gate in special way. */
638	pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
639	pIdte->Gen.u16OffsetLow = 0;
640	pIdte->Gen.u16OffsetHigh = 0;
641	SELMSetTrap8EIP(pVM, Offset);
642	continue;
643	}
644	/* (non-task gates only ) */
645	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
646	pIdte->Gen.u16OffsetHigh = Offset >> 16;
647	pIdte->Gen.u16SegSel = SelCS;
648	}
649	}
650
651	/*
652	* Update IDTR (limit is including!).
653	*/
654	CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
655
656	if (!pVM->trpm.s.fDisableMonitoring)
657	{
658	#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
659	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
660	{
661	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
662	AssertRC(rc);
663	}
664	pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
665	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
666	0, 0, "trpmRCShadowIDTWriteHandler", 0, "Shadow IDT write access handler");
667	AssertRC(rc);
668	#endif
669	}
670
671	/* Relocate IDT handlers for forwarding guest traps/interrupts. */
672	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
673	{
674	if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
675	{
676	Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
677	pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
678	}
679
680	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
681	{
682	PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
683	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
684
685	Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
686	pHandler += offDelta;
687
688	pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
689	pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
690	}
691	}
692
693	#ifdef VBOX_WITH_STATISTICS
694	pVM->trpm.s.paStatForwardedIRQRC += offDelta;
695	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
696	#endif
697	}
698
699
700	/**
701	* Terminates the Trap Manager
702	*
703	* @returns VBox status code.
704	* @param pVM The VM to operate on.
705	*/
706	VMMR3DECL(int) TRPMR3Term(PVM pVM)
707	{
708	NOREF(pVM);
709	return 0;
710	}
711
712
713	/**
714	* Resets a virtual CPU.
715	*
716	* Used by TRPMR3Reset and CPU hot plugging.
717	*
718	* @param pVCpu The virtual CPU handle.
719	*/
720	VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
721	{
722	pVCpu->trpm.s.uActiveVector = ~0;
723	}
724
725
726	/**
727	* The VM is being reset.
728	*
729	* For the TRPM component this means that any IDT write monitors
730	* needs to be removed, any pending trap cleared, and the IDT reset.
731	*
732	* @param pVM VM handle.
733	*/
734	VMMR3DECL(void) TRPMR3Reset(PVM pVM)
735	{
736	/*
737	* Deregister any virtual handlers.
738	*/
739	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
740	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
741	{
742	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
743	{
744	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
745	AssertRC(rc);
746	}
747	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
748	}
749	pVM->trpm.s.GuestIdtr.cbIdt = 0;
750	#endif
751
752	/*
753	* Reinitialize other members calling the relocator to get things right.
754	*/
755	for (VMCPUID i = 0; i < pVM->cCpus; i++)
756	TRPMR3ResetCpu(&pVM->aCpus[i]);
757	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
758	memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
759	TRPMR3Relocate(pVM, 0);
760
761	/*
762	* Default action when entering raw mode for the first time
763	*/
764	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
765	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
766	}
767
768
769	/**
770	* Execute state save operation.
771	*
772	* @returns VBox status code.
773	* @param pVM VM Handle.
774	* @param pSSM SSM operation handle.
775	*/
776	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
777	{
778	PTRPM pTrpm = &pVM->trpm.s;
779	LogFlow(("trpmR3Save:\n"));
780
781	/*
782	* Active and saved traps.
783	*/
784	for (VMCPUID i = 0; i < pVM->cCpus; i++)
785	{
786	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
787	SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
788	SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
789	SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
790	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
791	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
792	SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
793	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
794	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
795	SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
796	}
797	SSMR3PutBool(pSSM, pTrpm->fDisableMonitoring);
798	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
799	SSMR3PutUInt(pSSM, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT));
800	SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
801	SSMR3PutU32(pSSM, ~0); /* separator. */
802
803	/*
804	* Save any trampoline gates.
805	*/
806	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
807	{
808	if (pTrpm->aGuestTrapHandler[iTrap])
809	{
810	SSMR3PutU32(pSSM, iTrap);
811	SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
812	SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
813	}
814	}
815
816	return SSMR3PutU32(pSSM, ~0); /* terminator */
817	}
818
819
820	/**
821	* Execute state load operation.
822	*
823	* @returns VBox status code.
824	* @param pVM VM Handle.
825	* @param pSSM SSM operation handle.
826	* @param uVersion Data layout version.
827	* @param uPass The data pass.
828	*/
829	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
830	{
831	LogFlow(("trpmR3Load:\n"));
832	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
833
834	/*
835	* Validate version.
836	*/
837	if ( uVersion != TRPM_SAVED_STATE_VERSION
838	&& uVersion != TRPM_SAVED_STATE_VERSION_UNI)
839	{
840	AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
841	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
842	}
843
844	/*
845	* Call the reset function to kick out any handled gates and other potential trouble.
846	*/
847	TRPMR3Reset(pVM);
848
849	/*
850	* Active and saved traps.
851	*/
852	PTRPM pTrpm = &pVM->trpm.s;
853
854	if (uVersion == TRPM_SAVED_STATE_VERSION)
855	{
856	for (VMCPUID i = 0; i < pVM->cCpus; i++)
857	{
858	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
859	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
860	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
861	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
862	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
863	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
864	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
865	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
866	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
867	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
868	}
869
870	SSMR3GetBool(pSSM, &pVM->trpm.s.fDisableMonitoring);
871	}
872	else
873	{
874	PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
875	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
876	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
877	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
878	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
879	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
880	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
881	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
882	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
883	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
884
885	RTGCUINT fDisableMonitoring;
886	SSMR3GetGCUInt(pSSM, &fDisableMonitoring);
887	pTrpm->fDisableMonitoring = !!fDisableMonitoring;
888	}
889
890	RTUINT fSyncIDT;
891	int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
892	if (RT_FAILURE(rc))
893	return rc;
894	if (fSyncIDT & ~1)
895	{
896	AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
897	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
898	}
899	if (fSyncIDT)
900	{
901	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
902	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
903	}
904	/* else: cleared by reset call above. */
905
906	SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
907
908	/* check the separator */
909	uint32_t u32Sep;
910	rc = SSMR3GetU32(pSSM, &u32Sep);
911	if (RT_FAILURE(rc))
912	return rc;
913	if (u32Sep != (uint32_t)~0)
914	{
915	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
916	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
917	}
918
919	/*
920	* Restore any trampoline gates.
921	*/
922	for (;;)
923	{
924	/* gate number / terminator */
925	uint32_t iTrap;
926	rc = SSMR3GetU32(pSSM, &iTrap);
927	if (RT_FAILURE(rc))
928	return rc;
929	if (iTrap == (uint32_t)~0)
930	break;
931	if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
932	\|\| pTrpm->aGuestTrapHandler[iTrap])
933	{
934	AssertMsgFailed(("iTrap=%#x\n", iTrap));
935	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
936	}
937
938	/* restore the IDT entry. */
939	RTGCPTR GCPtrHandler;
940	SSMR3GetGCPtr(pSSM, &GCPtrHandler);
941	VBOXIDTE Idte;
942	rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
943	if (RT_FAILURE(rc))
944	return rc;
945	Assert(GCPtrHandler);
946	pTrpm->aIdt[iTrap] = Idte;
947	}
948
949	return VINF_SUCCESS;
950	}
951
952
953	/**
954	* Check if gate handlers were updated
955	* (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
956	*
957	* @returns VBox status code.
958	* @param pVM The VM handle.
959	* @param pVCpu The VMCPU handle.
960	*/
961	VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
962	{
963	STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
964	const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
965	int rc;
966
967	if (pVM->trpm.s.fDisableMonitoring)
968	{
969	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
970	return VINF_SUCCESS; /* Nothing to do */
971	}
972
973	if (fRawRing0 && CSAMIsEnabled(pVM))
974	{
975	/* Clear all handlers */
976	Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
977	/** @todo inefficient, but simple */
978	for (unsigned iGate = 0; iGate < 256; iGate++)
979	trpmClearGuestTrapHandler(pVM, iGate);
980
981	/* Scan them all (only the first time) */
982	CSAMR3CheckGates(pVM, 0, 256);
983	}
984
985	/*
986	* Get the IDTR.
987	*/
988	VBOXIDTR IDTR;
989	IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
990	if (!IDTR.cbIdt)
991	{
992	Log(("No IDT entries...\n"));
993	return DBGFSTOP(pVM);
994	}
995
996	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
997	/*
998	* Check if Guest's IDTR has changed.
999	*/
1000	if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1001	\|\| IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1002	{
1003	Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1004	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1005	{
1006	/*
1007	* [Re]Register write virtual handler for guest's IDT.
1008	*/
1009	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1010	{
1011	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1012	AssertRCReturn(rc, rc);
1013	}
1014	/* limit is including */
1015	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1016	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1017
1018	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1019	{
1020	/* Could be a conflict with CSAM */
1021	CSAMR3RemovePage(pVM, IDTR.pIdt);
1022	if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1023	CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1024
1025	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1026	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1027	}
1028
1029	AssertRCReturn(rc, rc);
1030	}
1031
1032	/* Update saved Guest IDTR. */
1033	pVM->trpm.s.GuestIdtr = IDTR;
1034	}
1035	#endif
1036
1037	/*
1038	* Sync the interrupt gate.
1039	* Should probably check/sync the others too, but for now we'll handle that in #GP.
1040	*/
1041	X86DESC Idte3;
1042	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1043	if (RT_FAILURE(rc))
1044	{
1045	AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1046	return DBGFSTOP(pVM);
1047	}
1048	AssertRCReturn(rc, rc);
1049	if (fRawRing0)
1050	pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1051	else
1052	pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1053
1054	/*
1055	* Clear the FF and we're done.
1056	*/
1057	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1058	STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1059	return VINF_SUCCESS;
1060	}
1061
1062
1063	/**
1064	* Disable IDT monitoring and syncing
1065	*
1066	* @param pVM The VM to operate on.
1067	*/
1068	VMMR3DECL(void) TRPMR3DisableMonitoring(PVM pVM)
1069	{
1070	/*
1071	* Deregister any virtual handlers.
1072	*/
1073	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1074	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1075	{
1076	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1077	{
1078	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1079	AssertRC(rc);
1080	}
1081	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
1082	}
1083	pVM->trpm.s.GuestIdtr.cbIdt = 0;
1084	#endif
1085
1086	#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
1087	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
1088	{
1089	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
1090	AssertRC(rc);
1091	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
1092	}
1093	#endif
1094
1095	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
1096	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1097
1098	pVM->trpm.s.fDisableMonitoring = true;
1099	}
1100
1101
1102	/**
1103	* \#PF Handler callback for virtual access handler ranges.
1104	*
1105	* Important to realize that a physical page in a range can have aliases, and
1106	* for ALL and WRITE handlers these will also trigger.
1107	*
1108	* @returns VINF_SUCCESS if the handler have carried out the operation.
1109	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1110	* @param pVM VM Handle.
1111	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1112	* @param pvPtr The HC mapping of that address.
1113	* @param pvBuf What the guest is reading/writing.
1114	* @param cbBuf How much it's reading/writing.
1115	* @param enmAccessType The access type.
1116	* @param pvUser User argument.
1117	*/
1118	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1119	{
1120	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1121	Log(("trpmR3GuestIDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1122	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TRPM_SYNC_IDT);
1123	return VINF_PGM_HANDLER_DO_DEFAULT;
1124	}
1125
1126
1127	/**
1128	* Clear passthrough interrupt gate handler (reset to default handler)
1129	*
1130	* @returns VBox status code.
1131	* @param pVM The VM to operate on.
1132	* @param iTrap Trap/interrupt gate number.
1133	*/
1134	VMMR3DECL(int) trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1135	{
1136	/* Only applies to raw mode which supports only 1 VCPU. */
1137	PVMCPU pVCpu = &pVM->aCpus[0];
1138
1139	/** @todo cleanup trpmR3ClearPassThroughHandler()! */
1140	RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1141	int rc;
1142
1143	memset(aGCPtrs, 0, sizeof(aGCPtrs));
1144
1145	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1146	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
1147
1148	if ( iTrap < TRPM_HANDLER_INT_BASE
1149	\|\| iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1150	{
1151	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1152	return VERR_INVALID_PARAMETER;
1153	}
1154	memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1155
1156	/* Unmark it for relocation purposes. */
1157	ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1158
1159	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1160	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1161	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1162	if (pIdte->Gen.u1Present)
1163	{
1164	Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1165	Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1166	RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1167
1168	/*
1169	* Generic handlers have different entrypoints for each possible
1170	* vector number. These entrypoints make a sort of an array with
1171	* 8 byte entries where the vector number is the index.
1172	* See TRPMGCHandlersA.asm for details.
1173	*/
1174	Offset += iTrap * 8;
1175
1176	if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1177	{
1178	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1179	pIdte->Gen.u16OffsetHigh = Offset >> 16;
1180	pIdte->Gen.u16SegSel = SelCS;
1181	}
1182	}
1183
1184	return VINF_SUCCESS;
1185	}
1186
1187
1188	/**
1189	* Check if address is a gate handler (interrupt or trap).
1190	*
1191	* @returns gate nr or ~0 is not found
1192	*
1193	* @param pVM VM handle.
1194	* @param GCPtr GC address to check.
1195	*/
1196	VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1197	{
1198	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1199	{
1200	if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1201	return iTrap;
1202
1203	/* redundant */
1204	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1205	{
1206	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1207	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1208
1209	if (pHandler == GCPtr)
1210	return iTrap;
1211	}
1212	}
1213	return ~0;
1214	}
1215
1216
1217	/**
1218	* Get guest trap/interrupt gate handler
1219	*
1220	* @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1221	* @param pVM The VM to operate on.
1222	* @param iTrap Interrupt/trap number.
1223	*/
1224	VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1225	{
1226	AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1227
1228	return pVM->trpm.s.aGuestTrapHandler[iTrap];
1229	}
1230
1231
1232	/**
1233	* Set guest trap/interrupt gate handler
1234	* Used for setting up trap gates used for kernel calls.
1235	*
1236	* @returns VBox status code.
1237	* @param pVM The VM to operate on.
1238	* @param iTrap Interrupt/trap number.
1239	* @param pHandler GC handler pointer
1240	*/
1241	VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1242	{
1243	/* Only valid in raw mode which implies 1 VCPU */
1244	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1245	PVMCPU pVCpu = &pVM->aCpus[0];
1246
1247	/*
1248	* Validate.
1249	*/
1250	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1251	{
1252	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1253	return VERR_INVALID_PARAMETER;
1254	}
1255
1256	AssertReturn(pHandler == TRPM_INVALID_HANDLER \|\| PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1257
1258	uint16_t cbIDT;
1259	RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1260	if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1261	return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1262
1263	if (pHandler == TRPM_INVALID_HANDLER)
1264	{
1265	/* clear trap handler */
1266	Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1267	return trpmClearGuestTrapHandler(pVM, iTrap);
1268	}
1269
1270	/*
1271	* Read the guest IDT entry.
1272	*/
1273	VBOXIDTE GuestIdte;
1274	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1275	if (RT_FAILURE(rc))
1276	{
1277	AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1278	return rc;
1279	}
1280
1281	if (EMIsRawRing0Enabled(pVM))
1282	{
1283	/*
1284	* Only replace handlers for which we are 100% certain there won't be
1285	* any host interrupts.
1286	*
1287	* 0x2E is safe on Windows because it's the system service interrupt gate. Not
1288	* quite certain if this is safe or not on 64-bit Vista, it probably is.
1289	*
1290	* 0x80 is safe on Linux because it's the syscall vector and is part of the
1291	* 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1292	* and will therefor never assign hardware interrupts to 0x80.
1293	*
1294	* Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1295	* to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1296	* Booting Linux/BSD guest will cause system lockups on most of the computers.
1297	* -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1298	* defect #3604.
1299	*
1300	* PORTME - Check if your host keeps any of these gates free from hw ints.
1301	*
1302	* Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1303	*/
1304	/** @todo handle those dependencies better! */
1305	/** @todo Solve this in a proper manner. see defect #1186 */
1306	#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1307	if (iTrap == 0x2E)
1308	#elif defined(RT_OS_LINUX)
1309	if (iTrap == 0x80)
1310	#else
1311	if (0)
1312	#endif
1313	{
1314	if ( GuestIdte.Gen.u1Present
1315	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1316	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1317	&& GuestIdte.Gen.u2DPL == 3)
1318	{
1319	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1320
1321	GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1322	GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1323	GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1324	GuestIdte.Gen.u16SegSel \|= 1; //ring 1
1325	*pIdte = GuestIdte;
1326
1327	/* Mark it for relocation purposes. */
1328	ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1329
1330	/* Also store it in our guest trap array. */
1331	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1332
1333	Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1334	return VINF_SUCCESS;
1335	}
1336	/* ok, let's try to install a trampoline handler then. */
1337	}
1338	}
1339
1340	if ( GuestIdte.Gen.u1Present
1341	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1342	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1343	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0))
1344	{
1345	/*
1346	* Save handler which can be used for a trampoline call inside the GC
1347	*/
1348	Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1349	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1350	return VINF_SUCCESS;
1351	}
1352	return VERR_INVALID_PARAMETER;
1353	}
1354
1355
1356	/**
1357	* Check if address is a gate handler (interrupt/trap/task/anything).
1358	*
1359	* @returns True is gate handler, false if not.
1360	*
1361	* @param pVM VM handle.
1362	* @param GCPtr GC address to check.
1363	*/
1364	VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1365	{
1366	/* Only valid in raw mode which implies 1 VCPU */
1367	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1368	PVMCPU pVCpu = &pVM->aCpus[0];
1369
1370	/*
1371	* Read IDTR and calc last entry.
1372	*/
1373	uint16_t cbIDT;
1374	RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1375	unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1376	if (!cEntries)
1377	return false;
1378	RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1379
1380	/*
1381	* Outer loop: interate pages.
1382	*/
1383	while (GCPtrIDTE <= GCPtrIDTELast)
1384	{
1385	/*
1386	* Convert this page to a HC address.
1387	* (This function checks for not-present pages.)
1388	*/
1389	PCVBOXIDTE pIDTE;
1390	PGMPAGEMAPLOCK Lock;
1391	int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1392	if (RT_SUCCESS(rc))
1393	{
1394	/*
1395	* Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1396	* N.B. Member of the Flat Earth Society...
1397	*/
1398	while (GCPtrIDTE <= GCPtrIDTELast)
1399	{
1400	if (pIDTE->Gen.u1Present)
1401	{
1402	RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1403	if (GCPtr == GCPtrHandler)
1404	{
1405	PGMPhysReleasePageMappingLock(pVM, &Lock);
1406	return true;
1407	}
1408	}
1409
1410	/* next entry */
1411	if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1412	{
1413	AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1414	("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1415	GCPtrIDTE += sizeof(VBOXIDTE);
1416	break;
1417	}
1418	GCPtrIDTE += sizeof(VBOXIDTE);
1419	pIDTE++;
1420	}
1421	PGMPhysReleasePageMappingLock(pVM, &Lock);
1422	}
1423	else
1424	{
1425	/* Skip to the next page (if any). Take care not to wrap around the address space. */
1426	if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1427	return false;
1428	GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1429	}
1430	}
1431	return false;
1432	}
1433
1434
1435	/**
1436	* Inject event (such as external irq or trap)
1437	*
1438	* @returns VBox status code.
1439	* @param pVM The VM to operate on.
1440	* @param pVCpu The VMCPU to operate on.
1441	* @param enmEvent Trpm event type
1442	*/
1443	VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1444	{
1445	PCPUMCTX pCtx;
1446	int rc;
1447
1448	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1449	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1450	Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1451
1452	/* Currently only useful for external hardware interrupts. */
1453	Assert(enmEvent == TRPM_HARDWARE_INT);
1454
1455	if (REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ)
1456	{
1457	#ifdef TRPM_FORWARD_TRAPS_IN_GC
1458
1459	# ifdef LOG_ENABLED
1460	DBGFR3InfoLog(pVM, "cpumguest", "TRPMInject");
1461	DBGFR3DisasInstrCurrentLog(pVCpu, "TRPMInject");
1462	# endif
1463
1464	uint8_t u8Interrupt;
1465	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1466	Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1467	if (RT_SUCCESS(rc))
1468	{
1469	if (HWACCMIsEnabled(pVM))
1470	{
1471	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1472	AssertRC(rc);
1473	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1474	return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM;
1475	}
1476	/* If the guest gate is not patched, then we will check (again) if we can patch it. */
1477	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1478	{
1479	CSAMR3CheckGates(pVM, u8Interrupt, 1);
1480	Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1481	}
1482
1483	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1484	{
1485	/* Must check pending forced actions as our IDT or GDT might be out of sync */
1486	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1487	if (rc == VINF_SUCCESS)
1488	{
1489	/* There's a handler -> let's execute it in raw mode */
1490	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1491	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1492	{
1493	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1494
1495	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1496	return VINF_EM_RESCHEDULE_RAW;
1497	}
1498	}
1499	}
1500	else
1501	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1502	REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1503	}
1504	else
1505	{
1506	AssertRC(rc);
1507	return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1508	}
1509	#else
1510	if (HWACCMR3IsActive(pVM))
1511	{
1512	uint8_t u8Interrupt;
1513	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1514	Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1515	if (RT_SUCCESS(rc))
1516	{
1517	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
1518	AssertRC(rc);
1519	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1520	return VINF_EM_RESCHEDULE_HWACC;
1521	}
1522	}
1523	else
1524	AssertRC(rc);
1525	#endif
1526	}
1527	/** @todo check if it's safe to translate the patch address to the original guest address.
1528	* this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1529	*/
1530	/* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1531
1532	/* Fall back to the recompiler */
1533	return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1534	}
1535

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source: vbox/trunk/src/VBox/VMM/TRPM.cpp@ 31816

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