VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 13263

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1/* $Id: VMM.cpp 13005 2008-10-06 12:35:21Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22//#define NO_SUPCALLR0VMM
23
24/** @page pg_vmm VMM - The Virtual Machine Monitor
25 *
26 * !Revise this! It's already incorrect!
27 *
28 * The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
29 * manages the alternate reality; controlling the virtualization, managing
30 * resources, tracking CPU state, it's resources and so on...
31 *
32 * We will split the VMM into smaller entities:
33 *
34 * - Virtual Machine Core Monitor (VMCM), which purpose it is to
35 * provide ring and world switching, that including routing
36 * interrupts to the host OS and traps to the appropriate trap
37 * handlers. It will implement an external interface for
38 * managing trap handlers.
39 *
40 * - CPU Monitor (CM), tracking the state of the CPU (in the alternate
41 * reality) and implementing external interfaces to read and change
42 * the state.
43 *
44 * - Memory Monitor (MM), which purpose it is to virtualize physical
45 * pages, segment descriptor tables, interrupt descriptor tables, task
46 * segments, and keep track of all memory providing external interfaces
47 * to access content and map pages. (Internally splitt into smaller entities!)
48 *
49 * - IO Monitor (IOM), which virtualizes in and out I/O operations. It
50 * interacts with the MM to implement memory mapped I/O. External
51 * interfaces for adding and removing I/O ranges are implemented.
52 *
53 * - External Interrupt Monitor (EIM), which purpose it is to manage
54 * interrupts generated by virtual devices. This monitor provides
55 * an interfaces for raising interrupts which is accessible at any
56 * time and from all thread.
57 * <p>
58 * A subentity of the EIM is the vitual Programmable Interrupt
59 * Controller Device (VPICD), and perhaps a virtual I/O Advanced
60 * Programmable Interrupt Controller Device (VAPICD).
61 *
62 * - Direct Memory Access Monitor (DMAM), which purpose it is to support
63 * virtual device using the DMA controller. Interfaces must be as the
64 * EIM interfaces independent and threadable.
65 * <p>
66 * A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
67 *
68 *
69 * Entities working on a higher level:
70 *
71 * - Device Manager (DM), which is a support facility for virtualized
72 * hardware. This provides generic facilities for efficient device
73 * virtualization. It will manage device attaching and detaching
74 * conversing with EIM and IOM.
75 *
76 * - Debugger Facility (DBGF) provides the basic features for
77 * debugging the alternate reality execution.
78 *
79 *
80 * @see grp_vmm, grp_vm
81 *
82 *
83 * @section pg_vmm_s_use_cases Use Cases
84 *
85 * @subsection pg_vmm_s_use_case_boot Bootstrap
86 *
87 * - Basic Init:
88 * - Init SUPDRV.
89 *
90 * - Init Virtual Machine Instance:
91 * - Load settings.
92 * - Check resource requirements (memory, com, stuff).
93 *
94 * - Init Host Ring 3 part:
95 * - Init Core code.
96 * - Load Pluggable Components.
97 * - Init Pluggable Components.
98 *
99 * - Init Host Ring 0 part:
100 * - Load Core (core = core components like VMM, RMI, CA, and so on) code.
101 * - Init Core code.
102 * - Load Pluggable Component code.
103 * - Init Pluggable Component code.
104 *
105 * - Allocate first chunk of memory and pin it down. This block of memory
106 * will fit the following pieces:
107 * - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
108 * (This is available from everywhere (at different addresses though)).
109 * - VMM Guest Context code.
110 * - Pluggable devices Guest Context code.
111 * - Page tables (directory and everything) for the VMM Guest
112 *
113 * - Setup Guest (Ring 0) part:
114 * - Setup initial page tables (i.e. directory all the stuff).
115 * - Load Core Guest Context code.
116 * - Load Pluggable Devices Guest Context code.
117 *
118 *
119 */
120
121
122/*******************************************************************************
123* Header Files *
124*******************************************************************************/
125#define LOG_GROUP LOG_GROUP_VMM
126#include <VBox/vmm.h>
127#include <VBox/vmapi.h>
128#include <VBox/pgm.h>
129#include <VBox/cfgm.h>
130#include <VBox/pdmqueue.h>
131#include <VBox/pdmapi.h>
132#include <VBox/cpum.h>
133#include <VBox/mm.h>
134#include <VBox/iom.h>
135#include <VBox/trpm.h>
136#include <VBox/selm.h>
137#include <VBox/em.h>
138#include <VBox/sup.h>
139#include <VBox/dbgf.h>
140#include <VBox/csam.h>
141#include <VBox/patm.h>
142#include <VBox/rem.h>
143#include <VBox/ssm.h>
144#include <VBox/tm.h>
145#include "VMMInternal.h"
146#include "VMMSwitcher/VMMSwitcher.h"
147#include <VBox/vm.h>
148#include <VBox/err.h>
149#include <VBox/param.h>
150#include <VBox/version.h>
151#include <VBox/x86.h>
152#include <VBox/hwaccm.h>
153#include <iprt/assert.h>
154#include <iprt/alloc.h>
155#include <iprt/asm.h>
156#include <iprt/time.h>
157#include <iprt/stream.h>
158#include <iprt/string.h>
159#include <iprt/stdarg.h>
160#include <iprt/ctype.h>
161
162
163
164/** The saved state version. */
165#define VMM_SAVED_STATE_VERSION 3
166
167
168/*******************************************************************************
169* Internal Functions *
170*******************************************************************************/
171static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
172static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
173static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
174static int vmmR3ServiceCallHostRequest(PVM pVM);
175static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176
177
178/*******************************************************************************
179* Global Variables *
180*******************************************************************************/
181/** Array of switcher defininitions.
182 * The type and index shall match!
183 */
184static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
185{
186 NULL, /* invalid entry */
187#ifndef RT_ARCH_AMD64
188 &vmmR3Switcher32BitTo32Bit_Def,
189 &vmmR3Switcher32BitToPAE_Def,
190 NULL, //&vmmR3Switcher32BitToAMD64_Def,
191 &vmmR3SwitcherPAETo32Bit_Def,
192 &vmmR3SwitcherPAEToPAE_Def,
193 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
194# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
195 &vmmR3SwitcherAMD64ToPAE_Def,
196# else
197 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
198# endif
199 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
200#else
201 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
202 NULL, //&vmmR3Switcher32BitToPAE_Def,
203 NULL, //&vmmR3Switcher32BitToAMD64_Def,
204 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
205 NULL, //&vmmR3SwitcherPAEToPAE_Def,
206 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
207 &vmmR3SwitcherAMD64ToPAE_Def,
208 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
209#endif
210};
211
212
213
214/**
215 * Initiates the core code.
216 *
217 * This is core per VM code which might need fixups and/or for ease of use
218 * are put on linear contiguous backing.
219 *
220 * @returns VBox status code.
221 * @param pVM Pointer to VM structure.
222 */
223static int vmmR3InitCoreCode(PVM pVM)
224{
225 /*
226 * Calc the size.
227 */
228 unsigned cbCoreCode = 0;
229 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
230 {
231 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
232 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
233 if (pSwitcher)
234 {
235 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
236 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
237 }
238 }
239
240 /*
241 * Allocate continguous pages for switchers and deal with
242 * conflicts in the intermediate mapping of the code.
243 */
244 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
245 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
246 int rc = VERR_NO_MEMORY;
247 if (pVM->vmm.s.pvHCCoreCodeR3)
248 {
249 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
250 if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
251 {
252 /* try more allocations - Solaris */
253 const unsigned cTries = 4112;
254 struct VMMInitBadTry
255 {
256 RTR0PTR pvR0;
257 void *pvR3;
258 RTHCPHYS HCPhys;
259 RTUINT cb;
260 } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
261 AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
262 unsigned i = 0;
263 do
264 {
265 paBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
266 paBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
267 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
268 i++;
269 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
270 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
271 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
272 if (!pVM->vmm.s.pvHCCoreCodeR3)
273 break;
274 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
275 } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
276 && i < cTries - 1);
277
278 /* cleanup */
279 if (VBOX_FAILURE(rc))
280 {
281 paBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
282 paBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
283 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
284 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
285 i++;
286 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
287 }
288 while (i-- > 0)
289 {
290 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
291 i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
292 SUPContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
293 }
294 RTMemTmpFree(paBadTries);
295 }
296 }
297 if (VBOX_SUCCESS(rc))
298 {
299 /*
300 * copy the code.
301 */
302 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
303 {
304 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
305 if (pSwitcher)
306 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
307 pSwitcher->pvCode, pSwitcher->cbCode);
308 }
309
310 /*
311 * Map the code into the GC address space.
312 */
313 RTGCPTR GCPtr;
314 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &GCPtr);
315 if (VBOX_SUCCESS(rc))
316 {
317 pVM->vmm.s.pvGCCoreCode = GCPtr;
318 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
319 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VRv Phys=%VHp cb=%#x\n",
320 pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
321
322 /*
323 * Finally, PGM probably have selected a switcher already but we need
324 * to do get the addresses so we'll reselect it.
325 * This may legally fail so, we're ignoring the rc.
326 */
327 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
328 return rc;
329 }
330
331 /* shit */
332 AssertMsgFailed(("PGMR3Map(,%VRv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
333 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
334 }
335 else
336 VMSetError(pVM, rc, RT_SRC_POS,
337 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
338 cbCoreCode);
339
340 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
341 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
342 pVM->vmm.s.pvGCCoreCode = 0;
343 return rc;
344}
345
346
347/**
348 * Initializes the VMM.
349 *
350 * @returns VBox status code.
351 * @param pVM The VM to operate on.
352 */
353VMMR3DECL(int) VMMR3Init(PVM pVM)
354{
355 LogFlow(("VMMR3Init\n"));
356
357 /*
358 * Assert alignment, sizes and order.
359 */
360 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
361 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
362 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
363 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
364
365 /*
366 * Init basic VM VMM members.
367 */
368 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
369 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
370 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
371 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
372 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
373 else
374 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
375
376 /* GC switchers are enabled by default. Turned off by HWACCM. */
377 pVM->vmm.s.fSwitcherDisabled = false;
378
379 /* Get the CPU count.*/
380 rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "NumCPUs", &pVM->cCPUs, 1);
381 AssertLogRelMsgRCReturn(rc, ("Configuration error: Querying \"NumCPUs\" as integer failed, rc=%Vrc\n", rc), rc);
382#ifdef VBOX_WITH_SMP_GUESTS
383 AssertLogRelMsgReturn(pVM->cCPUs > 0 && pVM->cCPUs <= 256,
384 ("Configuration error: \"NumCPUs\"=%RU32 is out of range [1..256]\n", pVM->cCPUs), VERR_INVALID_PARAMETER);
385#else
386 AssertLogRelMsgReturn(pVM->cCPUs != 0,
387 ("Configuration error: \"NumCPUs\"=%RU32, expected 1\n", pVM->cCPUs), VERR_INVALID_PARAMETER);
388#endif
389
390#ifdef VBOX_WITH_SMP_GUESTS
391 LogRel(("[SMP] VMM with %RU32 CPUs\n", pVM->cCPUs));
392#endif
393
394 /*
395 * Register the saved state data unit.
396 */
397 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
398 NULL, vmmR3Save, NULL,
399 NULL, vmmR3Load, NULL);
400 if (VBOX_FAILURE(rc))
401 return rc;
402
403 /*
404 * Register the Ring-0 VM handle with the session for fast ioctl calls.
405 */
406 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
407 if (VBOX_FAILURE(rc))
408 return rc;
409
410 /*
411 * Init core code.
412 */
413 rc = vmmR3InitCoreCode(pVM);
414 if (VBOX_SUCCESS(rc))
415 {
416 /*
417 * Allocate & init VMM GC stack.
418 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
419 * (The page protection is modifed during R3 init completion.)
420 */
421#ifdef VBOX_STRICT_VMM_STACK
422 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
423#else
424 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
425#endif
426 if (VBOX_SUCCESS(rc))
427 {
428 /* Set HC and GC stack pointers to top of stack. */
429 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
430 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
431 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
432 AssertRelease(pVM->vmm.s.pbGCStack);
433
434 /* Set hypervisor eip. */
435 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
436
437 /*
438 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
439 */
440#ifdef LOG_ENABLED
441 PRTLOGGER pLogger = RTLogDefaultInstance();
442 if (pLogger)
443 {
444 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERRC, afGroups[pLogger->cGroups]);
445 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
446 if (VBOX_SUCCESS(rc))
447 {
448 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
449
450/*
451 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
452 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
453 *
454 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
455 * to not stub all the log functions.
456 *
457 * You might also wish to enable the AssertMsg1/2 overrides in VMMR0.cpp when enabling this.
458 */
459# if defined(DEBUG_sandervl) || defined(DEBUG_frank)
460 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
461 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
462 if (VBOX_SUCCESS(rc))
463 {
464 pVM->vmm.s.pR0Logger->pVM = pVM->pVMR0;
465 //pVM->vmm.s.pR0Logger->fCreated = false;
466 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
467 }
468# endif
469 }
470 }
471#endif /* LOG_ENABLED */
472
473#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
474 /*
475 * Allocate GC Release Logger instances (finalized in the relocator).
476 */
477 if (VBOX_SUCCESS(rc))
478 {
479 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
480 if (pRelLogger)
481 {
482 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERRC, afGroups[pRelLogger->cGroups]);
483 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
484 if (VBOX_SUCCESS(rc))
485 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
486 }
487 }
488#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
489
490#ifdef VBOX_WITH_NMI
491 /*
492 * Allocate mapping for the host APIC.
493 */
494 if (VBOX_SUCCESS(rc))
495 {
496 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
497 AssertRC(rc);
498 }
499#endif
500 if (VBOX_SUCCESS(rc))
501 {
502 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
503 if (VBOX_SUCCESS(rc))
504 {
505 /*
506 * Debug info.
507 */
508 DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
509
510 /*
511 * Statistics.
512 */
513 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
514 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
517 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
518 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
519 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
520 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
521 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
522 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
523 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
524 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
525 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
526 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
527 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
528 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
529 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
530 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
531 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
532 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
533 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
534 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
535 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
536 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
537 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
538 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
539 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
540 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
541 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
542 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
543 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
544 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
545 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
546 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
547 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
548 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
549 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
550 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
551 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
552 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
553 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
554 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
555 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
556 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
557 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
558 STAM_REG(pVM, &pVM->vmm.s.StatGCRetHyperAssertion, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/HyperAssert", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
559 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
560 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
561 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
562 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
563
564 return VINF_SUCCESS;
565 }
566 AssertRC(rc);
567 }
568 }
569 /** @todo: Need failure cleanup. */
570
571 //more todo in here?
572 //if (VBOX_SUCCESS(rc))
573 //{
574 //}
575 //int rc2 = vmmR3TermCoreCode(pVM);
576 //AssertRC(rc2));
577 }
578
579 return rc;
580}
581
582
583/**
584 * Ring-3 init finalizing.
585 *
586 * @returns VBox status code.
587 * @param pVM The VM handle.
588 */
589VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
590{
591#ifdef VBOX_STRICT_VMM_STACK
592 /*
593 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
594 */
595 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
596 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
597 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
598
599 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
600 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
601 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
602#endif
603
604 /*
605 * Set page attributes to r/w for stack pages.
606 */
607 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
608 AssertRC(rc);
609 if (VBOX_SUCCESS(rc))
610 {
611 /*
612 * Create the EMT yield timer.
613 */
614 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
615 if (VBOX_SUCCESS(rc))
616 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
617 }
618#ifdef VBOX_WITH_NMI
619 /*
620 * Map the host APIC into GC - This may be host os specific!
621 */
622 if (VBOX_SUCCESS(rc))
623 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
624 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
625#endif
626 return rc;
627}
628
629
630/**
631 * Initializes the R0 VMM.
632 *
633 * @returns VBox status code.
634 * @param pVM The VM to operate on.
635 */
636VMMR3DECL(int) VMMR3InitR0(PVM pVM)
637{
638 int rc;
639
640 /*
641 * Initialize the ring-0 logger if we haven't done so yet.
642 */
643 if ( pVM->vmm.s.pR0Logger
644 && !pVM->vmm.s.pR0Logger->fCreated)
645 {
646 rc = VMMR3UpdateLoggers(pVM);
647 if (VBOX_FAILURE(rc))
648 return rc;
649 }
650
651 /*
652 * Call Ring-0 entry with init code.
653 */
654 for (;;)
655 {
656#ifdef NO_SUPCALLR0VMM
657 //rc = VERR_GENERAL_FAILURE;
658 rc = VINF_SUCCESS;
659#else
660 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, VMMGetSvnRev(), NULL);
661#endif
662 if ( pVM->vmm.s.pR0Logger
663 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
664 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
665 if (rc != VINF_VMM_CALL_HOST)
666 break;
667 rc = vmmR3ServiceCallHostRequest(pVM);
668 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
669 break;
670 /* Resume R0 */
671 }
672
673 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
674 {
675 LogRel(("R0 init failed, rc=%Vra\n", rc));
676 if (VBOX_SUCCESS(rc))
677 rc = VERR_INTERNAL_ERROR;
678 }
679 return rc;
680}
681
682
683/**
684 * Initializes the GC VMM.
685 *
686 * @returns VBox status code.
687 * @param pVM The VM to operate on.
688 */
689VMMR3DECL(int) VMMR3InitGC(PVM pVM)
690{
691 /* In VMX mode, there's no need to init GC. */
692 if (pVM->vmm.s.fSwitcherDisabled)
693 return VINF_SUCCESS;
694
695 /*
696 * Call VMMGCInit():
697 * -# resolve the address.
698 * -# setup stackframe and EIP to use the trampoline.
699 * -# do a generic hypervisor call.
700 */
701 RTGCPTR32 GCPtrEP;
702 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
703 if (VBOX_SUCCESS(rc))
704 {
705 CPUMHyperSetCtxCore(pVM, NULL);
706 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
707 uint64_t u64TS = RTTimeProgramStartNanoTS();
708 CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
709 CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
710 CPUMPushHyper(pVM, VMMGetSvnRev()); /* Param 2: Version argument. */
711 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
712 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
713 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR32)); /* trampoline param: stacksize. */
714 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
715 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
716
717 for (;;)
718 {
719#ifdef NO_SUPCALLR0VMM
720 //rc = VERR_GENERAL_FAILURE;
721 rc = VINF_SUCCESS;
722#else
723 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
724#endif
725#ifdef LOG_ENABLED
726 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
727 if ( pLogger
728 && pLogger->offScratch > 0)
729 RTLogFlushGC(NULL, pLogger);
730#endif
731#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
732 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
733 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
734 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
735#endif
736 if (rc != VINF_VMM_CALL_HOST)
737 break;
738 rc = vmmR3ServiceCallHostRequest(pVM);
739 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
740 break;
741 }
742
743 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
744 {
745 VMMR3FatalDump(pVM, rc);
746 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
747 rc = VERR_INTERNAL_ERROR;
748 }
749 AssertRC(rc);
750 }
751 return rc;
752}
753
754
755/**
756 * Terminate the VMM bits.
757 *
758 * @returns VINF_SUCCESS.
759 * @param pVM The VM handle.
760 */
761VMMR3DECL(int) VMMR3Term(PVM pVM)
762{
763 /*
764 * Call Ring-0 entry with termination code.
765 */
766 int rc;
767 for (;;)
768 {
769#ifdef NO_SUPCALLR0VMM
770 //rc = VERR_GENERAL_FAILURE;
771 rc = VINF_SUCCESS;
772#else
773 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_TERM, 0, NULL);
774#endif
775 if ( pVM->vmm.s.pR0Logger
776 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
777 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
778 if (rc != VINF_VMM_CALL_HOST)
779 break;
780 rc = vmmR3ServiceCallHostRequest(pVM);
781 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
782 break;
783 /* Resume R0 */
784 }
785 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
786 {
787 LogRel(("VMMR3Term: R0 term failed, rc=%Vra. (warning)\n", rc));
788 if (VBOX_SUCCESS(rc))
789 rc = VERR_INTERNAL_ERROR;
790 }
791
792#ifdef VBOX_STRICT_VMM_STACK
793 /*
794 * Make the two stack guard pages present again.
795 */
796 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
797 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
798#endif
799 return rc;
800}
801
802
803/**
804 * Applies relocations to data and code managed by this
805 * component. This function will be called at init and
806 * whenever the VMM need to relocate it self inside the GC.
807 *
808 * The VMM will need to apply relocations to the core code.
809 *
810 * @param pVM The VM handle.
811 * @param offDelta The relocation delta.
812 */
813VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
814{
815 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
816
817 /*
818 * Recalc the GC address.
819 */
820 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
821
822 /*
823 * The stack.
824 */
825 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
826 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
827 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
828
829 /*
830 * All the switchers.
831 */
832 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
833 {
834 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
835 if (pSwitcher && pSwitcher->pfnRelocate)
836 {
837 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
838 pSwitcher->pfnRelocate(pVM,
839 pSwitcher,
840 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
841 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
842 pVM->vmm.s.pvGCCoreCode + off,
843 pVM->vmm.s.HCPhysCoreCode + off);
844 }
845 }
846
847 /*
848 * Recalc the GC address for the current switcher.
849 */
850 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
851 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
852 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
853 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
854 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
855 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
856 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
857
858 /*
859 * Get other GC entry points.
860 */
861 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
862 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
863
864 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
865 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
866
867 /*
868 * Update the logger.
869 */
870 VMMR3UpdateLoggers(pVM);
871}
872
873
874/**
875 * Updates the settings for the GC and R0 loggers.
876 *
877 * @returns VBox status code.
878 * @param pVM The VM handle.
879 */
880VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
881{
882 /*
883 * Simply clone the logger instance (for GC).
884 */
885 int rc = VINF_SUCCESS;
886 RTGCPTR32 GCPtrLoggerFlush = 0;
887
888 if (pVM->vmm.s.pLoggerHC
889#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
890 || pVM->vmm.s.pRelLoggerHC
891#endif
892 )
893 {
894 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
895 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
896 }
897
898 if (pVM->vmm.s.pLoggerHC)
899 {
900 RTGCPTR32 GCPtrLoggerWrapper = 0;
901 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
902 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
903 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
904 rc = RTLogCloneRC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
905 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
906 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
907 }
908
909#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
910 if (pVM->vmm.s.pRelLoggerHC)
911 {
912 RTGCPTR32 GCPtrLoggerWrapper = 0;
913 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
914 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
915 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
916 rc = RTLogCloneRC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
917 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
918 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
919 }
920#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
921
922 /*
923 * For the ring-0 EMT logger, we use a per-thread logger
924 * instance in ring-0. Only initialize it once.
925 */
926 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
927 if (pR0Logger)
928 {
929 if (!pR0Logger->fCreated)
930 {
931 RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
932 rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
933 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
934
935 RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
936 rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
937 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
938
939 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
940 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
941 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
942 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
943 pR0Logger->fCreated = true;
944 }
945
946 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, pVM->vmm.s.pLoggerHC->fFlags, RTLOGFLAGS_BUFFERED);
947 AssertRC(rc);
948 }
949
950 return rc;
951}
952
953
954/**
955 * Generic switch code relocator.
956 *
957 * @param pVM The VM handle.
958 * @param pSwitcher The switcher definition.
959 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
960 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
961 * @param GCPtrCode The guest context address corresponding to pu8Code.
962 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
963 * @param SelCS The hypervisor CS selector.
964 * @param SelDS The hypervisor DS selector.
965 * @param SelTSS The hypervisor TSS selector.
966 * @param GCPtrGDT The GC address of the hypervisor GDT.
967 * @param SelCS64 The 64-bit mode hypervisor CS selector.
968 */
969static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
970 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
971{
972 union
973 {
974 const uint8_t *pu8;
975 const uint16_t *pu16;
976 const uint32_t *pu32;
977 const uint64_t *pu64;
978 const void *pv;
979 uintptr_t u;
980 } u;
981 u.pv = pSwitcher->pvFixups;
982
983 /*
984 * Process fixups.
985 */
986 uint8_t u8;
987 while ((u8 = *u.pu8++) != FIX_THE_END)
988 {
989 /*
990 * Get the source (where to write the fixup).
991 */
992 uint32_t offSrc = *u.pu32++;
993 Assert(offSrc < pSwitcher->cbCode);
994 union
995 {
996 uint8_t *pu8;
997 uint16_t *pu16;
998 uint32_t *pu32;
999 uint64_t *pu64;
1000 uintptr_t u;
1001 } uSrc;
1002 uSrc.pu8 = pu8CodeR3 + offSrc;
1003
1004 /* The fixup target and method depends on the type. */
1005 switch (u8)
1006 {
1007 /*
1008 * 32-bit relative, source in HC and target in GC.
1009 */
1010 case FIX_HC_2_GC_NEAR_REL:
1011 {
1012 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1013 uint32_t offTrg = *u.pu32++;
1014 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1015 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
1016 break;
1017 }
1018
1019 /*
1020 * 32-bit relative, source in HC and target in ID.
1021 */
1022 case FIX_HC_2_ID_NEAR_REL:
1023 {
1024 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1025 uint32_t offTrg = *u.pu32++;
1026 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1027 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - ((uintptr_t)pu8CodeR0 + offSrc + 4));
1028 break;
1029 }
1030
1031 /*
1032 * 32-bit relative, source in GC and target in HC.
1033 */
1034 case FIX_GC_2_HC_NEAR_REL:
1035 {
1036 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1037 uint32_t offTrg = *u.pu32++;
1038 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1039 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
1040 break;
1041 }
1042
1043 /*
1044 * 32-bit relative, source in GC and target in ID.
1045 */
1046 case FIX_GC_2_ID_NEAR_REL:
1047 {
1048 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1049 uint32_t offTrg = *u.pu32++;
1050 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1051 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1052 break;
1053 }
1054
1055 /*
1056 * 32-bit relative, source in ID and target in HC.
1057 */
1058 case FIX_ID_2_HC_NEAR_REL:
1059 {
1060 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1061 uint32_t offTrg = *u.pu32++;
1062 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1063 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1064 break;
1065 }
1066
1067 /*
1068 * 32-bit relative, source in ID and target in HC.
1069 */
1070 case FIX_ID_2_GC_NEAR_REL:
1071 {
1072 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1073 uint32_t offTrg = *u.pu32++;
1074 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1075 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1076 break;
1077 }
1078
1079 /*
1080 * 16:32 far jump, target in GC.
1081 */
1082 case FIX_GC_FAR32:
1083 {
1084 uint32_t offTrg = *u.pu32++;
1085 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1086 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1087 *uSrc.pu16++ = SelCS;
1088 break;
1089 }
1090
1091 /*
1092 * Make 32-bit GC pointer given CPUM offset.
1093 */
1094 case FIX_GC_CPUM_OFF:
1095 {
1096 uint32_t offCPUM = *u.pu32++;
1097 Assert(offCPUM < sizeof(pVM->cpum));
1098 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1099 break;
1100 }
1101
1102 /*
1103 * Make 32-bit GC pointer given VM offset.
1104 */
1105 case FIX_GC_VM_OFF:
1106 {
1107 uint32_t offVM = *u.pu32++;
1108 Assert(offVM < sizeof(VM));
1109 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1110 break;
1111 }
1112
1113 /*
1114 * Make 32-bit HC pointer given CPUM offset.
1115 */
1116 case FIX_HC_CPUM_OFF:
1117 {
1118 uint32_t offCPUM = *u.pu32++;
1119 Assert(offCPUM < sizeof(pVM->cpum));
1120 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1121 break;
1122 }
1123
1124 /*
1125 * Make 32-bit R0 pointer given VM offset.
1126 */
1127 case FIX_HC_VM_OFF:
1128 {
1129 uint32_t offVM = *u.pu32++;
1130 Assert(offVM < sizeof(VM));
1131 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1132 break;
1133 }
1134
1135 /*
1136 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1137 */
1138 case FIX_INTER_32BIT_CR3:
1139 {
1140
1141 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1142 break;
1143 }
1144
1145 /*
1146 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1147 */
1148 case FIX_INTER_PAE_CR3:
1149 {
1150
1151 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1152 break;
1153 }
1154
1155 /*
1156 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1157 */
1158 case FIX_INTER_AMD64_CR3:
1159 {
1160
1161 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1162 break;
1163 }
1164
1165 /*
1166 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1167 */
1168 case FIX_HYPER_32BIT_CR3:
1169 {
1170
1171 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1172 break;
1173 }
1174
1175 /*
1176 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1177 */
1178 case FIX_HYPER_PAE_CR3:
1179 {
1180
1181 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1182 break;
1183 }
1184
1185 /*
1186 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1187 */
1188 case FIX_HYPER_AMD64_CR3:
1189 {
1190
1191 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1192 break;
1193 }
1194
1195 /*
1196 * Store Hypervisor CS (16-bit).
1197 */
1198 case FIX_HYPER_CS:
1199 {
1200 *uSrc.pu16 = SelCS;
1201 break;
1202 }
1203
1204 /*
1205 * Store Hypervisor DS (16-bit).
1206 */
1207 case FIX_HYPER_DS:
1208 {
1209 *uSrc.pu16 = SelDS;
1210 break;
1211 }
1212
1213 /*
1214 * Store Hypervisor TSS (16-bit).
1215 */
1216 case FIX_HYPER_TSS:
1217 {
1218 *uSrc.pu16 = SelTSS;
1219 break;
1220 }
1221
1222 /*
1223 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1224 */
1225 case FIX_GC_TSS_GDTE_DW2:
1226 {
1227 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1228 *uSrc.pu32 = (uint32_t)GCPtr;
1229 break;
1230 }
1231
1232
1233 ///@todo case FIX_CR4_MASK:
1234 ///@todo case FIX_CR4_OSFSXR:
1235
1236 /*
1237 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1238 */
1239 case FIX_NO_FXSAVE_JMP:
1240 {
1241 uint32_t offTrg = *u.pu32++;
1242 Assert(offTrg < pSwitcher->cbCode);
1243 if (!CPUMSupportsFXSR(pVM))
1244 {
1245 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1246 *uSrc.pu32++ = offTrg - (offSrc + 5);
1247 }
1248 else
1249 {
1250 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1251 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1252 }
1253 break;
1254 }
1255
1256 /*
1257 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1258 */
1259 case FIX_NO_SYSENTER_JMP:
1260 {
1261 uint32_t offTrg = *u.pu32++;
1262 Assert(offTrg < pSwitcher->cbCode);
1263 if (!CPUMIsHostUsingSysEnter(pVM))
1264 {
1265 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1266 *uSrc.pu32++ = offTrg - (offSrc + 5);
1267 }
1268 else
1269 {
1270 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1271 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1272 }
1273 break;
1274 }
1275
1276 /*
1277 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1278 */
1279 case FIX_NO_SYSCALL_JMP:
1280 {
1281 uint32_t offTrg = *u.pu32++;
1282 Assert(offTrg < pSwitcher->cbCode);
1283 if (!CPUMIsHostUsingSysEnter(pVM))
1284 {
1285 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1286 *uSrc.pu32++ = offTrg - (offSrc + 5);
1287 }
1288 else
1289 {
1290 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1291 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1292 }
1293 break;
1294 }
1295
1296 /*
1297 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1298 */
1299 case FIX_HC_32BIT:
1300 {
1301 uint32_t offTrg = *u.pu32++;
1302 Assert(offSrc < pSwitcher->cbCode);
1303 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1304 *uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1305 break;
1306 }
1307
1308#if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1309 /*
1310 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1311 */
1312 case FIX_HC_64BIT:
1313 {
1314 uint32_t offTrg = *u.pu32++;
1315 Assert(offSrc < pSwitcher->cbCode);
1316 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1317 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1318 break;
1319 }
1320
1321 /*
1322 * 64-bit HC Code Selector (no argument).
1323 */
1324 case FIX_HC_64BIT_CS:
1325 {
1326 Assert(offSrc < pSwitcher->cbCode);
1327#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1328 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
1329#else
1330 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1331#endif
1332 break;
1333 }
1334
1335 /*
1336 * 64-bit HC pointer to the CPUM instance data (no argument).
1337 */
1338 case FIX_HC_64BIT_CPUM:
1339 {
1340 Assert(offSrc < pSwitcher->cbCode);
1341 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1342 break;
1343 }
1344#endif
1345
1346 /*
1347 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1348 */
1349 case FIX_ID_32BIT:
1350 {
1351 uint32_t offTrg = *u.pu32++;
1352 Assert(offSrc < pSwitcher->cbCode);
1353 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1354 *uSrc.pu32 = u32IDCode + offTrg;
1355 break;
1356 }
1357
1358 /*
1359 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1360 */
1361 case FIX_ID_64BIT:
1362 {
1363 uint32_t offTrg = *u.pu32++;
1364 Assert(offSrc < pSwitcher->cbCode);
1365 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1366 *uSrc.pu64 = u32IDCode + offTrg;
1367 break;
1368 }
1369
1370 /*
1371 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1372 */
1373 case FIX_ID_FAR32_TO_64BIT_MODE:
1374 {
1375 uint32_t offTrg = *u.pu32++;
1376 Assert(offSrc < pSwitcher->cbCode);
1377 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1378 *uSrc.pu32++ = u32IDCode + offTrg;
1379 *uSrc.pu16 = SelCS64;
1380 AssertRelease(SelCS64);
1381 break;
1382 }
1383
1384#ifdef VBOX_WITH_NMI
1385 /*
1386 * 32-bit address to the APIC base.
1387 */
1388 case FIX_GC_APIC_BASE_32BIT:
1389 {
1390 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1391 break;
1392 }
1393#endif
1394
1395 default:
1396 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1397 break;
1398 }
1399 }
1400
1401#ifdef LOG_ENABLED
1402 /*
1403 * If Log2 is enabled disassemble the switcher code.
1404 *
1405 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1406 */
1407 if (LogIs2Enabled())
1408 {
1409 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1410 " pu8CodeR0 = %p\n"
1411 " pu8CodeR3 = %p\n"
1412 " GCPtrCode = %VGv\n"
1413 " u32IDCode = %08x\n"
1414 " pVMGC = %VGv\n"
1415 " pCPUMGC = %VGv\n"
1416 " pVMHC = %p\n"
1417 " pCPUMHC = %p\n"
1418 " GCPtrGDT = %VGv\n"
1419 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1420 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1421 " SelCS = %04x\n"
1422 " SelDS = %04x\n"
1423 " SelCS64 = %04x\n"
1424 " SelTSS = %04x\n",
1425 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1426 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1427 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1428 GCPtrGDT,
1429 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1430 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1431 SelCS, SelDS, SelCS64, SelTSS);
1432
1433 uint32_t offCode = 0;
1434 while (offCode < pSwitcher->cbCode)
1435 {
1436 /*
1437 * Figure out where this is.
1438 */
1439 const char *pszDesc = NULL;
1440 RTUINTPTR uBase;
1441 uint32_t cbCode;
1442 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1443 {
1444 pszDesc = "HCCode0";
1445 uBase = (RTUINTPTR)pu8CodeR0;
1446 offCode = pSwitcher->offHCCode0;
1447 cbCode = pSwitcher->cbHCCode0;
1448 }
1449 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1450 {
1451 pszDesc = "HCCode1";
1452 uBase = (RTUINTPTR)pu8CodeR0;
1453 offCode = pSwitcher->offHCCode1;
1454 cbCode = pSwitcher->cbHCCode1;
1455 }
1456 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1457 {
1458 pszDesc = "GCCode";
1459 uBase = GCPtrCode;
1460 offCode = pSwitcher->offGCCode;
1461 cbCode = pSwitcher->cbGCCode;
1462 }
1463 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1464 {
1465 pszDesc = "IDCode0";
1466 uBase = u32IDCode;
1467 offCode = pSwitcher->offIDCode0;
1468 cbCode = pSwitcher->cbIDCode0;
1469 }
1470 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1471 {
1472 pszDesc = "IDCode1";
1473 uBase = u32IDCode;
1474 offCode = pSwitcher->offIDCode1;
1475 cbCode = pSwitcher->cbIDCode1;
1476 }
1477 else
1478 {
1479 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1480 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1481 offCode++;
1482 continue;
1483 }
1484
1485 /*
1486 * Disassemble it.
1487 */
1488 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1489 DISCPUSTATE Cpu;
1490
1491 memset(&Cpu, 0, sizeof(Cpu));
1492 Cpu.mode = CPUMODE_32BIT;
1493 while (cbCode > 0)
1494 {
1495 /* try label it */
1496 if (pSwitcher->offR0HostToGuest == offCode)
1497 RTLogPrintf(" *R0HostToGuest:\n");
1498 if (pSwitcher->offGCGuestToHost == offCode)
1499 RTLogPrintf(" *GCGuestToHost:\n");
1500 if (pSwitcher->offGCCallTrampoline == offCode)
1501 RTLogPrintf(" *GCCallTrampoline:\n");
1502 if (pSwitcher->offGCGuestToHostAsm == offCode)
1503 RTLogPrintf(" *GCGuestToHostAsm:\n");
1504 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1505 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1506 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1507 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1508
1509 /* disas */
1510 uint32_t cbInstr = 0;
1511 char szDisas[256];
1512 if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
1513 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1514 else
1515 {
1516 RTLogPrintf(" %04x: %02x '%c'\n",
1517 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1518 cbInstr = 1;
1519 }
1520 offCode += cbInstr;
1521 cbCode -= RT_MIN(cbInstr, cbCode);
1522 }
1523 }
1524 }
1525#endif
1526}
1527
1528
1529/**
1530 * Relocator for the 32-Bit to 32-Bit world switcher.
1531 */
1532DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1533{
1534 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1535 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1536}
1537
1538
1539/**
1540 * Relocator for the 32-Bit to PAE world switcher.
1541 */
1542DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1543{
1544 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1545 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1546}
1547
1548
1549/**
1550 * Relocator for the PAE to 32-Bit world switcher.
1551 */
1552DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1553{
1554 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1555 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1556}
1557
1558
1559/**
1560 * Relocator for the PAE to PAE world switcher.
1561 */
1562DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1563{
1564 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1565 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1566}
1567
1568
1569/**
1570 * Relocator for the AMD64 to PAE world switcher.
1571 */
1572DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1573{
1574 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1575 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1576}
1577
1578
1579/**
1580 * Gets the pointer to g_szRTAssertMsg1 in GC.
1581 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1582 * Returns NULL if not present.
1583 * @param pVM The VM handle.
1584 */
1585VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1586{
1587 RTGCPTR32 GCPtr;
1588 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1589 if (VBOX_SUCCESS(rc))
1590 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1591 return NULL;
1592}
1593
1594
1595/**
1596 * Gets the pointer to g_szRTAssertMsg2 in GC.
1597 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1598 * Returns NULL if not present.
1599 * @param pVM The VM handle.
1600 */
1601VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1602{
1603 RTGCPTR32 GCPtr;
1604 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1605 if (VBOX_SUCCESS(rc))
1606 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1607 return NULL;
1608}
1609
1610
1611/**
1612 * Execute state save operation.
1613 *
1614 * @returns VBox status code.
1615 * @param pVM VM Handle.
1616 * @param pSSM SSM operation handle.
1617 */
1618static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1619{
1620 LogFlow(("vmmR3Save:\n"));
1621
1622 /*
1623 * The hypervisor stack.
1624 */
1625 SSMR3PutRCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1626 RTRCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1627 AssertMsg(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE, ("Bottom %VGv ESP=%VGv\n", pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1628 SSMR3PutRCPtr(pSSM, GCPtrESP);
1629 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1630 return SSMR3PutU32(pSSM, ~0); /* terminator */
1631}
1632
1633
1634/**
1635 * Execute state load operation.
1636 *
1637 * @returns VBox status code.
1638 * @param pVM VM Handle.
1639 * @param pSSM SSM operation handle.
1640 * @param u32Version Data layout version.
1641 */
1642static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1643{
1644 LogFlow(("vmmR3Load:\n"));
1645
1646 /*
1647 * Validate version.
1648 */
1649 if (u32Version != VMM_SAVED_STATE_VERSION)
1650 {
1651 AssertMsgFailed(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1652 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1653 }
1654
1655 /*
1656 * Check that the stack is in the same place, or that it's fearly empty.
1657 */
1658 RTRCPTR GCPtrStackBottom;
1659 SSMR3GetRCPtr(pSSM, &GCPtrStackBottom);
1660 RTRCPTR GCPtrESP;
1661 int rc = SSMR3GetRCPtr(pSSM, &GCPtrESP);
1662 if (VBOX_FAILURE(rc))
1663 return rc;
1664
1665 /* Previously we checked if the location of the stack was identical or that the stack was empty.
1666 * This is not required as we can never initiate a save when GC context code performs a ring 3 call.
1667 */
1668 /* restore the stack. (not necessary; just consistency checking) */
1669 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1670
1671 /* terminator */
1672 uint32_t u32;
1673 rc = SSMR3GetU32(pSSM, &u32);
1674 if (VBOX_FAILURE(rc))
1675 return rc;
1676 if (u32 != ~0U)
1677 {
1678 AssertMsgFailed(("u32=%#x\n", u32));
1679 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1680 }
1681 return VINF_SUCCESS;
1682}
1683
1684
1685/**
1686 * Selects the switcher to be used for switching to GC.
1687 *
1688 * @returns VBox status code.
1689 * @param pVM VM handle.
1690 * @param enmSwitcher The new switcher.
1691 * @remark This function may be called before the VMM is initialized.
1692 */
1693VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1694{
1695 /*
1696 * Validate input.
1697 */
1698 if ( enmSwitcher < VMMSWITCHER_INVALID
1699 || enmSwitcher >= VMMSWITCHER_MAX)
1700 {
1701 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1702 return VERR_INVALID_PARAMETER;
1703 }
1704
1705 /* Do nothing if the switcher is disabled. */
1706 if (pVM->vmm.s.fSwitcherDisabled)
1707 return VINF_SUCCESS;
1708
1709 /*
1710 * Select the new switcher.
1711 */
1712 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1713 if (pSwitcher)
1714 {
1715 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1716 pVM->vmm.s.enmSwitcher = enmSwitcher;
1717
1718 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1719 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1720
1721 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1722 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1723 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1724 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1725 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1726 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1727 return VINF_SUCCESS;
1728 }
1729 return VERR_NOT_IMPLEMENTED;
1730}
1731
1732/**
1733 * Disable the switcher logic permanently.
1734 *
1735 * @returns VBox status code.
1736 * @param pVM VM handle.
1737 */
1738VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1739{
1740/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1741 * @code
1742 * mov eax, VERR_INTERNAL_ERROR
1743 * ret
1744 * @endcode
1745 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1746 */
1747 pVM->vmm.s.fSwitcherDisabled = true;
1748 return VINF_SUCCESS;
1749}
1750
1751
1752/**
1753 * Resolve a builtin GC symbol.
1754 * Called by PDM when loading or relocating GC modules.
1755 *
1756 * @returns VBox status
1757 * @param pVM VM Handle.
1758 * @param pszSymbol Symbol to resolv
1759 * @param pGCPtrValue Where to store the symbol value.
1760 * @remark This has to work before VMMR3Relocate() is called.
1761 */
1762VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1763{
1764 if (!strcmp(pszSymbol, "g_Logger"))
1765 {
1766 if (pVM->vmm.s.pLoggerHC)
1767 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1768 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1769 }
1770 else if (!strcmp(pszSymbol, "g_RelLogger"))
1771 {
1772#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1773 if (pVM->vmm.s.pRelLoggerHC)
1774 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1775 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1776#else
1777 *pGCPtrValue = NIL_RTGCPTR;
1778#endif
1779 }
1780 else
1781 return VERR_SYMBOL_NOT_FOUND;
1782 return VINF_SUCCESS;
1783}
1784
1785
1786/**
1787 * Suspends the the CPU yielder.
1788 *
1789 * @param pVM The VM handle.
1790 */
1791VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1792{
1793 if (!pVM->vmm.s.cYieldResumeMillies)
1794 {
1795 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1796 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1797 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1798 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1799 else
1800 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1801 TMTimerStop(pVM->vmm.s.pYieldTimer);
1802 }
1803 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1804}
1805
1806
1807/**
1808 * Stops the the CPU yielder.
1809 *
1810 * @param pVM The VM handle.
1811 */
1812VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1813{
1814 if (!pVM->vmm.s.cYieldResumeMillies)
1815 TMTimerStop(pVM->vmm.s.pYieldTimer);
1816 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1817 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1818}
1819
1820
1821/**
1822 * Resumes the CPU yielder when it has been a suspended or stopped.
1823 *
1824 * @param pVM The VM handle.
1825 */
1826VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1827{
1828 if (pVM->vmm.s.cYieldResumeMillies)
1829 {
1830 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1831 pVM->vmm.s.cYieldResumeMillies = 0;
1832 }
1833}
1834
1835
1836/**
1837 * Internal timer callback function.
1838 *
1839 * @param pVM The VM.
1840 * @param pTimer The timer handle.
1841 * @param pvUser User argument specified upon timer creation.
1842 */
1843static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1844{
1845 /*
1846 * This really needs some careful tuning. While we shouldn't be too gready since
1847 * that'll cause the rest of the system to stop up, we shouldn't be too nice either
1848 * because that'll cause us to stop up.
1849 *
1850 * The current logic is to use the default interval when there is no lag worth
1851 * mentioning, but when we start accumulating lag we don't bother yielding at all.
1852 *
1853 * (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1854 * so the lag is up to date.)
1855 */
1856 const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1857 if ( u64Lag < 50000000 /* 50ms */
1858 || ( u64Lag < 1000000000 /* 1s */
1859 && RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1860 )
1861 {
1862 uint64_t u64Elapsed = RTTimeNanoTS();
1863 pVM->vmm.s.u64LastYield = u64Elapsed;
1864
1865 RTThreadYield();
1866
1867#ifdef LOG_ENABLED
1868 u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1869 Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1870#endif
1871 }
1872 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1873}
1874
1875
1876/**
1877 * Acquire global VM lock.
1878 *
1879 * @returns VBox status code
1880 * @param pVM The VM to operate on.
1881 */
1882VMMR3DECL(int) VMMR3Lock(PVM pVM)
1883{
1884 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1885}
1886
1887
1888/**
1889 * Release global VM lock.
1890 *
1891 * @returns VBox status code
1892 * @param pVM The VM to operate on.
1893 */
1894VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1895{
1896 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1897}
1898
1899
1900/**
1901 * Return global VM lock owner.
1902 *
1903 * @returns Thread id of owner.
1904 * @returns NIL_RTTHREAD if no owner.
1905 * @param pVM The VM to operate on.
1906 */
1907VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1908{
1909 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1910}
1911
1912
1913/**
1914 * Checks if the current thread is the owner of the global VM lock.
1915 *
1916 * @returns true if owner.
1917 * @returns false if not owner.
1918 * @param pVM The VM to operate on.
1919 */
1920VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1921{
1922 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1923}
1924
1925
1926/**
1927 * Executes guest code.
1928 *
1929 * @param pVM VM handle.
1930 */
1931VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1932{
1933 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1934
1935 /*
1936 * Set the EIP and ESP.
1937 */
1938 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1939 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1940 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1941 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1942
1943 /*
1944 * We hide log flushes (outer) and hypervisor interrupts (inner).
1945 */
1946 for (;;)
1947 {
1948 int rc;
1949 do
1950 {
1951#ifdef NO_SUPCALLR0VMM
1952 rc = VERR_GENERAL_FAILURE;
1953#else
1954 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
1955 if (RT_LIKELY(rc == VINF_SUCCESS))
1956 rc = pVM->vmm.s.iLastGCRc;
1957#endif
1958 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1959
1960 /*
1961 * Flush the logs.
1962 */
1963#ifdef LOG_ENABLED
1964 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
1965 if ( pLogger
1966 && pLogger->offScratch > 0)
1967 RTLogFlushGC(NULL, pLogger);
1968#endif
1969#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1970 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1971 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1972 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1973#endif
1974 if (rc != VINF_VMM_CALL_HOST)
1975 {
1976 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1977 return rc;
1978 }
1979 rc = vmmR3ServiceCallHostRequest(pVM);
1980 if (VBOX_FAILURE(rc))
1981 return rc;
1982 /* Resume GC */
1983 }
1984}
1985
1986
1987/**
1988 * Executes guest code (Intel VT-x and AMD-V).
1989 *
1990 * @param pVM VM handle.
1991 */
1992VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1993{
1994 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1995
1996 for (;;)
1997 {
1998 int rc;
1999 do
2000 {
2001#ifdef NO_SUPCALLR0VMM
2002 rc = VERR_GENERAL_FAILURE;
2003#else
2004 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN);
2005 if (RT_LIKELY(rc == VINF_SUCCESS))
2006 rc = pVM->vmm.s.iLastGCRc;
2007#endif
2008 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2009
2010#ifdef LOG_ENABLED
2011 /*
2012 * Flush the log
2013 */
2014 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
2015 if ( pR0Logger
2016 && pR0Logger->Logger.offScratch > 0)
2017 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
2018#endif /* !LOG_ENABLED */
2019 if (rc != VINF_VMM_CALL_HOST)
2020 {
2021 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2022 return rc;
2023 }
2024 rc = vmmR3ServiceCallHostRequest(pVM);
2025 if (VBOX_FAILURE(rc) || rc == VINF_EM_DBG_HYPER_ASSERTION)
2026 return rc;
2027 /* Resume R0 */
2028 }
2029}
2030
2031/**
2032 * Calls GC a function.
2033 *
2034 * @param pVM The VM handle.
2035 * @param GCPtrEntry The GC function address.
2036 * @param cArgs The number of arguments in the ....
2037 * @param ... Arguments to the function.
2038 */
2039VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, ...)
2040{
2041 va_list args;
2042 va_start(args, cArgs);
2043 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
2044 va_end(args);
2045 return rc;
2046}
2047
2048
2049/**
2050 * Calls GC a function.
2051 *
2052 * @param pVM The VM handle.
2053 * @param GCPtrEntry The GC function address.
2054 * @param cArgs The number of arguments in the ....
2055 * @param args Arguments to the function.
2056 */
2057VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, va_list args)
2058{
2059 Log2(("VMMR3CallGCV: GCPtrEntry=%VRv cArgs=%d\n", GCPtrEntry, cArgs));
2060
2061 /*
2062 * Setup the call frame using the trampoline.
2063 */
2064 CPUMHyperSetCtxCore(pVM, NULL);
2065 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2066 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR32));
2067 PRTGCUINTPTR32 pFrame = (PRTGCUINTPTR32)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
2068 int i = cArgs;
2069 while (i-- > 0)
2070 *pFrame++ = va_arg(args, RTGCUINTPTR32);
2071
2072 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR32)); /* stack frame size */
2073 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2074 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2075
2076 /*
2077 * We hide log flushes (outer) and hypervisor interrupts (inner).
2078 */
2079 for (;;)
2080 {
2081 int rc;
2082 do
2083 {
2084#ifdef NO_SUPCALLR0VMM
2085 rc = VERR_GENERAL_FAILURE;
2086#else
2087 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2088 if (RT_LIKELY(rc == VINF_SUCCESS))
2089 rc = pVM->vmm.s.iLastGCRc;
2090#endif
2091 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2092
2093 /*
2094 * Flush the logs.
2095 */
2096#ifdef LOG_ENABLED
2097 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
2098 if ( pLogger
2099 && pLogger->offScratch > 0)
2100 RTLogFlushGC(NULL, pLogger);
2101#endif
2102#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2103 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2104 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2105 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2106#endif
2107 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2108 VMMR3FatalDump(pVM, rc);
2109 if (rc != VINF_VMM_CALL_HOST)
2110 {
2111 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2112 return rc;
2113 }
2114 rc = vmmR3ServiceCallHostRequest(pVM);
2115 if (VBOX_FAILURE(rc))
2116 return rc;
2117 }
2118}
2119
2120
2121/**
2122 * Resumes executing hypervisor code when interrupted
2123 * by a queue flush or a debug event.
2124 *
2125 * @returns VBox status code.
2126 * @param pVM VM handle.
2127 */
2128VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2129{
2130 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2131
2132 /*
2133 * We hide log flushes (outer) and hypervisor interrupts (inner).
2134 */
2135 for (;;)
2136 {
2137 int rc;
2138 do
2139 {
2140#ifdef NO_SUPCALLR0VMM
2141 rc = VERR_GENERAL_FAILURE;
2142#else
2143 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2144 if (RT_LIKELY(rc == VINF_SUCCESS))
2145 rc = pVM->vmm.s.iLastGCRc;
2146#endif
2147 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2148
2149 /*
2150 * Flush the loggers,
2151 */
2152#ifdef LOG_ENABLED
2153 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
2154 if ( pLogger
2155 && pLogger->offScratch > 0)
2156 RTLogFlushGC(NULL, pLogger);
2157#endif
2158#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2159 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2160 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2161 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2162#endif
2163 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2164 VMMR3FatalDump(pVM, rc);
2165 if (rc != VINF_VMM_CALL_HOST)
2166 {
2167 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2168 return rc;
2169 }
2170 rc = vmmR3ServiceCallHostRequest(pVM);
2171 if (VBOX_FAILURE(rc))
2172 return rc;
2173 }
2174}
2175
2176
2177/**
2178 * Service a call to the ring-3 host code.
2179 *
2180 * @returns VBox status code.
2181 * @param pVM VM handle.
2182 * @remark Careful with critsects.
2183 */
2184static int vmmR3ServiceCallHostRequest(PVM pVM)
2185{
2186 switch (pVM->vmm.s.enmCallHostOperation)
2187 {
2188 /*
2189 * Acquire the PDM lock.
2190 */
2191 case VMMCALLHOST_PDM_LOCK:
2192 {
2193 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2194 break;
2195 }
2196
2197 /*
2198 * Flush a PDM queue.
2199 */
2200 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2201 {
2202 PDMR3QueueFlushWorker(pVM, NULL);
2203 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2204 break;
2205 }
2206
2207 /*
2208 * Grow the PGM pool.
2209 */
2210 case VMMCALLHOST_PGM_POOL_GROW:
2211 {
2212 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2213 break;
2214 }
2215
2216 /*
2217 * Maps an page allocation chunk into ring-3 so ring-0 can use it.
2218 */
2219 case VMMCALLHOST_PGM_MAP_CHUNK:
2220 {
2221 pVM->vmm.s.rcCallHost = PGMR3PhysChunkMap(pVM, pVM->vmm.s.u64CallHostArg);
2222 break;
2223 }
2224
2225 /*
2226 * Allocates more handy pages.
2227 */
2228 case VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES:
2229 {
2230 pVM->vmm.s.rcCallHost = PGMR3PhysAllocateHandyPages(pVM);
2231 break;
2232 }
2233#ifndef VBOX_WITH_NEW_PHYS_CODE
2234
2235 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2236 {
2237 const RTGCPHYS GCPhys = pVM->vmm.s.u64CallHostArg;
2238 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, &GCPhys);
2239 break;
2240 }
2241#endif
2242
2243 /*
2244 * Acquire the PGM lock.
2245 */
2246 case VMMCALLHOST_PGM_LOCK:
2247 {
2248 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2249 break;
2250 }
2251
2252 /*
2253 * Flush REM handler notifications.
2254 */
2255 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2256 {
2257 REMR3ReplayHandlerNotifications(pVM);
2258 break;
2259 }
2260
2261 /*
2262 * This is a noop. We just take this route to avoid unnecessary
2263 * tests in the loops.
2264 */
2265 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2266 break;
2267
2268 /*
2269 * Set the VM error message.
2270 */
2271 case VMMCALLHOST_VM_SET_ERROR:
2272 VMR3SetErrorWorker(pVM);
2273 break;
2274
2275 /*
2276 * Set the VM runtime error message.
2277 */
2278 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2279 VMR3SetRuntimeErrorWorker(pVM);
2280 break;
2281
2282 /*
2283 * Signal a ring 0 hypervisor assertion.
2284 * Cancel the longjmp operation that's in progress.
2285 */
2286 case VMMCALLHOST_VM_R0_HYPER_ASSERTION:
2287 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2288 pVM->vmm.s.CallHostR0JmpBuf.fInRing3Call = false;
2289#ifdef RT_ARCH_X86
2290 pVM->vmm.s.CallHostR0JmpBuf.eip = 0;
2291#else
2292 pVM->vmm.s.CallHostR0JmpBuf.rip = 0;
2293#endif
2294 LogRel((pVM->vmm.s.szRing0AssertMsg1));
2295 LogRel((pVM->vmm.s.szRing0AssertMsg2));
2296 return VINF_EM_DBG_HYPER_ASSERTION;
2297
2298 default:
2299 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2300 return VERR_INTERNAL_ERROR;
2301 }
2302
2303 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2304 return VINF_SUCCESS;
2305}
2306
2307
2308
2309/**
2310 * Structure to pass to DBGFR3Info() and for doing all other
2311 * output during fatal dump.
2312 */
2313typedef struct VMMR3FATALDUMPINFOHLP
2314{
2315 /** The helper core. */
2316 DBGFINFOHLP Core;
2317 /** The release logger instance. */
2318 PRTLOGGER pRelLogger;
2319 /** The saved release logger flags. */
2320 RTUINT fRelLoggerFlags;
2321 /** The logger instance. */
2322 PRTLOGGER pLogger;
2323 /** The saved logger flags. */
2324 RTUINT fLoggerFlags;
2325 /** The saved logger destination flags. */
2326 RTUINT fLoggerDestFlags;
2327 /** Whether to output to stderr or not. */
2328 bool fStdErr;
2329} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2330typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2331
2332
2333/**
2334 * Print formatted string.
2335 *
2336 * @param pHlp Pointer to this structure.
2337 * @param pszFormat The format string.
2338 * @param ... Arguments.
2339 */
2340static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2341{
2342 va_list args;
2343 va_start(args, pszFormat);
2344 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2345 va_end(args);
2346}
2347
2348
2349/**
2350 * Print formatted string.
2351 *
2352 * @param pHlp Pointer to this structure.
2353 * @param pszFormat The format string.
2354 * @param args Argument list.
2355 */
2356static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2357{
2358 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2359
2360 if (pMyHlp->pRelLogger)
2361 {
2362 va_list args2;
2363 va_copy(args2, args);
2364 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2365 va_end(args2);
2366 }
2367 if (pMyHlp->pLogger)
2368 {
2369 va_list args2;
2370 va_copy(args2, args);
2371 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2372 va_end(args2);
2373 }
2374 if (pMyHlp->fStdErr)
2375 {
2376 va_list args2;
2377 va_copy(args2, args);
2378 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2379 va_end(args2);
2380 }
2381}
2382
2383
2384/**
2385 * Initializes the fatal dump output helper.
2386 *
2387 * @param pHlp The structure to initialize.
2388 */
2389static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2390{
2391 memset(pHlp, 0, sizeof(*pHlp));
2392
2393 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2394 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2395
2396 /*
2397 * The loggers.
2398 */
2399 pHlp->pRelLogger = RTLogRelDefaultInstance();
2400#ifndef LOG_ENABLED
2401 if (!pHlp->pRelLogger)
2402#endif
2403 pHlp->pLogger = RTLogDefaultInstance();
2404
2405 if (pHlp->pRelLogger)
2406 {
2407 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2408 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2409 }
2410
2411 if (pHlp->pLogger)
2412 {
2413 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2414 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2415 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2416#ifndef DEBUG_sandervl
2417 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2418#endif
2419 }
2420
2421 /*
2422 * Check if we need write to stderr.
2423 */
2424#ifdef DEBUG_sandervl
2425 pHlp->fStdErr = false; /* takes too long to display here */
2426#else
2427 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2428 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2429#endif
2430}
2431
2432
2433/**
2434 * Deletes the fatal dump output helper.
2435 *
2436 * @param pHlp The structure to delete.
2437 */
2438static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2439{
2440 if (pHlp->pRelLogger)
2441 {
2442 RTLogFlush(pHlp->pRelLogger);
2443 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2444 }
2445
2446 if (pHlp->pLogger)
2447 {
2448 RTLogFlush(pHlp->pLogger);
2449 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2450 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2451 }
2452}
2453
2454
2455/**
2456 * Dumps the VM state on a fatal error.
2457 *
2458 * @param pVM VM Handle.
2459 * @param rcErr VBox status code.
2460 */
2461VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2462{
2463 /*
2464 * Create our output helper and sync it with the log settings.
2465 * This helper will be used for all the output.
2466 */
2467 VMMR3FATALDUMPINFOHLP Hlp;
2468 PCDBGFINFOHLP pHlp = &Hlp.Core;
2469 vmmR3FatalDumpInfoHlpInit(&Hlp);
2470
2471 /*
2472 * Header.
2473 */
2474 pHlp->pfnPrintf(pHlp,
2475 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2476 "!!\n"
2477 "!! Guru Meditation %d (%Vrc)\n"
2478 "!!\n",
2479 rcErr, rcErr);
2480
2481 /*
2482 * Continue according to context.
2483 */
2484 bool fDoneHyper = false;
2485 switch (rcErr)
2486 {
2487 /*
2488 * Hypervisor errors.
2489 */
2490 case VINF_EM_DBG_HYPER_ASSERTION:
2491 {
2492 const char *pszMsg1 = HWACCMR3IsActive(pVM) ? pVM->vmm.s.szRing0AssertMsg1 : VMMR3GetGCAssertMsg1(pVM);
2493 while (pszMsg1 && *pszMsg1 == '\n')
2494 pszMsg1++;
2495 const char *pszMsg2 = HWACCMR3IsActive(pVM) ? pVM->vmm.s.szRing0AssertMsg2 : VMMR3GetGCAssertMsg2(pVM);
2496 while (pszMsg2 && *pszMsg2 == '\n')
2497 pszMsg2++;
2498 pHlp->pfnPrintf(pHlp,
2499 "%s"
2500 "%s",
2501 pszMsg1,
2502 pszMsg2);
2503 if ( !pszMsg2
2504 || !*pszMsg2
2505 || strchr(pszMsg2, '\0')[-1] != '\n')
2506 pHlp->pfnPrintf(pHlp, "\n");
2507 pHlp->pfnPrintf(pHlp, "!!\n");
2508 /* fall thru */
2509 }
2510 case VERR_TRPM_DONT_PANIC:
2511 case VERR_TRPM_PANIC:
2512 case VINF_EM_RAW_STALE_SELECTOR:
2513 case VINF_EM_RAW_IRET_TRAP:
2514 case VINF_EM_DBG_HYPER_BREAKPOINT:
2515 case VINF_EM_DBG_HYPER_STEPPED:
2516 {
2517 /*
2518 * Active trap? This is only of partial interest when in hardware
2519 * assisted virtualization mode, thus the different messages.
2520 */
2521 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2522 TRPMEVENT enmType;
2523 uint8_t u8TrapNo = 0xce;
2524 RTGCUINT uErrorCode = 0xdeadface;
2525 RTGCUINTPTR uCR2 = 0xdeadface;
2526 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
2527 if (!HWACCMR3IsActive(pVM))
2528 {
2529 if (RT_SUCCESS(rc2))
2530 pHlp->pfnPrintf(pHlp,
2531 "!! TRAP=%02x ERRCD=%RGv CR2=%RGv EIP=%RX32 Type=%d\n",
2532 u8TrapNo, uErrorCode, uCR2, uEIP, enmType);
2533 else
2534 pHlp->pfnPrintf(pHlp,
2535 "!! EIP=%RX32 NOTRAP\n",
2536 uEIP);
2537 }
2538 else if (RT_SUCCESS(rc2))
2539 pHlp->pfnPrintf(pHlp,
2540 "!! ACTIVE TRAP=%02x ERRCD=%RGv CR2=%RGv PC=%RGr Type=%d (Guest!)\n",
2541 u8TrapNo, uErrorCode, uCR2, CPUMGetGuestRIP(pVM), enmType);
2542
2543 /*
2544 * The hypervisor dump is not relevant when we're in VT-x/AMD-V mode.
2545 */
2546 if (HWACCMR3IsActive(pVM))
2547 pHlp->pfnPrintf(pHlp, "\n");
2548 else
2549 {
2550 /*
2551 * Try figure out where eip is.
2552 */
2553 /* core code? */
2554 if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2555 pHlp->pfnPrintf(pHlp,
2556 "!! EIP is in CoreCode, offset %#x\n",
2557 uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2558 else
2559 { /* ask PDM */ /** @todo ask DBGFR3Sym later? */
2560 char szModName[64];
2561 RTRCPTR RCPtrMod;
2562 char szNearSym1[260];
2563 RTRCPTR RCPtrNearSym1;
2564 char szNearSym2[260];
2565 RTRCPTR RCPtrNearSym2;
2566 int rc = PDMR3LdrQueryRCModFromPC(pVM, uEIP,
2567 &szModName[0], sizeof(szModName), &RCPtrMod,
2568 &szNearSym1[0], sizeof(szNearSym1), &RCPtrNearSym1,
2569 &szNearSym2[0], sizeof(szNearSym2), &RCPtrNearSym2);
2570 if (VBOX_SUCCESS(rc))
2571 pHlp->pfnPrintf(pHlp,
2572 "!! EIP in %s (%RRv) at rva %x near symbols:\n"
2573 "!! %RRv rva %RRv off %08x %s\n"
2574 "!! %RRv rva %RRv off -%08x %s\n",
2575 szModName, RCPtrMod, (unsigned)(uEIP - RCPtrMod),
2576 RCPtrNearSym1, RCPtrNearSym1 - RCPtrMod, (unsigned)(uEIP - RCPtrNearSym1), szNearSym1,
2577 RCPtrNearSym2, RCPtrNearSym2 - RCPtrMod, (unsigned)(RCPtrNearSym2 - uEIP), szNearSym2);
2578 else
2579 pHlp->pfnPrintf(pHlp,
2580 "!! EIP is not in any code known to VMM!\n");
2581 }
2582
2583 /* Disassemble the instruction. */
2584 char szInstr[256];
2585 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2586 if (VBOX_SUCCESS(rc2))
2587 pHlp->pfnPrintf(pHlp,
2588 "!! %s\n", szInstr);
2589
2590 /* Dump the hypervisor cpu state. */
2591 pHlp->pfnPrintf(pHlp,
2592 "!!\n"
2593 "!!\n"
2594 "!!\n");
2595 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2596 fDoneHyper = true;
2597
2598 /* Callstack. */
2599 DBGFSTACKFRAME Frame = {0};
2600 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2601 if (VBOX_SUCCESS(rc2))
2602 {
2603 pHlp->pfnPrintf(pHlp,
2604 "!!\n"
2605 "!! Call Stack:\n"
2606 "!!\n"
2607 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2608 do
2609 {
2610 pHlp->pfnPrintf(pHlp,
2611 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2612 (uint32_t)Frame.AddrFrame.off,
2613 (uint32_t)Frame.AddrReturnFrame.off,
2614 (uint32_t)Frame.AddrReturnPC.Sel,
2615 (uint32_t)Frame.AddrReturnPC.off,
2616 Frame.Args.au32[0],
2617 Frame.Args.au32[1],
2618 Frame.Args.au32[2],
2619 Frame.Args.au32[3]);
2620 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2621 if (Frame.pSymPC)
2622 {
2623 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2624 if (offDisp > 0)
2625 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2626 else if (offDisp < 0)
2627 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2628 else
2629 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2630 }
2631 if (Frame.pLinePC)
2632 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2633 pHlp->pfnPrintf(pHlp, "\n");
2634
2635 /* next */
2636 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2637 } while (VBOX_SUCCESS(rc2));
2638 DBGFR3StackWalkEnd(pVM, &Frame);
2639 }
2640
2641 /* raw stack */
2642 pHlp->pfnPrintf(pHlp,
2643 "!!\n"
2644 "!! Raw stack (mind the direction).\n"
2645 "!!\n"
2646 "%.*Vhxd\n",
2647 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2648 } /* !HWACCMR3IsActive */
2649 break;
2650 }
2651
2652 default:
2653 {
2654 break;
2655 }
2656
2657 } /* switch (rcErr) */
2658
2659
2660 /*
2661 * Generic info dumper loop.
2662 */
2663 static struct
2664 {
2665 const char *pszInfo;
2666 const char *pszArgs;
2667 } const aInfo[] =
2668 {
2669 { "mappings", NULL },
2670 { "hma", NULL },
2671 { "cpumguest", "verbose" },
2672 { "cpumguestinstr", "verbose" },
2673 { "cpumhyper", "verbose" },
2674 { "cpumhost", "verbose" },
2675 { "mode", "all" },
2676 { "cpuid", "verbose" },
2677 { "gdt", NULL },
2678 { "ldt", NULL },
2679 //{ "tss", NULL },
2680 { "ioport", NULL },
2681 { "mmio", NULL },
2682 { "phys", NULL },
2683 //{ "pgmpd", NULL }, - doesn't always work at init time...
2684 { "timers", NULL },
2685 { "activetimers", NULL },
2686 { "handlers", "phys virt hyper stats" },
2687 { "cfgm", NULL },
2688 };
2689 for (unsigned i = 0; i < RT_ELEMENTS(aInfo); i++)
2690 {
2691 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2692 continue;
2693 pHlp->pfnPrintf(pHlp,
2694 "!!\n"
2695 "!! {%s, %s}\n"
2696 "!!\n",
2697 aInfo[i].pszInfo, aInfo[i].pszArgs);
2698 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2699 }
2700
2701 /* done */
2702 pHlp->pfnPrintf(pHlp,
2703 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2704
2705
2706 /*
2707 * Delete the output instance (flushing and restoring of flags).
2708 */
2709 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2710}
2711
2712
2713
2714/**
2715 * Displays the Force action Flags.
2716 *
2717 * @param pVM The VM handle.
2718 * @param pHlp The output helpers.
2719 * @param pszArgs The additional arguments (ignored).
2720 */
2721static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2722{
2723 const uint32_t fForcedActions = pVM->fForcedActions;
2724
2725 pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2726
2727 /* show the flag mnemonics */
2728 int c = 0;
2729 uint32_t f = fForcedActions;
2730#define PRINT_FLAG(flag) do { \
2731 if (f & (flag)) \
2732 { \
2733 static const char *s_psz = #flag; \
2734 if (!(c % 6)) \
2735 pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2736 else \
2737 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2738 c++; \
2739 f &= ~(flag); \
2740 } \
2741 } while (0)
2742 PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2743 PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2744 PRINT_FLAG(VM_FF_TIMER);
2745 PRINT_FLAG(VM_FF_PDM_QUEUES);
2746 PRINT_FLAG(VM_FF_PDM_DMA);
2747 PRINT_FLAG(VM_FF_PDM_CRITSECT);
2748 PRINT_FLAG(VM_FF_DBGF);
2749 PRINT_FLAG(VM_FF_REQUEST);
2750 PRINT_FLAG(VM_FF_TERMINATE);
2751 PRINT_FLAG(VM_FF_RESET);
2752 PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2753 PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2754 PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2755 PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2756 PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2757 PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2758 PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2759 PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2760 PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2761 PRINT_FLAG(VM_FF_TO_R3);
2762 PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2763 if (f)
2764 pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2765 else
2766 pHlp->pfnPrintf(pHlp, "\n");
2767#undef PRINT_FLAG
2768
2769 /* the groups */
2770 c = 0;
2771#define PRINT_GROUP(grp) do { \
2772 if (fForcedActions & (grp)) \
2773 { \
2774 static const char *s_psz = #grp; \
2775 if (!(c % 5)) \
2776 pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2777 else \
2778 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2779 c++; \
2780 } \
2781 } while (0)
2782 PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2783 PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2784 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2785 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2786 PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2787 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2788 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2789 PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2790 PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2791 if (c)
2792 pHlp->pfnPrintf(pHlp, "\n");
2793#undef PRINT_GROUP
2794}
2795
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