VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 13782

Last change on this file since 13782 was 13778, checked in by vboxsync, 16 years ago

Per VCPU init/term.
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1/* $Id: VMM.cpp 13778 2008-11-04 09:45:27Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22//#define NO_SUPCALLR0VMM
23
24/** @page pg_vmm VMM - The Virtual Machine Monitor
25 *
26 * The VMM component is two things at the moment, it's a component doing a few
27 * management and routing tasks, and it's the whole virtual machine monitor
28 * thing. For hysterical reasons, it is not doing all the management that one
29 * would expect, this is instead done by @ref pg_vm. We'll address this
30 * misdesign eventually.
31 *
32 * @see grp_vmm, grp_vm
33 *
34 *
35 * @section sec_vmmstate VMM State
36 *
37 * @image html VM_Statechart_Diagram.gif
38 *
39 * To be written.
40 *
41 *
42 * @subsection subsec_vmm_init VMM Initialization
43 *
44 * To be written.
45 *
46 *
47 * @subsection subsec_vmm_term VMM Termination
48 *
49 * To be written.
50 *
51 */
52
53/*******************************************************************************
54* Header Files *
55*******************************************************************************/
56#define LOG_GROUP LOG_GROUP_VMM
57#include <VBox/vmm.h>
58#include <VBox/vmapi.h>
59#include <VBox/pgm.h>
60#include <VBox/cfgm.h>
61#include <VBox/pdmqueue.h>
62#include <VBox/pdmapi.h>
63#include <VBox/cpum.h>
64#include <VBox/mm.h>
65#include <VBox/iom.h>
66#include <VBox/trpm.h>
67#include <VBox/selm.h>
68#include <VBox/em.h>
69#include <VBox/sup.h>
70#include <VBox/dbgf.h>
71#include <VBox/csam.h>
72#include <VBox/patm.h>
73#include <VBox/rem.h>
74#include <VBox/ssm.h>
75#include <VBox/tm.h>
76#include "VMMInternal.h"
77#include "VMMSwitcher/VMMSwitcher.h"
78#include <VBox/vm.h>
79
80#include <VBox/err.h>
81#include <VBox/param.h>
82#include <VBox/version.h>
83#include <VBox/x86.h>
84#include <VBox/hwaccm.h>
85#include <iprt/assert.h>
86#include <iprt/alloc.h>
87#include <iprt/asm.h>
88#include <iprt/time.h>
89#include <iprt/stream.h>
90#include <iprt/string.h>
91#include <iprt/stdarg.h>
92#include <iprt/ctype.h>
93
94
95
96/** The saved state version. */
97#define VMM_SAVED_STATE_VERSION 3
98
99
100/*******************************************************************************
101* Global Variables *
102*******************************************************************************/
103/** Array of switcher defininitions.
104 * The type and index shall match!
105 */
106static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
107{
108 NULL, /* invalid entry */
109#ifndef RT_ARCH_AMD64
110 &vmmR3Switcher32BitTo32Bit_Def,
111 &vmmR3Switcher32BitToPAE_Def,
112 NULL, //&vmmR3Switcher32BitToAMD64_Def,
113 &vmmR3SwitcherPAETo32Bit_Def,
114 &vmmR3SwitcherPAEToPAE_Def,
115 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
116# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
117 &vmmR3SwitcherAMD64ToPAE_Def,
118# else
119 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
120# endif
121 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
122#else /* RT_ARCH_AMD64 */
123 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
124 NULL, //&vmmR3Switcher32BitToPAE_Def,
125 NULL, //&vmmR3Switcher32BitToAMD64_Def,
126 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
127 NULL, //&vmmR3SwitcherPAEToPAE_Def,
128 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
129 &vmmR3SwitcherAMD64ToPAE_Def,
130 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
131#endif /* RT_ARCH_AMD64 */
132};
133
134
135/*******************************************************************************
136* Internal Functions *
137*******************************************************************************/
138static int vmmR3InitCoreCode(PVM pVM);
139static int vmmR3InitStacks(PVM pVM);
140static int vmmR3InitLoggers(PVM pVM);
141static void vmmR3InitRegisterStats(PVM pVM);
142static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
143static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
144static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
145static int vmmR3ServiceCallHostRequest(PVM pVM);
146static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
147
148
149/**
150 * Initializes the VMM.
151 *
152 * @returns VBox status code.
153 * @param pVM The VM to operate on.
154 */
155VMMR3DECL(int) VMMR3Init(PVM pVM)
156{
157 LogFlow(("VMMR3Init\n"));
158
159 /*
160 * Assert alignment, sizes and order.
161 */
162 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
163 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
164 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
165 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
166
167 /*
168 * Init basic VM VMM members.
169 */
170 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
171 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
172 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
173 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
174 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
175 else
176 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
177
178 /* GC switchers are enabled by default. Turned off by HWACCM. */
179 pVM->vmm.s.fSwitcherDisabled = false;
180
181 /*
182 * Register the saved state data unit.
183 */
184 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
185 NULL, vmmR3Save, NULL,
186 NULL, vmmR3Load, NULL);
187 if (VBOX_FAILURE(rc))
188 return rc;
189
190 /*
191 * Register the Ring-0 VM handle with the session for fast ioctl calls.
192 */
193 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
194 if (VBOX_FAILURE(rc))
195 return rc;
196
197 /*
198 * Init various sub-components.
199 */
200 rc = vmmR3InitCoreCode(pVM);
201 if (RT_SUCCESS(rc))
202 {
203 rc = vmmR3InitStacks(pVM);
204 if (RT_SUCCESS(rc))
205 {
206 rc = vmmR3InitLoggers(pVM);
207
208#ifdef VBOX_WITH_NMI
209 /*
210 * Allocate mapping for the host APIC.
211 */
212 if (RT_SUCCESS(rc))
213 {
214 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
215 AssertRC(rc);
216 }
217#endif
218 if (RT_SUCCESS(rc))
219 {
220 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
221 if (VBOX_SUCCESS(rc))
222 {
223 /*
224 * Debug info and statistics.
225 */
226 DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
227 vmmR3InitRegisterStats(pVM);
228
229 return VINF_SUCCESS;
230 }
231 }
232 }
233 /** @todo: Need failure cleanup. */
234
235 //more todo in here?
236 //if (VBOX_SUCCESS(rc))
237 //{
238 //}
239 //int rc2 = vmmR3TermCoreCode(pVM);
240 //AssertRC(rc2));
241 }
242
243 return rc;
244}
245
246
247/**
248 * Initializes the per-VCPU VMM.
249 *
250 * @returns VBox status code.
251 * @param pVM The VM to operate on.
252 */
253VMMR3DECL(int) VMMR3InitCPU(PVM pVM)
254{
255 LogFlow(("VMMR3InitCPU\n"));
256 return VINF_SUCCESS;
257}
258
259/**
260 * VMMR3Init worker that initiates the core code.
261 *
262 * This is core per VM code which might need fixups and/or for ease of use are
263 * put on linear contiguous backing.
264 *
265 * @returns VBox status code.
266 * @param pVM Pointer to the shared VM structure.
267 */
268static int vmmR3InitCoreCode(PVM pVM)
269{
270 /*
271 * Calc the size.
272 */
273 unsigned cbCoreCode = 0;
274 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
275 {
276 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
277 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
278 if (pSwitcher)
279 {
280 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
281 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
282 }
283 }
284
285 /*
286 * Allocate continguous pages for switchers and deal with
287 * conflicts in the intermediate mapping of the code.
288 */
289 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
290 pVM->vmm.s.pvCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
291 int rc = VERR_NO_MEMORY;
292 if (pVM->vmm.s.pvCoreCodeR3)
293 {
294 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
295 if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
296 {
297 /* try more allocations - Solaris, Linux. */
298 const unsigned cTries = 8234;
299 struct VMMInitBadTry
300 {
301 RTR0PTR pvR0;
302 void *pvR3;
303 RTHCPHYS HCPhys;
304 RTUINT cb;
305 } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
306 AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
307 unsigned i = 0;
308 do
309 {
310 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
311 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
312 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
313 i++;
314 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
315 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
316 pVM->vmm.s.pvCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
317 if (!pVM->vmm.s.pvCoreCodeR3)
318 break;
319 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
320 } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
321 && i < cTries - 1);
322
323 /* cleanup */
324 if (VBOX_FAILURE(rc))
325 {
326 paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
327 paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
328 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
329 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
330 i++;
331 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
332 }
333 while (i-- > 0)
334 {
335 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
336 i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
337 SUPContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
338 }
339 RTMemTmpFree(paBadTries);
340 }
341 }
342 if (VBOX_SUCCESS(rc))
343 {
344 /*
345 * copy the code.
346 */
347 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
348 {
349 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
350 if (pSwitcher)
351 memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
352 pSwitcher->pvCode, pSwitcher->cbCode);
353 }
354
355 /*
356 * Map the code into the GC address space.
357 */
358 RTGCPTR GCPtr;
359 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &GCPtr);
360 if (VBOX_SUCCESS(rc))
361 {
362 pVM->vmm.s.pvCoreCodeRC = GCPtr;
363 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
364 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VRv Phys=%VHp cb=%#x\n",
365 pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
366
367 /*
368 * Finally, PGM probably have selected a switcher already but we need
369 * to get the routine addresses, so we'll reselect it.
370 * This may legally fail so, we're ignoring the rc.
371 */
372 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
373 return rc;
374 }
375
376 /* shit */
377 AssertMsgFailed(("PGMR3Map(,%VRv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
378 SUPContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
379 }
380 else
381 VMSetError(pVM, rc, RT_SRC_POS,
382 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
383 cbCoreCode);
384
385 pVM->vmm.s.pvCoreCodeR3 = NULL;
386 pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
387 pVM->vmm.s.pvCoreCodeRC = 0;
388 return rc;
389}
390
391
392/**
393 * Allocate & setup the VMM RC stack(s) (for EMTs).
394 *
395 * The stacks are also used for long jumps in Ring-0.
396 *
397 * @returns VBox status code.
398 * @param pVM Pointer to the shared VM structure.
399 *
400 * @remarks The optional guard page gets it protection setup up during R3 init
401 * completion because of init order issues.
402 */
403static int vmmR3InitStacks(PVM pVM)
404{
405 /** @todo SMP: On stack per vCPU. */
406#ifdef VBOX_STRICT_VMM_STACK
407 int rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbEMTStackR3);
408#else
409 int rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbEMTStackR3);
410#endif
411 if (VBOX_SUCCESS(rc))
412 {
413 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = MMHyperR3ToR0(pVM, pVM->vmm.s.pbEMTStackR3);
414 pVM->vmm.s.pbEMTStackRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3);
415 pVM->vmm.s.pbEMTStackBottomRC = pVM->vmm.s.pbEMTStackRC + VMM_STACK_SIZE;
416 AssertRelease(pVM->vmm.s.pbEMTStackRC);
417
418 CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC);
419 }
420
421 return rc;
422}
423
424
425/**
426 * Initialize the loggers.
427 *
428 * @returns VBox status code.
429 * @param pVM Pointer to the shared VM structure.
430 */
431static int vmmR3InitLoggers(PVM pVM)
432{
433 int rc;
434
435 /*
436 * Allocate RC & R0 Logger instances (they are finalized in the relocator).
437 */
438#ifdef LOG_ENABLED
439 PRTLOGGER pLogger = RTLogDefaultInstance();
440 if (pLogger)
441 {
442 pVM->vmm.s.cbRCLogger = RT_OFFSETOF(RTLOGGERRC, afGroups[pLogger->cGroups]);
443 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRCLogger, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRCLoggerR3);
444 if (RT_FAILURE(rc))
445 return rc;
446 pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
447
448# ifdef VBOX_WITH_R0_LOGGING
449 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
450 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0LoggerR3);
451 if (RT_FAILURE(rc))
452 return rc;
453 pVM->vmm.s.pR0LoggerR3->pVM = pVM->pVMR0;
454 //pVM->vmm.s.pR0LoggerR3->fCreated = false;
455 pVM->vmm.s.pR0LoggerR3->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
456 pVM->vmm.s.pR0LoggerR0 = MMHyperR3ToR0(pVM, pVM->vmm.s.pR0LoggerR3);
457# endif
458 }
459#endif /* LOG_ENABLED */
460
461#ifdef VBOX_WITH_RC_RELEASE_LOGGING
462 /*
463 * Allocate RC release logger instances (finalized in the relocator).
464 */
465 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
466 if (pRelLogger)
467 {
468 pVM->vmm.s.cbRCRelLogger = RT_OFFSETOF(RTLOGGERRC, afGroups[pRelLogger->cGroups]);
469 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRCRelLogger, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRCRelLoggerR3);
470 if (RT_FAILURE(rc))
471 return rc;
472 pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
473 }
474#endif /* VBOX_WITH_RC_RELEASE_LOGGING */
475 return VINF_SUCCESS;
476}
477
478
479/**
480 * VMMR3Init worker that register the statistics with STAM.
481 *
482 * @param pVM The shared VM structure.
483 */
484static void vmmR3InitRegisterStats(PVM pVM)
485{
486 /*
487 * Statistics.
488 */
489 STAM_REG(pVM, &pVM->vmm.s.StatRunRC, STAMTYPE_COUNTER, "/VMM/RunRC", STAMUNIT_OCCURENCES, "Number of context switches.");
490 STAM_REG(pVM, &pVM->vmm.s.StatRZRetNormal, STAMTYPE_COUNTER, "/VMM/RZRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
491 STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterrupt, STAMTYPE_COUNTER, "/VMM/RZRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
492 STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/RZRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
493 STAM_REG(pVM, &pVM->vmm.s.StatRZRetGuestTrap, STAMTYPE_COUNTER, "/VMM/RZRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
494 STAM_REG(pVM, &pVM->vmm.s.StatRZRetRingSwitch, STAMTYPE_COUNTER, "/VMM/RZRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
495 STAM_REG(pVM, &pVM->vmm.s.StatRZRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/RZRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
496 STAM_REG(pVM, &pVM->vmm.s.StatRZRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/RZRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
497 STAM_REG(pVM, &pVM->vmm.s.StatRZRetStaleSelector, STAMTYPE_COUNTER, "/VMM/RZRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
498 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIRETTrap, STAMTYPE_COUNTER, "/VMM/RZRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
499 STAM_REG(pVM, &pVM->vmm.s.StatRZRetEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
500 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
501 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIORead, STAMTYPE_COUNTER, "/VMM/RZRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
502 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIOWrite, STAMTYPE_COUNTER, "/VMM/RZRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
503 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIORead, STAMTYPE_COUNTER, "/VMM/RZRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
504 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
505 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
506 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
507 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
508 STAM_REG(pVM, &pVM->vmm.s.StatRZRetLDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
509 STAM_REG(pVM, &pVM->vmm.s.StatRZRetGDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
510 STAM_REG(pVM, &pVM->vmm.s.StatRZRetIDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
511 STAM_REG(pVM, &pVM->vmm.s.StatRZRetTSSFault, STAMTYPE_COUNTER, "/VMM/RZRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
512 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPDFault, STAMTYPE_COUNTER, "/VMM/RZRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
513 STAM_REG(pVM, &pVM->vmm.s.StatRZRetCSAMTask, STAMTYPE_COUNTER, "/VMM/RZRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
514 STAM_REG(pVM, &pVM->vmm.s.StatRZRetSyncCR3, STAMTYPE_COUNTER, "/VMM/RZRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMisc, STAMTYPE_COUNTER, "/VMM/RZRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchInt3, STAMTYPE_COUNTER, "/VMM/RZRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
517 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchPF, STAMTYPE_COUNTER, "/VMM/RZRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
518 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchGP, STAMTYPE_COUNTER, "/VMM/RZRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
519 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/RZRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
520 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPageOverflow, STAMTYPE_COUNTER, "/VMM/RZRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
521 STAM_REG(pVM, &pVM->vmm.s.StatRZRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/RZRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
522 STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
523 STAM_REG(pVM, &pVM->vmm.s.StatRZRetTimerPending, STAMTYPE_COUNTER, "/VMM/RZRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
524 STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterruptPending, STAMTYPE_COUNTER, "/VMM/RZRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
525 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/RZRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
526 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/RZRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
527 STAM_REG(pVM, &pVM->vmm.s.StatRZRetEmulHlt, STAMTYPE_COUNTER, "/VMM/RZRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
528 STAM_REG(pVM, &pVM->vmm.s.StatRZRetPendingRequest, STAMTYPE_COUNTER, "/VMM/RZRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
529
530 STAM_REG(pVM, &pVM->vmm.s.StatRZRetCallHost, STAMTYPE_COUNTER, "/VMM/RZCallR3/Misc", STAMUNIT_OCCURENCES, "Number of Other ring-3 calls.");
531 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPDMLock, STAMTYPE_COUNTER, "/VMM/RZCallR3/PDMLock", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PDM_LOCK calls.");
532 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/RZCallR3/PDMQueueFlush", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PDM_QUEUE_FLUSH calls.");
533 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMLock, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMLock", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_LOCK calls.");
534 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMPoolGrow", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_POOL_GROW calls.");
535 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMMapChunk, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMMapChunk", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_MAP_CHUNK calls.");
536 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMAllocHandy, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMAllocHandy", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES calls.");
537#ifndef VBOX_WITH_NEW_PHYS_CODE
538 STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMGrowRAM", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_RAM_GROW_RANGE calls.");
539#endif
540 STAM_REG(pVM, &pVM->vmm.s.StatRZCallRemReplay, STAMTYPE_COUNTER, "/VMM/RZCallR3/REMReplay", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS calls.");
541 STAM_REG(pVM, &pVM->vmm.s.StatRZCallLogFlush, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMMLogFlush", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_VMM_LOGGER_FLUSH calls.");
542 STAM_REG(pVM, &pVM->vmm.s.StatRZCallVMSetError, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMSetError", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_VM_SET_ERROR calls.");
543 STAM_REG(pVM, &pVM->vmm.s.StatRZCallVMSetRuntimeError, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMRuntimeError", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_VM_SET_RUNTIME_ERROR calls.");
544}
545
546
547/**
548 * Ring-3 init finalizing.
549 *
550 * @returns VBox status code.
551 * @param pVM The VM handle.
552 */
553VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
554{
555#ifdef VBOX_STRICT_VMM_STACK
556 /*
557 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
558 */
559 memset(pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE, 0xcc, PAGE_SIZE);
560 PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE), PAGE_SIZE, 0);
561 RTMemProtect(pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
562
563 memset(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
564 PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE), PAGE_SIZE, 0);
565 RTMemProtect(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
566#endif
567
568 /*
569 * Set page attributes to r/w for stack pages.
570 */
571 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbEMTStackRC, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
572 AssertRC(rc);
573 if (VBOX_SUCCESS(rc))
574 {
575 /*
576 * Create the EMT yield timer.
577 */
578 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
579 if (VBOX_SUCCESS(rc))
580 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
581 }
582
583#ifdef VBOX_WITH_NMI
584 /*
585 * Map the host APIC into GC - This is AMD/Intel + Host OS specific!
586 */
587 if (VBOX_SUCCESS(rc))
588 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
589 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
590#endif
591 return rc;
592}
593
594
595/**
596 * Initializes the R0 VMM.
597 *
598 * @returns VBox status code.
599 * @param pVM The VM to operate on.
600 */
601VMMR3DECL(int) VMMR3InitR0(PVM pVM)
602{
603 int rc;
604
605 /*
606 * Initialize the ring-0 logger if we haven't done so yet.
607 */
608 if ( pVM->vmm.s.pR0LoggerR3
609 && !pVM->vmm.s.pR0LoggerR3->fCreated)
610 {
611 rc = VMMR3UpdateLoggers(pVM);
612 if (VBOX_FAILURE(rc))
613 return rc;
614 }
615
616 /*
617 * Call Ring-0 entry with init code.
618 */
619 for (;;)
620 {
621#ifdef NO_SUPCALLR0VMM
622 //rc = VERR_GENERAL_FAILURE;
623 rc = VINF_SUCCESS;
624#else
625 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, VMMGetSvnRev(), NULL);
626#endif
627 if ( pVM->vmm.s.pR0LoggerR3
628 && pVM->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
629 RTLogFlushToLogger(&pVM->vmm.s.pR0LoggerR3->Logger, NULL);
630 if (rc != VINF_VMM_CALL_HOST)
631 break;
632 rc = vmmR3ServiceCallHostRequest(pVM);
633 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
634 break;
635 /* Resume R0 */
636 }
637
638 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
639 {
640 LogRel(("R0 init failed, rc=%Vra\n", rc));
641 if (VBOX_SUCCESS(rc))
642 rc = VERR_INTERNAL_ERROR;
643 }
644 return rc;
645}
646
647
648/**
649 * Initializes the RC VMM.
650 *
651 * @returns VBox status code.
652 * @param pVM The VM to operate on.
653 */
654VMMR3DECL(int) VMMR3InitRC(PVM pVM)
655{
656 /* In VMX mode, there's no need to init RC. */
657 if (pVM->vmm.s.fSwitcherDisabled)
658 return VINF_SUCCESS;
659
660 /*
661 * Call VMMGCInit():
662 * -# resolve the address.
663 * -# setup stackframe and EIP to use the trampoline.
664 * -# do a generic hypervisor call.
665 */
666 RTGCPTR32 GCPtrEP;
667 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
668 if (VBOX_SUCCESS(rc))
669 {
670 CPUMHyperSetCtxCore(pVM, NULL);
671 CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
672 uint64_t u64TS = RTTimeProgramStartNanoTS();
673 CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
674 CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
675 CPUMPushHyper(pVM, VMMGetSvnRev()); /* Param 2: Version argument. */
676 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
677 CPUMPushHyper(pVM, pVM->pVMRC); /* Param 0: pVM */
678 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR32)); /* trampoline param: stacksize. */
679 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
680 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnCallTrampolineRC);
681
682 for (;;)
683 {
684#ifdef NO_SUPCALLR0VMM
685 //rc = VERR_GENERAL_FAILURE;
686 rc = VINF_SUCCESS;
687#else
688 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
689#endif
690#ifdef LOG_ENABLED
691 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
692 if ( pLogger
693 && pLogger->offScratch > 0)
694 RTLogFlushRC(NULL, pLogger);
695#endif
696#ifdef VBOX_WITH_RC_RELEASE_LOGGING
697 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
698 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
699 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
700#endif
701 if (rc != VINF_VMM_CALL_HOST)
702 break;
703 rc = vmmR3ServiceCallHostRequest(pVM);
704 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
705 break;
706 }
707
708 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
709 {
710 VMMR3FatalDump(pVM, rc);
711 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
712 rc = VERR_INTERNAL_ERROR;
713 }
714 AssertRC(rc);
715 }
716 return rc;
717}
718
719
720/**
721 * Terminate the VMM bits.
722 *
723 * @returns VINF_SUCCESS.
724 * @param pVM The VM handle.
725 */
726VMMR3DECL(int) VMMR3Term(PVM pVM)
727{
728 /*
729 * Call Ring-0 entry with termination code.
730 */
731 int rc;
732 for (;;)
733 {
734#ifdef NO_SUPCALLR0VMM
735 //rc = VERR_GENERAL_FAILURE;
736 rc = VINF_SUCCESS;
737#else
738 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_TERM, 0, NULL);
739#endif
740 if ( pVM->vmm.s.pR0LoggerR3
741 && pVM->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
742 RTLogFlushToLogger(&pVM->vmm.s.pR0LoggerR3->Logger, NULL);
743 if (rc != VINF_VMM_CALL_HOST)
744 break;
745 rc = vmmR3ServiceCallHostRequest(pVM);
746 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
747 break;
748 /* Resume R0 */
749 }
750 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
751 {
752 LogRel(("VMMR3Term: R0 term failed, rc=%Vra. (warning)\n", rc));
753 if (VBOX_SUCCESS(rc))
754 rc = VERR_INTERNAL_ERROR;
755 }
756
757#ifdef VBOX_STRICT_VMM_STACK
758 /*
759 * Make the two stack guard pages present again.
760 */
761 RTMemProtect(pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
762 RTMemProtect(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
763#endif
764 return rc;
765}
766
767/**
768 * Terminates the per-VCPU VMM.
769 *
770 * Termination means cleaning up and freeing all resources,
771 * the VM it self is at this point powered off or suspended.
772 *
773 * @returns VBox status code.
774 * @param pVM The VM to operate on.
775 */
776VMMR3DECL(int) VMMR3TermCPU(PVM pVM)
777{
778 return 0;
779}
780
781
782/**
783 * Applies relocations to data and code managed by this
784 * component. This function will be called at init and
785 * whenever the VMM need to relocate it self inside the GC.
786 *
787 * The VMM will need to apply relocations to the core code.
788 *
789 * @param pVM The VM handle.
790 * @param offDelta The relocation delta.
791 */
792VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
793{
794 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
795
796 /*
797 * Recalc the RC address.
798 */
799 pVM->vmm.s.pvCoreCodeRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pvCoreCodeR3);
800
801 /*
802 * The stack.
803 */
804 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
805 pVM->vmm.s.pbEMTStackRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3);
806 pVM->vmm.s.pbEMTStackBottomRC = pVM->vmm.s.pbEMTStackRC + VMM_STACK_SIZE;
807
808 /*
809 * All the switchers.
810 */
811 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
812 {
813 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
814 if (pSwitcher && pSwitcher->pfnRelocate)
815 {
816 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
817 pSwitcher->pfnRelocate(pVM,
818 pSwitcher,
819 pVM->vmm.s.pvCoreCodeR0 + off,
820 (uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
821 pVM->vmm.s.pvCoreCodeRC + off,
822 pVM->vmm.s.HCPhysCoreCode + off);
823 }
824 }
825
826 /*
827 * Recalc the RC address for the current switcher.
828 */
829 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
830 RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
831 pVM->vmm.s.pfnGuestToHostRC = RCPtr + pSwitcher->offGCGuestToHost;
832 pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offGCCallTrampoline;
833 pVM->pfnVMMGCGuestToHostAsm = RCPtr + pSwitcher->offGCGuestToHostAsm;
834 pVM->pfnVMMGCGuestToHostAsmHyperCtx = RCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
835 pVM->pfnVMMGCGuestToHostAsmGuestCtx = RCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
836
837 /*
838 * Get other RC entry points.
839 */
840 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMRCResumeGuest);
841 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
842
843 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMRCResumeGuestV86);
844 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
845
846 /*
847 * Update the logger.
848 */
849 VMMR3UpdateLoggers(pVM);
850}
851
852
853/**
854 * Updates the settings for the RC and R0 loggers.
855 *
856 * @returns VBox status code.
857 * @param pVM The VM handle.
858 */
859VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
860{
861 /*
862 * Simply clone the logger instance (for RC).
863 */
864 int rc = VINF_SUCCESS;
865 RTRCPTR RCPtrLoggerFlush = 0;
866
867 if (pVM->vmm.s.pRCLoggerR3
868#ifdef VBOX_WITH_RC_RELEASE_LOGGING
869 || pVM->vmm.s.pRCRelLoggerR3
870#endif
871 )
872 {
873 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &RCPtrLoggerFlush);
874 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
875 }
876
877 if (pVM->vmm.s.pRCLoggerR3)
878 {
879 RTRCPTR RCPtrLoggerWrapper = 0;
880 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &RCPtrLoggerWrapper);
881 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
882
883 pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
884 rc = RTLogCloneRC(NULL /* default */, pVM->vmm.s.pRCLoggerR3, pVM->vmm.s.cbRCLogger,
885 RCPtrLoggerWrapper, RCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
886 AssertReleaseMsgRC(rc, ("RTLogCloneRC failed! rc=%Vra\n", rc));
887 }
888
889#ifdef VBOX_WITH_RC_RELEASE_LOGGING
890 if (pVM->vmm.s.pRCRelLoggerR3)
891 {
892 RTRCPTR RCPtrLoggerWrapper = 0;
893 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &RCPtrLoggerWrapper);
894 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
895
896 pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
897 rc = RTLogCloneRC(RTLogRelDefaultInstance(), pVM->vmm.s.pRCRelLoggerR3, pVM->vmm.s.cbRCRelLogger,
898 RCPtrLoggerWrapper, RCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
899 AssertReleaseMsgRC(rc, ("RTLogCloneRC failed! rc=%Vra\n", rc));
900 }
901#endif /* VBOX_WITH_RC_RELEASE_LOGGING */
902
903 /*
904 * For the ring-0 EMT logger, we use a per-thread logger instance
905 * in ring-0. Only initialize it once.
906 */
907 PVMMR0LOGGER pR0LoggerR3 = pVM->vmm.s.pR0LoggerR3;
908 if (pR0LoggerR3)
909 {
910 if (!pR0LoggerR3->fCreated)
911 {
912 RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
913 rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
914 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
915
916 RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
917 rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
918 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
919
920 rc = RTLogCreateForR0(&pR0LoggerR3->Logger, pR0LoggerR3->cbLogger,
921 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
922 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
923 AssertReleaseMsgRCReturn(rc, ("RTLogCreateForR0 failed! rc=%Vra\n", rc), rc);
924 pR0LoggerR3->fCreated = true;
925 }
926
927 rc = RTLogCopyGroupsAndFlags(&pR0LoggerR3->Logger, NULL /* default */, pVM->vmm.s.pRCLoggerR3->fFlags, RTLOGFLAGS_BUFFERED);
928 AssertRC(rc);
929 }
930
931 return rc;
932}
933
934
935/**
936 * Generic switch code relocator.
937 *
938 * @param pVM The VM handle.
939 * @param pSwitcher The switcher definition.
940 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
941 * @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
942 * @param GCPtrCode The guest context address corresponding to pu8Code.
943 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
944 * @param SelCS The hypervisor CS selector.
945 * @param SelDS The hypervisor DS selector.
946 * @param SelTSS The hypervisor TSS selector.
947 * @param GCPtrGDT The GC address of the hypervisor GDT.
948 * @param SelCS64 The 64-bit mode hypervisor CS selector.
949 */
950static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
951 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
952{
953 union
954 {
955 const uint8_t *pu8;
956 const uint16_t *pu16;
957 const uint32_t *pu32;
958 const uint64_t *pu64;
959 const void *pv;
960 uintptr_t u;
961 } u;
962 u.pv = pSwitcher->pvFixups;
963
964 /*
965 * Process fixups.
966 */
967 uint8_t u8;
968 while ((u8 = *u.pu8++) != FIX_THE_END)
969 {
970 /*
971 * Get the source (where to write the fixup).
972 */
973 uint32_t offSrc = *u.pu32++;
974 Assert(offSrc < pSwitcher->cbCode);
975 union
976 {
977 uint8_t *pu8;
978 uint16_t *pu16;
979 uint32_t *pu32;
980 uint64_t *pu64;
981 uintptr_t u;
982 } uSrc;
983 uSrc.pu8 = pu8CodeR3 + offSrc;
984
985 /* The fixup target and method depends on the type. */
986 switch (u8)
987 {
988 /*
989 * 32-bit relative, source in HC and target in GC.
990 */
991 case FIX_HC_2_GC_NEAR_REL:
992 {
993 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
994 uint32_t offTrg = *u.pu32++;
995 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
996 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
997 break;
998 }
999
1000 /*
1001 * 32-bit relative, source in HC and target in ID.
1002 */
1003 case FIX_HC_2_ID_NEAR_REL:
1004 {
1005 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1006 uint32_t offTrg = *u.pu32++;
1007 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1008 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
1009 break;
1010 }
1011
1012 /*
1013 * 32-bit relative, source in GC and target in HC.
1014 */
1015 case FIX_GC_2_HC_NEAR_REL:
1016 {
1017 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1018 uint32_t offTrg = *u.pu32++;
1019 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1020 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
1021 break;
1022 }
1023
1024 /*
1025 * 32-bit relative, source in GC and target in ID.
1026 */
1027 case FIX_GC_2_ID_NEAR_REL:
1028 {
1029 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1030 uint32_t offTrg = *u.pu32++;
1031 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1032 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1033 break;
1034 }
1035
1036 /*
1037 * 32-bit relative, source in ID and target in HC.
1038 */
1039 case FIX_ID_2_HC_NEAR_REL:
1040 {
1041 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1042 uint32_t offTrg = *u.pu32++;
1043 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1044 *uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
1045 break;
1046 }
1047
1048 /*
1049 * 32-bit relative, source in ID and target in HC.
1050 */
1051 case FIX_ID_2_GC_NEAR_REL:
1052 {
1053 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1054 uint32_t offTrg = *u.pu32++;
1055 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1056 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1057 break;
1058 }
1059
1060 /*
1061 * 16:32 far jump, target in GC.
1062 */
1063 case FIX_GC_FAR32:
1064 {
1065 uint32_t offTrg = *u.pu32++;
1066 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1067 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1068 *uSrc.pu16++ = SelCS;
1069 break;
1070 }
1071
1072 /*
1073 * Make 32-bit GC pointer given CPUM offset.
1074 */
1075 case FIX_GC_CPUM_OFF:
1076 {
1077 uint32_t offCPUM = *u.pu32++;
1078 Assert(offCPUM < sizeof(pVM->cpum));
1079 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1080 break;
1081 }
1082
1083 /*
1084 * Make 32-bit GC pointer given VM offset.
1085 */
1086 case FIX_GC_VM_OFF:
1087 {
1088 uint32_t offVM = *u.pu32++;
1089 Assert(offVM < sizeof(VM));
1090 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1091 break;
1092 }
1093
1094 /*
1095 * Make 32-bit HC pointer given CPUM offset.
1096 */
1097 case FIX_HC_CPUM_OFF:
1098 {
1099 uint32_t offCPUM = *u.pu32++;
1100 Assert(offCPUM < sizeof(pVM->cpum));
1101 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1102 break;
1103 }
1104
1105 /*
1106 * Make 32-bit R0 pointer given VM offset.
1107 */
1108 case FIX_HC_VM_OFF:
1109 {
1110 uint32_t offVM = *u.pu32++;
1111 Assert(offVM < sizeof(VM));
1112 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1113 break;
1114 }
1115
1116 /*
1117 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1118 */
1119 case FIX_INTER_32BIT_CR3:
1120 {
1121
1122 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1123 break;
1124 }
1125
1126 /*
1127 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1128 */
1129 case FIX_INTER_PAE_CR3:
1130 {
1131
1132 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1133 break;
1134 }
1135
1136 /*
1137 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1138 */
1139 case FIX_INTER_AMD64_CR3:
1140 {
1141
1142 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1143 break;
1144 }
1145
1146 /*
1147 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1148 */
1149 case FIX_HYPER_32BIT_CR3:
1150 {
1151
1152 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1153 break;
1154 }
1155
1156 /*
1157 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1158 */
1159 case FIX_HYPER_PAE_CR3:
1160 {
1161
1162 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1163 break;
1164 }
1165
1166 /*
1167 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1168 */
1169 case FIX_HYPER_AMD64_CR3:
1170 {
1171
1172 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1173 break;
1174 }
1175
1176 /*
1177 * Store Hypervisor CS (16-bit).
1178 */
1179 case FIX_HYPER_CS:
1180 {
1181 *uSrc.pu16 = SelCS;
1182 break;
1183 }
1184
1185 /*
1186 * Store Hypervisor DS (16-bit).
1187 */
1188 case FIX_HYPER_DS:
1189 {
1190 *uSrc.pu16 = SelDS;
1191 break;
1192 }
1193
1194 /*
1195 * Store Hypervisor TSS (16-bit).
1196 */
1197 case FIX_HYPER_TSS:
1198 {
1199 *uSrc.pu16 = SelTSS;
1200 break;
1201 }
1202
1203 /*
1204 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1205 */
1206 case FIX_GC_TSS_GDTE_DW2:
1207 {
1208 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1209 *uSrc.pu32 = (uint32_t)GCPtr;
1210 break;
1211 }
1212
1213
1214 ///@todo case FIX_CR4_MASK:
1215 ///@todo case FIX_CR4_OSFSXR:
1216
1217 /*
1218 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1219 */
1220 case FIX_NO_FXSAVE_JMP:
1221 {
1222 uint32_t offTrg = *u.pu32++;
1223 Assert(offTrg < pSwitcher->cbCode);
1224 if (!CPUMSupportsFXSR(pVM))
1225 {
1226 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1227 *uSrc.pu32++ = offTrg - (offSrc + 5);
1228 }
1229 else
1230 {
1231 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1232 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1233 }
1234 break;
1235 }
1236
1237 /*
1238 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1239 */
1240 case FIX_NO_SYSENTER_JMP:
1241 {
1242 uint32_t offTrg = *u.pu32++;
1243 Assert(offTrg < pSwitcher->cbCode);
1244 if (!CPUMIsHostUsingSysEnter(pVM))
1245 {
1246 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1247 *uSrc.pu32++ = offTrg - (offSrc + 5);
1248 }
1249 else
1250 {
1251 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1252 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1253 }
1254 break;
1255 }
1256
1257 /*
1258 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1259 */
1260 case FIX_NO_SYSCALL_JMP:
1261 {
1262 uint32_t offTrg = *u.pu32++;
1263 Assert(offTrg < pSwitcher->cbCode);
1264 if (!CPUMIsHostUsingSysEnter(pVM))
1265 {
1266 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1267 *uSrc.pu32++ = offTrg - (offSrc + 5);
1268 }
1269 else
1270 {
1271 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1272 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1273 }
1274 break;
1275 }
1276
1277 /*
1278 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1279 */
1280 case FIX_HC_32BIT:
1281 {
1282 uint32_t offTrg = *u.pu32++;
1283 Assert(offSrc < pSwitcher->cbCode);
1284 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1285 *uSrc.pu32 = R0PtrCode + offTrg;
1286 break;
1287 }
1288
1289#if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1290 /*
1291 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1292 */
1293 case FIX_HC_64BIT:
1294 {
1295 uint32_t offTrg = *u.pu32++;
1296 Assert(offSrc < pSwitcher->cbCode);
1297 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1298 *uSrc.pu64 = R0PtrCode + offTrg;
1299 break;
1300 }
1301
1302 /*
1303 * 64-bit HC Code Selector (no argument).
1304 */
1305 case FIX_HC_64BIT_CS:
1306 {
1307 Assert(offSrc < pSwitcher->cbCode);
1308#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1309 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
1310#else
1311 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1312#endif
1313 break;
1314 }
1315
1316 /*
1317 * 64-bit HC pointer to the CPUM instance data (no argument).
1318 */
1319 case FIX_HC_64BIT_CPUM:
1320 {
1321 Assert(offSrc < pSwitcher->cbCode);
1322 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1323 break;
1324 }
1325#endif
1326
1327 /*
1328 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1329 */
1330 case FIX_ID_32BIT:
1331 {
1332 uint32_t offTrg = *u.pu32++;
1333 Assert(offSrc < pSwitcher->cbCode);
1334 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1335 *uSrc.pu32 = u32IDCode + offTrg;
1336 break;
1337 }
1338
1339 /*
1340 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1341 */
1342 case FIX_ID_64BIT:
1343 {
1344 uint32_t offTrg = *u.pu32++;
1345 Assert(offSrc < pSwitcher->cbCode);
1346 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1347 *uSrc.pu64 = u32IDCode + offTrg;
1348 break;
1349 }
1350
1351 /*
1352 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1353 */
1354 case FIX_ID_FAR32_TO_64BIT_MODE:
1355 {
1356 uint32_t offTrg = *u.pu32++;
1357 Assert(offSrc < pSwitcher->cbCode);
1358 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1359 *uSrc.pu32++ = u32IDCode + offTrg;
1360 *uSrc.pu16 = SelCS64;
1361 AssertRelease(SelCS64);
1362 break;
1363 }
1364
1365#ifdef VBOX_WITH_NMI
1366 /*
1367 * 32-bit address to the APIC base.
1368 */
1369 case FIX_GC_APIC_BASE_32BIT:
1370 {
1371 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1372 break;
1373 }
1374#endif
1375
1376 default:
1377 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1378 break;
1379 }
1380 }
1381
1382#ifdef LOG_ENABLED
1383 /*
1384 * If Log2 is enabled disassemble the switcher code.
1385 *
1386 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1387 */
1388 if (LogIs2Enabled())
1389 {
1390 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1391 " R0PtrCode = %p\n"
1392 " pu8CodeR3 = %p\n"
1393 " GCPtrCode = %VGv\n"
1394 " u32IDCode = %08x\n"
1395 " pVMGC = %VGv\n"
1396 " pCPUMGC = %VGv\n"
1397 " pVMHC = %p\n"
1398 " pCPUMHC = %p\n"
1399 " GCPtrGDT = %VGv\n"
1400 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1401 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1402 " SelCS = %04x\n"
1403 " SelDS = %04x\n"
1404 " SelCS64 = %04x\n"
1405 " SelTSS = %04x\n",
1406 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1407 R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1408 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1409 GCPtrGDT,
1410 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1411 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1412 SelCS, SelDS, SelCS64, SelTSS);
1413
1414 uint32_t offCode = 0;
1415 while (offCode < pSwitcher->cbCode)
1416 {
1417 /*
1418 * Figure out where this is.
1419 */
1420 const char *pszDesc = NULL;
1421 RTUINTPTR uBase;
1422 uint32_t cbCode;
1423 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1424 {
1425 pszDesc = "HCCode0";
1426 uBase = R0PtrCode;
1427 offCode = pSwitcher->offHCCode0;
1428 cbCode = pSwitcher->cbHCCode0;
1429 }
1430 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1431 {
1432 pszDesc = "HCCode1";
1433 uBase = R0PtrCode;
1434 offCode = pSwitcher->offHCCode1;
1435 cbCode = pSwitcher->cbHCCode1;
1436 }
1437 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1438 {
1439 pszDesc = "GCCode";
1440 uBase = GCPtrCode;
1441 offCode = pSwitcher->offGCCode;
1442 cbCode = pSwitcher->cbGCCode;
1443 }
1444 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1445 {
1446 pszDesc = "IDCode0";
1447 uBase = u32IDCode;
1448 offCode = pSwitcher->offIDCode0;
1449 cbCode = pSwitcher->cbIDCode0;
1450 }
1451 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1452 {
1453 pszDesc = "IDCode1";
1454 uBase = u32IDCode;
1455 offCode = pSwitcher->offIDCode1;
1456 cbCode = pSwitcher->cbIDCode1;
1457 }
1458 else
1459 {
1460 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1461 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1462 offCode++;
1463 continue;
1464 }
1465
1466 /*
1467 * Disassemble it.
1468 */
1469 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1470 DISCPUSTATE Cpu;
1471
1472 memset(&Cpu, 0, sizeof(Cpu));
1473 Cpu.mode = CPUMODE_32BIT;
1474 while (cbCode > 0)
1475 {
1476 /* try label it */
1477 if (pSwitcher->offR0HostToGuest == offCode)
1478 RTLogPrintf(" *R0HostToGuest:\n");
1479 if (pSwitcher->offGCGuestToHost == offCode)
1480 RTLogPrintf(" *GCGuestToHost:\n");
1481 if (pSwitcher->offGCCallTrampoline == offCode)
1482 RTLogPrintf(" *GCCallTrampoline:\n");
1483 if (pSwitcher->offGCGuestToHostAsm == offCode)
1484 RTLogPrintf(" *GCGuestToHostAsm:\n");
1485 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1486 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1487 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1488 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1489
1490 /* disas */
1491 uint32_t cbInstr = 0;
1492 char szDisas[256];
1493 if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
1494 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1495 else
1496 {
1497 RTLogPrintf(" %04x: %02x '%c'\n",
1498 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1499 cbInstr = 1;
1500 }
1501 offCode += cbInstr;
1502 cbCode -= RT_MIN(cbInstr, cbCode);
1503 }
1504 }
1505 }
1506#endif
1507}
1508
1509
1510/**
1511 * Relocator for the 32-Bit to 32-Bit world switcher.
1512 */
1513DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1514{
1515 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1516 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1517}
1518
1519
1520/**
1521 * Relocator for the 32-Bit to PAE world switcher.
1522 */
1523DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1524{
1525 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1526 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1527}
1528
1529
1530/**
1531 * Relocator for the PAE to 32-Bit world switcher.
1532 */
1533DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1534{
1535 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1536 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1537}
1538
1539
1540/**
1541 * Relocator for the PAE to PAE world switcher.
1542 */
1543DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1544{
1545 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1546 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1547}
1548
1549
1550/**
1551 * Relocator for the AMD64 to PAE world switcher.
1552 */
1553DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1554{
1555 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1556 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1557}
1558
1559
1560/**
1561 * Gets the pointer to g_szRTAssertMsg1 in GC.
1562 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1563 * Returns NULL if not present.
1564 * @param pVM The VM handle.
1565 */
1566VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1567{
1568 RTGCPTR32 GCPtr;
1569 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1570 if (VBOX_SUCCESS(rc))
1571 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1572 return NULL;
1573}
1574
1575
1576/**
1577 * Gets the pointer to g_szRTAssertMsg2 in GC.
1578 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1579 * Returns NULL if not present.
1580 * @param pVM The VM handle.
1581 */
1582VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1583{
1584 RTGCPTR32 GCPtr;
1585 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1586 if (VBOX_SUCCESS(rc))
1587 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1588 return NULL;
1589}
1590
1591
1592/**
1593 * Execute state save operation.
1594 *
1595 * @returns VBox status code.
1596 * @param pVM VM Handle.
1597 * @param pSSM SSM operation handle.
1598 */
1599static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1600{
1601 LogFlow(("vmmR3Save:\n"));
1602
1603 /*
1604 * The hypervisor stack.
1605 * Note! See not in vmmR3Load.
1606 */
1607 SSMR3PutRCPtr(pSSM, pVM->vmm.s.pbEMTStackBottomRC);
1608 RTRCPTR RCPtrESP = CPUMGetHyperESP(pVM);
1609 AssertMsg(pVM->vmm.s.pbEMTStackBottomRC - RCPtrESP <= VMM_STACK_SIZE, ("Bottom %RRv ESP=%RRv\n", pVM->vmm.s.pbEMTStackBottomRC, RCPtrESP));
1610 SSMR3PutRCPtr(pSSM, RCPtrESP);
1611 SSMR3PutMem(pSSM, pVM->vmm.s.pbEMTStackR3, VMM_STACK_SIZE);
1612 return SSMR3PutU32(pSSM, ~0); /* terminator */
1613}
1614
1615
1616/**
1617 * Execute state load operation.
1618 *
1619 * @returns VBox status code.
1620 * @param pVM VM Handle.
1621 * @param pSSM SSM operation handle.
1622 * @param u32Version Data layout version.
1623 */
1624static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1625{
1626 LogFlow(("vmmR3Load:\n"));
1627
1628 /*
1629 * Validate version.
1630 */
1631 if (u32Version != VMM_SAVED_STATE_VERSION)
1632 {
1633 AssertMsgFailed(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1634 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1635 }
1636
1637 /*
1638 * Check that the stack is in the same place, or that it's fearly empty.
1639 *
1640 * Note! This can be skipped next time we update saved state as we will
1641 * never be in a R0/RC -> ring-3 call when saving the state. The
1642 * stack and the two associated pointers are not required.
1643 */
1644 RTRCPTR RCPtrStackBottom;
1645 SSMR3GetRCPtr(pSSM, &RCPtrStackBottom);
1646 RTRCPTR RCPtrESP;
1647 int rc = SSMR3GetRCPtr(pSSM, &RCPtrESP);
1648 if (VBOX_FAILURE(rc))
1649 return rc;
1650
1651 /* restore the stack. */
1652 SSMR3GetMem(pSSM, pVM->vmm.s.pbEMTStackR3, VMM_STACK_SIZE);
1653
1654 /* terminator */
1655 uint32_t u32;
1656 rc = SSMR3GetU32(pSSM, &u32);
1657 if (VBOX_FAILURE(rc))
1658 return rc;
1659 if (u32 != ~0U)
1660 {
1661 AssertMsgFailed(("u32=%#x\n", u32));
1662 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1663 }
1664 return VINF_SUCCESS;
1665}
1666
1667
1668/**
1669 * Selects the switcher to be used for switching to GC.
1670 *
1671 * @returns VBox status code.
1672 * @param pVM VM handle.
1673 * @param enmSwitcher The new switcher.
1674 * @remark This function may be called before the VMM is initialized.
1675 */
1676VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1677{
1678 /*
1679 * Validate input.
1680 */
1681 if ( enmSwitcher < VMMSWITCHER_INVALID
1682 || enmSwitcher >= VMMSWITCHER_MAX)
1683 {
1684 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1685 return VERR_INVALID_PARAMETER;
1686 }
1687
1688 /* Do nothing if the switcher is disabled. */
1689 if (pVM->vmm.s.fSwitcherDisabled)
1690 return VINF_SUCCESS;
1691
1692 /*
1693 * Select the new switcher.
1694 */
1695 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1696 if (pSwitcher)
1697 {
1698 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1699 pVM->vmm.s.enmSwitcher = enmSwitcher;
1700
1701 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1702 pVM->vmm.s.pfnHostToGuestR0 = pbCodeR0 + pSwitcher->offR0HostToGuest;
1703
1704 RTGCPTR GCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1705 pVM->vmm.s.pfnGuestToHostRC = GCPtr + pSwitcher->offGCGuestToHost;
1706 pVM->vmm.s.pfnCallTrampolineRC = GCPtr + pSwitcher->offGCCallTrampoline;
1707 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1708 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1709 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1710 return VINF_SUCCESS;
1711 }
1712 return VERR_NOT_IMPLEMENTED;
1713}
1714
1715/**
1716 * Disable the switcher logic permanently.
1717 *
1718 * @returns VBox status code.
1719 * @param pVM VM handle.
1720 */
1721VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1722{
1723/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1724 * @code
1725 * mov eax, VERR_INTERNAL_ERROR
1726 * ret
1727 * @endcode
1728 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1729 */
1730 pVM->vmm.s.fSwitcherDisabled = true;
1731 return VINF_SUCCESS;
1732}
1733
1734
1735/**
1736 * Resolve a builtin RC symbol.
1737 *
1738 * Called by PDM when loading or relocating RC modules.
1739 *
1740 * @returns VBox status
1741 * @param pVM VM Handle.
1742 * @param pszSymbol Symbol to resolv
1743 * @param pRCPtrValue Where to store the symbol value.
1744 *
1745 * @remark This has to work before VMMR3Relocate() is called.
1746 */
1747VMMR3DECL(int) VMMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
1748{
1749 if (!strcmp(pszSymbol, "g_Logger"))
1750 {
1751 if (pVM->vmm.s.pRCLoggerR3)
1752 pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
1753 *pRCPtrValue = pVM->vmm.s.pRCLoggerRC;
1754 }
1755 else if (!strcmp(pszSymbol, "g_RelLogger"))
1756 {
1757#ifdef VBOX_WITH_RC_RELEASE_LOGGING
1758 if (pVM->vmm.s.pRCRelLoggerR3)
1759 pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
1760 *pRCPtrValue = pVM->vmm.s.pRCRelLoggerRC;
1761#else
1762 *pRCPtrValue = NIL_RTRCPTR;
1763#endif
1764 }
1765 else
1766 return VERR_SYMBOL_NOT_FOUND;
1767 return VINF_SUCCESS;
1768}
1769
1770
1771/**
1772 * Suspends the the CPU yielder.
1773 *
1774 * @param pVM The VM handle.
1775 */
1776VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1777{
1778 if (!pVM->vmm.s.cYieldResumeMillies)
1779 {
1780 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1781 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1782 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1783 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1784 else
1785 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1786 TMTimerStop(pVM->vmm.s.pYieldTimer);
1787 }
1788 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1789}
1790
1791
1792/**
1793 * Stops the the CPU yielder.
1794 *
1795 * @param pVM The VM handle.
1796 */
1797VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1798{
1799 if (!pVM->vmm.s.cYieldResumeMillies)
1800 TMTimerStop(pVM->vmm.s.pYieldTimer);
1801 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1802 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1803}
1804
1805
1806/**
1807 * Resumes the CPU yielder when it has been a suspended or stopped.
1808 *
1809 * @param pVM The VM handle.
1810 */
1811VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1812{
1813 if (pVM->vmm.s.cYieldResumeMillies)
1814 {
1815 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1816 pVM->vmm.s.cYieldResumeMillies = 0;
1817 }
1818}
1819
1820
1821/**
1822 * Internal timer callback function.
1823 *
1824 * @param pVM The VM.
1825 * @param pTimer The timer handle.
1826 * @param pvUser User argument specified upon timer creation.
1827 */
1828static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1829{
1830 /*
1831 * This really needs some careful tuning. While we shouldn't be too gready since
1832 * that'll cause the rest of the system to stop up, we shouldn't be too nice either
1833 * because that'll cause us to stop up.
1834 *
1835 * The current logic is to use the default interval when there is no lag worth
1836 * mentioning, but when we start accumulating lag we don't bother yielding at all.
1837 *
1838 * (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1839 * so the lag is up to date.)
1840 */
1841 const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1842 if ( u64Lag < 50000000 /* 50ms */
1843 || ( u64Lag < 1000000000 /* 1s */
1844 && RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1845 )
1846 {
1847 uint64_t u64Elapsed = RTTimeNanoTS();
1848 pVM->vmm.s.u64LastYield = u64Elapsed;
1849
1850 RTThreadYield();
1851
1852#ifdef LOG_ENABLED
1853 u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1854 Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1855#endif
1856 }
1857 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1858}
1859
1860
1861/**
1862 * Acquire global VM lock.
1863 *
1864 * @returns VBox status code
1865 * @param pVM The VM to operate on.
1866 *
1867 * @remarks The global VMM lock isn't really used for anything any longer.
1868 */
1869VMMR3DECL(int) VMMR3Lock(PVM pVM)
1870{
1871 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1872}
1873
1874
1875/**
1876 * Release global VM lock.
1877 *
1878 * @returns VBox status code
1879 * @param pVM The VM to operate on.
1880 *
1881 * @remarks The global VMM lock isn't really used for anything any longer.
1882 */
1883VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1884{
1885 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1886}
1887
1888
1889/**
1890 * Return global VM lock owner.
1891 *
1892 * @returns Thread id of owner.
1893 * @returns NIL_RTTHREAD if no owner.
1894 * @param pVM The VM to operate on.
1895 *
1896 * @remarks The global VMM lock isn't really used for anything any longer.
1897 */
1898VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1899{
1900 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1901}
1902
1903
1904/**
1905 * Checks if the current thread is the owner of the global VM lock.
1906 *
1907 * @returns true if owner.
1908 * @returns false if not owner.
1909 * @param pVM The VM to operate on.
1910 *
1911 * @remarks The global VMM lock isn't really used for anything any longer.
1912 */
1913VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1914{
1915 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1916}
1917
1918
1919/**
1920 * Executes guest code in the raw-mode context.
1921 *
1922 * @param pVM VM handle.
1923 */
1924VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1925{
1926 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1927
1928 /*
1929 * Set the EIP and ESP.
1930 */
1931 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1932 ? pVM->vmm.s.pfnCPUMRCResumeGuestV86
1933 : pVM->vmm.s.pfnCPUMRCResumeGuest);
1934 CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC);
1935
1936 /*
1937 * We hide log flushes (outer) and hypervisor interrupts (inner).
1938 */
1939 for (;;)
1940 {
1941 int rc;
1942 do
1943 {
1944#ifdef NO_SUPCALLR0VMM
1945 rc = VERR_GENERAL_FAILURE;
1946#else
1947 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
1948 if (RT_LIKELY(rc == VINF_SUCCESS))
1949 rc = pVM->vmm.s.iLastGZRc;
1950#endif
1951 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1952
1953 /*
1954 * Flush the logs.
1955 */
1956#ifdef LOG_ENABLED
1957 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
1958 if ( pLogger
1959 && pLogger->offScratch > 0)
1960 RTLogFlushRC(NULL, pLogger);
1961#endif
1962#ifdef VBOX_WITH_RC_RELEASE_LOGGING
1963 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
1964 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1965 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
1966#endif
1967 if (rc != VINF_VMM_CALL_HOST)
1968 {
1969 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1970 return rc;
1971 }
1972 rc = vmmR3ServiceCallHostRequest(pVM);
1973 if (VBOX_FAILURE(rc))
1974 return rc;
1975 /* Resume GC */
1976 }
1977}
1978
1979
1980/**
1981 * Executes guest code (Intel VT-x and AMD-V).
1982 *
1983 * @param pVM VM handle.
1984 */
1985VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1986{
1987 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1988
1989 for (;;)
1990 {
1991 int rc;
1992 do
1993 {
1994#ifdef NO_SUPCALLR0VMM
1995 rc = VERR_GENERAL_FAILURE;
1996#else
1997 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN);
1998 if (RT_LIKELY(rc == VINF_SUCCESS))
1999 rc = pVM->vmm.s.iLastGZRc;
2000#endif
2001 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2002
2003#ifdef LOG_ENABLED
2004 /*
2005 * Flush the log
2006 */
2007 PVMMR0LOGGER pR0LoggerR3 = pVM->vmm.s.pR0LoggerR3;
2008 if ( pR0LoggerR3
2009 && pR0LoggerR3->Logger.offScratch > 0)
2010 RTLogFlushToLogger(&pR0LoggerR3->Logger, NULL);
2011#endif /* !LOG_ENABLED */
2012 if (rc != VINF_VMM_CALL_HOST)
2013 {
2014 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2015 return rc;
2016 }
2017 rc = vmmR3ServiceCallHostRequest(pVM);
2018 if (VBOX_FAILURE(rc))
2019 return rc;
2020 /* Resume R0 */
2021 }
2022}
2023
2024/**
2025 * Calls GC a function.
2026 *
2027 * @param pVM The VM handle.
2028 * @param GCPtrEntry The GC function address.
2029 * @param cArgs The number of arguments in the ....
2030 * @param ... Arguments to the function.
2031 */
2032VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, ...)
2033{
2034 va_list args;
2035 va_start(args, cArgs);
2036 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
2037 va_end(args);
2038 return rc;
2039}
2040
2041
2042/**
2043 * Calls GC a function.
2044 *
2045 * @param pVM The VM handle.
2046 * @param GCPtrEntry The GC function address.
2047 * @param cArgs The number of arguments in the ....
2048 * @param args Arguments to the function.
2049 */
2050VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, va_list args)
2051{
2052 Log2(("VMMR3CallGCV: GCPtrEntry=%VRv cArgs=%d\n", GCPtrEntry, cArgs));
2053
2054 /*
2055 * Setup the call frame using the trampoline.
2056 */
2057 CPUMHyperSetCtxCore(pVM, NULL);
2058 memset(pVM->vmm.s.pbEMTStackR3, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2059 CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC - cArgs * sizeof(RTGCUINTPTR32));
2060 PRTGCUINTPTR32 pFrame = (PRTGCUINTPTR32)(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE) - cArgs;
2061 int i = cArgs;
2062 while (i-- > 0)
2063 *pFrame++ = va_arg(args, RTGCUINTPTR32);
2064
2065 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR32)); /* stack frame size */
2066 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2067 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnCallTrampolineRC);
2068
2069 /*
2070 * We hide log flushes (outer) and hypervisor interrupts (inner).
2071 */
2072 for (;;)
2073 {
2074 int rc;
2075 do
2076 {
2077#ifdef NO_SUPCALLR0VMM
2078 rc = VERR_GENERAL_FAILURE;
2079#else
2080 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2081 if (RT_LIKELY(rc == VINF_SUCCESS))
2082 rc = pVM->vmm.s.iLastGZRc;
2083#endif
2084 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2085
2086 /*
2087 * Flush the logs.
2088 */
2089#ifdef LOG_ENABLED
2090 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
2091 if ( pLogger
2092 && pLogger->offScratch > 0)
2093 RTLogFlushRC(NULL, pLogger);
2094#endif
2095#ifdef VBOX_WITH_RC_RELEASE_LOGGING
2096 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
2097 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2098 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
2099#endif
2100 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2101 VMMR3FatalDump(pVM, rc);
2102 if (rc != VINF_VMM_CALL_HOST)
2103 {
2104 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2105 return rc;
2106 }
2107 rc = vmmR3ServiceCallHostRequest(pVM);
2108 if (VBOX_FAILURE(rc))
2109 return rc;
2110 }
2111}
2112
2113
2114/**
2115 * Resumes executing hypervisor code when interrupted by a queue flush or a
2116 * debug event.
2117 *
2118 * @returns VBox status code.
2119 * @param pVM VM handle.
2120 */
2121VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2122{
2123 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2124
2125 /*
2126 * We hide log flushes (outer) and hypervisor interrupts (inner).
2127 */
2128 for (;;)
2129 {
2130 int rc;
2131 do
2132 {
2133#ifdef NO_SUPCALLR0VMM
2134 rc = VERR_GENERAL_FAILURE;
2135#else
2136 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2137 if (RT_LIKELY(rc == VINF_SUCCESS))
2138 rc = pVM->vmm.s.iLastGZRc;
2139#endif
2140 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2141
2142 /*
2143 * Flush the loggers,
2144 */
2145#ifdef LOG_ENABLED
2146 PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
2147 if ( pLogger
2148 && pLogger->offScratch > 0)
2149 RTLogFlushRC(NULL, pLogger);
2150#endif
2151#ifdef VBOX_WITH_RC_RELEASE_LOGGING
2152 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
2153 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2154 RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
2155#endif
2156 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2157 VMMR3FatalDump(pVM, rc);
2158 if (rc != VINF_VMM_CALL_HOST)
2159 {
2160 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2161 return rc;
2162 }
2163 rc = vmmR3ServiceCallHostRequest(pVM);
2164 if (VBOX_FAILURE(rc))
2165 return rc;
2166 }
2167}
2168
2169
2170/**
2171 * Service a call to the ring-3 host code.
2172 *
2173 * @returns VBox status code.
2174 * @param pVM VM handle.
2175 * @remark Careful with critsects.
2176 */
2177static int vmmR3ServiceCallHostRequest(PVM pVM)
2178{
2179 switch (pVM->vmm.s.enmCallHostOperation)
2180 {
2181 /*
2182 * Acquire the PDM lock.
2183 */
2184 case VMMCALLHOST_PDM_LOCK:
2185 {
2186 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2187 break;
2188 }
2189
2190 /*
2191 * Flush a PDM queue.
2192 */
2193 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2194 {
2195 PDMR3QueueFlushWorker(pVM, NULL);
2196 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2197 break;
2198 }
2199
2200 /*
2201 * Grow the PGM pool.
2202 */
2203 case VMMCALLHOST_PGM_POOL_GROW:
2204 {
2205 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2206 break;
2207 }
2208
2209 /*
2210 * Maps an page allocation chunk into ring-3 so ring-0 can use it.
2211 */
2212 case VMMCALLHOST_PGM_MAP_CHUNK:
2213 {
2214 pVM->vmm.s.rcCallHost = PGMR3PhysChunkMap(pVM, pVM->vmm.s.u64CallHostArg);
2215 break;
2216 }
2217
2218 /*
2219 * Allocates more handy pages.
2220 */
2221 case VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES:
2222 {
2223 pVM->vmm.s.rcCallHost = PGMR3PhysAllocateHandyPages(pVM);
2224 break;
2225 }
2226#ifndef VBOX_WITH_NEW_PHYS_CODE
2227
2228 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2229 {
2230 const RTGCPHYS GCPhys = pVM->vmm.s.u64CallHostArg;
2231 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, &GCPhys);
2232 break;
2233 }
2234#endif
2235
2236 /*
2237 * Acquire the PGM lock.
2238 */
2239 case VMMCALLHOST_PGM_LOCK:
2240 {
2241 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2242 break;
2243 }
2244
2245 /*
2246 * Flush REM handler notifications.
2247 */
2248 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2249 {
2250 REMR3ReplayHandlerNotifications(pVM);
2251 break;
2252 }
2253
2254 /*
2255 * This is a noop. We just take this route to avoid unnecessary
2256 * tests in the loops.
2257 */
2258 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2259 break;
2260
2261 /*
2262 * Set the VM error message.
2263 */
2264 case VMMCALLHOST_VM_SET_ERROR:
2265 VMR3SetErrorWorker(pVM);
2266 break;
2267
2268 /*
2269 * Set the VM runtime error message.
2270 */
2271 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2272 VMR3SetRuntimeErrorWorker(pVM);
2273 break;
2274
2275 /*
2276 * Signal a ring 0 hypervisor assertion.
2277 * Cancel the longjmp operation that's in progress.
2278 */
2279 case VMMCALLHOST_VM_R0_ASSERTION:
2280 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2281 pVM->vmm.s.CallHostR0JmpBuf.fInRing3Call = false;
2282#ifdef RT_ARCH_X86
2283 pVM->vmm.s.CallHostR0JmpBuf.eip = 0;
2284#else
2285 pVM->vmm.s.CallHostR0JmpBuf.rip = 0;
2286#endif
2287 LogRel((pVM->vmm.s.szRing0AssertMsg1));
2288 LogRel((pVM->vmm.s.szRing0AssertMsg2));
2289 return VERR_VMM_RING0_ASSERTION;
2290
2291 default:
2292 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2293 return VERR_INTERNAL_ERROR;
2294 }
2295
2296 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2297 return VINF_SUCCESS;
2298}
2299
2300
2301/**
2302 * Displays the Force action Flags.
2303 *
2304 * @param pVM The VM handle.
2305 * @param pHlp The output helpers.
2306 * @param pszArgs The additional arguments (ignored).
2307 */
2308static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2309{
2310 const uint32_t fForcedActions = pVM->fForcedActions;
2311
2312 pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2313
2314 /* show the flag mnemonics */
2315 int c = 0;
2316 uint32_t f = fForcedActions;
2317#define PRINT_FLAG(flag) do { \
2318 if (f & (flag)) \
2319 { \
2320 static const char *s_psz = #flag; \
2321 if (!(c % 6)) \
2322 pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2323 else \
2324 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2325 c++; \
2326 f &= ~(flag); \
2327 } \
2328 } while (0)
2329 PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2330 PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2331 PRINT_FLAG(VM_FF_TIMER);
2332 PRINT_FLAG(VM_FF_PDM_QUEUES);
2333 PRINT_FLAG(VM_FF_PDM_DMA);
2334 PRINT_FLAG(VM_FF_PDM_CRITSECT);
2335 PRINT_FLAG(VM_FF_DBGF);
2336 PRINT_FLAG(VM_FF_REQUEST);
2337 PRINT_FLAG(VM_FF_TERMINATE);
2338 PRINT_FLAG(VM_FF_RESET);
2339 PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2340 PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2341 PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2342 PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2343 PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2344 PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2345 PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2346 PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2347 PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2348 PRINT_FLAG(VM_FF_TO_R3);
2349 PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2350 if (f)
2351 pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2352 else
2353 pHlp->pfnPrintf(pHlp, "\n");
2354#undef PRINT_FLAG
2355
2356 /* the groups */
2357 c = 0;
2358#define PRINT_GROUP(grp) do { \
2359 if (fForcedActions & (grp)) \
2360 { \
2361 static const char *s_psz = #grp; \
2362 if (!(c % 5)) \
2363 pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2364 else \
2365 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2366 c++; \
2367 } \
2368 } while (0)
2369 PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2370 PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2371 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2372 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2373 PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2374 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2375 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2376 PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2377 PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2378 if (c)
2379 pHlp->pfnPrintf(pHlp, "\n");
2380#undef PRINT_GROUP
2381}
2382
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