VMM.cpp@ 9026

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1	/* $Id: VMM.cpp 8841 2008-05-15 11:05:07Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor Core.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	//#define NO_SUPCALLR0VMM
23
24	/** @page pg_vmm VMM - The Virtual Machine Monitor
25	*
26	* !Revise this! It's already incorrect!
27	*
28	* The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
29	* manages the alternate reality; controlling the virtualization, managing
30	* resources, tracking CPU state, it's resources and so on...
31	*
32	* We will split the VMM into smaller entities:
33	*
34	* - Virtual Machine Core Monitor (VMCM), which purpose it is to
35	* provide ring and world switching, that including routing
36	* interrupts to the host OS and traps to the appropriate trap
37	* handlers. It will implement an external interface for
38	* managing trap handlers.
39	*
40	* - CPU Monitor (CM), tracking the state of the CPU (in the alternate
41	* reality) and implementing external interfaces to read and change
42	* the state.
43	*
44	* - Memory Monitor (MM), which purpose it is to virtualize physical
45	* pages, segment descriptor tables, interrupt descriptor tables, task
46	* segments, and keep track of all memory providing external interfaces
47	* to access content and map pages. (Internally splitt into smaller entities!)
48	*
49	* - IO Monitor (IOM), which virtualizes in and out I/O operations. It
50	* interacts with the MM to implement memory mapped I/O. External
51	* interfaces for adding and removing I/O ranges are implemented.
52	*
53	* - External Interrupt Monitor (EIM), which purpose it is to manage
54	* interrupts generated by virtual devices. This monitor provides
55	* an interfaces for raising interrupts which is accessible at any
56	* time and from all thread.
57	* <p>
58	* A subentity of the EIM is the vitual Programmable Interrupt
59	* Controller Device (VPICD), and perhaps a virtual I/O Advanced
60	* Programmable Interrupt Controller Device (VAPICD).
61	*
62	* - Direct Memory Access Monitor (DMAM), which purpose it is to support
63	* virtual device using the DMA controller. Interfaces must be as the
64	* EIM interfaces independent and threadable.
65	* <p>
66	* A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
67	*
68	*
69	* Entities working on a higher level:
70	*
71	* - Device Manager (DM), which is a support facility for virtualized
72	* hardware. This provides generic facilities for efficient device
73	* virtualization. It will manage device attaching and detaching
74	* conversing with EIM and IOM.
75	*
76	* - Debugger Facility (DBGF) provides the basic features for
77	* debugging the alternate reality execution.
78	*
79	*
80	*
81	* @section pg_vmm_s_use_cases Use Cases
82	*
83	* @subsection pg_vmm_s_use_case_boot Bootstrap
84	*
85	* - Basic Init:
86	* - Init SUPDRV.
87	*
88	* - Init Virtual Machine Instance:
89	* - Load settings.
90	* - Check resource requirements (memory, com, stuff).
91	*
92	* - Init Host Ring 3 part:
93	* - Init Core code.
94	* - Load Pluggable Components.
95	* - Init Pluggable Components.
96	*
97	* - Init Host Ring 0 part:
98	* - Load Core (core = core components like VMM, RMI, CA, and so on) code.
99	* - Init Core code.
100	* - Load Pluggable Component code.
101	* - Init Pluggable Component code.
102	*
103	* - Allocate first chunk of memory and pin it down. This block of memory
104	* will fit the following pieces:
105	* - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
106	* (This is available from everywhere (at different addresses though)).
107	* - VMM Guest Context code.
108	* - Pluggable devices Guest Context code.
109	* - Page tables (directory and everything) for the VMM Guest
110	*
111	* - Setup Guest (Ring 0) part:
112	* - Setup initial page tables (i.e. directory all the stuff).
113	* - Load Core Guest Context code.
114	* - Load Pluggable Devices Guest Context code.
115	*
116	*
117	*/
118
119
120	/*******************************************************************************
121	* Header Files *
122	*******************************************************************************/
123	#define LOG_GROUP LOG_GROUP_VMM
124	#include <VBox/vmm.h>
125	#include <VBox/vmapi.h>
126	#include <VBox/pgm.h>
127	#include <VBox/cfgm.h>
128	#include <VBox/pdmqueue.h>
129	#include <VBox/pdmapi.h>
130	#include <VBox/cpum.h>
131	#include <VBox/mm.h>
132	#include <VBox/iom.h>
133	#include <VBox/trpm.h>
134	#include <VBox/selm.h>
135	#include <VBox/em.h>
136	#include <VBox/sup.h>
137	#include <VBox/dbgf.h>
138	#include <VBox/csam.h>
139	#include <VBox/patm.h>
140	#include <VBox/rem.h>
141	#include <VBox/ssm.h>
142	#include <VBox/tm.h>
143	#include "VMMInternal.h"
144	#include "VMMSwitcher/VMMSwitcher.h"
145	#include <VBox/vm.h>
146	#include <VBox/err.h>
147	#include <VBox/param.h>
148	#include <VBox/version.h>
149	#include <VBox/x86.h>
150	#include <VBox/hwaccm.h>
151	#include <iprt/assert.h>
152	#include <iprt/alloc.h>
153	#include <iprt/asm.h>
154	#include <iprt/time.h>
155	#include <iprt/stream.h>
156	#include <iprt/string.h>
157	#include <iprt/stdarg.h>
158	#include <iprt/ctype.h>
159
160
161
162	/** The saved state version. */
163	#define VMM_SAVED_STATE_VERSION 3
164
165
166	/*******************************************************************************
167	* Internal Functions *
168	*******************************************************************************/
169	static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
170	static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
171	static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
172	static int vmmR3ServiceCallHostRequest(PVM pVM);
173	static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
174
175
176	/*******************************************************************************
177	* Global Variables *
178	*******************************************************************************/
179	/** Array of switcher defininitions.
180	* The type and index shall match!
181	*/
182	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
183	{
184	NULL, /* invalid entry */
185	#ifndef RT_ARCH_AMD64
186	&vmmR3Switcher32BitTo32Bit_Def,
187	&vmmR3Switcher32BitToPAE_Def,
188	NULL, //&vmmR3Switcher32BitToAMD64_Def,
189	&vmmR3SwitcherPAETo32Bit_Def,
190	&vmmR3SwitcherPAEToPAE_Def,
191	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
192	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
193	&vmmR3SwitcherAMD64ToPAE_Def,
194	# else
195	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
196	# endif
197	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
198	#else
199	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
200	NULL, //&vmmR3Switcher32BitToPAE_Def,
201	NULL, //&vmmR3Switcher32BitToAMD64_Def,
202	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
203	NULL, //&vmmR3SwitcherPAEToPAE_Def,
204	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
205	&vmmR3SwitcherAMD64ToPAE_Def,
206	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
207	#endif
208	};
209
210
211
212	/**
213	* Initiates the core code.
214	*
215	* This is core per VM code which might need fixups and/or for ease of use
216	* are put on linear contiguous backing.
217	*
218	* @returns VBox status code.
219	* @param pVM Pointer to VM structure.
220	*/
221	static int vmmR3InitCoreCode(PVM pVM)
222	{
223	/*
224	* Calc the size.
225	*/
226	unsigned cbCoreCode = 0;
227	for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
228	{
229	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
230	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
231	if (pSwitcher)
232	{
233	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
234	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
235	}
236	}
237
238	/*
239	* Allocate continguous pages for switchers and deal with
240	* conflicts in the intermediate mapping of the code.
241	*/
242	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
243	pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
244	int rc = VERR_NO_MEMORY;
245	if (pVM->vmm.s.pvHCCoreCodeR3)
246	{
247	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
248	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
249	{
250	/* try more allocations. */
251	struct
252	{
253	RTR0PTR pvR0;
254	void *pvR3;
255	RTHCPHYS HCPhys;
256	RTUINT cb;
257	} aBadTries[128];
258	unsigned i = 0;
259	do
260	{
261	aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
262	aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
263	aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
264	i++;
265	pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
266	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
267	pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
268	if (!pVM->vmm.s.pvHCCoreCodeR3)
269	break;
270	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
271	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
272	&& i < RT_ELEMENTS(aBadTries) - 1);
273
274	/* cleanup */
275	if (VBOX_FAILURE(rc))
276	{
277	aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
278	aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
279	aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
280	aBadTries[i].cb = pVM->vmm.s.cbCoreCode;
281	i++;
282	LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
283	}
284	while (i-- > 0)
285	{
286	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
287	i, aBadTries[i].pvR3, aBadTries[i].pvR0, aBadTries[i].HCPhys));
288	SUPContFree(aBadTries[i].pvR3, aBadTries[i].cb >> PAGE_SHIFT);
289	}
290	}
291	}
292	if (VBOX_SUCCESS(rc))
293	{
294	/*
295	* copy the code.
296	*/
297	for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
298	{
299	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
300	if (pSwitcher)
301	memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
302	pSwitcher->pvCode, pSwitcher->cbCode);
303	}
304
305	/*
306	* Map the code into the GC address space.
307	*/
308	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &pVM->vmm.s.pvGCCoreCode);
309	if (VBOX_SUCCESS(rc))
310	{
311	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
312	LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VGv Phys=%VHp cb=%#x\n",
313	pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
314
315	/*
316	* Finally, PGM probably have selected a switcher already but we need
317	* to do get the addresses so we'll reselect it.
318	* This may legally fail so, we're ignoring the rc.
319	*/
320	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
321	return rc;
322	}
323
324	/* shit */
325	AssertMsgFailed(("PGMR3Map(,%VGv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
326	SUPContFree(pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
327	}
328	else
329	VMSetError(pVM, rc, RT_SRC_POS,
330	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
331	cbCoreCode);
332
333	pVM->vmm.s.pvHCCoreCodeR3 = NULL;
334	pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
335	pVM->vmm.s.pvGCCoreCode = 0;
336	return rc;
337	}
338
339
340	/**
341	* Initializes the VMM.
342	*
343	* @returns VBox status code.
344	* @param pVM The VM to operate on.
345	*/
346	VMMR3DECL(int) VMMR3Init(PVM pVM)
347	{
348	LogFlow(("VMMR3Init\n"));
349
350	/*
351	* Assert alignment, sizes and order.
352	*/
353	AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
354	AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
355	("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
356	sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
357
358	/*
359	* Init basic VM VMM members.
360	*/
361	pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
362	int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
363	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
364	pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
365	//pVM->vmm.s.cYieldEveryMillies = 8; //debugging
366	else
367	AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
368
369	/* GC switchers are enabled by default. Turned off by HWACCM. */
370	pVM->vmm.s.fSwitcherDisabled = false;
371
372	/*
373	* Register the saved state data unit.
374	*/
375	rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
376	NULL, vmmR3Save, NULL,
377	NULL, vmmR3Load, NULL);
378	if (VBOX_FAILURE(rc))
379	return rc;
380
381	/*
382	* Register the Ring-0 VM handle with the session for fast ioctl calls.
383	*/
384	rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
385	if (VBOX_FAILURE(rc))
386	return rc;
387
388	/*
389	* Init core code.
390	*/
391	rc = vmmR3InitCoreCode(pVM);
392	if (VBOX_SUCCESS(rc))
393	{
394	/*
395	* Allocate & init VMM GC stack.
396	* The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
397	* (The page protection is modifed during R3 init completion.)
398	*/
399	#ifdef VBOX_STRICT_VMM_STACK
400	rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
401	#else
402	rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
403	#endif
404	if (VBOX_SUCCESS(rc))
405	{
406	/* Set HC and GC stack pointers to top of stack. */
407	pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
408	pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
409	pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
410	AssertRelease(pVM->vmm.s.pbGCStack);
411
412	/* Set hypervisor eip. */
413	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
414
415	/*
416	* Allocate GC & R0 Logger instances (they are finalized in the relocator).
417	*/
418	#ifdef LOG_ENABLED
419	PRTLOGGER pLogger = RTLogDefaultInstance();
420	if (pLogger)
421	{
422	pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pLogger->cGroups]);
423	rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
424	if (VBOX_SUCCESS(rc))
425	{
426	pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
427
428	/*
429	* Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
430	* you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
431	*
432	* If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
433	* to not stub all the log functions.
434	*
435	* You might also wish to enable the AssertMsg1/2 overrides in VMMR0.cpp when enabling this.
436	*/
437	# if defined(DEBUG_sandervl) \|\| defined(DEBUG_frank)
438	rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
439	0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
440	if (VBOX_SUCCESS(rc))
441	{
442	pVM->vmm.s.pR0Logger->pVM = pVM->pVMR0;
443	//pVM->vmm.s.pR0Logger->fCreated = false;
444	pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
445	}
446	# endif
447	}
448	}
449	#endif /* LOG_ENABLED */
450
451	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
452	/*
453	* Allocate GC Release Logger instances (finalized in the relocator).
454	*/
455	if (VBOX_SUCCESS(rc))
456	{
457	PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
458	if (pRelLogger)
459	{
460	pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pRelLogger->cGroups]);
461	rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
462	if (VBOX_SUCCESS(rc))
463	pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
464	}
465	}
466	#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
467
468	#ifdef VBOX_WITH_NMI
469	/*
470	* Allocate mapping for the host APIC.
471	*/
472	if (VBOX_SUCCESS(rc))
473	{
474	rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
475	AssertRC(rc);
476	}
477	#endif
478	if (VBOX_SUCCESS(rc))
479	{
480	rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
481	if (VBOX_SUCCESS(rc))
482	{
483	/*
484	* Debug info.
485	*/
486	DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
487
488	/*
489	* Statistics.
490	*/
491	STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
492	STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
493	STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
494	STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
495	STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
496	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
497	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
498	STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
499	STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
500	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
501	STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
502	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
503	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
504	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
505	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
506	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
507	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
508	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
509	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
510	STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
511	STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
512	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
513	STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
514	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
515	STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
516	STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
517	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
518	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
519	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
520	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
521	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
522	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
523	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
524	STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
525	STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
526	STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
527	STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
528	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
529	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
530	STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
531	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
532	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
533	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
534	STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
535	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
536	STAM_REG(pVM, &pVM->vmm.s.StatGCRetHyperAssertion, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/HyperAssert", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
537	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
538	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
539	STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
540	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
541
542	return VINF_SUCCESS;
543	}
544	AssertRC(rc);
545	}
546	}
547	/** @todo: Need failure cleanup. */
548
549	//more todo in here?
550	//if (VBOX_SUCCESS(rc))
551	//{
552	//}
553	//int rc2 = vmmR3TermCoreCode(pVM);
554	//AssertRC(rc2));
555	}
556
557	return rc;
558	}
559
560
561	/**
562	* Ring-3 init finalizing.
563	*
564	* @returns VBox status code.
565	* @param pVM The VM handle.
566	*/
567	VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
568	{
569	#ifdef VBOX_STRICT_VMM_STACK
570	/*
571	* Two inaccessible pages at each sides of the stack to catch over/under-flows.
572	*/
573	memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
574	PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
575	RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
576
577	memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
578	PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
579	RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
580	#endif
581
582	/*
583	* Set page attributes to r/w for stack pages.
584	*/
585	int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D \| X86_PTE_RW);
586	AssertRC(rc);
587	if (VBOX_SUCCESS(rc))
588	{
589	/*
590	* Create the EMT yield timer.
591	*/
592	rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
593	if (VBOX_SUCCESS(rc))
594	rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
595	}
596	#ifdef VBOX_WITH_NMI
597	/*
598	* Map the host APIC into GC - This may be host os specific!
599	*/
600	if (VBOX_SUCCESS(rc))
601	rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
602	X86_PTE_P \| X86_PTE_RW \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A \| X86_PTE_D);
603	#endif
604	return rc;
605	}
606
607
608	/**
609	* Initializes the R0 VMM.
610	*
611	* @returns VBox status code.
612	* @param pVM The VM to operate on.
613	*/
614	VMMR3DECL(int) VMMR3InitR0(PVM pVM)
615	{
616	int rc;
617
618	/*
619	* Initialize the ring-0 logger if we haven't done so yet.
620	*/
621	if ( pVM->vmm.s.pR0Logger
622	&& !pVM->vmm.s.pR0Logger->fCreated)
623	{
624	rc = VMMR3UpdateLoggers(pVM);
625	if (VBOX_FAILURE(rc))
626	return rc;
627	}
628
629	/*
630	* Call Ring-0 entry with init code.
631	*/
632	for (;;)
633	{
634	#ifdef NO_SUPCALLR0VMM
635	//rc = VERR_GENERAL_FAILURE;
636	rc = VINF_SUCCESS;
637	#else
638	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, VBOX_VERSION, NULL);
639	#endif
640	if ( pVM->vmm.s.pR0Logger
641	&& pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
642	RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
643	if (rc != VINF_VMM_CALL_HOST)
644	break;
645	rc = vmmR3ServiceCallHostRequest(pVM);
646	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
647	break;
648	/* Resume R0 */
649	}
650
651	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
652	{
653	LogRel(("R0 init failed, rc=%Vra\n", rc));
654	if (VBOX_SUCCESS(rc))
655	rc = VERR_INTERNAL_ERROR;
656	}
657	return rc;
658	}
659
660
661	/**
662	* Initializes the GC VMM.
663	*
664	* @returns VBox status code.
665	* @param pVM The VM to operate on.
666	*/
667	VMMR3DECL(int) VMMR3InitGC(PVM pVM)
668	{
669	/* In VMX mode, there's no need to init GC. */
670	if (pVM->vmm.s.fSwitcherDisabled)
671	return VINF_SUCCESS;
672
673	/*
674	* Call VMMGCInit():
675	* -# resolve the address.
676	* -# setup stackframe and EIP to use the trampoline.
677	* -# do a generic hypervisor call.
678	*/
679	RTGCPTR GCPtrEP;
680	int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
681	if (VBOX_SUCCESS(rc))
682	{
683	CPUMHyperSetCtxCore(pVM, NULL);
684	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
685	uint64_t u64TS = RTTimeProgramStartNanoTS();
686	#if GC_ARCH_BITS == 32
687	CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
688	CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
689	#else /* 64-bit GC */
690	CPUMPushHyper(pVM, u64TS); /* Param 3: The program startup TS. */
691	#endif
692	CPUMPushHyper(pVM, VBOX_VERSION); /* Param 2: Version argument. */
693	CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
694	CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
695	CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* trampoline param: stacksize. */
696	CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
697	CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
698
699	for (;;)
700	{
701	#ifdef NO_SUPCALLR0VMM
702	//rc = VERR_GENERAL_FAILURE;
703	rc = VINF_SUCCESS;
704	#else
705	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
706	#endif
707	#ifdef LOG_ENABLED
708	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
709	if ( pLogger
710	&& pLogger->offScratch > 0)
711	RTLogFlushGC(NULL, pLogger);
712	#endif
713	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
714	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
715	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
716	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
717	#endif
718	if (rc != VINF_VMM_CALL_HOST)
719	break;
720	rc = vmmR3ServiceCallHostRequest(pVM);
721	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
722	break;
723	}
724
725	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
726	{
727	VMMR3FatalDump(pVM, rc);
728	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
729	rc = VERR_INTERNAL_ERROR;
730	}
731	AssertRC(rc);
732	}
733	return rc;
734	}
735
736
737	/**
738	* Terminate the VMM bits.
739	*
740	* @returns VINF_SUCCESS.
741	* @param pVM The VM handle.
742	*/
743	VMMR3DECL(int) VMMR3Term(PVM pVM)
744	{
745	/*
746	* Call Ring-0 entry with termination code.
747	*/
748	int rc;
749	for (;;)
750	{
751	#ifdef NO_SUPCALLR0VMM
752	//rc = VERR_GENERAL_FAILURE;
753	rc = VINF_SUCCESS;
754	#else
755	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_TERM, VBOX_VERSION, NULL);
756	#endif
757	if ( pVM->vmm.s.pR0Logger
758	&& pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
759	RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
760	if (rc != VINF_VMM_CALL_HOST)
761	break;
762	rc = vmmR3ServiceCallHostRequest(pVM);
763	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
764	break;
765	/* Resume R0 */
766	}
767	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
768	{
769	LogRel(("VMMR3Term: R0 term failed, rc=%Vra. (warning)\n", rc));
770	if (VBOX_SUCCESS(rc))
771	rc = VERR_INTERNAL_ERROR;
772	}
773
774	#ifdef VBOX_STRICT_VMM_STACK
775	/*
776	* Make the two stack guard pages present again.
777	*/
778	RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
779	RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
780	#endif
781	return rc;
782	}
783
784
785	/**
786	* Applies relocations to data and code managed by this
787	* component. This function will be called at init and
788	* whenever the VMM need to relocate it self inside the GC.
789	*
790	* The VMM will need to apply relocations to the core code.
791	*
792	* @param pVM The VM handle.
793	* @param offDelta The relocation delta.
794	*/
795	VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
796	{
797	LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
798
799	/*
800	* Recalc the GC address.
801	*/
802	pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
803
804	/*
805	* The stack.
806	*/
807	CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
808	pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
809	pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
810
811	/*
812	* All the switchers.
813	*/
814	for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
815	{
816	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
817	if (pSwitcher && pSwitcher->pfnRelocate)
818	{
819	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
820	pSwitcher->pfnRelocate(pVM,
821	pSwitcher,
822	(uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
823	(uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
824	pVM->vmm.s.pvGCCoreCode + off,
825	pVM->vmm.s.HCPhysCoreCode + off);
826	}
827	}
828
829	/*
830	* Recalc the GC address for the current switcher.
831	*/
832	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
833	RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
834	pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
835	pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
836	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
837	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
838	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
839
840	/*
841	* Get other GC entry points.
842	*/
843	int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
844	AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
845
846	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
847	AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
848
849	/*
850	* Update the logger.
851	*/
852	VMMR3UpdateLoggers(pVM);
853	}
854
855
856	/**
857	* Updates the settings for the GC and R0 loggers.
858	*
859	* @returns VBox status code.
860	* @param pVM The VM handle.
861	*/
862	VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
863	{
864	/*
865	* Simply clone the logger instance (for GC).
866	*/
867	int rc = VINF_SUCCESS;
868	RTGCPTR GCPtrLoggerFlush = 0;
869
870	if (pVM->vmm.s.pLoggerHC
871	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
872	\|\| pVM->vmm.s.pRelLoggerHC
873	#endif
874	)
875	{
876	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
877	AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
878	}
879
880	if (pVM->vmm.s.pLoggerHC)
881	{
882	RTGCPTR GCPtrLoggerWrapper = 0;
883	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
884	AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
885	pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
886	rc = RTLogCloneGC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
887	GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
888	AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
889	}
890
891	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
892	if (pVM->vmm.s.pRelLoggerHC)
893	{
894	RTGCPTR GCPtrLoggerWrapper = 0;
895	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
896	AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
897	pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
898	rc = RTLogCloneGC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
899	GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
900	AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
901	}
902	#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
903
904	/*
905	* For the ring-0 EMT logger, we use a per-thread logger
906	* instance in ring-0. Only initialize it once.
907	*/
908	PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
909	if (pR0Logger)
910	{
911	if (!pR0Logger->fCreated)
912	{
913	RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
914	rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
915	AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
916
917	RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
918	rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
919	AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
920
921	rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
922	(PFNRTLOGGER )&pfnLoggerWrapper, (PFNRTLOGFLUSH )&pfnLoggerFlush,
923	RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
924	AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
925	pR0Logger->fCreated = true;
926	}
927
928	rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, RTLOGFLAGS_BUFFERED, 0);
929	AssertRC(rc);
930	}
931
932	return rc;
933	}
934
935
936	/**
937	* Generic switch code relocator.
938	*
939	* @param pVM The VM handle.
940	* @param pSwitcher The switcher definition.
941	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
942	* @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
943	* @param GCPtrCode The guest context address corresponding to pu8Code.
944	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
945	* @param SelCS The hypervisor CS selector.
946	* @param SelDS The hypervisor DS selector.
947	* @param SelTSS The hypervisor TSS selector.
948	* @param GCPtrGDT The GC address of the hypervisor GDT.
949	* @param SelCS64 The 64-bit mode hypervisor CS selector.
950	*/
951	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
952	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
953	{
954	union
955	{
956	const uint8_t *pu8;
957	const uint16_t *pu16;
958	const uint32_t *pu32;
959	const uint64_t *pu64;
960	const void *pv;
961	uintptr_t u;
962	} u;
963	u.pv = pSwitcher->pvFixups;
964
965	/*
966	* Process fixups.
967	*/
968	uint8_t u8;
969	while ((u8 = *u.pu8++) != FIX_THE_END)
970	{
971	/*
972	* Get the source (where to write the fixup).
973	*/
974	uint32_t offSrc = *u.pu32++;
975	Assert(offSrc < pSwitcher->cbCode);
976	union
977	{
978	uint8_t *pu8;
979	uint16_t *pu16;
980	uint32_t *pu32;
981	uint64_t *pu64;
982	uintptr_t u;
983	} uSrc;
984	uSrc.pu8 = pu8CodeR3 + offSrc;
985
986	/* The fixup target and method depends on the type. */
987	switch (u8)
988	{
989	/*
990	* 32-bit relative, source in HC and target in GC.
991	*/
992	case FIX_HC_2_GC_NEAR_REL:
993	{
994	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
995	uint32_t offTrg = *u.pu32++;
996	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
997	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
998	break;
999	}
1000
1001	/*
1002	* 32-bit relative, source in HC and target in ID.
1003	*/
1004	case FIX_HC_2_ID_NEAR_REL:
1005	{
1006	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1007	uint32_t offTrg = *u.pu32++;
1008	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1009	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - ((uintptr_t)pu8CodeR0 + offSrc + 4));
1010	break;
1011	}
1012
1013	/*
1014	* 32-bit relative, source in GC and target in HC.
1015	*/
1016	case FIX_GC_2_HC_NEAR_REL:
1017	{
1018	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1019	uint32_t offTrg = *u.pu32++;
1020	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1021	*uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
1022	break;
1023	}
1024
1025	/*
1026	* 32-bit relative, source in GC and target in ID.
1027	*/
1028	case FIX_GC_2_ID_NEAR_REL:
1029	{
1030	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1031	uint32_t offTrg = *u.pu32++;
1032	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1033	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1034	break;
1035	}
1036
1037	/*
1038	* 32-bit relative, source in ID and target in HC.
1039	*/
1040	case FIX_ID_2_HC_NEAR_REL:
1041	{
1042	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1043	uint32_t offTrg = *u.pu32++;
1044	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1045	*uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1046	break;
1047	}
1048
1049	/*
1050	* 32-bit relative, source in ID and target in HC.
1051	*/
1052	case FIX_ID_2_GC_NEAR_REL:
1053	{
1054	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1055	uint32_t offTrg = *u.pu32++;
1056	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1057	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1058	break;
1059	}
1060
1061	/*
1062	* 16:32 far jump, target in GC.
1063	*/
1064	case FIX_GC_FAR32:
1065	{
1066	uint32_t offTrg = *u.pu32++;
1067	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1068	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1069	*uSrc.pu16++ = SelCS;
1070	break;
1071	}
1072
1073	/*
1074	* Make 32-bit GC pointer given CPUM offset.
1075	*/
1076	case FIX_GC_CPUM_OFF:
1077	{
1078	uint32_t offCPUM = *u.pu32++;
1079	Assert(offCPUM < sizeof(pVM->cpum));
1080	*uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1081	break;
1082	}
1083
1084	/*
1085	* Make 32-bit GC pointer given VM offset.
1086	*/
1087	case FIX_GC_VM_OFF:
1088	{
1089	uint32_t offVM = *u.pu32++;
1090	Assert(offVM < sizeof(VM));
1091	*uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1092	break;
1093	}
1094
1095	/*
1096	* Make 32-bit HC pointer given CPUM offset.
1097	*/
1098	case FIX_HC_CPUM_OFF:
1099	{
1100	uint32_t offCPUM = *u.pu32++;
1101	Assert(offCPUM < sizeof(pVM->cpum));
1102	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1103	break;
1104	}
1105
1106	/*
1107	* Make 32-bit R0 pointer given VM offset.
1108	*/
1109	case FIX_HC_VM_OFF:
1110	{
1111	uint32_t offVM = *u.pu32++;
1112	Assert(offVM < sizeof(VM));
1113	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1114	break;
1115	}
1116
1117	/*
1118	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1119	*/
1120	case FIX_INTER_32BIT_CR3:
1121	{
1122
1123	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1124	break;
1125	}
1126
1127	/*
1128	* Store the PAE CR3 (32-bit) for the intermediate memory context.
1129	*/
1130	case FIX_INTER_PAE_CR3:
1131	{
1132
1133	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1134	break;
1135	}
1136
1137	/*
1138	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1139	*/
1140	case FIX_INTER_AMD64_CR3:
1141	{
1142
1143	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1144	break;
1145	}
1146
1147	/*
1148	* Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1149	*/
1150	case FIX_HYPER_32BIT_CR3:
1151	{
1152
1153	*uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1154	break;
1155	}
1156
1157	/*
1158	* Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1159	*/
1160	case FIX_HYPER_PAE_CR3:
1161	{
1162
1163	*uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1164	break;
1165	}
1166
1167	/*
1168	* Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1169	*/
1170	case FIX_HYPER_AMD64_CR3:
1171	{
1172
1173	*uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1174	break;
1175	}
1176
1177	/*
1178	* Store Hypervisor CS (16-bit).
1179	*/
1180	case FIX_HYPER_CS:
1181	{
1182	*uSrc.pu16 = SelCS;
1183	break;
1184	}
1185
1186	/*
1187	* Store Hypervisor DS (16-bit).
1188	*/
1189	case FIX_HYPER_DS:
1190	{
1191	*uSrc.pu16 = SelDS;
1192	break;
1193	}
1194
1195	/*
1196	* Store Hypervisor TSS (16-bit).
1197	*/
1198	case FIX_HYPER_TSS:
1199	{
1200	*uSrc.pu16 = SelTSS;
1201	break;
1202	}
1203
1204	/*
1205	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1206	*/
1207	case FIX_GC_TSS_GDTE_DW2:
1208	{
1209	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1210	*uSrc.pu32 = (uint32_t)GCPtr;
1211	break;
1212	}
1213
1214
1215	///@todo case FIX_CR4_MASK:
1216	///@todo case FIX_CR4_OSFSXR:
1217
1218	/*
1219	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1220	*/
1221	case FIX_NO_FXSAVE_JMP:
1222	{
1223	uint32_t offTrg = *u.pu32++;
1224	Assert(offTrg < pSwitcher->cbCode);
1225	if (!CPUMSupportsFXSR(pVM))
1226	{
1227	uSrc.pu8++ = 0xe9; / jmp rel32 */
1228	*uSrc.pu32++ = offTrg - (offSrc + 5);
1229	}
1230	else
1231	{
1232	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1233	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1234	}
1235	break;
1236	}
1237
1238	/*
1239	* Insert relative jump to specified target it SYSENTER isn't used by the host.
1240	*/
1241	case FIX_NO_SYSENTER_JMP:
1242	{
1243	uint32_t offTrg = *u.pu32++;
1244	Assert(offTrg < pSwitcher->cbCode);
1245	if (!CPUMIsHostUsingSysEnter(pVM))
1246	{
1247	uSrc.pu8++ = 0xe9; / jmp rel32 */
1248	*uSrc.pu32++ = offTrg - (offSrc + 5);
1249	}
1250	else
1251	{
1252	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1253	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1254	}
1255	break;
1256	}
1257
1258	/*
1259	* Insert relative jump to specified target it SYSENTER isn't used by the host.
1260	*/
1261	case FIX_NO_SYSCALL_JMP:
1262	{
1263	uint32_t offTrg = *u.pu32++;
1264	Assert(offTrg < pSwitcher->cbCode);
1265	if (!CPUMIsHostUsingSysEnter(pVM))
1266	{
1267	uSrc.pu8++ = 0xe9; / jmp rel32 */
1268	*uSrc.pu32++ = offTrg - (offSrc + 5);
1269	}
1270	else
1271	{
1272	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1273	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1274	}
1275	break;
1276	}
1277
1278	/*
1279	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1280	*/
1281	case FIX_HC_32BIT:
1282	{
1283	uint32_t offTrg = *u.pu32++;
1284	Assert(offSrc < pSwitcher->cbCode);
1285	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1286	*uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1287	break;
1288	}
1289
1290	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1291	/*
1292	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1293	*/
1294	case FIX_HC_64BIT:
1295	{
1296	uint32_t offTrg = *u.pu32++;
1297	Assert(offSrc < pSwitcher->cbCode);
1298	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1299	*uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1300	break;
1301	}
1302
1303	/*
1304	* 64-bit HC Code Selector (no argument).
1305	*/
1306	case FIX_HC_64BIT_CS:
1307	{
1308	Assert(offSrc < pSwitcher->cbCode);
1309	#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1310	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
1311	#else
1312	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1313	#endif
1314	break;
1315	}
1316
1317	/*
1318	* 64-bit HC pointer to the CPUM instance data (no argument).
1319	*/
1320	case FIX_HC_64BIT_CPUM:
1321	{
1322	Assert(offSrc < pSwitcher->cbCode);
1323	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1324	break;
1325	}
1326	#endif
1327
1328	/*
1329	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
1330	*/
1331	case FIX_ID_32BIT:
1332	{
1333	uint32_t offTrg = *u.pu32++;
1334	Assert(offSrc < pSwitcher->cbCode);
1335	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1336	*uSrc.pu32 = u32IDCode + offTrg;
1337	break;
1338	}
1339
1340	/*
1341	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
1342	*/
1343	case FIX_ID_64BIT:
1344	{
1345	uint32_t offTrg = *u.pu32++;
1346	Assert(offSrc < pSwitcher->cbCode);
1347	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1348	*uSrc.pu64 = u32IDCode + offTrg;
1349	break;
1350	}
1351
1352	/*
1353	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1354	*/
1355	case FIX_ID_FAR32_TO_64BIT_MODE:
1356	{
1357	uint32_t offTrg = *u.pu32++;
1358	Assert(offSrc < pSwitcher->cbCode);
1359	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1360	*uSrc.pu32++ = u32IDCode + offTrg;
1361	*uSrc.pu16 = SelCS64;
1362	AssertRelease(SelCS64);
1363	break;
1364	}
1365
1366	#ifdef VBOX_WITH_NMI
1367	/*
1368	* 32-bit address to the APIC base.
1369	*/
1370	case FIX_GC_APIC_BASE_32BIT:
1371	{
1372	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1373	break;
1374	}
1375	#endif
1376
1377	default:
1378	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1379	break;
1380	}
1381	}
1382
1383	#ifdef LOG_ENABLED
1384	/*
1385	* If Log2 is enabled disassemble the switcher code.
1386	*
1387	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1388	*/
1389	if (LogIs2Enabled())
1390	{
1391	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
1392	" pu8CodeR0 = %p\n"
1393	" pu8CodeR3 = %p\n"
1394	" GCPtrCode = %VGv\n"
1395	" u32IDCode = %08x\n"
1396	" pVMGC = %VGv\n"
1397	" pCPUMGC = %VGv\n"
1398	" pVMHC = %p\n"
1399	" pCPUMHC = %p\n"
1400	" GCPtrGDT = %VGv\n"
1401	" InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1402	" HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1403	" SelCS = %04x\n"
1404	" SelDS = %04x\n"
1405	" SelCS64 = %04x\n"
1406	" SelTSS = %04x\n",
1407	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1408	pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1409	VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1410	GCPtrGDT,
1411	PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1412	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1413	SelCS, SelDS, SelCS64, SelTSS);
1414
1415	uint32_t offCode = 0;
1416	while (offCode < pSwitcher->cbCode)
1417	{
1418	/*
1419	* Figure out where this is.
1420	*/
1421	const char *pszDesc = NULL;
1422	RTUINTPTR uBase;
1423	uint32_t cbCode;
1424	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1425	{
1426	pszDesc = "HCCode0";
1427	uBase = (RTUINTPTR)pu8CodeR0;
1428	offCode = pSwitcher->offHCCode0;
1429	cbCode = pSwitcher->cbHCCode0;
1430	}
1431	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1432	{
1433	pszDesc = "HCCode1";
1434	uBase = (RTUINTPTR)pu8CodeR0;
1435	offCode = pSwitcher->offHCCode1;
1436	cbCode = pSwitcher->cbHCCode1;
1437	}
1438	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1439	{
1440	pszDesc = "GCCode";
1441	uBase = GCPtrCode;
1442	offCode = pSwitcher->offGCCode;
1443	cbCode = pSwitcher->cbGCCode;
1444	}
1445	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1446	{
1447	pszDesc = "IDCode0";
1448	uBase = u32IDCode;
1449	offCode = pSwitcher->offIDCode0;
1450	cbCode = pSwitcher->cbIDCode0;
1451	}
1452	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1453	{
1454	pszDesc = "IDCode1";
1455	uBase = u32IDCode;
1456	offCode = pSwitcher->offIDCode1;
1457	cbCode = pSwitcher->cbIDCode1;
1458	}
1459	else
1460	{
1461	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1462	offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1463	offCode++;
1464	continue;
1465	}
1466
1467	/*
1468	* Disassemble it.
1469	*/
1470	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1471	DISCPUSTATE Cpu;
1472
1473	memset(&Cpu, 0, sizeof(Cpu));
1474	Cpu.mode = CPUMODE_32BIT;
1475	while (cbCode > 0)
1476	{
1477	/* try label it */
1478	if (pSwitcher->offR0HostToGuest == offCode)
1479	RTLogPrintf(" *R0HostToGuest:\n");
1480	if (pSwitcher->offGCGuestToHost == offCode)
1481	RTLogPrintf(" *GCGuestToHost:\n");
1482	if (pSwitcher->offGCCallTrampoline == offCode)
1483	RTLogPrintf(" *GCCallTrampoline:\n");
1484	if (pSwitcher->offGCGuestToHostAsm == offCode)
1485	RTLogPrintf(" *GCGuestToHostAsm:\n");
1486	if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1487	RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1488	if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1489	RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1490
1491	/* disas */
1492	uint32_t cbInstr = 0;
1493	char szDisas[256];
1494	if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
1495	RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1496	else
1497	{
1498	RTLogPrintf(" %04x: %02x '%c'\n",
1499	offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1500	cbInstr = 1;
1501	}
1502	offCode += cbInstr;
1503	cbCode -= RT_MIN(cbInstr, cbCode);
1504	}
1505	}
1506	}
1507	#endif
1508	}
1509
1510
1511	/**
1512	* Relocator for the 32-Bit to 32-Bit world switcher.
1513	*/
1514	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1515	{
1516	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1517	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1518	}
1519
1520
1521	/**
1522	* Relocator for the 32-Bit to PAE world switcher.
1523	*/
1524	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1525	{
1526	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1527	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1528	}
1529
1530
1531	/**
1532	* Relocator for the PAE to 32-Bit world switcher.
1533	*/
1534	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1535	{
1536	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1537	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1538	}
1539
1540
1541	/**
1542	* Relocator for the PAE to PAE world switcher.
1543	*/
1544	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1545	{
1546	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1547	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1548	}
1549
1550
1551	/**
1552	* Relocator for the AMD64 to PAE world switcher.
1553	*/
1554	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1555	{
1556	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1557	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1558	}
1559
1560
1561	/**
1562	* Gets the pointer to g_szRTAssertMsg1 in GC.
1563	* @returns Pointer to VMMGC::g_szRTAssertMsg1.
1564	* Returns NULL if not present.
1565	* @param pVM The VM handle.
1566	*/
1567	VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1568	{
1569	RTGCPTR GCPtr;
1570	int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1571	if (VBOX_SUCCESS(rc))
1572	return (const char *)MMHyperGC2HC(pVM, GCPtr);
1573	return NULL;
1574	}
1575
1576
1577	/**
1578	* Gets the pointer to g_szRTAssertMsg2 in GC.
1579	* @returns Pointer to VMMGC::g_szRTAssertMsg2.
1580	* Returns NULL if not present.
1581	* @param pVM The VM handle.
1582	*/
1583	VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1584	{
1585	RTGCPTR GCPtr;
1586	int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1587	if (VBOX_SUCCESS(rc))
1588	return (const char *)MMHyperGC2HC(pVM, GCPtr);
1589	return NULL;
1590	}
1591
1592
1593	/**
1594	* Execute state save operation.
1595	*
1596	* @returns VBox status code.
1597	* @param pVM VM Handle.
1598	* @param pSSM SSM operation handle.
1599	*/
1600	static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1601	{
1602	LogFlow(("vmmR3Save:\n"));
1603
1604	/*
1605	* The hypervisor stack.
1606	*/
1607	SSMR3PutGCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1608	RTGCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1609	Assert(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE);
1610	SSMR3PutGCPtr(pSSM, GCPtrESP);
1611	SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1612	return SSMR3PutU32(pSSM, ~0); /* terminator */
1613	}
1614
1615
1616	/**
1617	* Execute state load operation.
1618	*
1619	* @returns VBox status code.
1620	* @param pVM VM Handle.
1621	* @param pSSM SSM operation handle.
1622	* @param u32Version Data layout version.
1623	*/
1624	static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1625	{
1626	LogFlow(("vmmR3Load:\n"));
1627
1628	/*
1629	* Validate version.
1630	*/
1631	if (u32Version != VMM_SAVED_STATE_VERSION)
1632	{
1633	Log(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1634	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1635	}
1636
1637	/*
1638	* Check that the stack is in the same place, or that it's fearly empty.
1639	*/
1640	RTGCPTR GCPtrStackBottom;
1641	SSMR3GetGCPtr(pSSM, &GCPtrStackBottom);
1642	RTGCPTR GCPtrESP;
1643	int rc = SSMR3GetGCPtr(pSSM, &GCPtrESP);
1644	if (VBOX_FAILURE(rc))
1645	return rc;
1646	if ( GCPtrStackBottom == pVM->vmm.s.pbGCStackBottom
1647	\|\| (GCPtrStackBottom - GCPtrESP < 32)) /** @todo This will break if we start preemting the hypervisor. */
1648	{
1649	/*
1650	* We must set the ESP because the CPUM load + PGM load relocations will render
1651	* the ESP in CPUM fatally invalid.
1652	*/
1653	CPUMSetHyperESP(pVM, GCPtrESP);
1654
1655	/* restore the stack. */
1656	SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1657
1658	/* terminator */
1659	uint32_t u32;
1660	rc = SSMR3GetU32(pSSM, &u32);
1661	if (VBOX_FAILURE(rc))
1662	return rc;
1663	if (u32 != ~0U)
1664	{
1665	AssertMsgFailed(("u32=%#x\n", u32));
1666	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1667	}
1668	return VINF_SUCCESS;
1669	}
1670
1671	LogRel(("The stack is not in the same place and it's not empty! GCPtrStackBottom=%VGv pbGCStackBottom=%VGv ESP=%VGv\n",
1672	GCPtrStackBottom, pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1673	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1674	return VINF_SUCCESS; /* ignore this */
1675	AssertFailed();
1676	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1677	}
1678
1679
1680	/**
1681	* Selects the switcher to be used for switching to GC.
1682	*
1683	* @returns VBox status code.
1684	* @param pVM VM handle.
1685	* @param enmSwitcher The new switcher.
1686	* @remark This function may be called before the VMM is initialized.
1687	*/
1688	VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1689	{
1690	/*
1691	* Validate input.
1692	*/
1693	if ( enmSwitcher < VMMSWITCHER_INVALID
1694	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1695	{
1696	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1697	return VERR_INVALID_PARAMETER;
1698	}
1699
1700	/*
1701	* Select the new switcher.
1702	*/
1703	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1704	if (pSwitcher)
1705	{
1706	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1707	pVM->vmm.s.enmSwitcher = enmSwitcher;
1708
1709	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1710	pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1711
1712	RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1713	pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1714	pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1715	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1716	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1717	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1718	return VINF_SUCCESS;
1719	}
1720	return VERR_NOT_IMPLEMENTED;
1721	}
1722
1723	/**
1724	* Disable the switcher logic permanently.
1725	*
1726	* @returns VBox status code.
1727	* @param pVM VM handle.
1728	*/
1729	VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1730	{
1731	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1732	* @code
1733	* mov eax, VERR_INTERNAL_ERROR
1734	* ret
1735	* @endcode
1736	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1737	*/
1738	pVM->vmm.s.fSwitcherDisabled = true;
1739	return VINF_SUCCESS;
1740	}
1741
1742
1743	/**
1744	* Resolve a builtin GC symbol.
1745	* Called by PDM when loading or relocating GC modules.
1746	*
1747	* @returns VBox status
1748	* @param pVM VM Handle.
1749	* @param pszSymbol Symbol to resolv
1750	* @param pGCPtrValue Where to store the symbol value.
1751	* @remark This has to work before VMMR3Relocate() is called.
1752	*/
1753	VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1754	{
1755	if (!strcmp(pszSymbol, "g_Logger"))
1756	{
1757	if (pVM->vmm.s.pLoggerHC)
1758	pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1759	*pGCPtrValue = pVM->vmm.s.pLoggerGC;
1760	}
1761	else if (!strcmp(pszSymbol, "g_RelLogger"))
1762	{
1763	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1764	if (pVM->vmm.s.pRelLoggerHC)
1765	pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1766	*pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1767	#else
1768	*pGCPtrValue = NIL_RTGCPTR;
1769	#endif
1770	}
1771	else
1772	return VERR_SYMBOL_NOT_FOUND;
1773	return VINF_SUCCESS;
1774	}
1775
1776
1777	/**
1778	* Suspends the the CPU yielder.
1779	*
1780	* @param pVM The VM handle.
1781	*/
1782	VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1783	{
1784	if (!pVM->vmm.s.cYieldResumeMillies)
1785	{
1786	uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1787	uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1788	if (u64Now >= u64Expire \|\| u64Expire == ~(uint64_t)0)
1789	pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1790	else
1791	pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1792	TMTimerStop(pVM->vmm.s.pYieldTimer);
1793	}
1794	pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1795	}
1796
1797
1798	/**
1799	* Stops the the CPU yielder.
1800	*
1801	* @param pVM The VM handle.
1802	*/
1803	VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1804	{
1805	if (!pVM->vmm.s.cYieldResumeMillies)
1806	TMTimerStop(pVM->vmm.s.pYieldTimer);
1807	pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1808	pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1809	}
1810
1811
1812	/**
1813	* Resumes the CPU yielder when it has been a suspended or stopped.
1814	*
1815	* @param pVM The VM handle.
1816	*/
1817	VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1818	{
1819	if (pVM->vmm.s.cYieldResumeMillies)
1820	{
1821	TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1822	pVM->vmm.s.cYieldResumeMillies = 0;
1823	}
1824	}
1825
1826
1827	/**
1828	* Internal timer callback function.
1829	*
1830	* @param pVM The VM.
1831	* @param pTimer The timer handle.
1832	* @param pvUser User argument specified upon timer creation.
1833	*/
1834	static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1835	{
1836	/*
1837	* This really needs some careful tuning. While we shouldn't be too gready since
1838	* that'll cause the rest of the system to stop up, we shouldn't be too nice either
1839	* because that'll cause us to stop up.
1840	*
1841	* The current logic is to use the default interval when there is no lag worth
1842	* mentioning, but when we start accumulating lag we don't bother yielding at all.
1843	*
1844	* (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1845	* so the lag is up to date.)
1846	*/
1847	const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1848	if ( u64Lag < 50000000 /* 50ms */
1849	\|\| ( u64Lag < 1000000000 /* 1s */
1850	&& RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1851	)
1852	{
1853	uint64_t u64Elapsed = RTTimeNanoTS();
1854	pVM->vmm.s.u64LastYield = u64Elapsed;
1855
1856	RTThreadYield();
1857
1858	#ifdef LOG_ENABLED
1859	u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1860	Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1861	#endif
1862	}
1863	TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1864	}
1865
1866
1867	/**
1868	* Acquire global VM lock.
1869	*
1870	* @returns VBox status code
1871	* @param pVM The VM to operate on.
1872	*/
1873	VMMR3DECL(int) VMMR3Lock(PVM pVM)
1874	{
1875	return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1876	}
1877
1878
1879	/**
1880	* Release global VM lock.
1881	*
1882	* @returns VBox status code
1883	* @param pVM The VM to operate on.
1884	*/
1885	VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1886	{
1887	return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1888	}
1889
1890
1891	/**
1892	* Return global VM lock owner.
1893	*
1894	* @returns Thread id of owner.
1895	* @returns NIL_RTTHREAD if no owner.
1896	* @param pVM The VM to operate on.
1897	*/
1898	VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1899	{
1900	return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1901	}
1902
1903
1904	/**
1905	* Checks if the current thread is the owner of the global VM lock.
1906	*
1907	* @returns true if owner.
1908	* @returns false if not owner.
1909	* @param pVM The VM to operate on.
1910	*/
1911	VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1912	{
1913	return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1914	}
1915
1916
1917	/**
1918	* Executes guest code.
1919	*
1920	* @param pVM VM handle.
1921	*/
1922	VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1923	{
1924	Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1925
1926	/*
1927	* Set the EIP and ESP.
1928	*/
1929	CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1930	? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1931	: pVM->vmm.s.pfnCPUMGCResumeGuest);
1932	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1933
1934	/*
1935	* We hide log flushes (outer) and hypervisor interrupts (inner).
1936	*/
1937	for (;;)
1938	{
1939	int rc;
1940	do
1941	{
1942	#ifdef NO_SUPCALLR0VMM
1943	rc = VERR_GENERAL_FAILURE;
1944	#else
1945	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
1946	#endif
1947	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1948
1949	/*
1950	* Flush the logs.
1951	*/
1952	#ifdef LOG_ENABLED
1953	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1954	if ( pLogger
1955	&& pLogger->offScratch > 0)
1956	RTLogFlushGC(NULL, pLogger);
1957	#endif
1958	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1959	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1960	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1961	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1962	#endif
1963	if (rc != VINF_VMM_CALL_HOST)
1964	{
1965	Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1966	return rc;
1967	}
1968	rc = vmmR3ServiceCallHostRequest(pVM);
1969	if (VBOX_FAILURE(rc))
1970	return rc;
1971	/* Resume GC */
1972	}
1973	}
1974
1975
1976	/**
1977	* Executes guest code (Intel VT-x and AMD-V).
1978	*
1979	* @param pVM VM handle.
1980	*/
1981	VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1982	{
1983	Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1984
1985	for (;;)
1986	{
1987	int rc;
1988	do
1989	{
1990	#ifdef NO_SUPCALLR0VMM
1991	rc = VERR_GENERAL_FAILURE;
1992	#else
1993	rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN);
1994	#endif
1995	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1996
1997	#ifdef LOG_ENABLED
1998	/*
1999	* Flush the log
2000	*/
2001	PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
2002	if ( pR0Logger
2003	&& pR0Logger->Logger.offScratch > 0)
2004	RTLogFlushToLogger(&pR0Logger->Logger, NULL);
2005	#endif /* !LOG_ENABLED */
2006	if (rc != VINF_VMM_CALL_HOST)
2007	{
2008	Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2009	return rc;
2010	}
2011	rc = vmmR3ServiceCallHostRequest(pVM);
2012	if (VBOX_FAILURE(rc))
2013	return rc;
2014	/* Resume R0 */
2015	}
2016	}
2017
2018	/**
2019	* Calls GC a function.
2020	*
2021	* @param pVM The VM handle.
2022	* @param GCPtrEntry The GC function address.
2023	* @param cArgs The number of arguments in the ....
2024	* @param ... Arguments to the function.
2025	*/
2026	VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, ...)
2027	{
2028	va_list args;
2029	va_start(args, cArgs);
2030	int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
2031	va_end(args);
2032	return rc;
2033	}
2034
2035
2036	/**
2037	* Calls GC a function.
2038	*
2039	* @param pVM The VM handle.
2040	* @param GCPtrEntry The GC function address.
2041	* @param cArgs The number of arguments in the ....
2042	* @param args Arguments to the function.
2043	*/
2044	VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, va_list args)
2045	{
2046	Log2(("VMMR3CallGCV: GCPtrEntry=%VGv cArgs=%d\n", GCPtrEntry, cArgs));
2047
2048	/*
2049	* Setup the call frame using the trampoline.
2050	*/
2051	CPUMHyperSetCtxCore(pVM, NULL);
2052	memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2053	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR));
2054	PRTGCUINTPTR pFrame = (PRTGCUINTPTR)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
2055	int i = cArgs;
2056	while (i-- > 0)
2057	*pFrame++ = va_arg(args, RTGCUINTPTR);
2058
2059	CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR)); /* stack frame size */
2060	CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2061	CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2062
2063	/*
2064	* We hide log flushes (outer) and hypervisor interrupts (inner).
2065	*/
2066	for (;;)
2067	{
2068	int rc;
2069	do
2070	{
2071	#ifdef NO_SUPCALLR0VMM
2072	rc = VERR_GENERAL_FAILURE;
2073	#else
2074	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2075	#endif
2076	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2077
2078	/*
2079	* Flush the logs.
2080	*/
2081	#ifdef LOG_ENABLED
2082	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2083	if ( pLogger
2084	&& pLogger->offScratch > 0)
2085	RTLogFlushGC(NULL, pLogger);
2086	#endif
2087	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2088	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2089	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2090	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2091	#endif
2092	if (rc == VERR_TRPM_PANIC \|\| rc == VERR_TRPM_DONT_PANIC)
2093	VMMR3FatalDump(pVM, rc);
2094	if (rc != VINF_VMM_CALL_HOST)
2095	{
2096	Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2097	return rc;
2098	}
2099	rc = vmmR3ServiceCallHostRequest(pVM);
2100	if (VBOX_FAILURE(rc))
2101	return rc;
2102	}
2103	}
2104
2105
2106	/**
2107	* Resumes executing hypervisor code when interrupted
2108	* by a queue flush or a debug event.
2109	*
2110	* @returns VBox status code.
2111	* @param pVM VM handle.
2112	*/
2113	VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2114	{
2115	Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2116
2117	/*
2118	* We hide log flushes (outer) and hypervisor interrupts (inner).
2119	*/
2120	for (;;)
2121	{
2122	int rc;
2123	do
2124	{
2125	#ifdef NO_SUPCALLR0VMM
2126	rc = VERR_GENERAL_FAILURE;
2127	#else
2128	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2129	#endif
2130	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2131
2132	/*
2133	* Flush the loggers,
2134	*/
2135	#ifdef LOG_ENABLED
2136	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2137	if ( pLogger
2138	&& pLogger->offScratch > 0)
2139	RTLogFlushGC(NULL, pLogger);
2140	#endif
2141	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2142	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2143	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2144	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2145	#endif
2146	if (rc == VERR_TRPM_PANIC \|\| rc == VERR_TRPM_DONT_PANIC)
2147	VMMR3FatalDump(pVM, rc);
2148	if (rc != VINF_VMM_CALL_HOST)
2149	{
2150	Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2151	return rc;
2152	}
2153	rc = vmmR3ServiceCallHostRequest(pVM);
2154	if (VBOX_FAILURE(rc))
2155	return rc;
2156	}
2157	}
2158
2159
2160	/**
2161	* Service a call to the ring-3 host code.
2162	*
2163	* @returns VBox status code.
2164	* @param pVM VM handle.
2165	* @remark Careful with critsects.
2166	*/
2167	static int vmmR3ServiceCallHostRequest(PVM pVM)
2168	{
2169	switch (pVM->vmm.s.enmCallHostOperation)
2170	{
2171	/*
2172	* Acquire the PDM lock.
2173	*/
2174	case VMMCALLHOST_PDM_LOCK:
2175	{
2176	pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2177	break;
2178	}
2179
2180	/*
2181	* Flush a PDM queue.
2182	*/
2183	case VMMCALLHOST_PDM_QUEUE_FLUSH:
2184	{
2185	PDMR3QueueFlushWorker(pVM, NULL);
2186	pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2187	break;
2188	}
2189
2190	/*
2191	* Grow the PGM pool.
2192	*/
2193	case VMMCALLHOST_PGM_POOL_GROW:
2194	{
2195	pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2196	break;
2197	}
2198
2199	/*
2200	* Maps an page allocation chunk into ring-3 so ring-0 can use it.
2201	*/
2202	case VMMCALLHOST_PGM_MAP_CHUNK:
2203	{
2204	pVM->vmm.s.rcCallHost = PGMR3PhysChunkMap(pVM, pVM->vmm.s.u64CallHostArg);
2205	break;
2206	}
2207
2208	/*
2209	* Allocates more handy pages.
2210	*/
2211	case VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES:
2212	{
2213	pVM->vmm.s.rcCallHost = PGMR3PhysAllocateHandyPages(pVM);
2214	break;
2215	}
2216	#ifndef VBOX_WITH_NEW_PHYS_CODE
2217
2218	case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2219	{
2220	const RTGCPHYS GCPhys = pVM->vmm.s.u64CallHostArg;
2221	pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, &GCPhys);
2222	break;
2223	}
2224	#endif
2225
2226	/*
2227	* Acquire the PGM lock.
2228	*/
2229	case VMMCALLHOST_PGM_LOCK:
2230	{
2231	pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2232	break;
2233	}
2234
2235	/*
2236	* Flush REM handler notifications.
2237	*/
2238	case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2239	{
2240	REMR3ReplayHandlerNotifications(pVM);
2241	break;
2242	}
2243
2244	/*
2245	* This is a noop. We just take this route to avoid unnecessary
2246	* tests in the loops.
2247	*/
2248	case VMMCALLHOST_VMM_LOGGER_FLUSH:
2249	break;
2250
2251	/*
2252	* Set the VM error message.
2253	*/
2254	case VMMCALLHOST_VM_SET_ERROR:
2255	VMR3SetErrorWorker(pVM);
2256	break;
2257
2258	/*
2259	* Set the VM runtime error message.
2260	*/
2261	case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2262	VMR3SetRuntimeErrorWorker(pVM);
2263	break;
2264
2265	/*
2266	* Signal a ring 0 hypervisor assertion.
2267	* Cancel the longjmp operation that's in progress.
2268	*/
2269	case VMMCALLHOST_VM_R0_HYPER_ASSERTION:
2270	pVM->vmm.s.CallHostR0JmpBuf.fInRing3Call = false;
2271	#ifdef RT_ARCH_X86
2272	pVM->vmm.s.CallHostR0JmpBuf.eip = 0;
2273	#else
2274	pVM->vmm.s.CallHostR0JmpBuf.rip = 0;
2275	#endif
2276	return VINF_EM_DBG_HYPER_ASSERTION;
2277
2278	default:
2279	AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2280	return VERR_INTERNAL_ERROR;
2281	}
2282
2283	pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2284	return VINF_SUCCESS;
2285	}
2286
2287
2288
2289	/**
2290	* Structure to pass to DBGFR3Info() and for doing all other
2291	* output during fatal dump.
2292	*/
2293	typedef struct VMMR3FATALDUMPINFOHLP
2294	{
2295	/** The helper core. */
2296	DBGFINFOHLP Core;
2297	/** The release logger instance. */
2298	PRTLOGGER pRelLogger;
2299	/** The saved release logger flags. */
2300	RTUINT fRelLoggerFlags;
2301	/** The logger instance. */
2302	PRTLOGGER pLogger;
2303	/** The saved logger flags. */
2304	RTUINT fLoggerFlags;
2305	/** The saved logger destination flags. */
2306	RTUINT fLoggerDestFlags;
2307	/** Whether to output to stderr or not. */
2308	bool fStdErr;
2309	} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2310	typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2311
2312
2313	/**
2314	* Print formatted string.
2315	*
2316	* @param pHlp Pointer to this structure.
2317	* @param pszFormat The format string.
2318	* @param ... Arguments.
2319	*/
2320	static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2321	{
2322	va_list args;
2323	va_start(args, pszFormat);
2324	pHlp->pfnPrintfV(pHlp, pszFormat, args);
2325	va_end(args);
2326	}
2327
2328
2329	/**
2330	* Print formatted string.
2331	*
2332	* @param pHlp Pointer to this structure.
2333	* @param pszFormat The format string.
2334	* @param args Argument list.
2335	*/
2336	static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2337	{
2338	PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2339
2340	if (pMyHlp->pRelLogger)
2341	{
2342	va_list args2;
2343	va_copy(args2, args);
2344	RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2345	va_end(args2);
2346	}
2347	if (pMyHlp->pLogger)
2348	{
2349	va_list args2;
2350	va_copy(args2, args);
2351	RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2352	va_end(args2);
2353	}
2354	if (pMyHlp->fStdErr)
2355	{
2356	va_list args2;
2357	va_copy(args2, args);
2358	RTStrmPrintfV(g_pStdErr, pszFormat, args);
2359	va_end(args2);
2360	}
2361	}
2362
2363
2364	/**
2365	* Initializes the fatal dump output helper.
2366	*
2367	* @param pHlp The structure to initialize.
2368	*/
2369	static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2370	{
2371	memset(pHlp, 0, sizeof(*pHlp));
2372
2373	pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2374	pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2375
2376	/*
2377	* The loggers.
2378	*/
2379	pHlp->pRelLogger = RTLogRelDefaultInstance();
2380	#ifndef LOG_ENABLED
2381	if (!pHlp->pRelLogger)
2382	#endif
2383	pHlp->pLogger = RTLogDefaultInstance();
2384
2385	if (pHlp->pRelLogger)
2386	{
2387	pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2388	pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED \| RTLOGFLAGS_DISABLED);
2389	}
2390
2391	if (pHlp->pLogger)
2392	{
2393	pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2394	pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2395	pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED \| RTLOGFLAGS_DISABLED);
2396	#ifndef DEBUG_sandervl
2397	pHlp->pLogger->fDestFlags \|= RTLOGDEST_DEBUGGER;
2398	#endif
2399	}
2400
2401	/*
2402	* Check if we need write to stderr.
2403	*/
2404	pHlp->fStdErr = (!pHlp->pRelLogger \|\| !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT \| RTLOGDEST_STDERR)))
2405	&& (!pHlp->pLogger \|\| !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT \| RTLOGDEST_STDERR)));
2406	}
2407
2408
2409	/**
2410	* Deletes the fatal dump output helper.
2411	*
2412	* @param pHlp The structure to delete.
2413	*/
2414	static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2415	{
2416	if (pHlp->pRelLogger)
2417	{
2418	RTLogFlush(pHlp->pRelLogger);
2419	pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2420	}
2421
2422	if (pHlp->pLogger)
2423	{
2424	RTLogFlush(pHlp->pLogger);
2425	pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2426	pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2427	}
2428	}
2429
2430
2431	/**
2432	* Dumps the VM state on a fatal error.
2433	*
2434	* @param pVM VM Handle.
2435	* @param rcErr VBox status code.
2436	*/
2437	VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2438	{
2439	/*
2440	* Create our output helper and sync it with the log settings.
2441	* This helper will be used for all the output.
2442	*/
2443	VMMR3FATALDUMPINFOHLP Hlp;
2444	PCDBGFINFOHLP pHlp = &Hlp.Core;
2445	vmmR3FatalDumpInfoHlpInit(&Hlp);
2446
2447	/*
2448	* Header.
2449	*/
2450	pHlp->pfnPrintf(pHlp,
2451	"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2452	"!!\n"
2453	"!! Guru Meditation %d (%Vrc)\n"
2454	"!!\n",
2455	rcErr, rcErr);
2456
2457	/*
2458	* Continue according to context.
2459	*/
2460	bool fDoneHyper = false;
2461	switch (rcErr)
2462	{
2463	/*
2464	* Hyper visor errors.
2465	*/
2466	case VINF_EM_DBG_HYPER_ASSERTION:
2467	pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2468	/* fall thru */
2469	case VERR_TRPM_DONT_PANIC:
2470	case VERR_TRPM_PANIC:
2471	case VINF_EM_RAW_STALE_SELECTOR:
2472	case VINF_EM_RAW_IRET_TRAP:
2473	case VINF_EM_DBG_HYPER_BREAKPOINT:
2474	case VINF_EM_DBG_HYPER_STEPPED:
2475	{
2476	/* Trap? */
2477	uint32_t uEIP = CPUMGetHyperEIP(pVM);
2478	TRPMEVENT enmType;
2479	uint8_t u8TrapNo = 0xce;
2480	RTGCUINT uErrorCode = 0xdeadface;
2481	RTGCUINTPTR uCR2 = 0xdeadface;
2482	int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
2483	if (VBOX_SUCCESS(rc2))
2484	pHlp->pfnPrintf(pHlp,
2485	"!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv Type=%d\n",
2486	u8TrapNo, uErrorCode, uCR2, uEIP, enmType);
2487	else
2488	pHlp->pfnPrintf(pHlp,
2489	"!! EIP=%VGv NOTRAP\n",
2490	uEIP);
2491
2492	/*
2493	* Try figure out where eip is.
2494	*/
2495	/** @todo make query call for core code or move this function to VMM. */
2496	/* core code? */
2497	//if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2498	// pHlp->pfnPrintf(pHlp,
2499	// "!! EIP is in CoreCode, offset %#x\n",
2500	// uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2501	//else
2502	{ /* ask PDM */
2503	/** @todo ask DBGFR3Sym later. */
2504	char szModName[64];
2505	RTGCPTR GCPtrMod;
2506	char szNearSym1[260];
2507	RTGCPTR GCPtrNearSym1;
2508	char szNearSym2[260];
2509	RTGCPTR GCPtrNearSym2;
2510	int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2511	&szModName[0], sizeof(szModName), &GCPtrMod,
2512	&szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2513	&szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2514	if (VBOX_SUCCESS(rc))
2515	{
2516	pHlp->pfnPrintf(pHlp,
2517	"!! EIP in %s (%p) at rva %x near symbols:\n"
2518	"!! %VGv rva %VGv off %08x %s\n"
2519	"!! %VGv rva %VGv off -%08x %s\n",
2520	szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2521	GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2522	GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2523	}
2524	else
2525	pHlp->pfnPrintf(pHlp,
2526	"!! EIP is not in any code known to VMM!\n");
2527	}
2528
2529	/* Disassemble the instruction. */
2530	char szInstr[256];
2531	rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2532	if (VBOX_SUCCESS(rc2))
2533	pHlp->pfnPrintf(pHlp,
2534	"!! %s\n", szInstr);
2535
2536	/* Dump the hypervisor cpu state. */
2537	pHlp->pfnPrintf(pHlp,
2538	"!!\n"
2539	"!!\n"
2540	"!!\n");
2541	rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2542	fDoneHyper = true;
2543
2544	/* Callstack. */
2545	DBGFSTACKFRAME Frame = {0};
2546	rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2547	if (VBOX_SUCCESS(rc2))
2548	{
2549	pHlp->pfnPrintf(pHlp,
2550	"!!\n"
2551	"!! Call Stack:\n"
2552	"!!\n"
2553	"EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2554	do
2555	{
2556	pHlp->pfnPrintf(pHlp,
2557	"%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2558	(uint32_t)Frame.AddrFrame.off,
2559	(uint32_t)Frame.AddrReturnFrame.off,
2560	(uint32_t)Frame.AddrReturnPC.Sel,
2561	(uint32_t)Frame.AddrReturnPC.off,
2562	Frame.Args.au32[0],
2563	Frame.Args.au32[1],
2564	Frame.Args.au32[2],
2565	Frame.Args.au32[3]);
2566	pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2567	if (Frame.pSymPC)
2568	{
2569	RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2570	if (offDisp > 0)
2571	pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2572	else if (offDisp < 0)
2573	pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2574	else
2575	pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2576	}
2577	if (Frame.pLinePC)
2578	pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2579	pHlp->pfnPrintf(pHlp, "\n");
2580
2581	/* next */
2582	rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2583	} while (VBOX_SUCCESS(rc2));
2584	DBGFR3StackWalkEnd(pVM, &Frame);
2585	}
2586
2587	/* raw stack */
2588	pHlp->pfnPrintf(pHlp,
2589	"!!\n"
2590	"!! Raw stack (mind the direction).\n"
2591	"!!\n"
2592	"%.*Vhxd\n",
2593	VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2594	break;
2595	}
2596
2597	default:
2598	{
2599	break;
2600	}
2601
2602	} /* switch (rcErr) */
2603
2604
2605	/*
2606	* Generic info dumper loop.
2607	*/
2608	static struct
2609	{
2610	const char *pszInfo;
2611	const char *pszArgs;
2612	} const aInfo[] =
2613	{
2614	{ "mappings", NULL },
2615	{ "hma", NULL },
2616	{ "cpumguest", "verbose" },
2617	{ "cpumhyper", "verbose" },
2618	{ "cpumhost", "verbose" },
2619	{ "mode", "all" },
2620	{ "cpuid", "verbose" },
2621	{ "gdt", NULL },
2622	{ "ldt", NULL },
2623	//{ "tss", NULL },
2624	{ "ioport", NULL },
2625	{ "mmio", NULL },
2626	{ "phys", NULL },
2627	//{ "pgmpd", NULL }, - doesn't always work at init time...
2628	{ "timers", NULL },
2629	{ "activetimers", NULL },
2630	{ "handlers", "phys virt hyper stats" },
2631	{ "cfgm", NULL },
2632	};
2633	for (unsigned i = 0; i < ELEMENTS(aInfo); i++)
2634	{
2635	if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2636	continue;
2637	pHlp->pfnPrintf(pHlp,
2638	"!!\n"
2639	"!! {%s, %s}\n"
2640	"!!\n",
2641	aInfo[i].pszInfo, aInfo[i].pszArgs);
2642	DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2643	}
2644
2645	/* done */
2646	pHlp->pfnPrintf(pHlp,
2647	"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2648
2649
2650	/*
2651	* Delete the output instance (flushing and restoring of flags).
2652	*/
2653	vmmR3FatalDumpInfoHlpDelete(&Hlp);
2654	}
2655
2656
2657
2658	/**
2659	* Displays the Force action Flags.
2660	*
2661	* @param pVM The VM handle.
2662	* @param pHlp The output helpers.
2663	* @param pszArgs The additional arguments (ignored).
2664	*/
2665	static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2666	{
2667	const uint32_t fForcedActions = pVM->fForcedActions;
2668
2669	pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2670
2671	/* show the flag mnemonics */
2672	int c = 0;
2673	uint32_t f = fForcedActions;
2674	#define PRINT_FLAG(flag) do { \
2675	if (f & (flag)) \
2676	{ \
2677	static const char *s_psz = #flag; \
2678	if (!(c % 6)) \
2679	pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2680	else \
2681	pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2682	c++; \
2683	f &= ~(flag); \
2684	} \
2685	} while (0)
2686	PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2687	PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2688	PRINT_FLAG(VM_FF_TIMER);
2689	PRINT_FLAG(VM_FF_PDM_QUEUES);
2690	PRINT_FLAG(VM_FF_PDM_DMA);
2691	PRINT_FLAG(VM_FF_PDM_CRITSECT);
2692	PRINT_FLAG(VM_FF_DBGF);
2693	PRINT_FLAG(VM_FF_REQUEST);
2694	PRINT_FLAG(VM_FF_TERMINATE);
2695	PRINT_FLAG(VM_FF_RESET);
2696	PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2697	PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2698	PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2699	PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2700	PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2701	PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2702	PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2703	PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2704	PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2705	PRINT_FLAG(VM_FF_TO_R3);
2706	PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2707	if (f)
2708	pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2709	else
2710	pHlp->pfnPrintf(pHlp, "\n");
2711	#undef PRINT_FLAG
2712
2713	/* the groups */
2714	c = 0;
2715	#define PRINT_GROUP(grp) do { \
2716	if (fForcedActions & (grp)) \
2717	{ \
2718	static const char *s_psz = #grp; \
2719	if (!(c % 5)) \
2720	pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2721	else \
2722	pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2723	c++; \
2724	} \
2725	} while (0)
2726	PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2727	PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2728	PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2729	PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2730	PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2731	PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2732	PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2733	PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2734	PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2735	if (c)
2736	pHlp->pfnPrintf(pHlp, "\n");
2737	#undef PRINT_GROUP
2738	}
2739

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source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 9026

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