VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 1122

Last change on this file since 1122 was 1027, checked in by vboxsync, 18 years ago

Initial GIP change. Missing detection of SMP systems with TSC drift.
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1/* $Id: VMM.cpp 1027 2007-02-22 20:29:35Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22#if 0 //defined(__AMD64__) && !defined(__WIN__)
23# define NO_SUPCALLR0VMM
24#endif
25
26/** @page pg_vmm VMM - The Virtual Machine Monitor
27 *
28 * !Revise this! It's already incorrect!
29 *
30 * The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
31 * manages the alternate reality; controlling the virtualization, managing
32 * resources, tracking CPU state, it's resources and so on...
33 *
34 * We will split the VMM into smaller entities:
35 *
36 * - Virtual Machine Core Monitor (VMCM), which purpose it is to
37 * provide ring and world switching, that including routing
38 * interrupts to the host OS and traps to the appropriate trap
39 * handlers. It will implement an external interface for
40 * managing trap handlers.
41 *
42 * - CPU Monitor (CM), tracking the state of the CPU (in the alternate
43 * reality) and implementing external interfaces to read and change
44 * the state.
45 *
46 * - Memory Monitor (MM), which purpose it is to virtualize physical
47 * pages, segment descriptor tables, interrupt descriptor tables, task
48 * segments, and keep track of all memory providing external interfaces
49 * to access content and map pages. (Internally splitt into smaller entities!)
50 *
51 * - IO Monitor (IOM), which virtualizes in and out I/O operations. It
52 * interacts with the MM to implement memory mapped I/O. External
53 * interfaces for adding and removing I/O ranges are implemented.
54 *
55 * - External Interrupt Monitor (EIM), which purpose it is to manage
56 * interrupts generated by virtual devices. This monitor provides
57 * an interfaces for raising interrupts which is accessible at any
58 * time and from all thread.
59 * <p>
60 * A subentity of the EIM is the vitual Programmable Interrupt
61 * Controller Device (VPICD), and perhaps a virtual I/O Advanced
62 * Programmable Interrupt Controller Device (VAPICD).
63 *
64 * - Direct Memory Access Monitor (DMAM), which purpose it is to support
65 * virtual device using the DMA controller. Interfaces must be as the
66 * EIM interfaces independent and threadable.
67 * <p>
68 * A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
69 *
70 *
71 * Entities working on a higher level:
72 *
73 * - Device Manager (DM), which is a support facility for virtualized
74 * hardware. This provides generic facilities for efficient device
75 * virtualization. It will manage device attaching and detaching
76 * conversing with EIM and IOM.
77 *
78 * - Debugger Facility (DBGF) provides the basic features for
79 * debugging the alternate reality execution.
80 *
81 *
82 *
83 * @section pg_vmm_s_use_cases Use Cases
84 *
85 * @subsection pg_vmm_s_use_case_boot Bootstrap
86 *
87 * - Basic Init:
88 * - Init SUPDRV.
89 *
90 * - Init Virtual Machine Instance:
91 * - Load settings.
92 * - Check resource requirements (memory, com, stuff).
93 *
94 * - Init Host Ring 3 part:
95 * - Init Core code.
96 * - Load Pluggable Components.
97 * - Init Pluggable Components.
98 *
99 * - Init Host Ring 0 part:
100 * - Load Core (core = core components like VMM, RMI, CA, and so on) code.
101 * - Init Core code.
102 * - Load Pluggable Component code.
103 * - Init Pluggable Component code.
104 *
105 * - Allocate first chunk of memory and pin it down. This block of memory
106 * will fit the following pieces:
107 * - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
108 * (This is available from everywhere (at different addresses though)).
109 * - VMM Guest Context code.
110 * - Pluggable devices Guest Context code.
111 * - Page tables (directory and everything) for the VMM Guest
112 *
113 * - Setup Guest (Ring 0) part:
114 * - Setup initial page tables (i.e. directory all the stuff).
115 * - Load Core Guest Context code.
116 * - Load Pluggable Devices Guest Context code.
117 *
118 *
119 */
120
121
122/*******************************************************************************
123* Header Files *
124*******************************************************************************/
125#define LOG_GROUP LOG_GROUP_VMM
126#include <VBox/vmm.h>
127#include <VBox/vmapi.h>
128#include <VBox/pgm.h>
129#include <VBox/cfgm.h>
130#include <VBox/pdm.h>
131#include <VBox/cpum.h>
132#include <VBox/mm.h>
133#include <VBox/iom.h>
134#include <VBox/trpm.h>
135#include <VBox/selm.h>
136#include <VBox/em.h>
137#include <VBox/sup.h>
138#include <VBox/dbgf.h>
139#include <VBox/csam.h>
140#include <VBox/patm.h>
141#include <VBox/rem.h>
142#include <VBox/ssm.h>
143#include <VBox/tm.h>
144#include "VMMInternal.h"
145#include "VMMSwitcher/VMMSwitcher.h"
146#include <VBox/vm.h>
147#include <VBox/err.h>
148#include <VBox/param.h>
149#include <VBox/version.h>
150#include <VBox/x86.h>
151#include <iprt/assert.h>
152#include <iprt/alloc.h>
153#include <iprt/asm.h>
154#include <iprt/time.h>
155#include <iprt/stream.h>
156#include <iprt/string.h>
157#include <iprt/stdarg.h>
158#include <iprt/ctype.h>
159
160
161
162/** The saved state version. */
163#define VMM_SAVED_STATE_VERSION 3
164
165
166/*******************************************************************************
167* Internal Functions *
168*******************************************************************************/
169static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
170static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
171static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
172static int vmmR3ServiceCallHostRequest(PVM pVM);
173
174
175/*******************************************************************************
176* Global Variables *
177*******************************************************************************/
178/** Array of switcher defininitions.
179 * The type and index shall match!
180 */
181static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
182{
183 NULL, /* invalid entry */
184#ifndef __AMD64__
185 &vmmR3Switcher32BitTo32Bit_Def,
186 &vmmR3Switcher32BitToPAE_Def,
187 NULL, //&vmmR3Switcher32BitToAMD64_Def,
188 &vmmR3SwitcherPAETo32Bit_Def,
189 &vmmR3SwitcherPAEToPAE_Def,
190 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
191 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
192 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
193#else
194 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
195 NULL, //&vmmR3Switcher32BitToPAE_Def,
196 NULL, //&vmmR3Switcher32BitToAMD64_Def,
197 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
198 NULL, //&vmmR3SwitcherPAEToPAE_Def,
199 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
200 &vmmR3SwitcherAMD64ToPAE_Def,
201 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
202#endif
203};
204
205
206
207/**
208 * Initiates the core code.
209 *
210 * This is core per VM code which might need fixups and/or for ease of use
211 * are put on linear contiguous backing.
212 *
213 * @returns VBox status code.
214 * @param pVM Pointer to VM structure.
215 */
216static int vmmR3InitCoreCode(PVM pVM)
217{
218 /*
219 * Calc the size.
220 */
221 unsigned cbCoreCode = 0;
222 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
223 {
224 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
225 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
226 if (pSwitcher)
227 {
228 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
229 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
230 }
231 }
232
233 /*
234 * Allocate continguous pages for switchers and deal with
235 * conflicts in the intermediate mapping of the code.
236 */
237 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
238 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
239 int rc = VERR_NO_MEMORY;
240 if (pVM->vmm.s.pvHCCoreCodeR3)
241 {
242 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
243 if (rc == VERR_PGM_MAPPINGS_FIX_CONFLICT)
244 {
245 /* try more allocations. */
246 struct
247 {
248 RTR0PTR pvR0;
249 void *pvR3;
250 RTHCPHYS HCPhys;
251 } aBadTries[16];
252 unsigned i = 0;
253 do
254 {
255 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
256 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
257 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
258 i++;
259 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
260 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
261 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
262 if (!pVM->vmm.s.pvHCCoreCodeR3)
263 break;
264 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
265 } while ( rc == VERR_PGM_MAPPINGS_FIX_CONFLICT
266 && i < ELEMENTS(aBadTries) - 1);
267
268 /* cleanup */
269 if (VBOX_FAILURE(rc))
270 {
271 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
272 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
273 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
274 i++;
275 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
276 }
277 while (i-- > 0)
278 {
279 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
280 i, aBadTries[i].pvR3, aBadTries[i].pvR0, aBadTries[i].HCPhys));
281 SUPContFree(aBadTries[i].pvR3);
282 }
283 }
284 }
285 if (VBOX_SUCCESS(rc))
286 {
287 /*
288 * copy the code.
289 */
290 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
291 {
292 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
293 if (pSwitcher)
294 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
295 pSwitcher->pvCode, pSwitcher->cbCode);
296 }
297
298 /*
299 * Map the code into the GC address space.
300 */
301 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &pVM->vmm.s.pvGCCoreCode);
302 if (VBOX_SUCCESS(rc))
303 {
304 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
305 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VGv Phys=%VHp cb=%#x\n",
306 pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
307
308 /*
309 * Finally, PGM probably have selected a switcher already but we need
310 * to do get the addresses so we'll reselect it.
311 * This may legally fail so, we're ignoring the rc.
312 */
313 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
314 return rc;
315 }
316
317 /* shit */
318 AssertMsgFailed(("PGMR3Map(,%VGv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
319 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3);
320 }
321 else
322 VMSetError(pVM, rc, RT_SRC_POS,
323 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code."),
324 cbCoreCode);
325
326 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
327 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
328 pVM->vmm.s.pvGCCoreCode = 0;
329 return rc;
330}
331
332
333/**
334 * Initializes the VMM.
335 *
336 * @returns VBox status code.
337 * @param pVM The VM to operate on.
338 */
339VMMR3DECL(int) VMMR3Init(PVM pVM)
340{
341 LogFlow(("VMMR3Init\n"));
342
343 /*
344 * Assert alignment, sizes and order.
345 */
346 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
347 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
348 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
349 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
350
351 /*
352 * Init basic VM VMM members.
353 */
354 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
355 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
356 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
357 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
358 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
359 else
360 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
361
362 /* GC switchers are enabled by default. Turned off by HWACCM. */
363 pVM->vmm.s.fSwitcherDisabled = false;
364
365 /*
366 * Register the saved state data unit.
367 */
368 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
369 NULL, vmmR3Save, NULL,
370 NULL, vmmR3Load, NULL);
371 if (VBOX_FAILURE(rc))
372 return rc;
373
374#ifdef VBOX_WITHOUT_IDT_PATCHING
375 /*
376 * Register the Ring-0 VM handle with the session for fast ioctl calls.
377 */
378 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
379 if (VBOX_FAILURE(rc))
380 return rc;
381#endif
382
383 /*
384 * Init core code.
385 */
386 rc = vmmR3InitCoreCode(pVM);
387 if (VBOX_SUCCESS(rc))
388 {
389 /*
390 * Allocate & init VMM GC stack.
391 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
392 * (The page protection is modifed during R3 init completion.)
393 */
394#ifdef VBOX_STRICT_VMM_STACK
395 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
396#else
397 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
398#endif
399 if (VBOX_SUCCESS(rc))
400 {
401 /* Set HC and GC stack pointers to top of stack. */
402 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
403 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
404 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
405 AssertRelease(pVM->vmm.s.pbGCStack);
406
407 /* Set hypervisor eip. */
408 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
409
410 /*
411 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
412 */
413#ifdef LOG_ENABLED
414 PRTLOGGER pLogger = RTLogDefaultInstance();
415 if (pLogger)
416 {
417 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pLogger->cGroups]);
418 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
419 if (VBOX_SUCCESS(rc))
420 {
421 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
422
423/*
424 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
425 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
426 *
427 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
428 * to not stub all the log functions.
429 */
430# ifdef DEBUG_sandervl
431 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
432 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
433 if (VBOX_SUCCESS(rc))
434 {
435 pVM->vmm.s.pR0Logger->pVM = pVM;
436 //pVM->vmm.s.pR0Logger->fCreated = false;
437 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
438 }
439# endif
440 }
441 }
442#endif /* LOG_ENABLED */
443
444#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
445 /*
446 * Allocate GC Release Logger instances (finalized in the relocator).
447 */
448 if (VBOX_SUCCESS(rc))
449 {
450 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
451 if (pRelLogger)
452 {
453 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pRelLogger->cGroups]);
454 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
455 if (VBOX_SUCCESS(rc))
456 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
457 }
458 }
459#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
460
461#ifdef VBOX_WITH_NMI
462 /*
463 * Allocate mapping for the host APIC.
464 */
465 if (VBOX_SUCCESS(rc))
466 {
467 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
468 AssertRC(rc);
469 }
470#endif
471 if (VBOX_SUCCESS(rc))
472 {
473 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
474 if (VBOX_SUCCESS(rc))
475 {
476 /*
477 * Statistics.
478 */
479 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
480 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
481 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
482 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
483 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
484 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
485 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
486 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
487 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
488 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
489 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
490 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
491 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
492 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
493 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READWRITE returns.");
494 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
495 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
496 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
497 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
498 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
499 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
500 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
501 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
502 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
503 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
504 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
505 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
506 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
507 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
508 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
509 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
510 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
511 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
512 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
513 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
514 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
517 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
518 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
519 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
520 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
521 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
522 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
523 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
524 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
525 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
526 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
527 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
528 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
529
530 return VINF_SUCCESS;
531 }
532 AssertRC(rc);
533 }
534 }
535 /** @todo: Need failure cleanup. */
536
537 //more todo in here?
538 //if (VBOX_SUCCESS(rc))
539 //{
540 //}
541 //int rc2 = vmmR3TermCoreCode(pVM);
542 //AssertRC(rc2));
543 }
544
545 return rc;
546}
547
548
549/**
550 * Ring-3 init finalizing.
551 *
552 * @returns VBox status code.
553 * @param pVM The VM handle.
554 */
555VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
556{
557#ifdef VBOX_STRICT_VMM_STACK
558 /*
559 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
560 */
561 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
562 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
563 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
564
565 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
566 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
567 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
568#endif
569
570 /*
571 * Set page attributes to r/w for stack pages.
572 */
573 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
574 AssertRC(rc);
575 if (VBOX_SUCCESS(rc))
576 {
577 /*
578 * Create the EMT yield timer.
579 */
580 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
581 if (VBOX_SUCCESS(rc))
582 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
583 }
584#ifdef VBOX_WITH_NMI
585 /*
586 * Map the host APIC into GC - This may be host os specific!
587 */
588 if (VBOX_SUCCESS(rc))
589 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
590 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
591#endif
592 return rc;
593}
594
595
596/**
597 * Initializes the R0 VMM.
598 *
599 * @returns VBox status code.
600 * @param pVM The VM to operate on.
601 */
602VMMR3DECL(int) VMMR3InitR0(PVM pVM)
603{
604 int rc;
605
606 /*
607 * Initialize the ring-0 logger if we haven't done so yet.
608 */
609 if ( pVM->vmm.s.pR0Logger
610 && !pVM->vmm.s.pR0Logger->fCreated)
611 {
612 rc = VMMR3UpdateLoggers(pVM);
613 if (VBOX_FAILURE(rc))
614 return rc;
615 }
616
617 /*
618 * Call Ring-0 entry with init code.
619 */
620 for (;;)
621 {
622#ifdef NO_SUPCALLR0VMM
623 //rc = VERR_GENERAL_FAILURE;
624 rc = VINF_SUCCESS;
625#else
626 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, (void *)VBOX_VERSION);
627#endif
628 if ( pVM->vmm.s.pR0Logger
629 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
630 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
631 if (rc != VINF_VMM_CALL_HOST)
632 break;
633 rc = vmmR3ServiceCallHostRequest(pVM);
634 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
635 break;
636 break; // remove this when we do setjmp for all ring-0 stuff.
637 }
638
639 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
640 {
641 LogRel(("R0 init failed, rc=%Vra\n", rc));
642 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
643 rc = VERR_INTERNAL_ERROR;
644 }
645 return rc;
646}
647
648
649/**
650 * Initializes the GC VMM.
651 *
652 * @returns VBox status code.
653 * @param pVM The VM to operate on.
654 */
655VMMR3DECL(int) VMMR3InitGC(PVM pVM)
656{
657 /* In VMX mode, there's no need to init GC. */
658 if (pVM->vmm.s.fSwitcherDisabled)
659 return VINF_SUCCESS;
660
661 /*
662 * Call VMMGCInit():
663 * -# resolve the address.
664 * -# setup stackframe and EIP to use the trampoline.
665 * -# do a generic hypervisor call.
666 */
667 RTGCPTR GCPtrEP;
668 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
669 if (VBOX_SUCCESS(rc))
670 {
671 CPUMHyperSetCtxCore(pVM, NULL);
672 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
673 CPUMPushHyper(pVM, VBOX_VERSION); /* Param 2: Version argument. */
674 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
675 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
676 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* trampoline param: stacksize. */
677 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
678 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
679
680 for (;;)
681 {
682#ifdef NO_SUPCALLR0VMM
683 //rc = VERR_GENERAL_FAILURE;
684 rc = VINF_SUCCESS;
685#else
686 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
687#endif
688#ifdef LOG_ENABLED
689 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
690 if ( pLogger
691 && pLogger->offScratch > 0)
692 RTLogFlushGC(NULL, pLogger);
693#endif
694#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
695 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
696 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
697 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
698#endif
699 if (rc != VINF_VMM_CALL_HOST)
700 break;
701 rc = vmmR3ServiceCallHostRequest(pVM);
702 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
703 break;
704 }
705
706 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
707 {
708 VMMR3FatalDump(pVM, rc);
709 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
710 rc = VERR_INTERNAL_ERROR;
711 }
712 AssertRC(rc);
713 }
714 return rc;
715}
716
717
718/**
719 * Terminate the VMM bits.
720 *
721 * @returns VINF_SUCCESS.
722 * @param pVM The VM handle.
723 */
724VMMR3DECL(int) VMMR3Term(PVM pVM)
725{
726 /** @todo must call ring-0 so the logger thread instance can be properly removed. */
727
728#ifdef VBOX_STRICT_VMM_STACK
729 /*
730 * Make the two stack guard pages present again.
731 */
732 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
733 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
734#endif
735 return VINF_SUCCESS;
736}
737
738
739/**
740 * Applies relocations to data and code managed by this
741 * component. This function will be called at init and
742 * whenever the VMM need to relocate it self inside the GC.
743 *
744 * The VMM will need to apply relocations to the core code.
745 *
746 * @param pVM The VM handle.
747 * @param offDelta The relocation delta.
748 */
749VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
750{
751 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
752
753 /*
754 * Recalc the GC address.
755 */
756 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
757
758 /*
759 * The stack.
760 */
761 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
762 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
763 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
764
765 /*
766 * All the switchers.
767 */
768 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
769 {
770 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
771 if (pSwitcher && pSwitcher->pfnRelocate)
772 {
773 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
774 pSwitcher->pfnRelocate(pVM,
775 pSwitcher,
776 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
777 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
778 pVM->vmm.s.pvGCCoreCode + off,
779 pVM->vmm.s.HCPhysCoreCode + off);
780 }
781 }
782
783 /*
784 * Recalc the GC address for the current switcher.
785 */
786 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
787 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
788 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
789 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
790 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
791 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
792 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
793
794 /*
795 * Get other GC entry points.
796 */
797 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
798 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
799
800 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
801 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
802
803 /*
804 * Update the logger.
805 */
806 VMMR3UpdateLoggers(pVM);
807}
808
809
810/**
811 * Updates the settings for the GC and R0 loggers.
812 *
813 * @returns VBox status code.
814 * @param pVM The VM handle.
815 */
816VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
817{
818 /*
819 * Simply clone the logger instance (for GC).
820 */
821 int rc = VINF_SUCCESS;
822 RTGCPTR GCPtrLoggerFlush = 0;
823
824 if (pVM->vmm.s.pLoggerHC
825#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
826 || pVM->vmm.s.pRelLoggerHC
827#endif
828 )
829 {
830 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
831 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
832 }
833
834 if (pVM->vmm.s.pLoggerHC)
835 {
836 RTGCPTR GCPtrLoggerWrapper = 0;
837 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
838 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
839 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
840 rc = RTLogCloneGC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
841 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
842 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
843 }
844
845#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
846 if (pVM->vmm.s.pRelLoggerHC)
847 {
848 RTGCPTR GCPtrLoggerWrapper = 0;
849 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
850 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
851 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
852 rc = RTLogCloneGC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
853 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
854 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
855 }
856#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
857
858 /*
859 * For the ring-0 EMT logger, we use a per-thread logger
860 * instance in ring-0. Only initialize it once.
861 */
862 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
863 if (pR0Logger)
864 {
865 if (!pR0Logger->fCreated)
866 {
867 RTHCPTR pfnLoggerWrapper = NULL;
868 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
869 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
870
871 RTHCPTR pfnLoggerFlush = NULL;
872 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
873 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
874
875 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
876 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
877 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
878 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
879 pR0Logger->fCreated = true;
880 }
881
882 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, RTLOGFLAGS_BUFFERED, 0);
883 AssertRC(rc);
884 }
885
886 return rc;
887}
888
889
890/**
891 * Generic switch code relocator.
892 *
893 * @param pVM The VM handle.
894 * @param pSwitcher The switcher definition.
895 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
896 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
897 * @param GCPtrCode The guest context address corresponding to pu8Code.
898 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
899 * @param SelCS The hypervisor CS selector.
900 * @param SelDS The hypervisor DS selector.
901 * @param SelTSS The hypervisor TSS selector.
902 * @param GCPtrGDT The GC address of the hypervisor GDT.
903 * @param SelCS64 The 64-bit mode hypervisor CS selector.
904 */
905static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
906 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
907{
908 union
909 {
910 const uint8_t *pu8;
911 const uint16_t *pu16;
912 const uint32_t *pu32;
913 const uint64_t *pu64;
914 const void *pv;
915 uintptr_t u;
916 } u;
917 u.pv = pSwitcher->pvFixups;
918
919 /*
920 * Process fixups.
921 */
922 uint8_t u8;
923 while ((u8 = *u.pu8++) != FIX_THE_END)
924 {
925 /*
926 * Get the source (where to write the fixup).
927 */
928 uint32_t offSrc = *u.pu32++;
929 Assert(offSrc < pSwitcher->cbCode);
930 union
931 {
932 uint8_t *pu8;
933 uint16_t *pu16;
934 uint32_t *pu32;
935 uint64_t *pu64;
936 uintptr_t u;
937 } uSrc;
938 uSrc.pu8 = pu8CodeR3 + offSrc;
939
940 /* The fixup target and method depends on the type. */
941 switch (u8)
942 {
943 /*
944 * 32-bit relative, source in HC and target in GC.
945 */
946 case FIX_HC_2_GC_NEAR_REL:
947 {
948 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
949 uint32_t offTrg = *u.pu32++;
950 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
951 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
952 break;
953 }
954
955 /*
956 * 32-bit relative, source in HC and target in ID.
957 */
958 case FIX_HC_2_ID_NEAR_REL:
959 {
960 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
961 uint32_t offTrg = *u.pu32++;
962 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
963 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (uSrc.u + 4));
964 break;
965 }
966
967 /*
968 * 32-bit relative, source in GC and target in HC.
969 */
970 case FIX_GC_2_HC_NEAR_REL:
971 {
972 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
973 uint32_t offTrg = *u.pu32++;
974 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
975 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
976 break;
977 }
978
979 /*
980 * 32-bit relative, source in GC and target in ID.
981 */
982 case FIX_GC_2_ID_NEAR_REL:
983 {
984 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
985 uint32_t offTrg = *u.pu32++;
986 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
987 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
988 break;
989 }
990
991 /*
992 * 32-bit relative, source in ID and target in HC.
993 */
994 case FIX_ID_2_HC_NEAR_REL:
995 {
996 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
997 uint32_t offTrg = *u.pu32++;
998 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
999 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1000 break;
1001 }
1002
1003 /*
1004 * 32-bit relative, source in ID and target in HC.
1005 */
1006 case FIX_ID_2_GC_NEAR_REL:
1007 {
1008 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1009 uint32_t offTrg = *u.pu32++;
1010 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1011 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1012 break;
1013 }
1014
1015 /*
1016 * 16:32 far jump, target in GC.
1017 */
1018 case FIX_GC_FAR32:
1019 {
1020 uint32_t offTrg = *u.pu32++;
1021 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1022 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1023 *uSrc.pu16++ = SelCS;
1024 break;
1025 }
1026
1027 /*
1028 * Make 32-bit GC pointer given CPUM offset.
1029 */
1030 case FIX_GC_CPUM_OFF:
1031 {
1032 uint32_t offCPUM = *u.pu32++;
1033 Assert(offCPUM < sizeof(pVM->cpum));
1034 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1035 break;
1036 }
1037
1038 /*
1039 * Make 32-bit GC pointer given VM offset.
1040 */
1041 case FIX_GC_VM_OFF:
1042 {
1043 uint32_t offVM = *u.pu32++;
1044 Assert(offVM < sizeof(VM));
1045 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1046 break;
1047 }
1048
1049 /*
1050 * Make 32-bit HC pointer given CPUM offset.
1051 */
1052 case FIX_HC_CPUM_OFF:
1053 {
1054 uint32_t offCPUM = *u.pu32++;
1055 Assert(offCPUM < sizeof(pVM->cpum));
1056 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1057 break;
1058 }
1059
1060 /*
1061 * Make 32-bit R0 pointer given VM offset.
1062 */
1063 case FIX_HC_VM_OFF:
1064 {
1065 uint32_t offVM = *u.pu32++;
1066 Assert(offVM < sizeof(VM));
1067 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1068 break;
1069 }
1070
1071 /*
1072 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1073 */
1074 case FIX_INTER_32BIT_CR3:
1075 {
1076
1077 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1078 break;
1079 }
1080
1081 /*
1082 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1083 */
1084 case FIX_INTER_PAE_CR3:
1085 {
1086
1087 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1088 break;
1089 }
1090
1091 /*
1092 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1093 */
1094 case FIX_INTER_AMD64_CR3:
1095 {
1096
1097 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1098 break;
1099 }
1100
1101 /*
1102 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1103 */
1104 case FIX_HYPER_32BIT_CR3:
1105 {
1106
1107 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1108 break;
1109 }
1110
1111 /*
1112 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1113 */
1114 case FIX_HYPER_PAE_CR3:
1115 {
1116
1117 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1118 break;
1119 }
1120
1121 /*
1122 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1123 */
1124 case FIX_HYPER_AMD64_CR3:
1125 {
1126
1127 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1128 break;
1129 }
1130
1131 /*
1132 * Store Hypervisor CS (16-bit).
1133 */
1134 case FIX_HYPER_CS:
1135 {
1136 *uSrc.pu16 = SelCS;
1137 break;
1138 }
1139
1140 /*
1141 * Store Hypervisor DS (16-bit).
1142 */
1143 case FIX_HYPER_DS:
1144 {
1145 *uSrc.pu16 = SelDS;
1146 break;
1147 }
1148
1149 /*
1150 * Store Hypervisor TSS (16-bit).
1151 */
1152 case FIX_HYPER_TSS:
1153 {
1154 *uSrc.pu16 = SelTSS;
1155 break;
1156 }
1157
1158 /*
1159 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1160 */
1161 case FIX_GC_TSS_GDTE_DW2:
1162 {
1163 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1164 *uSrc.pu32 = (uint32_t)GCPtr;
1165 break;
1166 }
1167
1168
1169 ///@todo case FIX_CR4_MASK:
1170 ///@todo case FIX_CR4_OSFSXR:
1171
1172 /*
1173 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1174 */
1175 case FIX_NO_FXSAVE_JMP:
1176 {
1177 uint32_t offTrg = *u.pu32++;
1178 Assert(offTrg < pSwitcher->cbCode);
1179 if (!CPUMSupportsFXSR(pVM))
1180 {
1181 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1182 *uSrc.pu32++ = offTrg - (offSrc + 5);
1183 }
1184 else
1185 {
1186 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1187 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1188 }
1189 break;
1190 }
1191
1192 /*
1193 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1194 */
1195 case FIX_NO_SYSENTER_JMP:
1196 {
1197 uint32_t offTrg = *u.pu32++;
1198 Assert(offTrg < pSwitcher->cbCode);
1199 if (!CPUMIsHostUsingSysEnter(pVM))
1200 {
1201 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1202 *uSrc.pu32++ = offTrg - (offSrc + 5);
1203 }
1204 else
1205 {
1206 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1207 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1208 }
1209 break;
1210 }
1211
1212 /*
1213 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1214 */
1215 case FIX_NO_SYSCALL_JMP:
1216 {
1217 uint32_t offTrg = *u.pu32++;
1218 Assert(offTrg < pSwitcher->cbCode);
1219 if (!CPUMIsHostUsingSysEnter(pVM))
1220 {
1221 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1222 *uSrc.pu32++ = offTrg - (offSrc + 5);
1223 }
1224 else
1225 {
1226 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1227 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1228 }
1229 break;
1230 }
1231
1232#ifdef __AMD64__
1233 /*
1234 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1235 */
1236 case FIX_HC_64BIT:
1237 {
1238 uint32_t offTrg = *u.pu32++;
1239 Assert(offSrc < pSwitcher->cbCode);
1240 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1241 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1242 break;
1243 }
1244
1245 /*
1246 * 64-bit HC pointer to the CPUM instance data (no argument).
1247 */
1248 case FIX_HC_64BIT_CPUM:
1249 {
1250 Assert(offSrc < pSwitcher->cbCode);
1251 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1252 break;
1253 }
1254#endif
1255
1256 /*
1257 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1258 */
1259 case FIX_ID_32BIT:
1260 {
1261 uint32_t offTrg = *u.pu32++;
1262 Assert(offSrc < pSwitcher->cbCode);
1263 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1264 *uSrc.pu32 = u32IDCode + offTrg;
1265 break;
1266 }
1267
1268 /*
1269 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1270 */
1271 case FIX_ID_64BIT:
1272 {
1273 uint32_t offTrg = *u.pu32++;
1274 Assert(offSrc < pSwitcher->cbCode);
1275 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1276 *uSrc.pu64 = u32IDCode + offTrg;
1277 break;
1278 }
1279
1280 /*
1281 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1282 */
1283 case FIX_ID_FAR32_TO_64BIT_MODE:
1284 {
1285 uint32_t offTrg = *u.pu32++;
1286 Assert(offSrc < pSwitcher->cbCode);
1287 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1288 *uSrc.pu32++ = u32IDCode + offTrg;
1289 *uSrc.pu16 = SelCS64;
1290 AssertRelease(SelCS64);
1291 break;
1292 }
1293
1294#ifdef VBOX_WITH_NMI
1295 /*
1296 * 32-bit address to the APIC base.
1297 */
1298 case FIX_GC_APIC_BASE_32BIT:
1299 {
1300 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1301 break;
1302 }
1303#endif
1304
1305 default:
1306 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1307 break;
1308 }
1309 }
1310
1311#ifdef LOG_ENABLED
1312 /*
1313 * If Log2 is enabled disassemble the switcher code.
1314 *
1315 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1316 */
1317 if (LogIs2Enabled())
1318 {
1319 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1320 " pu8CodeR0 = %p\n"
1321 " pu8CodeR3 = %p\n"
1322 " GCPtrCode = %VGv\n"
1323 " u32IDCode = %08x\n"
1324 " pVMGC = %VGv\n"
1325 " pCPUMGC = %VGv\n"
1326 " pVMHC = %p\n"
1327 " pCPUMHC = %p\n"
1328 " GCPtrGDT = %VGv\n"
1329 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1330 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1331 " SelCS = %04x\n"
1332 " SelDS = %04x\n"
1333 " SelCS64 = %04x\n"
1334 " SelTSS = %04x\n",
1335 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1336 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1337 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1338 GCPtrGDT,
1339 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1340 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1341 SelCS, SelDS, SelCS64, SelTSS);
1342
1343 uint32_t offCode = 0;
1344 while (offCode < pSwitcher->cbCode)
1345 {
1346 /*
1347 * Figure out where this is.
1348 */
1349 const char *pszDesc = NULL;
1350 RTUINTPTR uBase;
1351 uint32_t cbCode;
1352 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1353 {
1354 pszDesc = "HCCode0";
1355 uBase = (RTUINTPTR)pu8CodeR0;
1356 offCode = pSwitcher->offHCCode0;
1357 cbCode = pSwitcher->cbHCCode0;
1358 }
1359 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1360 {
1361 pszDesc = "HCCode1";
1362 uBase = (RTUINTPTR)pu8CodeR0;
1363 offCode = pSwitcher->offHCCode1;
1364 cbCode = pSwitcher->cbHCCode1;
1365 }
1366 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1367 {
1368 pszDesc = "GCCode";
1369 uBase = GCPtrCode;
1370 offCode = pSwitcher->offGCCode;
1371 cbCode = pSwitcher->cbGCCode;
1372 }
1373 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1374 {
1375 pszDesc = "IDCode0";
1376 uBase = u32IDCode;
1377 offCode = pSwitcher->offIDCode0;
1378 cbCode = pSwitcher->cbIDCode0;
1379 }
1380 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1381 {
1382 pszDesc = "IDCode1";
1383 uBase = u32IDCode;
1384 offCode = pSwitcher->offIDCode1;
1385 cbCode = pSwitcher->cbIDCode1;
1386 }
1387 else
1388 {
1389 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1390 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1391 offCode++;
1392 continue;
1393 }
1394
1395 /*
1396 * Disassemble it.
1397 */
1398 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1399 DISCPUSTATE Cpu = {0};
1400 Cpu.mode = CPUMODE_32BIT;
1401 while (cbCode > 0)
1402 {
1403 /* try label it */
1404 if (pSwitcher->offR0HostToGuest == offCode)
1405 RTLogPrintf(" *R0HostToGuest:\n");
1406 if (pSwitcher->offGCGuestToHost == offCode)
1407 RTLogPrintf(" *GCGuestToHost:\n");
1408 if (pSwitcher->offGCCallTrampoline == offCode)
1409 RTLogPrintf(" *GCCallTrampoline:\n");
1410 if (pSwitcher->offGCGuestToHostAsm == offCode)
1411 RTLogPrintf(" *GCGuestToHostAsm:\n");
1412 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1413 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1414 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1415 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1416
1417 /* disas */
1418 uint32_t cbInstr = 0;
1419 char szDisas[256];
1420 if (DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas))
1421 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1422 else
1423 {
1424 RTLogPrintf(" %04x: %02x '%c'\n",
1425 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1426 cbInstr = 1;
1427 }
1428 offCode += cbInstr;
1429 cbCode -= RT_MIN(cbInstr, cbCode);
1430 }
1431 }
1432 }
1433#endif
1434}
1435
1436
1437/**
1438 * Relocator for the 32-Bit to 32-Bit world switcher.
1439 */
1440DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1441{
1442 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1443 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1444}
1445
1446
1447/**
1448 * Relocator for the 32-Bit to PAE world switcher.
1449 */
1450DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1451{
1452 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1453 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1454}
1455
1456
1457/**
1458 * Relocator for the PAE to 32-Bit world switcher.
1459 */
1460DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1461{
1462 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1463 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1464}
1465
1466
1467/**
1468 * Relocator for the PAE to PAE world switcher.
1469 */
1470DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1471{
1472 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1473 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1474}
1475
1476
1477/**
1478 * Relocator for the AMD64 to PAE world switcher.
1479 */
1480DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1481{
1482 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1483 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1484}
1485
1486
1487/**
1488 * Gets the pointer to g_szRTAssertMsg1 in GC.
1489 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1490 * Returns NULL if not present.
1491 * @param pVM The VM handle.
1492 */
1493VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1494{
1495 RTGCPTR GCPtr;
1496 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1497 if (VBOX_SUCCESS(rc))
1498 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1499 return NULL;
1500}
1501
1502
1503/**
1504 * Gets the pointer to g_szRTAssertMsg2 in GC.
1505 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1506 * Returns NULL if not present.
1507 * @param pVM The VM handle.
1508 */
1509VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1510{
1511 RTGCPTR GCPtr;
1512 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1513 if (VBOX_SUCCESS(rc))
1514 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1515 return NULL;
1516}
1517
1518
1519/**
1520 * Execute state save operation.
1521 *
1522 * @returns VBox status code.
1523 * @param pVM VM Handle.
1524 * @param pSSM SSM operation handle.
1525 */
1526static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1527{
1528 LogFlow(("vmmR3Save:\n"));
1529
1530 /*
1531 * The hypervisor stack.
1532 */
1533 SSMR3PutGCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1534 RTGCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1535 Assert(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE);
1536 SSMR3PutGCPtr(pSSM, GCPtrESP);
1537 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1538 return SSMR3PutU32(pSSM, ~0); /* terminator */
1539}
1540
1541
1542/**
1543 * Execute state load operation.
1544 *
1545 * @returns VBox status code.
1546 * @param pVM VM Handle.
1547 * @param pSSM SSM operation handle.
1548 * @param u32Version Data layout version.
1549 */
1550static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1551{
1552 LogFlow(("vmmR3Load:\n"));
1553
1554 /*
1555 * Validate version.
1556 */
1557 if (u32Version != VMM_SAVED_STATE_VERSION)
1558 {
1559 Log(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1560 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1561 }
1562
1563 /*
1564 * Check that the stack is in the same place, or that it's fearly empty.
1565 */
1566 RTGCPTR GCPtrStackBottom;
1567 SSMR3GetGCPtr(pSSM, &GCPtrStackBottom);
1568 RTGCPTR GCPtrESP;
1569 int rc = SSMR3GetGCPtr(pSSM, &GCPtrESP);
1570 if (VBOX_FAILURE(rc))
1571 return rc;
1572 if ( GCPtrStackBottom == pVM->vmm.s.pbGCStackBottom
1573 || (GCPtrStackBottom - GCPtrESP < 32)) /** @todo This will break if we start preemting the hypervisor. */
1574 {
1575 /*
1576 * We *must* set the ESP because the CPUM load + PGM load relocations will render
1577 * the ESP in CPUM fatally invalid.
1578 */
1579 CPUMSetHyperESP(pVM, GCPtrESP);
1580
1581 /* restore the stack. */
1582 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1583
1584 /* terminator */
1585 uint32_t u32;
1586 rc = SSMR3GetU32(pSSM, &u32);
1587 if (VBOX_FAILURE(rc))
1588 return rc;
1589 if (u32 != ~0U)
1590 {
1591 AssertMsgFailed(("u32=%#x\n", u32));
1592 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1593 }
1594 return VINF_SUCCESS;
1595 }
1596
1597 LogRel(("The stack is not in the same place and it's not empty! GCPtrStackBottom=%VGv pbGCStackBottom=%VGv ESP=%VGv\n",
1598 GCPtrStackBottom, pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1599 AssertFailed();
1600 return VERR_SSM_LOAD_CONFIG_MISMATCH;
1601}
1602
1603
1604/**
1605 * Selects the switcher to be used for switching to GC.
1606 *
1607 * @returns VBox status code.
1608 * @param pVM VM handle.
1609 * @param enmSwitcher The new switcher.
1610 * @remark This function may be called before the VMM is initialized.
1611 */
1612VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1613{
1614 /*
1615 * Validate input.
1616 */
1617 if ( enmSwitcher < VMMSWITCHER_INVALID
1618 || enmSwitcher >= VMMSWITCHER_MAX)
1619 {
1620 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1621 return VERR_INVALID_PARAMETER;
1622 }
1623
1624 /*
1625 * Select the new switcher.
1626 */
1627 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1628 if (pSwitcher)
1629 {
1630 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1631 pVM->vmm.s.enmSwitcher = enmSwitcher;
1632
1633 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1634 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1635
1636 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1637 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1638 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1639 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1640 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1641 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1642 return VINF_SUCCESS;
1643 }
1644 return VERR_NOT_IMPLEMENTED;
1645}
1646
1647/**
1648 * Disable the switcher logic permanently.
1649 *
1650 * @returns VBox status code.
1651 * @param pVM VM handle.
1652 */
1653VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1654{
1655/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1656 * @code
1657 * mov eax, VERR_INTERNAL_ERROR
1658 * ret
1659 * @endcode
1660 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1661 */
1662 pVM->vmm.s.fSwitcherDisabled = true;
1663 return VINF_SUCCESS;
1664}
1665
1666
1667/**
1668 * Resolve a builtin GC symbol.
1669 * Called by PDM when loading or relocating GC modules.
1670 *
1671 * @returns VBox status
1672 * @param pVM VM Handle.
1673 * @param pszSymbol Symbol to resolv
1674 * @param pGCPtrValue Where to store the symbol value.
1675 * @remark This has to work before VMMR3Relocate() is called.
1676 */
1677VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1678{
1679 if (!strcmp(pszSymbol, "g_Logger"))
1680 {
1681 if (pVM->vmm.s.pLoggerHC)
1682 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1683 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1684 }
1685 else if (!strcmp(pszSymbol, "g_RelLogger"))
1686 {
1687#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1688 if (pVM->vmm.s.pRelLoggerHC)
1689 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1690 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1691#else
1692 *pGCPtrValue = NIL_RTGCPTR;
1693#endif
1694 }
1695 else
1696 return VERR_SYMBOL_NOT_FOUND;
1697 return VINF_SUCCESS;
1698}
1699
1700
1701/**
1702 * Suspends the the CPU yielder.
1703 *
1704 * @param pVM The VM handle.
1705 */
1706VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1707{
1708 if (!pVM->vmm.s.cYieldResumeMillies)
1709 {
1710 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1711 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1712 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1713 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1714 else
1715 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1716 TMTimerStop(pVM->vmm.s.pYieldTimer);
1717 }
1718}
1719
1720
1721/**
1722 * Stops the the CPU yielder.
1723 *
1724 * @param pVM The VM handle.
1725 */
1726VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1727{
1728 if (!pVM->vmm.s.cYieldResumeMillies)
1729 TMTimerStop(pVM->vmm.s.pYieldTimer);
1730 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1731}
1732
1733
1734/**
1735 * Resumes the CPU yielder when it has been a suspended or stopped.
1736 *
1737 * @param pVM The VM handle.
1738 */
1739VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1740{
1741 if (pVM->vmm.s.cYieldResumeMillies)
1742 {
1743 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1744 pVM->vmm.s.cYieldResumeMillies = 0;
1745 }
1746}
1747
1748
1749/**
1750 * Internal timer callback function.
1751 *
1752 * @param pVM The VM.
1753 * @param pTimer The timer handle.
1754 * @param pvUser User argument specified upon timer creation.
1755 */
1756static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1757{
1758#ifdef LOG_ENABLED
1759 uint64_t u64Elapsed = RTTimeNanoTS();
1760#endif
1761 RTThreadYield();
1762 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1763 Log(("vmmR3YieldEMT: %RI64 ns\n", RTTimeNanoTS() - u64Elapsed));
1764}
1765
1766
1767/**
1768 * Acquire global VM lock.
1769 *
1770 * @returns VBox status code
1771 * @param pVM The VM to operate on.
1772 */
1773VMMR3DECL(int) VMMR3Lock(PVM pVM)
1774{
1775 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1776}
1777
1778
1779/**
1780 * Release global VM lock.
1781 *
1782 * @returns VBox status code
1783 * @param pVM The VM to operate on.
1784 */
1785VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1786{
1787 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1788}
1789
1790
1791/**
1792 * Return global VM lock owner.
1793 *
1794 * @returns Thread id of owner.
1795 * @returns NIL_RTTHREAD if no owner.
1796 * @param pVM The VM to operate on.
1797 */
1798VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1799{
1800 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1801}
1802
1803
1804/**
1805 * Checks if the current thread is the owner of the global VM lock.
1806 *
1807 * @returns true if owner.
1808 * @returns false if not owner.
1809 * @param pVM The VM to operate on.
1810 */
1811VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1812{
1813 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1814}
1815
1816
1817/**
1818 * Executes guest code.
1819 *
1820 * @param pVM VM handle.
1821 */
1822VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1823{
1824 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1825
1826 /*
1827 * Set the EIP and ESP.
1828 */
1829 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1830 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1831 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1832 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1833
1834 /*
1835 * We hide log flushes (outer) and hypervisor interrupts (inner).
1836 */
1837 for (;;)
1838 {
1839 int rc;
1840 do
1841 {
1842#ifdef NO_SUPCALLR0VMM
1843 rc = VERR_GENERAL_FAILURE;
1844#else
1845 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
1846#endif
1847 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1848
1849 /*
1850 * Flush the logs.
1851 */
1852#ifdef LOG_ENABLED
1853 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1854 if ( pLogger
1855 && pLogger->offScratch > 0)
1856 RTLogFlushGC(NULL, pLogger);
1857#endif
1858#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1859 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1860 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1861 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1862#endif
1863 if (rc != VINF_VMM_CALL_HOST)
1864 {
1865 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1866 return rc;
1867 }
1868 rc = vmmR3ServiceCallHostRequest(pVM);
1869 if (VBOX_FAILURE(rc))
1870 return rc;
1871 /* Resume GC */
1872 }
1873}
1874
1875
1876/**
1877 * Executes guest code (Intel VMX and AMD SVM).
1878 *
1879 * @param pVM VM handle.
1880 */
1881VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1882{
1883 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1884
1885 for (;;)
1886 {
1887 int rc;
1888 do
1889 {
1890#ifdef NO_SUPCALLR0VMM
1891 rc = VERR_GENERAL_FAILURE;
1892#else
1893 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_RUN, NULL);
1894#endif
1895 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1896
1897#ifdef LOG_ENABLED
1898 /*
1899 * Flush the log
1900 */
1901 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
1902 if ( pR0Logger
1903 && pR0Logger->Logger.offScratch > 0)
1904 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
1905#endif /* !LOG_ENABLED */
1906 if (rc != VINF_VMM_CALL_HOST)
1907 {
1908 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1909 return rc;
1910 }
1911 rc = vmmR3ServiceCallHostRequest(pVM);
1912 if (VBOX_FAILURE(rc))
1913 return rc;
1914 /* Resume R0 */
1915 }
1916}
1917
1918/**
1919 * Calls GC a function.
1920 *
1921 * @param pVM The VM handle.
1922 * @param GCPtrEntry The GC function address.
1923 * @param cArgs The number of arguments in the ....
1924 * @param ... Arguments to the function.
1925 */
1926VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, ...)
1927{
1928 va_list args;
1929 va_start(args, cArgs);
1930 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
1931 va_end(args);
1932 return rc;
1933}
1934
1935
1936/**
1937 * Calls GC a function.
1938 *
1939 * @param pVM The VM handle.
1940 * @param GCPtrEntry The GC function address.
1941 * @param cArgs The number of arguments in the ....
1942 * @param args Arguments to the function.
1943 */
1944VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, va_list args)
1945{
1946 Log2(("VMMR3CallGCV: GCPtrEntry=%VGv cArgs=%d\n", GCPtrEntry, cArgs));
1947
1948 /*
1949 * Setup the call frame using the trampoline.
1950 */
1951 CPUMHyperSetCtxCore(pVM, NULL);
1952 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
1953 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR));
1954 PRTGCUINTPTR pFrame = (PRTGCUINTPTR)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
1955 int i = cArgs;
1956 while (i-- > 0)
1957 *pFrame++ = va_arg(args, RTGCUINTPTR);
1958
1959 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR)); /* stack frame size */
1960 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
1961 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
1962
1963 /*
1964 * We hide log flushes (outer) and hypervisor interrupts (inner).
1965 */
1966 for (;;)
1967 {
1968 int rc;
1969 do
1970 {
1971#ifdef NO_SUPCALLR0VMM
1972 rc = VERR_GENERAL_FAILURE;
1973#else
1974 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
1975#endif
1976 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1977
1978 /*
1979 * Flush the logs.
1980 */
1981#ifdef LOG_ENABLED
1982 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1983 if ( pLogger
1984 && pLogger->offScratch > 0)
1985 RTLogFlushGC(NULL, pLogger);
1986#endif
1987#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1988 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1989 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1990 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1991#endif
1992 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
1993 VMMR3FatalDump(pVM, rc);
1994 if (rc != VINF_VMM_CALL_HOST)
1995 {
1996 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1997 return rc;
1998 }
1999 rc = vmmR3ServiceCallHostRequest(pVM);
2000 if (VBOX_FAILURE(rc))
2001 return rc;
2002 }
2003}
2004
2005
2006/**
2007 * Resumes executing hypervisor code when interrupted
2008 * by a queue flush or a debug event.
2009 *
2010 * @returns VBox status code.
2011 * @param pVM VM handle.
2012 */
2013VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2014{
2015 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2016
2017 /*
2018 * We hide log flushes (outer) and hypervisor interrupts (inner).
2019 */
2020 for (;;)
2021 {
2022 int rc;
2023 do
2024 {
2025#ifdef NO_SUPCALLR0VMM
2026 rc = VERR_GENERAL_FAILURE;
2027#else
2028 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2029#endif
2030 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2031
2032 /*
2033 * Flush the loggers,
2034 */
2035#ifdef LOG_ENABLED
2036 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2037 if ( pLogger
2038 && pLogger->offScratch > 0)
2039 RTLogFlushGC(NULL, pLogger);
2040#endif
2041#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2042 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2043 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2044 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2045#endif
2046 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2047 VMMR3FatalDump(pVM, rc);
2048 if (rc != VINF_VMM_CALL_HOST)
2049 {
2050 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2051 return rc;
2052 }
2053 rc = vmmR3ServiceCallHostRequest(pVM);
2054 if (VBOX_FAILURE(rc))
2055 return rc;
2056 }
2057}
2058
2059
2060/**
2061 * Service a call to the ring-3 host code.
2062 *
2063 * @returns VBox status code.
2064 * @param pVM VM handle.
2065 * @remark Careful with critsects.
2066 */
2067static int vmmR3ServiceCallHostRequest(PVM pVM)
2068{
2069 switch (pVM->vmm.s.enmCallHostOperation)
2070 {
2071 /*
2072 * Acquire the PDM lock.
2073 */
2074 case VMMCALLHOST_PDM_LOCK:
2075 {
2076 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2077 break;
2078 }
2079
2080 /*
2081 * Flush a PDM queue.
2082 */
2083 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2084 {
2085 PDMR3QueueFlushWorker(pVM, NULL);
2086 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2087 break;
2088 }
2089
2090 /*
2091 * Grow the PGM pool.
2092 */
2093 case VMMCALLHOST_PGM_POOL_GROW:
2094 {
2095 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2096 break;
2097 }
2098
2099 /*
2100 * Acquire the PGM lock.
2101 */
2102 case VMMCALLHOST_PGM_LOCK:
2103 {
2104 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2105 break;
2106 }
2107
2108 /*
2109 * Flush REM handler notifications.
2110 */
2111 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2112 {
2113 REMR3ReplayHandlerNotifications(pVM);
2114 break;
2115 }
2116
2117 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2118 {
2119 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, pVM->vmm.s.u64CallHostArg);
2120 break;
2121 }
2122
2123 /*
2124 * This is a noop. We just take this route to avoid unnecessary
2125 * tests in the loops.
2126 */
2127 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2128 break;
2129
2130 /*
2131 * Set the VM error message.
2132 */
2133 case VMMCALLHOST_VM_SET_ERROR:
2134 VMR3SetErrorWorker(pVM);
2135 break;
2136
2137 /*
2138 * Set the VM runtime error message.
2139 */
2140 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2141 VMR3SetRuntimeErrorWorker(pVM);
2142 break;
2143
2144 default:
2145 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2146 return VERR_INTERNAL_ERROR;
2147 }
2148
2149 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2150 return VINF_SUCCESS;
2151}
2152
2153
2154
2155/**
2156 * Structure to pass to DBGFR3Info() and for doing all other
2157 * output during fatal dump.
2158 */
2159typedef struct VMMR3FATALDUMPINFOHLP
2160{
2161 /** The helper core. */
2162 DBGFINFOHLP Core;
2163 /** The release logger instance. */
2164 PRTLOGGER pRelLogger;
2165 /** The saved release logger flags. */
2166 RTUINT fRelLoggerFlags;
2167 /** The logger instance. */
2168 PRTLOGGER pLogger;
2169 /** The saved logger flags. */
2170 RTUINT fLoggerFlags;
2171 /** The saved logger destination flags. */
2172 RTUINT fLoggerDestFlags;
2173 /** Whether to output to stderr or not. */
2174 bool fStdErr;
2175} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2176typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2177
2178
2179/**
2180 * Print formatted string.
2181 *
2182 * @param pHlp Pointer to this structure.
2183 * @param pszFormat The format string.
2184 * @param ... Arguments.
2185 */
2186static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2187{
2188 va_list args;
2189 va_start(args, pszFormat);
2190 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2191 va_end(args);
2192}
2193
2194
2195/**
2196 * Print formatted string.
2197 *
2198 * @param pHlp Pointer to this structure.
2199 * @param pszFormat The format string.
2200 * @param args Argument list.
2201 */
2202static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2203{
2204 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2205
2206 if (pMyHlp->pRelLogger)
2207 {
2208 va_list args2;
2209 va_copy(args2, args);
2210 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2211 va_end(args2);
2212 }
2213 if (pMyHlp->pLogger)
2214 {
2215 va_list args2;
2216 va_copy(args2, args);
2217 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2218 va_end(args2);
2219 }
2220 if (pMyHlp->fStdErr)
2221 {
2222 va_list args2;
2223 va_copy(args2, args);
2224 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2225 va_end(args2);
2226 }
2227}
2228
2229
2230/**
2231 * Initializes the fatal dump output helper.
2232 *
2233 * @param pHlp The structure to initialize.
2234 */
2235static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2236{
2237 memset(pHlp, 0, sizeof(*pHlp));
2238
2239 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2240 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2241
2242 /*
2243 * The loggers.
2244 */
2245 pHlp->pRelLogger = RTLogRelDefaultInstance();
2246#ifndef LOG_ENABLED
2247 if (!pHlp->pRelLogger)
2248#endif
2249 pHlp->pLogger = RTLogDefaultInstance();
2250
2251 if (pHlp->pRelLogger)
2252 {
2253 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2254 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2255 }
2256
2257 if (pHlp->pLogger)
2258 {
2259 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2260 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2261 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2262 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2263 }
2264
2265 /*
2266 * Check if we need write to stderr.
2267 */
2268 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2269 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2270}
2271
2272
2273/**
2274 * Deletes the fatal dump output helper.
2275 *
2276 * @param pHlp The structure to delete.
2277 */
2278static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2279{
2280 if (pHlp->pRelLogger)
2281 {
2282 RTLogFlush(pHlp->pRelLogger);
2283 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2284 }
2285
2286 if (pHlp->pLogger)
2287 {
2288 RTLogFlush(pHlp->pLogger);
2289 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2290 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2291 }
2292}
2293
2294
2295/**
2296 * Dumps the VM state on a fatal error.
2297 *
2298 * @param pVM VM Handle.
2299 * @param rcErr VBox status code.
2300 */
2301VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2302{
2303 /*
2304 * Create our output helper and sync it with the log settings.
2305 * This helper will be used for all the output.
2306 */
2307 VMMR3FATALDUMPINFOHLP Hlp;
2308 PCDBGFINFOHLP pHlp = &Hlp.Core;
2309 vmmR3FatalDumpInfoHlpInit(&Hlp);
2310
2311 /*
2312 * Header.
2313 */
2314 pHlp->pfnPrintf(pHlp,
2315 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2316 "!!\n"
2317 "!! Guru Meditation %d (%Vrc)\n"
2318 "!!\n",
2319 rcErr, rcErr);
2320
2321 /*
2322 * Continue according to context.
2323 */
2324 bool fDoneHyper = false;
2325 switch (rcErr)
2326 {
2327 /*
2328 * Hyper visor errors.
2329 */
2330 case VINF_EM_DBG_HYPER_ASSERTION:
2331 pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2332 /* fall thru */
2333 case VERR_TRPM_DONT_PANIC:
2334 case VERR_TRPM_PANIC:
2335 case VINF_EM_RAW_STALE_SELECTOR:
2336 case VINF_EM_RAW_IRET_TRAP:
2337 case VINF_EM_DBG_HYPER_BREAKPOINT:
2338 case VINF_EM_DBG_HYPER_STEPPED:
2339 {
2340 /* Trap? */
2341 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2342 bool fSoftwareInterrupt = false;
2343 uint8_t u8TrapNo = 0xce;
2344 RTGCUINT uErrorCode = 0xdeadface;
2345 RTGCUINTPTR uCR2 = 0xdeadface;
2346 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
2347 if (VBOX_SUCCESS(rc2))
2348 pHlp->pfnPrintf(pHlp,
2349 "!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv fSoft=%d\n",
2350 u8TrapNo, uErrorCode, uCR2, uEIP, fSoftwareInterrupt);
2351 else
2352 pHlp->pfnPrintf(pHlp,
2353 "!! EIP=%VGv NOTRAP\n",
2354 uEIP);
2355
2356 /*
2357 * Try figure out where eip is.
2358 */
2359 /** @todo make query call for core code or move this function to VMM. */
2360 /* core code? */
2361 //if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2362 // pHlp->pfnPrintf(pHlp,
2363 // "!! EIP is in CoreCode, offset %#x\n",
2364 // uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2365 //else
2366 { /* ask PDM */
2367 /** @todo ask DBGFR3Sym later. */
2368 char szModName[64];
2369 RTGCPTR GCPtrMod;
2370 char szNearSym1[260];
2371 RTGCPTR GCPtrNearSym1;
2372 char szNearSym2[260];
2373 RTGCPTR GCPtrNearSym2;
2374 int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2375 &szModName[0], sizeof(szModName), &GCPtrMod,
2376 &szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2377 &szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2378 if (VBOX_SUCCESS(rc))
2379 {
2380 pHlp->pfnPrintf(pHlp,
2381 "!! EIP in %s (%p) at rva %x near symbols:\n"
2382 "!! %VGv rva %VGv off %08x %s\n"
2383 "!! %VGv rva %VGv off -%08x %s\n",
2384 szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2385 GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2386 GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2387 }
2388 else
2389 pHlp->pfnPrintf(pHlp,
2390 "!! EIP is not in any code known to VMM!\n");
2391 }
2392
2393 /* Disassemble the instruction. */
2394 char szInstr[256];
2395 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2396 if (VBOX_SUCCESS(rc2))
2397 pHlp->pfnPrintf(pHlp,
2398 "!! %s\n", szInstr);
2399
2400 /* Dump the hypervisor cpu state. */
2401 pHlp->pfnPrintf(pHlp,
2402 "!!\n"
2403 "!!\n"
2404 "!!\n");
2405 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2406 fDoneHyper = true;
2407
2408 /* Callstack. */
2409 DBGFSTACKFRAME Frame = {0};
2410 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2411 if (VBOX_SUCCESS(rc2))
2412 {
2413 pHlp->pfnPrintf(pHlp,
2414 "!!\n"
2415 "!! Call Stack:\n"
2416 "!!\n"
2417 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2418 do
2419 {
2420 pHlp->pfnPrintf(pHlp,
2421 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2422 (uint32_t)Frame.AddrFrame.off,
2423 (uint32_t)Frame.AddrReturnFrame.off,
2424 (uint32_t)Frame.AddrReturnPC.Sel,
2425 (uint32_t)Frame.AddrReturnPC.off,
2426 Frame.Args.au32[0],
2427 Frame.Args.au32[1],
2428 Frame.Args.au32[2],
2429 Frame.Args.au32[3]);
2430 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2431 if (Frame.pSymPC)
2432 {
2433 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2434 if (offDisp > 0)
2435 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2436 else if (offDisp < 0)
2437 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2438 else
2439 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2440 }
2441 if (Frame.pLinePC)
2442 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2443 pHlp->pfnPrintf(pHlp, "\n");
2444
2445 /* next */
2446 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2447 } while (VBOX_SUCCESS(rc2));
2448 DBGFR3StackWalkEnd(pVM, &Frame);
2449 }
2450
2451 /* raw stack */
2452 pHlp->pfnPrintf(pHlp,
2453 "!!\n"
2454 "!! Raw stack (mind the direction).\n"
2455 "!!\n"
2456 "%.*Vhxd\n",
2457 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2458 break;
2459 }
2460
2461 default:
2462 {
2463 break;
2464 }
2465
2466 } /* switch (rcErr) */
2467
2468
2469 /*
2470 * Dump useful state information.
2471 */
2472 /** @todo convert these dumpers to DBGFR3Info() handlers!!! */
2473 pHlp->pfnPrintf(pHlp,
2474 "!!\n"
2475 "!! PGM Access Handlers & Stuff:\n"
2476 "!!\n");
2477 PGMR3DumpMappings(pVM);
2478
2479
2480 /*
2481 * Generic info dumper loop.
2482 */
2483 static struct
2484 {
2485 const char *pszInfo;
2486 const char *pszArgs;
2487 } const aInfo[] =
2488 {
2489 { "hma", NULL },
2490 { "cpumguest", "verbose" },
2491 { "cpumhyper", "verbose" },
2492 { "cpumhost", "verbose" },
2493 { "mode", "all" },
2494 { "cpuid", "verbose" },
2495 { "gdt", NULL },
2496 { "ldt", NULL },
2497 //{ "tss", NULL },
2498 { "ioport", NULL },
2499 { "mmio", NULL },
2500 { "phys", NULL },
2501 //{ "pgmpd", NULL }, - doesn't always work at init time...
2502 { "timers", NULL },
2503 { "activetimers", NULL },
2504 { "handlers", "phys virt stats" },
2505 { "cfgm", NULL },
2506 };
2507 for (unsigned i = 0; i < ELEMENTS(aInfo); i++)
2508 {
2509 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2510 continue;
2511 pHlp->pfnPrintf(pHlp,
2512 "!!\n"
2513 "!! {%s, %s}\n"
2514 "!!\n",
2515 aInfo[i].pszInfo, aInfo[i].pszArgs);
2516 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2517 }
2518
2519 /* done */
2520 pHlp->pfnPrintf(pHlp,
2521 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2522
2523
2524 /*
2525 * Delete the output instance (flushing and restoring of flags).
2526 */
2527 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2528}
2529
2530
2531/**
2532 * Performs a testcase.
2533 *
2534 * @returns return value from the test.
2535 * @param pVM The VM handle.
2536 * @param enmTestcase The testcase operation to perform.
2537 * @param uVariation The testcase variation id.
2538 */
2539static int vmmR3DoGCTest(PVM pVM, VMMGCOPERATION enmTestcase, unsigned uVariation)
2540{
2541 RTGCPTR GCPtrEP;
2542 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
2543 if (VBOX_FAILURE(rc))
2544 return rc;
2545
2546 CPUMHyperSetCtxCore(pVM, NULL);
2547 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE);
2548 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2549 CPUMPushHyper(pVM, uVariation);
2550 CPUMPushHyper(pVM, enmTestcase);
2551 CPUMPushHyper(pVM, pVM->pVMGC);
2552 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2553 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2554 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2555 return SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2556}
2557
2558
2559/**
2560 * Performs a trap test.
2561 *
2562 * @returns Return value from the trap test.
2563 * @param pVM The VM handle.
2564 * @param u8Trap The trap number to test.
2565 * @param uVariation The testcase variation.
2566 * @param rcExpect The expected result.
2567 * @param u32Eax The expected eax value.
2568 * @param pszFaultEIP The fault address. Pass NULL if this isn't available or doesn't apply.
2569 * @param pszDesc The test description.
2570 */
2571static int vmmR3DoTrapTest(PVM pVM, uint8_t u8Trap, unsigned uVariation, int rcExpect, uint32_t u32Eax, const char *pszFaultEIP, const char *pszDesc)
2572{
2573 RTPrintf("VMM: testing 0%x / %d - %s\n", u8Trap, uVariation, pszDesc);
2574
2575 RTGCPTR GCPtrEP;
2576 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
2577 if (VBOX_FAILURE(rc))
2578 return rc;
2579
2580 CPUMHyperSetCtxCore(pVM, NULL);
2581 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE);
2582 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2583 CPUMPushHyper(pVM, uVariation);
2584 CPUMPushHyper(pVM, u8Trap + VMMGC_DO_TESTCASE_TRAP_FIRST);
2585 CPUMPushHyper(pVM, pVM->pVMGC);
2586 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2587 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2588 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2589 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2590 bool fDump = false;
2591 if (rc != rcExpect)
2592 {
2593 RTPrintf("VMM: FAILURE - rc=%Vrc expected %Vrc\n", rc, rcExpect);
2594 if (rc != VERR_NOT_IMPLEMENTED)
2595 fDump = true;
2596 }
2597 else if ( rcExpect != VINF_SUCCESS
2598 && u8Trap != 8 /* double fault doesn't dare set TrapNo. */
2599 && u8Trap != 3 /* guest only, we're not in guest. */
2600 && u8Trap != 1 /* guest only, we're not in guest. */
2601 && u8Trap != TRPMGetTrapNo(pVM))
2602 {
2603 RTPrintf("VMM: FAILURE - Trap %#x expected %#x\n", TRPMGetTrapNo(pVM), u8Trap);
2604 fDump = true;
2605 }
2606 else if (pszFaultEIP)
2607 {
2608 RTGCPTR GCPtrFault;
2609 int rc2 = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, pszFaultEIP, &GCPtrFault);
2610 if (VBOX_FAILURE(rc2))
2611 RTPrintf("VMM: FAILURE - Failed to resolve symbol '%s', %Vrc!\n", pszFaultEIP, rc);
2612 else if (GCPtrFault != CPUMGetHyperEIP(pVM))
2613 {
2614 RTPrintf("VMM: FAILURE - EIP=%VGv expected %VGv (%s)\n", CPUMGetHyperEIP(pVM), GCPtrFault, pszFaultEIP);
2615 fDump = true;
2616 }
2617 }
2618 else if (rcExpect != VINF_SUCCESS)
2619 {
2620 if (CPUMGetHyperSS(pVM) == SELMGetHyperDS(pVM))
2621 RTPrintf("VMM: FAILURE - ss=%x expected %x\n", CPUMGetHyperSS(pVM), SELMGetHyperDS(pVM));
2622 if (CPUMGetHyperES(pVM) == SELMGetHyperDS(pVM))
2623 RTPrintf("VMM: FAILURE - es=%x expected %x\n", CPUMGetHyperES(pVM), SELMGetHyperDS(pVM));
2624 if (CPUMGetHyperDS(pVM) == SELMGetHyperDS(pVM))
2625 RTPrintf("VMM: FAILURE - ds=%x expected %x\n", CPUMGetHyperDS(pVM), SELMGetHyperDS(pVM));
2626 if (CPUMGetHyperFS(pVM) == SELMGetHyperDS(pVM))
2627 RTPrintf("VMM: FAILURE - fs=%x expected %x\n", CPUMGetHyperFS(pVM), SELMGetHyperDS(pVM));
2628 if (CPUMGetHyperGS(pVM) == SELMGetHyperDS(pVM))
2629 RTPrintf("VMM: FAILURE - gs=%x expected %x\n", CPUMGetHyperGS(pVM), SELMGetHyperDS(pVM));
2630 if (CPUMGetHyperEDI(pVM) == 0x01234567)
2631 RTPrintf("VMM: FAILURE - edi=%x expected %x\n", CPUMGetHyperEDI(pVM), 0x01234567);
2632 if (CPUMGetHyperESI(pVM) == 0x42000042)
2633 RTPrintf("VMM: FAILURE - esi=%x expected %x\n", CPUMGetHyperESI(pVM), 0x42000042);
2634 if (CPUMGetHyperEBP(pVM) == 0xffeeddcc)
2635 RTPrintf("VMM: FAILURE - ebp=%x expected %x\n", CPUMGetHyperEBP(pVM), 0xffeeddcc);
2636 if (CPUMGetHyperEBX(pVM) == 0x89abcdef)
2637 RTPrintf("VMM: FAILURE - ebx=%x expected %x\n", CPUMGetHyperEBX(pVM), 0x89abcdef);
2638 if (CPUMGetHyperECX(pVM) == 0xffffaaaa)
2639 RTPrintf("VMM: FAILURE - ecx=%x expected %x\n", CPUMGetHyperECX(pVM), 0xffffaaaa);
2640 if (CPUMGetHyperEDX(pVM) == 0x77778888)
2641 RTPrintf("VMM: FAILURE - edx=%x expected %x\n", CPUMGetHyperEDX(pVM), 0x77778888);
2642 if (CPUMGetHyperEAX(pVM) == u32Eax)
2643 RTPrintf("VMM: FAILURE - eax=%x expected %x\n", CPUMGetHyperEAX(pVM), u32Eax);
2644 }
2645 if (fDump)
2646 VMMR3FatalDump(pVM, rc);
2647 return rc;
2648}
2649
2650
2651/* execute the switch. */
2652VMMR3DECL(int) VMMDoTest(PVM pVM)
2653{
2654#if 1
2655#ifdef NO_SUPCALLR0VMM
2656 RTPrintf("NO_SUPCALLR0VMM\n");
2657 return VINF_SUCCESS;
2658#endif
2659
2660 /*
2661 * Setup stack for calling VMMGCEntry().
2662 */
2663 RTGCPTR GCPtrEP;
2664 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
2665 if (VBOX_SUCCESS(rc))
2666 {
2667 RTPrintf("VMM: VMMGCEntry=%VGv\n", GCPtrEP);
2668
2669 /*
2670 * Test various crashes which we must be able to recover from.
2671 */
2672 vmmR3DoTrapTest(pVM, 0x3, 0, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3");
2673 vmmR3DoTrapTest(pVM, 0x3, 1, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3 WP");
2674
2675#if defined(DEBUG_bird) /* guess most people would like to skip these since they write to com1. */
2676 vmmR3DoTrapTest(pVM, 0x8, 0, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG]");
2677 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
2678 bool f;
2679 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "DoubleFault", &f);
2680#if !defined(DEBUG_bird)
2681 if (VBOX_SUCCESS(rc) && f)
2682#endif
2683 {
2684 /* see tripple fault warnings in SELM and VMMGC.cpp. */
2685 vmmR3DoTrapTest(pVM, 0x8, 1, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG] WP");
2686 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
2687 }
2688#endif
2689
2690 vmmR3DoTrapTest(pVM, 0xd, 0, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP");
2691 ///@todo find a better \#GP case, on intel ltr will \#PF (busy update?) and not \#GP.
2692 //vmmR3DoTrapTest(pVM, 0xd, 1, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP WP");
2693
2694 vmmR3DoTrapTest(pVM, 0xe, 0, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL)");
2695 vmmR3DoTrapTest(pVM, 0xe, 1, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL) WP");
2696 vmmR3DoTrapTest(pVM, 0xe, 2, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler");
2697 vmmR3DoTrapTest(pVM, 0xe, 4, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler and bad fs");
2698
2699 /*
2700 * Set a debug register and perform a context switch.
2701 */
2702 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2703 if (rc != VINF_SUCCESS)
2704 {
2705 RTPrintf("VMM: Nop test failed, rc=%Vrc not VINF_SUCCESS\n", rc);
2706 return rc;
2707 }
2708
2709 /* a harmless breakpoint */
2710 RTPrintf("VMM: testing hardware bp at 0x10000 (not hit)\n");
2711 DBGFADDRESS Addr;
2712 DBGFR3AddrFromFlat(pVM, &Addr, 0x10000);
2713 RTUINT iBp0;
2714 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp0);
2715 AssertReleaseRC(rc);
2716 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2717 if (rc != VINF_SUCCESS)
2718 {
2719 RTPrintf("VMM: DR0=0x10000 test failed with rc=%Vrc!\n", rc);
2720 return rc;
2721 }
2722
2723 /* a bad one at VMMGCEntry */
2724 RTPrintf("VMM: testing hardware bp at VMMGCEntry (hit)\n");
2725 DBGFR3AddrFromFlat(pVM, &Addr, GCPtrEP);
2726 RTUINT iBp1;
2727 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp1);
2728 AssertReleaseRC(rc);
2729 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2730 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
2731 {
2732 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Vrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
2733 return rc;
2734 }
2735
2736 /* resume the breakpoint */
2737 RTPrintf("VMM: resuming hyper after breakpoint\n");
2738 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_RF);
2739 rc = VMMR3ResumeHyper(pVM);
2740 if (rc != VINF_SUCCESS)
2741 {
2742 RTPrintf("VMM: failed to resume on hyper breakpoint, rc=%Vrc\n", rc);
2743 return rc;
2744 }
2745
2746 /* engage the breakpoint again and try single stepping. */
2747 RTPrintf("VMM: testing hardware bp at VMMGCEntry + stepping\n");
2748 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2749 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
2750 {
2751 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Vrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
2752 return rc;
2753 }
2754
2755 RTGCUINTREG OldPc = CPUMGetHyperEIP(pVM);
2756 RTPrintf("%RGr=>", OldPc);
2757 unsigned i;
2758 for (i = 0; i < 8; i++)
2759 {
2760 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
2761 rc = VMMR3ResumeHyper(pVM);
2762 if (rc != VINF_EM_DBG_HYPER_STEPPED)
2763 {
2764 RTPrintf("\nVMM: failed to step on hyper breakpoint, rc=%Vrc\n", rc);
2765 return rc;
2766 }
2767 RTGCUINTREG Pc = CPUMGetHyperEIP(pVM);
2768 RTPrintf("%RGr=>", Pc);
2769 if (Pc == OldPc)
2770 {
2771 RTPrintf("\nVMM: step failed, PC: %RGr -> %RGr\n", OldPc, Pc);
2772 return VERR_GENERAL_FAILURE;
2773 }
2774 OldPc = Pc;
2775 }
2776 RTPrintf("ok\n");
2777
2778 /* done, clear it */
2779 if ( VBOX_FAILURE(DBGFR3BpClear(pVM, iBp0))
2780 || VBOX_FAILURE(DBGFR3BpClear(pVM, iBp1)))
2781 {
2782 RTPrintf("VMM: Failed to clear breakpoints!\n");
2783 return VERR_GENERAL_FAILURE;
2784 }
2785 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2786 if (rc != VINF_SUCCESS)
2787 {
2788 RTPrintf("VMM: NOP failed, rc=%Vrc\n", rc);
2789 return rc;
2790 }
2791
2792 /*
2793 * Interrupt masking.
2794 */
2795 RTPrintf("VMM: interrupt masking...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
2796 for (i = 0; i < 10000; i++)
2797 {
2798 uint64_t StartTick = ASMReadTSC();
2799 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_INTERRUPT_MASKING, 0);
2800 if (rc != VINF_SUCCESS)
2801 {
2802 RTPrintf("VMM: Interrupt masking failed: rc=%Vrc\n", rc);
2803 return rc;
2804 }
2805 uint64_t Ticks = ASMReadTSC() - StartTick;
2806 if (Ticks < (SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000))
2807 RTPrintf("Warning: Ticks=%RU64 (< %RU64)\n", Ticks, SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000);
2808 }
2809
2810 /*
2811 * Interrupt forwarding.
2812 */
2813 CPUMHyperSetCtxCore(pVM, NULL);
2814 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2815 CPUMPushHyper(pVM, 0);
2816 CPUMPushHyper(pVM, VMMGC_DO_TESTCASE_HYPER_INTERRUPT);
2817 CPUMPushHyper(pVM, pVM->pVMGC);
2818 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2819 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2820 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2821 Log(("trampoline=%x\n", pVM->vmm.s.pfnGCCallTrampoline));
2822
2823 /*
2824 * Switch and do da thing.
2825 */
2826 RTPrintf("VMM: interrupt forwarding...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
2827 i = 0;
2828 uint64_t tsBegin = RTTimeNanoTS();
2829 uint64_t TickStart = ASMReadTSC();
2830 do
2831 {
2832 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2833 if (VBOX_FAILURE(rc))
2834 {
2835 Log(("VMM: GC returned fatal %Vra in iteration %d\n", rc, i));
2836 VMMR3FatalDump(pVM, rc);
2837 return rc;
2838 }
2839 i++;
2840 if (!(i % 32))
2841 Log(("VMM: iteration %d, esi=%08x edi=%08x ebx=%08x\n",
2842 i, CPUMGetHyperESI(pVM), CPUMGetHyperEDI(pVM), CPUMGetHyperEBX(pVM)));
2843 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2844 uint64_t TickEnd = ASMReadTSC();
2845 uint64_t tsEnd = RTTimeNanoTS();
2846
2847 uint64_t Elapsed = tsEnd - tsBegin;
2848 uint64_t PerIteration = Elapsed / (uint64_t)i;
2849 uint64_t cTicksElapsed = TickEnd - TickStart;
2850 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
2851
2852 RTPrintf("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
2853 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration);
2854 Log(("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
2855 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration));
2856
2857 /*
2858 * These forced actions are not necessary for the test and trigger breakpoints too.
2859 */
2860 VM_FF_CLEAR(pVM, VM_FF_TRPM_SYNC_IDT);
2861 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
2862
2863 /*
2864 * Profile switching.
2865 */
2866 RTPrintf("VMM: profiling switcher...\n");
2867 Log(("VMM: profiling switcher...\n"));
2868 uint64_t TickMin = ~0;
2869 tsBegin = RTTimeNanoTS();
2870 TickStart = ASMReadTSC();
2871 for (i = 0; i < 1000000; i++)
2872 {
2873 CPUMHyperSetCtxCore(pVM, NULL);
2874 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2875 CPUMPushHyper(pVM, 0);
2876 CPUMPushHyper(pVM, VMMGC_DO_TESTCASE_NOP);
2877 CPUMPushHyper(pVM, pVM->pVMGC);
2878 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2879 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2880 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2881
2882 uint64_t TickThisStart = ASMReadTSC();
2883 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2884 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
2885 if (VBOX_FAILURE(rc))
2886 {
2887 Log(("VMM: GC returned fatal %Vra in iteration %d\n", rc, i));
2888 VMMR3FatalDump(pVM, rc);
2889 return rc;
2890 }
2891 if (TickThisElapsed < TickMin)
2892 TickMin = TickThisElapsed;
2893 }
2894 TickEnd = ASMReadTSC();
2895 tsEnd = RTTimeNanoTS();
2896
2897 Elapsed = tsEnd - tsBegin;
2898 PerIteration = Elapsed / (uint64_t)i;
2899 cTicksElapsed = TickEnd - TickStart;
2900 cTicksPerIteration = cTicksElapsed / (uint64_t)i;
2901
2902 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
2903 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
2904 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
2905 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
2906
2907 rc = VINF_SUCCESS;
2908 }
2909 else
2910 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Vrc\n", rc));
2911#endif
2912 return rc;
2913}
2914
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