VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 1313

Last change on this file since 1313 was 1313, checked in by vboxsync, 18 years ago

Moved the VMM tests into a separate file.
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1/* $Id: VMM.cpp 1313 2007-03-07 20:22:12Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22//#define NO_SUPCALLR0VMM
23
24/** @page pg_vmm VMM - The Virtual Machine Monitor
25 *
26 * !Revise this! It's already incorrect!
27 *
28 * The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
29 * manages the alternate reality; controlling the virtualization, managing
30 * resources, tracking CPU state, it's resources and so on...
31 *
32 * We will split the VMM into smaller entities:
33 *
34 * - Virtual Machine Core Monitor (VMCM), which purpose it is to
35 * provide ring and world switching, that including routing
36 * interrupts to the host OS and traps to the appropriate trap
37 * handlers. It will implement an external interface for
38 * managing trap handlers.
39 *
40 * - CPU Monitor (CM), tracking the state of the CPU (in the alternate
41 * reality) and implementing external interfaces to read and change
42 * the state.
43 *
44 * - Memory Monitor (MM), which purpose it is to virtualize physical
45 * pages, segment descriptor tables, interrupt descriptor tables, task
46 * segments, and keep track of all memory providing external interfaces
47 * to access content and map pages. (Internally splitt into smaller entities!)
48 *
49 * - IO Monitor (IOM), which virtualizes in and out I/O operations. It
50 * interacts with the MM to implement memory mapped I/O. External
51 * interfaces for adding and removing I/O ranges are implemented.
52 *
53 * - External Interrupt Monitor (EIM), which purpose it is to manage
54 * interrupts generated by virtual devices. This monitor provides
55 * an interfaces for raising interrupts which is accessible at any
56 * time and from all thread.
57 * <p>
58 * A subentity of the EIM is the vitual Programmable Interrupt
59 * Controller Device (VPICD), and perhaps a virtual I/O Advanced
60 * Programmable Interrupt Controller Device (VAPICD).
61 *
62 * - Direct Memory Access Monitor (DMAM), which purpose it is to support
63 * virtual device using the DMA controller. Interfaces must be as the
64 * EIM interfaces independent and threadable.
65 * <p>
66 * A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
67 *
68 *
69 * Entities working on a higher level:
70 *
71 * - Device Manager (DM), which is a support facility for virtualized
72 * hardware. This provides generic facilities for efficient device
73 * virtualization. It will manage device attaching and detaching
74 * conversing with EIM and IOM.
75 *
76 * - Debugger Facility (DBGF) provides the basic features for
77 * debugging the alternate reality execution.
78 *
79 *
80 *
81 * @section pg_vmm_s_use_cases Use Cases
82 *
83 * @subsection pg_vmm_s_use_case_boot Bootstrap
84 *
85 * - Basic Init:
86 * - Init SUPDRV.
87 *
88 * - Init Virtual Machine Instance:
89 * - Load settings.
90 * - Check resource requirements (memory, com, stuff).
91 *
92 * - Init Host Ring 3 part:
93 * - Init Core code.
94 * - Load Pluggable Components.
95 * - Init Pluggable Components.
96 *
97 * - Init Host Ring 0 part:
98 * - Load Core (core = core components like VMM, RMI, CA, and so on) code.
99 * - Init Core code.
100 * - Load Pluggable Component code.
101 * - Init Pluggable Component code.
102 *
103 * - Allocate first chunk of memory and pin it down. This block of memory
104 * will fit the following pieces:
105 * - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
106 * (This is available from everywhere (at different addresses though)).
107 * - VMM Guest Context code.
108 * - Pluggable devices Guest Context code.
109 * - Page tables (directory and everything) for the VMM Guest
110 *
111 * - Setup Guest (Ring 0) part:
112 * - Setup initial page tables (i.e. directory all the stuff).
113 * - Load Core Guest Context code.
114 * - Load Pluggable Devices Guest Context code.
115 *
116 *
117 */
118
119
120/*******************************************************************************
121* Header Files *
122*******************************************************************************/
123#define LOG_GROUP LOG_GROUP_VMM
124#include <VBox/vmm.h>
125#include <VBox/vmapi.h>
126#include <VBox/pgm.h>
127#include <VBox/cfgm.h>
128#include <VBox/pdm.h>
129#include <VBox/cpum.h>
130#include <VBox/mm.h>
131#include <VBox/iom.h>
132#include <VBox/trpm.h>
133#include <VBox/selm.h>
134#include <VBox/em.h>
135#include <VBox/sup.h>
136#include <VBox/dbgf.h>
137#include <VBox/csam.h>
138#include <VBox/patm.h>
139#include <VBox/rem.h>
140#include <VBox/ssm.h>
141#include <VBox/tm.h>
142#include "VMMInternal.h"
143#include "VMMSwitcher/VMMSwitcher.h"
144#include <VBox/vm.h>
145#include <VBox/err.h>
146#include <VBox/param.h>
147#include <VBox/version.h>
148#include <VBox/x86.h>
149#include <VBox/hwaccm.h>
150#include <iprt/assert.h>
151#include <iprt/alloc.h>
152#include <iprt/asm.h>
153#include <iprt/time.h>
154#include <iprt/stream.h>
155#include <iprt/string.h>
156#include <iprt/stdarg.h>
157#include <iprt/ctype.h>
158
159
160
161/** The saved state version. */
162#define VMM_SAVED_STATE_VERSION 3
163
164
165/*******************************************************************************
166* Internal Functions *
167*******************************************************************************/
168static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
169static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
170static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
171static int vmmR3ServiceCallHostRequest(PVM pVM);
172
173
174/*******************************************************************************
175* Global Variables *
176*******************************************************************************/
177/** Array of switcher defininitions.
178 * The type and index shall match!
179 */
180static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
181{
182 NULL, /* invalid entry */
183#ifndef __AMD64__
184 &vmmR3Switcher32BitTo32Bit_Def,
185 &vmmR3Switcher32BitToPAE_Def,
186 NULL, //&vmmR3Switcher32BitToAMD64_Def,
187 &vmmR3SwitcherPAETo32Bit_Def,
188 &vmmR3SwitcherPAEToPAE_Def,
189 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
190# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
191 &vmmR3SwitcherAMD64ToPAE_Def,
192# else
193 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
194# endif
195 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
196#else
197 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
198 NULL, //&vmmR3Switcher32BitToPAE_Def,
199 NULL, //&vmmR3Switcher32BitToAMD64_Def,
200 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
201 NULL, //&vmmR3SwitcherPAEToPAE_Def,
202 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
203 &vmmR3SwitcherAMD64ToPAE_Def,
204 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
205#endif
206};
207
208
209
210/**
211 * Initiates the core code.
212 *
213 * This is core per VM code which might need fixups and/or for ease of use
214 * are put on linear contiguous backing.
215 *
216 * @returns VBox status code.
217 * @param pVM Pointer to VM structure.
218 */
219static int vmmR3InitCoreCode(PVM pVM)
220{
221 /*
222 * Calc the size.
223 */
224 unsigned cbCoreCode = 0;
225 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
226 {
227 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
228 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
229 if (pSwitcher)
230 {
231 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
232 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
233 }
234 }
235
236 /*
237 * Allocate continguous pages for switchers and deal with
238 * conflicts in the intermediate mapping of the code.
239 */
240 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
241 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
242 int rc = VERR_NO_MEMORY;
243 if (pVM->vmm.s.pvHCCoreCodeR3)
244 {
245 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
246 if (rc == VERR_PGM_MAPPINGS_FIX_CONFLICT)
247 {
248 /* try more allocations. */
249 struct
250 {
251 RTR0PTR pvR0;
252 void *pvR3;
253 RTHCPHYS HCPhys;
254 } aBadTries[16];
255 unsigned i = 0;
256 do
257 {
258 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
259 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
260 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
261 i++;
262 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
263 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
264 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
265 if (!pVM->vmm.s.pvHCCoreCodeR3)
266 break;
267 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
268 } while ( rc == VERR_PGM_MAPPINGS_FIX_CONFLICT
269 && i < ELEMENTS(aBadTries) - 1);
270
271 /* cleanup */
272 if (VBOX_FAILURE(rc))
273 {
274 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
275 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
276 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
277 i++;
278 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
279 }
280 while (i-- > 0)
281 {
282 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
283 i, aBadTries[i].pvR3, aBadTries[i].pvR0, aBadTries[i].HCPhys));
284 SUPContFree(aBadTries[i].pvR3);
285 }
286 }
287 }
288 if (VBOX_SUCCESS(rc))
289 {
290 /*
291 * copy the code.
292 */
293 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
294 {
295 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
296 if (pSwitcher)
297 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
298 pSwitcher->pvCode, pSwitcher->cbCode);
299 }
300
301 /*
302 * Map the code into the GC address space.
303 */
304 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &pVM->vmm.s.pvGCCoreCode);
305 if (VBOX_SUCCESS(rc))
306 {
307 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
308 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VGv Phys=%VHp cb=%#x\n",
309 pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
310
311 /*
312 * Finally, PGM probably have selected a switcher already but we need
313 * to do get the addresses so we'll reselect it.
314 * This may legally fail so, we're ignoring the rc.
315 */
316 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
317 return rc;
318 }
319
320 /* shit */
321 AssertMsgFailed(("PGMR3Map(,%VGv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
322 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3);
323 }
324 else
325 VMSetError(pVM, rc, RT_SRC_POS,
326 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code."),
327 cbCoreCode);
328
329 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
330 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
331 pVM->vmm.s.pvGCCoreCode = 0;
332 return rc;
333}
334
335
336/**
337 * Initializes the VMM.
338 *
339 * @returns VBox status code.
340 * @param pVM The VM to operate on.
341 */
342VMMR3DECL(int) VMMR3Init(PVM pVM)
343{
344 LogFlow(("VMMR3Init\n"));
345
346 /*
347 * Assert alignment, sizes and order.
348 */
349 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
350 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
351 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
352 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
353
354 /*
355 * Init basic VM VMM members.
356 */
357 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
358 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
359 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
360 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
361 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
362 else
363 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
364
365 /* GC switchers are enabled by default. Turned off by HWACCM. */
366 pVM->vmm.s.fSwitcherDisabled = false;
367
368 /*
369 * Register the saved state data unit.
370 */
371 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
372 NULL, vmmR3Save, NULL,
373 NULL, vmmR3Load, NULL);
374 if (VBOX_FAILURE(rc))
375 return rc;
376
377#ifdef VBOX_WITHOUT_IDT_PATCHING
378 /*
379 * Register the Ring-0 VM handle with the session for fast ioctl calls.
380 */
381 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
382 if (VBOX_FAILURE(rc))
383 return rc;
384#endif
385
386 /*
387 * Init core code.
388 */
389 rc = vmmR3InitCoreCode(pVM);
390 if (VBOX_SUCCESS(rc))
391 {
392 /*
393 * Allocate & init VMM GC stack.
394 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
395 * (The page protection is modifed during R3 init completion.)
396 */
397#ifdef VBOX_STRICT_VMM_STACK
398 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
399#else
400 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
401#endif
402 if (VBOX_SUCCESS(rc))
403 {
404 /* Set HC and GC stack pointers to top of stack. */
405 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
406 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
407 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
408 AssertRelease(pVM->vmm.s.pbGCStack);
409
410 /* Set hypervisor eip. */
411 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
412
413 /*
414 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
415 */
416#ifdef LOG_ENABLED
417 PRTLOGGER pLogger = RTLogDefaultInstance();
418 if (pLogger)
419 {
420 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pLogger->cGroups]);
421 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
422 if (VBOX_SUCCESS(rc))
423 {
424 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
425
426/*
427 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
428 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
429 *
430 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
431 * to not stub all the log functions.
432 */
433# ifdef DEBUG_sandervl
434 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
435 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
436 if (VBOX_SUCCESS(rc))
437 {
438 pVM->vmm.s.pR0Logger->pVM = pVM;
439 //pVM->vmm.s.pR0Logger->fCreated = false;
440 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
441 }
442# endif
443 }
444 }
445#endif /* LOG_ENABLED */
446
447#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
448 /*
449 * Allocate GC Release Logger instances (finalized in the relocator).
450 */
451 if (VBOX_SUCCESS(rc))
452 {
453 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
454 if (pRelLogger)
455 {
456 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pRelLogger->cGroups]);
457 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
458 if (VBOX_SUCCESS(rc))
459 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
460 }
461 }
462#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
463
464#ifdef VBOX_WITH_NMI
465 /*
466 * Allocate mapping for the host APIC.
467 */
468 if (VBOX_SUCCESS(rc))
469 {
470 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
471 AssertRC(rc);
472 }
473#endif
474 if (VBOX_SUCCESS(rc))
475 {
476 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
477 if (VBOX_SUCCESS(rc))
478 {
479 /*
480 * Statistics.
481 */
482 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
483 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
484 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
485 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
486 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
487 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
488 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
489 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
490 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
491 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
492 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
493 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
494 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
495 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
496 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READWRITE returns.");
497 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
498 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
499 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
500 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
501 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
502 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
503 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
504 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
505 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
506 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
507 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
508 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
509 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
510 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
511 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
512 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
513 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
514 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
517 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
518 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
519 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
520 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
521 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
522 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
523 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
524 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
525 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
526 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
527 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
528 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
529 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
530 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
531 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
532
533 return VINF_SUCCESS;
534 }
535 AssertRC(rc);
536 }
537 }
538 /** @todo: Need failure cleanup. */
539
540 //more todo in here?
541 //if (VBOX_SUCCESS(rc))
542 //{
543 //}
544 //int rc2 = vmmR3TermCoreCode(pVM);
545 //AssertRC(rc2));
546 }
547
548 return rc;
549}
550
551
552/**
553 * Ring-3 init finalizing.
554 *
555 * @returns VBox status code.
556 * @param pVM The VM handle.
557 */
558VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
559{
560#ifdef VBOX_STRICT_VMM_STACK
561 /*
562 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
563 */
564 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
565 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
566 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
567
568 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
569 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
570 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
571#endif
572
573 /*
574 * Set page attributes to r/w for stack pages.
575 */
576 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
577 AssertRC(rc);
578 if (VBOX_SUCCESS(rc))
579 {
580 /*
581 * Create the EMT yield timer.
582 */
583 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
584 if (VBOX_SUCCESS(rc))
585 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
586 }
587#ifdef VBOX_WITH_NMI
588 /*
589 * Map the host APIC into GC - This may be host os specific!
590 */
591 if (VBOX_SUCCESS(rc))
592 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
593 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
594#endif
595 return rc;
596}
597
598
599/**
600 * Initializes the R0 VMM.
601 *
602 * @returns VBox status code.
603 * @param pVM The VM to operate on.
604 */
605VMMR3DECL(int) VMMR3InitR0(PVM pVM)
606{
607 int rc;
608
609 /*
610 * Initialize the ring-0 logger if we haven't done so yet.
611 */
612 if ( pVM->vmm.s.pR0Logger
613 && !pVM->vmm.s.pR0Logger->fCreated)
614 {
615 rc = VMMR3UpdateLoggers(pVM);
616 if (VBOX_FAILURE(rc))
617 return rc;
618 }
619
620 /*
621 * Call Ring-0 entry with init code.
622 */
623 for (;;)
624 {
625#ifdef NO_SUPCALLR0VMM
626 //rc = VERR_GENERAL_FAILURE;
627 rc = VINF_SUCCESS;
628#else
629 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, (void *)VBOX_VERSION);
630#endif
631 if ( pVM->vmm.s.pR0Logger
632 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
633 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
634 if (rc != VINF_VMM_CALL_HOST)
635 break;
636 rc = vmmR3ServiceCallHostRequest(pVM);
637 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
638 break;
639 break; // remove this when we do setjmp for all ring-0 stuff.
640 }
641
642 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
643 {
644 LogRel(("R0 init failed, rc=%Vra\n", rc));
645 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
646 rc = VERR_INTERNAL_ERROR;
647 }
648 return rc;
649}
650
651
652/**
653 * Initializes the GC VMM.
654 *
655 * @returns VBox status code.
656 * @param pVM The VM to operate on.
657 */
658VMMR3DECL(int) VMMR3InitGC(PVM pVM)
659{
660 /* In VMX mode, there's no need to init GC. */
661 if (pVM->vmm.s.fSwitcherDisabled)
662 return VINF_SUCCESS;
663
664 /*
665 * Call VMMGCInit():
666 * -# resolve the address.
667 * -# setup stackframe and EIP to use the trampoline.
668 * -# do a generic hypervisor call.
669 */
670 RTGCPTR GCPtrEP;
671 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
672 if (VBOX_SUCCESS(rc))
673 {
674 CPUMHyperSetCtxCore(pVM, NULL);
675 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
676 CPUMPushHyper(pVM, VBOX_VERSION); /* Param 2: Version argument. */
677 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
678 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
679 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* trampoline param: stacksize. */
680 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
681 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
682
683 for (;;)
684 {
685#ifdef NO_SUPCALLR0VMM
686 //rc = VERR_GENERAL_FAILURE;
687 rc = VINF_SUCCESS;
688#else
689 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
690#endif
691#ifdef LOG_ENABLED
692 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
693 if ( pLogger
694 && pLogger->offScratch > 0)
695 RTLogFlushGC(NULL, pLogger);
696#endif
697#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
698 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
699 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
700 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
701#endif
702 if (rc != VINF_VMM_CALL_HOST)
703 break;
704 rc = vmmR3ServiceCallHostRequest(pVM);
705 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
706 break;
707 }
708
709 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
710 {
711 VMMR3FatalDump(pVM, rc);
712 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
713 rc = VERR_INTERNAL_ERROR;
714 }
715 AssertRC(rc);
716 }
717 return rc;
718}
719
720
721/**
722 * Terminate the VMM bits.
723 *
724 * @returns VINF_SUCCESS.
725 * @param pVM The VM handle.
726 */
727VMMR3DECL(int) VMMR3Term(PVM pVM)
728{
729 /** @todo must call ring-0 so the logger thread instance can be properly removed. */
730
731#ifdef VBOX_STRICT_VMM_STACK
732 /*
733 * Make the two stack guard pages present again.
734 */
735 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
736 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
737#endif
738 return VINF_SUCCESS;
739}
740
741
742/**
743 * Applies relocations to data and code managed by this
744 * component. This function will be called at init and
745 * whenever the VMM need to relocate it self inside the GC.
746 *
747 * The VMM will need to apply relocations to the core code.
748 *
749 * @param pVM The VM handle.
750 * @param offDelta The relocation delta.
751 */
752VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
753{
754 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
755
756 /*
757 * Recalc the GC address.
758 */
759 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
760
761 /*
762 * The stack.
763 */
764 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
765 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
766 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
767
768 /*
769 * All the switchers.
770 */
771 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
772 {
773 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
774 if (pSwitcher && pSwitcher->pfnRelocate)
775 {
776 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
777 pSwitcher->pfnRelocate(pVM,
778 pSwitcher,
779 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
780 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
781 pVM->vmm.s.pvGCCoreCode + off,
782 pVM->vmm.s.HCPhysCoreCode + off);
783 }
784 }
785
786 /*
787 * Recalc the GC address for the current switcher.
788 */
789 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
790 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
791 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
792 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
793 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
794 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
795 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
796
797 /*
798 * Get other GC entry points.
799 */
800 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
801 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
802
803 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
804 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
805
806 /*
807 * Update the logger.
808 */
809 VMMR3UpdateLoggers(pVM);
810}
811
812
813/**
814 * Updates the settings for the GC and R0 loggers.
815 *
816 * @returns VBox status code.
817 * @param pVM The VM handle.
818 */
819VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
820{
821 /*
822 * Simply clone the logger instance (for GC).
823 */
824 int rc = VINF_SUCCESS;
825 RTGCPTR GCPtrLoggerFlush = 0;
826
827 if (pVM->vmm.s.pLoggerHC
828#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
829 || pVM->vmm.s.pRelLoggerHC
830#endif
831 )
832 {
833 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
834 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
835 }
836
837 if (pVM->vmm.s.pLoggerHC)
838 {
839 RTGCPTR GCPtrLoggerWrapper = 0;
840 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
841 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
842 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
843 rc = RTLogCloneGC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
844 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
845 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
846 }
847
848#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
849 if (pVM->vmm.s.pRelLoggerHC)
850 {
851 RTGCPTR GCPtrLoggerWrapper = 0;
852 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
853 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
854 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
855 rc = RTLogCloneGC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
856 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
857 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
858 }
859#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
860
861 /*
862 * For the ring-0 EMT logger, we use a per-thread logger
863 * instance in ring-0. Only initialize it once.
864 */
865 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
866 if (pR0Logger)
867 {
868 if (!pR0Logger->fCreated)
869 {
870 RTHCPTR pfnLoggerWrapper = NULL;
871 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
872 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
873
874 RTHCPTR pfnLoggerFlush = NULL;
875 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
876 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
877
878 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
879 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
880 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
881 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
882 pR0Logger->fCreated = true;
883 }
884
885 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, RTLOGFLAGS_BUFFERED, 0);
886 AssertRC(rc);
887 }
888
889 return rc;
890}
891
892
893/**
894 * Generic switch code relocator.
895 *
896 * @param pVM The VM handle.
897 * @param pSwitcher The switcher definition.
898 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
899 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
900 * @param GCPtrCode The guest context address corresponding to pu8Code.
901 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
902 * @param SelCS The hypervisor CS selector.
903 * @param SelDS The hypervisor DS selector.
904 * @param SelTSS The hypervisor TSS selector.
905 * @param GCPtrGDT The GC address of the hypervisor GDT.
906 * @param SelCS64 The 64-bit mode hypervisor CS selector.
907 */
908static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
909 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
910{
911 union
912 {
913 const uint8_t *pu8;
914 const uint16_t *pu16;
915 const uint32_t *pu32;
916 const uint64_t *pu64;
917 const void *pv;
918 uintptr_t u;
919 } u;
920 u.pv = pSwitcher->pvFixups;
921
922 /*
923 * Process fixups.
924 */
925 uint8_t u8;
926 while ((u8 = *u.pu8++) != FIX_THE_END)
927 {
928 /*
929 * Get the source (where to write the fixup).
930 */
931 uint32_t offSrc = *u.pu32++;
932 Assert(offSrc < pSwitcher->cbCode);
933 union
934 {
935 uint8_t *pu8;
936 uint16_t *pu16;
937 uint32_t *pu32;
938 uint64_t *pu64;
939 uintptr_t u;
940 } uSrc;
941 uSrc.pu8 = pu8CodeR3 + offSrc;
942
943 /* The fixup target and method depends on the type. */
944 switch (u8)
945 {
946 /*
947 * 32-bit relative, source in HC and target in GC.
948 */
949 case FIX_HC_2_GC_NEAR_REL:
950 {
951 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
952 uint32_t offTrg = *u.pu32++;
953 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
954 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
955 break;
956 }
957
958 /*
959 * 32-bit relative, source in HC and target in ID.
960 */
961 case FIX_HC_2_ID_NEAR_REL:
962 {
963 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
964 uint32_t offTrg = *u.pu32++;
965 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
966 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (uSrc.u + 4));
967 break;
968 }
969
970 /*
971 * 32-bit relative, source in GC and target in HC.
972 */
973 case FIX_GC_2_HC_NEAR_REL:
974 {
975 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
976 uint32_t offTrg = *u.pu32++;
977 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
978 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
979 break;
980 }
981
982 /*
983 * 32-bit relative, source in GC and target in ID.
984 */
985 case FIX_GC_2_ID_NEAR_REL:
986 {
987 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
988 uint32_t offTrg = *u.pu32++;
989 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
990 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
991 break;
992 }
993
994 /*
995 * 32-bit relative, source in ID and target in HC.
996 */
997 case FIX_ID_2_HC_NEAR_REL:
998 {
999 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1000 uint32_t offTrg = *u.pu32++;
1001 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1002 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1003 break;
1004 }
1005
1006 /*
1007 * 32-bit relative, source in ID and target in HC.
1008 */
1009 case FIX_ID_2_GC_NEAR_REL:
1010 {
1011 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1012 uint32_t offTrg = *u.pu32++;
1013 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1014 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1015 break;
1016 }
1017
1018 /*
1019 * 16:32 far jump, target in GC.
1020 */
1021 case FIX_GC_FAR32:
1022 {
1023 uint32_t offTrg = *u.pu32++;
1024 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1025 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1026 *uSrc.pu16++ = SelCS;
1027 break;
1028 }
1029
1030 /*
1031 * Make 32-bit GC pointer given CPUM offset.
1032 */
1033 case FIX_GC_CPUM_OFF:
1034 {
1035 uint32_t offCPUM = *u.pu32++;
1036 Assert(offCPUM < sizeof(pVM->cpum));
1037 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1038 break;
1039 }
1040
1041 /*
1042 * Make 32-bit GC pointer given VM offset.
1043 */
1044 case FIX_GC_VM_OFF:
1045 {
1046 uint32_t offVM = *u.pu32++;
1047 Assert(offVM < sizeof(VM));
1048 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1049 break;
1050 }
1051
1052 /*
1053 * Make 32-bit HC pointer given CPUM offset.
1054 */
1055 case FIX_HC_CPUM_OFF:
1056 {
1057 uint32_t offCPUM = *u.pu32++;
1058 Assert(offCPUM < sizeof(pVM->cpum));
1059 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1060 break;
1061 }
1062
1063 /*
1064 * Make 32-bit R0 pointer given VM offset.
1065 */
1066 case FIX_HC_VM_OFF:
1067 {
1068 uint32_t offVM = *u.pu32++;
1069 Assert(offVM < sizeof(VM));
1070 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1071 break;
1072 }
1073
1074 /*
1075 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1076 */
1077 case FIX_INTER_32BIT_CR3:
1078 {
1079
1080 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1081 break;
1082 }
1083
1084 /*
1085 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1086 */
1087 case FIX_INTER_PAE_CR3:
1088 {
1089
1090 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1091 break;
1092 }
1093
1094 /*
1095 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1096 */
1097 case FIX_INTER_AMD64_CR3:
1098 {
1099
1100 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1101 break;
1102 }
1103
1104 /*
1105 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1106 */
1107 case FIX_HYPER_32BIT_CR3:
1108 {
1109
1110 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1111 break;
1112 }
1113
1114 /*
1115 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1116 */
1117 case FIX_HYPER_PAE_CR3:
1118 {
1119
1120 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1121 break;
1122 }
1123
1124 /*
1125 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1126 */
1127 case FIX_HYPER_AMD64_CR3:
1128 {
1129
1130 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1131 break;
1132 }
1133
1134 /*
1135 * Store Hypervisor CS (16-bit).
1136 */
1137 case FIX_HYPER_CS:
1138 {
1139 *uSrc.pu16 = SelCS;
1140 break;
1141 }
1142
1143 /*
1144 * Store Hypervisor DS (16-bit).
1145 */
1146 case FIX_HYPER_DS:
1147 {
1148 *uSrc.pu16 = SelDS;
1149 break;
1150 }
1151
1152 /*
1153 * Store Hypervisor TSS (16-bit).
1154 */
1155 case FIX_HYPER_TSS:
1156 {
1157 *uSrc.pu16 = SelTSS;
1158 break;
1159 }
1160
1161 /*
1162 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1163 */
1164 case FIX_GC_TSS_GDTE_DW2:
1165 {
1166 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1167 *uSrc.pu32 = (uint32_t)GCPtr;
1168 break;
1169 }
1170
1171
1172 ///@todo case FIX_CR4_MASK:
1173 ///@todo case FIX_CR4_OSFSXR:
1174
1175 /*
1176 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1177 */
1178 case FIX_NO_FXSAVE_JMP:
1179 {
1180 uint32_t offTrg = *u.pu32++;
1181 Assert(offTrg < pSwitcher->cbCode);
1182 if (!CPUMSupportsFXSR(pVM))
1183 {
1184 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1185 *uSrc.pu32++ = offTrg - (offSrc + 5);
1186 }
1187 else
1188 {
1189 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1190 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1191 }
1192 break;
1193 }
1194
1195 /*
1196 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1197 */
1198 case FIX_NO_SYSENTER_JMP:
1199 {
1200 uint32_t offTrg = *u.pu32++;
1201 Assert(offTrg < pSwitcher->cbCode);
1202 if (!CPUMIsHostUsingSysEnter(pVM))
1203 {
1204 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1205 *uSrc.pu32++ = offTrg - (offSrc + 5);
1206 }
1207 else
1208 {
1209 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1210 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1211 }
1212 break;
1213 }
1214
1215 /*
1216 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1217 */
1218 case FIX_NO_SYSCALL_JMP:
1219 {
1220 uint32_t offTrg = *u.pu32++;
1221 Assert(offTrg < pSwitcher->cbCode);
1222 if (!CPUMIsHostUsingSysEnter(pVM))
1223 {
1224 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1225 *uSrc.pu32++ = offTrg - (offSrc + 5);
1226 }
1227 else
1228 {
1229 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1230 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1231 }
1232 break;
1233 }
1234
1235 /*
1236 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1237 */
1238 case FIX_HC_32BIT:
1239 {
1240 uint32_t offTrg = *u.pu32++;
1241 Assert(offSrc < pSwitcher->cbCode);
1242 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1243 *uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1244 break;
1245 }
1246
1247#if defined(__AMD64__) || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1248 /*
1249 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1250 */
1251 case FIX_HC_64BIT:
1252 {
1253 uint32_t offTrg = *u.pu32++;
1254 Assert(offSrc < pSwitcher->cbCode);
1255 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1256 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1257 break;
1258 }
1259
1260 /*
1261 * 64-bit HC Code Selector (no argument).
1262 */
1263 case FIX_HC_64BIT_CS:
1264 {
1265 Assert(offSrc < pSwitcher->cbCode);
1266#if defined(__DARWIN__) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1267 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
1268#else
1269 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1270#endif
1271 break;
1272 }
1273
1274 /*
1275 * 64-bit HC pointer to the CPUM instance data (no argument).
1276 */
1277 case FIX_HC_64BIT_CPUM:
1278 {
1279 Assert(offSrc < pSwitcher->cbCode);
1280 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1281 break;
1282 }
1283#endif
1284
1285 /*
1286 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1287 */
1288 case FIX_ID_32BIT:
1289 {
1290 uint32_t offTrg = *u.pu32++;
1291 Assert(offSrc < pSwitcher->cbCode);
1292 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1293 *uSrc.pu32 = u32IDCode + offTrg;
1294 break;
1295 }
1296
1297 /*
1298 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1299 */
1300 case FIX_ID_64BIT:
1301 {
1302 uint32_t offTrg = *u.pu32++;
1303 Assert(offSrc < pSwitcher->cbCode);
1304 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1305 *uSrc.pu64 = u32IDCode + offTrg;
1306 break;
1307 }
1308
1309 /*
1310 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1311 */
1312 case FIX_ID_FAR32_TO_64BIT_MODE:
1313 {
1314 uint32_t offTrg = *u.pu32++;
1315 Assert(offSrc < pSwitcher->cbCode);
1316 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1317 *uSrc.pu32++ = u32IDCode + offTrg;
1318 *uSrc.pu16 = SelCS64;
1319 AssertRelease(SelCS64);
1320 break;
1321 }
1322
1323#ifdef VBOX_WITH_NMI
1324 /*
1325 * 32-bit address to the APIC base.
1326 */
1327 case FIX_GC_APIC_BASE_32BIT:
1328 {
1329 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1330 break;
1331 }
1332#endif
1333
1334 default:
1335 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1336 break;
1337 }
1338 }
1339
1340#ifdef LOG_ENABLED
1341 /*
1342 * If Log2 is enabled disassemble the switcher code.
1343 *
1344 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1345 */
1346 if (LogIs2Enabled())
1347 {
1348 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1349 " pu8CodeR0 = %p\n"
1350 " pu8CodeR3 = %p\n"
1351 " GCPtrCode = %VGv\n"
1352 " u32IDCode = %08x\n"
1353 " pVMGC = %VGv\n"
1354 " pCPUMGC = %VGv\n"
1355 " pVMHC = %p\n"
1356 " pCPUMHC = %p\n"
1357 " GCPtrGDT = %VGv\n"
1358 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1359 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1360 " SelCS = %04x\n"
1361 " SelDS = %04x\n"
1362 " SelCS64 = %04x\n"
1363 " SelTSS = %04x\n",
1364 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1365 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1366 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1367 GCPtrGDT,
1368 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1369 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1370 SelCS, SelDS, SelCS64, SelTSS);
1371
1372 uint32_t offCode = 0;
1373 while (offCode < pSwitcher->cbCode)
1374 {
1375 /*
1376 * Figure out where this is.
1377 */
1378 const char *pszDesc = NULL;
1379 RTUINTPTR uBase;
1380 uint32_t cbCode;
1381 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1382 {
1383 pszDesc = "HCCode0";
1384 uBase = (RTUINTPTR)pu8CodeR0;
1385 offCode = pSwitcher->offHCCode0;
1386 cbCode = pSwitcher->cbHCCode0;
1387 }
1388 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1389 {
1390 pszDesc = "HCCode1";
1391 uBase = (RTUINTPTR)pu8CodeR0;
1392 offCode = pSwitcher->offHCCode1;
1393 cbCode = pSwitcher->cbHCCode1;
1394 }
1395 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1396 {
1397 pszDesc = "GCCode";
1398 uBase = GCPtrCode;
1399 offCode = pSwitcher->offGCCode;
1400 cbCode = pSwitcher->cbGCCode;
1401 }
1402 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1403 {
1404 pszDesc = "IDCode0";
1405 uBase = u32IDCode;
1406 offCode = pSwitcher->offIDCode0;
1407 cbCode = pSwitcher->cbIDCode0;
1408 }
1409 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1410 {
1411 pszDesc = "IDCode1";
1412 uBase = u32IDCode;
1413 offCode = pSwitcher->offIDCode1;
1414 cbCode = pSwitcher->cbIDCode1;
1415 }
1416 else
1417 {
1418 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1419 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1420 offCode++;
1421 continue;
1422 }
1423
1424 /*
1425 * Disassemble it.
1426 */
1427 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1428 DISCPUSTATE Cpu = {0};
1429 Cpu.mode = CPUMODE_32BIT;
1430 while (cbCode > 0)
1431 {
1432 /* try label it */
1433 if (pSwitcher->offR0HostToGuest == offCode)
1434 RTLogPrintf(" *R0HostToGuest:\n");
1435 if (pSwitcher->offGCGuestToHost == offCode)
1436 RTLogPrintf(" *GCGuestToHost:\n");
1437 if (pSwitcher->offGCCallTrampoline == offCode)
1438 RTLogPrintf(" *GCCallTrampoline:\n");
1439 if (pSwitcher->offGCGuestToHostAsm == offCode)
1440 RTLogPrintf(" *GCGuestToHostAsm:\n");
1441 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1442 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1443 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1444 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1445
1446 /* disas */
1447 uint32_t cbInstr = 0;
1448 char szDisas[256];
1449 if (DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas))
1450 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1451 else
1452 {
1453 RTLogPrintf(" %04x: %02x '%c'\n",
1454 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1455 cbInstr = 1;
1456 }
1457 offCode += cbInstr;
1458 cbCode -= RT_MIN(cbInstr, cbCode);
1459 }
1460 }
1461 }
1462#endif
1463}
1464
1465
1466/**
1467 * Relocator for the 32-Bit to 32-Bit world switcher.
1468 */
1469DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1470{
1471 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1472 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1473}
1474
1475
1476/**
1477 * Relocator for the 32-Bit to PAE world switcher.
1478 */
1479DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1480{
1481 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1482 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1483}
1484
1485
1486/**
1487 * Relocator for the PAE to 32-Bit world switcher.
1488 */
1489DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1490{
1491 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1492 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1493}
1494
1495
1496/**
1497 * Relocator for the PAE to PAE world switcher.
1498 */
1499DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1500{
1501 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1502 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1503}
1504
1505
1506/**
1507 * Relocator for the AMD64 to PAE world switcher.
1508 */
1509DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1510{
1511 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1512 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1513}
1514
1515
1516/**
1517 * Gets the pointer to g_szRTAssertMsg1 in GC.
1518 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1519 * Returns NULL if not present.
1520 * @param pVM The VM handle.
1521 */
1522VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1523{
1524 RTGCPTR GCPtr;
1525 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1526 if (VBOX_SUCCESS(rc))
1527 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1528 return NULL;
1529}
1530
1531
1532/**
1533 * Gets the pointer to g_szRTAssertMsg2 in GC.
1534 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1535 * Returns NULL if not present.
1536 * @param pVM The VM handle.
1537 */
1538VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1539{
1540 RTGCPTR GCPtr;
1541 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1542 if (VBOX_SUCCESS(rc))
1543 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1544 return NULL;
1545}
1546
1547
1548/**
1549 * Execute state save operation.
1550 *
1551 * @returns VBox status code.
1552 * @param pVM VM Handle.
1553 * @param pSSM SSM operation handle.
1554 */
1555static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1556{
1557 LogFlow(("vmmR3Save:\n"));
1558
1559 /*
1560 * The hypervisor stack.
1561 */
1562 SSMR3PutGCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1563 RTGCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1564 Assert(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE);
1565 SSMR3PutGCPtr(pSSM, GCPtrESP);
1566 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1567 return SSMR3PutU32(pSSM, ~0); /* terminator */
1568}
1569
1570
1571/**
1572 * Execute state load operation.
1573 *
1574 * @returns VBox status code.
1575 * @param pVM VM Handle.
1576 * @param pSSM SSM operation handle.
1577 * @param u32Version Data layout version.
1578 */
1579static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1580{
1581 LogFlow(("vmmR3Load:\n"));
1582
1583 /*
1584 * Validate version.
1585 */
1586 if (u32Version != VMM_SAVED_STATE_VERSION)
1587 {
1588 Log(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1589 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1590 }
1591
1592 /*
1593 * Check that the stack is in the same place, or that it's fearly empty.
1594 */
1595 RTGCPTR GCPtrStackBottom;
1596 SSMR3GetGCPtr(pSSM, &GCPtrStackBottom);
1597 RTGCPTR GCPtrESP;
1598 int rc = SSMR3GetGCPtr(pSSM, &GCPtrESP);
1599 if (VBOX_FAILURE(rc))
1600 return rc;
1601 if ( GCPtrStackBottom == pVM->vmm.s.pbGCStackBottom
1602 || (GCPtrStackBottom - GCPtrESP < 32)) /** @todo This will break if we start preemting the hypervisor. */
1603 {
1604 /*
1605 * We *must* set the ESP because the CPUM load + PGM load relocations will render
1606 * the ESP in CPUM fatally invalid.
1607 */
1608 CPUMSetHyperESP(pVM, GCPtrESP);
1609
1610 /* restore the stack. */
1611 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1612
1613 /* terminator */
1614 uint32_t u32;
1615 rc = SSMR3GetU32(pSSM, &u32);
1616 if (VBOX_FAILURE(rc))
1617 return rc;
1618 if (u32 != ~0U)
1619 {
1620 AssertMsgFailed(("u32=%#x\n", u32));
1621 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1622 }
1623 return VINF_SUCCESS;
1624 }
1625
1626 LogRel(("The stack is not in the same place and it's not empty! GCPtrStackBottom=%VGv pbGCStackBottom=%VGv ESP=%VGv\n",
1627 GCPtrStackBottom, pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1628 AssertFailed();
1629 return VERR_SSM_LOAD_CONFIG_MISMATCH;
1630}
1631
1632
1633/**
1634 * Selects the switcher to be used for switching to GC.
1635 *
1636 * @returns VBox status code.
1637 * @param pVM VM handle.
1638 * @param enmSwitcher The new switcher.
1639 * @remark This function may be called before the VMM is initialized.
1640 */
1641VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1642{
1643 /*
1644 * Validate input.
1645 */
1646 if ( enmSwitcher < VMMSWITCHER_INVALID
1647 || enmSwitcher >= VMMSWITCHER_MAX)
1648 {
1649 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1650 return VERR_INVALID_PARAMETER;
1651 }
1652
1653 /*
1654 * Select the new switcher.
1655 */
1656 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1657 if (pSwitcher)
1658 {
1659 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1660 pVM->vmm.s.enmSwitcher = enmSwitcher;
1661
1662 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1663 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1664
1665 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1666 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1667 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1668 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1669 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1670 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1671 return VINF_SUCCESS;
1672 }
1673 return VERR_NOT_IMPLEMENTED;
1674}
1675
1676/**
1677 * Disable the switcher logic permanently.
1678 *
1679 * @returns VBox status code.
1680 * @param pVM VM handle.
1681 */
1682VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1683{
1684/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1685 * @code
1686 * mov eax, VERR_INTERNAL_ERROR
1687 * ret
1688 * @endcode
1689 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1690 */
1691 pVM->vmm.s.fSwitcherDisabled = true;
1692 return VINF_SUCCESS;
1693}
1694
1695
1696/**
1697 * Resolve a builtin GC symbol.
1698 * Called by PDM when loading or relocating GC modules.
1699 *
1700 * @returns VBox status
1701 * @param pVM VM Handle.
1702 * @param pszSymbol Symbol to resolv
1703 * @param pGCPtrValue Where to store the symbol value.
1704 * @remark This has to work before VMMR3Relocate() is called.
1705 */
1706VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1707{
1708 if (!strcmp(pszSymbol, "g_Logger"))
1709 {
1710 if (pVM->vmm.s.pLoggerHC)
1711 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1712 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1713 }
1714 else if (!strcmp(pszSymbol, "g_RelLogger"))
1715 {
1716#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1717 if (pVM->vmm.s.pRelLoggerHC)
1718 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1719 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1720#else
1721 *pGCPtrValue = NIL_RTGCPTR;
1722#endif
1723 }
1724 else
1725 return VERR_SYMBOL_NOT_FOUND;
1726 return VINF_SUCCESS;
1727}
1728
1729
1730/**
1731 * Suspends the the CPU yielder.
1732 *
1733 * @param pVM The VM handle.
1734 */
1735VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1736{
1737 if (!pVM->vmm.s.cYieldResumeMillies)
1738 {
1739 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1740 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1741 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1742 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1743 else
1744 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1745 TMTimerStop(pVM->vmm.s.pYieldTimer);
1746 }
1747}
1748
1749
1750/**
1751 * Stops the the CPU yielder.
1752 *
1753 * @param pVM The VM handle.
1754 */
1755VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1756{
1757 if (!pVM->vmm.s.cYieldResumeMillies)
1758 TMTimerStop(pVM->vmm.s.pYieldTimer);
1759 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1760}
1761
1762
1763/**
1764 * Resumes the CPU yielder when it has been a suspended or stopped.
1765 *
1766 * @param pVM The VM handle.
1767 */
1768VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1769{
1770 if (pVM->vmm.s.cYieldResumeMillies)
1771 {
1772 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1773 pVM->vmm.s.cYieldResumeMillies = 0;
1774 }
1775}
1776
1777
1778/**
1779 * Internal timer callback function.
1780 *
1781 * @param pVM The VM.
1782 * @param pTimer The timer handle.
1783 * @param pvUser User argument specified upon timer creation.
1784 */
1785static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1786{
1787#ifdef LOG_ENABLED
1788 uint64_t u64Elapsed = RTTimeNanoTS();
1789#endif
1790 RTThreadYield();
1791 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1792 Log(("vmmR3YieldEMT: %RI64 ns\n", RTTimeNanoTS() - u64Elapsed));
1793}
1794
1795
1796/**
1797 * Acquire global VM lock.
1798 *
1799 * @returns VBox status code
1800 * @param pVM The VM to operate on.
1801 */
1802VMMR3DECL(int) VMMR3Lock(PVM pVM)
1803{
1804 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1805}
1806
1807
1808/**
1809 * Release global VM lock.
1810 *
1811 * @returns VBox status code
1812 * @param pVM The VM to operate on.
1813 */
1814VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1815{
1816 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1817}
1818
1819
1820/**
1821 * Return global VM lock owner.
1822 *
1823 * @returns Thread id of owner.
1824 * @returns NIL_RTTHREAD if no owner.
1825 * @param pVM The VM to operate on.
1826 */
1827VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1828{
1829 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1830}
1831
1832
1833/**
1834 * Checks if the current thread is the owner of the global VM lock.
1835 *
1836 * @returns true if owner.
1837 * @returns false if not owner.
1838 * @param pVM The VM to operate on.
1839 */
1840VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1841{
1842 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1843}
1844
1845
1846/**
1847 * Executes guest code.
1848 *
1849 * @param pVM VM handle.
1850 */
1851VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1852{
1853 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1854
1855 /*
1856 * Set the EIP and ESP.
1857 */
1858 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1859 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1860 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1861 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1862
1863 /*
1864 * We hide log flushes (outer) and hypervisor interrupts (inner).
1865 */
1866 for (;;)
1867 {
1868 int rc;
1869 do
1870 {
1871#ifdef NO_SUPCALLR0VMM
1872 rc = VERR_GENERAL_FAILURE;
1873#else
1874 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
1875#endif
1876 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1877
1878 /*
1879 * Flush the logs.
1880 */
1881#ifdef LOG_ENABLED
1882 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1883 if ( pLogger
1884 && pLogger->offScratch > 0)
1885 RTLogFlushGC(NULL, pLogger);
1886#endif
1887#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1888 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1889 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1890 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1891#endif
1892 if (rc != VINF_VMM_CALL_HOST)
1893 {
1894 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1895 return rc;
1896 }
1897 rc = vmmR3ServiceCallHostRequest(pVM);
1898 if (VBOX_FAILURE(rc))
1899 return rc;
1900 /* Resume GC */
1901 }
1902}
1903
1904
1905/**
1906 * Executes guest code (Intel VMX and AMD SVM).
1907 *
1908 * @param pVM VM handle.
1909 */
1910VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1911{
1912 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1913
1914 for (;;)
1915 {
1916 int rc;
1917 do
1918 {
1919#ifdef NO_SUPCALLR0VMM
1920 rc = VERR_GENERAL_FAILURE;
1921#else
1922 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_RUN, NULL);
1923#endif
1924 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1925
1926#ifdef LOG_ENABLED
1927 /*
1928 * Flush the log
1929 */
1930 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
1931 if ( pR0Logger
1932 && pR0Logger->Logger.offScratch > 0)
1933 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
1934#endif /* !LOG_ENABLED */
1935 if (rc != VINF_VMM_CALL_HOST)
1936 {
1937 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1938 return rc;
1939 }
1940 rc = vmmR3ServiceCallHostRequest(pVM);
1941 if (VBOX_FAILURE(rc))
1942 return rc;
1943 /* Resume R0 */
1944 }
1945}
1946
1947/**
1948 * Calls GC a function.
1949 *
1950 * @param pVM The VM handle.
1951 * @param GCPtrEntry The GC function address.
1952 * @param cArgs The number of arguments in the ....
1953 * @param ... Arguments to the function.
1954 */
1955VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, ...)
1956{
1957 va_list args;
1958 va_start(args, cArgs);
1959 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
1960 va_end(args);
1961 return rc;
1962}
1963
1964
1965/**
1966 * Calls GC a function.
1967 *
1968 * @param pVM The VM handle.
1969 * @param GCPtrEntry The GC function address.
1970 * @param cArgs The number of arguments in the ....
1971 * @param args Arguments to the function.
1972 */
1973VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, va_list args)
1974{
1975 Log2(("VMMR3CallGCV: GCPtrEntry=%VGv cArgs=%d\n", GCPtrEntry, cArgs));
1976
1977 /*
1978 * Setup the call frame using the trampoline.
1979 */
1980 CPUMHyperSetCtxCore(pVM, NULL);
1981 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
1982 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR));
1983 PRTGCUINTPTR pFrame = (PRTGCUINTPTR)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
1984 int i = cArgs;
1985 while (i-- > 0)
1986 *pFrame++ = va_arg(args, RTGCUINTPTR);
1987
1988 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR)); /* stack frame size */
1989 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
1990 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
1991
1992 /*
1993 * We hide log flushes (outer) and hypervisor interrupts (inner).
1994 */
1995 for (;;)
1996 {
1997 int rc;
1998 do
1999 {
2000#ifdef NO_SUPCALLR0VMM
2001 rc = VERR_GENERAL_FAILURE;
2002#else
2003 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2004#endif
2005 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2006
2007 /*
2008 * Flush the logs.
2009 */
2010#ifdef LOG_ENABLED
2011 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2012 if ( pLogger
2013 && pLogger->offScratch > 0)
2014 RTLogFlushGC(NULL, pLogger);
2015#endif
2016#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2017 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2018 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2019 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2020#endif
2021 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2022 VMMR3FatalDump(pVM, rc);
2023 if (rc != VINF_VMM_CALL_HOST)
2024 {
2025 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2026 return rc;
2027 }
2028 rc = vmmR3ServiceCallHostRequest(pVM);
2029 if (VBOX_FAILURE(rc))
2030 return rc;
2031 }
2032}
2033
2034
2035/**
2036 * Resumes executing hypervisor code when interrupted
2037 * by a queue flush or a debug event.
2038 *
2039 * @returns VBox status code.
2040 * @param pVM VM handle.
2041 */
2042VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2043{
2044 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2045
2046 /*
2047 * We hide log flushes (outer) and hypervisor interrupts (inner).
2048 */
2049 for (;;)
2050 {
2051 int rc;
2052 do
2053 {
2054#ifdef NO_SUPCALLR0VMM
2055 rc = VERR_GENERAL_FAILURE;
2056#else
2057 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2058#endif
2059 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2060
2061 /*
2062 * Flush the loggers,
2063 */
2064#ifdef LOG_ENABLED
2065 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2066 if ( pLogger
2067 && pLogger->offScratch > 0)
2068 RTLogFlushGC(NULL, pLogger);
2069#endif
2070#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2071 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2072 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2073 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2074#endif
2075 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2076 VMMR3FatalDump(pVM, rc);
2077 if (rc != VINF_VMM_CALL_HOST)
2078 {
2079 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2080 return rc;
2081 }
2082 rc = vmmR3ServiceCallHostRequest(pVM);
2083 if (VBOX_FAILURE(rc))
2084 return rc;
2085 }
2086}
2087
2088
2089/**
2090 * Service a call to the ring-3 host code.
2091 *
2092 * @returns VBox status code.
2093 * @param pVM VM handle.
2094 * @remark Careful with critsects.
2095 */
2096static int vmmR3ServiceCallHostRequest(PVM pVM)
2097{
2098 switch (pVM->vmm.s.enmCallHostOperation)
2099 {
2100 /*
2101 * Acquire the PDM lock.
2102 */
2103 case VMMCALLHOST_PDM_LOCK:
2104 {
2105 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2106 break;
2107 }
2108
2109 /*
2110 * Flush a PDM queue.
2111 */
2112 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2113 {
2114 PDMR3QueueFlushWorker(pVM, NULL);
2115 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2116 break;
2117 }
2118
2119 /*
2120 * Grow the PGM pool.
2121 */
2122 case VMMCALLHOST_PGM_POOL_GROW:
2123 {
2124 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2125 break;
2126 }
2127
2128 /*
2129 * Acquire the PGM lock.
2130 */
2131 case VMMCALLHOST_PGM_LOCK:
2132 {
2133 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2134 break;
2135 }
2136
2137 /*
2138 * Flush REM handler notifications.
2139 */
2140 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2141 {
2142 REMR3ReplayHandlerNotifications(pVM);
2143 break;
2144 }
2145
2146 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2147 {
2148 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, pVM->vmm.s.u64CallHostArg);
2149 break;
2150 }
2151
2152 /*
2153 * This is a noop. We just take this route to avoid unnecessary
2154 * tests in the loops.
2155 */
2156 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2157 break;
2158
2159 /*
2160 * Set the VM error message.
2161 */
2162 case VMMCALLHOST_VM_SET_ERROR:
2163 VMR3SetErrorWorker(pVM);
2164 break;
2165
2166 /*
2167 * Set the VM runtime error message.
2168 */
2169 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2170 VMR3SetRuntimeErrorWorker(pVM);
2171 break;
2172
2173 default:
2174 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2175 return VERR_INTERNAL_ERROR;
2176 }
2177
2178 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2179 return VINF_SUCCESS;
2180}
2181
2182
2183
2184/**
2185 * Structure to pass to DBGFR3Info() and for doing all other
2186 * output during fatal dump.
2187 */
2188typedef struct VMMR3FATALDUMPINFOHLP
2189{
2190 /** The helper core. */
2191 DBGFINFOHLP Core;
2192 /** The release logger instance. */
2193 PRTLOGGER pRelLogger;
2194 /** The saved release logger flags. */
2195 RTUINT fRelLoggerFlags;
2196 /** The logger instance. */
2197 PRTLOGGER pLogger;
2198 /** The saved logger flags. */
2199 RTUINT fLoggerFlags;
2200 /** The saved logger destination flags. */
2201 RTUINT fLoggerDestFlags;
2202 /** Whether to output to stderr or not. */
2203 bool fStdErr;
2204} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2205typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2206
2207
2208/**
2209 * Print formatted string.
2210 *
2211 * @param pHlp Pointer to this structure.
2212 * @param pszFormat The format string.
2213 * @param ... Arguments.
2214 */
2215static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2216{
2217 va_list args;
2218 va_start(args, pszFormat);
2219 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2220 va_end(args);
2221}
2222
2223
2224/**
2225 * Print formatted string.
2226 *
2227 * @param pHlp Pointer to this structure.
2228 * @param pszFormat The format string.
2229 * @param args Argument list.
2230 */
2231static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2232{
2233 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2234
2235 if (pMyHlp->pRelLogger)
2236 {
2237 va_list args2;
2238 va_copy(args2, args);
2239 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2240 va_end(args2);
2241 }
2242 if (pMyHlp->pLogger)
2243 {
2244 va_list args2;
2245 va_copy(args2, args);
2246 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2247 va_end(args2);
2248 }
2249 if (pMyHlp->fStdErr)
2250 {
2251 va_list args2;
2252 va_copy(args2, args);
2253 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2254 va_end(args2);
2255 }
2256}
2257
2258
2259/**
2260 * Initializes the fatal dump output helper.
2261 *
2262 * @param pHlp The structure to initialize.
2263 */
2264static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2265{
2266 memset(pHlp, 0, sizeof(*pHlp));
2267
2268 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2269 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2270
2271 /*
2272 * The loggers.
2273 */
2274 pHlp->pRelLogger = RTLogRelDefaultInstance();
2275#ifndef LOG_ENABLED
2276 if (!pHlp->pRelLogger)
2277#endif
2278 pHlp->pLogger = RTLogDefaultInstance();
2279
2280 if (pHlp->pRelLogger)
2281 {
2282 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2283 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2284 }
2285
2286 if (pHlp->pLogger)
2287 {
2288 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2289 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2290 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2291 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2292 }
2293
2294 /*
2295 * Check if we need write to stderr.
2296 */
2297 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2298 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2299}
2300
2301
2302/**
2303 * Deletes the fatal dump output helper.
2304 *
2305 * @param pHlp The structure to delete.
2306 */
2307static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2308{
2309 if (pHlp->pRelLogger)
2310 {
2311 RTLogFlush(pHlp->pRelLogger);
2312 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2313 }
2314
2315 if (pHlp->pLogger)
2316 {
2317 RTLogFlush(pHlp->pLogger);
2318 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2319 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2320 }
2321}
2322
2323
2324/**
2325 * Dumps the VM state on a fatal error.
2326 *
2327 * @param pVM VM Handle.
2328 * @param rcErr VBox status code.
2329 */
2330VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2331{
2332 /*
2333 * Create our output helper and sync it with the log settings.
2334 * This helper will be used for all the output.
2335 */
2336 VMMR3FATALDUMPINFOHLP Hlp;
2337 PCDBGFINFOHLP pHlp = &Hlp.Core;
2338 vmmR3FatalDumpInfoHlpInit(&Hlp);
2339
2340 /*
2341 * Header.
2342 */
2343 pHlp->pfnPrintf(pHlp,
2344 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2345 "!!\n"
2346 "!! Guru Meditation %d (%Vrc)\n"
2347 "!!\n",
2348 rcErr, rcErr);
2349
2350 /*
2351 * Continue according to context.
2352 */
2353 bool fDoneHyper = false;
2354 switch (rcErr)
2355 {
2356 /*
2357 * Hyper visor errors.
2358 */
2359 case VINF_EM_DBG_HYPER_ASSERTION:
2360 pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2361 /* fall thru */
2362 case VERR_TRPM_DONT_PANIC:
2363 case VERR_TRPM_PANIC:
2364 case VINF_EM_RAW_STALE_SELECTOR:
2365 case VINF_EM_RAW_IRET_TRAP:
2366 case VINF_EM_DBG_HYPER_BREAKPOINT:
2367 case VINF_EM_DBG_HYPER_STEPPED:
2368 {
2369 /* Trap? */
2370 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2371 bool fSoftwareInterrupt = false;
2372 uint8_t u8TrapNo = 0xce;
2373 RTGCUINT uErrorCode = 0xdeadface;
2374 RTGCUINTPTR uCR2 = 0xdeadface;
2375 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
2376 if (VBOX_SUCCESS(rc2))
2377 pHlp->pfnPrintf(pHlp,
2378 "!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv fSoft=%d\n",
2379 u8TrapNo, uErrorCode, uCR2, uEIP, fSoftwareInterrupt);
2380 else
2381 pHlp->pfnPrintf(pHlp,
2382 "!! EIP=%VGv NOTRAP\n",
2383 uEIP);
2384
2385 /*
2386 * Try figure out where eip is.
2387 */
2388 /** @todo make query call for core code or move this function to VMM. */
2389 /* core code? */
2390 //if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2391 // pHlp->pfnPrintf(pHlp,
2392 // "!! EIP is in CoreCode, offset %#x\n",
2393 // uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2394 //else
2395 { /* ask PDM */
2396 /** @todo ask DBGFR3Sym later. */
2397 char szModName[64];
2398 RTGCPTR GCPtrMod;
2399 char szNearSym1[260];
2400 RTGCPTR GCPtrNearSym1;
2401 char szNearSym2[260];
2402 RTGCPTR GCPtrNearSym2;
2403 int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2404 &szModName[0], sizeof(szModName), &GCPtrMod,
2405 &szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2406 &szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2407 if (VBOX_SUCCESS(rc))
2408 {
2409 pHlp->pfnPrintf(pHlp,
2410 "!! EIP in %s (%p) at rva %x near symbols:\n"
2411 "!! %VGv rva %VGv off %08x %s\n"
2412 "!! %VGv rva %VGv off -%08x %s\n",
2413 szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2414 GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2415 GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2416 }
2417 else
2418 pHlp->pfnPrintf(pHlp,
2419 "!! EIP is not in any code known to VMM!\n");
2420 }
2421
2422 /* Disassemble the instruction. */
2423 char szInstr[256];
2424 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2425 if (VBOX_SUCCESS(rc2))
2426 pHlp->pfnPrintf(pHlp,
2427 "!! %s\n", szInstr);
2428
2429 /* Dump the hypervisor cpu state. */
2430 pHlp->pfnPrintf(pHlp,
2431 "!!\n"
2432 "!!\n"
2433 "!!\n");
2434 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2435 fDoneHyper = true;
2436
2437 /* Callstack. */
2438 DBGFSTACKFRAME Frame = {0};
2439 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2440 if (VBOX_SUCCESS(rc2))
2441 {
2442 pHlp->pfnPrintf(pHlp,
2443 "!!\n"
2444 "!! Call Stack:\n"
2445 "!!\n"
2446 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2447 do
2448 {
2449 pHlp->pfnPrintf(pHlp,
2450 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2451 (uint32_t)Frame.AddrFrame.off,
2452 (uint32_t)Frame.AddrReturnFrame.off,
2453 (uint32_t)Frame.AddrReturnPC.Sel,
2454 (uint32_t)Frame.AddrReturnPC.off,
2455 Frame.Args.au32[0],
2456 Frame.Args.au32[1],
2457 Frame.Args.au32[2],
2458 Frame.Args.au32[3]);
2459 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2460 if (Frame.pSymPC)
2461 {
2462 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2463 if (offDisp > 0)
2464 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2465 else if (offDisp < 0)
2466 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2467 else
2468 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2469 }
2470 if (Frame.pLinePC)
2471 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2472 pHlp->pfnPrintf(pHlp, "\n");
2473
2474 /* next */
2475 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2476 } while (VBOX_SUCCESS(rc2));
2477 DBGFR3StackWalkEnd(pVM, &Frame);
2478 }
2479
2480 /* raw stack */
2481 pHlp->pfnPrintf(pHlp,
2482 "!!\n"
2483 "!! Raw stack (mind the direction).\n"
2484 "!!\n"
2485 "%.*Vhxd\n",
2486 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2487 break;
2488 }
2489
2490 default:
2491 {
2492 break;
2493 }
2494
2495 } /* switch (rcErr) */
2496
2497
2498 /*
2499 * Dump useful state information.
2500 */
2501 /** @todo convert these dumpers to DBGFR3Info() handlers!!! */
2502 pHlp->pfnPrintf(pHlp,
2503 "!!\n"
2504 "!! PGM Access Handlers & Stuff:\n"
2505 "!!\n");
2506 PGMR3DumpMappings(pVM);
2507
2508
2509 /*
2510 * Generic info dumper loop.
2511 */
2512 static struct
2513 {
2514 const char *pszInfo;
2515 const char *pszArgs;
2516 } const aInfo[] =
2517 {
2518 { "hma", NULL },
2519 { "cpumguest", "verbose" },
2520 { "cpumhyper", "verbose" },
2521 { "cpumhost", "verbose" },
2522 { "mode", "all" },
2523 { "cpuid", "verbose" },
2524 { "gdt", NULL },
2525 { "ldt", NULL },
2526 //{ "tss", NULL },
2527 { "ioport", NULL },
2528 { "mmio", NULL },
2529 { "phys", NULL },
2530 //{ "pgmpd", NULL }, - doesn't always work at init time...
2531 { "timers", NULL },
2532 { "activetimers", NULL },
2533 { "handlers", "phys virt stats" },
2534 { "cfgm", NULL },
2535 };
2536 for (unsigned i = 0; i < ELEMENTS(aInfo); i++)
2537 {
2538 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2539 continue;
2540 pHlp->pfnPrintf(pHlp,
2541 "!!\n"
2542 "!! {%s, %s}\n"
2543 "!!\n",
2544 aInfo[i].pszInfo, aInfo[i].pszArgs);
2545 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2546 }
2547
2548 /* done */
2549 pHlp->pfnPrintf(pHlp,
2550 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2551
2552
2553 /*
2554 * Delete the output instance (flushing and restoring of flags).
2555 */
2556 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2557}
2558
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