VMM.cpp@ 13717

Last change on this file since 13717 was 13717, checked in by vboxsync, 16 years ago
VMM,IPRT: More GC->RC and similar cleanups.
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1	/* $Id: VMM.cpp 13717 2008-10-31 14:31:23Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor Core.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	//#define NO_SUPCALLR0VMM
23
24	/** @page pg_vmm VMM - The Virtual Machine Monitor
25	*
26	* The VMM component is two things at the moment, it's a component doing a few
27	* management and routing tasks, and it's the whole virtual machine monitor
28	* thing. For hysterical reasons, it is not doing all the management that one
29	* would expect, this is instead done by @ref pg_vm. We'll address this
30	* misdesign eventually.
31	*
32	* @see grp_vmm, grp_vm
33	*
34	*
35	* @section sec_vmmstate VMM State
36	*
37	* @image html VM_Statechart_Diagram.gif
38	*
39	* To be written.
40	*
41	*
42	* @subsection subsec_vmm_init VMM Initialization
43	*
44	* To be written.
45	*
46	*
47	* @subsection subsec_vmm_term VMM Termination
48	*
49	* To be written.
50	*
51	*/
52
53	/*******************************************************************************
54	* Header Files *
55	*******************************************************************************/
56	#define LOG_GROUP LOG_GROUP_VMM
57	#include <VBox/vmm.h>
58	#include <VBox/vmapi.h>
59	#include <VBox/pgm.h>
60	#include <VBox/cfgm.h>
61	#include <VBox/pdmqueue.h>
62	#include <VBox/pdmapi.h>
63	#include <VBox/cpum.h>
64	#include <VBox/mm.h>
65	#include <VBox/iom.h>
66	#include <VBox/trpm.h>
67	#include <VBox/selm.h>
68	#include <VBox/em.h>
69	#include <VBox/sup.h>
70	#include <VBox/dbgf.h>
71	#include <VBox/csam.h>
72	#include <VBox/patm.h>
73	#include <VBox/rem.h>
74	#include <VBox/ssm.h>
75	#include <VBox/tm.h>
76	#include "VMMInternal.h"
77	#include "VMMSwitcher/VMMSwitcher.h"
78	#include <VBox/vm.h>
79
80	#include <VBox/err.h>
81	#include <VBox/param.h>
82	#include <VBox/version.h>
83	#include <VBox/x86.h>
84	#include <VBox/hwaccm.h>
85	#include <iprt/assert.h>
86	#include <iprt/alloc.h>
87	#include <iprt/asm.h>
88	#include <iprt/time.h>
89	#include <iprt/stream.h>
90	#include <iprt/string.h>
91	#include <iprt/stdarg.h>
92	#include <iprt/ctype.h>
93
94
95
96	/** The saved state version. */
97	#define VMM_SAVED_STATE_VERSION 3
98
99
100	/*******************************************************************************
101	* Global Variables *
102	*******************************************************************************/
103	/** Array of switcher defininitions.
104	* The type and index shall match!
105	*/
106	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
107	{
108	NULL, /* invalid entry */
109	#ifndef RT_ARCH_AMD64
110	&vmmR3Switcher32BitTo32Bit_Def,
111	&vmmR3Switcher32BitToPAE_Def,
112	NULL, //&vmmR3Switcher32BitToAMD64_Def,
113	&vmmR3SwitcherPAETo32Bit_Def,
114	&vmmR3SwitcherPAEToPAE_Def,
115	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
116	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
117	&vmmR3SwitcherAMD64ToPAE_Def,
118	# else
119	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
120	# endif
121	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
122	#else /* RT_ARCH_AMD64 */
123	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
124	NULL, //&vmmR3Switcher32BitToPAE_Def,
125	NULL, //&vmmR3Switcher32BitToAMD64_Def,
126	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
127	NULL, //&vmmR3SwitcherPAEToPAE_Def,
128	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
129	&vmmR3SwitcherAMD64ToPAE_Def,
130	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
131	#endif /* RT_ARCH_AMD64 */
132	};
133
134
135	/*******************************************************************************
136	* Internal Functions *
137	*******************************************************************************/
138	static int vmmR3InitCoreCode(PVM pVM);
139	static int vmmR3InitStacks(PVM pVM);
140	static int vmmR3InitLoggers(PVM pVM);
141	static void vmmR3InitRegisterStats(PVM pVM);
142	static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
143	static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
144	static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
145	static int vmmR3ServiceCallHostRequest(PVM pVM);
146	static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
147
148
149	/**
150	* Initializes the VMM.
151	*
152	* @returns VBox status code.
153	* @param pVM The VM to operate on.
154	*/
155	VMMR3DECL(int) VMMR3Init(PVM pVM)
156	{
157	LogFlow(("VMMR3Init\n"));
158
159	/*
160	* Assert alignment, sizes and order.
161	*/
162	AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
163	AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
164	("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
165	sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
166
167	/*
168	* Init basic VM VMM members.
169	*/
170	pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
171	int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
172	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
173	pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
174	//pVM->vmm.s.cYieldEveryMillies = 8; //debugging
175	else
176	AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
177
178	/* GC switchers are enabled by default. Turned off by HWACCM. */
179	pVM->vmm.s.fSwitcherDisabled = false;
180
181	/* Get the CPU count.*/
182	rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "NumCPUs", &pVM->cCPUs, 1);
183	AssertLogRelMsgRCReturn(rc, ("Configuration error: Querying \"NumCPUs\" as integer failed, rc=%Vrc\n", rc), rc);
184	#ifdef VBOX_WITH_SMP_GUESTS
185	AssertLogRelMsgReturn(pVM->cCPUs > 0 && pVM->cCPUs <= 256,
186	("Configuration error: \"NumCPUs\"=%RU32 is out of range [1..256]\n", pVM->cCPUs), VERR_INVALID_PARAMETER);
187	#else
188	AssertLogRelMsgReturn(pVM->cCPUs != 0,
189	("Configuration error: \"NumCPUs\"=%RU32, expected 1\n", pVM->cCPUs), VERR_INVALID_PARAMETER);
190	#endif
191
192	#ifdef VBOX_WITH_SMP_GUESTS
193	LogRel(("[SMP] VMM with %RU32 CPUs\n", pVM->cCPUs));
194	#endif
195
196	/*
197	* Register the saved state data unit.
198	*/
199	rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
200	NULL, vmmR3Save, NULL,
201	NULL, vmmR3Load, NULL);
202	if (VBOX_FAILURE(rc))
203	return rc;
204
205	/*
206	* Register the Ring-0 VM handle with the session for fast ioctl calls.
207	*/
208	rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
209	if (VBOX_FAILURE(rc))
210	return rc;
211
212	/*
213	* Init various sub-components.
214	*/
215	rc = vmmR3InitCoreCode(pVM);
216	if (RT_SUCCESS(rc))
217	{
218	rc = vmmR3InitStacks(pVM);
219	if (RT_SUCCESS(rc))
220	{
221	rc = vmmR3InitLoggers(pVM);
222
223	#ifdef VBOX_WITH_NMI
224	/*
225	* Allocate mapping for the host APIC.
226	*/
227	if (RT_SUCCESS(rc))
228	{
229	rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
230	AssertRC(rc);
231	}
232	#endif
233	if (RT_SUCCESS(rc))
234	{
235	rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
236	if (VBOX_SUCCESS(rc))
237	{
238	/*
239	* Debug info and statistics.
240	*/
241	DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
242	vmmR3InitRegisterStats(pVM);
243
244	return VINF_SUCCESS;
245	}
246	}
247	}
248	/** @todo: Need failure cleanup. */
249
250	//more todo in here?
251	//if (VBOX_SUCCESS(rc))
252	//{
253	//}
254	//int rc2 = vmmR3TermCoreCode(pVM);
255	//AssertRC(rc2));
256	}
257
258	return rc;
259	}
260
261
262	/**
263	* VMMR3Init worker that initiates the core code.
264	*
265	* This is core per VM code which might need fixups and/or for ease of use are
266	* put on linear contiguous backing.
267	*
268	* @returns VBox status code.
269	* @param pVM Pointer to the shared VM structure.
270	*/
271	static int vmmR3InitCoreCode(PVM pVM)
272	{
273	/*
274	* Calc the size.
275	*/
276	unsigned cbCoreCode = 0;
277	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
278	{
279	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
280	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
281	if (pSwitcher)
282	{
283	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
284	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
285	}
286	}
287
288	/*
289	* Allocate continguous pages for switchers and deal with
290	* conflicts in the intermediate mapping of the code.
291	*/
292	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
293	pVM->vmm.s.pvCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
294	int rc = VERR_NO_MEMORY;
295	if (pVM->vmm.s.pvCoreCodeR3)
296	{
297	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
298	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
299	{
300	/* try more allocations - Solaris, Linux. */
301	const unsigned cTries = 8234;
302	struct VMMInitBadTry
303	{
304	RTR0PTR pvR0;
305	void *pvR3;
306	RTHCPHYS HCPhys;
307	RTUINT cb;
308	} paBadTries = (struct VMMInitBadTry )RTMemTmpAlloc(sizeof(paBadTries) cTries);
309	AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
310	unsigned i = 0;
311	do
312	{
313	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
314	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
315	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
316	i++;
317	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
318	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
319	pVM->vmm.s.pvCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
320	if (!pVM->vmm.s.pvCoreCodeR3)
321	break;
322	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
323	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
324	&& i < cTries - 1);
325
326	/* cleanup */
327	if (VBOX_FAILURE(rc))
328	{
329	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
330	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
331	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
332	paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
333	i++;
334	LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
335	}
336	while (i-- > 0)
337	{
338	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
339	i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
340	SUPContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
341	}
342	RTMemTmpFree(paBadTries);
343	}
344	}
345	if (VBOX_SUCCESS(rc))
346	{
347	/*
348	* copy the code.
349	*/
350	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
351	{
352	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
353	if (pSwitcher)
354	memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
355	pSwitcher->pvCode, pSwitcher->cbCode);
356	}
357
358	/*
359	* Map the code into the GC address space.
360	*/
361	RTGCPTR GCPtr;
362	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &GCPtr);
363	if (VBOX_SUCCESS(rc))
364	{
365	pVM->vmm.s.pvCoreCodeRC = GCPtr;
366	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
367	LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VRv Phys=%VHp cb=%#x\n",
368	pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
369
370	/*
371	* Finally, PGM probably have selected a switcher already but we need
372	* to get the routine addresses, so we'll reselect it.
373	* This may legally fail so, we're ignoring the rc.
374	*/
375	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
376	return rc;
377	}
378
379	/* shit */
380	AssertMsgFailed(("PGMR3Map(,%VRv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
381	SUPContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
382	}
383	else
384	VMSetError(pVM, rc, RT_SRC_POS,
385	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
386	cbCoreCode);
387
388	pVM->vmm.s.pvCoreCodeR3 = NULL;
389	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
390	pVM->vmm.s.pvCoreCodeRC = 0;
391	return rc;
392	}
393
394
395	/**
396	* Allocate & setup the VMM RC stack(s) (for EMTs).
397	*
398	* The stacks are also used for long jumps in Ring-0.
399	*
400	* @returns VBox status code.
401	* @param pVM Pointer to the shared VM structure.
402	*
403	* @remarks The optional guard page gets it protection setup up during R3 init
404	* completion because of init order issues.
405	*/
406	static int vmmR3InitStacks(PVM pVM)
407	{
408	/** @todo SMP: On stack per vCPU. */
409	#ifdef VBOX_STRICT_VMM_STACK
410	int rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbEMTStackR3);
411	#else
412	int rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbEMTStackR3);
413	#endif
414	if (VBOX_SUCCESS(rc))
415	{
416	pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = MMHyperR3ToR0(pVM, pVM->vmm.s.pbEMTStackR3);
417	pVM->vmm.s.pbEMTStackRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3);
418	pVM->vmm.s.pbEMTStackBottomRC = pVM->vmm.s.pbEMTStackRC + VMM_STACK_SIZE;
419	AssertRelease(pVM->vmm.s.pbEMTStackRC);
420
421	CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC);
422	}
423
424	return rc;
425	}
426
427
428	/**
429	* Initialize the loggers.
430	*
431	* @returns VBox status code.
432	* @param pVM Pointer to the shared VM structure.
433	*/
434	static int vmmR3InitLoggers(PVM pVM)
435	{
436	int rc;
437
438	/*
439	* Allocate RC & R0 Logger instances (they are finalized in the relocator).
440	*/
441	#ifdef LOG_ENABLED
442	PRTLOGGER pLogger = RTLogDefaultInstance();
443	if (pLogger)
444	{
445	pVM->vmm.s.cbRCLogger = RT_OFFSETOF(RTLOGGERRC, afGroups[pLogger->cGroups]);
446	rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRCLogger, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRCLoggerR3);
447	if (RT_FAILURE(rc))
448	return rc;
449	pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
450
451	# ifdef VBOX_WITH_R0_LOGGING
452	rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
453	0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0LoggerR3);
454	if (RT_FAILURE(rc))
455	return rc;
456	pVM->vmm.s.pR0LoggerR3->pVM = pVM->pVMR0;
457	//pVM->vmm.s.pR0LoggerR3->fCreated = false;
458	pVM->vmm.s.pR0LoggerR3->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
459	pVM->vmm.s.pR0LoggerR0 = MMHyperR3ToR0(pVM, pVM->vmm.s.pR0LoggerR3);
460	# endif
461	}
462	#endif /* LOG_ENABLED */
463
464	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
465	/*
466	* Allocate RC release logger instances (finalized in the relocator).
467	*/
468	PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
469	if (pRelLogger)
470	{
471	pVM->vmm.s.cbRCRelLogger = RT_OFFSETOF(RTLOGGERRC, afGroups[pRelLogger->cGroups]);
472	rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRCRelLogger, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRCRelLoggerR3);
473	if (RT_FAILURE(rc))
474	return rc;
475	pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
476	}
477	#endif /* VBOX_WITH_RC_RELEASE_LOGGING */
478	return VINF_SUCCESS;
479	}
480
481
482	/**
483	* VMMR3Init worker that register the statistics with STAM.
484	*
485	* @param pVM The shared VM structure.
486	*/
487	static void vmmR3InitRegisterStats(PVM pVM)
488	{
489	/*
490	* Statistics.
491	*/
492	STAM_REG(pVM, &pVM->vmm.s.StatRunRC, STAMTYPE_COUNTER, "/VMM/RunRC", STAMUNIT_OCCURENCES, "Number of context switches.");
493	STAM_REG(pVM, &pVM->vmm.s.StatRZRetNormal, STAMTYPE_COUNTER, "/VMM/RZRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
494	STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterrupt, STAMTYPE_COUNTER, "/VMM/RZRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
495	STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/RZRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
496	STAM_REG(pVM, &pVM->vmm.s.StatRZRetGuestTrap, STAMTYPE_COUNTER, "/VMM/RZRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
497	STAM_REG(pVM, &pVM->vmm.s.StatRZRetRingSwitch, STAMTYPE_COUNTER, "/VMM/RZRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
498	STAM_REG(pVM, &pVM->vmm.s.StatRZRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/RZRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
499	STAM_REG(pVM, &pVM->vmm.s.StatRZRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/RZRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
500	STAM_REG(pVM, &pVM->vmm.s.StatRZRetStaleSelector, STAMTYPE_COUNTER, "/VMM/RZRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
501	STAM_REG(pVM, &pVM->vmm.s.StatRZRetIRETTrap, STAMTYPE_COUNTER, "/VMM/RZRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
502	STAM_REG(pVM, &pVM->vmm.s.StatRZRetEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
503	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/RZRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
504	STAM_REG(pVM, &pVM->vmm.s.StatRZRetIORead, STAMTYPE_COUNTER, "/VMM/RZRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
505	STAM_REG(pVM, &pVM->vmm.s.StatRZRetIOWrite, STAMTYPE_COUNTER, "/VMM/RZRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
506	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIORead, STAMTYPE_COUNTER, "/VMM/RZRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
507	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
508	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
509	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
510	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
511	STAM_REG(pVM, &pVM->vmm.s.StatRZRetLDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
512	STAM_REG(pVM, &pVM->vmm.s.StatRZRetGDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
513	STAM_REG(pVM, &pVM->vmm.s.StatRZRetIDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
514	STAM_REG(pVM, &pVM->vmm.s.StatRZRetTSSFault, STAMTYPE_COUNTER, "/VMM/RZRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
515	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPDFault, STAMTYPE_COUNTER, "/VMM/RZRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
516	STAM_REG(pVM, &pVM->vmm.s.StatRZRetCSAMTask, STAMTYPE_COUNTER, "/VMM/RZRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
517	STAM_REG(pVM, &pVM->vmm.s.StatRZRetSyncCR3, STAMTYPE_COUNTER, "/VMM/RZRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
518	STAM_REG(pVM, &pVM->vmm.s.StatRZRetMisc, STAMTYPE_COUNTER, "/VMM/RZRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
519	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchInt3, STAMTYPE_COUNTER, "/VMM/RZRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
520	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchPF, STAMTYPE_COUNTER, "/VMM/RZRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
521	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchGP, STAMTYPE_COUNTER, "/VMM/RZRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
522	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/RZRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
523	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPageOverflow, STAMTYPE_COUNTER, "/VMM/RZRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
524	STAM_REG(pVM, &pVM->vmm.s.StatRZRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/RZRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
525	STAM_REG(pVM, &pVM->vmm.s.StatRZRetToR3, STAMTYPE_COUNTER, "/VMM/RZRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
526	STAM_REG(pVM, &pVM->vmm.s.StatRZRetTimerPending, STAMTYPE_COUNTER, "/VMM/RZRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
527	STAM_REG(pVM, &pVM->vmm.s.StatRZRetInterruptPending, STAMTYPE_COUNTER, "/VMM/RZRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
528	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/RZRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
529	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/RZRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
530	STAM_REG(pVM, &pVM->vmm.s.StatRZRetEmulHlt, STAMTYPE_COUNTER, "/VMM/RZRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
531	STAM_REG(pVM, &pVM->vmm.s.StatRZRetPendingRequest, STAMTYPE_COUNTER, "/VMM/RZRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
532
533	STAM_REG(pVM, &pVM->vmm.s.StatRZRetCallHost, STAMTYPE_COUNTER, "/VMM/RZCallR3/Misc", STAMUNIT_OCCURENCES, "Number of Other ring-3 calls.");
534	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPDMLock, STAMTYPE_COUNTER, "/VMM/RZCallR3/PDMLock", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PDM_LOCK calls.");
535	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/RZCallR3/PDMQueueFlush", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PDM_QUEUE_FLUSH calls.");
536	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMLock, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMLock", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_LOCK calls.");
537	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMPoolGrow", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_POOL_GROW calls.");
538	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMMapChunk, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMMapChunk", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_MAP_CHUNK calls.");
539	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMAllocHandy, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMAllocHandy", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES calls.");
540	#ifndef VBOX_WITH_NEW_PHYS_CODE
541	STAM_REG(pVM, &pVM->vmm.s.StatRZCallPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/RZCallR3/PGMGrowRAM", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_PGM_RAM_GROW_RANGE calls.");
542	#endif
543	STAM_REG(pVM, &pVM->vmm.s.StatRZCallRemReplay, STAMTYPE_COUNTER, "/VMM/RZCallR3/REMReplay", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS calls.");
544	STAM_REG(pVM, &pVM->vmm.s.StatRZCallLogFlush, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMMLogFlush", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_VMM_LOGGER_FLUSH calls.");
545	STAM_REG(pVM, &pVM->vmm.s.StatRZCallVMSetError, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMSetError", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_VM_SET_ERROR calls.");
546	STAM_REG(pVM, &pVM->vmm.s.StatRZCallVMSetRuntimeError, STAMTYPE_COUNTER, "/VMM/RZCallR3/VMRuntimeError", STAMUNIT_OCCURENCES, "Number of VMMCALLHOST_VM_SET_RUNTIME_ERROR calls.");
547	}
548
549
550	/**
551	* Ring-3 init finalizing.
552	*
553	* @returns VBox status code.
554	* @param pVM The VM handle.
555	*/
556	VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
557	{
558	#ifdef VBOX_STRICT_VMM_STACK
559	/*
560	* Two inaccessible pages at each sides of the stack to catch over/under-flows.
561	*/
562	memset(pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE, 0xcc, PAGE_SIZE);
563	PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE), PAGE_SIZE, 0);
564	RTMemProtect(pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
565
566	memset(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
567	PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE), PAGE_SIZE, 0);
568	RTMemProtect(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
569	#endif
570
571	/*
572	* Set page attributes to r/w for stack pages.
573	*/
574	int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbEMTStackRC, VMM_STACK_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D \| X86_PTE_RW);
575	AssertRC(rc);
576	if (VBOX_SUCCESS(rc))
577	{
578	/*
579	* Create the EMT yield timer.
580	*/
581	rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
582	if (VBOX_SUCCESS(rc))
583	rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
584	}
585
586	#ifdef VBOX_WITH_NMI
587	/*
588	* Map the host APIC into GC - This is AMD/Intel + Host OS specific!
589	*/
590	if (VBOX_SUCCESS(rc))
591	rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
592	X86_PTE_P \| X86_PTE_RW \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A \| X86_PTE_D);
593	#endif
594	return rc;
595	}
596
597
598	/**
599	* Initializes the R0 VMM.
600	*
601	* @returns VBox status code.
602	* @param pVM The VM to operate on.
603	*/
604	VMMR3DECL(int) VMMR3InitR0(PVM pVM)
605	{
606	int rc;
607
608	/*
609	* Initialize the ring-0 logger if we haven't done so yet.
610	*/
611	if ( pVM->vmm.s.pR0LoggerR3
612	&& !pVM->vmm.s.pR0LoggerR3->fCreated)
613	{
614	rc = VMMR3UpdateLoggers(pVM);
615	if (VBOX_FAILURE(rc))
616	return rc;
617	}
618
619	/*
620	* Call Ring-0 entry with init code.
621	*/
622	for (;;)
623	{
624	#ifdef NO_SUPCALLR0VMM
625	//rc = VERR_GENERAL_FAILURE;
626	rc = VINF_SUCCESS;
627	#else
628	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, VMMGetSvnRev(), NULL);
629	#endif
630	if ( pVM->vmm.s.pR0LoggerR3
631	&& pVM->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
632	RTLogFlushToLogger(&pVM->vmm.s.pR0LoggerR3->Logger, NULL);
633	if (rc != VINF_VMM_CALL_HOST)
634	break;
635	rc = vmmR3ServiceCallHostRequest(pVM);
636	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
637	break;
638	/* Resume R0 */
639	}
640
641	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
642	{
643	LogRel(("R0 init failed, rc=%Vra\n", rc));
644	if (VBOX_SUCCESS(rc))
645	rc = VERR_INTERNAL_ERROR;
646	}
647	return rc;
648	}
649
650
651	/**
652	* Initializes the RC VMM.
653	*
654	* @returns VBox status code.
655	* @param pVM The VM to operate on.
656	*/
657	VMMR3DECL(int) VMMR3InitRC(PVM pVM)
658	{
659	/* In VMX mode, there's no need to init RC. */
660	if (pVM->vmm.s.fSwitcherDisabled)
661	return VINF_SUCCESS;
662
663	/*
664	* Call VMMGCInit():
665	* -# resolve the address.
666	* -# setup stackframe and EIP to use the trampoline.
667	* -# do a generic hypervisor call.
668	*/
669	RTGCPTR32 GCPtrEP;
670	int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
671	if (VBOX_SUCCESS(rc))
672	{
673	CPUMHyperSetCtxCore(pVM, NULL);
674	CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
675	uint64_t u64TS = RTTimeProgramStartNanoTS();
676	CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
677	CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
678	CPUMPushHyper(pVM, VMMGetSvnRev()); /* Param 2: Version argument. */
679	CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
680	CPUMPushHyper(pVM, pVM->pVMRC); /* Param 0: pVM */
681	CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR32)); /* trampoline param: stacksize. */
682	CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
683	CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnCallTrampolineRC);
684
685	for (;;)
686	{
687	#ifdef NO_SUPCALLR0VMM
688	//rc = VERR_GENERAL_FAILURE;
689	rc = VINF_SUCCESS;
690	#else
691	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
692	#endif
693	#ifdef LOG_ENABLED
694	PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
695	if ( pLogger
696	&& pLogger->offScratch > 0)
697	RTLogFlushRC(NULL, pLogger);
698	#endif
699	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
700	PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
701	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
702	RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
703	#endif
704	if (rc != VINF_VMM_CALL_HOST)
705	break;
706	rc = vmmR3ServiceCallHostRequest(pVM);
707	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
708	break;
709	}
710
711	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
712	{
713	VMMR3FatalDump(pVM, rc);
714	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
715	rc = VERR_INTERNAL_ERROR;
716	}
717	AssertRC(rc);
718	}
719	return rc;
720	}
721
722
723	/**
724	* Terminate the VMM bits.
725	*
726	* @returns VINF_SUCCESS.
727	* @param pVM The VM handle.
728	*/
729	VMMR3DECL(int) VMMR3Term(PVM pVM)
730	{
731	/*
732	* Call Ring-0 entry with termination code.
733	*/
734	int rc;
735	for (;;)
736	{
737	#ifdef NO_SUPCALLR0VMM
738	//rc = VERR_GENERAL_FAILURE;
739	rc = VINF_SUCCESS;
740	#else
741	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_TERM, 0, NULL);
742	#endif
743	if ( pVM->vmm.s.pR0LoggerR3
744	&& pVM->vmm.s.pR0LoggerR3->Logger.offScratch > 0)
745	RTLogFlushToLogger(&pVM->vmm.s.pR0LoggerR3->Logger, NULL);
746	if (rc != VINF_VMM_CALL_HOST)
747	break;
748	rc = vmmR3ServiceCallHostRequest(pVM);
749	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
750	break;
751	/* Resume R0 */
752	}
753	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
754	{
755	LogRel(("VMMR3Term: R0 term failed, rc=%Vra. (warning)\n", rc));
756	if (VBOX_SUCCESS(rc))
757	rc = VERR_INTERNAL_ERROR;
758	}
759
760	#ifdef VBOX_STRICT_VMM_STACK
761	/*
762	* Make the two stack guard pages present again.
763	*/
764	RTMemProtect(pVM->vmm.s.pbEMTStackR3 - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
765	RTMemProtect(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
766	#endif
767	return rc;
768	}
769
770
771	/**
772	* Applies relocations to data and code managed by this
773	* component. This function will be called at init and
774	* whenever the VMM need to relocate it self inside the GC.
775	*
776	* The VMM will need to apply relocations to the core code.
777	*
778	* @param pVM The VM handle.
779	* @param offDelta The relocation delta.
780	*/
781	VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
782	{
783	LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
784
785	/*
786	* Recalc the RC address.
787	*/
788	pVM->vmm.s.pvCoreCodeRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pvCoreCodeR3);
789
790	/*
791	* The stack.
792	*/
793	CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
794	pVM->vmm.s.pbEMTStackRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pbEMTStackR3);
795	pVM->vmm.s.pbEMTStackBottomRC = pVM->vmm.s.pbEMTStackRC + VMM_STACK_SIZE;
796
797	/*
798	* All the switchers.
799	*/
800	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
801	{
802	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
803	if (pSwitcher && pSwitcher->pfnRelocate)
804	{
805	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
806	pSwitcher->pfnRelocate(pVM,
807	pSwitcher,
808	pVM->vmm.s.pvCoreCodeR0 + off,
809	(uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
810	pVM->vmm.s.pvCoreCodeRC + off,
811	pVM->vmm.s.HCPhysCoreCode + off);
812	}
813	}
814
815	/*
816	* Recalc the RC address for the current switcher.
817	*/
818	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
819	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
820	pVM->vmm.s.pfnGuestToHostRC = RCPtr + pSwitcher->offGCGuestToHost;
821	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offGCCallTrampoline;
822	pVM->pfnVMMGCGuestToHostAsm = RCPtr + pSwitcher->offGCGuestToHostAsm;
823	pVM->pfnVMMGCGuestToHostAsmHyperCtx = RCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
824	pVM->pfnVMMGCGuestToHostAsmGuestCtx = RCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
825
826	/*
827	* Get other RC entry points.
828	*/
829	int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMRCResumeGuest);
830	AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
831
832	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMRCResumeGuestV86);
833	AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
834
835	/*
836	* Update the logger.
837	*/
838	VMMR3UpdateLoggers(pVM);
839	}
840
841
842	/**
843	* Updates the settings for the RC and R0 loggers.
844	*
845	* @returns VBox status code.
846	* @param pVM The VM handle.
847	*/
848	VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
849	{
850	/*
851	* Simply clone the logger instance (for RC).
852	*/
853	int rc = VINF_SUCCESS;
854	RTRCPTR RCPtrLoggerFlush = 0;
855
856	if (pVM->vmm.s.pRCLoggerR3
857	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
858	\|\| pVM->vmm.s.pRCRelLoggerR3
859	#endif
860	)
861	{
862	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &RCPtrLoggerFlush);
863	AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
864	}
865
866	if (pVM->vmm.s.pRCLoggerR3)
867	{
868	RTRCPTR RCPtrLoggerWrapper = 0;
869	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &RCPtrLoggerWrapper);
870	AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
871
872	pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
873	rc = RTLogCloneRC(NULL /* default */, pVM->vmm.s.pRCLoggerR3, pVM->vmm.s.cbRCLogger,
874	RCPtrLoggerWrapper, RCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
875	AssertReleaseMsgRC(rc, ("RTLogCloneRC failed! rc=%Vra\n", rc));
876	}
877
878	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
879	if (pVM->vmm.s.pRCRelLoggerR3)
880	{
881	RTRCPTR RCPtrLoggerWrapper = 0;
882	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &RCPtrLoggerWrapper);
883	AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
884
885	pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
886	rc = RTLogCloneRC(RTLogRelDefaultInstance(), pVM->vmm.s.pRCRelLoggerR3, pVM->vmm.s.cbRCRelLogger,
887	RCPtrLoggerWrapper, RCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
888	AssertReleaseMsgRC(rc, ("RTLogCloneRC failed! rc=%Vra\n", rc));
889	}
890	#endif /* VBOX_WITH_RC_RELEASE_LOGGING */
891
892	/*
893	* For the ring-0 EMT logger, we use a per-thread logger instance
894	* in ring-0. Only initialize it once.
895	*/
896	PVMMR0LOGGER pR0LoggerR3 = pVM->vmm.s.pR0LoggerR3;
897	if (pR0LoggerR3)
898	{
899	if (!pR0LoggerR3->fCreated)
900	{
901	RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
902	rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
903	AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
904
905	RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
906	rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
907	AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
908
909	rc = RTLogCreateForR0(&pR0LoggerR3->Logger, pR0LoggerR3->cbLogger,
910	(PFNRTLOGGER )&pfnLoggerWrapper, (PFNRTLOGFLUSH )&pfnLoggerFlush,
911	RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
912	AssertReleaseMsgRCReturn(rc, ("RTLogCreateForR0 failed! rc=%Vra\n", rc), rc);
913	pR0LoggerR3->fCreated = true;
914	}
915
916	rc = RTLogCopyGroupsAndFlags(&pR0LoggerR3->Logger, NULL /* default */, pVM->vmm.s.pRCLoggerR3->fFlags, RTLOGFLAGS_BUFFERED);
917	AssertRC(rc);
918	}
919
920	return rc;
921	}
922
923
924	/**
925	* Generic switch code relocator.
926	*
927	* @param pVM The VM handle.
928	* @param pSwitcher The switcher definition.
929	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
930	* @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
931	* @param GCPtrCode The guest context address corresponding to pu8Code.
932	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
933	* @param SelCS The hypervisor CS selector.
934	* @param SelDS The hypervisor DS selector.
935	* @param SelTSS The hypervisor TSS selector.
936	* @param GCPtrGDT The GC address of the hypervisor GDT.
937	* @param SelCS64 The 64-bit mode hypervisor CS selector.
938	*/
939	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
940	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
941	{
942	union
943	{
944	const uint8_t *pu8;
945	const uint16_t *pu16;
946	const uint32_t *pu32;
947	const uint64_t *pu64;
948	const void *pv;
949	uintptr_t u;
950	} u;
951	u.pv = pSwitcher->pvFixups;
952
953	/*
954	* Process fixups.
955	*/
956	uint8_t u8;
957	while ((u8 = *u.pu8++) != FIX_THE_END)
958	{
959	/*
960	* Get the source (where to write the fixup).
961	*/
962	uint32_t offSrc = *u.pu32++;
963	Assert(offSrc < pSwitcher->cbCode);
964	union
965	{
966	uint8_t *pu8;
967	uint16_t *pu16;
968	uint32_t *pu32;
969	uint64_t *pu64;
970	uintptr_t u;
971	} uSrc;
972	uSrc.pu8 = pu8CodeR3 + offSrc;
973
974	/* The fixup target and method depends on the type. */
975	switch (u8)
976	{
977	/*
978	* 32-bit relative, source in HC and target in GC.
979	*/
980	case FIX_HC_2_GC_NEAR_REL:
981	{
982	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
983	uint32_t offTrg = *u.pu32++;
984	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
985	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
986	break;
987	}
988
989	/*
990	* 32-bit relative, source in HC and target in ID.
991	*/
992	case FIX_HC_2_ID_NEAR_REL:
993	{
994	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
995	uint32_t offTrg = *u.pu32++;
996	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
997	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
998	break;
999	}
1000
1001	/*
1002	* 32-bit relative, source in GC and target in HC.
1003	*/
1004	case FIX_GC_2_HC_NEAR_REL:
1005	{
1006	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1007	uint32_t offTrg = *u.pu32++;
1008	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1009	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
1010	break;
1011	}
1012
1013	/*
1014	* 32-bit relative, source in GC and target in ID.
1015	*/
1016	case FIX_GC_2_ID_NEAR_REL:
1017	{
1018	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1019	uint32_t offTrg = *u.pu32++;
1020	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1021	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1022	break;
1023	}
1024
1025	/*
1026	* 32-bit relative, source in ID and target in HC.
1027	*/
1028	case FIX_ID_2_HC_NEAR_REL:
1029	{
1030	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1031	uint32_t offTrg = *u.pu32++;
1032	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1033	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
1034	break;
1035	}
1036
1037	/*
1038	* 32-bit relative, source in ID and target in HC.
1039	*/
1040	case FIX_ID_2_GC_NEAR_REL:
1041	{
1042	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1043	uint32_t offTrg = *u.pu32++;
1044	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1045	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1046	break;
1047	}
1048
1049	/*
1050	* 16:32 far jump, target in GC.
1051	*/
1052	case FIX_GC_FAR32:
1053	{
1054	uint32_t offTrg = *u.pu32++;
1055	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1056	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1057	*uSrc.pu16++ = SelCS;
1058	break;
1059	}
1060
1061	/*
1062	* Make 32-bit GC pointer given CPUM offset.
1063	*/
1064	case FIX_GC_CPUM_OFF:
1065	{
1066	uint32_t offCPUM = *u.pu32++;
1067	Assert(offCPUM < sizeof(pVM->cpum));
1068	*uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1069	break;
1070	}
1071
1072	/*
1073	* Make 32-bit GC pointer given VM offset.
1074	*/
1075	case FIX_GC_VM_OFF:
1076	{
1077	uint32_t offVM = *u.pu32++;
1078	Assert(offVM < sizeof(VM));
1079	*uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1080	break;
1081	}
1082
1083	/*
1084	* Make 32-bit HC pointer given CPUM offset.
1085	*/
1086	case FIX_HC_CPUM_OFF:
1087	{
1088	uint32_t offCPUM = *u.pu32++;
1089	Assert(offCPUM < sizeof(pVM->cpum));
1090	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1091	break;
1092	}
1093
1094	/*
1095	* Make 32-bit R0 pointer given VM offset.
1096	*/
1097	case FIX_HC_VM_OFF:
1098	{
1099	uint32_t offVM = *u.pu32++;
1100	Assert(offVM < sizeof(VM));
1101	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1102	break;
1103	}
1104
1105	/*
1106	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1107	*/
1108	case FIX_INTER_32BIT_CR3:
1109	{
1110
1111	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1112	break;
1113	}
1114
1115	/*
1116	* Store the PAE CR3 (32-bit) for the intermediate memory context.
1117	*/
1118	case FIX_INTER_PAE_CR3:
1119	{
1120
1121	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1122	break;
1123	}
1124
1125	/*
1126	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1127	*/
1128	case FIX_INTER_AMD64_CR3:
1129	{
1130
1131	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1132	break;
1133	}
1134
1135	/*
1136	* Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1137	*/
1138	case FIX_HYPER_32BIT_CR3:
1139	{
1140
1141	*uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1142	break;
1143	}
1144
1145	/*
1146	* Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1147	*/
1148	case FIX_HYPER_PAE_CR3:
1149	{
1150
1151	*uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1152	break;
1153	}
1154
1155	/*
1156	* Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1157	*/
1158	case FIX_HYPER_AMD64_CR3:
1159	{
1160
1161	*uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1162	break;
1163	}
1164
1165	/*
1166	* Store Hypervisor CS (16-bit).
1167	*/
1168	case FIX_HYPER_CS:
1169	{
1170	*uSrc.pu16 = SelCS;
1171	break;
1172	}
1173
1174	/*
1175	* Store Hypervisor DS (16-bit).
1176	*/
1177	case FIX_HYPER_DS:
1178	{
1179	*uSrc.pu16 = SelDS;
1180	break;
1181	}
1182
1183	/*
1184	* Store Hypervisor TSS (16-bit).
1185	*/
1186	case FIX_HYPER_TSS:
1187	{
1188	*uSrc.pu16 = SelTSS;
1189	break;
1190	}
1191
1192	/*
1193	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1194	*/
1195	case FIX_GC_TSS_GDTE_DW2:
1196	{
1197	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1198	*uSrc.pu32 = (uint32_t)GCPtr;
1199	break;
1200	}
1201
1202
1203	///@todo case FIX_CR4_MASK:
1204	///@todo case FIX_CR4_OSFSXR:
1205
1206	/*
1207	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1208	*/
1209	case FIX_NO_FXSAVE_JMP:
1210	{
1211	uint32_t offTrg = *u.pu32++;
1212	Assert(offTrg < pSwitcher->cbCode);
1213	if (!CPUMSupportsFXSR(pVM))
1214	{
1215	uSrc.pu8++ = 0xe9; / jmp rel32 */
1216	*uSrc.pu32++ = offTrg - (offSrc + 5);
1217	}
1218	else
1219	{
1220	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1221	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1222	}
1223	break;
1224	}
1225
1226	/*
1227	* Insert relative jump to specified target it SYSENTER isn't used by the host.
1228	*/
1229	case FIX_NO_SYSENTER_JMP:
1230	{
1231	uint32_t offTrg = *u.pu32++;
1232	Assert(offTrg < pSwitcher->cbCode);
1233	if (!CPUMIsHostUsingSysEnter(pVM))
1234	{
1235	uSrc.pu8++ = 0xe9; / jmp rel32 */
1236	*uSrc.pu32++ = offTrg - (offSrc + 5);
1237	}
1238	else
1239	{
1240	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1241	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1242	}
1243	break;
1244	}
1245
1246	/*
1247	* Insert relative jump to specified target it SYSENTER isn't used by the host.
1248	*/
1249	case FIX_NO_SYSCALL_JMP:
1250	{
1251	uint32_t offTrg = *u.pu32++;
1252	Assert(offTrg < pSwitcher->cbCode);
1253	if (!CPUMIsHostUsingSysEnter(pVM))
1254	{
1255	uSrc.pu8++ = 0xe9; / jmp rel32 */
1256	*uSrc.pu32++ = offTrg - (offSrc + 5);
1257	}
1258	else
1259	{
1260	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1261	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1262	}
1263	break;
1264	}
1265
1266	/*
1267	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1268	*/
1269	case FIX_HC_32BIT:
1270	{
1271	uint32_t offTrg = *u.pu32++;
1272	Assert(offSrc < pSwitcher->cbCode);
1273	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1274	*uSrc.pu32 = R0PtrCode + offTrg;
1275	break;
1276	}
1277
1278	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1279	/*
1280	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1281	*/
1282	case FIX_HC_64BIT:
1283	{
1284	uint32_t offTrg = *u.pu32++;
1285	Assert(offSrc < pSwitcher->cbCode);
1286	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1287	*uSrc.pu64 = R0PtrCode + offTrg;
1288	break;
1289	}
1290
1291	/*
1292	* 64-bit HC Code Selector (no argument).
1293	*/
1294	case FIX_HC_64BIT_CS:
1295	{
1296	Assert(offSrc < pSwitcher->cbCode);
1297	#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1298	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
1299	#else
1300	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1301	#endif
1302	break;
1303	}
1304
1305	/*
1306	* 64-bit HC pointer to the CPUM instance data (no argument).
1307	*/
1308	case FIX_HC_64BIT_CPUM:
1309	{
1310	Assert(offSrc < pSwitcher->cbCode);
1311	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1312	break;
1313	}
1314	#endif
1315
1316	/*
1317	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
1318	*/
1319	case FIX_ID_32BIT:
1320	{
1321	uint32_t offTrg = *u.pu32++;
1322	Assert(offSrc < pSwitcher->cbCode);
1323	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1324	*uSrc.pu32 = u32IDCode + offTrg;
1325	break;
1326	}
1327
1328	/*
1329	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
1330	*/
1331	case FIX_ID_64BIT:
1332	{
1333	uint32_t offTrg = *u.pu32++;
1334	Assert(offSrc < pSwitcher->cbCode);
1335	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1336	*uSrc.pu64 = u32IDCode + offTrg;
1337	break;
1338	}
1339
1340	/*
1341	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1342	*/
1343	case FIX_ID_FAR32_TO_64BIT_MODE:
1344	{
1345	uint32_t offTrg = *u.pu32++;
1346	Assert(offSrc < pSwitcher->cbCode);
1347	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1348	*uSrc.pu32++ = u32IDCode + offTrg;
1349	*uSrc.pu16 = SelCS64;
1350	AssertRelease(SelCS64);
1351	break;
1352	}
1353
1354	#ifdef VBOX_WITH_NMI
1355	/*
1356	* 32-bit address to the APIC base.
1357	*/
1358	case FIX_GC_APIC_BASE_32BIT:
1359	{
1360	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1361	break;
1362	}
1363	#endif
1364
1365	default:
1366	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1367	break;
1368	}
1369	}
1370
1371	#ifdef LOG_ENABLED
1372	/*
1373	* If Log2 is enabled disassemble the switcher code.
1374	*
1375	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1376	*/
1377	if (LogIs2Enabled())
1378	{
1379	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
1380	" R0PtrCode = %p\n"
1381	" pu8CodeR3 = %p\n"
1382	" GCPtrCode = %VGv\n"
1383	" u32IDCode = %08x\n"
1384	" pVMGC = %VGv\n"
1385	" pCPUMGC = %VGv\n"
1386	" pVMHC = %p\n"
1387	" pCPUMHC = %p\n"
1388	" GCPtrGDT = %VGv\n"
1389	" InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1390	" HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1391	" SelCS = %04x\n"
1392	" SelDS = %04x\n"
1393	" SelCS64 = %04x\n"
1394	" SelTSS = %04x\n",
1395	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1396	R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1397	VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1398	GCPtrGDT,
1399	PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1400	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1401	SelCS, SelDS, SelCS64, SelTSS);
1402
1403	uint32_t offCode = 0;
1404	while (offCode < pSwitcher->cbCode)
1405	{
1406	/*
1407	* Figure out where this is.
1408	*/
1409	const char *pszDesc = NULL;
1410	RTUINTPTR uBase;
1411	uint32_t cbCode;
1412	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1413	{
1414	pszDesc = "HCCode0";
1415	uBase = R0PtrCode;
1416	offCode = pSwitcher->offHCCode0;
1417	cbCode = pSwitcher->cbHCCode0;
1418	}
1419	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1420	{
1421	pszDesc = "HCCode1";
1422	uBase = R0PtrCode;
1423	offCode = pSwitcher->offHCCode1;
1424	cbCode = pSwitcher->cbHCCode1;
1425	}
1426	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1427	{
1428	pszDesc = "GCCode";
1429	uBase = GCPtrCode;
1430	offCode = pSwitcher->offGCCode;
1431	cbCode = pSwitcher->cbGCCode;
1432	}
1433	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1434	{
1435	pszDesc = "IDCode0";
1436	uBase = u32IDCode;
1437	offCode = pSwitcher->offIDCode0;
1438	cbCode = pSwitcher->cbIDCode0;
1439	}
1440	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1441	{
1442	pszDesc = "IDCode1";
1443	uBase = u32IDCode;
1444	offCode = pSwitcher->offIDCode1;
1445	cbCode = pSwitcher->cbIDCode1;
1446	}
1447	else
1448	{
1449	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1450	offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1451	offCode++;
1452	continue;
1453	}
1454
1455	/*
1456	* Disassemble it.
1457	*/
1458	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1459	DISCPUSTATE Cpu;
1460
1461	memset(&Cpu, 0, sizeof(Cpu));
1462	Cpu.mode = CPUMODE_32BIT;
1463	while (cbCode > 0)
1464	{
1465	/* try label it */
1466	if (pSwitcher->offR0HostToGuest == offCode)
1467	RTLogPrintf(" *R0HostToGuest:\n");
1468	if (pSwitcher->offGCGuestToHost == offCode)
1469	RTLogPrintf(" *GCGuestToHost:\n");
1470	if (pSwitcher->offGCCallTrampoline == offCode)
1471	RTLogPrintf(" *GCCallTrampoline:\n");
1472	if (pSwitcher->offGCGuestToHostAsm == offCode)
1473	RTLogPrintf(" *GCGuestToHostAsm:\n");
1474	if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1475	RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1476	if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1477	RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1478
1479	/* disas */
1480	uint32_t cbInstr = 0;
1481	char szDisas[256];
1482	if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
1483	RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1484	else
1485	{
1486	RTLogPrintf(" %04x: %02x '%c'\n",
1487	offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1488	cbInstr = 1;
1489	}
1490	offCode += cbInstr;
1491	cbCode -= RT_MIN(cbInstr, cbCode);
1492	}
1493	}
1494	}
1495	#endif
1496	}
1497
1498
1499	/**
1500	* Relocator for the 32-Bit to 32-Bit world switcher.
1501	*/
1502	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1503	{
1504	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1505	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1506	}
1507
1508
1509	/**
1510	* Relocator for the 32-Bit to PAE world switcher.
1511	*/
1512	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1513	{
1514	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1515	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1516	}
1517
1518
1519	/**
1520	* Relocator for the PAE to 32-Bit world switcher.
1521	*/
1522	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1523	{
1524	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1525	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1526	}
1527
1528
1529	/**
1530	* Relocator for the PAE to PAE world switcher.
1531	*/
1532	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1533	{
1534	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1535	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1536	}
1537
1538
1539	/**
1540	* Relocator for the AMD64 to PAE world switcher.
1541	*/
1542	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1543	{
1544	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
1545	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1546	}
1547
1548
1549	/**
1550	* Gets the pointer to g_szRTAssertMsg1 in GC.
1551	* @returns Pointer to VMMGC::g_szRTAssertMsg1.
1552	* Returns NULL if not present.
1553	* @param pVM The VM handle.
1554	*/
1555	VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1556	{
1557	RTGCPTR32 GCPtr;
1558	int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1559	if (VBOX_SUCCESS(rc))
1560	return (const char *)MMHyperGC2HC(pVM, GCPtr);
1561	return NULL;
1562	}
1563
1564
1565	/**
1566	* Gets the pointer to g_szRTAssertMsg2 in GC.
1567	* @returns Pointer to VMMGC::g_szRTAssertMsg2.
1568	* Returns NULL if not present.
1569	* @param pVM The VM handle.
1570	*/
1571	VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1572	{
1573	RTGCPTR32 GCPtr;
1574	int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1575	if (VBOX_SUCCESS(rc))
1576	return (const char *)MMHyperGC2HC(pVM, GCPtr);
1577	return NULL;
1578	}
1579
1580
1581	/**
1582	* Execute state save operation.
1583	*
1584	* @returns VBox status code.
1585	* @param pVM VM Handle.
1586	* @param pSSM SSM operation handle.
1587	*/
1588	static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1589	{
1590	LogFlow(("vmmR3Save:\n"));
1591
1592	/*
1593	* The hypervisor stack.
1594	* Note! See not in vmmR3Load.
1595	*/
1596	SSMR3PutRCPtr(pSSM, pVM->vmm.s.pbEMTStackBottomRC);
1597	RTRCPTR RCPtrESP = CPUMGetHyperESP(pVM);
1598	AssertMsg(pVM->vmm.s.pbEMTStackBottomRC - RCPtrESP <= VMM_STACK_SIZE, ("Bottom %RRv ESP=%RRv\n", pVM->vmm.s.pbEMTStackBottomRC, RCPtrESP));
1599	SSMR3PutRCPtr(pSSM, RCPtrESP);
1600	SSMR3PutMem(pSSM, pVM->vmm.s.pbEMTStackR3, VMM_STACK_SIZE);
1601	return SSMR3PutU32(pSSM, ~0); /* terminator */
1602	}
1603
1604
1605	/**
1606	* Execute state load operation.
1607	*
1608	* @returns VBox status code.
1609	* @param pVM VM Handle.
1610	* @param pSSM SSM operation handle.
1611	* @param u32Version Data layout version.
1612	*/
1613	static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1614	{
1615	LogFlow(("vmmR3Load:\n"));
1616
1617	/*
1618	* Validate version.
1619	*/
1620	if (u32Version != VMM_SAVED_STATE_VERSION)
1621	{
1622	AssertMsgFailed(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1623	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1624	}
1625
1626	/*
1627	* Check that the stack is in the same place, or that it's fearly empty.
1628	*
1629	* Note! This can be skipped next time we update saved state as we will
1630	* never be in a R0/RC -> ring-3 call when saving the state. The
1631	* stack and the two associated pointers are not required.
1632	*/
1633	RTRCPTR RCPtrStackBottom;
1634	SSMR3GetRCPtr(pSSM, &RCPtrStackBottom);
1635	RTRCPTR RCPtrESP;
1636	int rc = SSMR3GetRCPtr(pSSM, &RCPtrESP);
1637	if (VBOX_FAILURE(rc))
1638	return rc;
1639
1640	/* restore the stack. */
1641	SSMR3GetMem(pSSM, pVM->vmm.s.pbEMTStackR3, VMM_STACK_SIZE);
1642
1643	/* terminator */
1644	uint32_t u32;
1645	rc = SSMR3GetU32(pSSM, &u32);
1646	if (VBOX_FAILURE(rc))
1647	return rc;
1648	if (u32 != ~0U)
1649	{
1650	AssertMsgFailed(("u32=%#x\n", u32));
1651	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1652	}
1653	return VINF_SUCCESS;
1654	}
1655
1656
1657	/**
1658	* Selects the switcher to be used for switching to GC.
1659	*
1660	* @returns VBox status code.
1661	* @param pVM VM handle.
1662	* @param enmSwitcher The new switcher.
1663	* @remark This function may be called before the VMM is initialized.
1664	*/
1665	VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1666	{
1667	/*
1668	* Validate input.
1669	*/
1670	if ( enmSwitcher < VMMSWITCHER_INVALID
1671	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1672	{
1673	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1674	return VERR_INVALID_PARAMETER;
1675	}
1676
1677	/* Do nothing if the switcher is disabled. */
1678	if (pVM->vmm.s.fSwitcherDisabled)
1679	return VINF_SUCCESS;
1680
1681	/*
1682	* Select the new switcher.
1683	*/
1684	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1685	if (pSwitcher)
1686	{
1687	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1688	pVM->vmm.s.enmSwitcher = enmSwitcher;
1689
1690	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1691	pVM->vmm.s.pfnHostToGuestR0 = pbCodeR0 + pSwitcher->offR0HostToGuest;
1692
1693	RTGCPTR GCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1694	pVM->vmm.s.pfnGuestToHostRC = GCPtr + pSwitcher->offGCGuestToHost;
1695	pVM->vmm.s.pfnCallTrampolineRC = GCPtr + pSwitcher->offGCCallTrampoline;
1696	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1697	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1698	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1699	return VINF_SUCCESS;
1700	}
1701	return VERR_NOT_IMPLEMENTED;
1702	}
1703
1704	/**
1705	* Disable the switcher logic permanently.
1706	*
1707	* @returns VBox status code.
1708	* @param pVM VM handle.
1709	*/
1710	VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1711	{
1712	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1713	* @code
1714	* mov eax, VERR_INTERNAL_ERROR
1715	* ret
1716	* @endcode
1717	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1718	*/
1719	pVM->vmm.s.fSwitcherDisabled = true;
1720	return VINF_SUCCESS;
1721	}
1722
1723
1724	/**
1725	* Resolve a builtin RC symbol.
1726	*
1727	* Called by PDM when loading or relocating RC modules.
1728	*
1729	* @returns VBox status
1730	* @param pVM VM Handle.
1731	* @param pszSymbol Symbol to resolv
1732	* @param pRCPtrValue Where to store the symbol value.
1733	*
1734	* @remark This has to work before VMMR3Relocate() is called.
1735	*/
1736	VMMR3DECL(int) VMMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
1737	{
1738	if (!strcmp(pszSymbol, "g_Logger"))
1739	{
1740	if (pVM->vmm.s.pRCLoggerR3)
1741	pVM->vmm.s.pRCLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCLoggerR3);
1742	*pRCPtrValue = pVM->vmm.s.pRCLoggerRC;
1743	}
1744	else if (!strcmp(pszSymbol, "g_RelLogger"))
1745	{
1746	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
1747	if (pVM->vmm.s.pRCRelLoggerR3)
1748	pVM->vmm.s.pRCRelLoggerRC = MMHyperR3ToRC(pVM, pVM->vmm.s.pRCRelLoggerR3);
1749	*pRCPtrValue = pVM->vmm.s.pRCRelLoggerRC;
1750	#else
1751	*pRCPtrValue = NIL_RTRCPTR;
1752	#endif
1753	}
1754	else
1755	return VERR_SYMBOL_NOT_FOUND;
1756	return VINF_SUCCESS;
1757	}
1758
1759
1760	/**
1761	* Suspends the the CPU yielder.
1762	*
1763	* @param pVM The VM handle.
1764	*/
1765	VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1766	{
1767	if (!pVM->vmm.s.cYieldResumeMillies)
1768	{
1769	uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1770	uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1771	if (u64Now >= u64Expire \|\| u64Expire == ~(uint64_t)0)
1772	pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1773	else
1774	pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1775	TMTimerStop(pVM->vmm.s.pYieldTimer);
1776	}
1777	pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1778	}
1779
1780
1781	/**
1782	* Stops the the CPU yielder.
1783	*
1784	* @param pVM The VM handle.
1785	*/
1786	VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1787	{
1788	if (!pVM->vmm.s.cYieldResumeMillies)
1789	TMTimerStop(pVM->vmm.s.pYieldTimer);
1790	pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1791	pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1792	}
1793
1794
1795	/**
1796	* Resumes the CPU yielder when it has been a suspended or stopped.
1797	*
1798	* @param pVM The VM handle.
1799	*/
1800	VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1801	{
1802	if (pVM->vmm.s.cYieldResumeMillies)
1803	{
1804	TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1805	pVM->vmm.s.cYieldResumeMillies = 0;
1806	}
1807	}
1808
1809
1810	/**
1811	* Internal timer callback function.
1812	*
1813	* @param pVM The VM.
1814	* @param pTimer The timer handle.
1815	* @param pvUser User argument specified upon timer creation.
1816	*/
1817	static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1818	{
1819	/*
1820	* This really needs some careful tuning. While we shouldn't be too gready since
1821	* that'll cause the rest of the system to stop up, we shouldn't be too nice either
1822	* because that'll cause us to stop up.
1823	*
1824	* The current logic is to use the default interval when there is no lag worth
1825	* mentioning, but when we start accumulating lag we don't bother yielding at all.
1826	*
1827	* (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1828	* so the lag is up to date.)
1829	*/
1830	const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1831	if ( u64Lag < 50000000 /* 50ms */
1832	\|\| ( u64Lag < 1000000000 /* 1s */
1833	&& RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1834	)
1835	{
1836	uint64_t u64Elapsed = RTTimeNanoTS();
1837	pVM->vmm.s.u64LastYield = u64Elapsed;
1838
1839	RTThreadYield();
1840
1841	#ifdef LOG_ENABLED
1842	u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1843	Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1844	#endif
1845	}
1846	TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1847	}
1848
1849
1850	/**
1851	* Acquire global VM lock.
1852	*
1853	* @returns VBox status code
1854	* @param pVM The VM to operate on.
1855	*
1856	* @remarks The global VMM lock isn't really used for anything any longer.
1857	*/
1858	VMMR3DECL(int) VMMR3Lock(PVM pVM)
1859	{
1860	return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1861	}
1862
1863
1864	/**
1865	* Release global VM lock.
1866	*
1867	* @returns VBox status code
1868	* @param pVM The VM to operate on.
1869	*
1870	* @remarks The global VMM lock isn't really used for anything any longer.
1871	*/
1872	VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1873	{
1874	return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1875	}
1876
1877
1878	/**
1879	* Return global VM lock owner.
1880	*
1881	* @returns Thread id of owner.
1882	* @returns NIL_RTTHREAD if no owner.
1883	* @param pVM The VM to operate on.
1884	*
1885	* @remarks The global VMM lock isn't really used for anything any longer.
1886	*/
1887	VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1888	{
1889	return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1890	}
1891
1892
1893	/**
1894	* Checks if the current thread is the owner of the global VM lock.
1895	*
1896	* @returns true if owner.
1897	* @returns false if not owner.
1898	* @param pVM The VM to operate on.
1899	*
1900	* @remarks The global VMM lock isn't really used for anything any longer.
1901	*/
1902	VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1903	{
1904	return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1905	}
1906
1907
1908	/**
1909	* Executes guest code in the raw-mode context.
1910	*
1911	* @param pVM VM handle.
1912	*/
1913	VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1914	{
1915	Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1916
1917	/*
1918	* Set the EIP and ESP.
1919	*/
1920	CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1921	? pVM->vmm.s.pfnCPUMRCResumeGuestV86
1922	: pVM->vmm.s.pfnCPUMRCResumeGuest);
1923	CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC);
1924
1925	/*
1926	* We hide log flushes (outer) and hypervisor interrupts (inner).
1927	*/
1928	for (;;)
1929	{
1930	int rc;
1931	do
1932	{
1933	#ifdef NO_SUPCALLR0VMM
1934	rc = VERR_GENERAL_FAILURE;
1935	#else
1936	rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
1937	if (RT_LIKELY(rc == VINF_SUCCESS))
1938	rc = pVM->vmm.s.iLastGZRc;
1939	#endif
1940	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1941
1942	/*
1943	* Flush the logs.
1944	*/
1945	#ifdef LOG_ENABLED
1946	PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
1947	if ( pLogger
1948	&& pLogger->offScratch > 0)
1949	RTLogFlushRC(NULL, pLogger);
1950	#endif
1951	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
1952	PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
1953	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1954	RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
1955	#endif
1956	if (rc != VINF_VMM_CALL_HOST)
1957	{
1958	Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1959	return rc;
1960	}
1961	rc = vmmR3ServiceCallHostRequest(pVM);
1962	if (VBOX_FAILURE(rc))
1963	return rc;
1964	/* Resume GC */
1965	}
1966	}
1967
1968
1969	/**
1970	* Executes guest code (Intel VT-x and AMD-V).
1971	*
1972	* @param pVM VM handle.
1973	*/
1974	VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1975	{
1976	Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1977
1978	for (;;)
1979	{
1980	int rc;
1981	do
1982	{
1983	#ifdef NO_SUPCALLR0VMM
1984	rc = VERR_GENERAL_FAILURE;
1985	#else
1986	rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN);
1987	if (RT_LIKELY(rc == VINF_SUCCESS))
1988	rc = pVM->vmm.s.iLastGZRc;
1989	#endif
1990	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1991
1992	#ifdef LOG_ENABLED
1993	/*
1994	* Flush the log
1995	*/
1996	PVMMR0LOGGER pR0LoggerR3 = pVM->vmm.s.pR0LoggerR3;
1997	if ( pR0LoggerR3
1998	&& pR0LoggerR3->Logger.offScratch > 0)
1999	RTLogFlushToLogger(&pR0LoggerR3->Logger, NULL);
2000	#endif /* !LOG_ENABLED */
2001	if (rc != VINF_VMM_CALL_HOST)
2002	{
2003	Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2004	return rc;
2005	}
2006	rc = vmmR3ServiceCallHostRequest(pVM);
2007	if (VBOX_FAILURE(rc))
2008	return rc;
2009	/* Resume R0 */
2010	}
2011	}
2012
2013	/**
2014	* Calls GC a function.
2015	*
2016	* @param pVM The VM handle.
2017	* @param GCPtrEntry The GC function address.
2018	* @param cArgs The number of arguments in the ....
2019	* @param ... Arguments to the function.
2020	*/
2021	VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, ...)
2022	{
2023	va_list args;
2024	va_start(args, cArgs);
2025	int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
2026	va_end(args);
2027	return rc;
2028	}
2029
2030
2031	/**
2032	* Calls GC a function.
2033	*
2034	* @param pVM The VM handle.
2035	* @param GCPtrEntry The GC function address.
2036	* @param cArgs The number of arguments in the ....
2037	* @param args Arguments to the function.
2038	*/
2039	VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, va_list args)
2040	{
2041	Log2(("VMMR3CallGCV: GCPtrEntry=%VRv cArgs=%d\n", GCPtrEntry, cArgs));
2042
2043	/*
2044	* Setup the call frame using the trampoline.
2045	*/
2046	CPUMHyperSetCtxCore(pVM, NULL);
2047	memset(pVM->vmm.s.pbEMTStackR3, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2048	CPUMSetHyperESP(pVM, pVM->vmm.s.pbEMTStackBottomRC - cArgs * sizeof(RTGCUINTPTR32));
2049	PRTGCUINTPTR32 pFrame = (PRTGCUINTPTR32)(pVM->vmm.s.pbEMTStackR3 + VMM_STACK_SIZE) - cArgs;
2050	int i = cArgs;
2051	while (i-- > 0)
2052	*pFrame++ = va_arg(args, RTGCUINTPTR32);
2053
2054	CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR32)); /* stack frame size */
2055	CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2056	CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnCallTrampolineRC);
2057
2058	/*
2059	* We hide log flushes (outer) and hypervisor interrupts (inner).
2060	*/
2061	for (;;)
2062	{
2063	int rc;
2064	do
2065	{
2066	#ifdef NO_SUPCALLR0VMM
2067	rc = VERR_GENERAL_FAILURE;
2068	#else
2069	rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2070	if (RT_LIKELY(rc == VINF_SUCCESS))
2071	rc = pVM->vmm.s.iLastGZRc;
2072	#endif
2073	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2074
2075	/*
2076	* Flush the logs.
2077	*/
2078	#ifdef LOG_ENABLED
2079	PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
2080	if ( pLogger
2081	&& pLogger->offScratch > 0)
2082	RTLogFlushRC(NULL, pLogger);
2083	#endif
2084	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
2085	PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
2086	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2087	RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
2088	#endif
2089	if (rc == VERR_TRPM_PANIC \|\| rc == VERR_TRPM_DONT_PANIC)
2090	VMMR3FatalDump(pVM, rc);
2091	if (rc != VINF_VMM_CALL_HOST)
2092	{
2093	Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2094	return rc;
2095	}
2096	rc = vmmR3ServiceCallHostRequest(pVM);
2097	if (VBOX_FAILURE(rc))
2098	return rc;
2099	}
2100	}
2101
2102
2103	/**
2104	* Resumes executing hypervisor code when interrupted by a queue flush or a
2105	* debug event.
2106	*
2107	* @returns VBox status code.
2108	* @param pVM VM handle.
2109	*/
2110	VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2111	{
2112	Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2113
2114	/*
2115	* We hide log flushes (outer) and hypervisor interrupts (inner).
2116	*/
2117	for (;;)
2118	{
2119	int rc;
2120	do
2121	{
2122	#ifdef NO_SUPCALLR0VMM
2123	rc = VERR_GENERAL_FAILURE;
2124	#else
2125	rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2126	if (RT_LIKELY(rc == VINF_SUCCESS))
2127	rc = pVM->vmm.s.iLastGZRc;
2128	#endif
2129	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2130
2131	/*
2132	* Flush the loggers,
2133	*/
2134	#ifdef LOG_ENABLED
2135	PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
2136	if ( pLogger
2137	&& pLogger->offScratch > 0)
2138	RTLogFlushRC(NULL, pLogger);
2139	#endif
2140	#ifdef VBOX_WITH_RC_RELEASE_LOGGING
2141	PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
2142	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2143	RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
2144	#endif
2145	if (rc == VERR_TRPM_PANIC \|\| rc == VERR_TRPM_DONT_PANIC)
2146	VMMR3FatalDump(pVM, rc);
2147	if (rc != VINF_VMM_CALL_HOST)
2148	{
2149	Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2150	return rc;
2151	}
2152	rc = vmmR3ServiceCallHostRequest(pVM);
2153	if (VBOX_FAILURE(rc))
2154	return rc;
2155	}
2156	}
2157
2158
2159	/**
2160	* Service a call to the ring-3 host code.
2161	*
2162	* @returns VBox status code.
2163	* @param pVM VM handle.
2164	* @remark Careful with critsects.
2165	*/
2166	static int vmmR3ServiceCallHostRequest(PVM pVM)
2167	{
2168	switch (pVM->vmm.s.enmCallHostOperation)
2169	{
2170	/*
2171	* Acquire the PDM lock.
2172	*/
2173	case VMMCALLHOST_PDM_LOCK:
2174	{
2175	pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2176	break;
2177	}
2178
2179	/*
2180	* Flush a PDM queue.
2181	*/
2182	case VMMCALLHOST_PDM_QUEUE_FLUSH:
2183	{
2184	PDMR3QueueFlushWorker(pVM, NULL);
2185	pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2186	break;
2187	}
2188
2189	/*
2190	* Grow the PGM pool.
2191	*/
2192	case VMMCALLHOST_PGM_POOL_GROW:
2193	{
2194	pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2195	break;
2196	}
2197
2198	/*
2199	* Maps an page allocation chunk into ring-3 so ring-0 can use it.
2200	*/
2201	case VMMCALLHOST_PGM_MAP_CHUNK:
2202	{
2203	pVM->vmm.s.rcCallHost = PGMR3PhysChunkMap(pVM, pVM->vmm.s.u64CallHostArg);
2204	break;
2205	}
2206
2207	/*
2208	* Allocates more handy pages.
2209	*/
2210	case VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES:
2211	{
2212	pVM->vmm.s.rcCallHost = PGMR3PhysAllocateHandyPages(pVM);
2213	break;
2214	}
2215	#ifndef VBOX_WITH_NEW_PHYS_CODE
2216
2217	case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2218	{
2219	const RTGCPHYS GCPhys = pVM->vmm.s.u64CallHostArg;
2220	pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, &GCPhys);
2221	break;
2222	}
2223	#endif
2224
2225	/*
2226	* Acquire the PGM lock.
2227	*/
2228	case VMMCALLHOST_PGM_LOCK:
2229	{
2230	pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2231	break;
2232	}
2233
2234	/*
2235	* Flush REM handler notifications.
2236	*/
2237	case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2238	{
2239	REMR3ReplayHandlerNotifications(pVM);
2240	break;
2241	}
2242
2243	/*
2244	* This is a noop. We just take this route to avoid unnecessary
2245	* tests in the loops.
2246	*/
2247	case VMMCALLHOST_VMM_LOGGER_FLUSH:
2248	break;
2249
2250	/*
2251	* Set the VM error message.
2252	*/
2253	case VMMCALLHOST_VM_SET_ERROR:
2254	VMR3SetErrorWorker(pVM);
2255	break;
2256
2257	/*
2258	* Set the VM runtime error message.
2259	*/
2260	case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2261	VMR3SetRuntimeErrorWorker(pVM);
2262	break;
2263
2264	/*
2265	* Signal a ring 0 hypervisor assertion.
2266	* Cancel the longjmp operation that's in progress.
2267	*/
2268	case VMMCALLHOST_VM_R0_ASSERTION:
2269	pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2270	pVM->vmm.s.CallHostR0JmpBuf.fInRing3Call = false;
2271	#ifdef RT_ARCH_X86
2272	pVM->vmm.s.CallHostR0JmpBuf.eip = 0;
2273	#else
2274	pVM->vmm.s.CallHostR0JmpBuf.rip = 0;
2275	#endif
2276	LogRel((pVM->vmm.s.szRing0AssertMsg1));
2277	LogRel((pVM->vmm.s.szRing0AssertMsg2));
2278	return VERR_VMM_RING0_ASSERTION;
2279
2280	default:
2281	AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2282	return VERR_INTERNAL_ERROR;
2283	}
2284
2285	pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2286	return VINF_SUCCESS;
2287	}
2288
2289
2290	/**
2291	* Displays the Force action Flags.
2292	*
2293	* @param pVM The VM handle.
2294	* @param pHlp The output helpers.
2295	* @param pszArgs The additional arguments (ignored).
2296	*/
2297	static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2298	{
2299	const uint32_t fForcedActions = pVM->fForcedActions;
2300
2301	pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2302
2303	/* show the flag mnemonics */
2304	int c = 0;
2305	uint32_t f = fForcedActions;
2306	#define PRINT_FLAG(flag) do { \
2307	if (f & (flag)) \
2308	{ \
2309	static const char *s_psz = #flag; \
2310	if (!(c % 6)) \
2311	pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2312	else \
2313	pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2314	c++; \
2315	f &= ~(flag); \
2316	} \
2317	} while (0)
2318	PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2319	PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2320	PRINT_FLAG(VM_FF_TIMER);
2321	PRINT_FLAG(VM_FF_PDM_QUEUES);
2322	PRINT_FLAG(VM_FF_PDM_DMA);
2323	PRINT_FLAG(VM_FF_PDM_CRITSECT);
2324	PRINT_FLAG(VM_FF_DBGF);
2325	PRINT_FLAG(VM_FF_REQUEST);
2326	PRINT_FLAG(VM_FF_TERMINATE);
2327	PRINT_FLAG(VM_FF_RESET);
2328	PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2329	PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2330	PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2331	PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2332	PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2333	PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2334	PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2335	PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2336	PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2337	PRINT_FLAG(VM_FF_TO_R3);
2338	PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2339	if (f)
2340	pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2341	else
2342	pHlp->pfnPrintf(pHlp, "\n");
2343	#undef PRINT_FLAG
2344
2345	/* the groups */
2346	c = 0;
2347	#define PRINT_GROUP(grp) do { \
2348	if (fForcedActions & (grp)) \
2349	{ \
2350	static const char *s_psz = #grp; \
2351	if (!(c % 5)) \
2352	pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2353	else \
2354	pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2355	c++; \
2356	} \
2357	} while (0)
2358	PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2359	PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2360	PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2361	PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2362	PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2363	PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2364	PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2365	PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2366	PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2367	if (c)
2368	pHlp->pfnPrintf(pHlp, "\n");
2369	#undef PRINT_GROUP
2370	}
2371

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source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 13717

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